ST ST7LITE30F2, ST7LITE35F2, ST7LITE39F2 User Manual

Download

ST7LITE3xF2

8-bit MCU with single voltage Flash, data EEPROM, ADC, timers,

SPI, LINSCI

Features

■ Memories

– 8 Kbytes program memory: single voltage ex-

tended Flash (XFlash) Program memory with read-out protection, In-Circuit Programming and In-Application programming (ICP and

IAP), data retention: 20 years at 55°C. – 384 bytes RAM – 256 bytes data EEPROM with read-out pro-

tection. 300K write/erase cycles guaranteed,

data retention: 20 years at 55°C.

■ Clock, Reset and Supply Management

– Enhanced reset system – Enhanced low voltage supervisor (LVD) for

main supply and an auxiliary voltage detector

(AVD) with interrupt capability for implement-

ing safe power-down procedures – Clock sources: Internal RC 1% oscillator,

crystal/ceramic resonator or external clock – Optional x4 or x8 PLL for 4 or 8 MHz internal

clock – Five Power Saving Modes: Halt, Active-Halt,

Wait and Slow, Auto Wake Up From Halt

■ I/O Ports

– Up to 15 multifunctional bidirectional I/O lines –7 high sink outputs

■ 5 Timers

– Configurable Watchdog Timer – Two 8-bit Lite Timers with prescaler,

1 realtime base and 1 input capture – Two 12-bit Auto-reload Timers with 4 PWM

outputs, input capture and output compare

functions

DIP20

■ 2 Communication Interfaces

– Master/slave LINSCI™ asynchronous serial

interface

– SPI synchronous serial interface

■ Interrupt Management

– 10 interrupt vectors plus TRAP and RESET – 12 external interrupt lines (on 4 vectors)

■ A/D Converter

– 7 input channels – 10-bit resolution

■ Instruction Set

8-bit data manipulation

– 63 basic instructions with illegal opcode

detection – 17 main addressing modes – 8 x 8 unsigned multiply instructions

■ Development Tools

– Full hardware/software development package – DM (Debug module)

QFN20

™

SO20

Table 1. Device summary

Features ST7LITE30F2 ST7LITE35F2 ST7LITE39F2

Program memory - bytes 8K RAM (stack) - bytes 384 (128) Data EEPROM - bytes - - 256 Peripherals Lite Timer, Autoreload Timer, SPI, LINSCI, 10-bit ADC Operating Supply 2.7V to 5.5V

CPU Frequency

Operating Temperature -40°C to +125°C Packages SO20 300”, DIP20, QFN20

Up to 8Mhz

(w/ ext OSC up to 16MHz)

Up to 8Mhz (w/ ext OSC up to 16MHz

and int 1MHz RC 1% PLLx8/4MHz)

Rev. 9

November 2007 1/173

Table of Contents

ST7LITE3xF2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

3 REGISTER & MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

4 FLASH PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4.3 PROGRAMMING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4.4 ICC INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4.5 MEMORY PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

4.6 RELATED DOCUMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

4.7 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5 DATA EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5.3 MEMORY ACCESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

5.4 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5.5 ACCESS ERROR HANDLING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5.6 DATA EEPROM READ-OUT PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5.7 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

6 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

6.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

6.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

6.3 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

7 SUPPLY, RESET AND CLOCK MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

7.1 INTERNAL RC OSCILLATOR ADJUSTMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

7.2 PHASE LOCKED LOOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

7.3 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

7.4 MULTI-OSCILLATOR (MO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

7.5 RESET SEQUENCE MANAGER (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

7.6 SYSTEM INTEGRITY MANAGEMENT (SI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

8 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

8.1 NON MASKABLE SOFTWARE INTERRUPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

8.2 EXTERNAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

8.3 PERIPHERAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

9 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

9.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

9.2 SLOW MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

9.3 WAIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

9.4 HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

2/173

Table of Contents

9.5 ACTIVE-HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

9.6 AUTO WAKE UP FROM HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

10 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

10.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

10.2 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

10.3 I/O PORT IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

10.4 UNUSED I/O PINS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

10.5 LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

10.6 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

11 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

11.1 WATCHDOG TIMER (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

11.2 DUAL 12-BIT AUTORELOAD TIMER 3 (AT3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

11.3 LITE TIMER 2 (LT2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

11.4 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

11.5 LINSCI SERIAL COMMUNICATION INTERFACE (LIN MASTER/SLAVE) . . . . . . . . . . 90

11.6 10-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

12 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

12.1 ST7 ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

12.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

13 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

13.1 PARAMETER CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

13.2 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

13.3 OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

13.4 SUPPLY CURRENT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

13.5 CLOCK AND TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

13.6 MEMORY CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

13.7 EMC (ELECTROMAGNETIC COMPATIBILITY) CHARACTERISTICS . . . . . . . . . . . . 146

13.8 I/O PORT PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

13.9 CONTROL PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

13.10 COMMUNICATION INTERFACE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . 155

13.11 10-BIT ADC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

14 PACKAGE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

14.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

14.2 THERMAL CHARACTERISTICS 160

15 DEVICE CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

15.1 FLASH OPTION BYTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

15.2 DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE . . . . 163

15.3 DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

15.4 ST7 APPLICATION NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

16 KNOWN LIMITATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

16.1 CLEARING ACTIVE INTERRUPTS OUTSIDE INTERRUPT ROUTINE . . . . . . . . . . . . 169

3/173

Table of Contents

16.2 LINSCI LIMITATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

17 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

To obtain the most recent version of this datasheet,

please check at www.st.com

Please also pay special attention to the Section “KNOWN LIMITATIONS” on page 169.

4/173

1 INTRODUCTION

ST7LITE3xF2

The ST7LITE3 is a member of the ST7 microcontroller family. All ST7 devices are based on a common industry-standard 8-bit core, featuring an enhanced instruction set.

The ST7LITE3 features FLASH memory with byte-by-byte In-Circuit Programming (ICP) and InApplication Programming (IAP) capability.

Under software control, the ST7LITE3 device can be placed in WAIT, SLOW, or HALT mode, reducing power consumption when the application is in idle or standby state.

The enhanced instruction set and addressing modes of the ST7 offer both power and flexibility to software developers, enabling the design of highly

Figure 1. General Block Diagram

Int.

1% RC

CLKIN

OSC1 OSC2

RESET

Ext.

OSC

1MHz

16MHz

1MHz

PLL x 8

or PLL X4

/ 2

Internal CLOCK

LVD

POWER

SUPPLY

CONTROL

efficient and compact application code. In addition to standard 8-bit data management, all ST7 microcontrollers feature true bit manipulation, 8x8 unsigned multiplication and indirect addressing modes.

For easy reference, all parametric data are located in section 13 on page 131.

The devices feature an on-chip Debug Module (DM) to support in-circuit debugging (ICD). For a description of the DM registers, refer to the ST7 ICC Protocol Reference Manual.

12-Bit

Auto-Reload

TIMER 2

8-Bit

LITE TIMER 2

PORT A

ADDRESS AND DATA BUS

PORT B

Debug Module

ADC

PA7:0

(8 bits)

PB6:0

(7 bits)

8-BIT CORE

ALU

PROGRAM

MEMORY (8K Bytes)

RAM

(384 Bytes)

SPI

LINSCI

WDG

DATA EEPROM

( 256 Bytes)

5/173

ST7LITE3xF2

2 PIN DESCRIPTION

Figure 2. 20-Pin QFN Package Pinout

RESET

S/AIN0/PB0

SCK/AIN1/PB1

MISO/AIN2/PB2

MOSI/AIN3/PB3

CLKIN/AIN4/PB4

ei3

ei2

78 910

OSC1/CLKIN

17181920

ei0

ei1

OSC2

PA0 (HS)/LTIC

PA1 (HS)/ATIC

PA2 (HS)/ATPWM0

PA3 (HS)/ATPWM1

PA4 (HS)/ATPWM2

PA5 (HS)/ATPWM3/ICCDATA

AIN5/PB5

Figure 3. 20-Pin SO and DIP Package Pinout

V V

RESET

/AIN0/PB0

SCK/AIN1/PB1 MISO/AIN2/PB2 MOSI/AIN3/PB3

CLKIN/AIN4/PB4

AIN5/PB5

RDI/AIN6/PB6

8 9

TDO/PA7(HS)

RDI/AIN6/PB6

MCO/ICCCLKBREAK/PA6

ei3

ei0

ei2

ei1

ei2

(HS) 20mA High sink capability eix associated external interrupt vector

OSC1/CLKIN

OSC2

PA0 (HS)/LTIC

PA1 (HS)/ATIC

PA2 (HS)/ATPWM0

PA3 (HS)/ATPWM1

PA4 (HS)/ATPWM2

PA5 (HS)/ATPWM3/ICCDATA

PA6/MCO/ICCCLK/BREAK

PA7 (HS)/TDO

(HS) 20mA high sink capability eix associated external interrupt vector

6/173

ST7LITE3xF2

PIN DESCRIPTION (Cont’d)

Legend / Abbreviations for Table 2:

Type: I = input, O = output, S = supply In/Output level: C Output level: HS = 20mA high sink (on N-buffer only)

Port and control configuration:

– Input: float = floating, wpu = weak pull-up, int = interrupt, ana = analog – Output: OD = open drain, PP = push-pull

The RESET configuration of each pin is shown in bold which is valid as long as the device is in reset state.

Table 2. Device Pin Description

Pin Name

QFN20

SO20/DIP20

19 1 V

20 2 V

1 3 RESET

2 4 PB0/AIN0/SS

3 5 PB1/AIN1/SCK I/O C

7 9 PB5/AIN5 I/O C

8 10 PB6/AIN6/RDI I/O C

9 11 PA7/TDO I/O C

PB2/AIN2/ MISO

PB3/AIN3/ MOSI

PB4/AIN4/ CLKIN**

= CMOS 0.3VDD/0.7VDD with input trigger

Level Port / Control

Input Output

Type

Input

Output

float

wpu

int

S Ground

I/O C

S Main power supply

I/O C

X X Top priority non maskable interrupt (active low)

ei3

X XXXPort B1

I/O C

X XXXPort B2

X ei2 X X X Port B3

X XXXXPort B4

ei2

X XXXPort B6 ADC Analog Input 6 or LINSCI Input

HS X XXXPort A7 LINSCI Output

Main

ana

Function

(after

reset)

Alternate Function

ADC Analog Input 0 or SPI Slave Select (active low)

XXXPort B0

Caution: No negative current injection allowed on this pin. For details, refer to

section 13.2.2 on page 132

ADC Analog Input 1 or SPI Serial Clock Caution: No negative current injection allowed on this pin. For details, refer to

section 13.2.2 on page 132

ADC Analog Input 2 or SPI Master In/ Slave Out Data

ADC Analog Input 3 or SPI Master Out / Slave In Data

ADC Analog Input 4 or External clock input

XXXPort B5 ADC Analog Input 5

7/173

ST7LITE3xF2

Level Port / Control

Pin Name

QFN20

SO20/DIP20

PA6 /MCO/

10 12

11 13

12 14 PA4/ATPWM2 I/O C

13 15 PA3/ATPWM1 I/O C

14 16 PA2/ATPWM0 I/O C

15 17 PA1/ATIC I/O C

16 18 PA0/LTIC I/O C

17 19 OSC2 O Resonator oscillator inverter output

18 20 OSC1/CLKIN I

ICCCLK/ BREAK

PA5 /ATPWM3/ ICCDATA

Type

Input

I/O C

Output

HS X XXPort A5

HS X XXPort A4 Auto-Reload Timer PWM2

HS X

HS X XXPort A2 Auto-Reload Timer PWM0

HS X XXPort A1 Auto-Reload Timer Input Capture

HS X XXXPort A0 Lite Timer Input Capture

Input Output

int

wpu

float

ei1

ei0

ana

XXPort A6

XXPort A3 Auto-Reload Timer PWM1

Main

Function

(after

reset)

Main Clock Output or In Circuit Communication Clock or External BREAK

Caution: During normal operation this pin must be pulled- up, internally or externally (external pull-up of 10k mandatory in noisy environment). This is to avoid entering ICC mode unexpectedly during a reset. In the application, even if the pin is configured as output, any reset will put it back in input pull-up.

Auto-Reload Timer PWM3 or In Circuit Communication Data

Resonator oscillator inverter input or External clock input

Alternate Function

Notes:

1. It is mandatory to connect all available V

and V

pins to the supply voltage and all VSS and V

DDA

SSA

pins to ground.

2. For input with interrupt possibility “ei

” defines the associated external interrupt vector which can be as-

signed to one of the I/O pins using the EISR register. Each interrupt can be either weak pull-up or floating defined through option register OR.

8/173

3 REGISTER & MEMORY MAP

ST7LITE3xF2

As shown in Figure 4, the MCU is capable of addressing 64K bytes of memories and I/O registers.

The available memory locations consist of 128 bytes of register locations, 384 bytes of RAM, 256 bytes of data EEPROM and 8 Kbytes of user program memory. The RAM space includes up to 128 bytes for the stack from 180h to 1FFh.

The highest address bytes contain the user reset and interrupt vectors.

Figure 4. Memory Map

0080h

E000h

FBFFh FC00h

FFFFh

00FFh 0100h

017Fh

0180h

01FFh

0000h

007Fh 0080h

01FFh

0200h

0FFFh

1000h

10FFh

1100h

DFFFh

E000h

FFDFh

FFE0h

FFFFh

HW Registers

(see Table 3)

RAM

(384 Bytes)

Reserved

Data EEPROM

(256 Bytes)

Reserved

Flash Memory

(8K)

Interrupt & Reset Vectors

(see Table 6)

The Flash memory contains two sectors (see Fig-

ure 4) mapped in the upper part of the ST7 ad-

dressing space so the reset and interrupt vectors are located in Sector 0 (F000h-FFFFh).

The size of Flash Sector 0 and other device options are configurable by Option byte.

IMPORTANT: Memory locations marked as “Reserved” must never be accessed. Accessing a reseved area can have unpredictable effects on the device.

Short Addressing RAM (zero page)

16-bit Addressing

RAM

128 Bytes Stack

8K FLASH

PROGRAM MEMORY

7 Kbytes

SECTOR 1

1 Kbyte

SECTOR 0

DEE0h

DEE1h

DEE2h

DEE3h

DEE4h

see section 7.1 on page 23 and

RCCRH0

RCCRL0 RCCRH1

RCCRL1

Note 1)

1. DEE0h, DEE1h, DEE2h and DEE3h addresses are located in a reserved area but are special bytes containing also the RC calibration values which are read-accessible only in user mode. If all the EEPROM data or Flash space (including the RC calibration values locations) has been erased (after the read out protection removal), then the RC calibration values can still be obtained through these addresses.

9/173

ST7LITE3xF2

Table 3. Hardware Register Map

Address Block

0000h 0001h 0002h

0003h 0004h 0005h

0006h 0007h

0008h 0009h 000Ah 000Bh 000Ch

000Dh 000Eh 000Fh 0010h 0011h 0012h 0013h 0014h 0015h 0016h 0017h 0018h 0019h 001Ah 001Bh 001Ch 001Dh 001Eh 001Fh 0020h 0021h 0022h 0023h 0024h 0025h

Port A

Port B

LITE

TIMER 2

AUTO-

RELOAD

TIMER 3

Label

PADR PADDR PAOR

PBDR PBDDR PBOR

LTCSR2 LTARR LTCNTR LTCSR1 LTICR

ATCSR CNTR1H CNTR1L ATR1H ATR1L PWMCR PWM0CSR PWM1CSR PWM2CSR PWM3CSR DCR0H DCR0L DCR1H DCR1L DCR2H DCR2L DCR3H DCR3L ATICRH ATICRL ATCSR2 BREAKCR ATR2H ATR2L DTGR

Port A Data Register Port A Data Direction Register Port A Option Register

Port B Data Register Port B Data Direction Register Port B Option Register

Reserved area (2 bytes)

Lite Timer Control/Status Register 2 Lite Timer Auto-reload Register Lite Timer Counter Register Lite Timer Control/Status Register 1 Lite Timer Input Capture Register

Timer Control/Status Register Counter Register 1 High Counter Register 1 Low Auto-Reload Register 1 High Auto-Reload Register 1 Low PWM Output Control Register PWM 0 Control/Status Register PWM 1 Control/Status Register PWM 2 Control/Status Register PWM 3 Control/Status Register PWM 0 Duty Cycle Register High PWM 0 Duty Cycle Register Low PWM 1 Duty Cycle Register High PWM 1 Duty Cycle Register Low PWM 2 Duty Cycle Register High PWM 2 Duty Cycle Register Low PWM 3 Duty Cycle Register High PWM 3 Duty Cycle Register Low Input Capture Register High Input Capture Register Low Timer Control/Status Register 2 Break Control Register Auto-Reload Register 2 High Auto-Reload Register 2 Low Dead Time Generator Register

FFh

00h 40h

FFh

00h 00h

0Fh 00h 00h

0x00 00x0b

xxh

0x00 0000b

00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 03h 00h 00h 00h 00h

R/W R/W R/W

R/W R/W

R/W

R/W R/W Read Only R/W Read Only

R/W Read Only Read Only R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Read Only Read Only R/W R/W R/W R/W R/W

0026h to

002Dh

002Eh WDG WDGCR Watchdog Control Register 7Fh R/W

0002Fh FLASH FCSR Flash Control/Status Register 00h R/W

00030h EEPROM EECSR Data EEPROM Control/Status Register 00h R/W

10/173

Reserved area (8 bytes)

ST7LITE3xF2

Address Block

0031h 0032h 0033h

0034h 0035h 0036h

0037h ITC EICR External Interrupt Control Register 00h R/W

0038h MCC MCCSR Main Clock Control/Status Register 00h R/W

0039h 003Ah

003Bh Reserved area (1 byte)

003Ch ITC EISR External Interrupt Selection Register 00h R/W

003Dh to

003Fh

0040h 0041h 0042h 0043h 0044h 0045h 0046h 0047h

SPI

ADC

Clock and

Reset

LINSCI

(LIN Mas-

ter/Slave)

Label

SPIDR SPICR SPICSR

ADCCSR ADCDRH ADCDRL

RCCR SICSR

SCISR SCIDR SCIBRR SCICR1 SCICR2 SCICR3 SCIERPR SCIETPR

SPI Data I/O Register SPI Control Register SPI Control Status Register

A/D Control Status Register A/D Data Register High A/D control and Data Register Low

RC oscillator Control Register System Integrity Control/Status Register

Reserved area (3 bytes)

SCI Status Register SCI Data Register SCI Baud Rate Register SCI Control Register 1 SCI Control Register 2 SCI Control Register 3 SCI Extended Receive Prescaler Register SCI Extended Transmit Prescaler Register

xxh 0xh 00h

00h xxh x0h

FFh

0110 0xx0b

C0h

xxh

00xx xxxxb

xxh 00h 00h 00h 00h

R/W R/W R/W

R/W Read Only R/W

R/W R/W

Read Only R/W R/W R/W R/W R/W R/W R/W

0048h Reserved area (1 byte)

0049h 004Ah

004Bh 004Ch 004Dh

004Eh

004Fh

0050h

0051h to

007Fh

AWU

AWUPR AWUCSR

DMCR DMSR DMBK1H DMBK1L DMBK2H DMBK2L

AWU Prescaler Register AWU Control/Status Register

DM Control Register DM Status Register DM Breakpoint Register 1 High DM Breakpoint Register 1 Low DM Breakpoint Register 2 High DM Breakpoint Register 2 Low

Reserved area (47 bytes)

FFh

00h

00h 00h 00h 00h 00h 00h

R/W R/W

R/W R/W R/W R/W R/W R/W

Legend: x=undefined, R/W=read/write Notes:

1. The contents of the I/O port DR registers are readable only in output configuration. In input configuration, the values of the I/O pins are returned instead of the DR register contents.

2. The bits associated with unavailable pins must always keep their reset value.

3. For a description of the DM registers, see the ST7 ICC Reference Manual.

11/173

ST7LITE3xF2

4 FLASH PROGRAM MEMORY

4.1 Introduction

The ST7 single voltage extended Flash (XFlash) is a non-volatile memory that can be electrically erased and programmed either on a byte-by-byte basis or up to 32 bytes in parallel.

The XFlash devices can be programmed off-board (plugged in a programming tool) or on-board using In-Circuit Programming or In-Application Programming.

The array matrix organisation allows each sector to be erased and reprogrammed without affecting other sectors.

4.2 Main Features

■ ICP (In-Circuit Programming)

■ IAP (In-Application Programming)

■ ICT (In-Circuit Testing) for downloading and

executing user application test patterns in RAM

■ Sector 0 size configurable by option byte

■ Read-out and write protection

4.3 PROGRAMMING MODES

The ST7 can be programmed in three different ways:

– Insertion in a programming tool. In this mode,

FLASH sectors 0 and 1, option byte row and data EEPROM (if present) can be programmed or erased.

– In-Circuit Programming. In this mode, FLASH

sectors 0 and 1, option byte row and data EEPROM (if present) can be programmed or erased without removing the device from the application board.

– In-Application Programming. In this mode,

sector 1 and data EEPROM (if present) can be programmed or erased without removing

the device from the application board and while the application is running.

4.3.1 In-Circuit Programming (ICP)

ICP uses a protocol called ICC (In-Circuit Communication) which allows an ST7 plugged on a printed circuit board (PCB) to communicate with an external programming device connected via cable. ICP is performed in three steps:

Switch the ST7 to ICC mode (In-Circuit Communications). This is done by driving a specific signal sequence on the ICCCLK/DATA pins while the RESET pin is pulled low. When the ST7 enters ICC mode, it fetches a specific RESET vector which points to the ST7 System Memory containing the ICC protocol routine. This routine enables the ST7 to receive bytes from the ICC interface.

– Download ICP Driver code in RAM from the

ICCDATA pin

– Execute ICP Driver code in RAM to program

the FLASH memory

Depending on the ICP Driver code downloaded in RAM, FLASH memory programming can be fully customized (number of bytes to program, program locations, or selection of the serial communication interface for downloading).

4.3.2 In Application Programming (IAP)

This mode uses an IAP Driver program previously programmed in Sector 0 by the user (in ICP mode).

This mode is fully controlled by user software. This allows it to be adapted to the user application, (user-defined strategy for entering programming mode, choice of communications protocol used to fetch the data to be stored etc.) IAP mode can be used to program any memory areas except Sector 0, which is write/erase protected to allow recovery in case errors occur during the programming operation.

12/173

FLASH PROGRAM MEMORY (Cont’d)

4.4 ICC INTERFACE

ST7LITE3xF2

ICP needs a minimum of 4 and up to 6 pins to be connected to the programming tool. These pins are:

– RESET

–V

: device reset

: device power supply ground

Figure 5. Typical ICC Interface

APPLICATION POWER SUPPLY

(See Note 3)

OPTIONAL (See Note 4)

CLKIN/PB4

(See Note 5)

ST7

Notes:

1. If the ICCCLK or ICCDATA pins are only used as outputs in the application, no signal isolation is necessary. As soon as the Programming Tool is plugged to the board, even if an ICC session is not in progress, the ICCCLK and ICCDATA pins are not available for the application. If they are used as inputs by the application, isolation such as a serial resistor has to be implemented if another device forces the signal. Refer to the Programming Tool documentation for recommended resistor values.

2. During the ICP session, the programming tool must control the RESET

pin. This can lead to conflicts between the programming tool and the application reset circuit if it drives more than 5mA at high level (push pull output or pull-up resistor<1K). A schottky diode can be used to isolate the application RESET circuit in this case. When using a classical RC network with R>1K or a reset management IC with open drain output and pull-up resistor>1K, no additional components are needed. In all cases the user must ensure that no external reset is generated by the application during the ICC session.

3. The use of Pin 7 of the ICC connector depends on the Programming Tool architecture. This pin

– ICCCLK: ICC output serial clock pin – ICCDATA: ICC input serial data pin – CLKIN/PB4: main clock input for external

source

: application board power supply (option-

–V

al, see Note 3)

PROGRAMMING TOOL

ICC CONNECTOR

ICC Cable

ICC CONNECTOR

HE10 CONNECTOR TYPE

975 3

RESET

ICCCLK

246810

See Note 1 and caution

ICCDATA

APPLICATION BOARD

APPLICATION RESET SOURCE

See Note 2

APPLICATION

See Note 1

must be connected when using most ST Programming Tools (it is used to monitor the application power supply). Please refer to the Programming Tool manual.

4. Pin 9 must be connected to the PB4 pin of the ST7 when the clock is not available in the application or if the selected clock option is not programmed in the option byte. ST7 devices with multi-oscillator capability must have OSC2 grounded in this case.

5. With any programming tool, while the ICP option is disabled, the external clock must be provided on PB4.

6. In 38-pulse ICC mode, the internal RC oscillator is forced as a clock source, regardless of the selection in the option byte. For ST7LITE30 devices which do not support the internal RC oscillator, the “option byte disabled” mode must be used (35pulse ICC mode entry, clock provided by the tool). Caution: During normal operation ICCCLK pin must be pulled- up, internally or externally (external pull-up of 10k mandatory in noisy environment). This avoids entering ICC mode unexpectedly during a reset. In the application, even if the pin is configured as output, any reset puts it back in input pull-up.

I/O

13/173

ST7LITE3xF2

FLASH PROGRAM MEMORY (Cont’d)

4.5 Memory Protection

There are two different types of memory protection: Read Out Protection and Write/Erase Protection which can be applied individually.

4.5.1 Read out Protection

Readout protection, when selected provides a protection against program memory content extraction and against write access to Flash memory. Even if no protection can be considered as totally unbreakable, the feature provides a very high level of protection for a general purpose microcontroller. Both program and data E

memory are protected.

In flash devices, this protection is removed by reprogramming the option. In this case, both program and data E

memory are automatically

erased and the device can be reprogrammed. – Read-out protection selection is enabled and re-

moved through the FMP_R bit in the option byte.

4.5.2 Flash Write/Erase Protection

Write/erase protection, when set, makes it impossible to both overwrite and erase program memory. It does not apply to E

data. Its purpose is to provide advanced security to applications and prevent any change being made to the memory content.

Warning: Once set, Write/erase protection can never be removed. A write-protected flash device is no longer reprogrammable.

Write/erase protection is enabled through the FMP_W bit in the option byte.

4.6 Related Documentation

For details on Flash programming and ICC protocol, refer to the ST7 Flash Programming Reference Manual and to the ST7 ICC Protocol Reference Manual

4.7 Register Description

FLASH CONTROL/STATUS REGISTER (FCSR)

Read/Write Reset Value: 000 0000 (00h) 1st RASS Key: 0101 0110 (56h) 2nd RASS Key: 1010 1110 (AEh)

00000OPTLATPGM

Note: This register is reserved for programming using ICP, IAP or other programming methods. It controls the XFlash programming and erasing operations.

When an EPB or another programming tool is used (in socket or ICP mode), the RASS keys are sent automatically.

14/173

5 DATA EEPROM

ST7LITE3xF2

5.1 INTRODUCTION

The Electrically Erasable Programmable Read Only Memory can be used as a non volatile backup for storing data. Using the EEPROM requires a basic access protocol described in this chapter.

Figure 6. EEPROM Block Diagram

EECSR

ADDRESS DECODER

0 E2LAT00 0 0 0 E2PGM

DECODER

ROW

5.2 MAIN FEATURES

■ Up to 32 Bytes programmed in the same cycle

■ EEPROM mono-voltage (charge pump)

■ Chained erase and programming cycles

■ Internal control of the global programming cycle

duration

■ WAIT mode management

■ Readout protection

HIGH VOLTAGE

PUMP

EEPROM

MEMORY MATRIX

(1 ROW = 32 x 8 BITS)

ADDRESS BUS

128128

DATA

MULTIPLEXER

DATA BUS

32 x 8 BITS

DATA LATCHES

15/173

ST7LITE3xF2

DATA EEPROM (Cont’d)

5.3 MEMORY ACCESS

The Data EEPROM memory read/write access modes are controlled by the E2LAT bit of the EEPROM Control/Status register (EECSR). The flowchart in Figure 7 describes these different memory access modes.

Read Operation (E2LAT=0)

The EEPROM can be read as a normal ROM location when the E2LAT bit of the EECSR register is cleared.

On this device, Data EEPROM can also be used to execute machine code. Take care not to write to the Data EEPROM while executing from it. This would result in an unexpected code being executed.

Write Operation (E2LAT=1)

To access the write mode, the E2LAT bit has to be set by software (the E2PGM bit remains cleared). When a write access to the EEPROM area occurs,

Figure 7. Data EEPROM Programming Flowchart

READ MODE

E2LAT=0

E2PGM=0

the value is latched inside the 32 data latches according to its address.

When PGM bit is set by the software, all the previous bytes written in the data latches (up to 32) are programmed in the EEPROM cells. The effective high address (row) is determined by the last EEPROM write sequence. To avoid wrong programming, the user must take care that all the bytes written between two programming sequences have the same high address: only the five Least Significant Bits of the address can change.

At the end of the programming cycle, the PGM and LAT bits are cleared simultaneously.

Note: Care should be taken during the programming cycle. Writing to the same memory location will over-program the memory (logical AND between the two write access data result) because the data latches are only cleared at the end of the programming cycle and by the falling edge of the E2LAT bit. It is not possible to read the latched data. This note is ilustrated by the Figure 9.

WRITE MODE

E2LAT=1

E2PGM=0

16/173

READ BYTES

IN EEPROM AREA

CLEARED BY HARDWARE

WRITE UP TO 32 BYTES

(with the same 11 MSB of the address)

IN EEPROM AREA

START PROGRAMMING CYCLE

E2PGM=1 (set by software)

E2LAT=1

E2LAT

DATA EEPROM (Cont’d)

Figure 8. Data E

DEFINITION

PROM Write Operation

⇓ Row / Byte ⇒ 0 1 2 3 ... 30 31 Physical Address

ROW

ST7LITE3xF2

...

00h...1Fh 20h...3Fh

Nx20h...Nx20h+1Fh

E2LAT bit

E2PGM bit

Read operation impossible

Byte 1 Byte 2 Byte 32

PHASE 1

Writing data latches Waiting E2PGM and E2LAT to fall

Set by USER application

Programming cycle

PHASE 2

Read operation possible

Cleared by hardware

Note: If a programming cycle is interrupted (by a reset action), the integrity of the data in memory is not guaranteed.

17/173

ST7LITE3xF2

DATA EEPROM (Cont’d)

5.4 POWER SAVING MODES

Wait mode

The DATA EEPROM can enter WAIT mode on execution of the WFI instruction of the microcontroller or when the microcontroller enters Active-HALT mode.The DATA EEPROM will immediately enter this mode if there is no programming in progress, otherwise the DATA EEPROM will finish the cycle and then enter WAIT mode.

Active-Halt mode

Refer to Wait mode.

Halt mode

The DATA EEPROM immediately enters HALT mode if the microcontroller executes the HALT instruction. Therefore the EEPROM will stop the function in progress, and data may be corrupted.

5.5 ACCESS ERROR HANDLING

If a read access occurs while E2LAT=1, then the data bus will not be driven.

If a write access occurs while E2LAT=0, then the data on the bus will not be latched.

If a programming cycle is interrupted (by RESET action), the integrity of the data in memory is not guaranteed.

5.6 Data EEPROM Read-out Protection

The read-out protection is enabled through an option bit (see section 15.1 on page 161).

When this option is selected, the programs and data stored in the EEPROM memory are protected against read-out (including a re-write protection). In Flash devices, when this protection is removed by reprogramming the Option Byte, the entire Program memory and EEPROM is first automatically erased.

Note: Both Program Memory and data EEPROM are protected using the same option bit.

Figure 9. Data EEPROM Programming Cycle

READ OPERATION NOT POSSIBLE

INTERNAL PROGRAMMING VOLTAGE

ERASE CYCLE WRITE CYCLE

WRITE OF

DATA LATCHES

PROG

READ OPERATION POSSIBLE

LAT

PGM

18/173

DATA EEPROM (Cont’d)

5.7 REGISTER DESCRIPTION

EEPROM CONTROL/STATUS REGISTER (EECSR)

Read/Write Reset Value: 0000 0000 (00h)

000000E2LATE2PGM

Bits 7:2 = Reserved, forced by hardware to 0.

Bit 1 = E2LAT Latch Access Transfer This bit is set by software. It is cleared by hardware at the end of the programming cycle. It can only be cleared by software if the E2PGM bit is cleared. 0: Read mode 1: Write mode

ST7LITE3xF2

Bit 0 = E2PGM Programming control and status This bit is set by software to begin the programming cycle. At the end of the programming cycle, this bit is cleared by hardware. 0: Programming finished or not yet started 1: Programming cycle is in progress

Note: if the E2PGM bit is cleared during the programming cycle, the memory data is not guaranteed

Table 4. DATA EEPROM Register Map and Reset Values

Address

(Hex.)

0030h

Label

EECSR

Reset Value

76543210

000000

E2LAT0E2PGM

19/173

ST7LITE3xF2

6 CENTRAL PROCESSING UNIT

6.1 INTRODUCTION

This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8-bit data manipulation.

6.2 MAIN FEATURES

■ 63 basic instructions

■ Fast 8-bit by 8-bit multiply

■ 17 main addressing modes

■ Two 8-bit index registers

■ 16-bit stack pointer

■ Low power modes

■ Maskable hardware interrupts

■ Non-maskable software interrupt

6.3 CPU REGISTERS

The six CPU registers shown in Figure 10 are not present in the memory mapping and are accessed by specific instructions.

Figure 10. CPU Registers

RESET VALUE = XXh

Accumulator (A)

The Accumulator is an 8-bit general purpose register used to hold operands and the results of the arithmetic and logic calculations and to manipulate data.

Index Registers (X and Y)

In indexed addressing modes, these 8-bit registers are used to create either effective addresses or temporary storage areas for data manipulation. (The Cross-Assembler generates a precede instruction (PRE) to indicate that the following instruction refers to the Y register.)

The Y register is not affected by the interrupt automatic procedures (not pushed to and popped from the stack).

Program Counter (PC)

The program counter is a 16-bit register containing the address of the next instruction to be executed by the CPU. It is made of two 8-bit registers PCL (Program Counter Low which is the LSB) and PCH (Program Counter High which is the MSB).

ACCUMULATOR

X INDEX REGISTER

Y INDEX REGISTER

15 8

RESET VALUE = RESET VECTOR @ FFFEh-FFFFh

RESET VALUE = STACK HIGHER ADDRESS

20/173

PCH

RESET VALUE =

1C11HI NZ

1X11X1XX

PCL

PROGRAM COUNTER

CONDITION CODE REGISTER

STACK POINTER

X = Undefined Value

CPU REGISTERS (cont’d) CONDITION CODE REGISTER (CC)

Read/Write Reset Value: 111x1xxx

logical or data manipulation. It is a copy of the 7 bit of the result. 0: The result of the last operation is positive or null. 1: The result of the last operation is negative

(that is, the most significant bit is a logic 1).

This bit is accessed by the JRMI and JRPL instruc-

111HINZC

tions.

ST7LITE3xF2

The 8-bit Condition Code register contains the interrupt mask and four flags representative of the result of the instruction just executed. This register can also be handled by the PUSH and POP instructions.

These bits can be individually tested and/or controlled by specific instructions.

Bit 4 = H Half carry This bit is set by hardware when a carry occurs be-

tween bits 3 and 4 of the ALU during an ADD or ADC instruction. It is reset by hardware during the same instructions. 0: No half carry has occurred. 1: A half carry has occurred.

This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD arithmetic subroutines.

Bit 3 = I Interrupt mask This bit is set by hardware when entering in inter-

rupt or by software to disable all interrupts except the TRAP software interrupt. This bit is cleared by software. 0: Interrupts are enabled. 1: Interrupts are disabled.

This bit is controlled by the RIM, SIM and IRET instructions and is tested by the JRM and JRNM instructions.

Note: Interrupts requested while I is set are latched and can be processed when I is cleared. By default an interrupt routine is not interruptible because the I bit is set by hardware at the start of the routine and reset by the IRET instruction at the end of the routine. If the I bit is cleared by software in the interrupt routine, pending interrupts are serviced regardless of the priority level of the current interrupt routine.

Bit 2 = N Negative This bit is set and cleared by hardware. It is repre-

sentative of the result sign of the last arithmetic,

Bit 1 = Z Zero This bit is set and cleared by hardware. This bit in-

dicates that the result of the last arithmetic, logical or data manipulation is zero. 0: The result of the last operation is different from

zero.

1: The result of the last operation is zero. This bit is accessed by the JREQ and JRNE test

instructions.

Bit 0 = C Carry/borrow This bit is set and cleared by hardware and soft-

ware. It indicates an overflow or an underflow has occurred during the last arithmetic operation. 0: No overflow or underflow has occurred. 1: An overflow or underflow has occurred.

This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC instructions. It is also affected by the “bit test and branch”, shift and rotate instructions.

CPU REGISTERS (Cont’d) STACK POINTER (SP)

Read/Write Reset Value: 01FFh

15 8

00000001

1 SP6 SP5 SP4 SP3 SP2 SP1 SP0

The Stack Pointer is a 16-bit register which is always pointing to the next free location in the stack. It is then decremented after data has been pushed onto the stack and incremented before data is popped from the stack (see Figure 11).

Since the stack is 128 bytes deep, the 9 most significant bits are forced by hardware. Following an

21/173

ST7LITE3xF2

MCU Reset, or after a Reset Stack Pointer instruction (RSP), the Stack Pointer contains its reset value (the SP6 to SP0 bits are set) which is the stack higher address.

The least significant byte of the Stack Pointer (called S) can be directly accessed by a LD instruction.

Note: When the lower limit is exceeded, the Stack Pointer wraps around to the stack upper limit, without indicating the stack overflow. The previously stored information is then overwritten and therefore lost. The stack also wraps in case of an underflow.

The stack is used to save the return address during a subroutine call and the CPU context during an interrupt. The user may also directly manipulate the stack by means of the PUSH and POP instruc-

Figure 11. Stack Manipulation Example

@ 0180h

CALL

Subroutine

Interrupt

Event

PUSH Y POP Y IRET

tions. In the case of an interrupt, the PCL is stored at the first location pointed to by the SP. Then the other registers are stored in the next locations as shown in Figure 11.

– When an interrupt is received, the SP is decre-

mented and the context is pushed on the stack.

– On return from interrupt, the SP is incremented

and the context is popped from the stack.

A subroutine call occupies two locations and an interrupt five locations in the stack area.

RET

or RSP

@ 01FFh

X PCH PCL

PCH

PCL

Stack Higher Address = 01FFh Stack Lower Address =

PCH

PCL

0180h

X PCH PCL PCH PCL

PCH PCL

22/173

7 SUPPLY, RESET AND CLOCK MANAGEMENT

ST7LITE3xF2

The device includes a range of utility features for securing the application in critical situations (for example in case of a power brown-out), and reducing the number of external components.

Main features

■ Clock Management

– 1 MHz internal RC oscillator (enabled by op-

tion byte, available on ST7LITE35 and ST7LITE39 devices only)

– 1 to 16 MHz or 32kHz External crystal/ceramic

resonator (selected by option byte) – External Clock Input (enabled by option byte) – PLL for multiplying the frequency by 8 or 4

(enabled by option byte)

■ Reset Sequence Manager (RSM)

■ System Integrity Management (SI)

– Main supply Low voltage detection (LVD) with

reset generation (enabled by option byte) – Auxiliary Voltage detector (AVD) with interrupt

capability for monitoring the main supply (en-

abled by option byte)

7.1 INTERNAL RC OSCILLATOR ADJUSTMENT

The device contains an internal RC oscillator with an accuracy of 1% for a given device, temperature and voltage range (4.5V-5.5V). It must be calibrated to obtain the frequency required in the application. This is done by software writing a 8-bit calibration value in the RCCR (RC Control Register) and in the bits [6:5] in the SICSR (SI Control Status Register).

Whenever the microcontroller is reset, the RCCR returns to its default value (FFh), i.e. each time the device is reset, the calibration value must be loaded in the RCCR. Predefined calibration values are stored in EEPROM for 3V and 5V V ages at 25°C, as shown in the following table.

RCCR Conditions

T f

=5V

=25°C

=1MHz

=3.3V

=25°C

=1MHz

RCCRH0 V

RCCRL0 DEE1h

RCCRH1 V

RCCRL1 DEE3h

DEE0h

DEE2h

supply volt-

ST7LITE3

Addresses

(CR[9:2] bits)

(CR[1:0] bits)

(CR[9:2] bits)

(CR[1:0] bits)

1. DEE0h, DEE1h, DEE2h and DEE3h addresses are located in a reserved area of non-volatile memory. They are read-only bytes for the applica-

tion code. This area cannot be erased or programmed by any ICC operation.

For compatibility reasons with the SICSR register, CR[1:0] bits are stored in the 5th and 6th position of DEE1 and DEE3 addresses.

Note: – In 38-pulse ICC mode, the internal RC oscillator

is forced as a clock source, regardless of the selection in the option byte. For ST7LITE30 devices which do not support the internal RC oscillator, the “option byte disabled” mode must be used (35-pulse ICC mode entry, clock provided by the tool).

– See “ELECTRICAL CHARACTERISTICS” on

page 131. for more information on the frequency and accuracy of the RC oscillator.

– To improve clock stability and frequency accura-

cy, it is recommended to place a decoupling capacitor, typically 100nF, between the V

pins as close as possible to the ST7 device

and

– These bytes are systematically programmed by

ST, including on FASTROM devices. Consequently, customers intending to use FASTROM service must not use these bytes.

– RCCR0 and RCCR1 calibration values will not

be erased if the read-out protection bit is reset after it has been set . See “Read out Protection” on page 14.

Caution: If the voltage or temperature conditions change in the application, the frequency may need to be recalibrated.

Refer to application note AN1324 for information on how to calibrate the RC frequency using an external reference signal.

7.2 PHASE LOCKED LOOP

The PLL can be used to multiply a 1MHz frequency from the RC oscillator or the external clock by 4 or 8 to obtain f

of 4 or 8 MHz. The PLL is ena-

OSC

bled and the multiplication factor of 4 or 8 is selected by 2 option bits.

– The x4 PLL is intended for operation with V

the 2.7V to 3.3V range

– The x8 PLL is intended for operation with V

the 3.3V to 5.5V range

Refer to Section 15.1 for the option byte description.

If the PLL is disabled and the RC oscillator is enabled, then f

OSC =

1MHz.

23/173

ST7LITE3xF2

If both the RC oscillator and the PLL are disabled,

is driven by the external clock.

OSC

Figure 12. PLL Output Frequency Timing Diagram

LOCKED bit set

4/8 x input

freq.

STAB

LOCK

STARTUP

Output freq.

When the PLL is started, after reset or wakeup from Halt mode or AWUFH mode, it outputs the clock after a delay of t

STARTUP

When the PLL output signal reaches the operating frequency, the LOCKED bit in the SICSCR register is set. Full PLL accuracy (ACC a stabilization time of t

STAB

) is reached after

PLL

(see Figure 12 and

13.3.4Internal RC Oscillator and PLL)

Refer to section 7.6.4 on page 34 for a description of the LOCKED bit in the SICSR register.

7.3 REGISTER DESCRIPTION

MAIN CLOCK CONTROL/STATUS REGISTER (MCCSR)

Read / Write Reset Value: 0000 0000 (00h)

000000

MCO SMS

Bits 7:2 = Reserved, must be kept cleared.

Bit 1 = MCO Main Clock Out enable This bit is read/write by software and cleared by hardware after a reset. This bit allows to enable the MCO output clock. 0: MCO clock disabled, I/O port free for general

purpose I/O.

1: MCO clock enabled.

Bit 0 = SMS Slow Mode select This bit is read/write by software and cleared by hardware after a reset. This bit selects the input

OSC

or f

clock f 0: Normal mode (f 1: Slow mode (f

/32.

OSC

CPU = fOSC

/32)

RC CONTROL REGISTER (RCCR)

Read / Write Reset Value: 1111 1111 (FFh)

24/173

CR9 CR8 CR7 CR6 CR5 CR4 CR3 CR2

Bits 7:0 = CR[9:2] RC Oscillator Frequency Ad-

justment Bits

These bits must be written immediately after reset to adjust the RC oscillator frequency and to obtain an accuracy of 1%. The application can store the correct value for each voltage range in EEPROM and write it to this register at start-up. 00h = maximum available frequency FFh = lowest available frequency These bits are used with the CR[1:0] bits in the SICSR register. Refer to section 7.6.4 on page 34 Note: To tune the oscillator, write a series of different values in the register until the correct frequency is reached. The fastest method is to use a dichotomy starting with 80h.

Figure 13. Clock Management Block Diagram

ST7LITE3xF2

CLKIN

CLKIN/ OSC1

OSC2

OSCRANGE[2:0]

CLKIN

1-16 MHZ or 32kHz

OSC

Tunable

Oscillator1% RC

Option bits

DIVIDER

OSC

/32 DIVIDER

CR6CR9 CR2CR3CR4CR5CR8 CR7

CR1 CR0

1MHz

DIVIDER

PLL 1MHz -> 8MHz PLL 1MHz -> 4MHz

OSC Option bit

8-BIT

LITE TIMER 2 COUNTER

/32

OSC

RCCR

Crystal OSC /2

SICSR

CLKIN/2 (Ext Clock)

RC OSC 8MHz 4MHz

PLL

Clock

PLLx4x8

OSC,PLLOFF,

OSCRANGE[2:0]

Option bits

LTIMER

(1ms timebase @ 8 MHz f

CPU

TO CPU AND PERIPHERALS

OSC

)

MCO

SMS

MCCSR

CPU

MCO

25/173

ST7LITE3xF2

7.4 MULTI-OSCILLATOR (MO)

The main clock of the ST7 can be generated by four different source types coming from the multioscillator block (1 to 16MHz or 32kHz):

■ an external source

■ 5 crystal or ceramic resonator oscillators

■ an internal high frequency RC oscillator

Each oscillator is optimized for a given frequency range in terms of consumption and is selectable through the option byte. The associated hardware configurations are shown in Table 5. Refer to the electrical characteristics section for more details.

External Clock Source

In this external clock mode, a clock signal (square, sinus or triangle) with ~50% duty cycle has to drive the OSC1 pin while the OSC2 pin is tied to ground.

Note: when the Multi-Oscillator is not used, PB4 is selected by default as external clock.

Crystal/Ceramic Oscillators

This family of oscillators has the advantage of producing a very accurate rate on the main clock of the ST7. The selection within a list of 4 oscillators with different frequency ranges has to be done by option byte in order to reduce consumption (refer to section 15.1 on page 161 for more details on the frequency ranges). In this mode of the multi-oscillator, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and start-up stabilization time. The loading capacitance values must be adjusted according to the selected oscillator.

These oscillators are not stopped during the RESET phase to avoid losing time in the oscillator start-up phase.

Internal RC Oscillator

In this mode, the tunable 1%RC oscillator is used as main clock source. The two oscillator pins have to be tied to ground.

The calibration is done through the RCCR[7:0] and SICSR[6:5] registers.

Table 5. ST7 Clock Sources

Hardware Configuration

ST7

OSC1 OSC2

External ClockCrystal/Ceramic ResonatorsInternal RC Oscillator

EXTERNAL

SOURCE

OSC1 OSC2

CAPACITORS

OSC1 OSC2

ST7

LOAD

ST7

26/173

7.5 RESET SEQUENCE MANAGER (RSM)

ST7LITE3xF2

7.5.1 Introduction

The reset sequence manager includes three RESET sources as shown in Figure 15:

■ External RESET source pulse

■ Internal LVD RESET (Low Voltage Detection)

■ Internal WATCHDOG RESET

Note: A reset can also be triggered following the detection of an illegal opcode or prebyte code. Refer to section 12.2.1 on page 128 for further details.

These sources act on the RESET

pin and it is al-

ways kept low during the delay phase. The RESET service routine vector is fixed at ad-

dresses FFFEh-FFFFh in the ST7 memory map. The basic RESET sequence consists of 3 phases

as shown in Figure 14:

■ Active Phase depending on the RESET source

■ 256 or 4096 CPU clock cycle delay (see table

below)

■ RESET vector fetch

Caution: When the ST7 is unprogrammed or fully erased, the Flash is blank and the RESET vector is not programmed. For this reason, it is recommended to keep the RESET pin in low state until programming mode is entered, in order to avoid unwanted behavior.

The 256 or 4096 CPU clock cycle delay allows the oscillator to stabilise and ensures that recovery has taken place from the Reset state. The shorter or longer clock cycle delay is automatically selected depending on the clock source chosen by option byte:

The RESET vector fetch phase duration is 2 clock cycles.

Clock Source

Internal RC Oscillator 256 External clock (connected to CLKIN pin) 256 External Crystal/Ceramic Oscillator

(connected to OSC1/OSC2 pins)

CPU clock

cycle delay

4096

If the PLL is enabled by option byte, it outputs the clock after an additional delay of t

STARTUP

(see

Figure 12).

Figure 14. RESET Sequence Phases

RESET

Active Phase

INTERNAL RESET

256 or 4096 CLOCK CYCLES

7.5.2 Asynchronous External RESET

The RESET output with integrated R

pin is both an input and an open-drain

weak pull-up resistor.

FETCH

VECTOR

This pull-up has no fixed value but varies in accordance with the input voltage. It

can be pulled low by external circuitry to reset the device. See Electrical Characteristic section for more details.

A RESET signal originating from an external source must have a duration of at least t

h(RSTL)in

in order to be recognized (see Figure 16). This detection is asynchronous and therefore the MCU can enter reset state even in HALT mode.

27/173

ST7LITE3xF2

Figure 15. Reset Block Diagram

RESET

Filter

PULSE

GENERATOR

WATCHDOG RESET ILLEGAL OPCODE RESET LVD RESET

INTERNAL RESET

Note 1: See “Illegal Opcode Reset” on page 128. for more details on illegal opcode reset conditions.

28/173

RESET SEQUENCE MANAGER (Cont’d) The RESET

pin is an asynchronous signal which plays a major role in EMS performance. In a noisy environment, it is recommended to follow the guidelines mentioned in the electrical characteristics section.

7.5.3 External Power-On RESET

If the LVD is disabled by option byte, to start up the microcontroller correctly, the user must ensure by means of an external reset circuit that the reset signal is held low until V level specified for the selected f

A proper reset signal for a slow rising V

is over the minimum

frequency.

OSC

supply

can generally be provided by an external RC network connected to the RESET

pin.

Figure 16. RESET Sequences

ST7LITE3xF2

7.5.4 Internal Low Voltage Detector (LVD) RESET

Two different RESET sequences caused by the internal LVD circuitry can be distinguished:

■ Power-On RESET

■ Voltage Drop RESET

The device RESET pulled low when V V

DD<VIT-

(falling edge) as shown in Figure 16.

The LVD filters spikes on V avoid parasitic resets.

7.5.5 Internal Watchdog RESET

The RESET sequence generated by a internal Watchdog counter overflow is shown in Figure 16.

Starting from the Watchdog counter underflow, the device RESET low during at least t

pin acts as an output that is

DD<VIT+

(rising edge) or

larger than t

g(VDD)

pin acts as an output that is pulled

w(RSTL)out

IT+(LVD)

IT-(LVD)

EXTERNAL RESET SOURCE

RESET PIN

WATCHDOG RESET

RUN

LVD

RESET

ACTIVE PHASE

RUN

h(RSTL)in

EXTERNAL

RESET

ACTIVE PHASE

WATCHDOG UNDERFLOW

RUN RUN

INTERNAL RESET (256 or 4096 T VECTOR FETCH

WATCHDOG

RESET

ACTIVE

PHASE

w(RSTL)out

CPU

)

29/173

ST7LITE3xF2

7.6 SYSTEM INTEGRITY MANAGEMENT (SI)

The System Integrity Management block contains the Low voltage Detector (LVD) and Auxiliary Voltage Detector (AVD) functions. It is managed by the SICSR register.

Note: A reset can also be triggered following the detection of an illegal opcode or prebyte code. Refer to section 12.2.1 on page 128 for further details.

7.6.1 Low Voltage Detector (LVD)

The Low Voltage Detector function (LVD) generates a static reset when the V below a V

IT-(LVD)

reference value. This means that

supply voltage is

it secures the power-up as well as the power-down keeping the ST7 in reset.

The V

IT-(LVD)

lower than the V

reference value for a voltage drop is

IT+(LVD)

reference value for poweron in order to avoid a parasitic reset when the MCU starts running and sinks current on the supply (hysteresis).

The LVD Reset circuitry generates a reset when

is below:

–V –V

IT+(LVD)

IT-(LVD)

when VDD is rising

when VDD is falling The LVD function is illustrated in Figure 17. The voltage threshold can be configured by option

byte to be low, medium or high.

Provided the minimum V the oscillator frequency) is above V

value (guaranteed for

IT-(LVD)

, the

MCU can only be in two modes:

– under full software control – in static safe reset

In these conditions, secure operation is always ensured for the application without the need for external reset hardware.

During a Low Voltage Detector Reset, the RESET pin is held low, thus permitting the MCU to reset other devices.

Notes: The LVD allows the device to be used without any

external RESET circuitry. Use of LVD with capacitive power supply: with this

type of power supply, if power cuts occur in the application, it is recommended to pull V

down to

0V to ensure optimum restart conditions. Refer to circuit example in Figure 99 on page 154 and note

4. The LVD is an optional function which can be se-

lected by option byte. It is recommended to make sure that the V

supply voltage rises monotonously when the device is exiting from Reset, to ensure the application functions properly.

Figure 17. Low Voltage Detector vs Reset

IT+

(LVD)

IT-

(LVD)

RESET

30/173

hys

Figure 18. Reset and Supply Management Block Diagram

ST7LITE3xF2

RESET

RESET SEQUENCE

MANAGER

(RSM)

WATCHDOG

TIMER (WDG)

STATUS FLAG

SYSTEM INTEGRITY MANAGEMENT

SICSR

LOW VOLTAGE

AUXILIARY VOLTAGE

LVDRFLOCKEDWDGRF

DETECTOR

(LVD)

DETECTOR

(AVD)

AVD Interrupt Request

AVDIEAVDF

31/173

ST7LITE3xF2

SYSTEM INTEGRITY MANAGEMENT (Cont’d)

7.6.2 Auxiliary Voltage Detector (AVD)

The Voltage Detector function (AVD) is based on an analog comparison between a V V

IT+(AVD)

ply voltage (V

reference value and the VDD main sup-

). The V

AVD

IT-(AVD)

for falling voltage is lower than the V

IT-(AVD)

reference value

IT+(AVD)

ence value for rising voltage in order to avoid parasitic detection (hysteresis).

The output of the AVD comparator is directly readable by the application software through a real time status bit (AVDF) in the SICSR register. This bit is read only.

Caution: The AVD functions only if the LVD is en-

and

refer-

abled through the option byte.

7.6.2.1 Monitoring the V

Main Supply

The AVD voltage threshold value is relative to the selected LVD threshold configured by option byte (see section 15.1 on page 161).

If the AVD interrupt is enabled, an interrupt is generated when the voltage crosses the V V

IT-(AVD)

threshold (AVDF bit is set).

IT+(LVD)

In the case of a drop in voltage, the AVD interrupt acts as an early warning, allowing software to shut down safely before the LVD resets the microcontroller. See Figure 19.

Figure 19. Using the AVD to Monitor V

IT+(AVD)

IT-(AVD)

IT+(LVD)

IT-(LVD)

AVDF bit

AVD INTERRUPT REQUEST

IF AVDIE bit = 1

LVD RESET

INTERRUPT Cleared by

Early Warning Interrupt

(Power has dropped, MCU not not yet in reset)

hyst

RESET

reset

INTERRUPT Cleared by

hardware

32/173

SYSTEM INTEGRITY MANAGEMENT (Cont’d)

7.6.3 Low Power Modes

Mode Description

WAIT

HALT

No effect on SI. AVD interrupts cause the device to exit from Wait mode.

The SICSR register is frozen. The AVD becomes inactive and the AVD interrupt cannot be used to exit from Halt mode.

7.6.3.1 Interrupts

The AVD interrupt event generates an interrupt if the corresponding Enable Control Bit (AVDIE) is

ST7LITE3xF2

set and the interrupt mask in the CC register is reset (RIM instruction).

Flag

Enable

Control

Bit

Interrupt Event

AVD event AVDF AVDIE Yes No

Event

Exit from Wait

Exit

from

Halt

33/173

ST7LITE3xF2

SYSTEM INTEGRITY MANAGEMENT (Cont’d)

7.6.4 Register Description SYSTEM INTEGRITY (SI) CONTROL/STATUS REGISTER (SICSR)

Read/Write Reset Value: 0110 0xx0 (6xh)

0 CR1 CR0

WDG

LOCKED LVDRF AVDF AVDIE

Bit 1 = AVDF Voltage Detector flag This read-only bit is set and cleared by hardware. If the AVDIE bit is set, an interrupt request is generated when the AVDF bit is set. Refer to Figure

19 and to Section 7.6.2.1 for additional details.

over AVD threshold

0: V

under AVD threshold

1: V

Bit 7 = Reserved, must be kept cleared.

Bits 6:5 = CR[1:0] RC Oscillator Frequency Ad-

justment bits

These bits, as well as CR[9:2] bits in the RCCR register must be written immediately after reset to adjust the RC oscillator frequency and to obtain an accuracy of 1%. Refer to section 7.3 on page 24

Bit 4 = WDGRF Watchdog reset flag This bit indicates that the last Reset was generated by the Watchdog peripheral. It is set by hardware (watchdog reset) and cleared by software (by reading SICSR register) or an LVD Reset (to ensure a stable cleared state of the WDGRF flag when CPU starts). Combined with the LVDRF flag information, the flag description is given by the following table.

RESET Sources LVDRF WDGRF

External RESET

Watchdog 0 1

LVD 1 X

pin 0 0

Bit 3 = LOCKED PLL Locked Flag This bit is set by hardware. It is cleared only by a power-on reset. It is set automatically when the PLL reaches its operating frequency. 0: PLL not locked 1: PLL locked

Bit 0 = AVDIE Voltage Detector interrupt enable This bit is set and cleared by software. It enables an interrupt to be generated when the AVDF flag is set. The pending interrupt information is automatically cleared when software enters the AVD interrupt routine. 0: AVD interrupt disabled 1: AVD interrupt enabled

Application notes

The LVDRF flag is not cleared when another RESET type occurs (external or watchdog), the LVDRF flag remains set to keep trace of the original failure. In this case, a watchdog reset can be detected by software while an external reset can not.

Bit 2 = LVDRF LVD reset flag This bit indicates that the last Reset was generated by the LVD block. It is set by hardware (LVD reset) and cleared by software (by reading). When the LVD is disabled by OPTION BYTE, the LVDRF bit value is undefined.

34/173

8 INTERRUPTS

ST7LITE3xF2

The ST7 core may be interrupted by one of two different methods: Maskable hardware interrupts as listed in the “interrupt mapping” table and a nonmaskable software interrupt (TRAP). The Interrupt processing flowchart is shown in Figure 20.

The maskable interrupts must be enabled by clearing the I bit in order to be serviced. However, disabled interrupts may be latched and processed when they are enabled (see external interrupts subsection).

Note: After reset, all interrupts are disabled. When an interrupt has to be serviced: – Normal processing is suspended at the end of

the current instruction execution.

– The PC, X, A and CC registers are saved onto

the stack.

– The I bit of the CC register is set to prevent addi-

tional interrupts.

– The PC is then loaded with the interrupt vector of

the interrupt to service and the first instruction of the interrupt service routine is fetched (refer to the Interrupt Mapping table for vector addresses).

The interrupt service routine should finish with the IRET instruction which causes the contents of the saved registers to be recovered from the stack.

Note: As a consequence of the IRET instruction, the I bit is cleared and the main program resumes.

Priority Management

By default, a servicing interrupt cannot be interrupted because the I bit is set by hardware entering in interrupt routine.

In the case when several interrupts are simultaneously pending, an hardware priority defines which one will be serviced first (see the Interrupt Mapping table).

Interrupts and Low Power Mode

All interrupts allow the processor to leave the WAIT low power mode. Only external and specifically mentioned interrupts allow the processor to leave the HALT low power mode (refer to the “Exit from HALT” column in the Interrupt Mapping table).

8.1 NON MASKABLE SOFTWARE INTERRUPT

This interrupt is entered when the TRAP instruction is executed regardless of the state of the I bit. It is serviced according to the flowchart in Figure

20.

8.2 EXTERNAL INTERRUPTS

External interrupt vectors can be loaded into the PC register if the corresponding external interrupt occurred and if the I bit is cleared. These interrupts allow the processor to leave the HALT low power mode.

The external interrupt polarity is selected through the miscellaneous register or interrupt register (if available).

An external interrupt triggered on edge will be latched and the interrupt request automatically cleared upon entering the interrupt service routine.

Caution: The type of sensitivity defined in the Miscellaneous or Interrupt register (if available) applies to the ei source. In case of a NANDed source (as described in the I/O ports section), a low level on an I/O pin, configured as input with interrupt, masks the interrupt request even in case of risingedge sensitivity.

8.3 PERIPHERAL INTERRUPTS

Different peripheral interrupt flags in the status register are able to cause an interrupt when they are active if both:

– The I bit of the CC register is cleared. – The corresponding enable bit is set in the control

If any of these two conditions is false, the interrupt is latched and thus remains pending.

Clearing an interrupt request is done by: – Writing “0” to the corresponding bit in the status

– Access to the status register while the flag is set

followed by a read or write of an associated register.

Note: The clearing sequence resets the internal latch. A pending interrupt (that is, waiting for being enabled) will therefore be lost if the clear sequence is executed.

35/173

ST7LITE3xF2

INTERRUPTS (cont’d)

Figure 20. Interrupt Processing Flowchart

FROM RESET

I BIT SET?

INTERRUPT

PENDING?

STACK PC, X, A, CC

SET I BIT

LOAD PC FROM INTERRUPT VECTOR

EXECUTE INSTRUCTION

RESTORE PC, X, A, CC FROM STACK

FETCH NEXT INSTRUCTION

THIS CLEARS I BIT BY DEFAULT

IRET?

Table 6. Interrupt Mapping

N°

Source

Block

Description

RESET Reset

TRAP Software Interrupt no FFFCh-FFFDh

0 AWU 7 Interrupt AWUCSR yes

Label

N/A

Priority

Order

Highest

Priority

1 ei0 External Interrupt 0 2 ei1 External Interrupt 1 FFF6h-FFF7h 3 ei2 External Interrupt 2 FFF4h-FFF5h

N/A yes

4 ei3 External Interrupt 3 FFF2h-FFF3h 5 LITE TIMER LITE TIMER RTC2 interrupt LTCSR2 no FFF0h-FFF1h

6 LINSCI LINSCI Interrupt

SCICR1/

SCICR2

7 SI AVD interrupt SICSR no FFECh-FFEDh

AT TIMER

AT TIMER Output Compare Interrupt or Input Capture Interrupt

PWMxCSR

or ATCSR

9 AT TIMER Overflow Interrupt ATCSR yes

LITE TIMER

11 LITE TIMER RTC1 Interrupt LTCSR yes 12 SPI SPI Peripheral Interrupts SPICSR yes FFE2h-FFE3h

LITE TIMER Input Capture Interrupt LTCSR no FFE6h-FFE7h

Lowest Priority

13 AT TIMER AT TIMER Overflow Interrupt 2 ATCSR2 no FFE0h-FFE1h

Exit

from

HALT

Address

Vector

yes FFFEh-FFFFh

FFFAh-FFFBh

FFF8h-FFF9h

no FFEEh-FFEFh

no FFEAh-FFEBh

FFE8h-FFE9h

FFE4h-FFE5h

Note 1: This interrupt exits the MCU from “Auto Wake-up from Halt” mode only. Note 2: These interrupts exit the MCU from “ACTIVE-HALT” mode only.

36/173

INTERRUPTS (Cont’d)

ST7LITE3xF2

EXTERNAL INTERRUPT CONTROL REGISTER (EICR)

Read/Write Reset Value: 0000 0000 (00h)

IS31 IS30 IS21 IS20 IS11 IS10 IS01 IS00

Bit 7:6 = IS3[1:0] ei3 sensitivity These bits define the interrupt sensitivity for ei3 (Port B0) according to Table 7.

EXTERNAL INTERRUPT SELECTION REGISTER (EISR)

Read/Write Reset Value: 0000 0000 (00h)

ei31 ei30 ei21 ei20 ei11 ei10 ei01 ei00

Bit 7:6 = ei3[1:0] ei3 pin selection These bits are written by software. They select the Port B I/O pin used for the ei3 external interrupt according to the table below.

Bit 5:4 = IS2[1:0] ei2 sensitivity These bits define the interrupt sensitivity for ei2 (Port B3) according to Table 7.

Bit 3:2 = IS1[1:0] ei1 sensitivity These bits define the interrupt sensitivity for ei1 (Port A7) according to Table 7.

Bit 1:0 = IS0[1:0] ei0 sensitivity

External Interrupt I/O pin selection

ei31 ei30 I/O Pin

0 0 No interrupt * 0 1 PB0 1 0 PB1 1 1 PB2

* Reset State

These bits define the interrupt sensitivity for ei0 (Port A0) according to Table 7.

Note: These 8 bits can be written only when the I bit in the CC register is set.

Bit 5:4 = ei2[1:0] ei2 pin selection These bits are written by software. They select the Port B I/O pin used for the ei2 external interrupt according to the table below.

External Interrupt I/O pin selection

Table 7. Interrupt Sensitivity Bits

ei21 ei20 I/O Pin

ISx1 ISx0 External Interrupt Sensitivity

0 0 Falling edge & low level 0 1 Rising edge only 1 0 Falling edge only 1 1 Rising and falling edge

0 0 No interrupt * 0 1 PB3 1 0 PB5 1 1 PB6

* Reset State

37/173

ST7LITE3xF2

INTERRUPTS (Cont’d)

Bit 3:2 = ei1[1:0] ei1 pin selection These bits are written by software. They select the Port A I/O pin used for the ei1 external interrupt according to the table below.

External Interrupt I/O pin selection

ei11 ei10 I/O Pin

0 0 No interrupt* 01 PA4 10 PA5 11 PA6

Port A I/O pin used for the ei0 external interrupt according to the table below.

External Interrupt I/O pin selection

ei01 ei00 I/O Pin

0 0 No Interrupt* 0 1 PA1 1 0 PA2 1 1 PA3

* Reset State

* Reset State Bit 1:0 = ei0[1:0] ei0 pin selection

These bits are written by software. They select the

Bits 1:0 = Reserved.

38/173

9 POWER SAVING MODES

ST7LITE3xF2

9.1 INTRODUCTION

To give a large measure of flexibility to the application in terms of power consumption, five main power saving modes are implemented in the ST7 (see

Figure 21):

■ Slow

■ Wait (and Slow-Wait)

■ Active Halt

■ Auto Wake up From Halt (AWUFH)

■ Halt

After a RESET the normal operating mode is selected by default (RUN mode). This mode drives the device (CPU and embedded peripherals) by means of a master clock which is based on the main oscillator frequency divided or multiplied by 2

OSC2

From RUN mode, the different power saving modes may be selected by setting the relevant register bits or by calling the specific ST7 software instruction whose action depends on the oscillator status.

Figure 21. Power Saving Mode Transitions

High

9.2 SLOW MODE

This mode has two targets: – To reduce power consumption by decreasing the

internal clock in the device,

– To adapt the internal clock frequency (f

CPU

) to

the available supply voltage.

SLOW mode is controlled by the SMS bit in the MCCSR register which enables or disables Slow mode.

In this mode, the oscillator frequency is divided by

32. The CPU and peripherals are clocked at thislower frequency.

Note: SLOW-WAIT mode is activated when entering WAIT mode while the device is already in SLOW mode.

Figure 22. SLOW Mode Clock Transition

/32 f

CPU

OSC

RUN

SLOW

WAIT

SLOW WAIT

ACTIVE HALT

AUTO WAKE UP FROM HALT

HALT

POWER CONSUMPTION

SMS

NORMAL RUN MODE

REQUEST

Low

39/173

ST7LITE3xF2

POWER SAVING MODES (Cont’d)

9.3 WAIT MODE

WAIT mode places the MCU in a low power consumption mode by stopping the CPU. This power saving mode is selected by calling the ‘WFI’ instruction. All peripherals remain active. During WAIT mode, the I bit of the CC register is cleared, to enable all interrupts. All other registers and memory remain unchanged. The MCU remains in WAIT mode until an interrupt or RESET occurs, whereupon the Program Counter branches to the starting address of the interrupt or Reset service routine. The MCU will remain in WAIT mode until a Reset or an Interrupt occurs, causing it to wake up.

Refer to Figure 23.

Figure 23. WAIT Mode Flow-chart

OSCILLATOR

WFI INSTRUCTION

INTERRUPT

PERIPHERALS CPU IBIT

RESET

OSCILLATOR PERIPHERALS CPU IBIT

256 OR 4096 CPU CLOCK

CYCLE DELAY

OSCILLATOR PERIPHERALS CPU IBIT

ON ON

OFF

ON ON ON X

FETCH RESET VECTOR

OR SERVICE INTERRUPT

Note:

1. Before servicing an interrupt, the CC register is

pushed on the stack. The I bit of the CC register is set during the interrupt routine and cleared when the CC register is popped.

40/173

POWER SAVING MODES (Cont’d)

ST7LITE3xF2

9.4 HALT MODE

The HALT mode is the lowest power consumption mode of the MCU. It is entered by executing the ‘HALT’ instruction when ACTIVE-HALT is disabled (see section 9.5 on page 42 for more details) and when the AWUEN bit in the AWUCSR register is cleared.

The MCU can exit HALT mode on reception of either a specific interrupt (see Table 6, “Interrupt Mapping,” on page 36) or a RESET. When exiting HALT mode by means of a RESET or an interrupt, the oscillator is immediately turned on and the 256 CPU cycle delay is used to stabilize the oscillator. After the start up delay, the CPU resumes operation by servicing the interrupt or by fetching the reset vector which woke it up (see Figure 25).

When entering HALT mode, the I bit in the CC register is forced to 0 to enable interrupts. Therefore, if an interrupt is pending, the MCU wakes up immediately.

In HALT mode, the main oscillator is turned off causing all internal processing to be stopped, including the operation of the on-chip peripherals. All peripherals are not clocked except the ones which get their clock supply from another clock generator (such as an external or auxiliary oscillator).

The compatibility of Watchdog operation with HALT mode is configured by the “WDGHALT” option bit of the option byte. The HALT instruction when executed while the Watchdog system is enabled, can generate a Watchdog RESET (see sec-

tion 15.1 on page 161 for more details).

Figure 24. HALT Timing Overview

Figure 25. HALT Mode Flow-chart

HALT INSTRUCTION

(Active Halt disabled)

(AWUCSR.AWUEN=0)

WATCHDOG

RESET

CYCLE

WDGHALT

WATCHDOG

RESET

INTERRUPT

ENABLE

OSCILLATOR PERIPHERALS CPU IBIT

256 OR 4096 CPU CLOCK

OSCILLATOR PERIPHERALS CPU IBIT

DISABLE

DELAY

OFF OFF OFF

OFF

ON X

ON ON ON X

HALTRUN RUN

HALT

INSTRUCTION

[Active Halt disabled]

256 or 4096 CPU

CYCLE DELAY

RESET

INTERRUPT

FETCH

VECTOR

FETCH RESET VECTOR

OR SERVICE INTERRUPT

Notes:

1. WDGHALT is an option bit. See option byte sec-

tion for more details.

2. Peripheral clocked with an external clock source can still be active.

3. Only some specific interrupts can exit the MCU from HALT mode (such as external interrupt). Refer to Table 6, “Interrupt Mapping,” on page 36 for more details.

4. Before servicing an interrupt, the CC register is pushed on the stack. The I bit of the CC register is set during the interrupt routine and cleared when the CC register is popped.

41/173

ST7LITE3xF2

POWER SAVING MODES (Cont’d)

9.4.0.1 Halt Mode Recommendations

– Make sure that an external event is available to

wake up the microcontroller from Halt mode.

– When using an external interrupt to wake up the

microcontroller, reinitialize the corresponding I/O as “Input Pull-up with Interrupt” or “floating interrupt” before executing the HALT instruction. The main reason for this is that the I/O may be wrongly configured due to external interference or by an unforeseen logical condition.

– For the same reason, reinitialize the level sensi-

tiveness of each external interrupt as a precautionary measure.

– The opcode for the HALT instruction is 0x8E. To

avoid an unexpected HALT instruction due to a program counter failure, it is advised to clear all occurrences of the data value 0x8E from memory. For example, avoid defining a constant in program memory with the value 0x8E.

– As the HALT instruction clears the interrupt mask

in the CC register to allow interrupts, the user may choose to clear all pending interrupt bits before executing the HALT instruction. This avoids entering other peripheral interrupt routines after executing the external interrupt routine corresponding to the wake-up event (reset or external interrupt).

9.5 ACTIVE-HALT MODE

ACTIVE-HALT mode is the lowest power consumption mode of the MCU with a real time clock (RTC) available. It is entered by executing the ‘HALT’ instruction. The decision to enter either in ACTIVE-HALT or HALT mode is given by the LTCSR/ATCSR register status as shown in the following table:.

LTCSR1

TB1IE bit

ATCSR

OVFIE1

0xx0 00xx 1 xxx

x 101

bit

ATCSR CK1 bit

ATCSR CK0 bit

ACTIVE-HALT mode disabled

ACTIVE-HALT mode enabled

Meaning

The MCU can exit ACTIVE-HALT mode on reception of a specific interrupt (see Table 6, “Interrupt Mapping,” on page 36) or a RESET.

– When exiting ACTIVE-HALT mode by means of

a RESET, a 256 CPU cycle delay occurs. After the start up delay, the CPU resumes operation by fetching the reset vector which woke it up (see

Figure 27).

– When exiting ACTIVE-HALT mode by means of

an interrupt, the CPU immediately resumes operation by servicing the interrupt vector which woke it up (see Figure 27).

When entering ACTIVE-HALT mode, the I bit in the CC register is cleared to enable interrupts. Therefore, if an interrupt is pending, the MCU wakes up immediately (see Note 3).

In ACTIVE-HALT mode, only the main oscillator and the selected timer counter (LT/AT) are running to keep a wake-up time base. All other peripherals are not clocked except those which get their clock supply from another clock generator (such as external or auxiliary oscillator).

42/173

Note: As soon as ACTIVE-HALT is enabled, executing a HALT instruction while the Watchdog is active does not generate a RESET. This means that the device cannot spend more than a defined delay in this power saving mode.

POWER SAVING MODES (Cont’d)

ST7LITE3xF2

Figure 26. ACTIVE-HALT Timing Overview

ACTIVE

HALTRUN RUN

HALT

INSTRUCTION

[Active Halt Enabled]

256 OR 4096 CPU

CYCLE DELAY

RESET

INTERRUPT

FETCH

VECTOR

Figure 27. ACTIVE-HALT Mode Flow-chart

HALT INSTRUCTION

(Active Halt enabled)

(AWUCSR.AWUEN=0)

INTERRUPT

OSCILLATOR PERIPHERALS CPU IBIT

RESET

OSCILLATOR PERIPHERALS CPU IBIT

ON OFF OFF

ON OFF

9.6 AUTO WAKE UP FROM HALT MODE

Auto Wake Up From Halt (AWUFH) mode is similar to Halt mode with the additional of an internal RC oscillator for wake-up. Compared to ACTIVEHALT mode, AWUFH has lower power consumption (the main clock is not kept running), but there is no accurate realtime clock available.

It is entered by executing the HALT instruction when the AWUEN bit in the AWUCSR register has been set.

Figure 28. AWUFH Mode Block Diagram

AWUCK Opt bit

AWU RC

Oscillator

32-KHz

Timer Auto-Reload

Input Capture

Oscillator

AWU_RC

AWUFH

/64

divider

AWUFH

prescaler/1 .. 255

interrupt

(ei0 source)

256 OR 4096 CPU

CLOCK CYCLE

OSCILLATOR PERIPHERALS CPU IBIT

FETCH RESET VECTOR

OR SERVICE INTERRUPT

DELAY

Notes:

1. This delay occurs only if the MCU exits ACTIVE-

HALT mode by means of a RESET.

2. Peripherals clocked with an external clock source can still be active.

3. Only the RTC1 interrupt and some specific interrupts can exit the MCU from ACTIVE-HALT mode. Refer to Table 6, “Interrupt Mapping,” on page 36 for more details.

4. Before servicing an interrupt, the CC register is pushed on the stack. The I bit of the CC register is set during the interrupt routine and cleared when the CC register is popped.

As soon as HALT mode is entered, and if the AWUEN bit has been set in the AWUCSR register, the AWU RC oscillator provides a clock signal (f

AWU_RC

). Its frequency is divided by a fixed divider and a programmable prescaler controlled by the AWUPR register. The output of this prescaler provides the delay time. When the delay has elapsed the AWUF flag is set by hardware and an interrupt wakes-up the MCU from Halt mode. At the same time the main oscillator is immediately turned on and a 256 cycle delay is used to stabilize it. After this start-up delay, the CPU resumes operation by servicing the AWUFH interrupt. The AWU flag and its associated interrupt are cleared by software reading the AWUCSR register.

To compensate for any frequency dispersion of the AWU RC oscillator, it can be calibrated by measuring the clock frequency f

AWU_RC

and then calculating the right prescaler value. Measurement mode is enabled by setting the AWUM bit in the AWUCSR register in Run mode. This connects f

AWU_RC

lad timer, allowing the f

to the input capture of the 12-bit Auto-Re-

AWU_RC

to be measured using the main oscillator clock as a reference timebase.

43/173

ST7LITE3xF2

POWER SAVING MODES (Cont’d)

Similarities with Halt mode

The following AWUFH mode behaviour is the same as normal Halt mode:

– The MCU can exit AWUFH mode by means of

any interrupt with exit from Halt capability or a reset (see Section 9.4 HALT MODE).

– When entering AWUFH mode, the I bit in the CC

Figure 29. AWUF Halt Timing Diagram

AWU

– In AWUFH mode, the main oscillator is turned off

causing all internal processing to be stopped, including the operation of the on-chip peripherals. None of the peripherals are clocked except those which get their clock supply from another clock generator (such as an external or auxiliary oscillator like the AWU oscillator).

– The compatibility of Watchdog operation with

AWUFH mode is configured by the WDGHALT option bit in the option byte. Depending on this setting, the HALT instruction when executed while the Watchdog system is enabled, can generate a Watchdog RESET.

RUN MODE HALT MODE 256 OR 4096 t

CPU

AWU_RC

AWUFH interrupt

CPU

RUN MODE

Clear by software

44/173

POWER SAVING MODES (Cont’d)

Figure 30. AWUFH Mode Flow-chart Notes:

1. WDGHALT is an option bit. See option byte sec-

tion for more details.

HALT INSTRUCTION

(Active-Halt disabled)

(AWUCSR.AWUEN=1)

2. Peripheral clocked with an external clock source can still be active.

3. Only an AWUFH interrupt and some specific in-

ENABLE

WATCHDOG

terrupts can exit the MCU from HALT mode (such as external interrupt). Refer to Table 6, “Interrupt Mapping,” on page 36 for more details.

WDGHALT

DISABLE

4. Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the CC reg-

WATCHDOG

RESET

AWU RC OSC ON MAIN OSC PERIPHERALS

CPU I[1:0] BITS

RESET

OFF OFF OFF

ister are set to the current software priority level of the interrupt routine and recovered when the CC register is popped.

ST7LITE3xF2

INTERRUPT

AWU RC OSC OFF

MAIN OSC PERIPHERALS CPU I[1:0] BITS

AWU RC OSC OFF MAIN OSC PERIPHERALS CPU I[1:0] BITS

FETCH RESET VECTOR

OR SERVICE INTERRUPT

256 CPU CLOCK

CYCLE

DELAY

OFF

ON ON ON

45/173

ST7LITE3xF2

POWER SAVING MODES (Cont’d)

9.6.0.1 Register Description

AWUFH CONTROL/STATUS REGISTER (AWUCSR)

Read/Write Reset Value: 0000 0000 (00h)

AWUFH PRESCALER REGISTER (AWUPR)

Read/Write Reset Value: 1111 1111 (FFh)

AWU

PR7

PR6

PR5

PR4

PR3

AWU

PR2

AWU

PR1

AWU

PR0

00000AWUFAWUMAWUEN

Bits 7:3 = Reserved.

Bit 1= AWUF Auto Wake Up Flag This bit is set by hardware when the AWU module generates an interrupt and cleared by software on reading AWUCSR. Writing to this bit does not change its value. 0: No AWU interrupt occurred 1: AWU interrupt occurred

Bit 2= AWUM Auto Wake Up Measurement This bit enables the AWU RC oscillator and connects its output to the input capture of the 12-bit auto-reload timer. This allows the timer to be used to measure the AWU RC oscillator dispersion and then compensate this dispersion by providing the right value in the AWUPR register. 0: Measurement disabled 1: Measurement enabled

Bit 0 = AWUEN Auto Wake Up From Halt Enabled This bit enables the Auto Wake Up From Halt feature: once HALT mode is entered, the AWUFH wakes up the microcontroller after a time delay dependent on the AWU prescaler value. It is set and cleared by software. 0: AWUFH (Auto Wake Up From Halt) mode disa-

bled

1: AWUFH (Auto Wake Up From Halt) mode ena-

bled

Bits 7:0= AWUPR[7:0] Auto Wake Up Prescaler These 8 bits define the AWUPR Dividing factor (as explained below

AWUPR[7:0

] Dividing factor

00h Forbidden 01h 1

... ...

FEh 254 FFh 255

In AWU mode, the period that the MCU stays in Halt Mode (t

in Figure 29 on page 44) is de-

AWU

fined by

AWU

64 AW U PR×

--------------------------t f

AWURC

+×=

RCSTRT

This prescaler register can be programmed to modify the time that the MCU stays in Halt mode before waking up automatically.

Note: If 00h is written to AWUPR, depending on the product, an interrupt is generated immediately after a HALT instruction, or the AWUPR remains unchanged.

Table 8. AWU Register Map and Reset Values

Address

(Hex.)

0049h

004Ah

46/173

Label

AWUPR

Reset Value

AWUCSR

Reset Value

76543210

AWUPR71AWUPR61AWUPR51AWUPR41AWUPR31AWUPR21AWUPR11AWUPR0

00000AWUFAWUMAWUEN

10 I/O PORTS

ST7LITE3xF2

10.1 INTRODUCTION

The I/O ports allow data transfer. An I/O port can contain up to 8 pins. Each pin can be programmed independently either as a digital input or digital output. In addition, specific pins may have several other functions. These functions can include external interrupt, alternate signal input/output for onchip peripherals or analog input.

10.2 FUNCTIONAL DESCRIPTION

A Data Register (DR) and a Data Direction Register (DDR) are always associated with each port. The Option Register (OR), which allows input/output options, may or may not be implemented. The following description takes into account the OR register. Refer to the Port Configuration table for device specific information.

An I/O pin is programmed using the corresponding bits in the DDR, DR and OR registers: bit x corresponding to pin x of the port.

Figure 31 shows the generic I/O block diagram.

10.2.1 Input Modes

Clearing the DDRx bit selects input mode. In this mode, reading its DR bit returns the digital value from that I/O pin.

If an OR bit is available, different input modes can be configured by software: floating or pull-up. Refer to I/O Port Implementation section for configuration.

Notes:

1. Writing to the DR modifies the latch value but does not change the state of the input pin.

2. Do not use read/modify/write instructions (BSET/BRES) to modify the DR register.

External Interrupt Function

Depending on the device, setting the ORx bit while in input mode can configure an I/O as an input with interrupt. In this configuration, a signal edge or level input on the I/O generates an interrupt request via the corresponding interrupt vector (eix).

Falling or rising edge sensitivity is programmed independently for each interrupt vector. The External Interrupt Control Register (EICR) or the Miscellaneous Register controls this sensitivity, depending on the device.

A device may have up to 7 external interrupts. Several pins may be tied to one external interrupt vector. Refer to Pin Description to see which ports have external interrupts.

If several I/O interrupt pins on the same interrupt vector are selected simultaneously, they are logically combined. For this reason if one of the interrupt pins is tied low, it may mask the others.

External interrupts are hardware interrupts. Fetching the corresponding interrupt vector automatically clears the request latch. Modifying the sensitivity bits will clear any pending interrupts.

10.2.2 Output Modes

Setting the DDRx bit selects output mode. Writing to the DR bits applies a digital value to the I/O through the latch. Reading the DR bits returns the previously stored value.

If an OR bit is available, different output modes can be selected by software: push-pull or opendrain. Refer to I/O Port Implementation section for configuration.

DR Value and Output Pin Status

DR Push-Pull Open-Drain

0V 1VOHFloating

10.2.3 Alternate Functions

Many ST7s I/Os have one or more alternate functions. These may include output signals from, or input signals to, on-chip peripherals. The Device Pin Description table describes which peripheral signals can be input/output to which ports.

A signal coming from an on-chip peripheral can be output on an I/O. To do this, enable the on-chip peripheral as an output (enable bit in the peripheral’s control register). The peripheral configures the I/O as an output and takes priority over standard I/ O programming. The I/O’s state is readable by addressing the corresponding I/O data register.

Configuring an I/O as floating enables alternate function input. It is not recommended to configure an I/O as pull-up as this will increase current consumption. Before using an I/O as an alternate input, configure it without interrupt. Otherwise spurious interrupts can occur.

Configure an I/O as input floating for an on-chip peripheral signal which can be input and output.

Caution: I/Os which can be configured as both an analog and digital alternate function need special attention. The user must control the peripherals so that the signals do not arrive at the same time on the same pin. If an external clock is used, only the clock alternate function should be employed on that I/O pin and not the other alternate function.

47/173

ST7LITE3xF2

I/O PORTS (Cont’d)

Figure 31. I/O Port General Block Diagram

DATA BUS

DDR SEL

DDR

OR SEL

DR SEL

ALTERNATE OUTPUT

From on-chip peripheral

ALTERNATE ENABLE BIT

If implemented

PULL-UP CONDITION

N-BUFFER

CMOS SCHMITT TRIGGER

P-BUFFER (see table below)

PULL-UP (see table below)

PAD

DIODES (see table below)

ANALOG

INPUT

EXTERNAL INTERRUPT REQUEST (eix)

SENSITIVITY SELECTION

Combinational

Logic

FROM OTHER BITS

Table 9. I/O Port Mode Options

Configuration Mode Pull-Up P-Buffer

Input

Output

Floating with/without Interrupt Off Pull-up with/without Interrupt On Push-pull Open Drain (logic level) Off True Open Drain NI NI NI (see note 1)

Legend: NI - not implemented

Off - implemented not activated

On - implemented and activated Note 1: The diode to V true open drain pads. A local protection between

is not implemented in the

ALTERNATE

To on-chip peripheral

Note: Refer to the Port Configuration table for device specific information.

Diodes

to V

Off

the pad and V vice against positive stress.

is implemented to protect the de-

Note 2: For further details on port configuration, please refer to Table 11 and Table 12 on page 51.

INPUT

to V

48/173

I/O PORTS (Cont’d)

Table 10. I/O Configurations

ST7LITE3xF2

Hardware Configuration

INPUT

PAD

NOTE 3

PULL-UP CONDITION

INTERRUPT CONDITION

FROM

OTHER

PINS

COMBINATIONAL

DR REGISTER ACCESS

LOGIC

POLARITY SELECTION

DR REGISTER ACCESS

DATA B U S

ALTERNATE INPUT To on-chip peripheral

EXTERNAL INTERRUPT SOURCE (eix)

ANALOG INPUT

R/W

DATA BUS

OPEN-DRAIN OUTPUT

DR REGISTER ACCESS

ALTERNATEALTERNATE

R/W

DATA B U S

PUSH-PULL OUTPUT

PAD

NOTE 3

ENABLE OUTPUT

BIT From on-chip peripheral

Notes:

1. When the I/O port is in input configuration and the associated alternate function is enabled as an output,

reading the DR register will read the alternate function output status.

2. When the I/O port is in output configuration and the associated alternate function is enabled as an input,

the alternate function reads the pin status given by the DR register content.

3. For true open drain, these elements are not implemented.

49/173

ST7LITE3xF2

I/O PORTS (Cont’d) Analog alternate function

Configure the I/O as floating input to use an ADC input. The analog multiplexer (controlled by the ADC registers) switches the analog voltage present on the selected pin to the common analog rail, connected to the ADC input.

Analog Recommendations

Do not change the voltage level or loading on any I/O while conversion is in progress. Do not have clocking pins located close to a selected analog pin.

WARNING: The analog input voltage level must be within the limits stated in the absolute maximum ratings.

10.3 I/O PORT IMPLEMENTATION

The hardware implementation on each I/O port depends on the settings in the DDR and OR registers and specific I/O port features such as ADC input or open drain.

Switching these I/O ports from one state to another should be done in a sequence that prevents unwanted side effects. Recommended safe transitions are illustrated in Figure 32. Other transitions are potentially risky and should be avoided, since they may present unwanted side-effects such as spurious interrupt generation.

Figure 32. Interrupt I/O Port State Transitions

10.4 UNUSED I/O PINS

Unused I/O pins must be connected to fixed voltage levels. Refer to Section 13.8.

10.5 LOW POWER MODES

Mode Description

WAIT

HALT

No effect on I/O ports. External interrupts cause the device to exit from WAIT mode.

No effect on I/O ports. External interrupts cause the device to exit from HALT mode.

10.6 INTERRUPTS

The external interrupt event generates an interrupt if the corresponding configuration is selected with DDR and OR registers and if the I bit in the CC register is cleared (RIM instruction).

Interrupt Event

External interrupt on selected external event

Event

Flag

Enable

Control

Bit

DDRx

ORx

Exit

from

Wait

Yes Yes

Exit

from

Halt

11 ON-CHIP PERIPHERALS

11.1 WATCHDOG TIMER (WDG)

11.1.1 Introduction

The Watchdog timer is used to detect the occurrence of a software fault, usually generated by external interference or by unforeseen logical conditions, which causes the application program to abandon its normal sequence. The Watchdog circuit generates an MCU reset on expiry of a programmed time period, unless the program refreshes the counter’s contents before the T6 bit becomes cleared.

11.1.2 Main Features

■ Programmable free-running downcounter (64

increments of 16000 CPU cycles)

■ Programmable reset

■ Reset (if watchdog activated) when the T6 bit

reaches zero

Figure 33. Watchdog Block Diagram

RESET

■ Optional reset on HALT instruction

(configurable by option byte)

■ Hardware Watchdog selectable by option byte

11.1.3 Functional Description

The counter value stored in the CR register (bits T[6:0]), is decremented every 16000 machine cycles, and the length of the timeout period can be programmed by the user in 64 increments.

If the watchdog is activated (the WDGA bit is set) and when the 7-bit timer (bits T[6:0]) rolls over from 40h to 3Fh (T6 becomes cleared), it initiates a reset cycle pulling low the reset pin for typically 30µs.

CPU

WATCHDOG CONTROL REGISTER (CR)

WDGA

7-BIT DOWNCOUNTER

CLOCK DIVIDER

÷16000

52/173

WATCHDOG TIMER (Cont’d) The application program must write in the CR reg-

ister at regular intervals during normal operation to prevent an MCU reset. This downcounter is freerunning: it counts down even if the watchdog is disabled. The value to be stored in the CR register must be between FFh and C0h (see Table 14

.Watchdog Timing):

– The WDGA bit is set (watchdog enabled) – The T6 bit is set to prevent generating an imme-

diate reset

– The T[5:0] bits contain the number of increments

which represents the time delay before the watchdog produces a reset.

Following a reset, the watchdog is disabled. Once activated it cannot be disabled, except by a reset.

The T6 bit can be used to generate a software reset (the WDGA bit is set and the T6 bit is cleared).

If the watchdog is activated, the HALT instruction will generate a Reset.

ST7LITE3xF2

Table 14.Watchdog Timing

= 8MHz

CPU

WDG

Counter

Code

C0h 1 2 FFh 127 128

Notes: The timing variation shown in Table 14 is due to the unknown status of the prescaler when writing to the CR register.

11.1.4 Hardware Watchdog Option

If Hardware Watchdog is selected by option byte, the watchdog is always active and the WDGA bit in the CR is not used.

Refer to the Option Byte description in section

15.1 on page 161.

11.1.4.1 Using Halt Mode with the WDG (WDGHALT option)

If Halt mode with Watchdog is enabled by option byte (No watchdog reset on HALT instruction), it is recommended before executing the HALT instruction to refresh the WDG counter, to avoid an unexpected WDG reset immediately after waking up the microcontroller.

min

[ms]

max

[ms]

53/173

ST7LITE3xF2

WATCHDOG TIMER (Cont’d)

11.1.5 Interrupts

None.

Bit 6:0 = T[6:0] 7-bit timer (MSB to LSB). These bits contain the decremented value. A reset is produced when it rolls over from 40h to 3Fh (T6 becomes cleared).

11.1.6 Register Description CONTROL REGISTER (CR)

Read/Write Reset Value: 0111 1111 (7Fh)

WDGA T6 T5 T4 T3 T2 T1 T0

Bit 7 = WDGA Activation bit. This bit is set by software and only cleared by hardware after a reset. When WDGA = 1, the watchdog can generate a reset. 0: Watchdog disabled 1: Watchdog enabled

Note: This bit is not used if the hardware watchdog option is enabled by option byte.

54/173

WATCHDOG TIMER (Cont’d)

Table 15. Watchdog Timer Register Map and Reset Values

ST7LITE3xF2

Address

(Hex.)

002Eh

Label

WDGCR

Reset Value

76543210

WDGA

55/173

ST7LITE3xF2

11.2 DUAL 12-BIT AUTORELOAD TIMER 3 (AT3)

11.2.1 Introduction

The 12-bit Autoreload Timer can be used for general-purpose timing functions. It is based on one or two free-running 12-bit upcounters with an input capture register and four PWM output channels. There are 6 external pins:

– Four PWM outputs – ATIC/LTIC pin for the Input Capture function – BREAK pin for forcing a break condition on the

PWM outputs

11.2.2 Main Features

■ Single Timer or Dual Timer mode with two 12-bit

upcounters (CNTR1/CNTR2) and two 12-bit autoreload registers (ATR1/ATR2)

■ Maskable overflow interrupts

Figure 34. Single Timer Mode (ENCNTR2=0)

ATIC

Edge Detection Circuit

12-Bit Autoreload Register 1

Clock Control

CPU

12-Bit Upcounter 1

12-bit Input Capture

PWM0 Duty Cycle Generator

PWM1 Duty Cycle Generator

PWM2 Duty Cycle Generator

PWM3 Duty Cycle Generator

■ PWM mode

– Generation of four independent PWMx signals – Dead time generation for Half bridge driving

mode with programmable dead time

– Frequency 2KHz-4MHz (@ 8 MHz f

CPU

– Programmable duty-cycles – Polarity control – Programmable output modes

■ Output Compare Mode

■ Input Capture Mode

– 12-bit input capture register (ATICR) – Triggered by rising and falling edges – Maskable IC interrupt – Long range input capture

■ Break control

■ Flexible Clock control

DTE bit

CMP Interrupt

OE0

OE1

OE2

OE3

Break Function

BPEN bit

Output Compare

Dead Time

Generator

)

PWM0

PWM1

PWM2

PWM3

56/173

from Lite Timer

1ms

OVF1 Interrupt

DUAL 12-BIT AUTORELOAD TIMER 3 (Cont’d)

Figure 35. Dual Timer Mode (ENCNTR2=1)

ST7LITE3xF2

ATIC

Edge Detection Circuit

12-Bit Autoreload Register 1

Clock Control

12-Bit Autoreload Register 2

CPU

1ms

12-Bit Upcounter 1

12-Bit Upcounter 2

12-bit Input Capture

PWM0 Duty Cycle Generator

PWM1 Duty Cycle Generator

OVF1 interrupt OVF2 interrupt

PWM2 Duty Cycle Generator

PWM3 Duty Cycle Generator

Output Compare

Dead Time

Generator

DTE bit

CMP Interrupt

OE0

OE1

OE2

OE3

Break Function

BPEN bit

PWM0

PWM1

PWM2

PWM3

57/173

ST7LITE3xF2

DUAL 12-BIT AUTORELOAD TIMER 3 (Cont’d)

11.2.3 Functional Description

11.2.3.1 PWM Mode

This mode allows up to four Pulse Width Modulated signals to be generated on the PWMx output pins.

PWM Frequency

The four PWM signals can have the same frequency (f cies. This is selected by the ENCNTR2 bit which enables single timer or dual timer mode (see Fig-

ure 34 and Figure 35).

The frequency is controlled by the counter period and the ATR register value. In dual timer mode, PWM2 and PWM3 can be generated with a different frequency controlled by CNTR2 and ATR2.

Following the above formula, – If f

COUNTER

is 2 MHz (ATR register value = 4094),the minimum value is 1 KHz (ATR register value = 0).

Duty Cycle

The duty cycle is selected by programming the DCRx registers. These are preload registers. The DCRx values are transferred in Active duty cycle registers after an overflow event if the corresponding transfer bit (TRANx bit) is set.

The TRAN1 bit controls the PWMx outputs driven by counter 1 and the TRAN2 bit controls the PWMx outputs driven by counter 2.

PWM generation and output compare are done by comparing these active DCRx values with the counter.

The maximum available resolution for the PWMx duty cycle is:

where ATR is equal to 0. With this maximum resolution, 0% and 100% duty cycle can be obtained by changing the polarity.

At reset, the counter starts counting from 0.

) or can have two different frequen-

PWM

= f

COUNTER

/ (4096 - ATR)

is 4 Mhz, the maximum value of f

Resolution = 1 / (4096 - ATR)

PWM

the active Duty Cycle registers and the PWMx signals are set to a high level. When the upcounter matches the active DCRx value the PWMx signals are set to a low level. To obtain a signal on a PWMx pin, the contents of the corresponding active DCRx register must be greater than the contents of the ATR register.

The maximum value of ATR is 4094 because it must be lower than the DCR value which must be 4095 in this case.

Polarity Inversion

The polarity bits can be used to invert any of the four output signals. The inversion is synchronized with the counter overflow if the corresponding transfer bit in the ATCSR2 register is set (reset value). See Figure 36.

Figure 36. PWM Polarity Inversion

PWMx

PWMxCSR Register

TRANx

ATCSR2 Register

OPx

counter

overflow

inverter

DFF

The Data Flip Flop (DFF) applies the polarity inversion when triggered by the counter overflow input.

Output Control

The PWMx output signals can be enabled or disabled using the OEx bits in the PWMCR register.

PWMx PIN

When a upcounter overflow occurs (OVF event), the preloaded Duty cycle values are transferred to

58/173

DUAL 12-BIT AUTORELOAD TIMER 3 (Cont’d)

Figure 37. PWM Function

4095

DUTY CYCLE

(DCRx)

AUTO-RELOAD

COUNTER

(ATR)

000

WITH OE=1 AND OPx=0

WITH OE=1 AND OPx=1

PWMx OUTPUT

Figure 38. PWM Signal from 0% to 100% Duty Cycle

ST7LITE3xF2

PWMx OUTPUTtWITH MOD00=1

AND OPx=0

PWMx OUTPUT

WITH MOD00=1

AND OPx=1

COUNTER

DCRx=000h

DCRx=FFDh

DCRx=FFEh

DCRx=000h

ATR= FFDh

FFDh FFEh FFFh FFDh FFEh FFFh FFDh FFEh

59/173

ST7LITE3xF2

DUAL 12-BIT AUTORELOAD TIMER 3 (Cont’d) Dead Time Generation

A dead time can be inserted between PWM0 and PWM1 using the DTGR register. This is required for half-bridge driving where PWM signals must not be overlapped. The non-overlapping PWM0/ PWM1 signals are generated through a programmable dead time by setting the DTE bit.

Dead time value = DT[6:0] x Tcounter1 DTGR[7:0] is buffered inside so as to avoid de-

forming the current PWM cycle. The DTGR effect will take place only after an overflow.

Figure 39. Dead Time Generation

counter1

CK_CNTR1

Notes:

1. Dead time is generated only when DTE=1 and DT[6:0] ≠ 0. If DTE is set and DT[6:0]=0, PWM output signals will be at their reset state.

2. Half Bridge driving is possible only if polarities of PWM0 and PWM1 are not inverted, i.e. if OP0 and OP1 are not set. If polarity is inverted, overlapping PWM0/PWM1 signals will be generated.

CNTR1

DCR0+1 ATR1DCR0

counter = DCR0

PWM 0

if DTE = 0

PWM 1

PWM 0

if DTE = 1

PWM 1

counter = DCR1

In the above example, when the DTE bit is set: – PWM goes low at DCR0 match and goes high at

ATR1+Tdt

– PWM1 goes high at DCR0+Tdt and goes low at

ATR match.

OVF

Tdt = DT[6:0] x T

counter1

With this programmable delay (Tdt), the PWM0 and PWM1 signals which are generated are not overlapped.

60/173

DUAL 12-BIT AUTORELOAD TIMER 3 (Cont’d) Break Function

The break function can be used to perform an emergency shutdown of the application being driven by the PWM signals.

The break function is activated by the external BREAK pin (active low). In order to use the BREAK pin it must be previously enabled by software setting the BPEN bit in the BREAKCR register.

When a low level is detected on the BREAK pin, the BA bit is set and the break function is activated. In this case, the 4 PWM signals are stopped.

Software can set the BA bit to activate the break function without using the BREAK pin.

When the break function is activated (BA bit =1):

Figure 40. Block Diagram of Break Function

BREAK pin

(Active Low)

ST7LITE3xF2

– The break pattern (PWM[3:0] bits in the BREAK-

CR) is forced directly on the PWMx output pins (after the inverter).

– The 12-bit PWM counter CNTR1 is put to its re-

set value, i.e. 00h.

– The 12-bit PWM counter CNTR2 is put to its re-

set value,i.e. 00h.

– ATR1, ATR2, Preload and Active DCRx are put

to their reset values. – The PWMCR register is reset. – Counters stop counting. When the break function is deactivated after ap-

plying the break (BA bit goes from 1 to 0 by software):

– The control of the 4 PWM outputs is transferred

to the port registers.

BREAKCR Register

PWM0

PWM1

PWM2

PWM3

Note: The BREAK pin value is latched by the BA bit.

(Inverters)

PWM0PWM1PWM2PWM3BPENBA

When BA is set:

PWM counter -> Reset value ATRx & DCRx -> Reset value PWM Mode -> Reset value

PWM0

PWM1

PWM2

PWM3

61/173

ST7LITE3xF2

DUAL 12-BIT AUTORELOAD TIMER 3 (Cont’d)

11.2.3.2 Output Compare Mode

To use this function, load a 12-bit value in the Preload DCRxH and DCRxL registers.

When the 12-bit upcounter (CNTR1) reaches the value stored in the Active DCRxH and DCRxL registers, the CMPFx bit in the PWMxCSR register is set and an interrupt request is generated if the CMPIE bit is set.

The output compare function is always performed on CNTR1 in both Single Timer mode and Dual Timer mode, and never on CNTR2. The difference is that in Single Timer mode the counter 1 can be compared with any of the four DCR registers, and

Figure 41. Block Diagram of Output Compare Mode (single timer)

DCRx

PRELOAD DUTY CYCLE REGx

TRAN1 (ATCSR2)

in Dual Timer mode, counter 1 is compared with DCR0 or DCR1.

Notes:

1. The output compare function is only available

for DCRx values other than 0 (reset value).

2. Duty cycle registers are buffered internally. The CPU writes in Preload Duty Cycle Registers and these values are transferred in Active Duty Cycle Registers after an overflow event if the corresponding transfer bit (TRAN1 bit) is set. Output compare is done by comparing these active DCRx values with the counter.

(ATCSR)

OVF

ACTIVE DUTY CYCLE REGx

CNTR1

COUNTER 1

CMP

OUTPUT COMPARE CIRCUIT

REQUESTINTERRUPT

CMPFx (PWMxCSR)

(ATCSR)CMPIE

62/173

DUAL 12-BIT AUTORELOAD TIMER 3 (Cont’d)

11.2.3.3 Input Capture Mode

ST7LITE3xF2

The 12-bit ATICR register is used to latch the value of the 12-bit free running upcounter CNTR1 after a rising or falling edge is detected on the ATIC pin. When an input capture occurs, the ICF bit is set and the ATICR register contains the value of the free running upcounter. An IC interrupt is generated if the ICIE bit is set. The ICF bit is reset by

Figure 42. Block Diagram of Input Capture Mode

ATIC

LTIMER

(1 ms timebase

@ 8MHz)

CPU

OFF

ATICR

ATCSR

12-BIT INPUT CAPTURE REGISTER

IC INTERRUPT

REQUEST

CK0CK1ICIEICF

12-BIT UPCOUNTER1

CNTR1

12-BIT AUTORELOAD REGISTER

ATR1

reading the ATICRH/ATICRL register when the ICF bit is set. The ATICR is a read only register and always contains the free running upcounter value which corresponds to the most recent input capture. Any further input capture is inhibited while the ICF bit is set.

Figure 43. Input Capture timing diagram

COUNTER

COUNTER1

ATIC PIN

ICF FLAG

01h

02h 03h 04h 05h 06h 07h

xxh

INTERRUPT

04h

08h 09h 0Ah

ATICR READ

09h

INTERRUPT

63/173

ST7LITE3xF2

DUAL 12-BIT AUTORELOAD TIMER 3 (Cont’d)

■ Long input capture

– The signal to be captured is connected to LTIC

Pulses that last between 8µs and 2s can be measured with an accuracy of 4µs if f

= 8MHz in the

OSC

– Input Capture registers LTICR, ATICRH and

following conditions: – The 12-bit AT3 Timer is clocked by the Lite Timer

(RTC pulse: CK[1:0] = 01 in the ATCSR register)

– The ICS bit in the ATCSR2 register is set so that

This configuration allows to cascade the Lite Timer and the 12-bit AT3 Timer to get a 20-bit input capture value. Refer to Figure 44.

the LTIC pin is used to trigger the AT3 Timer capture.

Figure 44. Long Range Input Capture Block Diagram

LTICR

8-bit Input Capture Register

OSC/32

8-bit Timebase Counter1

ATICRL are read

8 LSB bits

ATR1

12-bit AutoReload Register

LT IM E R

cpu

OFF

LT IC

AT IC

ICS

Notes:

1. Since the input capture flags (ICF) for both tim-

ers (AT3 Timer and LT Timer) are set when signal transition occurs, software must mask one interrupt by clearing the corresponding ICIE bit before setting the ICS bit.

2. If the ICS bit changes (from 0 to 1 or from 1 to

0), a spurious transition might occur on the input capture signal because of different values on LTIC and ATIC. To avoid this situation, it is recommended to do as follows:

– First, reset both ICIE bits. – Then set the ICS bit. – Reset both ICF bits.

CNTR1

12-bit Upcounter1

ATICR

12-bit Input Capture Register

LITE TIMER

12-Bit ARTIMER

12 MSB bits

– And then set the ICIE bit of desired interrupt.

3. How to compute a pulse length with long input capture feature.

As both timers are used, computing a pulse length is not straight-forward. The procedure is as follows:

– At the first input capture on the rising edge of the

pulse, we assume that values in the registers are

as follows:

LTICR = LT1

ATICRH = ATH1

ATICRL = ATL1

Hence ATICR1 [11:0] = ATH1 & ATL1 Refer to Figure 45 on page 65.

20 cascaded bits

64/173

DUAL 12-BIT AUTORELOAD TIMER 3 (Cont’d) – At the second input capture on the falling edge of

the pulse, we assume that the values in the registers are as follows: LTICR = LT2 ATICRH = ATH2

Now pulse width P between first capture and second capture will be: P = decimal (F9 – LT1 + LT2 + 1) * 0.004ms + decimal (ATICR2 - ATICR1 – 1) * 1ms

Figure 45. Long Range Input Capture Timing Diagram

OSC/32

ST7LITE3xF2

ATICRL = ATL2

Hence ATICR2 [11:0] = ATH2 & ATL2

TB Counter1

CNTR1

LTIC

LTICR

ATICRH

ATICRL

F9h 00h LT1 F9h 00h LT2

_ _ _

00h

ATH1 & ATL1

11.2.4 Low Power Modes

Mode Description

SLOW The input frequency is divided by 32 WAIT No effect on AT timer ACTIVE-

HALT

AT timer halted except if CK0=1, CK1=0 and OVFIE=1

HALT AT timer halted.

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _

_ _ _

LT1

ATH1

ATL1

ATICR = ATICRH[3:0] & ATICRL[7:0]

ATH2 & ATL2

LT2

ATH2

ATL2

65/173

ST7LITE3xF2

DUAL 12-BIT AUTORELOAD TIMER 3 (Cont’d)

11.2.5 Interrupts

Interrupt

Event

Overflow Event

AT3 IC Event

CMP Event CMPFx CMPIE Yes No No

Event

Flag

OVF1 OVIE1 Yes No Yes

Enable Control

Bit

ICF ICIE Yes No No

Exit

from

WAIT

Exit

from

HALT

Exit

from

ACTIVE

-HALT

Note 1: The CMP and AT3 IC events are connected to the same interrupt vector. The OVF event is mapped on a separate vector (see Interrupts chapter). They generate an interrupt if the enable bit is set in

the ATCSR register and the interrupt mask in the CC register is reset (RIM instruction).

Note 2: Only if CK0=1 and CK1=0 (f

)

LTIMER

COUNTER

66/173

DUAL 12-BIT AUTORELOAD TIMER 3 (Cont’d)

11.2.6 Register Description

TIMER CONTROL STATUS REGISTER (ATCSR)

Read / Write Reset Value: 0x00 0000 (x0h)

76 0

0 ICF ICIE CK1 CK0 OVF1 OVFIE1 CMPIE

Bit 7 = Reserved.

Bit 6 = ICF Input Capture Flag. This bit is set by hardware and cleared by software by reading the ATICR register (a read access to ATICRH or ATICRL will clear this flag). Writing to this bit does not change the bit value. 0: No input capture 1: An input capture has occurred

ST7LITE3xF2

0: Overflow interrupt disabled. 1: Overflow interrupt enabled.

Bit 0 = CMPIE Compare Interrupt Enable. This bit is read/write by software and cleared by hardware after a reset. It can be used to mask the interrupt generated when any of the CMPFx bit is set. 0: Output compare interrupt disabled. 1: Output Compare interrupt enabled.

COUNTER REGISTER 1 HIGH (CNTR1H)

Read only Reset Value: 0000 0000 (000h)

15 8

0000

CNTR1_11CNTR1_10CNTR1_9CNTR1_

Bit 5 = ICIE IC Interrupt Enable. This bit is set and cleared by software. 0: Input capture interrupt disabled 1: Input capture interrupt enabled

Bits 4:3 = CK[1:0] Counter Clock Selection. These bits are set and cleared by software and cleared by hardware after a reset. They select the clock frequency of the counter.

Counter Clock Selection CK1 CK0

OFF 0 0 OFF 1 1

(1 ms timebase @ 8 MHz) 0 1

LTIMER

CPU

Bit 2 = OVF1 Overflow Flag. This bit is set by hardware and cleared by software by reading the TCSR register. It indicates the transition of the counter1 CNTR1 from FFh to ATR1 value. 0: No counter overflow occurred 1: Counter overflow occurred

COUNTER REGISTER 1 LOW (CNTR1L)

Read only Reset Value: 0000 0000 (000h)

CNTR1_7CNTR1_6CNTR1_5CNTR1_4CNTR1_3CNTR1_2CNTR1_1CNTR1_

Bits 15:12 = Reserved.

Bits 11:0 = CNTR1[11:0] Counter Value. This 12-bit register is read by software and cleared by hardware after a reset. The counter CNTR1 is incremented continuously as soon as a counter clock is selected. To obtain the 12-bit value, software should read the counter value in two consecutive read operations. The CNTR1H register can be incremented between the two reads, and in order to be accurate when f

TIMER=fCPU

, the software should take this into account when CNTR1L and CNTR1H are read. If CNTR1L is close to its highest value, CNTR1H could be incremented before it is read. When a counter overflow occurs, the counter restarts from the value specified in the ATR1 register.

Bit 1 = OVFIE1 Overflow Interrupt Enable. This bit is read/write by software and cleared by hardware after a reset.

67/173

ST7LITE3xF2

DUAL 12-BIT AUTORELOAD TIMER 3 (Cont’d)

AUTORELOAD REGISTER (ATR1H)

Read / Write Reset Value: 0000 0000 (00h)

PWMx CONTROL STATUS REGISTER (PWMxCSR)

Read / Write Reset Value: 0000 0000 (00h)

15 8

76 0

0 0 0 0 ATR11 ATR10 ATR9 ATR8

000000OPxCMPFx

AUTORELOAD REGISTER (ATR1L)

Read / Write

Bits 7:2= Reserved, must be kept cleared.

Reset Value: 0000 0000 (00h)

Bit 1 = OPx PWMx Output Polarity. This bit is read/write by software and cleared by

ATR7 ATR6 ATR5 ATR4 ATR3 ATR2 ATR1 ATR0

hardware after a reset. This bit selects the polarity of the PWM signal. 0: The PWM signal is not inverted.

Bits 11:0 = ATR1[11:0] Autoreload Register 1.

1: The PWM signal is inverted.

This is a 12-bit register which is written by software. The ATR1 register value is automatically loaded into the upcounter CNTR1 when an overflow occurs. The register value is used to set the PWM frequency.

Bit 0 = CMPFx PWMx Compare Flag. This bit is set by hardware and cleared by software by reading the PWMxCSR register. It indicates that the upcounter value matches the Active DCRx register value.

PWM OUTPUT CONTROL REGISTER (PWMCR)

0: Upcounter value does not match DCRx value. 1: Upcounter value matches DCRx value.

Read/Write Reset Value: 0000 0000 (00h)

BREAK CONTROL REGISTER (BREAKCR)

Read/Write Reset Value: 0000 0000 (00h)

0OE30OE20OE10OE0

Bits 7:0 = OE[3:0] PWMx output enable. These bits are set and cleared by software and cleared by hardware after a reset. 0: PWM mode disabled. PWMx Output Alternate

Function disabled (I/O pin free for general purpose I/O)

1: PWM mode enabled

68/173

0 0 BA BPEN PWM3 PWM2 PWM1 PWM0

Bits 7:6 = Reserved. Forced by hardware to 0.

Bit 5 = BA Break Active. This bit is read/write by software, cleared by hardware after reset and set by hardware when the BREAK pin is low. It activates/deactivates the Break function. 0: Break not active 1: Break active

DUAL 12-BIT AUTORELOAD TIMER 3 (Cont’d) Bit 4 = BPEN Break Pin Enable.

This bit is read/write by software and cleared by hardware after Reset. 0: Break pin disabled 1: Break pin enabled

ST7LITE3xF2

INPUT CAPTURE REGISTER HIGH (ATICRH)

Read only Reset Value: 0000 0000 (00h)

15 8

Bit 3:0 = PWM[3:0] Break Pattern.

0 0 0 0 ICR11 ICR10 ICR9 ICR8

These bits are read/write by software and cleared by hardware after a reset. They are used to force the four PWMx output signals into a stable state when the Break function is active.

INPUT CAPTURE REGISTER LOW (ATICRL)

Read only Reset Value: 0000 0000 (00h)

PWMx DUTY CYCLE REGISTER HIGH (DCRxH)

Read / Write Reset Value: 0000 0000 (00h)

15 8

ICR7 ICR6 ICR5 ICR4 ICR3 ICR2 ICR1 ICR0

Bits 15:12 = Reserved.

0 0 0 0 DCR11 DCR10 DCR9 DCR8

Bits 11:0 = ICR[11:0] Input Capture Data. This is a 12-bit register which is readable by software and cleared by hardware after a reset. The ATICR register contains captured the value of the

PWMx DUTY CYCLE REGISTER LOW (DCRxL) Read / Write Reset Value: 0000 0000 (00h)

12-bit CNTR1 register when a rising or falling edge occurs on the ATIC or LTIC pin (depending on ICS). Capture will only be performed when the ICF flag is cleared.

TIMER CONTROL REGISTER2 (ATCSR2)

DCR7 DCR6 DCR5 DCR4 DCR3 DCR2 DCR1 DCR0

Read/Write Reset Value: 0000 0011 (03h)

Bits 15:12 = Reserved.

Bits 11:0 = DCRx[11:0] PWMx Duty Cycle Value This 12-bit value is written by software. It defines the duty cycle of the corresponding PWM output signal (see Figure 37).

In PWM mode (OEx=1 in the PWMCR register) the DCR[11:0] bits define the duty cycle of the PWMx output signal (see Figure 37). In Output Compare mode, they define the value to be compared with the 12-bit upcounter value.

0 0 ICS OVFIE2 OVF2

ENCNT

TRAN2 TRAN1

Bits 7:6 = Reserved. Forced by hardware to 0.

Bit 5 = ICS Input Capture Shorted This bit is read/write by software. It allows the ATtimer CNTR1 to use the LTIC pin for long input capture. 0 : ATIC for CNTR1 input capture 1 : LTIC for CNTR1 input capture

69/173

ST7LITE3xF2

DUAL 12-BIT AUTORELOAD TIMER 3 (Cont’d)

Bit 4 = OVFIE2 Overflow interrupt 2 enable This bit is read/write by software and controls the overflow interrupt of counter2. 0: Overflow interrupt disabled. 1: Overflow interrupt enabled.

AUTORELOAD REGISTER2 (ATR2H)

Read / Write Reset Value: 0000 0000 (00h)

15 8

Bit 3 = OVF2 Overflow Flag. This bit is set by hardware and cleared by software by reading the ATCSR2 register. It indicates the transition of the counter2 from FFFh to ATR2 value. 0: No counter overflow occurred 1: Counter overflow occurred

Bit 2 = ENCNTR2 Enable counter2 This bit is read/write be software and switches the

second counter CNTR2. If this bit is set, PWM2 and PWM3 will be generated using CNTR2. 0: CNTR2 stopped. 1: CNTR2 starts running.

Bit 1= TRAN2 Transfer enable2 This bit is read/write by software, cleared by hardware after each completed transfer and set by hardware after reset. It controls the transfers on CNTR2.

It allows the value of the Preload DCRx registers to be transferred to the Active DCRx registers after the next overflow event.

The OPx bits are transferred to the shadow OPx bits in the same way.

(Only DCR2/DCR3 can be controlled with this bit)

0 0 0 0 ATR11 ATR10 ATR9 ATR8

AUTORELOAD REGISTER (ATR2L)

Read / Write Reset Value: 0000 0000 (00h)

ATR7 ATR6 ATR5 ATR4 ATR3 ATR2 ATR1 ATR0

Bits 11:0 = ATR2[11:0] Autoreload Register 2. This is a 12-bit register which is written by software. The ATR2 register value is automatically loaded into the upcounter CNTR2 when an overflow of CNTR2 occurs. The register value is used to set the PWM2/PWM3 frequency when ENCNTR2 is set.

DEAD TIME GENERATOR REGISTER (DTGR)

Read/Write Reset Value: 0000 0000 (00h)

DTE DT6 DT5 DT4 DT3 DT2 DT1 DT0

Bit 0 = TRAN1 Transfer enable 1 This bit is read/write by software, cleared by hardware after each completed transfer and set by hardware after reset. It controls the transfers on CNTR1. It allows the value of the Preload DCRx registers to be transferred to the Active DCRx registers after the next overflow event.

The OPx bits are transferred to the shadow OPx bits in the same way.

70/173

Bits 7 = DTE Dead Time Enable This bit is read/write by software. It enables a dead time generation on PWM0/PWM1. 0: No Dead time insertion. 1: Dead time insertion enabled.

Bit 6:0 = DT[6:0] Dead Time Value These bits are read/write by software. They define

the dead time inserted between PWM0/PWM1. Dead time is calculated as follows:

Dead Time = DT[6:0] x Tcounter1

DUAL 12-BIT AUTORELOAD TIMER 3 (Cont’d)

Table 16. Register Map and Reset Values

ST7LITE3xF2

Address

(Hex.)

Label

ATCSR

Reset Value

CNTR1H

Reset Value

CNTR1L

Reset Value

ATR1H

Reset Value

ATR1L

Reset Value

PWMCR

Reset Value

PWM0CSR

Reset Value

PWM1CSR

Reset Value

PWM2CSR

Reset Value

PWM3CSR

Reset Value

DCR0H

Reset Value

DCR0L

Reset Value

DCR1H

Reset Value

DCR1L

Reset Value

DCR2H

Reset Value

DCR2L

Reset Value

DCR3H

Reset Value

DCR3L

Reset Value

ATICRH

Reset Value

ATICRL

Reset Value

765 4 3 2 1 0

000 0

CNTR1_70CNTR1_60CNTR1_50CNTR1_40CNTR1_30CNTR1_20CNTR1_10CNTR1_0

000 0

ATR7

000 0 0 0

000 0

DCR70DCR60DCR5

000 0

DCR70DCR60DCR5

000 0

DCR70DCR60DCR5

000 0

DCR70DCR60DCR5

000 0

ICR7

ICF

ATR6

OE3

ICR6

ICIE

ATR5

ICR5

CK1

ATR4

OE2

DCR4

ICR4

CK0

CNTR1_110CNTR1_100CNTR1_90CNTR1_8

ATR11

ATR3

DCR110DCR100DCR9

DCR3

DCR110DCR100DCR9

DCR3

DCR110DCR10

DCR3

DCR110DCR100DCR9

DCR3

ICR11

ICR3

OVF10OVFIE10CMPIE

ATR10

ATR2

OE1

DCR2

ICR10

ICR2

ATR9

ATR1

OP0

OP1

OP2

OP3

DCR1

DCR9

DCR1

ICR9

ICR1

ATR8

ATR0

OE0

CMPF0

CMPF1

CMPF2

CMPF3

DCR8

DCR0

DCR8

DCR0

DCR8

DCR0

DCR8

DCR0

ICR8

ICR0

71/173

ST7LITE3xF2

Address

(Hex.)

Label

ATCSR2

Reset Value

BREAKCR

Reset Value

ATR2H

Reset Value

ATR2L

Reset Value

DTGR

Reset Value

765 4 3 2 1 0

000 0

ATR7

DTE

ATR6

DT6

ICS

ATR5

DT5

OVFIE20OVF20ENCNTR20TRAN21TRAN1

BPEN

ATR4

DT4

PWM3

ATR11

ATR3

DT3

PWM2

ATR10

ATR2

DT2

PWM10PWM0

ATR9

ATR1

DT1

ATR8

ATR0

DT0

72/173

11.3 LITE TIMER 2 (LT2)

ST7LITE3xF2

11.3.1 Introduction

The Lite Timer can be used for general-purpose timing functions. It is based on two free-running 8bit upcounters and an 8-bit input capture register.

11.3.2 Main Features

■ Realtime Clock (RTC)

– One 8-bit upcounter 1 ms or 2 ms timebase

period (@ 8 MHz f

OSC

)

Figure 46. Lite Timer 2 Block Diagram

/32

OSC

LTCNTR

8-bit TIMEBASE

COUNTER 2

LTARR

8-bit AUTORELOAD

LTCSR2

– One 8-bit upcounter with autoreload and pro-

– 2 Maskable timebase interrupts

■ Input Capture

– 8-bit input capture register (LTICR) – Maskable interrupt with wakeup from Halt

grammable timebase period from 4µs to

1.024ms in 4µs increments (@ 8 MHz f

OSC

)

Mode capability

LTTB2

Interrupt request

TB2IE

LTIMER

TB2F

To 12-bit AT TImer

LTIC

8-bit TIMEBASE

COUNTER 1

LTICR

8-bit

INPUT CAPTURE

LTIMER

LTCSR1

Timebase 1 or 2 ms (@ 8MHz f

OSC

)

TB1F TB1IETBICFICIE

LTTB1 INTERRUPT REQUEST

LTIC INTERRUPT REQUEST

73/173

ST7LITE3xF2

LITE TIMER (Cont’d)

11.3.3 Functional Description

11.3.3.1 Timebase Counter 1

The 8-bit value of Counter 1 cannot be read or written by software. After an MCU reset, it starts incrementing from 0 at a frequency of f overflow event occurs when the counter rolls over from F9h to 00h. If f

= 8 MHz, then the time pe-

OSC

riod between two counter overflow events is 1 ms. This period can be doubled by setting the TB bit in the LTCSR1 register.

OSC

/32. An

LTARR reload value. Software can write a new value at anytime in the LTARR register, this value will be automatically loaded in the counter when the next overflow occurs.

When Counter 2 overflows, the TB2F bit in the LTCSR2 register is set by hardware and an interrupt request is generated if the TB2IE bit is set. The TB2F bit is cleared by software reading the LTCSR2 register.

11.3.3.3 Input Capture

When Counter 1 overflows, the TB1F bit is set by hardware and an interrupt request is generated if the TB1IE bit is set. The TB1F bit is cleared by software reading the LTCSR1 register.

11.3.3.2 Timebase Counter 2

Counter 2 is an 8-bit autoreload upcounter. It can be read by accessing the LTCNTR register. After an MCU reset, it increments at a frequency of

/32 starting from the value stored in the

OSC

LTARR register. A counter overflow event occurs when the counter rolls over from FFh to the

Figure 47. Input Capture Timing Diagram.

4µs

CPU

/32

OSC

8-bit COUNTER 1

LTIC PIN

ICF FLAG

LTICR REGISTER

(@ 8MHz f

01h

)

OSC

02h 03h 05h 06h 07h

xxh

04h

The 8-bit input capture register is used to latch the free-running upcounter (Counter 1) 1 after a rising or falling edge is detected on the LTIC pin. When an input capture occurs, the ICF bit is set and the LTICR register contains the value of Counter 1. An interrupt is generated if the ICIE bit is set. The ICF bit is cleared by reading the LTICR register.

The LTICR is a read-only register and always contains the data from the last input capture. Input capture is inhibited if the ICF bit is set.

CLEARED

BY S/W

READING

LTIC REGISTER

04h

07h

74/173

LITE TIMER (Cont’d)

11.3.4 Low Power Modes

ST7LITE3xF2

11.3.6 Register Description

Mode Description

No effect on Lite timer

SLOW

(this peripheral is driven directly

OSC

/32)

by f WAIT No effect on Lite timer ACTIVE-HALT No effect on Lite timer HALT Lite timer stops counting

11.3.5 Interrupts

Exit

from

Wait

Flag

Enable

Control

Bit

Interrupt

Event

Timebase 1 Event

Timebase 2 Event

IC Event ICF ICIE Yes No No

Event

TB1F TB1IE Yes Yes No

TB2F TB2IE Yes No No

Exit

from

Active

Halt

Exit

from

Halt

Note: The TBxF and ICF interrupt events are con-

nected to separate interrupt vectors (see Interrupts chapter).

They generate an interrupt if the enable bit is set in the LTCSR1 or LTCSR2 register and the interrupt mask in the CC register is reset (RIM instruction).

LITE TIMER CONTROL/STATUS REGISTER 2 (LTCSR2)

Read / Write Reset Value: 0x00 0000 (x0h)

000000TB2IETB2F

Bits 7:2 = Reserved, must be kept cleared.

Bit 1 = TB2IE Timebase 2 Interrupt enable. This bit is set and cleared by software. 0: Timebase (TB2) interrupt disabled 1: Timebase (TB2) interrupt enabled

Bit 0 = TB2F Timebase 2 Interrupt Flag. This bit is set by hardware and cleared by software reading the LTCSR2 register. Writing to this bit has no effect. 0: No Counter 2 overflow 1: A Counter 2 overflow has occurred

LITE TIMER AUTORELOAD REGISTER (LTARR)

Read / Write Reset Value: 0000 0000 (00h)

AR7 AR7 AR7 AR7 AR3 AR2 AR1 AR0

Bits 7:0 = AR[7:0] Counter 2 Reload Value. These bits register is read/write by software. The LTARR value is automatically loaded into Counter 2 (LTCNTR) when an overflow occurs.

75/173

ST7LITE3xF2

LITE TIMER (Cont’d)

LITE TIMER COUNTER 2 (LTCNTR)

Read only Reset Value: 0000 0000 (00h)

CNT7 CNT7 CNT7 CNT7 CNT3 CNT2 CNT1 CNT0

Bit 5 = TB Timebase period selection. This bit is set and cleared by software. 0: Timebase period = t 1: Timebase period = t

* 8000 (1ms @ 8 MHz)

OSC

* 16000 (2ms @ 8

OSC

MHz)

Bit 4 = TB1IE Timebase Interrupt enable. This bit is set and cleared by software.

Bits 7:0 = CNT[7:0] Counter 2 Reload Value. This register is read by software. The LTARR val-

0: Timebase (TB1) interrupt disabled 1: Timebase (TB1) interrupt enabled

ue is automatically loaded into Counter 2 (LTCNTR) when an overflow occurs.

Bit 3 = TB1F Timebase Interrupt Flag. This bit is set by hardware and cleared by software

LITE TIMER CONTROL/STATUS REGISTER (LTCSR1)

Read / Write Reset Value: 0x00 00x0 (xxh)

ICIE ICF TB TB1IE TB1F - - -

reading the LTCSR register. Writing to this bit has no effect. 0: No counter overflow 1: A counter overflow has occurred

Bits 2:0 = Reserved

LITE TIMER INPUT CAPTURE REGISTER

Bit 7 = ICIE Interrupt Enable. This bit is set and cleared by software. 0: Input Capture (IC) interrupt disabled 1: Input Capture (IC) interrupt enabled

(LTICR)

Read only Reset Value: 0000 0000 (00h)

Bit 6 = ICF Input Capture Flag. This bit is set by hardware and cleared by software by reading the LTICR register. Writing to this bit does not change the bit value. 0: No input capture 1: An input capture has occurred

Note: After an MCU reset, software must initialise the ICF bit by reading the LTICR register

76/173

ICR7 ICR6 ICR5 ICR4 ICR3 ICR2 ICR1 ICR0

Bits 7:0 = ICR[7:0] Input Capture Value These bits are read by software and cleared by hardware after a reset. If the ICF bit in the LTCSR is cleared, the value of the 8-bit up-counter will be captured when a rising or falling edge occurs on the LTIC pin.

LITE TIMER (Cont’d)

Table 17. Lite Timer Register Map and Reset Values

ST7LITE3xF2

Address

(Hex.)

Label

LTCSR2

Reset Value

LTARR

Reset Value

LTCNTR

Reset Value

LTCSR1

Reset Value

LTICR

Reset Value

76543210

000000

AR7

CNT7

ICIE

ICR7

AR6

CNT6

ICF

ICR6

AR5

CNT5

ICR5

AR4

CNT4

TB1IE

ICR4

AR3

CNT3

TB1F

ICR3

AR2

CNT2

0x0

ICR2

TB2IE

AR1

CNT1

ICR1

TB2F

AR0

CNT0

ICR0

77/173

ST7LITE3xF2

ON-CHIP PERIPHERALS (cont’d)

11.4 SERIAL PERIPHERAL INTERFACE (SPI)

11.4.1 Introduction

The Serial Peripheral Interface (SPI) allows fullduplex, synchronous, serial communication with external devices. An SPI system may consist of a master and one or more slaves or a system in which devices may be either masters or slaves.

11.4.2 Main Features

■ Full duplex synchronous transfers (on three

lines)

■ Simplex synchronous transfers (on two lines)

■ Master or slave operation

■ 6 master mode frequencies (f

■ f

■ SS Management by software or hardware

■ Programmable clock polarity and phase

■ End of transfer interrupt flag

■

/2 max. slave mode frequency (see note)

CPU

Write collision, Master Mode Fault and Overrun

CPU

/4 max.)

flags

Note: In slave mode, continuous transmission is not possible at maximum frequency due to the software overhead for clearing status flags and to initiate the next transmission sequence.

11.4.3 General Description

Figure 48 on page 79 shows the serial peripheral

interface (SPI) block diagram. There are three registers:

– SPI Control Register (SPICR) – SPI Control/Status Register (SPICSR) – SPI Data Register (SPIDR)

The SPI is connected to external devices through four pins:

– MISO: Master In / Slave Out data – MOSI: Master Out / Slave In data – SCK: Serial Clock out by SPI masters and in-

put by SPI slaves

: Slave select:

–SS

This input signal acts as a ‘chip select’ to let the SPI master communicate with slaves individually and to avoid contention on the data lines. Slave SS

inputs can be driven by stand-

ard I/O ports on the master Device.

78/173

SERIAL PERIPHERAL INTERFACE (SPI) (cont’d)

Figure 48. Serial Peripheral Interface Block Diagram

Data/Address Bus

ST7LITE3xF2

MOSI

MISO

SCK

SOD

bit

SPIDR

Read Buffer

8-bit Shift Register

Read

Write

MASTER

CONTROL

SERIAL CLOCK

GENERATOR

Interrupt request

SPIF WCOL MODF

OVR SSISSMSOD

SPI

STATE

CONTROL

SPIE SPE

SPR2

MSTR

CPOL

CPHA

SPICSR

SPICR

SPR1

SPR0

79/173

ST7LITE3xF2

SERIAL PERIPHERAL INTERFACE (cont’d)

11.4.3.1 Functional Description

A basic example of interconnections between a single master and a single slave is illustrated in

Figure 49.

The MOSI pins are connected together and the MISO pins are connected together. In this way data is transferred serially between master and slave (most significant bit first).

The communication is always initiated by the master. When the master device transmits data to a slave device via MOSI pin, the slave device responds by sending data to the master device via

Figure 49. Single Master/ Single Slave Application

the MISO pin. This implies full duplex communication with both data out and data in synchronized with the same clock signal (which is provided by the master device via the SCK pin).

To use a single data line, the MISO and MOSI pins must be connected at each node (in this case only simplex communication is possible).

Four possible data/clock timing relationships may be chosen (see Figure 52 on page 83) but master and slave must be programmed with the same timing mode.

MASTER

MSBit LSBit MSBit LSBit

+5V

MISO

MOSI

SCK

8-bit SHIFT REGISTER

SPI

CLOCK

GENERATOR

MISO

MOSI

SCK

SLAVE

8-bit SHIFT REGISTER

Not used if SS is managed by software

80/173

SERIAL PERIPHERAL INTERFACE (cont’d)

11.4.3.2 Slave Select Management

As an alternative to using the SS

pin to control the Slave Select signal, the application can choose to manage the Slave Select signal by software. This is configured by the SSM bit in the SPICSR register (see Figure 51).

In software management, the external SS

pin is free for other application uses and the internal SS signal level is driven by writing to the SSI bit in the SPICSR register.

In Master mode:

–SS

internal must be held high continuously

ST7LITE3xF2

In Slave Mode:

There are two cases depending on the data/clock timing relationship (see Figure 50):

If CPHA = 1 (data latched on second clock edge):

–SS

internal must be held low during the entire transmission. This implies that in single slave applications the SS V

, or made free for standard I/O by manag-

ing the SS

function by software (SSM = 1 and

SSI = 0 in the in the SPICSR register)

If CPHA = 0 (data latched on first clock edge):

–SS

internal must be held low during byte transmission and pulled high between each byte to allow the slave to write to the shift register. If SS

is not pulled high, a Write Collision error will occur when the slave writes to the shift register (see Section 11.4.5.3).

pin either can be tied to

Figure 50. Generic SS

MOSI/MISO

Master SS

Slave SS

(if CPHA = 0)

Slave SS

(if CPHA = 1)

Timing Diagram

Byte 1 Byte 2

Figure 51. Hardware/Software Slave Select Management

SSM bit

external pin

SSI bit

SS internal

Byte 3

81/173

ST7LITE3xF2

SERIAL PERIPHERAL INTERFACE (cont’d)

11.4.3.3 Master Mode Operation

In master mode, the serial clock is output on the SCK pin. The clock frequency, polarity and phase are configured by software (refer to the description of the SPICSR register).

Note: The idle state of SCK must correspond to the polarity selected in the SPICSR register (by pulling up SCK if CPOL = 1 or pulling down SCK if CPOL = 0).

How to operate the SPI in master mode

To operate the SPI in master mode, perform the following steps in order:

1. Write to the SPICR register: – Select the clock frequency by configuring the

SPR[2:0] bits.

– Select the clock polarity and clock phase by

configuring the CPOL and CPHA bits. Figure

52 shows the four possible configurations.

Note: The slave must have the same CPOL and CPHA settings as the master.

2. Write to the SPICSR register: – Either set the SSM bit and set the SSI bit or

clear the SSM bit and tie the SS the complete byte transmit sequence.

3. Write to the SPICR register: – Set the MSTR and SPE bits

Note: MSTR and SPE bits remain set only if SS

is high).

Important note: if the SPICSR register is not written first, the SPICR register setting (MSTR bit) may be not taken into account.

The transmit sequence begins when software writes a byte in the SPIDR register.

11.4.3.4 Master Mode Transmit Sequence

When software writes to the SPIDR register, the data byte is loaded into the 8-bit shift register and then shifted out serially to the MOSI pin most significant bit first.

When data transfer is complete:

– The SPIF bit is set by hardware. – An interrupt request is generated if the SPIE

bit is set and the interrupt mask in the CCR register is cleared.

Clearing the SPIF bit is performed by the following software sequence:

1. An access to the SPICSR register while the SPIF bit is set

2. A read to the SPIDR register

pin high for

Note: While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR register is read.

11.4.3.5 Slave Mode Operation

In slave mode, the serial clock is received on the SCK pin from the master device.

To operate the SPI in slave mode:

1. Write to the SPICSR register to perform the following actions:

– Select the clock polarity and clock phase by

configuring the CPOL and CPHA bits (see

Figure 52).

Note: The slave must have the same CPOL and CPHA settings as the master.

– Manage the SS

11.4.3.2 and Figure 50. If CPHA = 1 SS

be held low continuously. If CPHA = 0 SS must be held low during byte transmission and pulled up between each byte to let the slave write in the shift register.

2. Write to the SPICR register to clear the MSTR bit and set the SPE bit to enable the SPI I/O functions.

11.4.3.6 Slave Mode Transmit Sequence

When software writes to the SPIDR register, the data byte is loaded into the 8-bit shift register and then shifted out serially to the MISO pin most significant bit first.

The transmit sequence begins when the slave device receives the clock signal and the most significant bit of the data on its MOSI pin.

When data transfer is complete:

– The SPIF bit is set by hardware. – An interrupt request is generated if SPIE bit is

set and interrupt mask in the CCR register is cleared.

Clearing the SPIF bit is performed by the following software sequence:

1. An access to the SPICSR register while the SPIF bit is set

2. A write or a read to the SPIDR register

Notes: While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR register is read.

The SPIF bit can be cleared during a second transmission; however, it must be cleared before the second SPIF bit in order to prevent an Overrun condition (see Section 11.4.5.2).

pin as described in Section

must

82/173

SERIAL PERIPHERAL INTERFACE (cont’d)

11.4.4 Clock Phase and Clock Polarity

Four possible timing relationships may be chosen by software, using the CPOL and CPHA bits (See

Figure 52).

Note: The idle state of SCK must correspond to the polarity selected in the SPICSR register (by pulling up SCK if CPOL = 1 or pulling down SCK if CPOL = 0).

The combination of the CPOL clock polarity and CPHA (clock phase) bits selects the data capture clock edge.

Figure 52. Data Clock Timing Diagram

SCK

(CPOL = 1)

SCK (CPOL = 0)

ST7LITE3xF2

Figure 52 shows an SPI transfer with the four com-

binations of the CPHA and CPOL bits. The diagram may be interpreted as a master or slave timing diagram where the SCK pin, the MISO pin and the MOSI pin are directly connected between the master and the slave device.

Note: If CPOL is changed at the communication byte boundaries, the SPI must be disabled by resetting the SPE bit.

CPHA = 1

MISO

(from master)

MOSI

(from slave)

(to slave)

CAPTURE STROBE

SCK (CPOL = 1)

SCK (CPOL = 0)

MISO

(from master)

MOSI

(from slave)

(to slave)

CAPTURE STROBE

MSBit Bit 6 Bit 5

Bit 4 Bit3 Bit 2 Bit 1 LSBit

CPHA = 0

Bit 4 Bit3 Bit 2 Bit 1 LSBit

Note: This figure should not be used as a replacement for parametric information. Refer to the Electrical Characteristics chapter.

83/173

ST7LITE3xF2

SERIAL PERIPHERAL INTERFACE (cont’d)

11.4.5 Error Flags

11.4.5.1 Master Mode Fault (MODF)

Master mode fault occurs when the master device’s SS

When a Master mode fault occurs:

– The MODF bit is set and an SPI interrupt re-

– The SPE bit is reset. This blocks all output

– The MSTR bit is reset, thus forcing the device

Clearing the MODF bit is done through a software sequence:

1. A read access to the SPICSR register while the

2. A write to the SPICR register. Notes: To avoid any conflicts in an application

with multiple slaves, the SS high during the MODF bit clearing sequence. The SPE and MSTR bits may be restored to their original state during or after this clearing sequence.

Hardware does not allow the user to set the SPE and MSTR bits while the MODF bit is set except in the MODF bit clearing sequence.

In a slave device, the MODF bit can not be set, but in a multimaster configuration the device can be in slave mode with the MODF bit set.

The MODF bit indicates that there might have been a multimaster conflict and allows software to handle this using an interrupt routine and either perform a reset or return to an application default state.

pin is pulled low.

quest is generated if the SPIE bit is set.

from the device and disables the SPI peripheral.

into slave mode.

MODF bit is set.

pin must be pulled

11.4.5.2 Overrun Condition (OVR)

An overrun condition occurs when the master device has sent a data byte and the slave device has not cleared the SPIF bit issued from the previously transmitted byte.

When an Overrun occurs: – The OVR bit is set and an interrupt request is

generated if the SPIE bit is set.

In this case, the receiver buffer contains the byte sent after the SPIF bit was last cleared. A read to the SPIDR register returns this byte. All other bytes are lost.

The OVR bit is cleared by reading the SPICSR register.

11.4.5.3 Write Collision Error (WCOL)

A write collision occurs when the software tries to write to the SPIDR register while a data transfer is taking place with an external device. When this happens, the transfer continues uninterrupted and the software write will be unsuccessful.

Write collisions can occur both in master and slave mode. See also Section 11.4.3.2 Slave Select

Management.

Note: A "read collision" will never occur since the received data byte is placed in a buffer in which access is always synchronous with the CPU operation.

The WCOL bit in the SPICSR register is set if a write collision occurs.

No SPI interrupt is generated when the WCOL bit is set (the WCOL bit is a status flag only).

Clearing the WCOL bit is done through a software sequence (see Figure 53).

Figure 53. Clearing the WCOL Bit (Write Collision Flag) Software Sequence

Clearing sequence after SPIF = 1 (end of a data byte transfer)

1st Step

2nd Step

Clearing sequence before SPIF = 1 (during a data byte transfer)

1st Step

2nd Step

84/173

Read SPICSR

Read SPIDR

RESULT

SPIF = 0 WCOL = 0

Read SPICSR

Read SPIDR

RESULT

WCOL = 0

Note: Writing to the SPIDR register instead of reading it does not reset the WCOL bit.

SERIAL PERIPHERAL INTERFACE (cont’d)

11.4.5.4 Single Master and Multimaster Configurations

There are two types of SPI systems: – Single Master System – Multimaster System

Single Master System

A typical single master system may be configured using a device as the master and four devices as slaves (see Figure 54).

The master device selects the individual slave devices by using four pins of a parallel port to control the four SS

The SS

pins of the slave devices.

pins are pulled high during reset since the master device ports will be forced to be inputs at that time, thus disabling the slave devices.

Note: To prevent a bus conflict on the MISO line, the master allows only one active slave device

For more security, the slave device may respond to the master with the received data byte. Then the master will receive the previous byte back from the slave device if all MISO and MOSI pins are connected and the slave has not written to its SPIDR register.

Other transmission security methods can use ports for handshake lines or data bytes with command fields.

Multimaster System

A multimaster system may also be configured by the user. Transfer of master control could be implemented using a handshake method through the I/O ports or by an exchange of code messages through the serial peripheral interface system.

The multimaster system is principally handled by the MSTR bit in the SPICR register and the MODF bit in the SPICSR register.

during a transmission.

Figure 54. Single Master / Multiple Slave Configuration

ST7LITE3xF2

SCK

MOSI

SCK

Master Device

SS SS

Slave

Device

MISO

Ports

SCK

MOSI MOSI MOSIMISO MISO MISOMISO

Slave

Device

SCK SCK

Slave

Device

Slave

Device

85/173

ST7LITE3xF2

SERIAL PERIPHERAL INTERFACE (cont’d)

11.4.6 Low Power Modes

Mode Description

No effect on SPI.

WAIT

HALT

11.4.6.1 Using the SPI to wake up the device from Halt mode

In slave configuration, the SPI is able to wake up the device from HALT mode through a SPIF interrupt. The data received is subsequently read from the SPIDR register when the software is running (interrupt vector fetch). If multiple data transfers have been performed before software clears the SPIF bit, then the OVR bit is set by hardware.

Note: When waking up from HALT mode, if the SPI remains in Slave mode, it is recommended to perform an extra communications cycle to bring

SPI interrupt events cause the device to exit from WAIT mode.

SPI registers are frozen. In HALT mode, the SPI is inactive. SPI operation resumes when the device is woken up by an interrupt with “exit from HALT mode” capability. The data received is subsequently read from the SPIDR register when the software is running (interrupt vector fetching). If several data are received before the wakeup event, then an overrun error is generated. This error can be detected after the fetch of the interrupt routine that woke up the Device.

the SPI from HALT mode state to normal state. If the SPI exits from Slave mode, it returns to normal state immediately.

Caution: The SPI can wake up the device from HALT mode only if the Slave Select signal (exter-

pin or the SSI bit in the SPICSR register) is

nal SS low when the device enters HALT mode. So, if Slave selection is configured as external (see Sec-

tion 11.4.3.2), make sure the master drives a low

level on the SS

pin when the slave enters HALT

mode.

11.4.7 Interrupts

Interrupt Event

SPI End of Transfer Event

Master Mode Fault Event

Overrun Error OVR

Event

Flag

SPIF

MODF

Enable

Control

Bit

SPIE Yes

Exit from Wait

Exit

from

Halt

Yes

Note: The SPI interrupt events are connected to the same interrupt vector (see Interrupts chapter). They generate an interrupt if the corresponding Enable Control Bit is set and the interrupt mask in the CC register is reset (RIM instruction).

86/173

11.4.8 Register Description SPI CONTROL REGISTER (SPICR)

Read/Write Reset Value: 0000 xxxx (0xh)

SPIE SPE SPR2 MSTR CPOL CPHA SPR1 SPR0

Bit 3 = CPOL Clock Polarity This bit is set and cleared by software. This bit determines the idle state of the serial Clock. The CPOL bit affects both the master and slave modes. 0: SCK pin has a low level idle state 1: SCK pin has a high level idle state

Note: If CPOL is changed at the communication byte boundaries, the SPI must be disabled by re-

Bit 7 = SPIE Serial Peripheral Interrupt Enable

setting the SPE bit.

This bit is set and cleared by software. 0: Interrupt is inhibited 1: An SPI interrupt is generated whenever an End

of Transfer event, Master Mode Fault or Overrun error occurs (SPIF = 1, MODF = 1 or OVR = 1 in the SPICSR register)

Bit 2 = CPHA Clock Phase This bit is set and cleared by software. 0: The first clock transition is the first data capture

edge.

1: The second clock transition is the first capture

edge.

Bit 6 = SPE Serial Peripheral Output Enable This bit is set and cleared by software. It is also

Note: The slave must have the same CPOL and CPHA settings as the master.

cleared by hardware when, in master mode,

=0 (see Section 11.4.5.1 Master Mode Fault

(MODF)). The SPE bit is cleared by reset, so the

SPI peripheral is not initially connected to the external pins. 0: I/O pins free for general purpose I/O 1: SPI I/O pin alternate functions enabled

Bits 1:0 = SPR[1:0] Serial Clock Frequency These bits are set and cleared by software. Used with the SPR2 bit, they select the baud rate of the SPI serial clock SCK output by the SPI in master mode.

Note: These 2 bits have no effect in slave mode.

Bit 5 = SPR2 Divider Enable This bit is set and cleared by software and is cleared by reset. It is used with the SPR[1:0] bits to set the baud rate. Refer to Table 18 SPI Master

Mode SCK Frequency.

0: Divider by 2 enabled 1: Divider by 2 disabled

Note: This bit has no effect in slave mode.

Bit 4 = MSTR Master Mode

Table 18. SPI Master Mode SCK Frequency

Serial Clock SPR2 SPR1 SPR0

/4 1

CPU

/16 1

CPU

/32 1

CPU

/64

CPU

/128 1

CPU

This bit is set and cleared by software. It is also cleared by hardware when, in master mode,

=0 (see Section 11.4.5.1 Master Mode Fault

(MODF)).

0: Slave mode 1: Master mode. The function of the SCK pin

changes from an input to an output and the functions of the MISO and MOSI pins are reversed.

ST7LITE3xF2

87/173

ST7LITE3xF2

SERIAL PERIPHERAL INTERFACE (cont’d) SPI CONTROL/STATUS REGISTER (SPICSR)

Read/Write (some bits Read Only) Reset Value: 0000 0000 (00h)

SPIF WCOL OVR MODF - SOD SSM SSI

Bit 2 = SOD SPI Output Disable This bit is set and cleared by software. When set, it disables the alternate function of the SPI output (MOSI in master mode / MISO in slave mode) 0: SPI output enabled (if SPE = 1) 1: SPI output disabled

Bit 7 = SPIF Serial Peripheral Data Transfer Flag

(Read only)

This bit is set by hardware when a transfer has been completed. An interrupt is generated if SPIE = 1 in the SPICR register. It is cleared by a software sequence (an access to the SPICSR register followed by a write or a read to the SPIDR register).

0: Data transfer is in progress or the flag has been

cleared.

1: Data transfer between the device and an exter-

nal device has been completed.

Note: While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR register is read.

Bit 6 = WCOL Write Collision status (Read only) This bit is set by hardware when a write to the SPIDR register is done during a transmit sequence. It is cleared by a software sequence (see

Figure 53).

0: No write collision occurred 1: A write collision has been detected

Bit 5 = OVR SPI Overrun error (Read only) This bit is set by hardware when the byte currently being received in the shift register is ready to be transferred into the SPIDR register while SPIF = 1 (See Section 11.4.5.2). An interrupt is generated if SPIE = 1 in the SPICR register. The OVR bit is cleared by software reading the SPICSR register. 0: No overrun error 1: Overrun error detected

Bit 4 = MODF Mode Fault flag (Read only) This bit is set by hardware when the SS

pin is pulled low in master mode (see Section 11.4.5.1

Master Mode Fault (MODF)). An SPI interrupt can

be generated if SPIE = 1 in the SPICR register. This bit is cleared by a software sequence (An access to the SPICSR register while MODF = 1 followed by a write to the SPICR register). 0: No master mode fault detected 1: A fault in master mode has been detected

Bit 3 = Reserved, must be kept cleared.

Bit 1 = SSM SS

Management

This bit is set and cleared by software. When set, it disables the alternate function of the SPI SS

and uses the SSI bit value instead. See Section

11.4.3.2 Slave Select Management.

0: Hardware management (SS

managed by exter-

nal pin)

1: Software management (internal SS

trolled by SSI bit. External SS

signal con-

pin free for gener-

al-purpose I/O)

Bit 0 = SSI SS

Internal Mode

This bit is set and cleared by software. It acts as a ‘chip select’ by controlling the level of the SS

slave select signal when the SSM bit is set. 0: Slave selected 1: Slave deselected

SPI DATA I/O REGISTER (SPIDR)

Read/Write Reset Value: Undefined

D7 D6 D5 D4 D3 D2 D1 D0

The SPIDR register is used to transmit and receive data on the serial bus. In a master device, a write to this register will initiate transmission/reception of another byte.

Notes: During the last clock cycle the SPIF bit is set, a copy of the received data byte in the shift register is moved to a buffer. When the user reads the serial peripheral data I/O register, the buffer is actually being read.

While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR register is read.

Warning: A write to the SPIDR register places data directly into the shift register for transmission.

A read to the SPIDR register returns the value located in the buffer and not the content of the shift register (see Figure 48).

88/173

Table 19. SPI Register Map and Reset Values

ST7LITE3xF2

Address

(Hex.)

0031h

0032h

0033h

Label

SPIDR

Reset Value

SPICR

Reset Value

SPICSR

Reset Value

76543210

MSB

xxxxxxx

SPIE

SPIF

SPE

WCOL

SPR20MSTR0CPOLxCPHA

OVR0MODF

SOD

SPR1

SSM

LSB

SPR0

SSI

89/173

ST7LITE3xF2

11.5 LINSCI SERIAL COMMUNICATION INTERFACE (LIN MASTER/SLAVE)

11.5.1 Introduction

The Serial Communications Interface (SCI) offers a flexible means of full-duplex data exchange with external equipment requiring an industry standard NRZ asynchronous serial data format. The SCI offers a very wide range of baud rates using two baud rate generator systems.

The LIN-dedicated features support the LIN (Local Interconnect Network) protocol for both master and slave nodes.

This chapter is divided into SCI Mode and LIN mode sections. For information on general SCI communications, refer to the SCI mode section. For LIN applications, refer to both the SCI mode and LIN mode sections.

11.5.2 SCI Features

■ Full duplex, asynchronous communications

■ NRZ standard format (Mark/Space)

■ Independently programmable transmit and

receive baud rates up to 500K baud

■ Programmable data word length (8 or 9 bits)

■ Receive buffer full, Transmit buffer empty and

End of Transmission flags

■ 2 receiver wake-up modes:

– Address bit (MSB) – Idle line

■ Muting function for multiprocessor configurations

■ Separate enable bits for Transmitter and

Receiver

■ Overrun, Noise and Frame error detection

■ 6 interrupt sources

– Transmit data register empty – Transmission complete – Receive data register full – Idle line received – Overrun error – Parity interrupt

■ Parity control:

– Transmits parity bit – Checks parity of received data byte

■ Reduced power consumption mode

11.5.3 LIN Features

– LIN Master

– 13-bit LIN Synch Break generation

– LIN Slave

– Automatic Header Handling – Automatic baud rate resynchronization based

on recognition and measurement of the LIN Synch Field (for LIN slave nodes)

– Automatic baud rate adjustment (at CPU fre-

quency precision) – 11-bit LIN Synch Break detection capability – LIN Parity check on the LIN Identifier Field

(only in reception) – LIN Error management – LIN Header Timeout – Hot plugging support

90/173

LINSCI™ SERIAL COMMUNICATION INTERFACE (cont’d)

11.5.4 General Description

The interface is externally connected to another device by two pins:

– TDO: Transmit Data Output. When the transmit-

ter is disabled, the output pin returns to its I/O port configuration. When the transmitter is enabled and nothing is to be transmitted, the TDO pin is at high level.

– RDI: Receive Data Input is the serial data input.

Oversampling techniques are used for data recovery by discriminating between valid incoming data and noise.

Through these pins, serial data is transmitted and received as characters comprising:

– An Idle Line prior to transmission or reception – A start bit – A data word (8 or 9 bits) least significant bit first – A Stop bit indicating that the character is com-

plete

This interface uses three types of baud rate generator:

– A conventional type for commonly-used baud

rates

– An extended type with a prescaler offering a very

wide range of baud rates even with non-standard oscillator frequencies

– A LIN baud rate generator with automatic resyn-

chronization

ST7LITE3xF2

91/173

ST7LITE3xF2

LINSCI™ SERIAL COMMUNICATION INTERFACE (SCI Mode) (cont’d)

Figure 55. SCI Block Diagram (in Conventional Baud Rate Generator Mode)

TDO

RDI

Write

Transmit Data Register (TDR)

Transmit Shift Register

TRANSMIT

CONTROL

SCICR2

WAKE

UNIT

Read

Received Data Register (RDR)

Receive Shift Register

SCID

SBKRWURETEILIERIETCIETIE

M WAKE

TDRE

RECEIVER

CONTROL

(DATA REGISTER) SCIDR

SCICR1

PCE

PS PIE

OR/

RDRF

IDLE

LHE

RECEIVER

CLOCK

SCISR

FE PE

92/173

SCI

INTERRUPT

CONTROL

TRANSMITTER

CLOCK

CPU

/16

/PR

TRANSMITTER RATE

CONTROL

SCIBRR

SCP1

CONVENTIONAL BAUD RATE GENERATOR

SCP0

SCT2

SCT1 SCT0 SCR2 SCR1SCR0

RECEIVER RATE CONTROL

LINSCI™ SERIAL COMMUNICATION INTERFACE (SCI Mode) (cont’d)

11.5.5 SCI Mode - Functional Description Conventional Baud Rate Generator Mode

The block diagram of the Serial Control Interface in conventional baud rate generator mode is shown in Figure 55.

It uses four registers: – 2 control registers (SCICR1 and SCICR2) – A status register (SCISR) – A baud rate register (SCIBRR)

Extended Prescaler Mode

Two additional prescalers are available in extend-

11.5.5.1 Serial Data Format

Word length may be selected as being either 8 or 9 bits by programming the M bit in the SCICR1 register (see Figure 56).

The TDO pin is in low state during the start bit. The TDO pin is in high state during the stop bit. An Idle character is interpreted as a continuous

logic high level for 10 (or 11) full bit times. A Break character is a character with a sufficient

number of low level bits to break the normal data format followed by an extra “1” bit to acknowledge the start bit.

ed prescaler mode. They are shown in Figure 57. – An extended prescaler receiver register (SCIER-

PR)

– An extended prescaler transmitter register (SCI-

ETPR)

Figure 56. Word Length Programming

9-bit Word length (M bit is set)

Possible

Start

Bit

Bit0

Data Character

Bit2

Bit1

Bit3

Bit4

Bit5

Bit6

Bit7

Parity

Bit

Bit8

Next Data Character

Next Start

Stop

Bit

ST7LITE3xF2

Idle Line

Break Character

8-bit Word length (M bit is reset)

Data Character

Start

Bit

Bit0

Bit1

Bit2

Bit3

Idle Line

Break Character

Bit4

Bit5

Bit6

Possible

Parity

Bit

Bit7

Stop

Bit

Start

Bit

Start

Extra

’1’

Bit

Next Data Character

Start

Bit

Start

Bit

Start

Extra

’1’

Bit

93/173

ST7LITE3xF2

LINSCI™ SERIAL COMMUNICATION INTERFACE (SCI Mode) (cont’d)

11.5.5.2 Transmitter

The transmitter can send data words of either 8 or 9 bits depending on the M bit status. When the M bit is set, word length is 9 bits and the 9th bit (the MSB) has to be stored in the T8 bit in the SCICR1 register.

Character Transmission

During an SCI transmission, data shifts out least significant bit first on the TDO pin. In this mode, the SCIDR register consists of a buffer (TDR) between the internal bus and the transmit shift register (see Figure 55).

Procedure

– Select the M bit to define the word length. – Select the desired baud rate using the SCIBRR

and the SCIETPR registers.

– Set the TE bit to send a preamble of 10 (M = 0)

or 11 (M = 1) consecutive ones (Idle Line) as first transmission.

– Access the SCISR register and write the data to

send in the SCIDR register (this sequence clears the TDRE bit). Repeat this sequence for each data to be transmitted.

Clearing the TDRE bit is always performed by the following software sequence:

1. An access to the SCISR register

2. A write to the SCIDR register The TDRE bit is set by hardware and it indicates: – The TDR register is empty. – The data transfer is beginning. – The next data can be written in the SCIDR regis-

ter without overwriting the previous data.

This flag generates an interrupt if the TIE bit is set and the I[|1:0] bits are cleared in the CCR register.

When a transmission is taking place, a write instruction to the SCIDR register stores the data in the TDR register and which is copied in the shift register at the end of the current transmission.

When no transmission is taking place, a write instruction to the SCIDR register places the data directly in the shift register, the data transmission starts, and the TDRE bit is immediately set.

When a character transmission is complete (after the stop bit) the TC bit is set and an interrupt is generated if the TCIE is set and the I[1:0] bits are cleared in the CCR register.

Clearing the TC bit is performed by the following software sequence:

1. An access to the SCISR register

2. A write to the SCIDR register Note: The TDRE and TC bits are cleared by the

same software sequence.

Break Characters

Setting the SBK bit loads the shift register with a break character. The break character length depends on the M bit (see Figure 56).

As long as the SBK bit is set, the SCI sends break characters to the TDO pin. After clearing this bit by software, the SCI inserts a logic 1 bit at the end of the last break character to guarantee the recognition of the start bit of the next character.

Idle Line

Setting the TE bit drives the SCI to send a preamble of 10 (M = 0) or 11 (M = 1) consecutive ‘1’s (idle line) before the first character.

In this case, clearing and then setting the TE bit during a transmission sends a preamble (idle line) after the current word. Note that the preamble duration (10 or 11 consecutive ‘1’s depending on the M bit) does not take into account the stop bit of the previous character.

Note: Resetting and setting the TE bit causes the data in the TDR register to be lost. Therefore the best time to toggle the TE bit is when the TDRE bit is set, that is, before writing the next byte in the SCIDR.

94/173

LINSCI™ SERIAL COMMUNICATION INTERFACE (SCI Mode) (cont’d)

11.5.5.3 Receiver

The SCI can receive data words of either 8 or 9 bits. When the M bit is set, word length is 9 bits and the MSB is stored in the R8 bit in the SCICR1 register.

Character reception

During a SCI reception, data shifts in least significant bit first through the RDI pin. In this mode, the SCIDR register consists or a buffer (RDR) between the internal bus and the received shift register (see Figure 55).

Procedure

– Select the M bit to define the word length. – Select the desired baud rate using the SCIBRR

and the SCIERPR registers.

– Set the RE bit, this enables the receiver which

begins searching for a start bit. When a character is received: – The RDRF bit is set. It indicates that the content

of the shift register is transferred to the RDR. – An interrupt is generated if the RIE bit is set and

the I[1:0] bits are cleared in the CCR register. – The error flags can be set if a frame error, noise

or an overrun error has been detected during re-

ception. Clearing the RDRF bit is performed by the following

software sequence done by:

1. An access to the SCISR register

2. A read to the SCIDR register. The RDRF bit must be cleared before the end of the

reception of the next character to avoid an overrun error.

Idle Line

When an idle line is detected, there is the same procedure as a data received character plus an interrupt if the ILIE bit is set and the I[|1:0] bits are cleared in the CCR register.

Overrun Error

An overrun error occurs when a character is received when RDRF has not been reset. Data can not be transferred from the shift register to the TDR register as long as the RDRF bit is not cleared.

When an overrun error occurs:

– The OR bit is set. – The RDR content will not be lost. – The shift register will be overwritten. – An interrupt is generated if the RIE bit is set and

the I[|1:0] bits are cleared in the CCR register.

The OR bit is reset by an access to the SCISR register followed by a SCIDR register read operation.

Noise Error

Oversampling techniques are used for data recovery by discriminating between valid incoming data and noise.

When noise is detected in a character: – The NF bit is set at the rising edge of the RDRF

bit.

– Data is transferred from the Shift register to the

SCIDR register.

– No interrupt is generated. However this bit rises

at the same time as the RDRF bit which itself generates an interrupt.

The NF bit is reset by a SCISR register read operation followed by a SCIDR register read operation.

Framing Error

A framing error is detected when: – The stop bit is not recognized on reception at the

expected time, following either a desynchroniza-

tion or excessive noise. – A break is received. When the framing error is detected: – the FE bit is set by hardware – Data is transferred from the Shift register to the

SCIDR register. – No interrupt is generated. However this bit rises

at the same time as the RDRF bit which itself

generates an interrupt. The FE bit is reset by a SCISR register read oper-

ation followed by a SCIDR register read operation.

Break Character

– When a break character is received, the SCI

handles it as a framing error. To differentiate a

break character from a framing error, it is neces-

sary to read the SCIDR. If the received value is

00h, it is a break character. Otherwise it is a

framing error.

ST7LITE3xF2

95/173

ST7LITE3xF2

LINSCI™ SERIAL COMMUNICATION INTERFACE (SCI Mode) (cont’d)

11.5.5.4 Conventional Baud Rate Generation

The baud rates for the receiver and transmitter (Rx and Tx) are set independently and calculated as follows:

(16

CPU

PR)*RR

Tx =

(16

CPU

PR)*TR

Rx =

with: PR = 1, 3, 4 or 13 (see SCP[1:0] bits) TR = 1, 2, 4, 8, 16, 32, 64,128 (see SCT[2:0] bits) RR = 1, 2, 4, 8, 16, 32, 64,128 (see SCR[2:0] bits) All these bits are in the SCIBRR register. Example: If f

is 8 MHz (normal mode) and if

CPU

PR = 13 and TR = RR = 1, the transmit and receive baud rates are 38400 baud.

Note: The baud rate registers MUST NOT be changed while the transmitter or the receiver is enabled.

11.5.5.5 Extended Baud Rate Generation

The extended prescaler option gives a very fine tuning on the baud rate, using a 255 value prescaler, whereas the conventional Baud Rate Generator retains industry standard software compatibility.

The extended baud rate generator block diagram is described in Figure 57.

The output clock rate sent to the transmitter or to the receiver will be the output from the 16 divider divided by a factor ranging from 1 to 255 set in the SCIERPR or the SCIETPR register.

Note: The extended prescaler is activated by setting the SCIETPR or SCIERPR register to a value other than zero. The baud rates are calculated as follows:

Tx =

CPU

ETPR*(PR*TR)

with: ETPR = 1, ..., 255 (see SCIETPR register) ERPR = 1, ..., 255 (see SCIERPR register)

Rx =

CPU

ERPR*(PR*RR)

96/173

LINSCI™ SERIAL COMMUNICATION INTERFACE (SCI Mode) (cont’d)

Figure 57. SCI Baud Rate and Extended Prescaler Block Diagram

EXTENDED PRESCALER TRANSMITTER RATE CONTROL

SCIETPR

EXTENDED TRANSMITTER PRESCALER REGISTER

SCIERPR

EXTENDED RECEIVER PRESCALER REGISTER

EXTENDED PRESCALER RECEIVER RATE CONTROL

EXTENDED PRESCALER

ST7LITE3xF2

TRANSMITTER

CLOCK

RECEIVER

CLOCK

CPU

/16

/PR

TRANSMITTER RATE

CONTROL

SCIBRR

SCP1

SCP0

SCT2

SCT1 SCT0

RECEIVER RATE

SCR2 SCR1SCR0

CONTROL

CONVENTIONAL BAUD RATE GENERATOR

97/173

ST7LITE3xF2

LINSCI™ SERIAL COMMUNICATION INTERFACE (SCI Mode) (cont’d)

11.5.5.6 Receiver Muting and Wake-up Feature

In multiprocessor configurations it is often desirable that only the intended message recipient should actively receive the full message contents, thus reducing redundant SCI service overhead for all non-addressed receivers.

The non-addressed devices may be placed in sleep mode by means of the muting function.

Setting the RWU bit by software puts the SCI in sleep mode:

All the reception status bits can not be set. All the receive interrupts are inhibited. A muted receiver may be woken up in one of the

following ways: – by Idle Line detection if the WAKE bit is reset, – by Address Mark detection if the WAKE bit is set.

Idle Line Detection

Receiver wakes up by Idle Line detection when the Receive line has recognized an Idle Line. Then the RWU bit is reset by hardware but the IDLE bit is not set.

This feature is useful in a multiprocessor system when the first characters of the message determine the address and when each message ends by an idle line: As soon as the line becomes idle, every receivers is waken up and analyse the first characters of the message which indicates the addressed receiver. The receivers which are not addressed set RWU bit to enter in mute mode. Consequently, they will not treat the next characters constituting the next part of the message. At the end of the message, an idle line is sent by the transmitter: this wakes up every receivers which are ready to analyse the addressing characters of the new message.

In such a system, the inter-characters space must be smaller than the idle time.

Address Mark Detection

Receiver wakes up by Address Mark detection when it received a “1” as the most significant bit of a word, thus indicating that the message is an address. The reception of this particular word wakes up the receiver, resets the RWU bit and sets the RDRF bit, which allows the receiver to receive this word normally and to use it as an address word.

This feature is useful in a multiprocessor system when the most significant bit of each character (except for the break character) is reserved for Address Detection. As soon as the receivers re-

ceived an address character (most significant bit = ’1’), the receivers are waken up. The receivers which are not addressed set RWU bit to enter in mute mode. Consequently, they will not treat the next characters constituting the next part of the message.

11.5.5.7 Parity Control

Hardware byte Parity control (generation of parity bit in transmission and parity checking in reception) can be enabled by setting the PCE bit in the SCICR1 register. Depending on the character format defined by the M bit, the possible SCI character formats are as listed in Table 20.

Note: In case of wake-up by an address mark, the MSB bit of the data is taken into account and not the parity bit

Table 20. Character Formats

M bit PCE bit Character format

0 | SB | 8 bit data | STB |

1 | SB | 7-bit data | PB | STB |

0 | SB | 9-bit data | STB | 1 | SB | 8-bit data | PB | STB |

Legend: SB = Start Bit, STB = Stop Bit, PB = Parity Bit

Even parity: The parity bit is calculated to obtain an even number of “1s” inside the character made of the 7 or 8 LSB bits (depending on whether M is equal to 0 or 1) and the parity bit.

Example: data = 00110101; 4 bits set => parity bit will be 0 if even parity is selected (PS bit = 0).

Odd parity: The parity bit is calculated to obtain an odd number of “1s” inside the character made of the 7 or 8 LSB bits (depending on whether M is equal to 0 or 1) and the parity bit.

Example: data = 00110101; 4 bits set => parity bit will be 1 if odd parity is selected (PS bit = 1).

Transmission mode: If the PCE bit is set then the MSB bit of the data written in the data register is not transmitted but is changed by the parity bit.

Reception mode: If the PCE bit is set then the interface checks if the received data byte has an even number of “1s” if even parity is selected (PS = 0) or an odd number of “1s” if odd parity is selected (PS = 1). If the parity check fails, the PE flag is set in the SCISR register and an interrupt is generated if PCIE is set in the SCICR1 register.

98/173

LINSCI™ SERIAL COMMUNICATION INTERFACE (SCI Mode) (cont’d)

11.5.6 Low Power Modes 11.5.7 Interrupts

Mode Description

Interrupt Event

Transmit Data Register Empty

Transmission Complete

Received Data Ready to be Read

Overrun Error or LIN Synch Error Detected

Idle Line Detected IDLE ILIE Parity Error PE PIE LIN Header Detection LHDF LHIE

WAIT

HALT

No effect on SCI. SCI interrupts cause the device to exit from Wait mode.

SCI registers are frozen. In Halt mode, the SCI stops transmitting/receiving until Halt mode is exited.

The SCI interrupt events are connected to the same interrupt vector (see Interrupts chapter).

These events generate an interrupt if the corresponding Enable Control Bit is set and the interrupt mask in the CC register is reset (RIM instruction).

Enable

Event

Control

Flag

TDRE TIE

TC TCIE

RDRF

OR/ LHE

Bit

RIE

ST7LITE3xF2

Exit from Wait

Exit

from

Halt

Yes No

99/173

ST7LITE3xF2

LINSCI™ SERIAL COMMUNICATION INTERFACE (SCI Mode) (cont’d)

11.5.8 SCI Mode Register Description STATUS REGISTER (SCISR)

Read Only Reset Value: 1100 0000 (C0h)

TDRE TC RDRF IDLE

OR1)NF1)FE1)PE

Bit 7 = TDRE Transmit data register empty This bit is set by hardware when the content of the TDR register has been transferred into the shift register. An interrupt is generated if the TIE = 1 in the SCICR2 register. It is cleared by a software sequence (an access to the SCISR register followed by a write to the SCIDR register). 0: Data is not transferred to the shift register 1: Data is transferred to the shift register

Bit 6 = TC Transmission complete This bit is set by hardware when transmission of a character containing Data is complete. An interrupt is generated if TCIE = 1 in the SCICR2 register. It is cleared by a software sequence (an access to the SCISR register followed by a write to the SCIDR register). 0: Transmission is not complete 1: Transmission is complete

Note: TC is not set after the transmission of a Preamble or a Break.

Bit 5 = RDRF Received data ready flag This bit is set by hardware when the content of the RDR register has been transferred to the SCIDR register. An interrupt is generated if RIE = 1 in the SCICR2 register. It is cleared by a software sequence (an access to the SCISR register followed by a read to the SCIDR register). 0: Data is not received 1: Received data is ready to be read

Bit 3 = OR Overrun error The OR bit is set by hardware when the word cur-

rently being received in the shift register is ready to be transferred into the RDR register whereas RDRF is still set. An interrupt is generated if RIE = 1 in the SCICR2 register. It is cleared by a software sequence (an access to the SCISR register followed by a read to the SCIDR register). 0: No Overrun error 1: Overrun error detected

Note: When this bit is set, RDR register contents will not be lost but the shift register will be overwritten.

Bit 2 = NF Character Noise flag This bit is set by hardware when noise is detected on a received character. It is cleared by a software sequence (an access to the SCISR register followed by a read to the SCIDR register). 0: No noise 1: Noise is detected

Note: This bit does not generate interrupt as it appears at the same time as the RDRF bit which itself generates an interrupt.

Bit 1 = FE Framing error This bit is set by hardware when a desynchronization, excessive noise or a break character is detected. It is cleared by a software sequence (an access to the SCISR register followed by a read to the SCIDR register). 0: No Framing error 1: Framing error or break character detected

Note: This bit does not generate an interrupt as it appears at the same time as the RDRF bit which itself generates an interrupt. If the word currently being transferred causes both a frame error and an overrun error, it will be transferred and only the OR bit will be set.

Bit 4 = IDLE Idle line detected This bit is set by hardware when an Idle Line is detected. An interrupt is generated if the ILIE = 1 in the SCICR2 register. It is cleared by a software sequence (an access to the SCISR register followed by a read to the SCIDR register). 0: No Idle Line is detected 1: Idle Line is detected

Note: The IDLE bit will not be set again until the RDRF bit has been set itself (that is, a new idle line occurs).

100/173

Bit 0 = PE Parity error This bit is set by hardware when a byte parity error occurs (if the PCE bit is set) in receiver mode. It is cleared by a software sequence (a read to the status register followed by an access to the SCIDR data register). An interrupt is generated if PIE = 1 in the SCICR1 register. 0: No parity error 1: Parity error detected

ST ST7LITE30F2, ST7LITE35F2, ST7LITE39F2 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

1 INTRODUCTION

2 PIN DESCRIPTION

3 REGISTER & MEMORY MAP

4 FLASH PROGRAM MEMORY

4.1 Introduction

4.2 Main Features

4.3 PROGRAMMING MODES

4.4 ICC INTERFACE

4.5 Memory Protection

4.6 Related Documentation

4.7 Register Description

5 DATA EEPROM

5.1 INTRODUCTION

5.2 MAIN FEATURES

5.3 MEMORY ACCESS

5.4 POWER SAVING MODES

5.5 ACCESS ERROR HANDLING

5.6 Data EEPROM Read-out Protection

5.7 REGISTER DESCRIPTION

6 CENTRAL PROCESSING UNIT

6.1 INTRODUCTION

6.2 MAIN FEATURES

6.3 CPU REGISTERS

7 SUPPLY, RESET AND CLOCK MANAGEMENT

7.1 INTERNAL RC OSCILLATOR ADJUSTMENT

7.2 PHASE LOCKED LOOP

7.3 REGISTER DESCRIPTION

7.4 MULTI-OSCILLATOR (MO)

7.5 RESET SEQUENCE MANAGER (RSM)

7.6 SYSTEM INTEGRITY MANAGEMENT (SI)

8 INTERRUPTS

8.1 NON MASKABLE SOFTWARE INTERRUPT

8.2 EXTERNAL INTERRUPTS

8.3 PERIPHERAL INTERRUPTS

9 POWER SAVING MODES

9.1 INTRODUCTION

9.2 SLOW MODE

9.3 WAIT MODE

9.4 HALT MODE

9.5 ACTIVE-HALT MODE

9.6 AUTO WAKE UP FROM HALT MODE

10 I/O PORTS

10.1 INTRODUCTION

10.2 FUNCTIONAL DESCRIPTION

10.3 I/O PORT IMPLEMENTATION

10.4 UNUSED I/O PINS

10.5 LOW POWER MODES

10.6 INTERRUPTS

11 ON-CHIP PERIPHERALS

11.1 WATCHDOG TIMER (WDG)

11.2 DUAL 12-BIT AUTORELOAD TIMER 3 (AT3)

11.3 LITE TIMER 2 (LT2)

11.4 SERIAL PERIPHERAL INTERFACE (SPI)

11.5 LINSCI SERIAL COMMUNICATION INTERFACE (LIN MASTER/SLAVE)