ST ST7LITE2 User Manual

July 2006 1/133

Rev. 4

ST7LITE2

8-BIT MICROCONTROLLER WITH SINGLE VOLTAGE FLASH

MEMORY, DATA EEPROM, ADC, TIMERS, SPI

■ Memories

– 8 Kbytes single voltage Flash Program mem-

ory with read-out protection, In-Circuit Pro-

gramming and In-Application programming

(ICP and IAP). 10K write/erase cycles guar-

anteed, data retention: 20 years at 55°C.

– 384 bytes RAM

■ Clock, Reset and Supply Management

– Enhanced reset system

– Enhanced low voltage supervisor (LVD) for

main supply and an auxiliary voltage detector

(AVD) with interrupt capability for implement-

ing safe power-down procedures

– Clock sources: Internal 1% RC oscillator,

crystal/ceramic resonator or external clock

– Internal 32-MHz input clock for Auto-reload

timer

– Optional x4 or x8 PLL for 4 or 8 MHz internal

clock

– Five Power Saving Modes: Halt, Active-Halt,

Wait and Slow, Auto Wake Up From Halt

■ I/O Ports

– Up to 15 multifunctional bidirectional I/O lines

–7 high sink outputs

■ 4 Timers

– Configurable Watchdog Timer

– Two 8-bit Lite Timers with prescaler,

1 realtime base and 1 input capture

– One 12-bit Auto-reload Timer with 4 PWM

outputs, input capture and output compare

functions

■ 1 Communication Interface

– SPI synchronous serial interface

■ Interrupt Management

– 10 interrupt vectors plus TRAP and RESET

– 15 external interrupt lines (on 4 vectors)

■ A/D Converter

– 7 input channels

– Fixed gain Op-amp

– 13-bit resolution for 0 to 430 mV (@ 5V V

)

– 10-bit resolution for 430 mV to 5V (@ 5V V

)

■ Instruction Set

– 8-bit data manipulation

– 63 basic instructions with illegal opcode de-

tection

– 17 main addressing modes

– 8 x 8 unsigned multiply instructions

■ Development Tools

– Full hardware/software development package

– DM (Debug Module)

Device Summary

DIP20

SO20

300”

Features ST7LITE20 ST7LITE25 ST7LITE29

Program memory - bytes 8K

RAM (stack) - bytes 384 (128)

Data EEPROM - bytes - - 256

Peripherals

Lite Timer with Watchdog,

Autoreload Timer, SPI,

10-bit ADC with Op-Amp

Lite Timer with Watchdog,

Autoreload Timer with 32-MHz input clock,

SPI, 10-bit ADC with Op-Amp

Operating Supply 2.4V to 5.5V

CPU Frequency

Up to 8Mhz

(w/ ext OSC up to 16MHz)

Up to 8Mhz (w/ ext OSC up to 16MHz

and int 1MHz RC 1% PLLx8/4MHz)

Operating Temperature -40°C to +85°C

Packages SO20 300”, DIP20

Table of Contents

133

2/133

1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

3 REGISTER & MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

4 FLASH PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4.3 PROGRAMMING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4.4 ICC INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4.5 MEMORY PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

4.6 RELATED DOCUMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

4.7 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5 DATA EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5.3 MEMORY ACCESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

5.4 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5.5 ACCESS ERROR HANDLING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5.6 DATA EEPROM READ-OUT PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5.7 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

6 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

6.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

6.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

6.3 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

7 SUPPLY, RESET AND CLOCK MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

7.1 INTERNAL RC OSCILLATOR ADJUSTMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

7.2 PHASE LOCKED LOOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

7.3 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

7.4 MULTI-OSCILLATOR (MO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

7.5 RESET SEQUENCE MANAGER (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

7.6 SYSTEM INTEGRITY MANAGEMENT (SI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

8 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

8.1 NON MASKABLE SOFTWARE INTERRUPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

8.2 EXTERNAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

8.3 PERIPHERAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

9 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

9.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

9.2 SLOW MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

9.3 WAIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

9.4 HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

9.5 ACTIVE-HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

9.6 AUTO WAKE UP FROM HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

10 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

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10.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

10.2 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

10.3 I/O PORT IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

10.4 UNUSED I/O PINS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

10.5 LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

10.6 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

10.7 DEVICE-SPECIFIC I/O PORT CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

11 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

11.1 WATCHDOG TIMER (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

11.2 12-BIT AUTORELOAD TIMER 2 (AT2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

11.3 LITE TIMER 2 (LT2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

11.4 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

11.5 10-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

12 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

12.1 ST7 ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

12.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

13 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

13.1 PARAMETER CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

13.2 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

13.3 OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

13.4 SUPPLY CURRENT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

13.5 CLOCK AND TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

13.6 MEMORY CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

13.7 EMC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

13.8 I/O PORT PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

13.9 CONTROL PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

13.10 COMMUNICATION INTERFACE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . 113

13.11 10-BIT ADC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

14 PACKAGE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

14.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

14.2 SOLDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

15 DEVICE CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

15.1 OPTION BYTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

15.2 DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE . . . . 124

15.3 DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

15.4 ST7 APPLICATION NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

16 IMPORTANT NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

16.1 EXECUTION OF BTJX INSTRUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

16.2 ADC CONVERSION SPURIOUS RESULTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

16.3 A/ D CONVERTER ACCURACY FOR FIRST CONVERSION . . . . . . . . . . . . . . . . . . . 130

16.4 NEGATIVE INJECTION IMPACT ON ADC ACCURACY . . . . . . . . . . . . . . . . . . . . . . . 130

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133

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16.5 CLEARING ACTIVE INTERRUPTS OUTSIDE INTERRUPT ROUTINE . . . . . . . . . . . . 130

16.6 USING PB4 AS EXTERNAL INTERRUPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

16.7 TIMEBASE 2 INTERRUPT IN SLOW MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

17 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

To obtain the most recent version of this datasheet,

please check at www.st.com>products>technical literature>datasheet

Please also pay special attention to the Section “IMPORTANT NOTES” on page 130.

ST7LITE2

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1 INTRODUCTION

The ST7LITE2 is a member of the ST7 microcon-

troller family. All ST7 devices are based on a com-

mon industry-standard 8-bit core, featuring an en-

hanced instruction set.

The ST7LITE2 features FLASH memory with

byte-by-byte In-Circuit Programming (ICP) and In-

Application Programming (IAP) capability.

Under software control, the ST7LITE2 device can

be placed in WAIT, SLOW, or HALT mode, reduc-

ing power consumption when the application is in

idle or standby state.

The enhanced instruction set and addressing

modes of the ST7 offer both power and flexibility to

software developers, enabling the design of highly

efficient and compact application code. In addition

to standard 8-bit data management, all ST7 micro-

controllers feature true bit manipulation, 8x8 un-

signed multiplication and indirect addressing

modes.

For easy reference, all parametric data are located

in section 13 on page 91.

The devices feature an on-chip Debug Module

(DM) to support in-circuit debugging (ICD). For a

description of the DM registers, refer to the ST7

ICC Protocol Reference Manual.

Figure 1. General Block Diagram

8-BIT CORE

ALU

ADDRESS AND DATA BUS

OSC1

OSC2

RESET

PORT A

Internal

CLOCK

CONTROL

RAM

(384 Bytes)

PA7:0

(8 bits)

POWER

SUPPLY

PROGRAM

(8K Bytes)

LVD

MEMORY

PLL x 8

Ext.

1MHz

PLL

Int.

1MHz

8-Bit

LITE TIMER 2

PORT B

SPI

PB6:0

(7 bits)

DATA EEPROM

(256 Bytes)

1% RC

OSC

16MHz

ADC

+ OpAmp

12-Bit

Auto-Reload

TIMER 2

CLKIN

/ 2

or PLL X4

8MHz -> 32MHz

WATCHDOG

Debug Module

ST7LITE2

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2 PIN DESCRIPTION

Figure 2. 20-Pin SO Package Pinout

Figure 3. 20-Pin DIP Package Pinout

AIN5/PB5

CLKIN/AIN4/PB4

MOSI/AIN3/PB3

MISO/AIN2/PB2

SCK/AIN1/PB1

/AIN0/PB0

OSC1/CLKIN

OSC2

PA5 (HS)/ATPWM3/ICCDATA

PA4 (HS)/ATPWM2

PA3 (HS)/ATPWM1

PA2 (HS)/ATPWM0

PA1 (HS)/ATIC

PA0 (HS)/LTIC

(HS) 20mA high sink capability

eix associated external interrupt vector

AIN6/PB6

PA7(HS)

PA6/MCO/ICCCLK/BREAK

RESET

ei3

ei2

ei0

ei1

MISO/AIN2/PB2

MOSI/AIN3/PB3

ATPWM2/PA4(HS)

ATPWM3/ICCDATA/PA5(HS)

MCO/ICCCLK/BREAK/PA6

PA7(HS)

AIN6/PB6

AIN5/PB5

SCK/AIN1/PB1

/AIN0/PB0

PA0(HS)/LTIC

OSC2

OSC1/CLKIN

RESET

(HS) 20mA high sink capability

eix associated external interrupt vector

ATPWM1/PA3(HS)

PA2(HS)/ATPWM0

PA1(HS)/ATIC

CLKIN/AIN4/PB4

ei3

ei2

ei1

ei0

ST7LITE2

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PIN DESCRIPTION (Cont’d)

Legend / Abbreviations for Table 1:

Type: I = input, O = output, S = supply

In/Output level: C

= CMOS 0.3V

/0.7V

with input trigger

Output level: HS = 20mA high sink (on N-buffer only)

Port and control configuration:

– Input: float = floating, wpu = weak pull-up, int = interrupt, ana = analog

– Output: OD = open drain, PP = push-pull

The RESET configuration of each pin is shown in bold which is valid as long as the device is in reset state.

Table 1. Device Pin Description

Pin No.

Pin Name

Type

Level Port / Control

Main

Function

(after reset)

Alternate Function

SO20

DIP20

Input

Output

Input Output

float

wpu

int

ana

116V

S Ground

217V

S Main power supply

3 18 RESET

I/O C

Top priority non maskable interrupt (active

low)

4 19 PB0/AIN0/SS

I/O C

ei3

XXXPort B0

ADC Analog Input 0 or SPI

Slave Select (active low)

Caution: No negative current

injection allowed on this pin.

For details, refer to section

13.2.2 on page 92

5 20 PB1/AIN1/SCK I/O C

X XXXPort B1

ADC Analog Input 1 or SPI Se-

rial Clock

Caution: No negative current

injection allowed on this pin.

For details, refer to section

13.2.2 on page 92

6 1 PB2/AIN2/MISO I/O C

X XXXPort B2

ADC Analog Input 2 or SPI

Master In/ Slave Out Data

7 2 PB3/AIN3/MOSI I/O C

ei2

XXXPort B3

ADC Analog Input 3 or SPI

Master Out / Slave In Data

8 3 PB4/AIN4/CLKIN I/O C

X XXXPort B4

ADC Analog Input 4 or Exter-

nal clock input

9 4 PB5/AIN5 I/O C

X XXXPort B5 ADC Analog Input 5

10 5 PB6/AIN6 I/O C

X XXXPort B6 ADC Analog Input 6

11 6 PA7 I/O C

HS X ei1 X X Port A7

ST7LITE2

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12 7

PA6 /MCO/

ICCCLK/BREAK

I/O C

X ei1 XXPort A6

Main Clock Output or In Circuit

Communication Clock or Ex-

ternal BREAK

Caution: During normal oper-

ation this pin must be pulled-

up, internally or externally (ex-

ternal pull-up of 10k mandato-

ry in noisy environment). This

is to avoid entering ICC mode

unexpectedly during a reset.

In the application, even if the

pin is configured as output,

any reset will put it back in in-

put pull-up

13 8

PA5 /ATPWM3/

ICCDATA

I/O C

HS X

ei1

XXPort A5

Auto-Reload Timer PWM3 or

In Circuit Communication Data

14 9 PA4/ATPWM2 I/O C

HS X XXPort A4 Auto-Reload Timer PWM2

15 10 PA3/ATPWM1 I/O C

HS X

ei0

XXPort A3 Auto-Reload Timer PWM1

16 11 PA2/ATPWM0 I/O C

HS X XXPort A2 Auto-Reload Timer PWM0

17 12 PA1/ATIC I/O C

HS X XXPort A1

Auto-Reload Timer Input Cap-

ture

18 13 PA0/LTIC I/O C

HS X XXPort A0 Lite Timer Input Capture

19 14 OSC2 O Resonator oscillator inverter output

20 15 OSC1/CLKIN I

Resonator oscillator inverter input or Exter-

nal clock input

Pin No.

Pin Name

Type

Level Port / Control

Main

Function

(after reset)

Alternate Function

SO20

DIP20

Input

Output

Input Output

float

wpu

int

ana

ST7LITE2

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3 REGISTER & MEMORY MAP

As shown in Figure 4, the MCU is capable of ad-

dressing 64K bytes of memories and I/O registers.

The available memory locations consist of 128

bytes of register locations, 384 bytes of RAM, 256

bytes of data EEPROM and 8 Kbytes of user pro-

gram memory. The RAM space includes up to 128

bytes for the stack from 180h to 1FFh.

The highest address bytes contain the user reset

and interrupt vectors.

The Flash memory contains two sectors (see Fig-

ure 4) mapped in the upper part of the ST7 ad-

dressing space so the reset and interrupt vectors

are located in Sector 0 (F000h-FFFFh).

The size of Flash Sector 0 and other device op-

tions are configurable by Option byte (refer to sec-

tion 15.1 on page 122).

IMPORTANT: Memory locations marked as “Re-

served” must never be accessed. Accessing a re-

seved area can have unpredictable effects on the

device.

Figure 4. Memory Map

0000h

RAM

Flash Memory

(8K)

Interrupt & Reset Vectors

HW Registers

0080h

007Fh

0FFFh

(see Table 2)

1000h

10FFh

FFE0h

FFFFh

(see Table 5)

0200h

Reserved

01FFh

Short Addressing

RAM (zero page)

128 Bytes Stack

0180h

01FFh

0080h

00FFh

(384 Bytes)

Data EEPROM

(256 Bytes)

E000h

1100h

DFFFh

Reserved

FFDFh

16-bit Addressing

RAM

0100h

017Fh

1 Kbyte

7 Kbytes

SECTOR 1

SECTOR 0

8K FLASH

FFFFh

FC00h

FBFFh

E000h

PROGRAM MEMORY

1000h

1001h

RCCR0

RCCR1

see section 7.1 on page 23

FFDEh

FFDFh

RCCR0

RCCR1

see section 7.1 on page 23

ST7LITE2

10/133

Table 2. Hardware Register Map

Address Block Register Label Register Name Reset Status Remarks

0000h

0001h

0002h

Port A

PADR

PADDR

PAOR

Port A Data Register

Port A Data Direction Register

Port A Option Register

FFh

00h

40h

R/W

0003h

0004h

0005h

Port B

PBDR

PBDDR

PBOR

Port B Data Register

Port B Data Direction Register

Port B Option Register

FFh

00h

R/W

0006h

0007h

Reserved Area (2 bytes)

0008h

0009h

000Ah

000Bh

000Ch

LITE

TIMER 2

LTCSR2

LTARR

LTCNTR

LTCSR1

LTICR

Lite Timer Control/Status Register 2

Lite Timer Auto-reload Register

Lite Timer Counter Register

Lite Timer Control/Status Register 1

Lite Timer Input Capture Register

00h

0X00 0000h

00h

R/W

Read Only

R/W

Read Only

000Dh

000Eh

000Fh

0010h

0011h

0012h

0013h

0014h

0015h

0016h

0017h

0018h

0019h

001Ah

001Bh

001Ch

001Dh

001Eh

001Fh

0020h

0021h

0022h

AUTO-

RELOAD

TIMER 2

ATCSR

CNTRH

CNTRL

ATRH

ATRL

PWMCR

PWM0CSR

PWM1CSR

PWM2CSR

PWM3CSR

DCR0H

DCR0L

DCR1H

DCR1L

DCR2H

DCR2L

DCR3H

DCR3L

ATICRH

ATICRL

TRANCR

BREAKCR

Timer Control/Status Register

Counter Register High

Counter Register Low

Auto-Reload Register High

Auto-Reload Register Low

PWM Output Control Register

PWM 0 Control/Status Register

PWM 1 Control/Status Register

PWM 2 Control/Status Register

PWM 3 Control/Status Register

PWM 0 Duty Cycle Register High

PWM 0 Duty Cycle Register Low

PWM 1 Duty Cycle Register High

PWM 1 Duty Cycle Register Low

PWM 2 Duty Cycle Register High

PWM 2 Duty Cycle Register Low

PWM 3 Duty Cycle Register High

PWM 3 Duty Cycle Register Low

Input Capture Register High

Input Capture Register Low

Transfer Control Register

Break Control Register

0X00 0000h

00h

01h

00h

R/W

Read Only

R/W

Read Only

R/W

0023h to

002Dh

Reserved area (11 bytes)

002Eh WDG WDGCR Watchdog Control Register 7Fh R/W

0002Fh FLASH FCSR Flash Control/Status Register 00h R/W

00030h EEPROM EECSR Data EEPROM Control/Status Register 00h R/W

0031h

0032h

0033h

SPI

SPIDR

SPICR

SPICSR

SPI Data I/O Register

SPI Control Register

SPI Control Status Register

xxh

0xh

00h

R/W

0034h

0035h

0036h

ADC

ADCCSR

ADCDRH

ADCDRL

A/D Control Status Register

A/D Data Register High

A/D Amplifier Control/Data Low Register

00h

xxh

0xh

R/W

Read Only

R/W

ST7LITE2

11/133

Legend: x=undefined, R/W=read/write

Notes:

1. The contents of the I/O port DR registers are readable only in output configuration. In input configura-

tion, the values of the I/O pins are returned instead of the DR register contents.

2. The bits associated with unavailable pins must always keep their reset value.

3. For a description of the Debug Module registers, see ICC reference manual.

0037h ITC EICR External Interrupt Control Register 00h R/W

0038h MCC MCCSR Main Clock Control/Status Register 00h R/W

0039h

003Ah

Clock and

Reset

RCCR

SICSR

RC oscillator Control Register

System Integrity Control/Status Register

FFh

0000 0XX0h

R/W

003Bh Reserved area (1 byte)

003Ch ITC EISR External Interrupt Selection Register 0Ch R/W

003Dh to

0048h

Reserved area (12 bytes)

0049h

004Ah

AWU

AWUPR

AWUCSR

AWU Prescaler Register

AWU Control/Status Register

FFh

00h

R/W

004Bh

004Ch

004Dh

004Eh

004Fh

0050h

DMCR

DMSR

DMBK1H

DMBK1L

DMBK2H

DMBK2L

DM Control Register

DM Status Register

DM Breakpoint Register 1 High

DM Breakpoint Register 1 Low

DM Breakpoint Register 2 High

DM Breakpoint Register 2 Low

00h

R/W

0051h to

007Fh

Reserved area (47 bytes)

Address Block Register Label Register Name Reset Status Remarks

ST7LITE2

12/133

4 FLASH PROGRAM MEMORY

4.1 Introduction

The ST7 single voltage extended Flash (XFlash) is

a non-volatile memory that can be electrically

erased and programmed either on a byte-by-byte

basis or up to 32 bytes in parallel.

The XFlash devices can be programmed off-board

(plugged in a programming tool) or on-board using

In-Circuit Programming or In-Application Program-

ming.

The array matrix organisation allows each sector

to be erased and reprogrammed without affecting

other sectors.

4.2 Main Features

■ ICP (In-Circuit Programming)

■ IAP (In-Application Programming)

■ ICT (In-Circuit Testing) for downloading and

executing user application test patterns in RAM

■ Sector 0 size configurable by option byte

■ Read-out and write protection

4.3 PROGRAMMING MODES

The ST7 can be programmed in three different

ways:

– Insertion in a programming tool. In this mode,

FLASH sectors 0 and 1, option byte row and

data EEPROM (if present) can be pro-

grammed or erased.

– In-Circuit Programming. In this mode, FLASH

sectors 0 and 1, option byte row and data

EEPROM (if present) can be programmed or

erased without removing the device from the

application board.

– In-Application Programming. In this mode,

sector 1 and data EEPROM (if present) can

be programmed or erased without removing

the device from the application board and

while the application is running.

4.3.1 In-Circuit Programming (ICP)

ICP uses a protocol called ICC (In-Circuit Commu-

nication) which allows an ST7 plugged on a print-

ed circuit board (PCB) to communicate with an ex-

ternal programming device connected via cable.

ICP is performed in three steps:

Switch the ST7 to ICC mode (In-Circuit Communi-

cations). This is done by driving a specific signal

sequence on the ICCCLK/DATA pins while the

RESET pin is pulled low. When the ST7 enters

ICC mode, it fetches a specific RESET vector

which points to the ST7 System Memory contain-

ing the ICC protocol routine. This routine enables

the ST7 to receive bytes from the ICC interface.

– Download ICP Driver code in RAM from the

ICCDATA pin

– Execute ICP Driver code in RAM to program

the FLASH memory

Depending on the ICP Driver code downloaded in

RAM, FLASH memory programming can be fully

customized (number of bytes to program, program

locations, or selection of the serial communication

interface for downloading).

4.3.2 In Application Programming (IAP)

This mode uses an IAP Driver program previously

programmed in Sector 0 by the user (in ICP

mode).

This mode is fully controlled by user software. This

allows it to be adapted to the user application, (us-

er-defined strategy for entering programming

mode, choice of communications protocol used to

fetch the data to be stored etc.).

IAP mode can be used to program any memory ar-

eas except Sector 0, which is write/erase protect-

ed to allow recovery in case errors occur during

the programming operation.

ST7LITE2

13/133

FLASH PROGRAM MEMORY (Cont’d)

4.4 ICC interface

ICP needs a minimum of 4 and up to 6 pins to be

connected to the programming tool. These pins

are:

– RESET

: device reset

–V

: device power supply ground

– ICCCLK: ICC output serial clock pin

– ICCDATA: ICC input serial data pin

– CLKIN/PB4: main clock input for external

source

–V

: application board power supply (option-

al, see Note 3)

Notes:

1. If the ICCCLK or ICCDATA pins are only used

as outputs in the application, no signal isolation is

necessary. As soon as the Programming Tool is

plugged to the board, even if an ICC session is not

in progress, the ICCCLK and ICCDATA pins are

not available for the application. If they are used as

inputs by the application, isolation such as a serial

resistor has to be implemented in case another de-

vice forces the signal. Refer to the Programming

Tool documentation for recommended resistor val-

ues.

2. During the ICP session, the programming tool

must control the RESET

pin. This can lead to con-

flicts between the programming tool and the appli-

cation reset circuit if it drives more than 5mA at

high level (push pull output or pull-up resistor<1K).

A schottky diode can be used to isolate the appli-

cation RESET circuit in this case. When using a

classical RC network with R>1K or a reset man-

agement IC with open drain output and pull-up re-

sistor>1K, no additional components are needed.

In all cases the user must ensure that no external

reset is generated by the application during the

ICC session.

3. The use of Pin 7 of the ICC connector depends

on the Programming Tool architecture. This pin

must be connected when using most ST Program-

ming Tools (it is used to monitor the application

power supply). Please refer to the Programming

Tool manual.

4. Pin 9 has to be connected to the CLKIN/PB4 pin

of the ST7 when the clock is not available in the

application or if the selected clock option is not

programmed in the option byte. ST7 devices with

multi-oscillator capability need to have OSC1 and

OSC2 grounded in this case.

5. With any programming tool, while the ICP option

is disabled, the external clock has to be provided

on PB4.

Caution: During normal operation the ICCCLK pin

must be pulled- up, internally or externally (exter-

nal pull-up of 10k mandatory in noisy environ-

ment). This is to avoid entering ICC mode unex-

pectedly during a reset. In the application, even if

the pin is configured as output, any reset will put it

back in input pull-up.

Figure 5. Typical ICC Interface

ICC CONNECTOR

ICCDATA

ICCCLK

RESET

HE10 CONNECTOR TYPE

APPLICATION

POWER SUPPLY

246810

975 3

PROGRAMMING TOOL

ICC CONNECTOR

APPLICATION BOARD

ICC Cable

(See Note 3)

ST7

OPTIONAL

See Note 1 and Caution

See Note 2

APPLICATION

RESET SOURCE

APPLICATION

I/O

(See Note 4)

(See Note 5)

CLKIN/PB4

ST7LITE2

14/133

FLASH PROGRAM MEMORY (Cont’d)

4.5 Memory Protection

There are two different types of memory protec-

tion: Read Out Protection and Write/Erase Protec-

tion which can be applied individually.

4.5.1 Read-out Protection

Read-out protection, when selected provides a

protection against program memory content ex-

traction and against write access to Flash memo-

ry. Even if no protection can be considered as to-

tally unbreakable, the feature provides a very high

level of protection for a general purpose microcon-

troller. Both program and data E

memory are pro-

tected.

In flash devices, this protection is removed by re-

programming the option. In this case, both pro-

gram and data E

memory are automatically

erased and the device can be reprogrammed.

Read-out protection selection depends on the de-

vice type:

– In Flash devices it is enabled and removed

through the FMP_R bit in the option byte.

– In ROM devices it is enabled by mask option

specified in the Option List.

4.5.2 Flash Write/Erase Protection

Write/erase protection, when set, makes it impos-

sible to both overwrite and erase program memo-

ry. It does not apply to E

data. Its purpose is to

provide advanced security to applications and pre-

vent any change being made to the memory con-

tent.

Warning: Once set, Write/erase protection can

never be removed. A write-protected flash device

is no longer reprogrammable.

Write/erase protection is enabled through the

FMP_W bit in the option byte.

4.6 Related Documentation

For details on Flash programming and ICC proto-

col, refer to the ST7 Flash Programming Refer-

ence Manual and to the ST7 ICC Protocol Refer-

ence Manual

4.7 Register Description

FLASH CONTROL/STATUS REGISTER (FCSR)

Read/Write

Reset Value: 000 0000 (00h)

1st RASS Key: 0101 0110 (56h)

2nd RASS Key: 1010 1110 (AEh)

Note: This register is reserved for programming

using ICP, IAP or other programming methods. It

controls the XFlash programming and erasing op-

erations.

When an EPB or another programming tool is

used (in socket or ICP mode), the RASS keys are

sent automatically.

00000OPTLATPGM

ST7LITE2

15/133

5 DATA EEPROM

5.1 INTRODUCTION

The Electrically Erasable Programmable Read

Only Memory can be used as a non volatile back-

up for storing data. Using the EEPROM requires a

basic access protocol described in this chapter.

5.2 MAIN FEATURES

■ Up to 32 Bytes programmed in the same cycle

■ EEPROM mono-voltage (charge pump)

■ Chained erase and programming cycles

■ Internal control of the global programming cycle

duration

■ WAIT mode management

■ Read-out protection

Figure 6. EEPROM Block Diagram

EECSR

HIGH VOLTAGE

PUMP

0 E2LAT00 0 0 0 E2PGM

EEPROM

MEMORY MATRIX

(1 ROW = 32 x 8 BITS)

ADDRESS

DECODER

DATA

MULTIPLEXER

32 x 8 BITS

DATA LATCHES

ROW

DECODER

DATA BUS

128128

ADDRESS BUS

ST7LITE2

16/133

DATA EEPROM (Cont’d)

5.3 MEMORY ACCESS

The Data EEPROM memory read/write access

modes are controlled by the E2LAT bit of the EEP-

ROM Control/Status register (EECSR). The flow-

chart in Figure 7 describes these different memory

access modes.

Read Operation (E2LAT=0)

The EEPROM can be read as a normal ROM loca-

tion when the E2LAT bit of the EECSR register is

cleared.

On this device, Data EEPROM can also be used to

execute machine code. Take care not to write to

the Data EEPROM while executing from it. This

would result in an unexpected code being execut-

ed.

Write Operation (E2LAT=1)

To access the write mode, the E2LAT bit has to be

set by software (the E2PGM bit remains cleared).

When a write access to the EEPROM area occurs,

the value is latched inside the 32 data latches ac-

cording to its address.

When PGM bit is set by the software, all the previ-

ous bytes written in the data latches (up to 32) are

programmed in the EEPROM cells. The effective

high address (row) is determined by the last EEP-

ROM write sequence. To avoid wrong program-

ming, the user must take care that all the bytes

written between two programming sequences

have the same high address: only the five Least

Significant Bits of the address can change.

At the end of the programming cycle, the PGM and

LAT bits are cleared simultaneously.

Note: Care should be taken during the program-

ming cycle. Writing to the same memory location

will over-program the memory (logical AND be-

tween the two write access data result) because

the data latches are only cleared at the end of the

programming cycle and by the falling edge of the

E2LAT bit.

It is not possible to read the latched data.

This note is illustrated by the Figure 9.

Figure 7. Data EEPROM Programming Flowchart

READ MODE

E2LAT=0

E2PGM=0

WRITE MODE

E2LAT=1

E2PGM=0

READ BYTES

IN EEPROM AREA

WRITE UP TO 32 BYTES

IN EEPROM AREA

(with the same 11 MSB of the address)

START PROGRAMMING CYCLE

E2LAT=1

E2PGM=1 (set by software)

E2LAT

CLEARED BY HARDWARE

ST7LITE2

17/133

DATA EEPROM (Cont’d)

Figure 8. Data E

PROM Write Operation

Note: If a programming cycle is interrupted (by a reset action), the integrity of the data in memory is not

guaranteed.

Byte 1 Byte 2 Byte 32

PHASE 1

Programming cycle

Read operation impossible

PHASE 2

Read operation possible

E2LAT bit

E2PGM bit

Writing data latches Waiting E2PGM and E2LAT to fall

Set by USER application

Cleared by hardware

⇓ Row / Byte ⇒ 0 1 2 3 ... 30 31 Physical Address

00h...1Fh

20h...3Fh

...

Nx20h...Nx20h+1Fh

ROW

DEFINITION

ST7LITE2

18/133

DATA EEPROM (Cont’d)

5.4 POWER SAVING MODES

Wait mode

The DATA EEPROM can enter WAIT mode on ex-

ecution of the WFI instruction of the microcontrol-

ler or when the microcontroller enters Active-HALT

mode.The DATA EEPROM will immediately enter

this mode if there is no programming in progress,

otherwise the DATA EEPROM will finish the cycle

and then enter WAIT mode.

Active-Halt mode

Refer to Wait mode.

Halt mode

The DATA EEPROM immediately enters HALT

mode if the microcontroller executes the HALT in-

struction. Therefore the EEPROM will stop the

function in progress, and data may be corrupted.

5.5 ACCESS ERROR HANDLING

If a read access occurs while E2LAT=1, then the

data bus will not be driven.

If a write access occurs while E2LAT=0, then the

data on the bus will not be latched.

If a programming cycle is interrupted (by a RESET

action), the memory data will not be guaranteed.

5.6 Data EEPROM Read-out Protection

The read-out protection is enabled through an op-

tion bit (see section 15.1 on page 122).

When this option is selected, the programs and

data stored in the EEPROM memory are protected

against read-out (including a re-write protection).

In Flash devices, when this protection is removed

by reprogramming the Option Byte, the entire Pro-

gram memory and EEPROM is first automatically

erased.

Note: Both Program Memory and data EEPROM

are protected using the same option bit.

Figure 9. Data EEPROM programming cycle

LAT

ERASE CYCLE WRITE CYCLE

PGM

PROG

READ OPERATION NOT POSSIBLE

WRITE OF

DATA LATCHES

READ OPERATION POSSIBLE

INTERNAL

PROGRAMMING

VOLTAGE

ST7LITE2

19/133

DATA EEPROM (Cont’d)

5.7 REGISTER DESCRIPTION

EEPROM CONTROL/STATUS REGISTER (EEC-

SR)

Read/Write

Reset Value: 0000 0000 (00h)

Bits 7:2 = Reserved, forced by hardware to 0.

Bit 1 = E2LAT Latch Access Transfer

This bit is set by software. It is cleared by hard-

ware at the end of the programming cycle. It can

only be cleared by software if the E2PGM bit is

cleared.

0: Read mode

1: Write mode

Bit 0 = E2PGM Programming control and status

This bit is set by software to begin the programming

cycle. At the end of the programming cycle, this bit

is cleared by hardware.

0: Programming finished or not yet started

1: Programming cycle is in progress

Note: if the E2PGM bit is cleared during the pro-

gramming cycle, the memory data is not guaran-

teed

Table 3. DATA EEPROM Register Map and Reset Values

000000E2LATE2PGM

Address

(Hex.)

Label

76543210

0030h

EECSR

Reset Value

000000

E2LAT

E2PGM

ST7LITE2

20/133

6 CENTRAL PROCESSING UNIT

6.1 INTRODUCTION

This CPU has a full 8-bit architecture and contains

six internal registers allowing efficient 8-bit data

manipulation.

6.2 MAIN FEATURES

■ 63 basic instructions

■ Fast 8-bit by 8-bit multiply

■ 17 main addressing modes

■ Two 8-bit index registers

■ 16-bit stack pointer

■ Low power modes

■ Maskable hardware interrupts

■ Non-maskable software interrupt

6.3 CPU REGISTERS

The 6 CPU registers shown in Figure 10 are not

present in the memory mapping and are accessed

by specific instructions.

Accumulator (A)

The Accumulator is an 8-bit general purpose reg-

ister used to hold operands and the results of the

arithmetic and logic calculations and to manipulate

data.

Index Registers (X and Y)

In indexed addressing modes, these 8-bit registers

are used to create either effective addresses or

temporary storage areas for data manipulation.

(The Cross-Assembler generates a precede in-

struction (PRE) to indicate that the following in-

struction refers to the Y register.)

The Y register is not affected by the interrupt auto-

matic procedures (not pushed to and popped from

the stack).

Program Counter (PC)

The program counter is a 16-bit register containing

the address of the next instruction to be executed

by the CPU. It is made of two 8-bit registers PCL

(Program Counter Low which is the LSB) and PCH

(Program Counter High which is the MSB).

Figure 10. CPU Registers

ACCUMULATOR

X INDEX REGISTER

Y INDEX REGISTER

STACK POINTER

CONDITION CODE REGISTER

PROGRAM COUNTER

1C11HI NZ

RESET VALUE = RESET VECTOR @ FFFEh-FFFFh

15 8

PCH

PCL

RESET VALUE = STACK HIGHER ADDRESS

RESET VALUE =

1X11X1XX

RESET VALUE = XXh

X = Undefined Value

ST7LITE2

21/133

CPU REGISTERS (Cont’d)

CONDITION CODE REGISTER (CC)

Read/Write

Reset Value: 111x1xxx

The 8-bit Condition Code register contains the in-

terrupt mask and four flags representative of the

result of the instruction just executed. This register

can also be handled by the PUSH and POP in-

structions.

These bits can be individually tested and/or con-

trolled by specific instructions.

Bit 4 = H Half carry.

This bit is set by hardware when a carry occurs be-

tween bits 3 and 4 of the ALU during an ADD or

ADC instruction. It is reset by hardware during the

same instructions.

0: No half carry has occurred.

1: A half carry has occurred.

This bit is tested using the JRH or JRNH instruc-

tion. The H bit is useful in BCD arithmetic subrou-

tines.

Bit 3 = I Interrupt mask.

This bit is set by hardware when entering in inter-

rupt or by software to disable all interrupts except

the TRAP software interrupt. This bit is cleared by

software.

0: Interrupts are enabled.

1: Interrupts are disabled.

This bit is controlled by the RIM, SIM and IRET in-

structions and is tested by the JRM and JRNM in-

structions.

Note: Interrupts requested while I is set are

latched and can be processed when I is cleared.

By default an interrupt routine is not interruptible

because the I bit is set by hardware at the start of

the routine and reset by the IRET instruction at the

end of the routine. If the I bit is cleared by software

in the interrupt routine, pending interrupts are

serviced regardless of the priority level of the cur-

rent interrupt routine.

Bit 2 = N Negative.

This bit is set and cleared by hardware. It is repre-

sentative of the result sign of the last arithmetic,

logical or data manipulation. It is a copy of the 7

bit of the result.

0: The result of the last operation is positive or null.

1: The result of the last operation is negative

(i.e. the most significant bit is a logic 1).

This bit is accessed by the JRMI and JRPL instruc-

tions.

Bit 1 = Z Zero.

This bit is set and cleared by hardware. This bit in-

dicates that the result of the last arithmetic, logical

or data manipulation is zero.

0: The result of the last operation is different from

zero.

1: The result of the last operation is zero.

This bit is accessed by the JREQ and JRNE test

instructions.

Bit 0 = C Carry/borrow.

This bit is set and cleared by hardware and soft-

ware. It indicates an overflow or an underflow has

occurred during the last arithmetic operation.

0: No overflow or underflow has occurred.

1: An overflow or underflow has occurred.

This bit is driven by the SCF and RCF instructions

and tested by the JRC and JRNC instructions. It is

also affected by the “bit test and branch”, shift and

rotate instructions.

111HINZC

ST7LITE2

22/133

CPU REGISTERS (Cont’d)

STACK POINTER (SP)

Read/Write

Reset Value: 01FFh

The Stack Pointer is a 16-bit register which is al-

ways pointing to the next free location in the stack.

It is then decremented after data has been pushed

onto the stack and incremented before data is

popped from the stack (see Figure 11).

Since the stack is 128 bytes deep, the 9 most sig-

nificant bits are forced by hardware. Following an

MCU Reset, or after a Reset Stack Pointer instruc-

tion (RSP), the Stack Pointer contains its reset val-

ue (the SP6 to SP0 bits are set) which is the stack

higher address.

The least significant byte of the Stack Pointer

(called S) can be directly accessed by a LD in-

struction.

Note: When the lower limit is exceeded, the Stack

Pointer wraps around to the stack upper limit, with-

out indicating the stack overflow. The previously

stored information is then overwritten and there-

fore lost. The stack also wraps in case of an under-

flow.

The stack is used to save the return address dur-

ing a subroutine call and the CPU context during

an interrupt. The user may also directly manipulate

the stack by means of the PUSH and POP instruc-

tions. In the case of an interrupt, the PCL is stored

at the first location pointed to by the SP. Then the

other registers are stored in the next locations as

shown in Figure 11.

– When an interrupt is received, the SP is decre-

mented and the context is pushed on the stack.

– On return from interrupt, the SP is incremented

and the context is popped from the stack.

A subroutine call occupies two locations and an in-

terrupt five locations in the stack area.

Figure 11. Stack Manipulation Example

15 8

00000001

1 SP6 SP5 SP4 SP3 SP2 SP1 SP0

PCH

PCL

PCH

PCL

PCH

PCL

PCH

PCL

PCH

PCL

CALL

Subroutine

Interrupt

Event

PUSH Y POP Y IRET

RET

or RSP

@ 01FFh

@ 0180h

Stack Higher Address = 01FFh

Stack Lower Address =

0180h

ST7LITE2

23/133

7 SUPPLY, RESET AND CLOCK MANAGEMENT

The device includes a range of utility features for

securing the application in critical situations (for

example in case of a power brown-out), and re-

ducing the number of external components.

Main features

■ Clock Management

– 1 MHz internal RC oscillator (enabled by op-

tion byte, available on ST7LITE25 and

ST7LITE29 devices only)

– 1 to 16 MHz or 32kHz External crystal/ceramic

resonator (selected by option byte)

– External Clock Input (enabled by option byte)

– PLL for multiplying the frequency by 8 or 4

(enabled by option byte)

– For clock ART counter only: PLL32 for multi-

plying the 8 MHz frequency by 4 (enabled by

option byte). The 8 MHz input frequency is

mandatory and can be obtained in the follow-

ing ways:

–1 MHz RC + PLLx8

–16 MHz external clock (internally divided

by 2)

–2 MHz. external clock (internally divided by

2) + PLLx8

–Crystal oscillator with 16 MHz output fre-

quency (internally divided by 2)

■ Reset Sequence Manager (RSM)

■ System Integrity Management (SI)

– Main supply Low voltage detection (LVD) with

reset generation (enabled by option byte)

– Auxiliary Voltage detector (AVD) with interrupt

capability for monitoring the main supply (en-

abled by option byte)

7.1 INTERNAL RC OSCILLATOR ADJUSTMENT

The device contains an internal RC oscillator with

an accuracy of 1% for a given device, temperature

and voltage range (4.5V-5.5V). It must be calibrat-

ed to obtain the frequency required in the applica-

tion. This is done by software writing a calibration

value in the RCCR (RC Control Register).

Whenever the microcontroller is reset, the RCCR

returns to its default value (FFh), i.e. each time the

device is reset, the calibration value must be load-

ed in the RCCR. Predefined calibration values are

stored in EEPROM for 3 and 5V V

supply volt-

ages at 25°C, as shown in the following table.

Note:

– See “ELECTRICAL CHARACTERISTICS” on

page 91. for more information on the frequency

and accuracy of the RC oscillator.

– To improve clock stability and frequency accura-

cy, it is recommended to place a decoupling ca-

pacitor, typically 100nF, between the V

and

pins as close as possible to the ST7 device.

– These two bytes are systematically programmed

by ST, including on FASTROM devices. Conse-

quently, customers intending to use FASTROM

service must not use these two bytes.

– RCCR0 and RCCR1 calibration values will be

erased if the read-out protection bit is reset after

it has been set. See “Read-out Protection” on

page 14.

Caution: If the voltage or temperature conditions

change in the application, the frequency may need

to be recalibrated.

Refer to application note AN1324 for information

on how to calibrate the RC frequency using an ex-

ternal reference signal.

7.2 PHASE LOCKED LOOP

The PLL can be used to multiply a 1MHz frequen-

cy from the RC oscillator or the external clock by 4

or 8 to obtain f

OSC

of 4 or 8 MHz. The PLL is ena-

bled and the multiplication factor of 4 or 8 is select-

ed by 2 option bits.

– The x4 PLL is intended for operation with V

the 2.4V to 3.3V range

– The x8 PLL is intended for operation with V

the 3.3V to 5.5V range

Refer to Section 15.1 for the option byte descrip-

tion.

If the PLL is disabled and the RC oscillator is ena-

bled, then f

OSC =

1MHz.

If both the RC oscillator and the PLL are disabled,

OSC

is driven by the external clock.

RCCR Conditions

ST7LITE29

Address

ST7LITE25

Address

RCCR0

=5V

=25°C

=1MHz

1000h

and FFDEh

FFDEh

RCCR1

=3V

=25°C

=700KHz

1001h

and FFDFh

FFDFh

ST7LITE2

24/133

PHASE LOCKED LOOP (Cont’d)

Figure 12. PLL Output Frequency Timing

Diagram

When the PLL is started, after reset or wakeup

from Halt mode or AWUFH mode, it outputs the

clock after a delay of t

STARTUP

When the PLL output signal reaches the operating

frequency, the LOCKED bit in the SICSCR register

is set. Full PLL accuracy (ACC

PLL

) is reached after

a stabilization time of t

STAB

(see Figure 12 and

13.3.4 Internal RC Oscillator and PLL)

Refer to section 7.6.4 on page 33 for a description

of the LOCKED bit in the SICSR register.

7.3 REGISTER DESCRIPTION

MAIN CLOCK CONTROL/STATUS REGISTER

(MCCSR)

Read / Write

Reset Value: 0000 0000 (00h)

Bits 7:2 = Reserved, must be kept cleared.

Bit 1 = MCO Main Clock Out enable

This bit is read/write by software and cleared by

hardware after a reset. This bit allows to enable

the MCO output clock.

0: MCO clock disabled, I/O port free for general

purpose I/O.

1: MCO clock enabled.

Bit 0 = SMS Slow Mode select

This bit is read/write by software and cleared by

hardware after a reset. This bit selects the input

clock f

OSC

or f

OSC

/32.

0: Normal mode (f

CPU =

OSC

1: Slow mode (f

CPU =

OSC

/32)

RC CONTROL REGISTER (RCCR)

Read / Write

Reset Value: 1111 1111 (FFh)

Bits 7:0 = CR[7:0] RC Oscillator Frequency Ad-

justment Bits

These bits must be written immediately after reset

to adjust the RC oscillator frequency and to obtain

an accuracy of 1%. The application can store the

correct value for each voltage range in EEPROM

and write it to this register at start-up.

00h = maximum available frequency

FFh = lowest available frequency

Note: To tune the oscillator, write a series of differ-

ent values in the register until the correct frequen-

cy is reached. The fastest method is to use a di-

chotomy starting with 80h.

4/8 x

freq.

LOCKED bit set

STAB

LOCK

input

Output freq.

STARTUP

000000

MCO SMS

CR70 CR60 CR50 CR40 CR30 CR20 CR10

ST7LITE2

25/133

Figure 13. Clock Management Block Diagram

CR4CR7 CR0CR1CR2CR3CR6 CR5

RCCR

OSC

MCCSR

SMS

MCO

CPU

TO CPU AND

PERIPHERALS

(1ms timebase @ 8 MHz f

OSC

)

/32 DIVIDER

OSC

/32

OSC

LTIMER

LITE TIMER 2 COUNTER

8-BIT

AT TIMER 2

12-BIT

PLL

8MHz -> 32MHz

CPU

CLKIN

OSC2

CLKIN

Tunable

Oscillator1% RC

PLL 1MHz -> 8MHz

PLL 1MHz -> 4MHz

RC OSC

PLLx4x8

DIVIDER

Option bits

OSC,PLLOFF,

OSCRANGE[2:0]

OSC

1-16 MHZ

or 32kHz

CLKIN

/OSC1

OSC

DIVIDER

OSC/2

CLKIN/2

Option bits

OSC,PLLOFF,

OSCRANGE[2:0]

ST7LITE2

26/133

7.4 MULTI-OSCILLATOR (MO)

The main clock of the ST7 can be generated by

four different source types coming from the multi-

oscillator block (1 to 16MHz or 32kHz):

■ an external source

■ 5 crystal or ceramic resonator oscillators

■ an internal high frequency RC oscillator

Each oscillator is optimized for a given frequency

range in terms of consumption and is selectable

through the option byte. The associated hardware

configurations are shown in Table 4. Refer to the

electrical characteristics section for more details.

External Clock Source

In this external clock mode, a clock signal (square,

sinus or triangle) with ~50% duty cycle has to drive

the OSC1 pin while the OSC2 pin is tied to ground.

Note: when the Multi-Oscillator is not used, PB4 is

selected by default as external clock.

Crystal/Ceramic Oscillators

This family of oscillators has the advantage of pro-

ducing a very accurate rate on the main clock of

the ST7. The selection within a list of 4 oscillators

with different frequency ranges has to be done by

option byte in order to reduce consumption (refer

to section 15.1 on page 122 for more details on the

frequency ranges). In this mode of the multi-oscil-

lator, the resonator and the load capacitors have

to be placed as close as possible to the oscillator

pins in order to minimize output distortion and

start-up stabilization time. The loading capaci-

tance values must be adjusted according to the

selected oscillator.

These oscillators are not stopped during the

RESET phase to avoid losing time in the oscillator

start-up phase.

Internal RC Oscillator

In this mode, the tunable 1%RC oscillator is used

as main clock source. The two oscillator pins have

to be tied to ground.

Table 4. ST7 Clock Sources

Hardware Configuration

External ClockCrystal/Ceramic Resonators

Internal RC Oscillator or

External Clock on PB4

OSC1 OSC2

EXTERNAL

ST7

SOURCE

OSC1 OSC2

LOAD

CAPACITORS

ST7

OSC1 OSC2

ST7

ST7LITE2

27/133

7.5 RESET SEQUENCE MANAGER (RSM)

7.5.1 Introduction

The reset sequence manager includes three RE-

SET sources as shown in Figure 15:

■ External RESET source pulse

■ Internal LVD RESET (Low Voltage Detection)

■ Internal WATCHDOG RESET

Note: A reset can also be triggered following the

detection of an illegal opcode or prebyte code. Re-

fer to section 12.2.1 on page 88 for further details.

These sources act on the RESET

pin and it is al-

ways kept low during the delay phase.

The RESET service routine vector is fixed at ad-

dresses FFFEh-FFFFh in the ST7 memory map.

The basic RESET sequence consists of 3 phases

as shown in Figure 14:

■ Active Phase depending on the RESET source

■ 256 or 4096 CPU clock cycle delay (see table

below)

■ RESET vector fetch

The 256 or 4096 CPU clock cycle delay allows the

oscillator to stabilise and ensures that recovery

has taken place from the Reset state. The shorter

or longer clock cycle delay is automatically select-

ed depending on the clock source chosen by op-

tion byte:

The RESET vector fetch phase duration is 2 clock

cycles.

If the PLL is enabled by option byte, it outputs the

clock after an additional delay of t

STARTUP

(see

Figure 12).

Figure 14. RESET Sequence Phases

7.5.2 Asynchronous External RESET

The RESET

pin is both an input and an open-drain

output with integrated R

weak pull-up resistor.

This pull-up has no fixed value but varies in ac-

cordance with the input voltage. It

can be pulled

low by external circuitry to reset the device. See

Electrical Characteristic section for more details.

A RESET signal originating from an external

source must have a duration of at least t

h(RSTL)in

order to be recognized (see Figure 16). This de-

tection is asynchronous and therefore the MCU

can enter reset state even in HALT mode.

Figure 15. Reset Block Diagram

Clock Source

CPU clock

cycle delay

Internal RC Oscillator 256

External clock (connected to CLKIN pin) 256

External Crystal/Ceramic Oscillator

(connected to OSC1/OSC2 pins)

4096

RESET

Active Phase

INTERNAL RESET

256 or 4096 CLOCK CYCLES

FETCH

VECTOR

RESET

WATCHDOG RESET

LVD RESET

INTERNAL

RESET

PULSE

GENERATOR

Filter

Note 1: See “Illegal Opcode Reset” on page 88. for more details on illegal opcode reset conditions.

ILLEGAL OPCODE RESET

ST7LITE2

28/133

RESET SEQUENCE MANAGER (Cont’d)

The RESET

pin is an asynchronous signal which

plays a major role in EMS performance. In a noisy

environment, it is recommended to follow the

guidelines mentioned in the electrical characteris-

tics section.

7.5.3 External Power-On RESET

If the LVD is disabled by option byte, to start up the

microcontroller correctly, the user must ensure by

means of an external reset circuit that the reset

signal is held low until V

is over the minimum

level specified for the selected f

OSC

frequency.

A proper reset signal for a slow rising V

supply

can generally be provided by an external RC net-

work connected to the RESET

pin.

7.5.4 Internal Low Voltage Detector (LVD)

RESET

Two different RESET sequences caused by the in-

ternal LVD circuitry can be distinguished:

■ Power-On RESET

■ Voltage Drop RESET

The device RESET

pin acts as an output that is

pulled low when V

IT+

(rising edge) or

IT-

(falling edge) as shown in Figure 16.

The LVD filters spikes on V

larger than t

g(VDD)

avoid parasitic resets.

7.5.5 Internal Watchdog RESET

The RESET sequence generated by a internal

Watchdog counter overflow is shown in Figure 16.

Starting from the Watchdog counter underflow, the

device RESET

pin acts as an output that is pulled

low during at least t

w(RSTL)out

Figure 16. RESET Sequences

RUN

RESET PIN

EXTERNAL

WATCHDOG

ACTIVE PHASE

IT+(LVD)

IT-(LVD)

h(RSTL)in

RUN

WATCHDOG UNDERFLOW

w(RSTL)out

RUN RUN

RESET

SOURCE

EXTERNAL

RESET

LVD

RESET

WATCHDOG

RESET

INTERNAL RESET (256 or 4096 T

CPU

)

VECTOR FETCH

ACTIVE

PHASE

ACTIVE

PHASE

ST7LITE2

29/133

7.6 SYSTEM INTEGRITY MANAGEMENT (SI)

The System Integrity Management block contains

the Low voltage Detector (LVD) and Auxiliary Volt-

age Detector (AVD) functions. It is managed by

the SICSR register.

Note: A reset can also be triggered following the

detection of an illegal opcode or prebyte code. Re-

fer to section 12.2.1 on page 88 for further details.

7.6.1 Low Voltage Detector (LVD)

The Low Voltage Detector function (LVD) gener-

ates a static reset when the V

supply voltage is

below a V

IT-(LVD)

reference value. This means that

it secures the power-up as well as the power-down

keeping the ST7 in reset.

The V

IT-(LVD)

reference value for a voltage drop is

lower than the V

IT+(LVD)

reference value for power-

on in order to avoid a parasitic reset when the

MCU starts running and sinks current on the sup-

ply (hysteresis).

The LVD Reset circuitry generates a reset when

is below:

–V

IT+(LVD)

when V

is rising

–V

IT-(LVD)

when V

is falling

The LVD function is illustrated in Figure 17.

The voltage threshold can be configured by option

byte to be low, medium or high.

Provided the minimum V

value (guaranteed for

the oscillator frequency) is above V

IT-(LVD)

, the

MCU can only be in two modes:

– under full software control

– in static safe reset

In these conditions, secure operation is always en-

sured for the application without the need for ex-

ternal reset hardware.

During a Low Voltage Detector Reset, the RESET

pin is held low, thus permitting the MCU to reset

other devices.

Notes:

The LVD allows the device to be used without any

external RESET circuitry.

The LVD is an optional function which can be se-

lected by option byte.

Use of LVD with capacitive power supply: with this

type of power supply, if power cuts occur in the ap-

plication, it is recommended to pull V

down to

0V to ensure optimum restart conditions. Refer to

circuit example in Figure 84 on page 112 and note

It is recommended to make sure that the V

sup-

ply voltage rises monotonously when the device is

exiting from Reset, to ensure the application func-

tions properly.

Figure 17. Low Voltage Detector vs Reset

IT+

(LVD)

RESET

IT-

(LVD)

hys

ST7LITE2

30/133

Figure 18. Reset and Supply Management Block Diagram

LOW VOLTAGE

DETECTOR

(LVD)

AUXILIARY VOLTAGE

DETECTOR

(AVD)

RESET

RESET SEQUENCE

MANAGER

(RSM)

AVD Interrupt Request

SYSTEM INTEGRITY MANAGEMENT

WATCHDOG

SICSR

TIMER (WDG)

AVDIEAVDF

STATUS FLAG

00 LVDRFLOCKEDWDGRF0

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