ST ST7FOXF1, ST7FOXK1, ST7FOXK2 User Manual

ST7FOXF1, ST7FOXK1, ST7FOXK2

8-bit MCU with single voltage Flash memory,

Features

■ Memories

– 4 to 8 Kbytes single voltage extended Flash

(XFlash) Program memory with Read-Out Protection In-Circuit Programming and In-Application programming (ICP and IAP) Endurance: 1K write/erase cycles guaranteed Data retention: 20 years at 55 °C

– 384 bytes RAM

■ Clock, Reset and Supply Management

– Low voltage supervisor (LVD) for safe

power-on/off

– Clock sources: Intern al trimmable 8 MHz

RC oscillator, auto wakeup internal low power - low frequency oscillator,

crystal/ceramic resonator or external clock – External reset source and watchdog reset – Five power saving modes: Halt, Active-Halt,

Auto Wakeup from Halt, Wait and Slow

■ I/O Ports

– Up to 24 multifunctional bidirectional I/Os – Up to 8 high sink outputs

SPI, I²C, ADC, timers

DIP20

■ 6 timers

SO20

– Configurable watchdog timer – Dual 8-bit Lite timers with prescaler,

1 real time base and 1 input capture

– Dual 12-bit Auto-reload timers with 4 PWM

outputs, input capture, output compare, dead-time generation and enhanced one pulse mode functions

– One 16-bit timer

■ Communication interfaces:

– I²C multimaster interface – SPI synchronous serial interface

■ A/D converter: up to 10 input channels

■ Interrupt management

– 13 interrupt vectors plus TRAP and RESET

■ Instruction set

– 8-bit data manipulation – 63 basic instructions with illegal opcode

detection – 17 main addressing modes – 8 x 8 unsigned multiply instructions

■ Development tools

– Full HW/SW development package – DM (Debug Module)

LQFP32 SDIP32

February 2008 Rev 4 1/226

www.st.com

Contents ST7FOXF1, ST7FOXK1, ST7FOXK2

Contents

1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3 Register and memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4 Flash programmable memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.3 Programming modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.3.1 In-Circuit Programming (ICP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.3.2 In Application Programming (IAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.4 ICC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.5 Memory protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

4.5.1 Read-out protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

4.5.2 Flash write/erase protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

4.6 Related documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

4.7 Description of Flash Control/Status register (FCSR) . . . . . . . . . . . . . . . . 28

5 Central processing unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

5.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

5.3 CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

5.3.1 Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

5.3.2 Index registers (X and Y) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

5.3.3 Program Counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

5.3.4 Condition Code register (CC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

5.3.5 Stack Pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

6 Supply, reset and clock management . . . . . . . . . . . . . . . . . . . . . . . . . . 34

6.1 RC oscillator adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

6.1.1 Internal RC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

6.1.2 Customized RC calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

6.1.3 Auto wakeup RC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

2/226

ST7FOXF1, ST7FOXK1, ST7FOXK2 Contents

6.2 Multi-oscillator (MO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

6.2.1 External clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

6.2.2 Crystal/ceramic oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

6.2.3 Internal RC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

6.3 Reset sequence manager (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

6.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

6.3.2 Asynchronous external RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

6.3.3 External power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

6.3.4 Internal Low Voltage Detector (LVD) reset . . . . . . . . . . . . . . . . . . . . . . . 42

6.3.5 Internal watchdog reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

6.4 System Integrity management (SI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

6.4.1 Low Voltage Detector (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

6.5 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

6.5.1 RC calibration control/status register (RCC_CSR) . . . . . . . . . . . . . . . . 46

6.5.2 Main Clock Control/Status Register (MCCSR) . . . . . . . . . . . . . . . . . . . 46

6.5.3 RC Control Register High (RCCRH) . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

6.5.4 RC Control Register Low (RCCRL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

6.5.5 Prescaler register (PSCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

6.5.6 Clock controller control/status register (CKCNTCSR) . . . . . . . . . . . . . . 49

7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

7.2 Masking and processing flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

7.2.1 Servicing pending interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

7.2.2 Interrupt vector sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

7.3 Interrupts and low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

7.4 Concurrent and nested management . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

7.5 Description of interrupt registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

7.5.1 CPU CC register interrupt bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

7.5.2 Interrupt software priority registers (ISPRx) . . . . . . . . . . . . . . . . . . . . . . 56

7.5.3 External Interrupt Control register (EICR) . . . . . . . . . . . . . . . . . . . . . . . 60

8 Power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

8.2 Slow mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

8.3 Wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

3/226

Contents ST7FOXF1, ST7FOXK1, ST7FOXK2

8.4 Active-halt and halt modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

8.4.1 Active-halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

8.4.2 Halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

8.5 Auto-wakeup from Halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

8.5.1 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

8.5.2 AWUFH Control/Status Register (AWUCSR) . . . . . . . . . . . . . . . . . . . . 70

8.5.3 AWUFH prescaler register (AWUPR) . . . . . . . . . . . . . . . . . . . . . . . . . . 71

9 I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

9.2 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

9.2.1 Input modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

9.2.2 Output modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

9.2.3 Alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

9.2.4 Analog alternate function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

9.3 I/O port implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

9.4 Unused I/O pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

9.5 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

9.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

9.7 Device-specific I/O port configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

9.7.1 Standard ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

9.7.2 Other ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

10 On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

10.1 Watchdog timer (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

10.1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

10.1.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

10.1.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

10.1.4 Hardware watchdog option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

10.1.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

10.1.6 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

10.2 Dual 12-bit autoreload timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

10.2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

10.2.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

10.2.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

10.2.4 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

4/226

ST7FOXF1, ST7FOXK1, ST7FOXK2 Contents

10.2.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

10.2.6 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

10.3 Lite timer 2 (LT2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

10.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

10.3.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

10.3.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

10.3.4 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

10.3.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

10.3.6 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

10.4 16-bit timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

10.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

10.4.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

10.4.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

10.4.4 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

10.4.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

10.4.6 Summary of 16-bit timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

10.4.7 16-bit timer registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

10.4.8 16-bit timer register map and reset values . . . . . . . . . . . . . . . . . . . . . . 139

10.5 I2C bus interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

10.5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

10.5.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

10.5.3 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

10.5.4 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

Slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

Master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

10.5.5 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

10.5.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

10.5.7 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

10.6 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

10.6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

10.6.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

10.6.3 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

10.6.4 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

10.6.5 Clock phase and clock polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

10.6.6 Error flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

10.6.7 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

10.6.8 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

5/226

Contents ST7FOXF1, ST7FOXK1, ST7FOXK2

10.6.9 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

10.7 10-bit A/D converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

10.7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

10.7.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

10.7.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

10.7.4 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

10.7.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

10.7.6 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

11 Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

11.1 ST7 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

11.1.1 Inherent mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

11.1.2 Immediate mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

11.1.3 Direct modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

11.1.4 Indexed modes (No Offset, Short, Long) . . . . . . . . . . . . . . . . . . . . . . . 180

11.1.5 Indirect modes (short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

11.1.6 Indirect indexed modes (short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . 181

11.1.7 Relative modes (direct, indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

11.2 Instruction groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

11.2.1 Illegal opcode reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

12 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

12.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

12.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

12.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

12.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

12.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

12.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

12.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188

12.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190

12.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190

12.3.2 Operating conditions with Low Voltage Detector (LVD) . . . . . . . . . . . . 190

12.3.3 Internal RC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191

12.4 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

12.4.1 Supply current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

12.4.2 On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193

6/226

ST7FOXF1, ST7FOXK1, ST7FOXK2 Contents

12.5 Communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . 194

12.5.1 I2C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194

12.5.2 SPI interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

12.6 Clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197

12.6.1 Auto wakeup from Halt oscillator (AWU) . . . . . . . . . . . . . . . . . . . . . . . 198

12.6.2 Crystal and ceramic resonator oscillators . . . . . . . . . . . . . . . . . . . . . . 199

12.7 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200

12.8 EMC (electromagnetic compatibility) characteristics . . . . . . . . . . . . . . . 201

12.8.1 Functional EMS (electromagnetic susceptibility) . . . . . . . . . . . . . . . . . 201

12.8.2 EMI (Electromagnetic interference) . . . . . . . . . . . . . . . . . . . . . . . . . . . 202

12.8.3 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 203

12.9 I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204

12.9.1 General characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204

12.9.2 Output driving current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205

12.10 Control pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206

12.10.1 Asynchronous RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206

12.11 10-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209

13 Device configuration and ordering information . . . . . . . . . . . . . . . . . 211

13.1 Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211

13.1.1 Option byte 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211

13.1.2 Option byte 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212

13.2 Device ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214

ST7FOX failure analysis service . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214

13.3 Development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215

13.3.1 Starter kits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215

13.3.2 Development and debugging tools . . . . . . . . . . . . . . . . . . . . . . . . . . . 215

13.3.3 Programming tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215

13.3.4 Order codes for development and programming tools . . . . . . . . . . . . . 215

13.4 ST7 application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216

14 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220

14.1 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224

15 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225

7/226

List of tables ST7FOXF1, ST7FOXK1, ST7FOXK2

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 2. Device pin description (32-pin packages). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 3. Device pin description (20-pin package). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 4. Hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 5. Flash register mapping and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 6. Interrupt software priority truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 7. Predefined RC oscillator calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 8. ST7 clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 9. CPU clock delay during Reset sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Table 10. Reset source selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Table 11. Internal RC prescaler selection bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 12. Clock register mapping and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 13. Interrupt software priority levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Table 14. Setting the interrupt software priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Table 15. Interrupt vector vs ISPRx bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Table 16. Dedicated interrupt instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Table 17. ST7FOXF1/ST7FOXK1 Interrupt mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Table 18. ST7FOXK2 interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Table 19. Interrupt sensitivity bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Table 20. Enabling/disabling active-halt and halt modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Table 21. Configuring the dividing factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Table 22. AWU register mapping and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Table 23. DR Value and output pin status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Table 24. I/O port mode options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Table 25. ST7FOXF1/ST7FOXK1/ST7FOXK2 I/O port configuration . . . . . . . . . . . . . . . . . . . . . . . . 75

Table 26. Effect of low power modes on I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Table 27. Description of interrupt events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Table 28. PA5:0, PB7:0, PC7:4 and PC2:0 pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Table 29. PA7:6 pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Table 30. PC3 pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Table 31. Port configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Table 32. I/O port register mapping and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Table 33. Watchdog timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Table 34. Watchdog timer register mapping and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Table 35. Effect of low power modes on autoreload timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Table 36. Description of interrupt events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Table 37. Counter clock selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Table 38. Register mapping and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Table 39. Effect of low power modes on Lite timer 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Table 40. Description of interrupt events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

Table 41. Lite Timer register mapping and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Table 42. Effect of low power modes on 16-bit timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

Table 43. 16-bit timer interrupt control/wakeup capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

Table 44. Summary of 16-bit timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

Table 45. 16-bit timer register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

Table 46. Effect of low power modes on the I

Table 47. Description of interrupt events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

Table 48. Configuratio n of I

C delay times. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

8/226

ST7FOXF1, ST7FOXK1, ST7FOXK2 List of tables

Table 49. I2C register mapping and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

Table 50. Low power mode descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

Table 51. Interrupt events. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

Table 52. SPI Master mode SCK Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

Table 53. SPI Register Map and Reset Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

Table 54. Effect of low power modes on the A/D converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

Table 55. Channel selection using CH[3:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

Table 56. Configuring the ADC clock speed. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

Table 57. ADC register mapping and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

Table 58. Description of addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

Table 59. ST7 addressing mode overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

Table 60. Instructions supporting inherent addressing mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

Table 61. Instructions supporting inherent immediate addressing mode . . . . . . . . . . . . . . . . . . . . . 180

Table 62. Instructions supporting direct, indexed, indirect and indirect indexed addressing modes 181

Table 63. Instructions supporting relative modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

Table 64. ST7 instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

Table 65. Illegal opcode detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

Table 66. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188

Table 67. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189

Table 68. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189

Table 69. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190

Table 70. Operating characteristics with LVD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190

Table 71. Internal RC oscillator characteristics (5.0 V calibration) . . . . . . . . . . . . . . . . . . . . . . . . . . 191

Table 72. Supply current characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

Table 73. On-chip peripheral characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193

Table 74. I Table 75. SCL frequency (multimaster I

C interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194

C interface). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194

Table 76. SPI interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

Table 77. General timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197

Table 78. External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198

Table 79. AWU from Halt characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198

Table 80. Crystal/ceramic resonator oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199

Table 81. RAM and hardware registers characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200

Table 82. Flash program memory characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200

Table 83. EMS test results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201

Table 84. EMI emissions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202

Table 85. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203

Table 86. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203

Table 87. General characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204

Table 88. Output driving current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205

Table 89. Asynchronous RESET pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206

Table 90. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209

Table 91. ADC accuracy with VDD = 4.5 to 5.5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210

Table 92. Startup clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211

Table 93. Selection of the resonator oscillator range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212

Table 94. Configuration of sector size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212

Table 95. Development tool order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216

Table 96. ST7 application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216

Table 97. 20-pin plastic small outline package, 300-mil width, mechanical data . . . . . . . . . . . . . . . 220

Table 98. 20-pin plastic dual in-line package, 300-mil width, mechanical data . . . . . . . . . . . . . . . . 221

Table 99. 32-pin plastic dual in-line package, shrink 400-mil width, mechanical data . . . . . . . . . . . 222

Table 100. 32-pin low profile quad flat package (7x7), package mechanical data . . . . . . . . . . . . . . . 223

9/226

List of tables ST7FOXF1, ST7FOXK1, ST7FOXK2

Table 101. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224

Table 102. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225

10/226

ST7FOXF1, ST7FOXK1, ST7FOXK2 List of figures

List of figures

Figure 1. General block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 2. 32-pin SDIP package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 5

Figure 3. 32-pin LQFP 7x7 package pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 4. 20-pin SO and DIP package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 5. ST7FOXF1/ST7FOXK1/ST7FOXK2 memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 6. Typical ICC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 7. CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 8. Stack manipulation example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 9. RCCRH_USER and RCCRL_USER programming flowchart. . . . . . . . . . . . . . . . . . . . . . . 35

Figure 10. RC user calibration programming cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 11. Clock switching. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 12. Clock management block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Figure 13. Reset sequence phases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Figure 14. Reset block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Figure 15. Reset sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Figure 16. Low voltage detector vs reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Figure 17. Reset and supply management block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Figure 18. Interrupt processing flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Figure 19. Priority decision process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Figure 20. Concurrent interrupt management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Figure 21. Nested interrupt management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Figure 22. Power saving mode transitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Figure 23. Slow mode clock transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Figure 24. Wait mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Figure 25. Active-halt timing overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Figure 26. Active-halt mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Figure 27. Halt timing overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Figure 28. Halt mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Figure 29. AWUFH mode block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Figure 30. AWUF halt timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Figure 31. AWUFH mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Figure 32. I/O port general block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Figure 33. Interrupt I/O port state transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Figure 34. Watchdog block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Figure 35. Single timer mode (ENCNTR2=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Figure 36. Dual timer mode (ENCNTR2=1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Figure 37. PWM polarity inversion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Figure 38. PWM function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Figure 39. PWM signal from 0% to 100% duty cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Figure 40. Dead time generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Figure 41. ST7FOXF1/ST7FOXK1 Block diagram of break function. . . . . . . . . . . . . . . . . . . . . . . . . . 88

Figure 42. ST7FOXK2 Block diagram of break function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Figure 43. Block diagram of output compare mode (single timer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Figure 44. Block diagram of input capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Figure 45. Input capture timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Figure 46. Long range input capture block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Figure 47. Long range input capture timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Figure 48. Block diagram of one pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

11/226

List of figures ST7FOXF1, ST7FOXK1, ST7FOXK2

Figure 49. One pulse mode and PWM timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Figure 50. Dynamic DCR2/3 update in one pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Figure 51. Force overflow timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Figure 52. Lite timer 2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Figure 53. Input Capture timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

Figure 54. Watchdog timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Figure 55. Timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Figure 56. 16-bit read sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

Figure 57. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

Figure 58. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

Figure 59. Counter timing diagram, internal clock divided by 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

Figure 60. Input capture block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

Figure 61. Input capture timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

Figure 62. Output compare block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

Figure 63. Output compare timi ng diagram, f Figure 64. Output compare timi ng diagram, f

TIMER=fCPU TIMER=fCPU

/2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

/4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

Figure 65. One pulse mode sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

Figure 66. One pulse mode timing example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

Figure 67. Pulse width modulation mode timing example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

Figure 68. Pulse width modulation cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

Figure 69. I Figure 70. I

C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

C interface block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

Figure 71. Transfer sequencing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

Figure 72. Event flags and interrupt generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

Figure 73. Serial peripheral interface block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

Figure 74. Single master/ single slave application. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

Figure 75. Generic SS timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

Figure 76. Hardware/software slave select management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

Figure 77. Data clock timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

Figure 78. Clearing the WCOL bit (write collision flag) software sequence. . . . . . . . . . . . . . . . . . . . 166

Figure 79. Single master / multiple slave configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

Figure 80. ADC block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

Figure 81. Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

Figure 82. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188

Figure 83. SPI slave timing diagram with CPHA=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

Figure 84. SPI slave timing diagram with CPHA=1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

Figure 85. SPI master timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197

Figure 86. Typical application with an external clock source. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198

Figure 87. Typical application with a crystal or ceramic resonator. . . . . . . . . . . . . . . . . . . . . . . . . . . 199

Figure 88. Two typical applications with unused I/O pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204

Figure 89. RESET pin protection when LVD is enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207

Figure 90. RESET pin protection when LVD is disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208

Figure 91. Typical application with ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209

Figure 92. ADC accuracy characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210

Figure 93. ST7FOXF1/ST7FOXK1/ST7FOXK2 ordering information scheme . . . . . . . . . . . . . . . . . 214

Figure 94. 20-pin plastic small outline package, 300-mil width, package outline. . . . . . . . . . . . . . . . 220

Figure 95. 20-pin plastic dual in-line package, 300-mil width, package outline . . . . . . . . . . . . . . . . . 221

Figure 96. 32-pin plastic dual in-line package, shrink 400-mil width, package outline. . . . . . . . . . . . 222

Figure 97. 32-pin low profile quad flat package (7x7), package outline. . . . . . . . . . . . . . . . . . . . . . . 223

12/226

ST7FOXF1, ST7FOXK1, ST7FOXK2 Description

1 Description

The ST7FO X is a member of th e ST7 microcon troller family. All ST7 devices are based on a common industry-standard 8-bit core, featuring an enhanced instruction set.

The device is positioned at the entry level of the 8-bit microcontroller range providing an attractive cost while at the same time embedding the most advanced features.

The ST7FO X features Flash memory with byte-by-by te In-Circuit Prog r amming (ICP) and InApplication Programming (IAP) capability.

Under software control, the ST7FOX device can be placed in Wait, Slow, or Halt mode, reducing power consumption when the application is in idle or standby state.

The enhanced instruction set and addressing modes of the ST7 offer both power and flexibility to software developers, enabling the design of highly efficient and compact application code. In addition to standard 8-bit data management, all ST7 microcontrollers feature true bit manipulation, 8x8 unsigned multiplication and indirect addressing modes.

The ST7FOX features an on-chip Debug Module (DM) to support In-Circuit Debugging (ICD). For a description of the DM registers, refer to the ST7 ICC Protocol Reference Manual.

Table 1. Device summary

Features ST7FOXF1 / ST7FOXK1 ST7FOXK2

Program memory - bytes 4K 8K

RAM (stack) - bytes 384 (128)

Timers

ADC 1 x 10-bit

Peripherals I²C I²C and SPI

Packages DIP20, SO20, LQFP32, SDIP32 LQFP32, SDIP32

Dual 8-bit timer,

dual 12-bit AT (4 PWM)

Dual 8-bit timer, dual 12-bit AT

(4 PWM), 1 x 16-bit timer

13/226

Description ST7FOXF1, ST7FOXK1, ST7FOXK2

Figure 1. General block diagram

CLKIN

OSC1

OSC2

RESET

Ext.

OSC

1 MHz

16 MHz

Int.

8 MHz

RC OSC

Int.

32 kHz

RC OSC

/ 2

LVD

Power

Supply

Control

8-bit core

ALU

Flash

Program

Memory

(4 to 8 Kbytes)

RAM

(384 bytes)

Internal clock

12-bit

8-bit

Port A

Port B

Port C

PA7:0

(8 bits)

PB7:0

(8 bits)

PC7:0

(8 bits)

16-bit timer

Auto-reload

dual timer

dual Lite timer

ADDRESS AND DATA BUS

10-bit ADC

SPI

I2C

Watchdog

Debug module

Note 1 : available on 8K version only

14/226

ST7FOXF1, ST7FOXK1, ST7FOXK2 Pin description

2 Pin description

Figure 2. 32-pin SDIP package pinout

OCMP1_A1)/PA0(HS)

BREAK1/PC7

ATIC/PA1(HS) ATPWM0/PA2(HS) ATPWM1/PA3(HS)

ATPWM2/MCO/PA4(HS)

ATPWM3/PA5(HS)

I2CDATA/PA6(HS)

I2CCLK/PA7(HS)

OSC1/CLKIN

Note 1: Available on 8K version only

RESET

OSC2

SSA

ei2 2 3 4 5

ei0

6 7 8 9 10 11 12 13 14 15 16

ei1

ei2

PC6 PC5/BREAK2

31 30

PC4/LTIC

PC3/ICCCLK

PC2/ICCDATA

PC1/AIN9/ICAP2_A

PC0/AIN8/ICAP1_A

PB7/AIN7/SS/OCMP2_A PB6/AIN6/SCK

24 23

PB5/AIN5/EXTCLK_A

PB4/AIN4/MISO

PB3/AIN3/MOSI

PB2/AIN2

PB1/AIN1/CLKIN

PB0/AIN0

DDA

(HS) 20mA high sink capability eix associated external interrupt vector

Figure 3. 32-pin LQFP 7x7 package pinout

ATPWM1/PA3(HS)

ATPWM2/MCO/PA4(HS)

ATPWM3/PA5(HS)

I2CDATA/PA6(HS)

I2CCLK/PA7(HS)

RESET

PA2(HS)/ATPWM0

32 31 30 29 28 27 26 25

1 2

ei0

3 4 5 6 7 8

9 10111213141516

PC6

PA1(HS)/ATIC

PC5/BREAK2

PA0(HS)/OCMP1_A

PC7/BREAK1

ei2

ei1

SSA

DDA

OSC2

OSC1/CLKIN

AIN0/PB0

PC4/LTIC

PC3/ICCCLK

PC2/ICCDATA

PC1/AIN9/ICAP2_A

PC0/AIN8/ICAP1_A

PB7/AIN7/SS

PB6/AIN6/SCK

PB5/AIN5/EXTCLK_A

PB4/AIN4/MISO

PB3/AIN3/MOSI

AIN2/PB2

CLKIN/AIN1/PB1

(HS) 20mA high sink capability eix associated external interrupt vector

/OCMP2_A

15/226

Pin description ST7FOXF1, ST7FOXK1, ST7FOXK2

Legend / Abbreviations for Table 2: Type: I = input, O = output, S = supply In/Output level: C

= CMOS 0.3VDD/0.7VDD with input trigger

Output level: HS = 20 mA high sink (on N-buffer only)

Port and control configuration:

● Input: float = floating, wpu = we ak pull-up, int = interrupt, ana = analog

● Output: OD = open drain, PP = push-pull

The RESET configuration of each pin is shown in bold which is v alid as long as the de vice is in reset state.

Table 2. Device pin description (32-pin packages)

number

LQFP32

1 5 PA3(HS)/ATPWM1 I/O CTHS x

SDIP32

ATPWM2/MCO

Pin name

PA4(HS)/

Level Port/control

Type

Input

Output

float

I/O C

HS x xx

Input Output

ana

(1)

int

wpu

ei0

Main

function

(after

reset)

Port A3

(HS)

Port A4

(HS)

Alternate

function

ATPWM1

ATPWM2/

MCO

3 7 PA5 (HS)ATPWM3 I/O C

PA6(HS)/

I2CDATA/SCK

PA7(HS)/I2CCLK/SS

(2)

I/O CTHS x

I/O CTHS x T

HS x xx

ei0

Port A5

(HS)

Port A6

(HS)

Port A7

(HS)

ATPWM3

I2CDATA/SPI

serial clock

I2CCLK/SPI

slave select

(active low) 6 10 RESET x x Reset 812 V 913 V

DD SS

(3) (3)

S Digital Supply Voltage S Digital Ground Voltage

Resonator oscillator

10 14 OSC1/CLKIN I

inverter input or External

clock input 11 15 OSC2 O Resonator oscillator output 12 16 V 13 17 V

SSA DDA

(3) (3)

S Analog Ground Voltage S Analog Supply Voltage

16/226

ST7FOXF1, ST7FOXK1, ST7FOXK2 Pin description

Table 2. Device pin description (32-pin packages) (continued)

number

Pin name

SDIP32

LQFP32

Type

14 18 PB0/AIN0 I/O C

15 19 PB1/AIN1/CLKIN I/O C

16 20 PB2/AIN2 I/O C

(2)

I/O C

17 21 PB3/AIN3/MOSI

18 22 PB4/AIN4/MISO

19 23

PB5/AIN5/

EXTCLK_A

20 24 PB6/AIN6/SCK

21 25

22 26

23 27

PB7/AIN7/SS

OCMP2_A

PC0/AIN8/

ICAP1_A

PC1/AIN9/

ICAP2_A

24 28 PC2/ICCDATA I/O C 25 29 PC3/ICCCLK I/O C 26 30 PC4/LTIC I/O C

(4)

27 31 PC5/BREAK2

I/O C 28 32 PC6 I/O C 29 1 PC7/BREAK1 I/O C

Level Port/control

Input Output

Input

Output

float

x xxx Port B1

x xxx Port B2 AIN2

x xxx Port B3

x xxx Port B4

int

wpu

ana

xxxPort B0 AIN0

ei1

x xxx Port B5

x xxx Port B6

x xxx Port B7

xxxPort C0

ei2

T T T T T T

x xxx Port C1

x xxPort C2 ICCDATA x x xxPort C3 ICCCLK x x xxPort C5 BREAK2 x xx Port C6

ei2

x xxPort C7 BREAK1

Main

(1)

function

(after

reset)

Alternate

function

AIN1/Externa

l clock source

AIN3/SPI

Master out

/Slave in data

AIN4/SPI

Master

in/Slave out

data

AIN5/Timer A

input clock

AIN6/SPI

serial clock

AIN7/SPI

slave select

(active low)/

Timer A

Output

Compare 2

AIN8/Timer A

Input

Capture 1

AIN9/Timer A

Input

Capture 2

xxPort C4 LTIC

17/226

Pin description ST7FOXF1, ST7FOXK1, ST7FOXK2

Table 2. Device pin description (32-pin packages) (continued)

number

Pin name

SDIP32

LQFP32

30 2

(HS)

PA0

(5)

/OCMP1_A

(2)

31 3 PA1 (HS)/ATIC I/O CTHS x xx

32 4 PA2 (HS)/ATPWM0 I/O C

1. In the open-drain output column, T defines a true open-drain I/O (P-Buffer and protection diode to VDD are not implemented).

2. Available on ST7FOXK2 only.

3. It is mandatory to connect all available V

4. BREAK2 available on ST7FOXK2 only

5. Available on ST7FOXK1 only.

Level Port/control

Type

Input

Output

float

I/O C

(5)

HS x xx

and V

pins to the supply voltage and all VSS and V

DDA

Input Output

ana

(1)

int

wpu

ei0

Main

function

(after

reset)

Port A0 (HS)

Output Compare 1

Port A1

(HS)

Port A2

(HS)

pins to ground.

SSA

Figure 4. 20-pin SO and DIP package pinout

Alternate

function

(5)

/ Timer A

ATIC

ATPWM0

ei2

ei0

ei2

ei1

PC4/LTIC

PC3/ICCCLK

PC2/ICCDATA

PB5/AIN5

PB4/AIN4

PB3/AIN3

PB2/AIN2

PB1/AIN1/CLKIN

PB0/AIN0

(HS) 20mA high sink capability eix associated externalinterrupt vector

PC6

ATIC/PA1(HS) ATPWM0/PA2(HS) ATPWM1/PA3(HS)

ATPWM2/MCO/PA4(HS)

ATPWM3/PA5(HS)

I2CDATA/PA6(HS)

I2CCLK/PA7(HS)

RESET

1 2 3 4 5 6 7 8 9 10

Legend / Abbreviations for Table 3: Type: I = input, O = output, S = supply In/Output level:CT= CMOS 0.3VDD/0.7VDD with input trigger Output lev el: HS = 20mA high sink (on N-buffer only) Port and control configuration:

● Input: float = floating, wpu = we ak pull-up, int = interrupt, ana = analog

● Output: OD = open drain, PP = push-pull

Note: The RESET configuration of each pin is shown in bold which is valid as long as the device is

in reset state.

18/226

ST7FOXF1, ST7FOXK1, ST7FOXK2 Pin description

Table 3. Device pin description (20-pin package)

Level Port / Control

function

(after reset)

Main

SSA

Alternate

function

AIN1/External

clock source

pins to ground.

Number

Pin Name

1 PC6 I/O C 2 PA1 (HS)/ATIC I/O C 3 PA2 (HS)/ATPWM0 I/O C 4 PA3 (HS)/ATPWM1 I/O C

PA4

(HS)ATPWM2/MCO

Type

I/O C

Input Output

Input

Output

float

T T T T

x ei2 x x Port C6 HS x HS x x x Port A2 (HS) ATPWM0 HS x x x Port A3 (HS) ATPWM1

HS x x x Port A4 (HS) ATPWM2/MCO

wpu

ei0

int

ana

(1)

x x Port A1 (HS) ATIC

6 PA5 (HS)ATPWM3 I/O CTHS x x x Port A5 (HS) ATPWM3 7 PA6 (HS)/I2CDATA I/O C 8 PA7 (HS)/ I2CCLK I/O C

HS x T Port A6 (HS) I2CDATA

HS x T Port A7 (HS) I2CCLK

9 RESET x x Reset 10 V 11 V 12 PB0/AIN0 I/O C

13 PB1/AIN1/CLKIN I/O C

14 PB2/AIN2 I/O C 15 PB3/AIN3 I/O C 16 PB4/AIN4 I/O C 17 PB5/AIN5 I/O C 18 PC2/ICCDATA I/O C 19 PC3/ICCCLK I/O C 20 PC4/LTIC I/O C

1. In the open-drain output column, T defines a true open-drain I/O (P-Buffer and protection diode to VDD not implemented).

2. It is mandatory to connect all available V

SS DD

(3) (2)

S Digital Ground Voltage S Digital Supply Voltage

T T T T T T T

and V

xxxxPort B1

x x x x Port B2 AIN2

ei1

x x x x Port B3 AIN3 x x x x Port B4 AIN4 x x x x Port B5 AIN5 x ei2 x x Port C2 ICCDATA x x x Port C3 ICCCLK x ei2 x x Port C4 LTIC

pins to the supply voltage and all VSS and V

DDA

x x x Port B0 AIN0

19/226

3 Register and memory mapping

As shown in Figure 5, the MCU is capable of addressing 64 Kbytes of memories and I/O registers.

The availab le memory locations consist of 128 b ytes of r egister locations , 384 b yte s of RAM and 4 to 8 Kbytes of Flash program memory. The RAM space includes up to 128 bytes for the stack from 180h to 1FFh.

The highest address bytes contain the user reset and interrupt vectors. The Flash memory contains two sectors (see Figure 5) mapped in the upper part of the ST7

addressing space so the reset and interrupt vectors are locat ed in Sector 0 (FFE0h -FFFFh). The size of Flash Sector 0 and other device options are configurable by option bytes (refer

to Section 13.1 on page 211).

Caution: Memory locations marked as “Reserved” must never be accessed. Accessing a reserved

area can have unpredictable effects on the device.

Figure 5. ST7FOXF1/ST7FOXK1/ST7FOXK2 memory map

0000h 007Fh

0080h

01FFh 0200h

DFFFh

E000h

EFFFh

F000h

F7FFh

F800h

FFDFh FFE0h

FFFFh

HW registers

(seeTable 8)

RAM

(384 bytes)

Reserved

Flash Memory

(8 Kbytes)

(4 Kbytes)

Interrupt & Reset Vectors

(see Table 17)

0080h

00FFh 0100h

017Fh

0180h

01FFh

Short Addressing RAM (zero page)

RAM

128 bytes Stack

8 or 4 Kbytes

Flash program memory

Sector 1 Sector 0

(4 Kbytes) (2 Kbytes) (1 Kbyte)

(0.5 Kbyte)

E000h

FFFFh

1000h 1001h

DEE0h DEE1h

RCCRH_USER

RCCRL_USER

RCCRH RCCRL

see Section 6.1.1

20/226

ST7FOXF1, ST7FOXK1, ST7FOXK2 Register and memory mapping

Table 4. Hardware register map

(1)

Address Block Register label Register name Reset status Remarks

0000h 0001h 0002h

0003h 0004h 0005h

0006h 0007h 0008h

0009h to

000Bh

000Ch 000Dh 000Eh 000Fh

0010h 0011h

0012h 0013h 0014h 0015h 0016h 0017h 0018h

0019h 001Ah 001Bh 001Ch 001Dh 001Eh 001Fh

0020h

0021h

0022h

0023h

0024h

0025h

0026h

0027h

0028h

0029h 002Ah

Port A

Port B

Port C

LITE

TIMER

AUTO-

RELOAD

TIMER

PADR

PADDR

PAOR

PBDR

PBDDR

PBOR PCDR

PCDDR

PCOR

LTCSR2

LTARR

LTCNTR

LTCSR1

LTICR

ATCSR

CNTR1H

CNTR1L

ATR1H

ATR1L

PWMCR PWM0CSR PWM1CSR PWM2CSR PWM3CSR

DCR0H DCR0L DCR1H DCR1L DCR2H DCR2L DCR3H DCR3L

ATICRH

ATICRL

ATCSR2

BREAKCR1

ATR2H

ATR2L DTGR

BREAKEN

Port A Data register

Port A Data Direction register

Port A Option register

Port B Data register

Port B Data Direction register

Port B Option register

Port C Data register

Port C Data Direction register

Port C Option register

Reserved area (3 bytes)

Lite Timer Control/Status register 2

Lite Timer Auto-reload register

Lite Timer Counter register

Lite Timer Control/Status register 1

Lite Timer Input Capture register

Timer Control/Status register

Counter register 1 High

Counter register 1 Low

Auto-Reload register 1 High

Auto-Reload register 1 Low

PWM Output Control register PWM 0 Control/Status register PWM 1 Control/Status register PWM 2 Control/Status register PWM 3 Control/Status register

PWM 0 Duty Cycle register High

PWM 0 Duty Cycle register Low

PWM 1 Duty Cycle register High

PWM 1 Duty Cycle register Low

PWM 2 Duty Cycle register High

PWM 2 Duty Cycle register Low

PWM 3 Duty Cycle register High

PWM 3 Duty Cycle register Low

Input Capture register High

Input Capture register Lo w

Timer Control/Status register 2

Break Control register

Auto-Reload register 2 High

Auto-Reload register 2 Low

Dead Time Generation register

Break Enable register

00h 00h 00h

00h 00h 08h

0Fh 00h 00h

0x00 0000b

xxh

0x00 0000b

00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 03h 00h 00h 00h 00h 03h

R/W R/W R/W

R/W R/W

Read Only

R/W

Read Only

R/W Read Only Read Only

R/W

R/W Read Only Read Only

R/W

002Bh Reserved area (1 byte)

002Ch

AUTO-

RELOAD

BREAKCR2

(4)

Break Control register 2

(4)

00h R/W

TIMER

21/226

Table 4. Hardware register map

(1)

(continued)

Address Block Register label Register name Reset status Remarks

002Dh 002Eh 002Fh

0030h 0031h

ITC

ISPR0 ISPR1 ISPR2 ISPR3

EICR

Interrupt Software Priority register 0 Interrupt Software Priority register 1 Interrupt Software Priority register 2 Interrupt Software Priority register 3

External Interrupt Control register

FFh FFh FFh FFh

00h

R/W

0032h Reserved area (1 byte) 0033h WDG WDGCR Watchdog Control register 7Fh R/W 0034h FLASH FCSR Flash Con tro l /St at us re gi ster 00h R/W

0035h

0036h 0037h 0038h

Calibration

ADC

RCC_CSR RC calibration Control/Status register 00h R/W

ADCCSR ADCDRH

ADCDRL

A/D Control Status register

A/D Data register High

A/D Data Low / test register

00h xxh 0xh

R/W Read Only

R/W

0039h Reserved area (1 byte) 003Ah MCC MCCSR Main Clock Control/Status register 00h R/W 003Bh

003Ch 003Dh

Clock and

Reset

RCCRH

RCCRL

PSCR

RC oscillator Control register High

RC oscillator Control register Low

Prescaler register

FFh

011x 0x00b

00h or 03h

(2)

R/W R/W R/W

003Eh to

0047h

0048h

0049h 004Ah

004Bh 004Ch 004Dh 004Eh 004Fh

0050h

0051h

0052h to

0054h

AWU

(3)

Clock

Controller

Reserved area (10 bytes)

AWUCSR

AWUPR

DMCR DMSR

DMBK1H

DMBK1L

DMBK2H

DMBK2L

DMCR2

AWU Control/Status register

AWU Preload register

DM Control register

DM Status register

DM Breakpoint register 1 High

DM Breakpoint register 1 Low

DM Breakpoint register 2 High

DM Breakpoint register 2 Low

DM Control register 2

FFh

00h 00h

00h 00h 00h 00h 00h 00h

R/W R/W

R/W R/W R/W R/W R/W R/W R/W

CKCNTCSR Clock Controller Status register 09h R/W

Reserved area (3 bytes)

22/226

ST7FOXF1, ST7FOXK1, ST7FOXK2 Register and memory mapping

Table 4. Hardware register map

(1)

(continued)

Address Block Register label Register name Reset status Remarks

0055h

0056h

0057h

0058h

0059h 005Ah 005Bh 005Ch 005Dh

16-bit

Timer

(4)

005Eh 005Fh

0060h

0061h

0062h

0063h

0064h

0065h

0066h

0067h

I2C 0068h 0069h

006Ah

0070h 0071h

SPI

(4)

0072h

1. Legend: x=undefined, R/W=read/write.

2. Reset status is 03h for ST7FOXK2 and 00h for ST7FOXF1 and ST7FOXK1

TACR2 TACR1

TACSR TAICHR1 TAICLR1

TAOCHR1 TAOCLR1

TACHR

TACLR TAACHR

TAACLR

TAICHR2 TAICLR2

TAOCHR2 TAOCLR2

I2CCR I2CSR1 I2CSR2

I2CCCR I2COAR1 I2COAR2

I2CDR

SPIDR SPICR

SPISR

Timer A Control register 2 Timer A Control register 1

Timer A Control/status register

Timer A Input capture 1 high register

Timer A Input capture 1 low register

Timer A Output compare 1 high register

Timer A Output compare 1 low register

Timer A Output counter high register

Timer A Output counter low register

Timer A Alternate counter high register

Timer A Alternate counter low register

Timer A Input capture 2 high register

Timer A Input capture 2 low register

Timer A Output compare 2 high register

Timer A Output compare 2 low register

C Control register

C Status register 1

I I2C Status register 2

C Clock Control register

I I2C Own Address register 1 I2C Own Address register 2

C Data register

I SPI Data register

SPI Control register

SPI Status register

00h 00h 00h xxh xxh 80h

00h FFh FCh FFh FCh

xxh

80h

00h

40h

00h

0xh

00h

xxh

R/W

R/W Read Only Read Only Read Only

R/W

R/W Read Only Read Only Read Only Read Only Read Only Read Only

R/W

Read only Read only

R/W

3. For a description of the Debug Module registers, see ICC protocol reference manual.

4. Available on ST7FOXK2 only

23/226

Flash programmable memory ST7FOXF1, ST7FOXK1, ST7FOXK2

4 Flash programmable memory

4.1 Introduction

The ST7 single voltage extended Flash (XFlash) is a non-volatile memory that can be electrically erased and programmed either on a byte-by-byte basis or up to 32 bytes in parallel.

The XFlash devices can be prog rammed off-board (plugged in a programming tool) or onboard using In-Circuit Programming or In-Application Programming.

The array matrix organization allows each sector to be erased and reprogrammed without affecting other sectors.

4.2 Main features

● ICP (In-Circuit Programming)

● IAP (In-Application Programming)

● ICT (In-Circuit Testing) for downloading and executing user application test patterns in

RAM

● Sector 0 size configurable by option byte

● Read-out and write protection

4.3 Programming modes

The ST7 can be programmed in three different ways:

● Insertion in a programming tool. In this mode, Flash sectors 0 and 1, option byte row

can be programmed or erased.

● In-Circuit Programming. In this mode, Flash sectors 0 and 1, option byte row can be

programmed or erased without removing the device from the application board.

● In-Application Programming. In this mode, sector 1 can be programmed or erased

without removing the de vice from the application board and while the application is running.

4.3.1 In-Circuit Programming (ICP)

ICP uses a protocol called ICC (In-Circuit Communication) which allows an ST7 plug ged on a printed circuit board (PCB) to communicate with an external programming device connected via cable. ICP is performed in three steps:

Switch the ST7 to ICC mode (In-Circuit Communications). This is done by driving a specific signal sequence on the ICCCLK/DATA pins while the RESET ST7 enters ICC mode, it fetches a specific Reset vector which points to the ST7 System Memory containing the ICC protocol routine. This routine enables the ST7 to receive bytes from the ICC interface.

● Download ICP Driver code in RAM from the ICCDATA pin

● Execute ICP Driver code in RAM t o program the Flash memory

pin is pulled low. When the

24/226

ST7FOXF1, ST7FOXK1, ST7FOXK2 Flash programmable memory

Depending on the ICP Driver code downloaded in RAM, Flash memory programming can be fully customized (number of bytes to program, program locations, or selection of the serial communication interface for downloading).

4.3.2 In Application Programming (IAP)

This mode uses an IAP Driver program previously programmed in Sector 0 by the user (in ICP mode).

This mode is fully controlled by user softwa re. This allows it to be adapted to the user application, (user-defined strategy for entering programming mode, choice of communications protocol used to fetch the data to be stored etc.) IAP mode can be used to progr am an y memory areas e xcept Sector 0, which is Write/Erase protected to allow recovery in case errors occur during the programming operatio n.

4.4 ICC interface

ICP needs a minimum of 4 and up to 6 pins to be connected to t he progr amming tool. These pins are:

● RESET: device reset

● V

● ICCCLK: ICC output serial clock pin

● ICCDATA: ICC input serial data pin

● OSC1: main clock input for external source

● V

Note: 1 If the ICCCLK or ICCDATA pins are only used as outputs in the app licat ion , no sign al

isolation is necessary. As soon as the Programming Tool is plugged to the board, even if an ICC session is not in progress, the ICCCLK and ICCDATA pins are not available for the application. If they are used as inputs by the application, isolation such as a serial resistor has to be implemented in case another device forces the signal. Refer to the Programming Tool documentation for recommended resistor values.

2 During the ICP session, the programming tool must control the RESET

conflicts between the programming tool a nd the application reset circuit if it d rives more than 5mA at high level (push pull output or pull-up resistor<1 k to isolate the application RESET circuit in this case. When using a classical RC network with R>1 k additional components are needed. In all cases the user must ensure that no external reset is generated by the application during the ICC session.

3 The use of pin 7 of the ICC connector depends on the Programming Tool architecture. This

pin must be connected when using most ST Programming Tools (it is used to monitor the application power supply). Please refer to the Programming Tool manual.

4 In “enabled option byte” mode (38-pulse ICC mode), the internal RC oscillator is forced as a

clock source, regardless of the selection in the option byte. In “disabled option byte” mode (35-pulse ICC mode), pin 9 has to be co nne cted t o t he PB1/ CLKI N pi n o f th e ST7 when the clock is not available in the application or if the selected clock option is not programmed in the option byte.

: device power supply ground

: application board power supply (optional, see Note 3)

pin. This can lead to

Ω

). A schottky diode can be used

Ω

or a reset management IC with open drain output and pull-up resistor>1 kΩ, no

Caution: During normal operation the ICCCLK pin must be in ternally or externally pulled- up (e xternal

pull-up of 10 kΩ mandatory in noisy environment) to a v oid entering ICC mode unexpectedly

25/226

Flash programmable memory ST7FOXF1, ST7FOXK1, ST7FOXK2

during a reset. In the application, even if the pin is configured as output, any reset will put it back in input pull-up.

Figure 6. Typical ICC Interface

PROGRAMMING TOOL

ICC CONNECTOR

ICC Cable

ICC CONNECTOR

(See Note 3)

OPTIONAL

(See Note 4)

HE10 CONNECTOR TYPE

975 3

1 246810

APPLICATION BOARD

APPLICATION RESET SOURCE

See Note 2

APPLICATION POWER SUPPLY

VDD

ST7

PB1/CLKIN

RESET

ICCCLK

See Note 1 and Caution

See Note 1

ICCDATA

APPLICATION

I/O

26/226

ST7FOXF1, ST7FOXK1, ST7FOXK2 Flash programmable memory

4.5 Memory protection

There are two different types of memory protection: Read-Out Protection and Write/Erase Protection which can be applied individually.

4.5.1 Read-out protection

Read-Out Protection, when selected prov ides a protection against program me mory content extraction and against write access to Flash memory. Ev en if no protection can be considered as totally unbreakable, the feature provides a very high level of protection for a general purpose microcontroller.

● In Flash devices, this protection is removed by reprogramming the option. In this case,

the program memory is automatically erased and the device can be reprogrammed. The read-out protection is enabled and removed through the FMP_R bit in t he option byte.

4.5.2 Flash write/erase protection

Write/Erase Protection, when set, makes it impossible to both overwrite and erase program memory . Its purpose is to provide adv anced security to applica tions and pre ven t any change being made to the memory content. Write/Erase Protection is enabled through the FMP_W bit in the option byte.

Caution: Once set, Write/Erase Protection can never be removed. A write-protected Flash

device is no longer reprogrammable.

4.6 Related documentation

For details on Flash programming and ICC protocol, refer to the ST7 Flash Programming Reference Manual and to the ST7 ICC Protocol Reference Manual

27/226

Flash programmable memory ST7FOXF1, ST7FOXK1, ST7FOXK2

4.7 Description of Flash Control/Status register (FCSR)

This register controls the XFlash erasin g and programming using ICP, IAP or other programming methods.

1st RASS Key: 0101 0110 (56h) 2nd RASS Key: 1010 1110 (AEh) When an EPB or another programming tool is used (in socke t or ICP mode), the RASS ke ys

are sent automatically. Reset value: 000 0000 (00h)

7 0 00000OPTLATPGM

Read/write

Table 5. Flash register mapping and reset values

Address

(Hex.)

0034

label

FCSR

Reset Value

76543210

OPT

LAT

PGM

28/226

ST7FOXF1, ST7FOXK1, ST7FOXK2 Central processing unit

5 Central processing unit

5.1 Introduction

This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8bit data manipulation.

5.2 Main features

● 63 basic instructions

● Fast 8-bit by 8-bit multiply

● 17 main addressing modes

● Two 8-bit index registers

● 16-bit stack pointer

● Low power modes

● Maskable hardware inter rupts

● Non-maskable software interrupt

5.3 CPU registers

The six CPU registers shown in Figure 7. They are n ot present in the memo ry mapping and are accessed by specific instructions.

Figure 7. CPU registers

15 8

RESET VALUE = RESET VECTOR @ FFFEh-FFFFh

RESET VALUE = STACK HIGHER ADDRESS

PCH

RESET VALUE =

RESET VALUE = XXh

PCL

70 1C11HI NZ 1X11X1XX

ACCUMULATOR

X INDEX REGISTER

Y INDEX REGISTER

PROGRAM COUNTER

CONDITION CODE REGISTER

STACK POINTER

X = Undefined Value

29/226

Central processing unit ST7FOXF1, ST7FOXK1, ST7FOXK2

5.3.1 Accumulator (A)

The Accumulator is an 8-bit general purpose register used to hold operands and the re su lts of the arithmetic and logic calculations and to manipulate data.

5.3.2 Index registers (X and Y)

In indexed addressing modes, these 8-bit registers are used to create either effective addresses or temporary storage areas for data manipulation. (The Cross-Assembler generates a precede instruction (PRE) to indicate that the following instruction refers to the Y register.)

The Y register is not affected by the interrupt automatic procedures (not pushed to and popped from the stack).

5.3.3 Pr ogram Counter (PC)

The Program Counter is a 16 -bit registe r containin g the a ddress of the ne xt instruction to be exe cuted by the CPU. It is made of two 8-bit registers PCL (Program Counter low which is the LSB) and PCH (Program Counter high which is the MSB).

5.3.4 Condition Code register (CC)

The 8-bit Condition Code register contains the interrupt mask and four flags representat ive of the result of the instruction just executed. This register can also be handled b y the PUSH and POP instructions.

Reset value: 111x 1xxx

7 0 11I1HI0NZC

Read/write

These bits can be individually tested and/or controlled by specific instructions.

Arithmetic management bits

Bit 4 = H Half carry bit

This bit is set by hard war e when a carry occurs between bit s 3 and 4 of the ALU during an ADD or ADC instruction. It is reset by hardware during the same instructions.

0: No half carry has occurred. 1: A half carry has occurred.

This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD arithmetic subroutines.

30/226

+ 196 hidden pages