ST ST7FOXF1, ST7FOXK1, ST7FOXK2 User Manual

ST7FOXF1, ST7FOXK1, ST7FOXK2

8-bit MCU with single voltage Flash memory,

Features

■ Memories

– 4 to 8 Kbytes single voltage extended Flash

(XFlash) Program memory with Read-Out Protection In-Circuit Programming and In-Application programming (ICP and IAP) Endurance: 1K write/erase cycles guaranteed Data retention: 20 years at 55 °C

– 384 bytes RAM

■ Clock, Reset and Supply Management

– Low voltage supervisor (LVD) for safe

power-on/off

– Clock sources: Intern al trimmable 8 MHz

RC oscillator, auto wakeup internal low power - low frequency oscillator,

crystal/ceramic resonator or external clock – External reset source and watchdog reset – Five power saving modes: Halt, Active-Halt,

Auto Wakeup from Halt, Wait and Slow

■ I/O Ports

– Up to 24 multifunctional bidirectional I/Os – Up to 8 high sink outputs

SPI, I²C, ADC, timers

DIP20

■ 6 timers

SO20

– Configurable watchdog timer – Dual 8-bit Lite timers with prescaler,

1 real time base and 1 input capture

– Dual 12-bit Auto-reload timers with 4 PWM

outputs, input capture, output compare, dead-time generation and enhanced one pulse mode functions

– One 16-bit timer

■ Communication interfaces:

– I²C multimaster interface – SPI synchronous serial interface

■ A/D converter: up to 10 input channels

■ Interrupt management

– 13 interrupt vectors plus TRAP and RESET

■ Instruction set

– 8-bit data manipulation – 63 basic instructions with illegal opcode

detection – 17 main addressing modes – 8 x 8 unsigned multiply instructions

■ Development tools

– Full HW/SW development package – DM (Debug Module)

LQFP32 SDIP32

February 2008 Rev 4 1/226

www.st.com

Contents ST7FOXF1, ST7FOXK1, ST7FOXK2

Contents

1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3 Register and memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4 Flash programmable memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.3 Programming modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.3.1 In-Circuit Programming (ICP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.3.2 In Application Programming (IAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.4 ICC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.5 Memory protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

4.5.1 Read-out protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

4.5.2 Flash write/erase protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

4.6 Related documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

4.7 Description of Flash Control/Status register (FCSR) . . . . . . . . . . . . . . . . 28

5 Central processing unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

5.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

5.3 CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

5.3.1 Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

5.3.2 Index registers (X and Y) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

5.3.3 Program Counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

5.3.4 Condition Code register (CC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

5.3.5 Stack Pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

6 Supply, reset and clock management . . . . . . . . . . . . . . . . . . . . . . . . . . 34

6.1 RC oscillator adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

6.1.1 Internal RC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

6.1.2 Customized RC calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

6.1.3 Auto wakeup RC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

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6.2 Multi-oscillator (MO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

6.2.1 External clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

6.2.2 Crystal/ceramic oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

6.2.3 Internal RC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

6.3 Reset sequence manager (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

6.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

6.3.2 Asynchronous external RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

6.3.3 External power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

6.3.4 Internal Low Voltage Detector (LVD) reset . . . . . . . . . . . . . . . . . . . . . . . 42

6.3.5 Internal watchdog reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

6.4 System Integrity management (SI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

6.4.1 Low Voltage Detector (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

6.5 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

6.5.1 RC calibration control/status register (RCC_CSR) . . . . . . . . . . . . . . . . 46

6.5.2 Main Clock Control/Status Register (MCCSR) . . . . . . . . . . . . . . . . . . . 46

6.5.3 RC Control Register High (RCCRH) . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

6.5.4 RC Control Register Low (RCCRL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

6.5.5 Prescaler register (PSCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

6.5.6 Clock controller control/status register (CKCNTCSR) . . . . . . . . . . . . . . 49

7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

7.2 Masking and processing flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

7.2.1 Servicing pending interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

7.2.2 Interrupt vector sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

7.3 Interrupts and low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

7.4 Concurrent and nested management . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

7.5 Description of interrupt registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

7.5.1 CPU CC register interrupt bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

7.5.2 Interrupt software priority registers (ISPRx) . . . . . . . . . . . . . . . . . . . . . . 56

7.5.3 External Interrupt Control register (EICR) . . . . . . . . . . . . . . . . . . . . . . . 60

8 Power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

8.2 Slow mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

8.3 Wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

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8.4 Active-halt and halt modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

8.4.1 Active-halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

8.4.2 Halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

8.5 Auto-wakeup from Halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

8.5.1 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

8.5.2 AWUFH Control/Status Register (AWUCSR) . . . . . . . . . . . . . . . . . . . . 70

8.5.3 AWUFH prescaler register (AWUPR) . . . . . . . . . . . . . . . . . . . . . . . . . . 71

9 I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

9.2 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

9.2.1 Input modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

9.2.2 Output modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

9.2.3 Alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

9.2.4 Analog alternate function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

9.3 I/O port implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

9.4 Unused I/O pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

9.5 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

9.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

9.7 Device-specific I/O port configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

9.7.1 Standard ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

9.7.2 Other ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

10 On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

10.1 Watchdog timer (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

10.1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

10.1.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

10.1.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

10.1.4 Hardware watchdog option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

10.1.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

10.1.6 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

10.2 Dual 12-bit autoreload timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

10.2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

10.2.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

10.2.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

10.2.4 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

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10.2.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

10.2.6 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

10.3 Lite timer 2 (LT2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

10.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

10.3.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

10.3.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

10.3.4 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

10.3.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

10.3.6 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

10.4 16-bit timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

10.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

10.4.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

10.4.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

10.4.4 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

10.4.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

10.4.6 Summary of 16-bit timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

10.4.7 16-bit timer registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

10.4.8 16-bit timer register map and reset values . . . . . . . . . . . . . . . . . . . . . . 139

10.5 I2C bus interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

10.5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

10.5.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

10.5.3 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

10.5.4 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

Slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

Master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

10.5.5 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

10.5.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

10.5.7 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

10.6 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

10.6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

10.6.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

10.6.3 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

10.6.4 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

10.6.5 Clock phase and clock polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

10.6.6 Error flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

10.6.7 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

10.6.8 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

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10.6.9 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

10.7 10-bit A/D converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

10.7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

10.7.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

10.7.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

10.7.4 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

10.7.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

10.7.6 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

11 Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

11.1 ST7 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

11.1.1 Inherent mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

11.1.2 Immediate mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

11.1.3 Direct modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

11.1.4 Indexed modes (No Offset, Short, Long) . . . . . . . . . . . . . . . . . . . . . . . 180

11.1.5 Indirect modes (short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

11.1.6 Indirect indexed modes (short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . 181

11.1.7 Relative modes (direct, indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

11.2 Instruction groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

11.2.1 Illegal opcode reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

12 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

12.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

12.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

12.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

12.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

12.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

12.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

12.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188

12.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190

12.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190

12.3.2 Operating conditions with Low Voltage Detector (LVD) . . . . . . . . . . . . 190

12.3.3 Internal RC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191

12.4 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

12.4.1 Supply current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

12.4.2 On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193

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12.5 Communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . 194

12.5.1 I2C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194

12.5.2 SPI interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

12.6 Clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197

12.6.1 Auto wakeup from Halt oscillator (AWU) . . . . . . . . . . . . . . . . . . . . . . . 198

12.6.2 Crystal and ceramic resonator oscillators . . . . . . . . . . . . . . . . . . . . . . 199

12.7 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200

12.8 EMC (electromagnetic compatibility) characteristics . . . . . . . . . . . . . . . 201

12.8.1 Functional EMS (electromagnetic susceptibility) . . . . . . . . . . . . . . . . . 201

12.8.2 EMI (Electromagnetic interference) . . . . . . . . . . . . . . . . . . . . . . . . . . . 202

12.8.3 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 203

12.9 I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204

12.9.1 General characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204

12.9.2 Output driving current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205

12.10 Control pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206

12.10.1 Asynchronous RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206

12.11 10-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209

13 Device configuration and ordering information . . . . . . . . . . . . . . . . . 211

13.1 Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211

13.1.1 Option byte 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211

13.1.2 Option byte 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212

13.2 Device ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214

ST7FOX failure analysis service . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214

13.3 Development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215

13.3.1 Starter kits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215

13.3.2 Development and debugging tools . . . . . . . . . . . . . . . . . . . . . . . . . . . 215

13.3.3 Programming tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215

13.3.4 Order codes for development and programming tools . . . . . . . . . . . . . 215

13.4 ST7 application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216

14 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220

14.1 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224

15 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225

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List of tables ST7FOXF1, ST7FOXK1, ST7FOXK2

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 2. Device pin description (32-pin packages). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 3. Device pin description (20-pin package). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 4. Hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 5. Flash register mapping and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 6. Interrupt software priority truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 7. Predefined RC oscillator calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 8. ST7 clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 9. CPU clock delay during Reset sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Table 10. Reset source selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Table 11. Internal RC prescaler selection bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 12. Clock register mapping and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 13. Interrupt software priority levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Table 14. Setting the interrupt software priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Table 15. Interrupt vector vs ISPRx bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Table 16. Dedicated interrupt instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Table 17. ST7FOXF1/ST7FOXK1 Interrupt mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Table 18. ST7FOXK2 interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Table 19. Interrupt sensitivity bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Table 20. Enabling/disabling active-halt and halt modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Table 21. Configuring the dividing factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Table 22. AWU register mapping and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Table 23. DR Value and output pin status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Table 24. I/O port mode options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Table 25. ST7FOXF1/ST7FOXK1/ST7FOXK2 I/O port configuration . . . . . . . . . . . . . . . . . . . . . . . . 75

Table 26. Effect of low power modes on I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Table 27. Description of interrupt events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Table 28. PA5:0, PB7:0, PC7:4 and PC2:0 pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Table 29. PA7:6 pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Table 30. PC3 pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Table 31. Port configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Table 32. I/O port register mapping and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Table 33. Watchdog timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Table 34. Watchdog timer register mapping and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Table 35. Effect of low power modes on autoreload timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Table 36. Description of interrupt events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Table 37. Counter clock selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Table 38. Register mapping and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Table 39. Effect of low power modes on Lite timer 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Table 40. Description of interrupt events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

Table 41. Lite Timer register mapping and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Table 42. Effect of low power modes on 16-bit timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

Table 43. 16-bit timer interrupt control/wakeup capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

Table 44. Summary of 16-bit timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

Table 45. 16-bit timer register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

Table 46. Effect of low power modes on the I

Table 47. Description of interrupt events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

Table 48. Configuratio n of I

C delay times. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

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Table 49. I2C register mapping and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

Table 50. Low power mode descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

Table 51. Interrupt events. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

Table 52. SPI Master mode SCK Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

Table 53. SPI Register Map and Reset Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

Table 54. Effect of low power modes on the A/D converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

Table 55. Channel selection using CH[3:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

Table 56. Configuring the ADC clock speed. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

Table 57. ADC register mapping and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

Table 58. Description of addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

Table 59. ST7 addressing mode overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

Table 60. Instructions supporting inherent addressing mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

Table 61. Instructions supporting inherent immediate addressing mode . . . . . . . . . . . . . . . . . . . . . 180

Table 62. Instructions supporting direct, indexed, indirect and indirect indexed addressing modes 181

Table 63. Instructions supporting relative modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

Table 64. ST7 instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

Table 65. Illegal opcode detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

Table 66. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188

Table 67. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189

Table 68. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189

Table 69. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190

Table 70. Operating characteristics with LVD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190

Table 71. Internal RC oscillator characteristics (5.0 V calibration) . . . . . . . . . . . . . . . . . . . . . . . . . . 191

Table 72. Supply current characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

Table 73. On-chip peripheral characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193

Table 74. I Table 75. SCL frequency (multimaster I

C interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194

C interface). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194

Table 76. SPI interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

Table 77. General timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197

Table 78. External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198

Table 79. AWU from Halt characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198

Table 80. Crystal/ceramic resonator oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199

Table 81. RAM and hardware registers characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200

Table 82. Flash program memory characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200

Table 83. EMS test results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201

Table 84. EMI emissions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202

Table 85. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203

Table 86. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203

Table 87. General characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204

Table 88. Output driving current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205

Table 89. Asynchronous RESET pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206

Table 90. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209

Table 91. ADC accuracy with VDD = 4.5 to 5.5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210

Table 92. Startup clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211

Table 93. Selection of the resonator oscillator range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212

Table 94. Configuration of sector size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212

Table 95. Development tool order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216

Table 96. ST7 application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216

Table 97. 20-pin plastic small outline package, 300-mil width, mechanical data . . . . . . . . . . . . . . . 220

Table 98. 20-pin plastic dual in-line package, 300-mil width, mechanical data . . . . . . . . . . . . . . . . 221

Table 99. 32-pin plastic dual in-line package, shrink 400-mil width, mechanical data . . . . . . . . . . . 222

Table 100. 32-pin low profile quad flat package (7x7), package mechanical data . . . . . . . . . . . . . . . 223

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Table 101. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224

Table 102. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225

10/226

ST7FOXF1, ST7FOXK1, ST7FOXK2 List of figures

List of figures

Figure 1. General block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 2. 32-pin SDIP package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 5

Figure 3. 32-pin LQFP 7x7 package pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 4. 20-pin SO and DIP package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 5. ST7FOXF1/ST7FOXK1/ST7FOXK2 memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 6. Typical ICC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 7. CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 8. Stack manipulation example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 9. RCCRH_USER and RCCRL_USER programming flowchart. . . . . . . . . . . . . . . . . . . . . . . 35

Figure 10. RC user calibration programming cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 11. Clock switching. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 12. Clock management block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Figure 13. Reset sequence phases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Figure 14. Reset block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Figure 15. Reset sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Figure 16. Low voltage detector vs reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Figure 17. Reset and supply management block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Figure 18. Interrupt processing flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Figure 19. Priority decision process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Figure 20. Concurrent interrupt management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Figure 21. Nested interrupt management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Figure 22. Power saving mode transitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Figure 23. Slow mode clock transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Figure 24. Wait mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Figure 25. Active-halt timing overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Figure 26. Active-halt mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Figure 27. Halt timing overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Figure 28. Halt mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Figure 29. AWUFH mode block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Figure 30. AWUF halt timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Figure 31. AWUFH mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Figure 32. I/O port general block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Figure 33. Interrupt I/O port state transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Figure 34. Watchdog block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Figure 35. Single timer mode (ENCNTR2=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Figure 36. Dual timer mode (ENCNTR2=1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Figure 37. PWM polarity inversion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Figure 38. PWM function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Figure 39. PWM signal from 0% to 100% duty cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Figure 40. Dead time generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Figure 41. ST7FOXF1/ST7FOXK1 Block diagram of break function. . . . . . . . . . . . . . . . . . . . . . . . . . 88

Figure 42. ST7FOXK2 Block diagram of break function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Figure 43. Block diagram of output compare mode (single timer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Figure 44. Block diagram of input capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Figure 45. Input capture timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Figure 46. Long range input capture block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Figure 47. Long range input capture timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Figure 48. Block diagram of one pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

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List of figures ST7FOXF1, ST7FOXK1, ST7FOXK2

Figure 49. One pulse mode and PWM timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Figure 50. Dynamic DCR2/3 update in one pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Figure 51. Force overflow timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Figure 52. Lite timer 2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Figure 53. Input Capture timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

Figure 54. Watchdog timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Figure 55. Timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Figure 56. 16-bit read sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

Figure 57. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

Figure 58. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

Figure 59. Counter timing diagram, internal clock divided by 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

Figure 60. Input capture block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

Figure 61. Input capture timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

Figure 62. Output compare block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

Figure 63. Output compare timi ng diagram, f Figure 64. Output compare timi ng diagram, f

TIMER=fCPU TIMER=fCPU

/2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

/4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

Figure 65. One pulse mode sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

Figure 66. One pulse mode timing example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

Figure 67. Pulse width modulation mode timing example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

Figure 68. Pulse width modulation cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

Figure 69. I Figure 70. I

C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

C interface block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

Figure 71. Transfer sequencing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

Figure 72. Event flags and interrupt generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

Figure 73. Serial peripheral interface block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

Figure 74. Single master/ single slave application. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

Figure 75. Generic SS timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

Figure 76. Hardware/software slave select management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

Figure 77. Data clock timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

Figure 78. Clearing the WCOL bit (write collision flag) software sequence. . . . . . . . . . . . . . . . . . . . 166

Figure 79. Single master / multiple slave configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

Figure 80. ADC block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

Figure 81. Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

Figure 82. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188

Figure 83. SPI slave timing diagram with CPHA=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

Figure 84. SPI slave timing diagram with CPHA=1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

Figure 85. SPI master timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197

Figure 86. Typical application with an external clock source. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198

Figure 87. Typical application with a crystal or ceramic resonator. . . . . . . . . . . . . . . . . . . . . . . . . . . 199

Figure 88. Two typical applications with unused I/O pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204

Figure 89. RESET pin protection when LVD is enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207

Figure 90. RESET pin protection when LVD is disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208

Figure 91. Typical application with ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209

Figure 92. ADC accuracy characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210

Figure 93. ST7FOXF1/ST7FOXK1/ST7FOXK2 ordering information scheme . . . . . . . . . . . . . . . . . 214

Figure 94. 20-pin plastic small outline package, 300-mil width, package outline. . . . . . . . . . . . . . . . 220

Figure 95. 20-pin plastic dual in-line package, 300-mil width, package outline . . . . . . . . . . . . . . . . . 221

Figure 96. 32-pin plastic dual in-line package, shrink 400-mil width, package outline. . . . . . . . . . . . 222

Figure 97. 32-pin low profile quad flat package (7x7), package outline. . . . . . . . . . . . . . . . . . . . . . . 223

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ST7FOXF1, ST7FOXK1, ST7FOXK2 Description

1 Description

The ST7FO X is a member of th e ST7 microcon troller family. All ST7 devices are based on a common industry-standard 8-bit core, featuring an enhanced instruction set.

The device is positioned at the entry level of the 8-bit microcontroller range providing an attractive cost while at the same time embedding the most advanced features.

The ST7FO X features Flash memory with byte-by-by te In-Circuit Prog r amming (ICP) and InApplication Programming (IAP) capability.

Under software control, the ST7FOX device can be placed in Wait, Slow, or Halt mode, reducing power consumption when the application is in idle or standby state.

The enhanced instruction set and addressing modes of the ST7 offer both power and flexibility to software developers, enabling the design of highly efficient and compact application code. In addition to standard 8-bit data management, all ST7 microcontrollers feature true bit manipulation, 8x8 unsigned multiplication and indirect addressing modes.

The ST7FOX features an on-chip Debug Module (DM) to support In-Circuit Debugging (ICD). For a description of the DM registers, refer to the ST7 ICC Protocol Reference Manual.

Table 1. Device summary

Features ST7FOXF1 / ST7FOXK1 ST7FOXK2

Program memory - bytes 4K 8K

RAM (stack) - bytes 384 (128)

Timers

ADC 1 x 10-bit

Peripherals I²C I²C and SPI

Packages DIP20, SO20, LQFP32, SDIP32 LQFP32, SDIP32

Dual 8-bit timer,

dual 12-bit AT (4 PWM)

Dual 8-bit timer, dual 12-bit AT

(4 PWM), 1 x 16-bit timer

13/226

Description ST7FOXF1, ST7FOXK1, ST7FOXK2

Figure 1. General block diagram

CLKIN

OSC1

OSC2

RESET

Ext.

OSC

1 MHz

16 MHz

Int.

8 MHz

RC OSC

Int.

32 kHz

RC OSC

/ 2

LVD

Power

Supply

Control

8-bit core

ALU

Flash

Program

Memory

(4 to 8 Kbytes)

RAM

(384 bytes)

Internal clock

12-bit

8-bit

Port A

Port B

Port C

PA7:0

(8 bits)

PB7:0

(8 bits)

PC7:0

(8 bits)

16-bit timer

Auto-reload

dual timer

dual Lite timer

ADDRESS AND DATA BUS

10-bit ADC

SPI

I2C

Watchdog

Debug module

Note 1 : available on 8K version only

14/226

ST7FOXF1, ST7FOXK1, ST7FOXK2 Pin description

2 Pin description

Figure 2. 32-pin SDIP package pinout

OCMP1_A1)/PA0(HS)

BREAK1/PC7

ATIC/PA1(HS) ATPWM0/PA2(HS) ATPWM1/PA3(HS)

ATPWM2/MCO/PA4(HS)

ATPWM3/PA5(HS)

I2CDATA/PA6(HS)

I2CCLK/PA7(HS)

OSC1/CLKIN

Note 1: Available on 8K version only

RESET

OSC2

SSA

ei2 2 3 4 5

ei0

6 7 8 9 10 11 12 13 14 15 16

ei1

ei2

PC6 PC5/BREAK2

31 30

PC4/LTIC

PC3/ICCCLK

PC2/ICCDATA

PC1/AIN9/ICAP2_A

PC0/AIN8/ICAP1_A

PB7/AIN7/SS/OCMP2_A PB6/AIN6/SCK

24 23

PB5/AIN5/EXTCLK_A

PB4/AIN4/MISO

PB3/AIN3/MOSI

PB2/AIN2

PB1/AIN1/CLKIN

PB0/AIN0

DDA

(HS) 20mA high sink capability eix associated external interrupt vector

Figure 3. 32-pin LQFP 7x7 package pinout

ATPWM1/PA3(HS)

ATPWM2/MCO/PA4(HS)

ATPWM3/PA5(HS)

I2CDATA/PA6(HS)

I2CCLK/PA7(HS)

RESET

PA2(HS)/ATPWM0

32 31 30 29 28 27 26 25

1 2

ei0

3 4 5 6 7 8

9 10111213141516

PC6

PA1(HS)/ATIC

PC5/BREAK2

PA0(HS)/OCMP1_A

PC7/BREAK1

ei2

ei1

SSA

DDA

OSC2

OSC1/CLKIN

AIN0/PB0

PC4/LTIC

PC3/ICCCLK

PC2/ICCDATA

PC1/AIN9/ICAP2_A

PC0/AIN8/ICAP1_A

PB7/AIN7/SS

PB6/AIN6/SCK

PB5/AIN5/EXTCLK_A

PB4/AIN4/MISO

PB3/AIN3/MOSI

AIN2/PB2

CLKIN/AIN1/PB1

(HS) 20mA high sink capability eix associated external interrupt vector

/OCMP2_A

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Pin description ST7FOXF1, ST7FOXK1, ST7FOXK2

Legend / Abbreviations for Table 2: Type: I = input, O = output, S = supply In/Output level: C

= CMOS 0.3VDD/0.7VDD with input trigger

Output level: HS = 20 mA high sink (on N-buffer only)

Port and control configuration:

● Input: float = floating, wpu = we ak pull-up, int = interrupt, ana = analog

● Output: OD = open drain, PP = push-pull

The RESET configuration of each pin is shown in bold which is v alid as long as the de vice is in reset state.

Table 2. Device pin description (32-pin packages)

number

LQFP32

1 5 PA3(HS)/ATPWM1 I/O CTHS x

SDIP32

ATPWM2/MCO

Pin name

PA4(HS)/

Level Port/control

Type

Input

Output

float

I/O C

HS x xx

Input Output

ana

(1)

int

wpu

ei0

Main

function

(after

reset)

Port A3

(HS)

Port A4

(HS)

Alternate

function

ATPWM1

ATPWM2/

MCO

3 7 PA5 (HS)ATPWM3 I/O C

PA6(HS)/

I2CDATA/SCK

PA7(HS)/I2CCLK/SS

(2)

I/O CTHS x

I/O CTHS x T

HS x xx

ei0

Port A5

(HS)

Port A6

(HS)

Port A7

(HS)

ATPWM3

I2CDATA/SPI

serial clock

I2CCLK/SPI

slave select

(active low) 6 10 RESET x x Reset 812 V 913 V

DD SS

(3) (3)

S Digital Supply Voltage S Digital Ground Voltage

Resonator oscillator

10 14 OSC1/CLKIN I

inverter input or External

clock input 11 15 OSC2 O Resonator oscillator output 12 16 V 13 17 V

SSA DDA

(3) (3)

S Analog Ground Voltage S Analog Supply Voltage

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ST7FOXF1, ST7FOXK1, ST7FOXK2 Pin description

Table 2. Device pin description (32-pin packages) (continued)

number

Pin name

SDIP32

LQFP32

Type

14 18 PB0/AIN0 I/O C

15 19 PB1/AIN1/CLKIN I/O C

16 20 PB2/AIN2 I/O C

(2)

I/O C

17 21 PB3/AIN3/MOSI

18 22 PB4/AIN4/MISO

19 23

PB5/AIN5/

EXTCLK_A

20 24 PB6/AIN6/SCK

21 25

22 26

23 27

PB7/AIN7/SS

OCMP2_A

PC0/AIN8/

ICAP1_A

PC1/AIN9/

ICAP2_A

24 28 PC2/ICCDATA I/O C 25 29 PC3/ICCCLK I/O C 26 30 PC4/LTIC I/O C

(4)

27 31 PC5/BREAK2

I/O C 28 32 PC6 I/O C 29 1 PC7/BREAK1 I/O C

Level Port/control

Input Output

Input

Output

float

x xxx Port B1

x xxx Port B2 AIN2

x xxx Port B3

x xxx Port B4

int

wpu

ana

xxxPort B0 AIN0

ei1

x xxx Port B5

x xxx Port B6

x xxx Port B7

xxxPort C0

ei2

T T T T T T

x xxx Port C1

x xxPort C2 ICCDATA x x xxPort C3 ICCCLK x x xxPort C5 BREAK2 x xx Port C6

ei2

x xxPort C7 BREAK1

Main

(1)

function

(after

reset)

Alternate

function

AIN1/Externa

l clock source

AIN3/SPI

Master out

/Slave in data

AIN4/SPI

Master

in/Slave out

data

AIN5/Timer A

input clock

AIN6/SPI

serial clock

AIN7/SPI

slave select

(active low)/

Timer A

Output

Compare 2

AIN8/Timer A

Input

Capture 1

AIN9/Timer A

Input

Capture 2

xxPort C4 LTIC

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Pin description ST7FOXF1, ST7FOXK1, ST7FOXK2

Table 2. Device pin description (32-pin packages) (continued)

number

Pin name

SDIP32

LQFP32

30 2

(HS)

PA0

(5)

/OCMP1_A

(2)

31 3 PA1 (HS)/ATIC I/O CTHS x xx

32 4 PA2 (HS)/ATPWM0 I/O C

1. In the open-drain output column, T defines a true open-drain I/O (P-Buffer and protection diode to VDD are not implemented).

2. Available on ST7FOXK2 only.

3. It is mandatory to connect all available V

4. BREAK2 available on ST7FOXK2 only

5. Available on ST7FOXK1 only.

Level Port/control

Type

Input

Output

float

I/O C

(5)

HS x xx

and V

pins to the supply voltage and all VSS and V

DDA

Input Output

ana

(1)

int

wpu

ei0

Main

function

(after

reset)

Port A0 (HS)

Output Compare 1

Port A1

(HS)

Port A2

(HS)

pins to ground.

SSA

Figure 4. 20-pin SO and DIP package pinout

Alternate

function

(5)

/ Timer A

ATIC

ATPWM0

ei2

ei0

ei2

ei1

PC4/LTIC

PC3/ICCCLK

PC2/ICCDATA

PB5/AIN5

PB4/AIN4

PB3/AIN3

PB2/AIN2

PB1/AIN1/CLKIN

PB0/AIN0

(HS) 20mA high sink capability eix associated externalinterrupt vector

PC6

ATIC/PA1(HS) ATPWM0/PA2(HS) ATPWM1/PA3(HS)

ATPWM2/MCO/PA4(HS)

ATPWM3/PA5(HS)

I2CDATA/PA6(HS)

I2CCLK/PA7(HS)

RESET

1 2 3 4 5 6 7 8 9 10

Legend / Abbreviations for Table 3: Type: I = input, O = output, S = supply In/Output level:CT= CMOS 0.3VDD/0.7VDD with input trigger Output lev el: HS = 20mA high sink (on N-buffer only) Port and control configuration:

● Input: float = floating, wpu = we ak pull-up, int = interrupt, ana = analog

● Output: OD = open drain, PP = push-pull

Note: The RESET configuration of each pin is shown in bold which is valid as long as the device is

in reset state.

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ST7FOXF1, ST7FOXK1, ST7FOXK2 Pin description

Table 3. Device pin description (20-pin package)

Level Port / Control

function

(after reset)

Main

SSA

Alternate

function

AIN1/External

clock source

pins to ground.

Number

Pin Name

1 PC6 I/O C 2 PA1 (HS)/ATIC I/O C 3 PA2 (HS)/ATPWM0 I/O C 4 PA3 (HS)/ATPWM1 I/O C

PA4

(HS)ATPWM2/MCO

Type

I/O C

Input Output

Input

Output

float

T T T T

x ei2 x x Port C6 HS x HS x x x Port A2 (HS) ATPWM0 HS x x x Port A3 (HS) ATPWM1

HS x x x Port A4 (HS) ATPWM2/MCO

wpu

ei0

int

ana

(1)

x x Port A1 (HS) ATIC

6 PA5 (HS)ATPWM3 I/O CTHS x x x Port A5 (HS) ATPWM3 7 PA6 (HS)/I2CDATA I/O C 8 PA7 (HS)/ I2CCLK I/O C

HS x T Port A6 (HS) I2CDATA

HS x T Port A7 (HS) I2CCLK

9 RESET x x Reset 10 V 11 V 12 PB0/AIN0 I/O C

13 PB1/AIN1/CLKIN I/O C

14 PB2/AIN2 I/O C 15 PB3/AIN3 I/O C 16 PB4/AIN4 I/O C 17 PB5/AIN5 I/O C 18 PC2/ICCDATA I/O C 19 PC3/ICCCLK I/O C 20 PC4/LTIC I/O C

1. In the open-drain output column, T defines a true open-drain I/O (P-Buffer and protection diode to VDD not implemented).

2. It is mandatory to connect all available V

SS DD

(3) (2)

S Digital Ground Voltage S Digital Supply Voltage

T T T T T T T

and V

xxxxPort B1

x x x x Port B2 AIN2

ei1

x x x x Port B3 AIN3 x x x x Port B4 AIN4 x x x x Port B5 AIN5 x ei2 x x Port C2 ICCDATA x x x Port C3 ICCCLK x ei2 x x Port C4 LTIC

pins to the supply voltage and all VSS and V

DDA

x x x Port B0 AIN0

19/226

3 Register and memory mapping

As shown in Figure 5, the MCU is capable of addressing 64 Kbytes of memories and I/O registers.

The availab le memory locations consist of 128 b ytes of r egister locations , 384 b yte s of RAM and 4 to 8 Kbytes of Flash program memory. The RAM space includes up to 128 bytes for the stack from 180h to 1FFh.

The highest address bytes contain the user reset and interrupt vectors. The Flash memory contains two sectors (see Figure 5) mapped in the upper part of the ST7

addressing space so the reset and interrupt vectors are locat ed in Sector 0 (FFE0h -FFFFh). The size of Flash Sector 0 and other device options are configurable by option bytes (refer

to Section 13.1 on page 211).

Caution: Memory locations marked as “Reserved” must never be accessed. Accessing a reserved

area can have unpredictable effects on the device.

Figure 5. ST7FOXF1/ST7FOXK1/ST7FOXK2 memory map

0000h 007Fh

0080h

01FFh 0200h

DFFFh

E000h

EFFFh

F000h

F7FFh

F800h

FFDFh FFE0h

FFFFh

HW registers

(seeTable 8)

RAM

(384 bytes)

Reserved

Flash Memory

(8 Kbytes)

(4 Kbytes)

Interrupt & Reset Vectors

(see Table 17)

0080h

00FFh 0100h

017Fh

0180h

01FFh

Short Addressing RAM (zero page)

RAM

128 bytes Stack

8 or 4 Kbytes

Flash program memory

Sector 1 Sector 0

(4 Kbytes) (2 Kbytes) (1 Kbyte)

(0.5 Kbyte)

E000h

FFFFh

1000h 1001h

DEE0h DEE1h

RCCRH_USER

RCCRL_USER

RCCRH RCCRL

see Section 6.1.1

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ST7FOXF1, ST7FOXK1, ST7FOXK2 Register and memory mapping

Table 4. Hardware register map

(1)

Address Block Register label Register name Reset status Remarks

0000h 0001h 0002h

0003h 0004h 0005h

0006h 0007h 0008h

0009h to

000Bh

000Ch 000Dh 000Eh 000Fh

0010h 0011h

0012h 0013h 0014h 0015h 0016h 0017h 0018h

0019h 001Ah 001Bh 001Ch 001Dh 001Eh 001Fh

0020h

0021h

0022h

0023h

0024h

0025h

0026h

0027h

0028h

0029h 002Ah

Port A

Port B

Port C

LITE

TIMER

AUTO-

RELOAD

TIMER

PADR

PADDR

PAOR

PBDR

PBDDR

PBOR PCDR

PCDDR

PCOR

LTCSR2

LTARR

LTCNTR

LTCSR1

LTICR

ATCSR

CNTR1H

CNTR1L

ATR1H

ATR1L

PWMCR PWM0CSR PWM1CSR PWM2CSR PWM3CSR

DCR0H DCR0L DCR1H DCR1L DCR2H DCR2L DCR3H DCR3L

ATICRH

ATICRL

ATCSR2

BREAKCR1

ATR2H

ATR2L DTGR

BREAKEN

Port A Data register

Port A Data Direction register

Port A Option register

Port B Data register

Port B Data Direction register

Port B Option register

Port C Data register

Port C Data Direction register

Port C Option register

Reserved area (3 bytes)

Lite Timer Control/Status register 2

Lite Timer Auto-reload register

Lite Timer Counter register

Lite Timer Control/Status register 1

Lite Timer Input Capture register

Timer Control/Status register

Counter register 1 High

Counter register 1 Low

Auto-Reload register 1 High

Auto-Reload register 1 Low

PWM Output Control register PWM 0 Control/Status register PWM 1 Control/Status register PWM 2 Control/Status register PWM 3 Control/Status register

PWM 0 Duty Cycle register High

PWM 0 Duty Cycle register Low

PWM 1 Duty Cycle register High

PWM 1 Duty Cycle register Low

PWM 2 Duty Cycle register High

PWM 2 Duty Cycle register Low

PWM 3 Duty Cycle register High

PWM 3 Duty Cycle register Low

Input Capture register High

Input Capture register Lo w

Timer Control/Status register 2

Break Control register

Auto-Reload register 2 High

Auto-Reload register 2 Low

Dead Time Generation register

Break Enable register

00h 00h 00h

00h 00h 08h

0Fh 00h 00h

0x00 0000b

xxh

0x00 0000b

00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 03h 00h 00h 00h 00h 03h

R/W R/W R/W

R/W R/W

Read Only

R/W

Read Only

R/W Read Only Read Only

R/W

R/W Read Only Read Only

R/W

002Bh Reserved area (1 byte)

002Ch

AUTO-

RELOAD

BREAKCR2

(4)

Break Control register 2

(4)

00h R/W

TIMER

21/226

Table 4. Hardware register map

(1)

(continued)

Address Block Register label Register name Reset status Remarks

002Dh 002Eh 002Fh

0030h 0031h

ITC

ISPR0 ISPR1 ISPR2 ISPR3

EICR

Interrupt Software Priority register 0 Interrupt Software Priority register 1 Interrupt Software Priority register 2 Interrupt Software Priority register 3

External Interrupt Control register

FFh FFh FFh FFh

00h

R/W

0032h Reserved area (1 byte) 0033h WDG WDGCR Watchdog Control register 7Fh R/W 0034h FLASH FCSR Flash Con tro l /St at us re gi ster 00h R/W

0035h

0036h 0037h 0038h

Calibration

ADC

RCC_CSR RC calibration Control/Status register 00h R/W

ADCCSR ADCDRH

ADCDRL

A/D Control Status register

A/D Data register High

A/D Data Low / test register

00h xxh 0xh

R/W Read Only

R/W

0039h Reserved area (1 byte) 003Ah MCC MCCSR Main Clock Control/Status register 00h R/W 003Bh

003Ch 003Dh

Clock and

Reset

RCCRH

RCCRL

PSCR

RC oscillator Control register High

RC oscillator Control register Low

Prescaler register

FFh

011x 0x00b

00h or 03h

(2)

R/W R/W R/W

003Eh to

0047h

0048h

0049h 004Ah

004Bh 004Ch 004Dh 004Eh 004Fh

0050h

0051h

0052h to

0054h

AWU

(3)

Clock

Controller

Reserved area (10 bytes)

AWUCSR

AWUPR

DMCR DMSR

DMBK1H

DMBK1L

DMBK2H

DMBK2L

DMCR2

AWU Control/Status register

AWU Preload register

DM Control register

DM Status register

DM Breakpoint register 1 High

DM Breakpoint register 1 Low

DM Breakpoint register 2 High

DM Breakpoint register 2 Low

DM Control register 2

FFh

00h 00h

00h 00h 00h 00h 00h 00h

R/W R/W

R/W R/W R/W R/W R/W R/W R/W

CKCNTCSR Clock Controller Status register 09h R/W

Reserved area (3 bytes)

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ST7FOXF1, ST7FOXK1, ST7FOXK2 Register and memory mapping

Table 4. Hardware register map

(1)

(continued)

Address Block Register label Register name Reset status Remarks

0055h

0056h

0057h

0058h

0059h 005Ah 005Bh 005Ch 005Dh

16-bit

Timer

(4)

005Eh 005Fh

0060h

0061h

0062h

0063h

0064h

0065h

0066h

0067h

I2C 0068h 0069h

006Ah

0070h 0071h

SPI

(4)

0072h

1. Legend: x=undefined, R/W=read/write.

2. Reset status is 03h for ST7FOXK2 and 00h for ST7FOXF1 and ST7FOXK1

TACR2 TACR1

TACSR TAICHR1 TAICLR1

TAOCHR1 TAOCLR1

TACHR

TACLR TAACHR

TAACLR

TAICHR2 TAICLR2

TAOCHR2 TAOCLR2

I2CCR I2CSR1 I2CSR2

I2CCCR I2COAR1 I2COAR2

I2CDR

SPIDR SPICR

SPISR

Timer A Control register 2 Timer A Control register 1

Timer A Control/status register

Timer A Input capture 1 high register

Timer A Input capture 1 low register

Timer A Output compare 1 high register

Timer A Output compare 1 low register

Timer A Output counter high register

Timer A Output counter low register

Timer A Alternate counter high register

Timer A Alternate counter low register

Timer A Input capture 2 high register

Timer A Input capture 2 low register

Timer A Output compare 2 high register

Timer A Output compare 2 low register

C Control register

C Status register 1

I I2C Status register 2

C Clock Control register

I I2C Own Address register 1 I2C Own Address register 2

C Data register

I SPI Data register

SPI Control register

SPI Status register

00h 00h 00h xxh xxh 80h

00h FFh FCh FFh FCh

xxh

80h

00h

40h

00h

0xh

00h

xxh

R/W

R/W Read Only Read Only Read Only

R/W

R/W Read Only Read Only Read Only Read Only Read Only Read Only

R/W

Read only Read only

R/W

3. For a description of the Debug Module registers, see ICC protocol reference manual.

4. Available on ST7FOXK2 only

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Flash programmable memory ST7FOXF1, ST7FOXK1, ST7FOXK2

4 Flash programmable memory

4.1 Introduction

The ST7 single voltage extended Flash (XFlash) is a non-volatile memory that can be electrically erased and programmed either on a byte-by-byte basis or up to 32 bytes in parallel.

The XFlash devices can be prog rammed off-board (plugged in a programming tool) or onboard using In-Circuit Programming or In-Application Programming.

The array matrix organization allows each sector to be erased and reprogrammed without affecting other sectors.

4.2 Main features

● ICP (In-Circuit Programming)

● IAP (In-Application Programming)

● ICT (In-Circuit Testing) for downloading and executing user application test patterns in

RAM

● Sector 0 size configurable by option byte

● Read-out and write protection

4.3 Programming modes

The ST7 can be programmed in three different ways:

● Insertion in a programming tool. In this mode, Flash sectors 0 and 1, option byte row

can be programmed or erased.

● In-Circuit Programming. In this mode, Flash sectors 0 and 1, option byte row can be

programmed or erased without removing the device from the application board.

● In-Application Programming. In this mode, sector 1 can be programmed or erased

without removing the de vice from the application board and while the application is running.

4.3.1 In-Circuit Programming (ICP)

ICP uses a protocol called ICC (In-Circuit Communication) which allows an ST7 plug ged on a printed circuit board (PCB) to communicate with an external programming device connected via cable. ICP is performed in three steps:

Switch the ST7 to ICC mode (In-Circuit Communications). This is done by driving a specific signal sequence on the ICCCLK/DATA pins while the RESET ST7 enters ICC mode, it fetches a specific Reset vector which points to the ST7 System Memory containing the ICC protocol routine. This routine enables the ST7 to receive bytes from the ICC interface.

● Download ICP Driver code in RAM from the ICCDATA pin

● Execute ICP Driver code in RAM t o program the Flash memory

pin is pulled low. When the

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ST7FOXF1, ST7FOXK1, ST7FOXK2 Flash programmable memory

Depending on the ICP Driver code downloaded in RAM, Flash memory programming can be fully customized (number of bytes to program, program locations, or selection of the serial communication interface for downloading).

4.3.2 In Application Programming (IAP)

This mode uses an IAP Driver program previously programmed in Sector 0 by the user (in ICP mode).

This mode is fully controlled by user softwa re. This allows it to be adapted to the user application, (user-defined strategy for entering programming mode, choice of communications protocol used to fetch the data to be stored etc.) IAP mode can be used to progr am an y memory areas e xcept Sector 0, which is Write/Erase protected to allow recovery in case errors occur during the programming operatio n.

4.4 ICC interface

ICP needs a minimum of 4 and up to 6 pins to be connected to t he progr amming tool. These pins are:

● RESET: device reset

● V

● ICCCLK: ICC output serial clock pin

● ICCDATA: ICC input serial data pin

● OSC1: main clock input for external source

● V

Note: 1 If the ICCCLK or ICCDATA pins are only used as outputs in the app licat ion , no sign al

isolation is necessary. As soon as the Programming Tool is plugged to the board, even if an ICC session is not in progress, the ICCCLK and ICCDATA pins are not available for the application. If they are used as inputs by the application, isolation such as a serial resistor has to be implemented in case another device forces the signal. Refer to the Programming Tool documentation for recommended resistor values.

2 During the ICP session, the programming tool must control the RESET

conflicts between the programming tool a nd the application reset circuit if it d rives more than 5mA at high level (push pull output or pull-up resistor<1 k to isolate the application RESET circuit in this case. When using a classical RC network with R>1 k additional components are needed. In all cases the user must ensure that no external reset is generated by the application during the ICC session.

3 The use of pin 7 of the ICC connector depends on the Programming Tool architecture. This

pin must be connected when using most ST Programming Tools (it is used to monitor the application power supply). Please refer to the Programming Tool manual.

4 In “enabled option byte” mode (38-pulse ICC mode), the internal RC oscillator is forced as a

clock source, regardless of the selection in the option byte. In “disabled option byte” mode (35-pulse ICC mode), pin 9 has to be co nne cted t o t he PB1/ CLKI N pi n o f th e ST7 when the clock is not available in the application or if the selected clock option is not programmed in the option byte.

: device power supply ground

: application board power supply (optional, see Note 3)

pin. This can lead to

Ω

). A schottky diode can be used

Ω

or a reset management IC with open drain output and pull-up resistor>1 kΩ, no

Caution: During normal operation the ICCCLK pin must be in ternally or externally pulled- up (e xternal

pull-up of 10 kΩ mandatory in noisy environment) to a v oid entering ICC mode unexpectedly

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Flash programmable memory ST7FOXF1, ST7FOXK1, ST7FOXK2

during a reset. In the application, even if the pin is configured as output, any reset will put it back in input pull-up.

Figure 6. Typical ICC Interface

PROGRAMMING TOOL

ICC CONNECTOR

ICC Cable

ICC CONNECTOR

(See Note 3)

OPTIONAL

(See Note 4)

HE10 CONNECTOR TYPE

975 3

1 246810

APPLICATION BOARD

APPLICATION RESET SOURCE

See Note 2

APPLICATION POWER SUPPLY

VDD

ST7

PB1/CLKIN

RESET

ICCCLK

See Note 1 and Caution

See Note 1

ICCDATA

APPLICATION

I/O

26/226

ST7FOXF1, ST7FOXK1, ST7FOXK2 Flash programmable memory

4.5 Memory protection

There are two different types of memory protection: Read-Out Protection and Write/Erase Protection which can be applied individually.

4.5.1 Read-out protection

Read-Out Protection, when selected prov ides a protection against program me mory content extraction and against write access to Flash memory. Ev en if no protection can be considered as totally unbreakable, the feature provides a very high level of protection for a general purpose microcontroller.

● In Flash devices, this protection is removed by reprogramming the option. In this case,

the program memory is automatically erased and the device can be reprogrammed. The read-out protection is enabled and removed through the FMP_R bit in t he option byte.

4.5.2 Flash write/erase protection

Write/Erase Protection, when set, makes it impossible to both overwrite and erase program memory . Its purpose is to provide adv anced security to applica tions and pre ven t any change being made to the memory content. Write/Erase Protection is enabled through the FMP_W bit in the option byte.

Caution: Once set, Write/Erase Protection can never be removed. A write-protected Flash

device is no longer reprogrammable.

4.6 Related documentation

For details on Flash programming and ICC protocol, refer to the ST7 Flash Programming Reference Manual and to the ST7 ICC Protocol Reference Manual

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Flash programmable memory ST7FOXF1, ST7FOXK1, ST7FOXK2

4.7 Description of Flash Control/Status register (FCSR)

This register controls the XFlash erasin g and programming using ICP, IAP or other programming methods.

1st RASS Key: 0101 0110 (56h) 2nd RASS Key: 1010 1110 (AEh) When an EPB or another programming tool is used (in socke t or ICP mode), the RASS ke ys

are sent automatically. Reset value: 000 0000 (00h)

7 0 00000OPTLATPGM

Read/write

Table 5. Flash register mapping and reset values

Address

(Hex.)

0034

label

FCSR

Reset Value

76543210

OPT

LAT

PGM

28/226

ST7FOXF1, ST7FOXK1, ST7FOXK2 Central processing unit

5 Central processing unit

5.1 Introduction

This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8bit data manipulation.

5.2 Main features

● 63 basic instructions

● Fast 8-bit by 8-bit multiply

● 17 main addressing modes

● Two 8-bit index registers

● 16-bit stack pointer

● Low power modes

● Maskable hardware inter rupts

● Non-maskable software interrupt

5.3 CPU registers

The six CPU registers shown in Figure 7. They are n ot present in the memo ry mapping and are accessed by specific instructions.

Figure 7. CPU registers

15 8

RESET VALUE = RESET VECTOR @ FFFEh-FFFFh

RESET VALUE = STACK HIGHER ADDRESS

PCH

RESET VALUE =

RESET VALUE = XXh

PCL

70 1C11HI NZ 1X11X1XX

ACCUMULATOR

X INDEX REGISTER

Y INDEX REGISTER

PROGRAM COUNTER

CONDITION CODE REGISTER

STACK POINTER

X = Undefined Value

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Central processing unit ST7FOXF1, ST7FOXK1, ST7FOXK2

5.3.1 Accumulator (A)

The Accumulator is an 8-bit general purpose register used to hold operands and the re su lts of the arithmetic and logic calculations and to manipulate data.

5.3.2 Index registers (X and Y)

In indexed addressing modes, these 8-bit registers are used to create either effective addresses or temporary storage areas for data manipulation. (The Cross-Assembler generates a precede instruction (PRE) to indicate that the following instruction refers to the Y register.)

The Y register is not affected by the interrupt automatic procedures (not pushed to and popped from the stack).

5.3.3 Pr ogram Counter (PC)

The Program Counter is a 16 -bit registe r containin g the a ddress of the ne xt instruction to be exe cuted by the CPU. It is made of two 8-bit registers PCL (Program Counter low which is the LSB) and PCH (Program Counter high which is the MSB).

5.3.4 Condition Code register (CC)

The 8-bit Condition Code register contains the interrupt mask and four flags representat ive of the result of the instruction just executed. This register can also be handled b y the PUSH and POP instructions.

Reset value: 111x 1xxx

7 0 11I1HI0NZC

Read/write

These bits can be individually tested and/or controlled by specific instructions.

Arithmetic management bits

Bit 4 = H Half carry bit

This bit is set by hard war e when a carry occurs between bit s 3 and 4 of the ALU during an ADD or ADC instruction. It is reset by hardware during the same instructions.

0: No half carry has occurred. 1: A half carry has occurred.

This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD arithmetic subroutines.

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ST7FOXF1, ST7FOXK1, ST7FOXK2 Central processing unit

Bit 3 = I Interrupt mask

bit

This bit is set by hardware when entering in interrupt or by software to disable all interrupts except the TRAP software interrupt. This bit is cleared by software.

0: Interrupts are enabled. 1: Interrupts are disabled. This bit is controlled by the RIM, SIM and IRET instructions and is tested by the JRM

and JRNM instructions.

Note: Interrupts requested while I is set are latched and can be processed when I is cleared. By

default an interrupt routine is not interruptib le because the I bit is set b y hardw are at the start of the routine and reset b y the IRET instruction at the end of the rout ine. I f the I bit i s cleared by software in the int errupt routine , pe nding inter rupts are serviced regardless of the priority level of the current interrupt routine.

Bit 2 = N Negative bit

This bit is set and cleared by hardware. It is representative of the result sign of the last arithmetic, logical or data manipulation. It is a copy of the 7

bit of the result. 0: The result of the last operation is positive or null. 1: The result of the last operation is negative (that is, the most significant bit is a logic

1). This bit is accessed by the JRMI and JRPL instructions.

Bit 1 = Z Zero bit

This bit is set and cleared by hardware. This bit indicates that the result of the last arithmetic, logical or data manipulation is zero.

0: The result of the last operation is different from zero. 1: The result of the last operation is zero. This bit is accessed by the JREQ and JRNE test instructions.

Bit 0 = C Carry/borrow

bit

This bit is set and cleared by hardware and software. It indicates an overflow or an underflow has occurred during the last arithmetic operation.

0: No overflow or underflow has occurred. 1: An overflow or underflow has occurred. This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC

instructions. It is also affected by the “bit test and branch”, shift and rotate instructions.

Interrupt management bits

Bits 5,3 = I1, I0 Interrupt bits

The combination of the I1 and I0 bits gives the current interrupt software priority. These two bits are set/cleared by hardware when entering in interrupt. The loaded

value is given by the corresponding bits in the interrupt software priority registers (IxSPR). They can be also set/cleared b y soft wa re with the RIM, SIM, IRET, HALT, WFI and PUSH/POP instructions. See Section 9.6: Interrupts for more details.

31/226

Central processing unit ST7FOXF1, ST7FOXK1, ST7FOXK2

Table 6. Interrupt software priority truth table

Interrupt software priority I1 I0

Level 0 (main) 1 0

Level 1 0 1 Level 2 0 0

Level 3 (= interrupt disable) 1 1

5.3.5 Stack Pointer (SP)

Reset value: 01FFh

15 8 7 0

0 0 0 0 0 0 0 1 1 SP6 SP5 SP4 SP3 SP2 SP1 SP0

Read/write

The Stack P oin ter is a 16-b it regi ster wh ich is alw ays pointing to the next free location in the stack. It is then decremented afte r data has been pushed onto the stack and incremented before data is popped from the stack (see Figure 8).

Since the stack is 128 bytes deep, the 9 most significant bits are forced by hardware. Following an MCU Reset, or after a Reset Stac k Pointer instruction (RSP), the Stack P ointer contains its reset value (the SP6 to SP0 bits are set) which is the stack higher address.

The least significant byte of the Stack Pointer (called S) can be directly accessed by a LD instruction.

Note: When the lower limit is exceeded, the Stack Pointer wraps around to the stack upper limit,

without indicating the stack overflow. The previously stored information is then overwritten and therefore lost. The stack also wraps in case of an underflow.

The stack is used to save the return address during a subroutine call and the CPU context during an interrupt. The user may also directly manipulate the stack by means of the PUSH and POP instructions. In the case of an interrupt, the PCL is stored at the first location pointed to by the SP. Then the other registers are stored in the next locations as shown in

Figure 8.

● When an interrupt is received, the SP is decremen ted and t he context is pushed on the

stack.

● On return from interrupt, the SP is incremented and the context is popped from the

stack.

A subroutine call occupies two locations and an interrupt five locations in the stack area.

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ST7FOXF1, ST7FOXK1, ST7FOXK2 Central processing unit

Figure 8. Stack manipulation example

@ 0180h

@ 01FFh

CALL

Subroutine

PCH PCL

Interrupt

Event

X PCH PCL PCH PCL

PUSH Y POP Y IRET

A X

PCH

PCL

PCH

PCL

A X

PCH

PCL

PCH

PCL

PCH PCL

RET

or RSP

Stack Higher Address = 01FFh Stack Lower Address =

0180h

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Supply, reset and clock management ST7FOXF1, ST7FOXK1, ST7FOXK2

6 Supply, reset and clock management

The device includes a range of utility features for securing the application in critical situations (for example in case of a power brown-out), and reducing the number of external components. The main features are the following:

● Clock management

– 8 MHz internal RC oscillator (enabled by option byte) – Auto wakeup RC oscillator (enabled by option byte) – 1 to 16 MHz or 32 kHz External crystal/ceramic resonator (selected by opti on by te) – External clock input (enabled b y option byte)

● Reset Sequence Manager (RSM)

● System Integrity management (SI)

– Main supply Low voltage detecti on (LVD) with reset generation (enabled by option

byte)

6.1 RC oscillator adjustment

6.1.1 Internal RC oscillator

The device contains an internal RC oscillator with a specific accuracy for a given device, temperature and voltage range (4.5 V - 5.5 V). It must be calibrated to obtain the frequency required in the application. This is done by software writing a 10-bit calibration value in the RCCRH (RC Control register High) and in the bits 6:5 in the RCCRL (RC Control register Low).

Whenever the microcontroller is reset, the RCCR returns to its default value (FFh), i.e . each time the device is reset, the calibration value must be loaded in the RCCR. Predefined calibration values are store d for 5 V V

Table 7. Predefined RC oscillator calibration values

RCCR Conditions

RCCRH V

RCCRL DEE1h

1. The DEE0h and DEE1h addresses are located in a reserved area in non-volatile memory. They are readonly bytes for the application code. This area cannot be erased or programmed by any ICC operations. For compatibility reasons with the RCCRL register, CR[1:0] bits are stored in the 5th and 6th position of DEE1 address.

In 38-pulse ICC mode, the internal RC oscillator is forced as a clock source, regardless of the selection in the option byte.

= 8 MHz

= 5V

= 25°C

supply voltage at 25 °C (see Table 7).

ST7FOX

Address

(1)

DEE0h

(CR[9:2])

(1)

(CR[1:0])

Section 12: Electrical characteristics on page 187 for more information on the frequency

and accuracy of the RC oscillator. To improve cloc k stability and frequency accuracy, it is recommended to place a decoupling

capacitor, typically 100 nF, between the V V

pins as close as possible to the ST7 device.

SSA

34/226

and V

pins and also between the V

DDA

and

ST7FOXF1, ST7FOXK1, ST7FOXK2 Supply, reset and clock management

These bytes are systematically programmed by ST.

6.1.2 Customized RC calibration

If the application requires a higher frequency accuracy or if the voltage or temperature conditions change in the application, the frequency may need to be recalibrated. Two nonvolatile bytes (RCCRH_USER and RCCRL_USER) are reserved for storing these new values. These two-byte area is Electrically Erasable Programmable Read Only Memory.

Note: Refer to application note AN1324 f or inf ormation on how t o calibrate the RC frequency using

an external reference signal.

How to program RCCRH_USER and RCCRL_USER

To access the write mode, the RCCLAT bit has to be set by software (the RCCPGM bit remains cleared). When a write access to this two-byte area occurs , t he values are latched.

When RCCPGM bit is set by the software, the latched data are programmed in the EEPROM cells. To avoid wrong programming, the user must tak e care to only access these two-byte addresses.

At the end of the programming cycle, the RCCPGM and RCCLAT bits are cleared simultaneously.

Note: During the programming cycle, it is forbidden to access the latched data (see Figure 9).

Figure 9. RCCRH_USER and RCCRL_USER programming flowchart

READ MODE

RCCLAT=0

RCCPGM=0

READ BYTES

CLEARED BY HARDWARE

START PROGRAMMING CYCLE

WRITE MODE

RCCLAT=1

RCCPGM=0

WRITE THE 2 BYTES

AT THEIR ADDRESS

RCCPGM=1 (set by software)

RCCLAT=1

RCCLAT

Note: If a programming cycle is interrupted (by a reset action), the integrity of the data in memory

is not guaranteed.

Access error handling

If a read access occurs while RCCLAT=1, then the data bus will not be driven. If a write access occurs while RCCLAT=0, then the data on the bus will not be latched.

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Supply, reset and clock management ST7FOXF1, ST7FOXK1, ST7FOXK2

If a programming cycle is interrupted (by a RESET action), the integrity of the data in memory will not be guaranteed.

Caution: When the Read-Out Protection is enabled through an option bit (see Section 13.1: Option

bytes), these two bytes are protected against Read-out (including a re-write protection). In

Flash devices, when this protection is remo v ed b y reprogr amming the option b yte , these two bytes are automatically erased.

Figure 10. RC user calibration programming cycle

Internal Programming

voltage

WRITE OF

DATA LATCHES

Byte1Byte

is typically 5 ms and max 10 ms

PROG

READ OPERATION NOT POSSIBLE

ERASE CYCLE

6.1.3 Auto wakeup RC oscillator

The ST7FOX also contains an Auto wakeup RC oscillator. This RC oscillator should be enabled to enter Auto wakeup from halt mode.

The Auto wakeup (AWU) RC oscillator can also be configured as the startup clock through the CKSEL[1:0] option bits (see Section 13.1: Option bytes on page 211).

This is recommended for applications where very low power consumption is required.

PROG

READ OPERATION POSSIBLE

WRITE CYCLE

RCCLAT

RCCPGM

Switching from one startup clock to another can be done in run mode as follows (see

Figure 11):

Case 1 Switching from internal RC to AWU

1. Set the RC/AWU bit in the CKCNTCSR register to enable the AWU RC oscillator

2. The RC_FLAG is cleared and the clock output is at 1.

3. Wait 3 AWU RC cycles till the AWU_FLAG is set

4. The switch to the AWU clock is made at the posit ive edge of the AWU clock signal

5. Once the switch is made, the internal RC is stopped

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ST7FOXF1, ST7FOXK1, ST7FOXK2 Supply, reset and clock management

Case 2 Switching from AWU RC to internal RC

1. Reset the RC/AWU bit to enable the internal RC oscillator

2. Using a 4-bit counter, wait until 8 internal RC cycles have elapsed. The counter is

running on internal RC clock.

3. Wait till the AWU_FLAG is cleared (1AWU RC cycle) and the RC_FLAG is set (2 RC

cycles)

4. The switch to the internal RC clock is made at the positiv e edge of the internal RC clock

signal

5. Once the switch is made, the AWU RC is stopped

Note: 1 When the internal RC is not selected, it is stopped so as to save power consumption.

2 When the internal RC is selected, the AWU RC is turned on by hardware when entering

Auto wakeup from Halt mode.

3 When the external clock is selected, the AWU RC oscillator is always on.

Figure 11. Clock switching

Internal RC AWU RC

AWU RC

Set RC/AWU

Poll AWU_FLAG until set

Reset RC/AWU

Poll RC_FLAG until set

Internal RC

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Supply, reset and clock management ST7FOXF1, ST7FOXK1, ST7FOXK2

Figure 12. Clock management block diagram

CLKIN

CLKIN /OSC1

OSC2

CK2 CK1 CK0

8 MHz (f

Prescaler

CLKSEL[1:0]

Option bits

CLKIN CLKIN

OSC

1-16 MHz or 32kHz

CR6CR9 CR2CR3CR4CR5CR8 CR7

Tunable

OscillatorRC )

8 MHz 4 MHz 2 MHz 1 MHz

500 kHz

CR1 CR0

RC OSC

DIVIDER

OSC

CLKIN/2

DIVIDER

PSCR

RCCRH

AWU RC OSC

Clock controller

RCCRL

CPU

RC/AWU

CLKIN/2 OSC/2

CKCNTCSR

12-BIT

AT TIMER 2

CLKSEL[1:0]

Option bits

OSC

/32 DIVIDER

6.2 Multi-oscillator (MO)

The main clock of the ST7 can be generated by four different source types coming from the multi-oscillator block (1 to 16 MHz):

● An external source

● 5 different configurations for crystal or ceramic resonator oscillators

● An internal high frequency RC oscillator

Each oscillator is optimized for a given frequency range in terms of consumption and is selectable through the option byte. The associated hardware configurations are shown in

Table 8. Refer to the electrical characteristics section for more details.

8-BIT

LITE TIMER 2 COUNTER

/32

OSC

MCCSR

SMS

MCO

LTIMER

(1ms timebase @ 8 MHz f

CPU

TO CPU AND PERIPHERALS

CPU

OSC

)

MCO

38/226

ST7FOXF1, ST7FOXK1, ST7FOXK2 Supply, reset and clock management

6.2.1 External clock source

In this external clock mode, a clock signal (square, sinus or triangle) with ~50% duty cycle has to drive the OSC1 pin while the OSC2 pin is tied to ground.

Note: When the Multi-Oscillator is not used OSCI1 and OSCI2 must be tied to ground, and PB1 is

selected by default as the external clock.

6.2.2 Crystal/ceramic oscillators

In this mode, with a self-controlled gain feature, oscillator of an y frequency from 1 to 16 MHz can be placed on OSC1 and OSC2 pins. This family of oscillators has the advantage of producing a very accurate rate on the main clock of the ST7. In this mode of the multioscillator, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and start-up stabilization time. The loading capacitance values must be adjusted according to the selected oscillator.

These oscillators are not stopped during the RESET phase to avoid losing time in the oscillator start-up phase.

6.2.3 Internal RC oscillator

In this mode, the tunable RC oscillator is used as main clock source. The two oscillator pins have to be tied to ground.

The calibration is done through the RCCRH[7:0] and RCCRL[6:5] registers.

Table 8. ST7 clock sources

Hardware configuration

ST7

OSC1 OSC2

External Clock

EXTERNAL

SOURCE

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Supply, reset and clock management ST7FOXF1, ST7FOXK1, ST7FOXK2

Table 8. ST7 clock sources

Hardware configuration

ST7

OSC1 OSC2

CAPACITORS

Crystal/Ceramic ResonatorsInternal RC Oscillator

OSC1 OSC2

6.3 Reset sequence manager (RSM)

6.3.1 Introduction

The reset sequence manager includes three RESET sources as shown in Figure 14:

● External RESET source pulse

● Internal LVD RESET (Low Voltage Detection)

● Internal WATCHDOG RESET

LOAD

ST7

Note: A reset can also be triggered following the detection of an illegal opcode or prebyte code.

Refer to Section 11.2.1 on page 184 for further details.

These sources act on the RESET

pin and it is always kept low during the delay phase.

The RESET service routine vector is fixed at addresses FFFEh-FFFFh in the ST7 me mory mapping.

The basic RESET sequence consists of 3 phases as shown in Figure 13:

● Active Phase depending on the RESET source

● 256 or 4096 CPU clock cycle dela y (see Table 13)

Caution: When the ST7 is unprogrammed or fully erased, the Flash is blank and the Reset vector is

not programmed. For this reason, it is recommended to keep the RESET

pin in low state

until programming mode is entered, in order to avoid unwanted behavior. The 256 or 4096 CPU clock cycle delay allows the oscillator to stabilize and ensures that

recovery has taken place from the Reset state. The shorter or longer clock cycle delay is automatically selected depending on the clock source chosen by option byte.

The Reset vector fetch phase duration is 2 clock cycles.

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ST7FOXF1, ST7FOXK1, ST7FOXK2 Supply, reset and clock management

Table 9. CPU clock delay during Reset sequence

Clock source CPU clock cycle delay

Internal RC 8 MHz Oscillator 4096

Internal RC 32 kHz Oscillator 256

External clock (connected to CLKIN/PB1 pin) 4096

External Crystal/Ceramic Oscillator (connected to OSC1/OSC2 pins) 4096

External Crystal/Ceramic 1-16 MHz Oscillator 4096

External Crystal/Ceramic 32 kHz Oscillator 256

Figure 13. Reset sequence phases

RESET

active phase

Internal reset

256 or 4096 clock cycles

Fetch

vector

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Supply, reset and clock management ST7FOXF1, ST7FOXK1, ST7FOXK2

6.3.2 Asynchronous external RESET pin

The RESET pin is both an input and an open-dr ai n o utput wit h inte grated RON weak pull-up resistor. This pull-up has no fixed value but varies in accordance with the input voltage. It can be pulled low by external circuitry to reset the device. See Electrical Characteristic section for more details.

A RESET signal originating from an external source must have a duration of at least t

h(RSTL)in

in order to be recognized (see Figure 15: Reset sequences). This detection is

asynchronous and therefor e the MCU can enter reset state even in Halt mode. The RESET

pin is an asynchronous signal which pla ys a major role in EMS perf ormance. In a noisy environment, it is recommended to follow the guidelines mentioned in the electrical characteristics section.

Figure 14. Reset block diagram

RESET

1. See Section11.2.1: Illegal opcode reset on page 184 for more details on illegal opcode reset conditions.

6.3.3 External power-on reset

If the LVD is disabled by option byte, to start up the microcontroller correctly, the user must ensure by means of an external reset circuit that the reset signal is held low until V the minimum level specified for the selected f

A proper reset signal for a slow rising V RC network connected to the RESET

Filter

GENERATOR

pin.

INTERNAL RESET

___

PULSE

frequency.

OSC

supply can generally be provided by an external

WATCHDOG RESET

___

ILLEGAL OPCODE RESET

___

LVD RESET

is over

6.3.4 Internal Low Voltage Detector (LVD) reset

Two different Reset sequences caused by the internal LVD circuitry can be distinguished:

● Power-On reset

● Voltage Drop reset

The device RESET (rising edge) or V

The LVD filters spikes on V

42/226

pin acts as an output that is pulled low when V

lower than V

(falling edge) as shown in Figure 15.

IT-

larger than t

to avoid parasitic resets.

g(VDD)

is lower than V

IT+

ST7FOXF1, ST7FOXK1, ST7FOXK2 Supply, reset and clock management

6.3.5 Internal watchdog reset

The Reset sequence generated by an internal watchdog counter overflow is shown in

Figure 15: Reset sequences

Starting from the watchdog counter underflow, the de vice RESET is pulled low during at least t

w(RSTL)out

Figure 15. Reset sequences

IT+(LVD)

IT-(LVD)

EXTERNAL

RESET

ACTIVE

PHASE

WATCHDOG UNDERFLOW

RUN RUN

INTERNAL RESET (256 or 4096 T VECTOR FETCH

EXTERNAL RESET SOURCE

RESET PIN

WATCHDOG RESET

RUN

LVD

RESET

ACTIVE PHASE

RUN

h(RSTL)in

pin acts as an output that

WATCHDOG

RESET

ACTIVE PHASE

w(RSTL)out

)

CPU

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Supply, reset and clock management ST7FOXF1, ST7FOXK1, ST7FOXK2

6.4 System Integrity management (SI)

The System Integrity Management block contains the Low voltage Detector (LVD).

Note: A reset can also be triggered following the detection of an illegal opcode or prebyte code.

Refer to Section 11.2.1 on page 184 for further details.

6.4.1 Lo w Voltage Detector (LVD)

The Low Voltage Detector function (LVD) generates a static reset when the VDD supply voltage is below a V as the power-down keeping the ST7 in reset.

reference v alue . Th is means th at it secu res the po w er-up as well

IT-(LVD)

The V

reference value for a voltage drop is lower than the V

IT-(LVD)

IT+(LVD)

reference value for power-on in order to avoid a parasitic reset when the MCU starts running and sinks current on the supply (hysteresis).

The LVD Reset circuitry generates a reset when V

● V

IT+(LVD) IT-(LVD)

when VDD is rising

when VDD is falling

is below:

The LVD function is illustrated in Figure 16. The voltage threshold can be enabled/disabled by option byte. See Section 13.1 on page

211.

Provided the minimum V

value (guaranteed for the oscillator frequency) is abov e V

IT-(LVD)

the MCU can only be in two modes:

● Under full software control

● In static safe reset

In these conditions, secure oper at ion is always ensured for t he app lica tion wit hou t th e ne ed for external reset hardware.

During a Low Voltage Detector Reset, the RESET

pin is held low, thus permitting the MCU

to reset other devices.

Note: Use of LVD with capacitive power supply: with this type of power supply, if power cuts occur

in the application, it is recommended to pull V

down to 0 V to ensure optimum restart

conditions. Refer to circuit example in Figure 89 on page 207 and note 4. The LVD is an optional function which can be selected by option byte. See Section 13.1 on

page 211.

It allows the device to be used without any e x ternal RESET circuitry.

If the LVD is disabled, an external circuitry must be used to ensure a proper power-on reset.

It is recommended to make sure that the V

supply voltage rises monotonously when the

device is exiting from Reset, to ensure the application functions properly.

Caution: If an LVD reset occurs after a watchdog reset has occurred, the LVD will take priority and will

clear the watchdog flag.

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ST7FOXF1, ST7FOXK1, ST7FOXK2 Supply, reset and clock management

Figure 16. Low voltage detector vs reset

IT+(LVD)

IT-(LVD)

hys

RESET

Figure 17. Reset and supply management block diagram

RESET

WATCHDOG

TIMER (WDG)

RESET SEQUENCE

MANAGER

(RSM)

STATUS FLAG

SYSTEM INTEGRITY MANAGEMENT

RCCRL

LVDRF

CR0CR1

0WDGF

LOW VOLTAGE

DETECTOR

(LVD)

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Supply, reset and clock management ST7FOXF1, ST7FOXK1, ST7FOXK2

6.5 Register description

6.5.1 RC calibration control/status register (RCC_CSR)

Reset value: 0000 0000 (00h)

7 0 000000RCCLAT RCCPGM

Read/write

Bits 7:2 = Reserved, forced by hardware to 0

0: Read mode 1: Write mode

Bit 1 = RCCLAT Latch Access Transfer bit: this bit is set by software.

It is cleared by hardw are at the end o f the pr ogr amming cycle. It can on ly be cleare d b y software if the RCCPGM bit is cleared

Bit 0 = RCCPGM Programming Control and Status bit

This bit is set by software to begin the programming cycle. At the end of the programming cycle, this bit is cleared by hardware.

0: Programming finished or not yet started 1: Programming cycle is in progress

Note: If the RCCPGM bit is cleared during the programming cycle, the memory data is not

guaranteed.

6.5.2 Main Clock Control/Status Register (MCCSR)

Reset value: 0000 0000 (00h)

7 0 000000MCOSMS

Read/write

Bits 7:2 = Reserved, must be kept cleared. Bit 1 = MCO Main Clock Out enable

This bit is read/write by software and cleared by hardware after a reset. This bit allows to enable the MCO output clock.

0: MCO clock disabled, I/O port free for general purpose I/O. 1: MCO clock enabled.

Bit 0 = SMS Slow mode selection

This bit is read/write by software and cleare d b y hardw are af ter a reset. This bit selects the input clock f

0: Normal mode (f 1: Slow mode (f

or f

OSC

CPU = fOSC

OSC

CPU = fOSC

bit

/32.

/32)

46/226

ST7FOXF1, ST7FOXK1, ST7FOXK2 Supply, reset and clock management

6.5.3 RC Control Register High (RCCRH)

Reset value: 1111 1111 (FFh)

7 0

CR9 CR8 CR7 CR6 CR5 CR4 CR3 CR2

Read/write

Bits 7:0 = CR[9:2] RC Oscillator Frequency Adjustment bits

These bits must be written immediately after reset to adjust the RC oscillator frequency. The application can store the correct value for each voltage range in Flash memory and write it to this register at start-up.

00h = maximum available frequency FFh = lowest available frequency These bits are used with the CR[1:0] bits in the RCCRL register. Refer to

Chapter 6.5.4.

Note: To tune the oscillator, write a series of different values in the register until the correct

frequency is reached. The fastest meth od is to use a dichotomy starting with 80h.

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Supply, reset and clock management ST7FOXF1, ST7FOXK1, ST7FOXK2

6.5.4 RC Control Register Low (RCCRL)

Reset value: 011x 0x00 (xxh)

7 0

0 CR1 CR0 WDGRF 0 LVDRF 0 0

Read/write

Bit 7 = Reserved, must be kept cleared Bits 6:5 = CR[1:0] RC Oscillator Frequency Adjustment bits

These bits, as well as CR[9:2] bits in the RCCRH register must be written immediately after reset to adjust the RC oscillator frequency. Refer to Section 6.1.1: Internal RC

oscillator on page 34.

Bit 4 = WDGRF Watchdog Reset flag This bit indicates that the last reset was generated by the watchdog peripheral. It is set by

hardware (watchdog reset) and cleared by software (writing zero) or an LVD Reset (to ensure a stable cleared state of the WDGRF flag when CPU starts). The WDGRF and the LVDRF flags areis used to select the reset source (see Table 10: Reset source selection on

page 48).

Table 10. Reset source selection

RESET source LVDRF WDGRF

External RESET

Watchdog 0 1

LVD 1 X

pin 0 0

Bit 3 = Reserved, must be kept cleared Bit 2 = LVDRF LVD reset flag

This bit indicates that the last Reset was generated by the LVD block. It is set by hardware (LVD reset) and cleared by software (by re ading). When the LVD is disabled by option byte, the LVDRF bit value is undefined.

The LVDRF flag is not cleared when another RESET type occurs (external or watchdog), the LVDRF flag remains set to keep trace of the original failure. In this case, a watchdog reset can be detected by software while an external reset can not.

Bits 1:0 = Reserved, must be kept cleared

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ST7FOXF1, ST7FOXK1, ST7FOXK2 Supply, reset and clock management

6.5.5 Prescaler register (PSCR)

Reset value: 0000 0000 (00h) for ST7FOXF1 and ST7FOXK1 Reset value: 0000 0011 (03h) for ST7FOXK2

7 0

CK2 CK1 CK0 0 0 0 0 or 1 0 or 1

Read/write

Bits 7:5 = CK[2:0] internal RC Prescaler Selection

These bits are set by softw are and clear ed by hardware after a reset. These bits select the prescaler of the internal RC oscillator. See Table 11.

If the internal RC is used with a supply operating range below 3.3 V, a division ratio of at least 2 must be enabled in the RC prescaler.

Table 11. Internal RC prescaler selection bits

CK2 CK1 CK0 f

001 f 010 f 011 f 100 f

others f

OSC

RC/2 RC/4 RC/8

RC/16

Bits 4:2 = Reserved, must be cleared. Bits 1:0 = Must be set.

Caution: For ST7FOXF1 and ST7FOXK1 devices, PRSC[1:0] bits must be forced to 1 by software in

order to reduce current consumption.

6.5.6 Clock controller control/status register (CKCNTCSR)

Reset value: 0000 1001 (09h)

7 0

0 0 0 0 AWU_FLAG RC_FLAG 0 RC/AWU

Read/write

Bits 7:4 = Reserved, must be kept cleared. Bit 3 = AWU_FLAG AWU Selection

bit

This bit is set and cleared by hardware. 0: No switch from AWU to RC requested 1: AWU clock activated and temporization completed

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Supply, reset and clock management ST7FOXF1, ST7FOXK1, ST7FOXK2

Bit 2 = RC_FLAG RC Selection

bit

This bit is set and cleared by hardware. 0: No switch from RC to AWU requested

1: RC clock activated and temporization completed Bit 1 = Reserved, must be kept cleared . Bit 0 = RC/AWU RC/AWU Selection

bit

0: RC enabled

1: AWU enabled (default value)

Table 12. Clock register mapping and reset values

Addre

(Hex.)

0035h RCC_CSR

003Ah

003Bh

003Ch

003Dh

0051h

label

MCCSR

Reset Value

RCCRH

Reset Value

RCCRL

Reset Value

PSCR

Reset Value

CKCNTCSR

Reset Value

765 4 32 1 0

CR9

CK2

CR8

CR1

CK1

CR7

CR01WDGRF

CK0

CR6

CR5

AWU_

FLAG

CR4

LVDRF

RC_FLA

RCCLAT0RCCPGM

MCO

CR3

0 or 1

SMS

CR2

0 or 1

RC/AWU

50/226

ST7FOXF1, ST7FOXK1, ST7FOXK2 Interrupts

7 Interrupts

7.1 Introduction

The ST7 enhanced interrupt management provides th e following features:

● Hardware interrupts

● Software interrupt (TRAP)

● Nested or concurrent interrupt management with flexible interrupt priority and level

management:

– Up to 4 software programmable nesting levels

– 13 interrupt vectors fixed by hardware

– 2 non maskable events: RESET, TRAP This interrupt management is based on :

● Bit 5 and bit 3 of the CPU CC register (I1:0),

● Interrupt software priority registers (ISPRx),

● Fixed interrupt vector addresses located at the high addresses of the memory mapping

(FFE0h to FFFFh) sorted by hardware priority order. This enhanced interrupt controller guarantees full upward compatibility with the standard

(not nested) ST7 interrupt controller.

7.2 Masking and processing flow

The interrupt masking is managed by the I1 and I0 bits of the CC register and the ISPRx registers which give the interrupt software priority level of each interrupt vector (see

Table 13). The processing flow is shown in Figure 18.

When an interrupt request has to be serviced:

● Normal processing is suspended at the end of the current instruction execution.

● The PC, X, A and CC registers are saved onto the stack.

● I1 and I0 bits of CC register are set according to the correspondin g v alues in the I SPRx

registers of the serviced interrupt vector.

● The PC is then loaded with the interrupt vector of the interrupt to service and the first

instruction of the interrupt service routine is fetched (refer to interrupt mapping table f o r

vector addresses). The interrupt service routine should end with the IRET instruction which causes the

contents of the save d registers to be recovered from the stack.

Note: As a consequence of the IRET instruction, the I1 and I0 bits will be restored from the stack

and the program in the previous level will resume.

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Interrupts ST7FOXF1, ST7FOXK1, ST7FOXK2

Table 13. Interrupt software priority levels

Interrupt software priority Level I1 I0

Level 0 (main)

Level 1 Level 2 0

Level 3 (= interrupt disable) 1 1

Figure 18. Interrupt processing flowchart

RESET

RESTORE PC, X, A, CC

FROM STACK

PENDING

INTERRUPT

FETCH NEXT

INSTRUCTION

“IRET”

EXECUTE

INSTRUCTION

Low

High

Interrupt has the same or a

lower software priority

than current one

THE INTERRUPT STAYS PENDING

STACK PC, X, A, CC

LOAD I1:0 FROM INTERRUPT SW REG.

LOAD PC FROM INTERRUPT VECTOR

TLI

I1:0

software priority

Interrupt has a higher

than current one

52/226

ST7FOXF1, ST7FOXK1, ST7FOXK2 Interrupts

7.2.1 Servicing pending interrupts

As sever al interrupts can be p ending at the sam e time , the interrupt to b e tak en into account is determined by the following two-step process:

● The highest software priority interrupt is serviced,

● If sever al interrupts have the same software priority then the interrupt with the highest

hardware priority is serviced first.

Figure 19 describes this decision process.

Figure 19. Priority decision process

PENDING

INTERRUPTS

Same

HIGHEST HARDWARE

PRIORITY SERVICED

SOFTWARE

PRIORITY

HIGHEST SOFTWARE

PRIORITY SERVICED

Different

When an interrupt request is not serviced immediately, it is latched and then processed when its software priority combined with the hardware priority becomes the highest one.

Note: 1 The hardware priority is exclusive while the software one is not. This allows the previous

process to succeed with only one interrupt.

2 RESET and TRAP can be considered as having the highest software priority in the decision

process.

7.2.2 Interrupt vector sources

Two interrupt source types are managed by the ST7 interrupt controller: the non-maskable type (RESET, TRAP) and the maskable type (external or from internal peripherals).

Non-maskable sources

These sources are processed regardless of the state of the I1 and I0 bits of the CC register (see Figure 18). After stacking the PC, X, A and CC registers (except for RESET), the corresponding vector is loaded in the PC register and the I1 and I0 bits of the CC are set to disable interrupts (level 3). These sources allow the processor to exit Halt mode.

● TRAP (non maskable software interrupt)

This software interrupt is serviced when the TRAP instruction is executed. It will be

serviced according to the flowchart in Figure 18.

● RESET

The RESET source has the highest priority in the ST7. This means t hat the fi rst current

routine has the highest software priority (le vel 3) and the highest hardware priority.

See the RESET chapter for more details.

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Interrupts ST7FOXF1, ST7FOXK1, ST7FOXK2

Maskable sources

Maskable interrupt vector sources can be serviced if the corresponding interrupt is enabled and if its own interrupt software priority (in ISPRx registers) is higher than the one currently being serviced (I1 and I0 in CC register). If any of these tw o conditions is false, the interrupt is latched and thus remains pending.

● External interr up ts

External interrup ts allow the pro ces so r to exit from Halt low power mode.

External interrup t s ensit ivity is s oftware select able through th e Exte rnal Interrupt

Control register (EICR).

External interrupt triggered on edge will be latched and the interrupt request

automatically cleared upon entering the interrupt service routine.

If several input pins of a group connected to the same interrupt line are selected

simultaneously, these will be logically ORed.

● Peripheral inter rupts

Usually the peripheral interrupts cause the MCU to exit from Halt mode except those

mentioned in Table 17: ST7FOXF1/ST7FOXK1 Interrupt mapping.

A peripheral interrupt occurs when a specific flag is set in the peripheral status

registers and if the corresponding enable bit is set in the peripheral control register.

The general sequence for clearing an interrupt is based on an access to the status

Note: The clearing sequence resets the internal latch. A pending interrupt (that is, waiting for

being serviced) will therefore be lost if the clear sequence is executed.

7.3 Interrupts and low power modes

All interrupts allow the processor to exit the Wait low power mode. On the contrary, only external and other specified interrupts allow the processor to exit from the Halt modes (see column “Exit from Halt” in Table 17: ST7FOXF1/ST7FOXK1 Interrupt mapping). When several pending interrupts are present while exiting Halt mode, the first one serviced can only be an interrupt with exit from Halt mode capability and it is selected through the same decision process shown in Figure 19.

Note: If an interrupt, that is not able to Exit from Halt mode, is pending with the highest priority

when exiting Halt mode, this interrupt is serviced after the first one serviced.

54/226

ST7FOXF1, ST7FOXK1, ST7FOXK2 Interrupts

7.4 Concurrent and nested management

The following Figure 20 and Figure 21 show two different inte rrupt management modes. The first is called concurrent mode and does not allow an interrupt to be interrupted, unlike the nested mode in Figure 21. The interrupt hardware priority is given in this order from the lowest to the highest: MAIN, IT5, IT4, IT3, IT2, IT1, IT0. The software priority is given for each interrupt.

Caution: A stack overflow may occur without notifying the software of the failure.

Figure 20. Concurrent interrupt management

IT0

IT1

IT0

IT1

IT2

RIM

IT3

IT2

IT5

IT4

IT2

HARDWARE PRIORITY

MAIN

11 / 10

Figure 21. Nested interrupt management

IT4

IT0

IT4

IT1

TLI

IT4

HARDWARE PRIORITY

RIM

MAIN

11 / 10

IT3

IT2

IT5

IT1

IT0

IT4

IT3

IT1

IT5

SOFTWARE PRIORITY LEVEL

MAIN

SOFTWARE PRIORITY LEVEL

IT2

MAIN

3 3 3 3 3 3 3/0

3 3 2 1 3 3 3/0

11 11 11 11 11 11

I1 I0

11 11 00 01 11 11

USED STACK = 10 BYTES

USED STACK = 20 BYTES

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Interrupts ST7FOXF1, ST7FOXK1, ST7FOXK2

7.5 Description of interrupt registers

7.5.1 CPU CC register interrupt bits

Reset value: 111x 1010(xAh)

7 0 11I1HI0NZC

Read/write

Bits 5, 3 = I1, I0 Software Interrupt Priority

bits

These two bits indicate the current interrupt software priority (see Table 14).

These two bits are set/cleared by hardware when entering in interrupt. The loaded

value is given by the corresponding bits in the interrupt software priority registers

(ISPRx).

They can be also set/cleared by software with the RIM, SIM, HALT, WFI, IRET and

PUSH/POP instructions (see Table 16: Dedicated interrupt instruction set).

TRAP and RESET events can interrupt a level 3 program.

Table 14. Setting the interrupt software priority

Interrupt software priority Level I1 I0

Level 0 (main)

Level 1 Level 2 0

Level 3 (= interrupt disable*) 1 1

7.5.2 Interrupt software priority registers (ISPRx)

All ISPRx register bits are read/write except bit 7:4 of ISPR3 which are read only. Reset value: 1111 1111 (FFh)

Low

High

ISPR0 I1_3 I0_3 I1_2 I0_2 I1_1 I0_1 I1_0 I0_0 ISPR1 I1_7 I0_7 I1_6 I0_6 I1_5 I0_5 I1_4 I0_4 ISPR2 I1_11 I0_11 I1_10 I0_10 I1_9 I0_9 I1_8 I0_8 ISPR3 111111I1_12I0_12

ISPRx registers contain the interrupt software priority of each interrupt vector. Each interrupt vector (except RESET and TRAP) has corresponding bits in these registers to define its software priority. This correspondence is shown in Table 15.

Each I1_x and I0_x bit value in the ISPRx registers has the same meaning as the I1 and I0 bits in the CC register.

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ST7FOXF1, ST7FOXK1, ST7FOXK2 Interrupts

The RESET and TRAP vectors hav e no software priorities. When one is serviced, the I1 and I0 bits of the CC register are both set.

Level 0 cannot be written (I1_x = 1, I0_x = 0). In this case, the previously stored value is kept (Example: previous = CFh, write = 64h, result = 44h).

Table 15. Interrupt vector vs ISPRx bits

Vector address ISPRx bits

FFFBh-FFFAh I1_0 and I0_0 bits

(1)

FFF9h-FFF8h I1_1 and I0_1 bits

... ...

FFE1h-FFE0h I1_13 and I0_13 bits

1. Bits in the ISPRx registers can be read and written but they are not significant in the interrupt process

management.

Caution: If the I1_x and I0_x bits are modified while the interrupt x is executed the following behavior

has to be considered: If the interrupt x is still pending (new interrupt or flag not cleared) and the new software priority is higher than the previous one, the interrupt x is re-entered. Otherwise, the software priority stays unchanged up to the next interrupt request (after the IRET of the interrupt x).

Table 16. Dedicated interrupt instruction set

(1)

Instruction New description Function/Example I1 H I0 N Z C

HALT Entering Halt mode 1 0

IRET Interrupt routine return Pop CC, A, X, PC I1 H I0 N Z C

JRM Jump if I1:0 = 11 (level 3) I1:0 = 11

JRNM Jump if I1:0 <> 11 I1:0 <> 11

POP CC Pop CC from the Stack Mem => CC I1 H I0 N Z C

RIM Enable interrupt (level 0 set) Load 10 in I1:0 of CC 1 0 SIM Disable interrupt (level 3 set) Load 11 in I1:0 of CC 1 1

TRAP Software trap Software NMI 1 1

WFI Wait for interrupt 1 0

1. During the execution of an interrupt routine, the HALT, POPCC, RIM, SIM and WFI instructions change the

current software priority up to the next IRET instruction or one of the previously mentioned instructions.

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Interrupts ST7FOXF1, ST7FOXK1, ST7FOXK2

Table 17. ST7FOXF1/ST7FOXK1 Interrupt mapping

Exit

from

Number

Source

block

Description

RESET Reset

label

Priority

order

HALT

AWUFH

(1)

Address

vector

yes FFFEh-FFFFh

N/A

TRAP Software interrupt no FFFCh-FFFDh

0 AWU Auto Wake Up interrupt AWUCSR yes

(2)

FFFAh-FFFBh

Highest

1 Reserved - FFF8h-FFF9h 2 ei0 External interrupt 0 (Port A) 3 e i1 External interrupt 1 (Port B) FFF4h-FFF5h

N/A

Priority

FFF6h-FFF7

yes 4 ei2 External interrupt 2 (Port C) FFF2h-FFF3h 5

AT timer Output Compare interrupt

no FFF0h-FFF1h

6 AT timer input Capture interrupt no FFEEh-FFEFh

(3)

AT TIMER

AT timer overflow 1 interrupt no FFECh-FFEDh

ATCSR

8 AT timer Overflow 2 interrupt no FFEAh-FFEBh

(3)

C interrupt N/A no FFE8h-FFE9h

Lite timer RTC interrupt

Lowest

yes FFE6h-FFE7h

Priority

11 Lite timer Input Capture interrupt no FFE4h-FFE5h

LITE TIMER

LTCSR2

12 Lite timer RTC2 interrupt no FFE2h-FFE3h

1. For an interrupt, all events do not have the same capability to wake up the MCU from Halt, Active-Halt or Auto Wake-up from Halt modes. Refer to the description of interrupt events for more details.

2. This interrupt exits the MCU from Auto Wake-up from Halt mode only.

3. These interrupts exit the MCU from Active-Halt mode only.

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ST7FOXF1, ST7FOXK1, ST7FOXK2 Interrupts

Table 18. ST7FOXK2 interrupt mapping

Exit

from

Number

Source

block

Description

label

Priority

order

HALT

AWUFH

(1)

Address

vector

RESET Reset

yes FFFEh-FFFFh

N/A

TRAP Software interrupt no FFFCh-FFFDh

0 AWU Auto Wake Up interrupt AWUCSR yes

(2)

FFFAh-FFFBh 1 Reserved - FFF8h-FFF9h 2 Reserved - FFF6h-FFF7h 3 Reserved - FFF4h-FFF5h 4 ei0 External interrupt 0 (Port A) 5 e i1 External interrupt 1 (Port B) FFF0h-FFF1h

N/A yes

Highest

Priority

FFF2h-FFF3h

6 ei2 External interrupt 2 (Port C) FFEEh-FFEFh

(3)

AT TIMER

AT timer input Capture/Output

Compare interrupt

AT timer overflow 1 interrupt no FFEAh-FFEBh

ATCSR

no FFECh-FFEDh

9 AT timer Overflow 2 interrupt no FFE8h-FFE9h

10 I

C interrupt

11 SPI SPI interrupt SPICSR no FFE4h-FFE5h

I2CSR1/ I2CSR2

no FFE6h-FFE7h

Lowest Priority

12 TIM16 16-bit timer peripheral interrupt TACSR no FFE2h-FFE3h

(3)

1. For an interrupt, all events do not have the same capability to wake up the MCU from Halt, Active-Halt or Auto-wakeup from Halt modes. Refer to the description of interrupt events for more details.

2. This interrupt exits the MCU from Auto-wakeup from Halt mode only.

3. These interrupts exit the MCU from Active-Halt mode only.

LITE TIMER Lite timer RTC/IC/RTC2 interrupt LTCSR2 yes FFE0h-FFE1h

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Interrupts ST7FOXF1, ST7FOXK1, ST7FOXK2

7.5.3 External Interrupt Control register (EICR)

Reset value: 0000 0000 (00h)

7 0

0 0 IS21 IS20 IS11 IS10 IS01 IS00

Read/write

Bits 7:6 = Reserved, must be kept cleared. Bits 5:4 = IS2[1:0] ei2 sensitivity

bits

These bits define the interrupt sensitivity for ei2 (Port C) according to Table 19.

Bits 3:2 = IS1[1:0] ei1 sensitivity

bits

These bits define the interrupt sensitivity for ei1 (Port B) according to Table 19.

Bits 1:0 = IS0[1:0] ei0 sensitivity

bits

These bits define the interrupt sensitivity for ei0 (Port A) according to Table 19.

Note: 1 These 8 bits can be written only when the I bit in the CC register is set.

2 Changing the sensitivity of a particular external interrupt clears this pending interrupt. This

can be used to clear unwanted pending interrupts. Refer to Section : External interrupt

function.

Table 19. Interrupt sensitivity bits

ISx1 ISx0 External interrupt sensitivity

0 0 Falling edge & low level 0 1 Rising edge only 1 0 Falling edge only 1 1 Rising and falling edge

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ST7FOXF1, ST7FOXK1, ST7FOXK2 Power saving modes

8 Power saving modes

8.1 Introduction

To give a large measure of flexibility to the application in terms of power consumption, four main power saving mod es are implemented in the ST7 (see Figure 22):

● Slow

● Wait (and Slow-Wait)

● Active Halt

● Auto wakeup From Halt (AWUFH)

● Halt

After a reset the normal operating mode is selected by default (Run mode). This mode drives the device (CPU and embedded peripherals) by means of a master clock which is based on the main oscillator frequency (f

From Run mode, the different power saving modes may be selected by setting the relevant register bits or by calling the specific ST7 software instruction whose action depends on the oscillator status.

Figure 22. Power saving mode t ransitions

OSC

High

Run

Slow

Wait

Slow Wait

Active Halt

Halt

Low

POWER CONSUMPTION

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Power saving modes ST7FOXF1, ST7FOXK1, ST7FOXK2

8.2 Slow mode

This mode has two targets:

● To reduce power consumption by decreasing the internal clock in the device,

● To adapt the internal clock frequency (f

Slow mode is controlled by the SMS bit in the MCCSR register which enables or disables Slow mode.

In this mode, the oscillator frequency is divided by 32. The CPU and peripherals are clock ed at this lower frequency.

Note: Slow-Wait mode is activated when entering Wait mode while the device is already in Slow

mode.

Figure 23. Slow mode clock transition

CPU

OSC

) to the available supply voltage.

CPU

/32 f

OSC

8.3 Wait mode

Wait mode places the MCU in a low power consumption mode by stopping the CPU. This power saving mode is selected by calling the ‘WFI’ instruction. All peripherals remain active. During Wait mode, the I bit of the CC register is cleared, to

enable all interrupts. All other registers and memory remain unchanged. The MCU remains in Wait mode until an interrupt or Reset occurs, whereupon the Program Counter branches to the starting address of the interrupt or Reset service routine.

The MCU will remain in Wait mode until a Reset or an Interrupt occurs, causing it to wake up.

Refer to Figure 24 for a description of the Wait mode flowchart.

SMS

NORMAL RUN MODE

REQUEST

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ST7FOXF1, ST7FOXK1, ST7FOXK2 Power saving modes

Figure 24. Wait mode flowchart

WFI INSTRUCTION

INTERRUPT

OSCILLATOR PERIPHERALS CPU IBIT

RESET

OSCILLATOR PERIPHERALS CPU IBIT

256 CPU CLOCK CYCLE

DELAY

OSCILLATOR PERIPHERALS CPU IBIT

FETCH RESET VECTOR

OR SERVICE INTERRUPT

ON ON

OFF

ON ON ON

1. Before servicing an interrupt, the CC register is pushed on the stack. The I bit of the CC register is set during the interrupt routine and cleared when the CC register is popped.

8.4 Active-halt and halt modes

Active-Halt and Halt modes are the two low est po wer consumption modes of the MCU. They are both entered by executing the ‘HALT’ instruction. The decision to enter either in ActiveHalt or Halt mode is given by the LTCSR/A TCSR register status as shown in the following table:

Table 20. Enabling/disabling active-halt and halt modes

LTCSR TBIE

bit

0xx0

0111 1xxx x101

A TCSR O VFIE

bit

ATCSRCK1 bit ATCSRCK0 bit Meaning

Active-Halt mode disabled00xx

Active-Halt mode enabled

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Power saving modes ST7FOXF1, ST7FOXK1, ST7FOXK2

8.4.1 Active-halt mode

Active-Halt mode is the lowest power consumption mode of the MCU with a real-time clock available. It is entered by executing the ‘HALT’ instruction when active halt mode is enabled.

The MCU can exit Active- Halt mode on reception of a Lite timer/ AT timer interrupt or a Reset.

● When exiting Active-Halt mode by means of a Reset, a 256 CPU cycle delay occurs.

After the start up delay, the CPU resumes operation by fetching the Re set v ect or which woke it up (see Figure 26).

● When exiting Active-Halt mode by means of an interrupt, the CPU immediately

resumes operation by servicing the interrupt vector which woke it up (see Figure 26).

When entering Active-Halt mode, the I bit in the CC register is cleared to enable interrupts. Therefore , if an interrupt is pending, the MCU wakes up immediately.

In Active-Halt mode, only the main oscillator and the selected timer counter (LT/AT) are running to keep a wakeup time base. All other peripherals are not clocked except those which get their clock supply from another clock generator (such as external or auxiliary oscillator).

Caution: As soon as Active-Halt is enabled, executing a HALT instruction while the Watchdog is

active does not generate a Reset if the WDGHALT bit is reset. This means that the device cannot spend more than a defined delay in this power saving mode.

Figure 25. Active-halt timing overview

ACTIVE

HALTRUN RUN

[Active Halt Enabled]

1. This delay occurs only if the MCU exits Active-Halt mode by means of a RESET.

HALT

INSTRUCTION

256 CPU

CYCLE DELAY

RESET

INTERRUPT

FETCH

VECTOR

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ST7FOXF1, ST7FOXK1, ST7FOXK2 Power saving modes

Figure 26. Active-halt mode flowchart

HALT INSTRUCTION

(Active Halt enabled)

INTERRUPT

OSCILLATOR PERIPHERALS CPU

IBIT

RESET

256 CPU CLOCK CYCLE

FETCH RESET VECTOR

OR SERVICE INTERRUPT

OSCILLATOR PERIPHERALS CPU

IBIT

DELAY

OSCILLATOR PERIPHERALS CPU

IBITS

ON OFF OFF

ON OFF

1. This delay occurs only if the MCU exits Active-Halt mode by means of a RESET.

2. Peripherals clocked with an external clock source can still be active.

3. Only the Lite timer RTC and AT timer interrupts can exit the MCU from Active-Halt mode.

4. Before servicing an interrupt, the CC register is pushed on the stack. The I bit of the CC register is set during the interrupt routine and cleared when the CC register is popped.

8.4.2 Halt mode

The Halt mode is the lowest power consumption mode of the MCU. It is entered by executing the HALT instruction when active halt mode is disabled.

The MCU can exit Halt mode on reception of either a specific interrupt (seeTable 17:

ST7FOXF1/ST7FO XK1 Interrupt mapping) or a Reset. When exiting Halt mode b y means of

a Reset or an interrupt, the main oscillator is immediately turned on and the 256 CPU cycle delay is used to stabilize it. After the start up delay , the CPU resumes oper ation b y servicing the interrupt or by fetching the Reset vector which woke it up (see Figure 28).

When entering Halt mode, the I bit in the CC register is forced to 0 to enable interrupts. Therefore, if an interrupt is pending, the MCU wakes immediately.

In Halt mode, the main oscillator is turned off causing all internal processing to be stopped, including the operation of the on-chip p eripheral s . All peripher als are not clocked except the ones which get their clock supply from another clock generator (such as an external or auxiliary oscillator).

The compatibility of Watchdog operation with Halt mode is configured by the “WDGHALT” option bit of the option byte. The HALT instruction when executed while the Watchdog system is enabled, can generate a Watchdog Reset (see Section 13.1: Option bytes for more details).

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Power saving modes ST7FOXF1, ST7FOXK1, ST7FOXK2

Figure 27. Halt timing overview

HALTRUN RUN

HALT

INSTRUCTION

[Active Halt disabled]

256 CPU CYCLE

DELAY

RESET

INTERRUPT

FETCH

VECTOR

1. A reset pulse of at least 42 µs must be applied when exiting from Halt mode.

Figure 28. Halt mode flowchart

HALT INSTRUCTION

(Active Halt disabled)

WDGHALT

WATCHDOG

RESET

INTERRUPT

ENABLE

WATCHDOG

OSCILLATOR PERIPHERALS CPU IBIT

RESET

OSCILLATOR PERIPHERALS CPU IBIT

DISABLE

OFF

OFF OFF

OFF

1. WDGHALT is an option bit. See option byte section for more details.

2. Peripheral clocked with an external clock source can still be active.

3. Only some specific interrupts can exit the MCU from Halt mode (such as external interrupt). Refer to

Table 17: ST7FOXF1/ST7FOXK1 Interrupt mappingfor more details.

4. Before servicing an interrupt, the CC register is pushed on the stack. The I bit of the CC register is set during the interrupt routine and cleared when the CC register is popped.

5. The CPU clock must be switched to 1 MHz (RC/8) or AWU RC before entering Halt mode.

66/226

256 CPU CLOCK CYCLE

OSCILLATOR PERIPHERALS CPU IBITS

FETCH RESET VECTOR

OR SERVICE INTERRUPT

DELAY

ON ON ON

ST7FOXF1, ST7FOXK1, ST7FOXK2 Power saving modes

Halt mode recommendations

● Make sure that an external event is available to wake up the microcontroller from Halt

mode.

● When using an external interrupt to wake up the microcontroller, reinitialize the

corresponding I/O as “Input Pull-up with Interrupt” before executing the HALT instruction. The main reason for this is that the I/O may be wrongly configured due to external interference or by an unforeseen logical condition.

● For the same reason, reinitialize the level sensitiveness of each external interrupt as a

precautionary measure.

● The opcode for the HALT instruction is 0x8E. To avoid an unexpected HALT instruction

due to a Program Counter f ailu re, it is a dvised to clear a ll occurrences of the data v a lue 0x8E from memory. For example, avoid defining a constant in ROM with the value 0x8E.

● As the HALT instruction clears the I bit in the CC register to allow inter rupts, the user

may choose to clear all pending interrupt bits before executing the HALT instruction. This avoids entering other peripheral interrupt routines after executing the external interrupt routine corresponding to the w akeup event (reset or external interrupt).

8.5 Auto-wakeup from Halt mode

Auto wakeup from Halt (AWUFH) mode is similar to Halt mode with the addition of a specific internal RC oscillator for wakeup (Auto-wak eup from Halt oscillator) which replaces the main clock which was active before entering Halt mode. Compared to Active-Halt mode, AWUFH has lower power consumption (the main clock is not kept running), but there is no accurate real-time clock available.

It is entered by executing the HALT instruction when the AWUEN bit in the AWUCSR register has been set.

Figure 29. AWUFH mode block diagram

AWU RC

oscillator

AWU_RC

/64

divider

to 8-bit timer Input Capture

AWUFH

prescaler/1 .. 255

interrupt

(ei0 source)

67/226

Power saving modes ST7FOXF1, ST7FOXK1, ST7FOXK2

As soon as Halt mode is entered, and if the AWUEN bit has been set in the AWUCSR register, the A WU RC oscillator provides a clock signal (f

AWU_RC

). Its frequency is divided b y a fixed divider an d a prog r ammab le prescale r controlled by the AWUPR regist er. The output of this prescaler provides the dela y ti me. When the delay has elapsed, the following actions are performed:

● the AWUF flag is set by hardware,

● an interrupt wakes-up the MCU from Halt mode,

● the main oscillator is immediately turned on and the 256 CPU cycle delay is used to

stabilize it.

After this start-up delay, the CPU resumes operation by servicing the AWUFH interrupt. The AWU flag and its associated interrupt are cleared by software reading the AWUCSR register.

To compensate for any frequency dispersion of the AWU RC oscillator, it can be calibrated by measuring the clock frequency f

AWU_RC

and then calculating the right prescaler value. Measurement mode is enabled by setting the AWUM bit in the AWUCSR register in Run mode. This connects f f

AWU_RC

to be measured using the main oscillator clock as a reference timebase.

AWU_RC

to the Input Capture of the 8-bit Lite timer, allowing the

Similarities with halt mode

The following AWUFH mode behavior is the same as normal Halt mode:

● The MCU can exit AWUFH mode by means of any interrupt with exit from Halt

capability or a reset (see Section 8.4: Active-halt and halt modes).

● When entering AWUFH mode, the I bit in the CC register is forced to 0 to enable

interrupts. Theref ore, if an interrupt is pending, the MCU wakes up immediately.

● In AWUFH mode, the main oscillator is turned off causing all internal processing to be

stopped, including the operation of the on-ch ip peripherals . None of the peripherals ar e clocked except those which get their clock supply from anot her clock generator (such as an external or auxiliary oscillator like the AWU oscillator).

● The compatibility of watchdog operation with AWUFH mode is configured by the

WDGHALT option bit in the option b yte. Depending on this setting, the HALT instruction when ex ecuted while the w atchdog system is enab led, can gener ate a w atchdog Reset.

Figure 30. AWUF halt timing diagram

AWU

RUN MODE HALT MODE 256 t

CPU

AWU_RC

AWUFH interrupt

68/226

CPU

RUN MODE

Clear by software

ST7FOXF1, ST7FOXK1, ST7FOXK2 Power saving modes

Figure 31. AWUFH mode flowchart

HALT INSTRUCTION

(Active-Halt disabled)

(AWUCSR.AWUEN=1)

WDGHALT

WATCHDOG

RESET

INTERRUPT

ENABLE

AWU RC OSC ON MAIN OSC PERIPHERALS CPU I[1:0] BITS

AWU RC OSC OFF MAIN OSC PERIPHERALS

CPU I[1:0] BITS

256 CPU CLOCK

CYCLE

AWU RC OSC OFF MAIN OSC PERIPHERALS CPU I[1:0] BITS

FETCH RESET VECTOR OR SERVICE INTERRUPT

WATCHDOG

DISABLE

OFF

OFF OFF

RESET

OFF XX

DELAY

ON ON

ON ON ON

1. WDGHALT is an option bit. See option byte section for more details.

2. Peripheral clocked with an external clock source can still be active.

3. Only an AWUFH interrupt and some specific interrupts can exit the MCU from Halt mode (such as external

interrupt). Refer to Table 17: ST7FOXF1/ST7FOXK1 Interrupt mapping for more details.

4. Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the CC register are

set to the current software priority level of the interrupt routine and recovered when the CC register is popped.

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Power saving modes ST7FOXF1, ST7FOXK1, ST7FOXK2

8.5.1 Register description

8.5.2 AWUFH Control/Status Register (AWUCSR)

Reset value: 0000 0000 (00h)

7 0

00000

AWU

AWUM AWUEN

Read /Write

Bits 7:3 = Reserved Bit 2 = AWUF Auto wakeup flag

This bit is set by hardware when the AWU module generates an interrupt and clea red by software on reading AWUCSR. Writing to this bit does not change its value.

0: No AWU interrupt occurre d 1: AWU interrupt occurred

Bit 1 = AWUM Auto wakeup Measurement

bit

This bit enables the AWU RC oscillator and connects its output to the Input Capture of the 8-bit Lite timer. This allows the timer to be used to measure the AWU RC oscillator dispersion and then compensate this dispersion by providing the right value in the AWUPRE register.

0: Measurement disabled 1: Measurement enabled

Bit 0 = AWUEN Auto wakeup From Halt Enabled

bit

This bit enables the Auto wakeup from halt feature: once Halt mode is entered, the AWUFH wakes up the microcontroller after a time delay dependent on th e AWU prescaler value. It is set and cleared by software.

0: AWUFH (Auto wakeup fro m Halt) mode disabled 1: AWUF H (Auto wakeup from Halt) mode enabled

Note: Whatever the clock source, this bit should be set to enable the AWUFH mode once the

HALT instruction has been executed.

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ST7FOXF1, ST7FOXK1, ST7FOXK2 Power saving modes

8.5.3 AWUFH prescaler register (AWUPR)

Reset value: 1111 1111 (FFh)

7 0

AWUPR7 AWUPR6 AWUPR5 AWUPR4 AWUPR3 AWUPR2 AWUPR1 AWUPR0

Read /Write

Bits 7:0= AWUPR[7:0] Auto w akeup Prescaler

These 8 bits define the AWUPR Dividing factor (see Table 21).

Table 21. Configuring the dividing factor

AWUPR[7:0] Dividing factor

00h Forbidden 01h 1

... ...

FEh 254 FFh 255

In AWU mode , the time during which the MCU stays in Halt mode, t equation below. See also Figure 30 on page 68.

AWU

64 AWUPR×

--------------------

× t

AWURC

RCSTRT

The AWUPR prescaler register can be programmed to modify the time during which the MCU stays in Halt mode before waking up automatically.

Note: If 00h is written to AWUPR, the AWUPR remains unchanged.

Table 22. AWU register mapping and reset values

Address

(Hex.)

0048h

0049h

label

AWUCSR

Reset

Value

AWUPR

Reset

Value

76543210

00000AWUFAWUMAWUEN

AWUPR71AWUPR61AWUPR51AWUPR41AWUPR31AWUPR21AWUPR11AWUPR0

, is given by the

AWU

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I/O ports ST7FOXF1, ST7FOXK1, ST7FOXK2

9 I/O ports

9.1 Introduction

The I/O ports allow data transfer. An I/O port can contain up to 8 pins. Each pin can be programmed independently either as a digital inp ut or digital output. In addition, specific pins may have several other functions. These functions can include external interrupt, alternate signal input/output for on-chip periphe rals or analog input.

9.2 Functional description

A Data register (DR) and a Data Direction register (DDR) are always associated with each port. The Option register (OR), which allows input/output options, may or may not be implemented. The fo llowing d escription tak es into account the O R register. Refer t o the Port Configuration table for device specific information.

An I/O pin is programmed using the correspo nding bits in the DDR, DR and OR re gisters: bit x corresponding to pin x of the port.

Figure 32 shows the generic I/O block diagram.

9.2.1 Input modes

Clearing the DDRx bit selects input mode. In this mode , re ading its DR bit r eturns the digital value from that I/O pin.

If an OR bit is av ailab le , different input modes can be configured b y softw ar e: floating or pullup. Refer to I/O Port Implementation section for configuration.

Note: 1 Writing to the DR modifies the latch value but does not change the state of the input pin.

2 Do not use read/modify/write instructions (BSET/BRES) to modify the DR register.

External interrupt function

Depending on the device , set ting the ORx bit while in inp ut mode can configure an I/O as an input with interrupt. In this configuration, a sig nal edge or level input on the I/O gener ates an interrupt request via the corresponding interrupt vector (eix).

Falling or rising edge sensitivity is programmed independently f or each interrupt vector. The External Interrupt Control register (EICR) or the Miscellaneous register controls this sensitivity, depending on the device.

Each external interrupt vector is linked to a dedicated group of I/O port pins (see pinout description and interrupt section). If several I/O interrupt pins on the same interrupt vector are selected simultaneously, they are logically combined. For this reason if one of the interrupt pins is tied low, it may mask the others.

External interrupts are hardware interrupts. Fetching the corresponding interrupt vector automatically clears the request latch. Changing the sensitivity of a particular external interrupt clears this pending interrupt. This can be used to clear unwanted pending interrupts.

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ST7FOXF1, ST7FOXK1, ST7FOXK2 I/O ports

Spurious interrupts

When enabling/disabling an external interrupt by setting/resetting the related OR register bit, a spurious interrupt is generated if the pin level is low and its edge sensitivity includes falling/rising edge. This is due to the edge detector input which is switched to '1' when the external interrupt is disabled by the OR register.

To avoid this unwanted interrupt, a "safe" edge sensitivity (rising edge for enabling and falling edge for disabling) has to be selected before changing the OR register bit and configuring the appropriate sensitivity again.

Caution: In case a pin level change occurs during these operations (asynchronous signal input ), as

interrupts are generated according to the current sensitivity, it is advised to disable all interrupts before and to reenable them after the complete previous sequence in order to avoid an external interrupt occurring on the unwanted edge.

This corresponds to the following steps:

a) Set the interrupt mask with the SIM instruction (in cases where a pin level change

could occur) b) Select rising edge c) Enable the external interrupt through the OR register d) Select the desired sensitivity if different from rising edge e) Reset the interrupt mask with the RIM instruction (in cases where a pin level

change could occur)

2. To disable an external interrupt: a) Set the interrupt mask with the SIM instruction SIM (in cases where a pin level

change could occur) b) Select falling edge c) Disable the extern al int er rupt through the OR register d) Select rising edge e) Reset the interrupt mask with the RIM instruction (in cases where a pin level

change could occur)

9.2.2 Output modes

Setting the DDRx bit selects output mode. Writing to the DR bits applies a digital v alue to the I/O through the latch. Reading the DR bits returns the previously stored value.

If an OR bit is available, different output modes can be selected by software: push-pull or open-drain. Refer to I/O Port Implementation section for configuration.

Table 23. DR Value and output pin status

DR Push-Pull Open-Drain

0V 1V

Floating

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I/O ports ST7FOXF1, ST7FOXK1, ST7FOXK2

9.2.3 Alternate functions

Many ST7s I/Os have one or more alternate functions. These may include output signals from, or input signals to, on-chip peripherals.Table 2 an d Table 3 describe which peripheral signals can be input/output to which ports.

A signal coming from an on-chip peripheral can be output on an I/O. To do this, enable the on-chip peripheral as an output (enable bit in the peripheral’s control register). The peripheral configures the I/O as an outpu t and tak es priority ov er standard I/O programming. The I/O’s state is readable by addressing the corresponding I/O data register.

Configuring an I/O as floating enables alternate function input. It is not recommended to configure an I/O as pull-up as this will increase current consumption. Before using an I/O as an alternate input, configure it without interrupt. Otherwise spurious interrupts can occur.

Configure an I/O as input floating for an on-chip peripheral signal which can be input and output.

Caution: I/Os which can be configured as both an analog and digital alternate function need special

attention. The user must control th e peripherals so th at the signals do not ar rive at the same time on the same pin. If an external clock is used, only the clock alternate function should be employed on that I/O pin and not the other alternate function.

Figure 32. I/O port general block diagram

ALTERNATE OUTPUT

From on-chip peripheral

ALTERNATE ENABLE BIT

P-BUFFER (see table below)

PULL-UP (see table below)

DDR

DATA BUS

OR SEL

DDR SEL

DR SEL

EXTERNAL INTERRUPT REQUEST (eix)

If implemented

SENSITIVITY SELECTION

Combinational

Logic

PULL-UP CONDITION

N-BUFFER

FROM OTHER BITS

Note: Refer to the Port Configuration table for device specific information.

CMOS SCHMITT TRIGGER

PAD

DIODES (see table below)

ANALOG

INPUT

ALTERNATE

INPUT

To on-chip peripheral

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ST7FOXF1, ST7FOXK1, ST7FOXK2 I/O ports

Table 24. I/O port mode options

(1)

Configuration mode Pull-Up P-Buffer

to V

Floating with/without Interrupt Off

Input

Off

Pull-up with Interrupt On

On On

Output

Push-pull

Off

Open Drain (logic level) Off

1. Off means implemented not activated, On means implemented and activated.

Table 25. ST7FOXF1/ST7FOXK1/ST7FOXK2 I/O port configuration

Hardware configuration

DR REGISTER ACCESS

LOGIC

POLARITY

SELECTION

DATA BUS

ALTERNATE INPUT To on-chip peripheral

EXTERNAL INTERRUPT SOURCE (eix)

ANALOG INPUT

(1)

INPUT

PAD

OTHER

INTERRUPT CONDITION

FROM

PINS

COMBINATIONAL

Diodes

to V

(2)

DR REGISTER ACCESS

PAD

R/W

DATA BUS

OPEN-DRAIN OUTPUT

(2)

PAD

PUSH-PULL OUTPUT

1. When the I/O port is in input configuration and the associated alternate function is enabled as an output, reading the DR register will read the alternate function output status.

2. When the I/O port is in output configuration and the associated alternate function is enabled as an input, the alternate function reads the pin status given by the DR register content.

ENABLE OUTPUT

BIT From on-chip peripheral

DR REGISTER ACCESS

ALTERNATEAL TERNATE

R/W

DATA BUS

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I/O ports ST7FOXF1, ST7FOXK1, ST7FOXK2

9.2.4 Analog alternate function

Configure the I/O as floating input to use an ADC input. The analog multiplexer (controlled by the ADC registers) switches the analog voltage present on the selected pin to the common analog rail, connected to the ADC input.

Analog Recommendations Do not change the voltage le v el or loading on any I /O while conv ersion is in progr ess. Do not

have clocking pins located close to a selected analog pin.

Caution: The analog input voltage level must be within the limits stated in the absolute maximum

ratings.

9.3 I/O port implementation

The hardware implementati on on each I /O port depends on the setti ngs in the DDR and O R registers and specific I/O port features such as ADC input or open drain.

Switching these I/O ports from one state to another should be done in a sequence that prevents unwanted side effects. Recommended safe transitions are illustrated in Figure 33. Other transitions are potentially risky and should be avoided, since they may present unwanted side-effects such as spurious interrupt generation.

Figure 33. Interrupt I/O port state transitions

INPUT

floating/pull-up

interrupt

9.4 Unused I/O pins

Unused I/O pins must be connected to fixed voltage levels. Refer to Section 12.9: I/O port

pin characteristics.

9.5 Low power modes

Table 26. Effect of low power modes on I/O ports

Mode Description

Wait

No effect on I/O ports. External interrupts cause the device to exit from Wait

INPUT

floating

(reset state)

OUTPUT

open-drain

mode.

OUTPUT push-pull

= DDR, OR

Halt

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No effect on I/O ports. External interrupts cause the device to exit from Halt

mode.

ST7FOXF1, ST7FOXK1, ST7FOXK2 I/O ports

9.6 Interrupts

The external interrupt event generates an interrupt if the corresponding configurat ion is selected with DDR and OR registers and if the I bit in the CC register is cleared (RIM instruction).

Table 27. Description of interrupt events

Interrupt Event Event flag

External interrupt on selecte d

external event

Enable

Control bit

DDRx

ORx

See application notes AN1045 software implementation of I software LCD driver

9.7 Device-specific I/O port configuration

The I/O port register configurations are summarized in Section 9.7.1: Standard ports and

Section 9.7.2: Other ports .

9.7.1 Standard ports

Table 28. PA5:0, PB7:0, PC7:4 and PC2:0 pins

Mode DDR OR

floating input 0 0

pull-up interrupt input 0 1

Exit from

Wait

Yes Yes

C bus master, and AN1048 -

Exit from

Halt

9.7.2 Other ports

Table 29. PA7:6 pins

open drain output 1 0

push-pull output 1 1

Mode DDR OR

floating input 0 0

interrupt input 0 1

open drain output 1 0

push-pull output 1 1

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I/O ports ST7FOXF1, ST7FOXK1, ST7FOXK2

Table 30. PC3 pin

Mode DDR OR

floating input 0 0

pull-up input 0 1

open drain output 1 0

push-pull output 1 1

Table 31. Port configuration

Input Output

Port Pin nam e

OR = 0 OR = 1 OR = 0 OR = 1

Port A

PA5:0 floating pull-up interrupt open drain push-pull PA7:6 floating interrupt true open drain

Port B PB7:0 floating pull-up interrupt open drain push-pull

Port C

PC7:4,

PC2:0

floating pull-up interrupt open drain push-pull

PC3 floating pull-up open drain push-pull

Table 32. I/O port register mapping and reset va lues

Address

(Hex.)

0000h

0001h

0002h

0003h

0004h

label

PADR

Reset Value

PADDR

Reset Value

PAOR

Reset Value

PBDR

Reset Value

PBDDR

Reset Value

76543210

MSB

0000000

MSB

0000000

MSB

0000000

MSB

0000000

MSB

0000000

LSB

0005h

0006h

0007h

0008h

PBOR

Reset Value

PCDR

Reset Value

PCDDR

Reset Value

PCOR

Reset Value

MSB

0000000

MSB

0000000

MSB

0000000

MSB

0000100

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LSB

ST7FOXF1, ST7FOXK1, ST7FOXK2 On-chip peripherals

10 On-chip peripherals

10.1 Watchdog timer (WDG)

10.1.1 Introduction

The Watchdog time r is used to detect the occurrence of a software fault, usually generated by external interference or by unforeseen logical conditions, which causes the application program to abandon its normal sequence . The W atchdog circuit g enerates an MCU reset on expiry of a programmed time period, unless the program refreshes the counter’s contents before the T6 bit becomes cleared.

10.1.2 Main features

● Programmable free-running downcounter (64 increments of 16000 CPU cycles)

● Programmable reset

● Reset (if watchdog activated) when the T6 bit reaches zero

● Optional reset on HALT instruction (configurable by option byte)

● Hardware Watchdog selectable by option byte

10.1.3 Functional description

The counter value stored in the CR register (bits T[6:0]), is decremented every 16000 machine cycles, and the length of the timeout period can be programmed by the user in 64 increments.

If the watchdog is activated (the WDGA bit is set) and when the 7-bit timer (bits T[6:0]) rolls over from 40h to 3Fh (T6 becomes cleared), it initiates a reset cycle pulling low the RESET pin for typically 30µs.

Figure 34. Watchdog block diagram

RESET

WDGA

CPU

WATCHDOG CONTROL REGISTER (CR) T5

7-BIT DOWNCOUNTER

CLOCK DIVIDER

÷16000

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On-chip peripherals ST7FOXF1, ST7FOXK1, ST7FOXK2

The application program must write in the CR register at regular intervals during normal operation to prevent an MCU reset. This downcounter is free-running: it counts do wn e v en if the watchdog is disabled. The value to be stored in the CR register must be between FFh and C0h (see Table 33: Watchdog timing):

● The WDGA bit is set (watchdog enabled)

● The T6 bit is set to prevent generating an immediate reset

● The T[5:0] bits contain the number of increment s which represents the time delay

before the watchdog produces a reset.

Following a reset , the w atchdog is disab l ed. Once activated it cannot be disabled, except b y a reset.

The T6 bit can be used to generate a software reset (the WDGA bit is set and the T6 bit is cleared).

If the watchdog is activated, the HALT instruction will generate a Reset.

Table 33. Watchdog timing

(1)(2)

CPU

= 8 MHz

WDG

counter code

C0h 1 2 FFh 127 128

1. The timing variation shown in Table 33 is due to the unknown status of the prescaler when writing to the CR register.

2. The number of CPU clock cycles applied during the Reset phase (256 or 4096) must be taken into account in addition to these timings.

10.1.4 Hardware watchdog option

If Hardware Watchdog is selected by option byte, the watchdog is always active and the WDGA bit in the CR is not used.

Refer to the option byte description in Section 13 on page 211.

Using Halt mode with the WDG (WDGHALT option)

If Halt mode with Watchdog is enabled by option byte (No watchdog reset on HALT instruction), it is recommended before executing the HALT instruction to refresh the WDG counter, to av oid an unexpected WDG reset immediately after waking up the microcontroller. Same behavior in active-halt mode.

10.1.5 Interrupts

min

[ms]

max [ms]

None.

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ST7FOXF1, ST7FOXK1, ST7FOXK2 On-chip peripherals

10.1.6 Register description

Control register (WDGCR)

Reset value: 0111 1111 (7Fh)

7 0

WDGA T6 T5 T4 T3 T2 T1 T0

Read /Write

Bit 7 = WDGA Activation bit

This bit is set by software a nd only cleared b y hardware af ter a reset. When WDGA = 1, the watchdog can generate a reset.

0: Watchdog disabled 1: Watchdog enabled

Note: This bit is not used if the hardware watchdog option is enabled by option byte.

Bits 6:0 = T[6:0] 7-bit timer (MSB to LSB)

These bits contain the decremented value. A reset is produced when it rolls over from 40h to 3Fh (T6 becomes cleared).

Table 34. Watchdog timer register mapping and reset values

Address

(Hex.)

0033h

label

WDGCR

Reset

Value

76543210

WDGA0T6

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On-chip peripherals ST7FOXF1, ST7FOXK1, ST7FOXK2

10.2 Dual 12-bit autoreload timer

10.2.1 Introduction

The 12-bit Autoreload timer can be used f or ge neral-purpose timing fun ctions . It is based on one or two free-running 12-bit upcounters with an Input Capture register and four PWM output channels. There are 7 external pins:

● Four PWM outputs

● ATIC/LTIC pins for the Input Capture function

● BREAK pins for forcing a break condition on the PWM outputs

10.2.2 Main features

● Single Timer or Dual Timer mode with two 12-bit up counte rs (CNTR1/CNTR2 ) and tw o

12-bit autoreload registers (ATR1/ATR2)

● Maskable overflow interrupts

● PWM mode

– Generation of four independent PWMx signals – Dead time generation for Half bridge driving mode with programmable dead time – Frequency 2 kHz - 4 MHz (@ 8 MHz f – Programmable duty-cycle s – Polarity control – Programmable output modes

● Output Compare mode

● Input Capture mode

– 12-bit Input Capture register (ATICR) – Triggered by rising and falling edges – Maskable IC interrupt – Long range Input Capture

● Internal/External Break control

● Flexible Cloc k control

● One Pulse mode on PWM2/3

● Force update

CPU

)

82/226

ST7FOXF1, ST7FOXK1, ST7FOXK2 On-chip peripherals

Figure 35. Single timer mode (ENCNTR2=0)

ATIC

Edge Detection Circuit

12-Bit Autoreload register 1

12-Bit Upcounter 1

Clock

Control

OVF1 interrupt

OFF

CPU

1 ms from

Lite timer

12-bit Input Capture

PWM0 Duty Cycle Generator PWM1 Duty Cycle Generator

PWM2 Duty Cycle Generator

PWM3 Duty Cycle Generator

Figure 36. Dual timer mode (ENCNTR2=1)

Output Compare

CMP Interrupt

Dead Time Generator

DTE bit

OE0

OE1

OE2

OE3

Break Function

BPEN bit

PWM0

PWM1

PWM2

PWM3

ATIC

LTIC

Edge Detection Circuit

12-Bit Autoreload register 1

12-Bit Upcounter 1

12-Bit Upcounter 2

12-Bit Autoreload register 2

Clock

Control

OFF f

CPU

1 ms from

Lite timer

12-bit Input Capture

PWM0 Duty Cycle Generator PWM1 Duty Cycle Generator

OVF1 interrupt OVF2 interrupt

PWM2 Duty Cycle Generator PWM3 Duty Cycle Generator

Output Compare

CMP Interrupt

Dead Time

Generator

DTE bit

One Pulse

mode

OP_EN bit

CMP Interrupt

OE0

OE1

OE2 OE3

Break Function

BPEN bit

PWM0

PWM1

PWM2 PWM3

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On-chip peripherals ST7FOXF1, ST7FOXK1, ST7FOXK2

10.2.3 Functional description

PWM mode

This mode allows up to four Pulse Width Modulated signals to be generated on the PWMx output pins.

● PWM frequency

The four PWM signals can have the same frequency (f frequencies. This is selected by the ENCNTR2 bit which enables Single Timer or Dual Timer mode (see Figure 35 and Figure 36). The frequency is controlled by the counter period and the ATR register value. In Dual Timer mode, PWM2 and PWM3 can be generated with a different frequency controlled by CNTR2 and ATR2.

) or can have two different

PWM

PWMfCOUNTER

Following the above formula, if f

COUNTER

4096 ATR–()⁄=

equals 4 MHz, the maximum value of f 2 MHz (ATR register value = 4094), and the minimum value is 1 kHz (ATR register value = 0).

The maximum value of ATR is 4094 because it must be lower than the DC4R value which must be 4095 in this case.

● Duty cycle

The duty cycle is selected by programming the DCRx registers. These are preload registers. The DCRx values are transferred in Active duty cycle registers after an overflow event if the corresponding transfer bit (TRANx bit) is set.

The TRAN1 bit controls the PWMx outputs driven by counter 1 and the TRAN2 bit controls the PWMx outputs driven by counter 2.

PWM generation and output compare are done by comparing these active DCRx values with the counter.

The maximum availab l e resolution for the PWMx duty cycle is:

Resolution 1 4096 ATR–()⁄=

where ATR is equal to 0. With this maximum resolution, 0% and 100% duty cycle can be obtained by changing the polarity.

At reset, the counter starts counting from 0. When a upcounter overflow occurs (OVF event), the preloaded Duty cycle values are

transferred to the active Duty Cycle registers and the PWMx signals are set to a high level. Whe n the upcounter matc hes the activ e DCRx v alue the PWMx signals are set to a low lev el. To obtain a signal on a PWMx pin, the contents of the cor respond ing active DCRx register must be greater than the contents of the ATR register.

The maximum value of ATR is 4094 because it must be lower than the DCR value which must be 4095 in this case.

● Polarity inversion

The polarity bits can be used to invert any of the four output signals. The inversion is synchronized with the counter overflow if the corresponding transfer bit in the ATCSR2 register is set (reset value). See Figure 37.

PWM

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ST7FOXF1, ST7FOXK1, ST7FOXK2 On-chip peripherals

Figure 37. PWM polarity inversion

inverter

PWMx

PWMxCSR register

OPx

PWMx PIN

TRANx

DFF

ATCSR2 register

counter

overflow

The Data Flip Flop (DFF) applies the polarity inversion when triggered by the counter overflow input.

● Output control

The PWMx output signals can be enabled or disabled using the OEx bits in the PWMCR register.

Figure 38. PWM function

4095

DUTY CYCLE

(DCRx)

AUTO-RELOAD

COUNTER

(ATR)

000

WITH OE=1 AND OPx=0

WITH OE=1 AND OPx=1

PWMx OUTPUT

85/226

On-chip peripherals ST7FOXF1, ST7FOXK1, ST7FOXK2

Figure 39. PWM signal from 0% to 100% duty cycle

COUNTER

ATR= FFDh

PWMx OUTPUTtWITH MOD00=1

AND OPx=0

PWMx OUTPUT

WITH MOD00=1

AND OPx=1

COUNTER

DCRx=000h

DCRx=FFDh

DCRx=FFEh

DCRx=000h

FFDh FFEh FFFh FFDh FFEh FFFh FFDh FFEh

Dead time generation

A dead time can be inserted between PWM0 and PWM1 using the DTGR register. This is required for half-bridge driving where PWM signals must not be overlapped. The nonoverlapping PWM0/PWM1 signals are generated through a programmable dead time by setting the DTE bit.

Dead time DT 6:0[]Tcounter1×=

DTGR[7:0] is buffered inside so as to avoid deforming the current PWM cycle. The DTGR effect will take place only after an ov erflow.

Note: 1 Dead time is generated only when DTE=1 and DT[6:0]

PWM output signals will be at their reset state.

2 Half Bridge driving is possible only if polarities of PWM0 and PWM1 are not inverted, i.e. if

OP0 and OP1 are not set. If polarity is inverted, overlapping PWM0/PWM1 signals will be generated.

3 Dead Time generation does not work at 1msec timebase.

≠ 0.

If DTE is set and DT[6:0]=0,

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ST7FOXF1, ST7FOXK1, ST7FOXK2 On-chip peripherals

Figure 40. Dead time generation

counter1

CK_CNTR1

CNTR1

PWM 0

if DTE = 0

PWM 0

if DTE = 1

PWM 1

counter = DCR0

PWM 1

DCR0+1 ATR1DCR0

counter = DCR1

OVF

Tdt = DT[6:0] x T

counter1

In the above example, when the DTE bit is set:

● PWM goes low at DCR0 match and goes high at ATR1+Tdt

● PWM1 goes high at DCR0+Tdt and goes low at ATR match.

With this programmable delay (Tdt), the PWM0 and PWM1 signals which are generated are not overlapped.

Break function

The break function can be used to pe rf orm an emergency sh utdown of the app lication being driven by the PWM signals.

The break function is activated by the external BREAK pin. This can be selected by using the BRSEL bit in BREAKCR register. In order to use the break function it must be pre viously enabled by software setting the BPEN bit in the BREAKCR register.

The Break active level can be programmed by the BREDGE bit in the BREAKCR register. When an active level is detected on the BREAK pin, the BA bit is set and the break function is activated. In this case, the PWM signals are forced to BREAK value if respective OEx bit is set in PWMCR register.

Software can set the BA bit to activate the break function without using the BREAK pin. The BREN1 and BREN2 bits in the BREAKEN register are used to enable the break activation on the 2 counters respective ly. In Dual Timer mode, the break for PWM2 and PWM3 is enabled by the BREN2 bi t. In Single Timer mode, the BREN1 bit enables the break for all PWM channels.

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On-chip peripherals ST7FOXF1, ST7FOXK1, ST7FOXK2

When a break function is activated (BA bit =1 and BREN1/BREN2 =1):

● The break pattern (PWM[3:0] bits in the BREAKCR) is forced directly on the PWMx

output pins if respective OEx is set. (after the inverter).

● The 12-bit PWM counter CNTR1 is put to its reset value, i.e. 00h (if BREN1 = 1).

● The 12-bit PWM counter CNTR2 is put to its reset value,i.e. 00h (if BREN2 = 1).

● ATR1, ATR2, Preload and Active DCRx are put to their reset values.

● Counters stop counting.

When the break function is deactiv ated after applying the break (BA bit goes from 1 to 0 by software), Timer takes the control of PWM ports.

Note: The break function of the ST7FOXK2 is different from the break function of the

ST7FOXF1 /ST7FOXK1. Refer to Figure 41: ST7FOXF1/ST7FOXK1 Block diagram of break

function on page 88 and Figure 42: ST7FOXK2 Block diagram of break function on page 89

Figure 41. ST7FOXF1/ST7FOXK1 Block diagram of break function

BREDGE

BREAK pin

BRSEL

Level Selection

BREAKCR register

BREAKEN register

BREN2

BREN1

BREAKCR register

PWM0/1 Break Enable PWM2/3 Break Enable

ENCNTR2 bit

PWM0 PWM1 PWM2 PWM3

PWM0PWM1PWM2PWM3BPENBA

(Inverters)

OEx

PWM0

PWM1

PWM2

PWM3

88/226

ST7FOXF1, ST7FOXK1, ST7FOXK2 On-chip peripherals

Figure 42. ST7FOXK2 Block diagram of break function

BREAK1 pin

Level Selection

Comparator1

BREAKCR2 register

BR2SEL

BREAK2 pin

Comparator2

BR2EDGE

BR1SEL

BR1EDGE

0 1

Level Selection

BREAKCR1 register

PWM0PWM1PWM2PWM3BP1ENBA1

BREN1 bit

0 1

BREN2 bit

SWBR1SWBR2--BP2ENBA2

PWM0

PWM1 PWM2 PWM3

PWM0/1 Break Enable

ENCNTR2 bit

(Inverters)

PWM2/3 Break Enable

OEx

PWM0

PWM1

PWM2

PWM3

Output compare mode

To use this function, load a 12-bit value in the Preload DCRxH and DCRxL registers. When the 12-bit upcounter CNTR1 reaches the value stored in the Active DCRxH and

DCRxL registers, the CMPFx bit in the PWMxCSR register is set and an interrupt request is generated if the CMPIE bit is set.

In Single Timer mode the output compare function is performed only on CNTR1. The difference betw een bot h the modes is that , in Single Ti mer mode , CNTR1 can be co mpared with any of the four DCR registers, and in Dual Timer mode, CNTR1 is compared with DCR0 or DCR1 and CNTR2 is compared with DCR2 or DCR3.

Note: 1 The output compare function is only available for DCRx values other than 0 (reset value).

2 Duty cycle registers are buffered internally. The CPU writes in Preload Duty Cycle registers

and these values are transferred in Active Duty Cycle r egi ster s af ter an overflow event if the corresponding transfer bit (TRANx bit) is set. Output compare is done by comparing these active DCRx values with the counters.

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On-chip peripherals ST7FOXF1, ST7FOXK1, ST7FOXK2

Figure 43. Block diagram of output compare mode (single timer)

DCRx

PRELOAD DUTY CYCLE REG0/1/2/3

TRAN1 (ATCSR2)

(ATCSR)

OVF

ACTIVE DUTY CYCLE REGx

CNTR1

COUNTER 1

CMP

OUTPUT COMPARE CIRCUIT

REQUESTINTERRUPT

CMPFx (PWMxCSR)

(ATCSR)CMPIE

Input capture mode

The 12-bit ATICR register is used to latch the value of the 12-bit free running upcounter CNTR1 after a rising or falling edge is detected on the ATIC pin. When an Input Capture occurs, the ICF bit is set and the ATICR register contains the value of the free running upcounter. An IC interrupt is generated if the ICIE bit is set. The ICF bit is reset by reading the ATICRH/ATICRL register when the ICF bit is set. The ATICR is a read only register and always contains the free running upcounter value which corresponds to the most recent Input Capture. Any further Input Capture is inhibite d while the ICF bit is set.

Figure 44. Block diagram of input capture mode

ATIC

LTIMER

(1 ms

timebase

@ 8MHz)

CPU

OFF

ATICR

ATCSR

12-BIT INPUT CAPTURE REGISTER

IC INTERRUPT

REQUEST

CK0CK1ICIEICF

12-BIT UPCOUNTER1

CNTR1

12-BIT AUTORELOAD REGISTER

ATR1

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ST7FOXF1, ST7FOXK1, ST7FOXK2 On-chip peripherals

Figure 45. Input capture timing diagram

COUNTER

COUNTER1

ATIC PIN

ICF FLAG

01h

02h 03h 04h 05h 06h 07h

INTERRUPT

xxh

04h

08h 09h 0Ah

ATICR READ

09h

INTERRUPT

Long range input capture

Pulses that last more than 8 µs can be measured with an accuracy of 4 µs if f MHz in the following conditions:

● The 12-bit AT4 timer is clocked by the Lite timer (R TC pulse: CK[1:0] = 01 in the ATCSR

● The ICS bit in the ATCSR2 register is set so that the LTIC pin is used to trigger the AT4

timer capture.

● The signal to be captured is connected to LTIC pin

● Input Capture registers LTICR, ATICRH and ATICRL are read

This configuration allows to cascade the Lite timer and the 12- bit AT4 timer to get a 20-bit Input Capture value. Refer to Figure 46.

equals 8

OSC

Figure 46. Long range input capture block diagram

LTICR

8-bit Input Capture register

LTIC

ATIC

ICS

OSC/32

LTI MER

cpu

OFF

1 0

8-bit Timebase Counter1

LITE TIMER

12-bit ARTIMER

ATR1

12-bit AutoReload register

CNTR1

12-bit Upcounter1

ATICR

12-bit Input Capture register

8 LSB bits

20 cascaded bits

12 MSB bits

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On-chip peripherals ST7FOXF1, ST7FOXK1, ST7FOXK2

Since the Input Capture flags (ICF) for both timers (AT4 timer and LT timer) are set when signal transition occurs, software must mask one interrupt by clearing the corresponding ICIE bit before setting the ICS bit.

If the ICS bit changes (from 0 to 1 or from 1 to 0), a spur io us transition mig ht occu r on the Input Capture signal because of di fferent values on LTIC and ATIC. To avoid this situation, it is recommended to do as follows:

1. First, reset both ICIE bits.

2. Then set the ICS bit.

3. Reset both ICF bits.

4. And then set the ICIE bit of desired interrupt. Computing a pulse length in long Input Capture mode is not str aightforward since both

timers are used. The following steps are required:

1. At the first Input Capture on the rising edge of the pulse, we assume that values in the registers are the following:

– LTICR = LT1 – ATICRH = ATH1 – ATICRL = ATL1 – Hence ATICR1 [11:0] = ATH1 & ATL1. Refer to Figure 47 on page 93.

2. At the second Input Capture on the falling edge of the pulse, w e assume that the values in the registers are as follows:

– LTICR = LT2 – ATICRH = ATH2 – ATICRL = ATL2 – Hence ATICR2 [11:0] = ATH2 & ATL2.

Now pulse width P between first capture and second capture is given by:

P decimal F9 LT1– LT2 1++()× 0.004ms×

decimal FFF N×()N ATICR2 ATICR1– 1–++()1ms×+

where N is the number of overflows of 12-bit CNTR1.

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ST7FOXF1, ST7FOXK1, ST7FOXK2 On-chip peripherals

Figure 47. Long range input capture timing diagram

OSC/32

TB Counter1

CNTR1

LTIC

LTICR

ATICRH

ATICRL

F9h 00h LT1 F9h 00h LT2

_ _ _

00h

ATH1 & ATL1

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _

_ _ _

LT1

ATH1

ATL1

ATICR = ATICRH[3:0] & ATICRL[7:0]

ATH2 & ATL2

LT2

ATH2

ATL2

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On-chip peripherals ST7FOXF1, ST7FOXK1, ST7FOXK2

One pulse mode

One Pulse mode can be used to control PWM2/3 signal with an external LTIC pin. This mode is available only in Dual Timer mode i.e. only for CNTR2, when the OP_EN bit in PWM3CSR register is set.

One Pulse mode is activated by the external LTIC input. The active edge of the LTIC pin is selected by the OPEDGE bit in the PWM3CSR register.

After getting the active edge of the LTIC pin, CNTR2 is reset (000h) and PWM3 is set to high. CNTR2 starts counting from 000h, when it reaches the activ e DCR3 v alue then PWM3 goes low. Till this time, any further transitions on the LTIC signal will have no effect. If there are LTIC transitions after CNTR2 reaches DCR3 value, CNTR2 is reset again and PWM3 goes high.

If there is no LTIC active edge, CNTR2 counts until it reaches the ATR2 value, then it is reset again and PWM3 is set to high. The counter again starts counting from 000h, when it reaches the active DCR3 v alue PWM3 goes lo w, the counter counts until it reaches ATR2, it resets and PWM3 is set to high and so on.

The same operation applies for PWM2, but in this case the comparison is done on DCR2. OP_EN and OPEDGE bits take effect on the fly and are not synchronized with Counter 2 overflo w. The output bit OP2/3 can be used to inverse the polarity of PWM2/3 in one-pulse mode. The update of these bits (OP2/3) is synchronized with th e co un te r 2 overflow, they will be updated if the TRAN2 bit is set.

The time taken from activation of LTIC input and CNTR2 reset is between 1 and 2 t cycles, that is, 125 ns to 250 ns (with 8-MHz f

CPU

Lite timer Input Capture interrupt should be disabled while 12-bit ARtimer is in One Pulse mode. This is to avoid spurious interrupts.

The priority of the various conditions for PWM3 is the following: Break > one-pulse mode with active LTIC edge > Forced overflow by s/w > one-pulse mode without act ive LTIC edge > normal PWM operation.

It is possible to update DCR2/3 and OP2/3 at the counter 2 reset, the update is synchronized with the counter reset. This is managed by the overflow interrupt which is generated if counter is reset either due to ATR match or active pulse at LTIC pin. DCR2/3 and OP2/3 update in one-pulse mode is performed dynamically using a software force update. DCR3 update in this mode is not synchronized with any event. That may lead to a longer next PWM3 cycle duration than expected just after the change.

In One Pulse mode ATR2 value must be greater than DCR2/3 value for PWM2/3. (opposite to normal PWM mode).

If there is an active edge on the LTIC pin after the counter has reset due to an A TR2 match, then the timer again gets reset and appears as modified Duty cycle depending on whether the new DCR value is less than or more than the previous value.

The TRAN2 bit should be set along with the FORCE2 bit with the same instruction after a write to the DCR register.

ATR2 value should be changed after an overflow in one pulse mode t o avoid any irregular PWM cycle.

When exiting from one pulse mode, the OP_EN bit in the PWM3CSR register should be reset first and then the ENCNTR2 bit (if counter 2 must be stopped).

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ST7FOXF1, ST7FOXK1, ST7FOXK2 On-chip peripherals

How to enter one pulse mode

The steps required to enter One Pulse mode are the following:

1. Load ATR2H/ATR2L with required value.

2. Load DCR3H/DCR3 L for PWM3. ATR2 value must be greater than DCR3.

3. Set OP3 in PWM3CSR if polarity change is required.

4. Select CNTR2 by setting ENCNTR2 bit in ATCSR2.

5. Set TRAN2 bit in ATCSR2 to enable transfer.

6. "Wait for Overflow" by checking the OVF2 flag in AT CSR2 .

7. Select counter clock using CK<1:0> bits in ATCSR.

8. Set OP_EN bit in PWM3CSR to enable one-pulse mode.

9. Enable PWM3 by OE3 bit of PWMCR.

The "Wait for Overflow" in step 6 can be replaced by a forced update. Follow the same procedure for PWM2 with the bits corresponding to PWM2.

Note: When break is applied in one-pulse mode, CNTR2, DCR2/3 & ATR2 registers are reset. So,

these registers have to be initialized again when break is removed.

Figure 48. Block diagram of one pulse mode

LTIC pin

PWM3CSR register

Edge Selection

OPEDGE

OP_EN

12-bit Upcounter 2

12-bit AutoReload register 2

12-bit Active DCR2/3

OP2/3

Figure 49. One pulse mode and PWM timing diagram

OP_EN=1

OP_EN=0

counter2

CNTR2

LTI C

PWM2/3

counter2

CNTR2

LTIC

PWM2/3

000 DCR2/3

OVF

ATR2 DCR2/3

000 DCR2/3 A TR2

OVF

ATR2 DCR2/3

PWM

Generation

OVF

ATR 2

PWM2/3

000

Note 1: When OP_EN=0, LTIC edges are not taken into account as the timer runs in PWM mode.

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On-chip peripherals ST7FOXF1, ST7FOXK1, ST7FOXK2

Figure 50. Dynamic DCR2/3 update in one pulse mode

OP_EN=1

counter2

CNTR2

LTI C

FORCE2

TRAN2

DCR2/3

PWM2/3

(DCR2/3)

000

FFF

old

000

(DCR3)

old

extra PWM3 period due to DCR3 update dynamically in one-pulse mode.

(DCR2/3)

(DCR3)

new

ATR2 000

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ST7FOXF1, ST7FOXK1, ST7FOXK2 On-chip peripherals

Force update

In order not to wait for the counterx overflow to load the value into active DCRx registers, a programmable counter which when set, make the counters start with the overflow value, i.e. FFFh. After overflow, the counters start co un tin g fr om the i r re sp ect ive auto reload regist er values.

These bits are FORCE1 and FORCE2 in the ATCSR2 register. FORCE1 is used to force an overflow on Counter 1 and, FORCE2 is used for Counter 2. These bits are set by software and reset by hardware after the respective counter overflow event has occurred.

This feature can be used at any time. All related features such as PWM generation, Output Compare, Input Capture, One-pulse (refer to Figure 50: Dynamic DCR2/3 update in one

pulse mode) etc. can be used this way.

Figure 51. Force overflow timing diagram

CNTRx

FORCEx

overflow is provided. For both counters, a separate bit is provided

FORCE2

CNTRx

FORCE1

E03

ATCSR2 register

10.2.4 Low power modes

Table 35. Effect of low power modes on autoreload timer

Mode Description

Wait No effect on AT timer

Halt AT timer halted.

10.2.5 Interrupts

Table 36. Description of interrupt events

Interrupt Event

Overflow Event OVF1 OVIE1 Yes No Yes

AT4 IC Event ICF ICIE Yes No No

Overflow Event2 OVF2 OVIE2 Yes No No

E04

Event

Flag

FFF

ARRx

Enable

Control bit

Exit from

Wait

Exit from

Halt

Exit from

Active-Halt

Note: The AT4 IC is connected to an interrupt vector. The OVF event is mapped on a separate

vector (see Interrupts chapter). They generate an interrupt if the enable bit is set in the ATCSR register and the interrupt mask in the CC register is reset (RIM instruc tio n) .

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On-chip peripherals ST7FOXF1, ST7FOXK1, ST7FOXK2

10.2.6 Register description

Timer control status register (ATCSR)

Reset value: 0x00 0000 (x0h)

7 0 0 ICF ICIE CK1 CK0 OVF1 OVFIE1 CMPIE

Read / Write

Bit 7 = Reserved Bit 6 = ICF Input Capture flag

This Bit is set by hardware and cleared by software by reading the ATICR register (a read access to ATICRH or AT ICRL clears this flag). Writing to this bit does not change the bit value.

0: No input capture 1: An input capture has occurred

Bit 5 = ICIE IC Interrupt Enable

bit

This bit is set and cleared by software. 0: Input Capture Interrupt Disabled

1: Input Capture Interrupt Enabled

Bits 4:3 = CK[1:0] Counter Clock Selection

bits

These bits are set and cleared by software and cleared by hardware after a re se t. th ey select the clock frequency of the counter.

Table 37. Counter clock selection

Counter clock selection CK1 CK0

OFF 0 0

selection forbidden 1 1

(1 ms timebase @ 8 MHz) 0 1

LTIMER

CPU

Bit 2 = OVF1 Overflow flag

This bit is set by hardware and cleared by software by reading the ATCSR register. It indicates the transition of the Counter1 CNTR1 from FFFh to ATR1 value.

0: No Counter Overflow Occurred 1: Counter Overflow Occurred

Bit 1 = OVFIE1 Overflow Interrupt Enable

This bit is read/write by softwar e and cleared by hardware after a reset. 0: Overflow Interrupt Disabled. 1: Overflow Interrupt Enabled.

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bit

ST7FOXF1, ST7FOXK1, ST7FOXK2 On-chip peripherals

Bit 0 = CMPIE Compare Interrupt Enable

bit

This bit is read/write by software and cleared by hardware after a reset. it can be used to mask the interrupt generated when any of the cmpfx bit is set.

0: Output Compare Interrupt Disabled. 1: Output Compare Interrupt Enabled.

Counter register 1 High (CNTR1H)

Reset value: 0000 0000 (00h)

15 8

0000

CNTR1_11CNTR1_

Read only

CNTR1_9 CNTR1_8

Counter register 1 Low (CNTR1L)

Reset value: 0000 0000 (00h)

7 0

CNTR1_7 CNTR1_6 CNTR1_5 CNTR1_4 CNTR1_3 CNTR1_2 CNTR1_1 CNTR1_0

Read only

Bits 15:12 = Reserved Bits 11:0 = CNTR1[11:0] Counter value

This 12-bit register is read by software and cleared by hardware after a reset. The counter CNTR1 increments continuously as soon as a counter clock is selected. To obtain the 12-bit value , softw are should re ad the coun ter v alue in two consecut iv e read operations. As there is no latch, it is recommended to read LSB first. In this case, CNTR1H can be incremented between the two read operations and to have an accurate result when f

timer=fCPU

, special care must be taken when CNTR1L values

close to FFh are read. When a counter overflow occurs, the counter restarts from the value specified in the

ATR1 register.

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On-chip peripherals ST7FOXF1, ST7FOXK1, ST7FOXK2

Autoreload register (ATR1H)

Reset value: 0000 0000 (00h)

15 8

0 0 0 0 ATR11 ATR10 ATR9 ATR8

Read/write

Autoreload register (ATR1L)

Reset value: 0000 0000 (00h)

7 0

ATR7 ATR6 ATR5 ATR4 ATR3 ATR2 ATR1 ATR0

Read/write

Bits 11:0 = ATR1[11:0] Autoreload register 1: This is a 12-bit register which is written by software. Th e ATR1 register value is automatically loaded into the upcounter CNTR1 when an overflow occurs. The register value is used to set the PWM frequency.

PWM output control register (PWMCR)

Reset value: 0000 0000 (00h)

7 0 0OE30OE20OE10OE0

Read/write

Bits 7:0 = OE[3:0] PWMx output enable bits

These bits are set and cleared by software and cleared by hardware after a reset. 0: PWM mode disabled. PWMx Output Alternate function disabled (I/O pin free for

general purpose I/O) 1: PWM mode enabled

PWMX control status register (PWMxCSR)

Reset value: 0000 0000 (00h)

7 0 0000OP_ENOPEDGEOPxCMPFx

Read/write

Bits 7:4= Reserved, must be kept cleared. Bit 3 = OP_EN One Pulse Mode Enable

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bit

ST ST7FOXF1, ST7FOXK1, ST7FOXK2 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

1 Description

Table 1. Device summary

Figure 1. General block diagram

2 Pin description

Figure 2. 32-pin SDIP package pinout

Figure 3. 32-pin LQFP 7x7 package pinout

Table 2. Device pin description (32-pin packages)

Figure 4. 20-pin SO and DIP package pinout

Table 3. Device pin description (20-pin package)

3 Register and memory mapping

Figure 5. ST7FOXF1/ST7FOXK1/ST7FOXK2 memory map

Table 4. Hardware register map

4 Flash programmable memory

4.1 Introduction

4.2 Main features

4.3 Programming modes

4.3.1 In-Circuit Programming (ICP)

4.3.2 In Application Programming (IAP)

4.4 ICC interface

Figure 6. Typical ICC Interface

4.5 Memory protection

4.5.1 Read-out protection

4.5.2 Flash write/erase protection

4.6 Related documentation

4.7 Description of Flash Control/Status register (FCSR)

Table 5. Flash register mapping and reset values

5 Central processing unit

5.1 Introduction

5.2 Main features

5.3 CPU registers

Figure 7. CPU registers

5.3.1 Accumulator (A)

5.3.2 Index registers (X and Y)

5.3.3 Pr ogram Counter (PC)

5.3.4 Condition Code register (CC)

Table 6. Interrupt software priority truth table

5.3.5 Stack Pointer (SP)

Figure 8. Stack manipulation example

6 Supply, reset and clock management

6.1 RC oscillator adjustment

6.1.1 Internal RC oscillator

Table 7. Predefined RC oscillator calibration values

6.1.2 Customized RC calibration

Figure 9. RCCRH_USER and RCCRL_USER programming flowchart

Figure 10. RC user calibration programming cycle

6.1.3 Auto wakeup RC oscillator

Figure 11. Clock switching

Figure 12. Clock management block diagram

6.2 Multi-oscillator (MO)

6.2.1 External clock source

6.2.2 Crystal/ceramic oscillators

6.2.3 Internal RC oscillator

Table 8. ST7 clock sources

6.3 Reset sequence manager (RSM)

6.3.1 Introduction

Table 9. CPU clock delay during Reset sequence

Figure 13. Reset sequence phases

6.3.2 Asynchronous external RESET pin

Figure 14. Reset block diagram

6.3.3 External power-on reset

6.3.4 Internal Low Voltage Detector (LVD) reset

6.3.5 Internal watchdog reset

Figure 15. Reset sequences

6.4 System Integrity management (SI)

6.4.1 Lo w Voltage Detector (LVD)

Figure 16. Low voltage detector vs reset

Figure 17. Reset and supply management block diagram

6.5 Register description

6.5.1 RC calibration control/status register (RCC_CSR)

6.5.2 Main Clock Control/Status Register (MCCSR)

6.5.3 RC Control Register High (RCCRH)

6.5.4 RC Control Register Low (RCCRL)

Table 10. Reset source selection

6.5.5 Prescaler register (PSCR)

Table 11. Internal RC prescaler selection bits

6.5.6 Clock controller control/status register (CKCNTCSR)