ST ST7DALIF2 User Manual
8-bit MCU family with single voltage Flash memory,
SO20
300”
Features
■ Memories
– 8 Kbytes single voltage Flash Program
memory with readout protection, In-Circuit
Programming and In-Application
programming (ICP and IAP). 10K
write/erase cycles guaranteed, data
retention: 20 years at 55°C.
– 384 bytes RAM
– 256 bytes data EEPROM with readout
protection. 300K write/erase cycles
guaranteed, data retention: 20 yrs at 55°C.
■ Clock, reset and supply management
– Enhanced reset system
– Enhanced low voltage supervisor (LVD) for
main supply and an auxiliary voltage
detector (AVD) with interrupt capability for
implementing safe power-down procedures
– Clock sources: Internal 1% RC oscillator,
crystal/ceramic resonator or external clock
– Internal 32 MHz input clock for Auto-reload
timer
– Optional x4 or x8 PLL for 4 or 8 MHz
internal clock
– 5 power saving modes: Halt, Active-halt,
Wait and Slow, Auto Wake Up From Halt
■ I/O ports
– Up to 15 multifunctional bidirectional I/Os
–7 high sink outputs
■ 4 timers
– Configurable watchdog timer
– Two 8-bit Lite timers with prescaler,
watchdog, 1 real-time base and 1 input
capture
– 12-bit auto-reload timer with 4 PWM
outputs, input capture and output compare
functions
ST7DALIF2
data EEPROM, ADC, timers, SPI, DALI
■ 2 communication interfaces
– SPI synchronous serial interface
– DALI communication interface
■ Interrupt management
– 10 interrupt vectors plus TRAP and RESET
– 15 external interrupt lines (on 4 vectors)
■ A/D converter
– 7 input channels
– Fixed gain op-amp
– 13-bit resolution for 0 to 430 mV (@ 5 V
V
)
DD
– 10-bit resolution for 430 mV to 5 V (@ 5 V
V
)
DD
■ Instruction set
– 8-bit data manipulation
– 63 basic instructions with illegal opcode
detection
– 17 main addressing modes
– 8 x 8 unsigned multiply instructions
■ Development tools
– Full hardware/software development
package
– DM (Debug module)
February 2009 Rev 3 1/171
www.st.com
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Contents ST7DALIF2
Contents
1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2 Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5 Register and memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6 Flash program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.3 Programming modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.3.1 In-circuit programming (ICP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.3.2 In application programming (IAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.4 ICC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.5 Memory protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.5.1 Readout protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.5.2 Flash write/erase protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.6 Related documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.7 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.7.1 Flash control/status register (FCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7 Data EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.3 Memory access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.4 Power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.5 Access error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.6 Data EEPROM readout protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7.7 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.8 EEPROM control/status register (EECSR) . . . . . . . . . . . . . . . . . . . . . . . . 27
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8 Central processing unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
8.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
8.3 CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
8.3.1 Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
8.3.2 Index registers (X and Y) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
8.3.3 Program counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
8.3.4 Condition code register (CC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
8.3.5 Stack pointer register (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
9 Supply, reset and clock management . . . . . . . . . . . . . . . . . . . . . . . . . . 32
9.1 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
9.2 Internal RC oscillator adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
9.3 Phase locked loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
9.4 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
9.4.1 Main clock control/status register (MCCSR) . . . . . . . . . . . . . . . . . . . . . 34
9.4.2 RC control register (RCCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
9.5 Multi-oscillator (MO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
9.6 Reset sequence manager (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
9.6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
9.6.2 Asynchronous external RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
9.6.3 External power-on RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
9.6.4 Internal low voltage detector (LVD) RESET . . . . . . . . . . . . . . . . . . . . . . 39
9.6.5 Internal watchdog RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
9.7 System integrity management (SI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
9.7.1 Low voltage detector (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
9.7.2 Auxiliary voltage detector (AVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
9.7.3 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
9.7.4 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
10 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
10.1 Non maskable software interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
10.2 External interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
10.3 Peripheral interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
10.4 Interrupt registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
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10.4.1 External interrupt control register (EICR) . . . . . . . . . . . . . . . . . . . . . . . . 48
10.4.2 External interrupt selection register (EISR) . . . . . . . . . . . . . . . . . . . . . . 48
11 Power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
11.2 Slow mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
11.3 Wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
11.4 Halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
11.4.1 Halt mode recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
11.5 Active-halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
11.6 Auto wakeup from Halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
11.6.1 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
12 I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
12.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
12.2 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
12.2.1 Input modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
12.2.2 Output modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
12.2.3 Alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
12.3 I/O port implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
12.4 Unused I/O pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
12.5 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
12.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
12.7 Device-specific I/O port configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
13 Watchdog timer (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
13.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
13.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
13.4 Hardware watchdog option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
13.4.1 Using Halt mode with the WDG (WDGHALT option) . . . . . . . . . . . . . . . 70
13.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
13.6 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
13.6.1 Control register (CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
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14 12-bit autoreload timer 2 (AT2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
14.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
14.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
14.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
14.3.1 PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
14.3.2 Output compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
14.3.3 Break function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
14.3.4 Input capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
14.4 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
14.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
14.6 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
14.6.1 Timer control status register (ATCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . 77
14.6.2 Counter register high (CNTRH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
14.6.3 Counter register low (CNTRL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
14.6.4 Autoreload register (ATRH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
14.6.5 Autoreload register (ATRL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
14.6.6 PWM output control register (PWMCR) . . . . . . . . . . . . . . . . . . . . . . . . . 79
14.6.7 PWMx control status register (PWMxCSR) . . . . . . . . . . . . . . . . . . . . . . 79
14.6.8 Break control register (BREAKCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
14.6.9 PWMx duty cycle register high (DCRxH) . . . . . . . . . . . . . . . . . . . . . . . . 80
14.6.10 PWMx duty cycle register low (DCRxL) . . . . . . . . . . . . . . . . . . . . . . . . . 81
14.6.11 Input capture register high (ATICRH) . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
14.6.12 Input capture register low (ATICRL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
14.6.13 Transfer control register (TRANCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
15 Lite timer 2 (LT2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
15.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
15.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
15.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
15.3.1 Timebase counter 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
15.3.2 Input capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
15.3.3 Timebase counter 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
15.4 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
15.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
15.6 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
15.6.1 Lite timer control/status register 2 (LTCSR2) . . . . . . . . . . . . . . . . . . . . . 86
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15.6.2 Lite timer autoreload register (LTARR) . . . . . . . . . . . . . . . . . . . . . . . . . . 87
15.6.3 Lite timer counter 2 (LTCNTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
15.6.4 Lite timer control/status register (LTCSR1) . . . . . . . . . . . . . . . . . . . . . . 87
15.6.5 Lite timer input capture register (LTICR) . . . . . . . . . . . . . . . . . . . . . . . . 88
16 DALI communication module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
16.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
16.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
16.3 DALI standard protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
16.4 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
16.5 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
16.6 Special functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
16.6.1 Forced transmission (test mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
16.6.2 Normal transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
16.6.3 DCM enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
16.7 DALI interface failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
16.8 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
16.9 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
16.10 Bi-phase bit detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
16.11 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
16.11.1 DCM data rate control register (DCMCLK) . . . . . . . . . . . . . . . . . . . . . . 96
16.11.2 DCM forward address register (DCMFA) . . . . . . . . . . . . . . . . . . . . . . . . 96
16.11.3 DCM forward data register (DCMFD) . . . . . . . . . . . . . . . . . . . . . . . . . . 97
16.11.4 DCM backward data register (DCMBD) . . . . . . . . . . . . . . . . . . . . . . . . . 97
16.11.5 DCM control register (DCMCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
16.11.6 DCM control/status register (DCMCSR) . . . . . . . . . . . . . . . . . . . . . . . . 98
17 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
17.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
17.3 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
17.4 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
17.4.1 Slave select management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
17.4.2 Master mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
17.4.3 Slave mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
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ST7DALIF2 Contents
17.4.4 Clock phase and clock polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
17.4.5 Error flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
17.4.6 Single master and multimaster configurations . . . . . . . . . . . . . . . . . . . 107
17.5 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
17.5.1 Using the SPI to wake-up the device from Halt mode . . . . . . . . . . . . . 108
17.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
17.7 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
17.7.1 Control register (SPICR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
17.7.2 Control/status register (SPICSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
17.7.3 Data I/O register (SPIDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
18 10-bit A/D converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
18.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
18.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
18.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
18.3.1 Analog power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
18.3.2 Input voltage amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
18.3.3 Digital A/D conversion result . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
18.3.4 A/D conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
18.4 Changing the conversion channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
18.5 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
18.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
18.7 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
18.7.1 Control/status register (ADCCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
18.7.2 Data register high (ADCDRH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
18.7.3 AMP control/data register low (ADCDRL) . . . . . . . . . . . . . . . . . . . . . . 117
19 Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
19.1 CPU addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
19.1.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
19.1.2 Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
19.1.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
19.1.4 Indexed (no offset, short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
19.1.5 Indirect (short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
19.1.6 Indirect indexed (short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
19.1.7 Relative mode (direct, indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
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Contents ST7DALIF2
19.2 Instruction groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
20 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
20.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
20.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
20.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
20.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
20.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
20.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
20.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
20.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
20.3.1 Operating conditions with low voltage detector (LVD) . . . . . . . . . . . . . 131
20.3.2 Auxiliary Voltage Detector (AVD) Thresholds . . . . . . . . . . . . . . . . . . . 131
20.3.3 Internal RC oscillator and PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
20.4 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
20.4.1 Supply current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
20.5 Clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
20.5.1 Crystal and ceramic resonator oscillators . . . . . . . . . . . . . . . . . . . . . . 138
20.6 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
20.7 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
20.7.1 Functional EMS (electromagnetic susceptibility) . . . . . . . . . . . . . . . . . 141
20.7.2 Electromagnetic interference (EMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
20.7.3 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 142
20.8 I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
20.8.1 General characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
20.9 Control pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
20.10 Communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . 151
20.10.1 SPI - serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
20.11 10-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
20.11.1 Amplifier output offset variation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
21 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
21.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
22 Device configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
22.1 Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
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ST7DALIF2 Contents
22.1.1 Option byte 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
22.1.2 Option byte 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
22.2 Device ordering information and transfer of customer code . . . . . . . . . . 164
23 Important notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
23.1 Execution of BTJX instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
23.2 ADC conversion spurious results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
23.3 A/ D converter accuracy for first conversion . . . . . . . . . . . . . . . . . . . . . . 166
23.4 Negative injection impact on ADC accuracy . . . . . . . . . . . . . . . . . . . . . 166
23.5 Clearing active interrupts outside interrupt routine . . . . . . . . . . . . . . . . . 166
23.6 Using PB4 as external interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
23.7 Timebase 2 interrupt in Slow mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
24 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
9/171
Description ST7DALIF2
1 Description
The ST7DALIF2 device is a member of the ST7 microcontroller family designed for DALI
applications running from 2.4 to 5.5 V. Different package options offer up to 15 I/O pins.
All devices are based on a common industry-standard 8-bit core, featuring an enhanced
instruction set and are available with Flash or ROM program memory. The ST7 family
architecture offers both power and flexibility to software developers, enabling the design of
highly efficient and compact application code.
The on-chip peripherals include a DALI communication interface and an SPI. For power
economy, the microcontroller can switch dynamically into, Slow, Wait, Active-halt, Auto
Wakeup from Halt or Halt mode when the application is in idle or stand-by state.
Typical applications include consumer, home, office, lighting and industrial products.
10/171
ST7DALIF2 Device summary
2 Device summary
Table 1. Device summary
Features ST7DALIF2
Program memory 8 Kbytes
RAM (stack) 384 (128) bytes
Data EEPROM 256 bytes
Peripherals
Operating supply 2.4V to 5.5V
CPU frequency
Operating temperature -40°C to +85°C
Packages SO20 300”
Lite Timer with Watchdog, Autoreload Timer with 32 MHz input clock, SPI,
10-bit ADC with Op-Amp, DALI
Up to 8 MHz (with external OSC up to 16 MHz and internal 1 MHz RC 1%
PLLx8/4 MHz)
11/171
Block diagram ST7DALIF2
8-BIT CORE
ALU
ADDRESS AND DATA BUS
OSC1
OSC2
RESET
PORT A
Internal
CLOCK
CONTROL
RAM
(384 Bytes)
PA7:0
(8 bits)
V
SS
V
DD
POWER
SUPPLY
PROGRAM
(8K Bytes)
LVD
MEMORY
PLL x 8
Ext.
1MHz
PLL
Int.
1MHz
8-Bit
LITE TIMER 2
PORT B
SPI
PB6:0
(7 bits)
DATA EEPROM
( 256 Bytes)
1% RC
OSC
to
16MHz
ADC
+ OpAmp
12-Bit
Auto-Reload
TIMER 2
CLKIN
/ 2
or PLL X4
8MHz -> 32MHz
WATCHDOG
DALI
3 Block diagram
Figure 1. General block diagram
12/171
ST7DALIF2 Pin description
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
V
SS
V
DD
AIN5/PB5
CLKIN/AIN4/PB4
MOSI/AIN3/PB3
MISO/AIN2/PB2
SCK/AIN1/PB1
SS
/AIN0/PB0
OSC1/CLKIN
OSC2
PA 5 (HS)/ATPWM3/ICCDATA
PA 4 (HS)/ATPWM2
PA 3 (HS)/ATPWM1
PA 2 (HS)/ATPWM0
PA 1 (HS)/ATIC
PA 0 (HS)/LTIC
12
11
9
10
DALIIN/AIN6/PB6
PA7(HS)/DALIOUT
PA6/MCO/ICCCLK/BREAK
RESET
ei3
ei2
ei0
ei1
eix associated external interrupt vector
(HS) 20mA high sink capability
4 Pin description
Figure 2. 20-pin SO package pinout
13/171
Pin description ST7DALIF2
Legend / Abbreviations for Ta b le 2:
Type: I = input, O = output, S = supply
In/Output level: C
Output level: HS = 20mA high sink (on N-buffer only)
Port and control configuration:
● Input: float = floating, wpu = weak pull-up, int = interrupt, ana = analog
● Output: OD = open drain, PP = push-pull
The RESET configuration of each pin is shown in bold which is valid as long as the device is
in reset state.
Table 2. Device pin description
Pin
no.
1V
2V
3 RESET
4 PB0/AIN0/SS
5 PB1/AIN1/SCK I/O C
Pin name
SS
DD
I/O C
Level Port / control
Type
Input
Output
S Ground
S Main power supply
T
I/O C
T
T
= CMOS 0.3VDD/0.7VDD with input trigger
T
Main
Input Output
int
float
wpu
ana
OD
function
reset)
PP
(after
Alternate function
X X Top priority non maskable interrupt (active low)
ADC Analog Input 0 or SPI Slave
Select (active low)
X
XX XPort B0
Caution: No negative current injection
allowed on this pin. For details, refer to
Section 20.2 on page 128
ei3
XXXXPort B1
ADC Analog Input 1 or SPI Serial
Clock
Caution: No negative current injection
allowed on this pin. For details, refer to
Section 20.2 on page 128
6 PB2/AIN2/MISO I/O C
7 PB3/AIN3/MOSI I/O C
8 PB4/AIN4/CLKIN I/O C
9 PB5/AIN5 I/O C
10 PB6/AIN6/DALIIN I/O C
XXXXPort B2
T
X
T
XXXXPort B4
T
XXXXPort B5 ADC Analog Input 5
T
XXXXPort B6 ADC Analog Input 6 or DALI Input
T
XX XPort B3
ei2
14/171
ADC Analog Input 2 or SPI Master In/
Slave Out Data
ADC Analog Input 3 or SPI Master Out
/ Slave In Data
ADC Analog Input 4 or External clock
input
ST7DALIF2 Pin description
Table 2. Device pin description (continued)
Pin
no.
Pin name
Type
11 PA7/DALIOUT I/O C
Level Port / control
Input Output
Input
T
Output
HS X
float
int
wpu
ana
XXPort A7 DALI Output
OD
function
reset)
PP
Main
(after
Alternate function
Main Clock Output or In Circuit
Communication Clock
or External BREAK
Caution: During normal operation this
pin must be pulled- up, internally or
PA6 /M C O/
12
ICCCLK/BREAK
I/O C
XXXPort A6
T
ei1
externally (external pull-up of 10k
mandatory in noisy environment). This
is to avoid entering ICC mode
unexpectedly during a reset. In the
application, even if the pin is
configured as output, any reset will put
it back in input pull-up.
PA5 /ATPWM3/
13
ICCDATA
I/O C
HS X X X Port A5
T
Auto-Reload Timer PWM3 or In Circuit
Communication Data
14 PA 4/ AT PW M 2 I/ O CTHS X X X Port A4 Auto-Reload Timer PWM2
15 PA 3/ AT PW M 1 I/ O C
16 PA 2/ AT PW M 0 I/ O C
17 PA1/ATIC I/O C
18 PA0 /LTIC I/O C
HS X
T
HS X X X Port A2 Auto-Reload Timer PWM0
T
HS X X X Port A1 Auto-Reload Timer Input Capture
T
HS X X X Port A0 Lite Timer Input Capture
T
ei0
XXPort A3 Auto-Reload Timer PWM1
19 OSC2 O Resonator oscillator inverter output
20 OSC1/CLKIN I
Resonator oscillator inverter input or External
clock input
15/171
Register and memory map ST7DALIF2
0000h
RAM
Flash Memory
(8K)
Interrupt & Reset Vectors
HW Registers
0080h
007Fh
0FFFh
(see Ta bl e 3 )
1000h
10FFh
FFE0h
FFFFh
(see Ta bl e 1 5)
0200h
Reserved
01FFh
Short Addressing
RAM (zero page)
128 Bytes Stack
0180h
01FFh
0080h
00FFh
(384 Bytes)
Data EEPROM
(256 Bytes)
E000h
1100h
DFFFh
Reserved
FFDFh
16-bit Addressing
RAM
0100h
017Fh
1 Kbyte
7 Kbytes
SECTOR 1
SECTOR 0
8K FLASH
FFFFh
FC00h
FBFFh
E000h
PROGRAM MEMORY
1000h
1001h
RCCR0
RCCR1
see Section 9.2 on page 32
FFDEh
FFDFh
RCCR0
RCCR1
see Section 9.2 on page 32
5 Register and memory map
As shown in Figure 3, the MCU is capable of addressing 64K bytes of memories and I/O
registers.
The available memory locations consist of 128 bytes of register locations, 384 bytes of
RAM, 256 bytes of data EEPROM and 8 Kbytes of user program memory. The RAM space
includes up to 128 bytes for the stack from 180h to 1FFh.
The highest address bytes contain the user reset and interrupt vectors.
The Flash memory contains two sectors (see Figure 3) mapped in the upper part of the ST7
addressing space so the reset and interrupt vectors are located in Sector 0 (F000h-FFFFh).
The size of Flash Sector 0 and other device options are configurable by Option byte (refer to
Section 22.1 on page 161).
Note: IMPORTANT: memory locations marked as “Reserved” must never be accessed. Accessing
a reserved area can have unpredictable effects on the device.
Figure 3. Memory map
16/171
ST7DALIF2 Register and memory map
Table 3. Hardware register map
Address Block
0000h
0001h
Por t A
0002h
0003h
0004h
Por t B
0005h
0006h
0007h
0008h
0009h
000Ah
000Bh
LITE
TIMER 2
000Ch
000Dh
000Eh
000Fh
0010h
0011h
0012h
0013h
0014h
0015h
0016h
0017h
0018h
AUTORELOAD
TIMER 2
0019h
001Ah
001Bh
001Ch
001Dh
001Eh
001Fh
0020h
0021h
0022h
0023h to
002Dh
Register
label
PA DR
PA DD R
PA OR
PBDR
PBDDR
PBOR
LTCSR2
LTA RR
LTCNTR
LTCSR1
LT IC R
AT CS R
CNTRH
CNTRL
AT RH
AT RL
PWMCR
PWM0CSR
PWM1CSR
PWM2CSR
PWM3CSR
DCR0H
DCR0L
DCR1H
DCR1L
DCR2H
DCR2L
DCR3H
DCR3L
ATICRH
ATICRL
TRANCR
BREAKCR
Register name
Port A Data Register
Port A Data Direction Register
Port A Option Register
Port B Data Register
Port B Data Direction Register
Port B Option Register
Reserved Area (2 bytes)
Lite Timer Control/Status Register 2
Lite Timer Auto-reload Register
Lite Timer Counter Register
Lite Timer Control/Status Register 1
Lite Timer Input Capture Register
Timer Control/Status Register
Counter Register High
Counter Register Low
Auto-Reload Register High
Auto-Reload Register Low
PWM Output Control Register
PWM 0 Control/Status Register
PWM 1 Control/Status Register
PWM 2 Control/Status Register
PWM 3 Control/Status Register
PWM 0 Duty Cycle Register High
PWM 0 Duty Cycle Register Low
PWM 1 Duty Cycle Register High
PWM 1 Duty Cycle Register Low
PWM 2 Duty Cycle Register High
PWM 2 Duty Cycle Register Low
PWM 3 Duty Cycle Register High
PWM 3 Duty Cycle Register Low
Input Capture Register High
Input Capture Register Low
Transfer Control Register
Break Control Register
Reserved area (11 bytes)
Reset
status
(1)
FFh
00h
40h
1)
FFh
00h
00h
00h
00h
00h
0x00 0000b
00h
0x00 0000b
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
01h
00h
Remarks
R/W
R/W
R/W
R/W
R/W
(2)
R/W
R/W
R/W
Read Only
R/W
Read Only
R/W
Read Only
Read Only
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Read Only
Read Only
R/W
R/W
002Eh WDG WDGCR Watchdog Control Register 7Fh R/W
0002Fh FLASH FCSR Flash Control/Status Register 00h R/W
00030h EEPROM EECSR
0031h
0032h
0033h
SPI
SPIDR
SPICR
SPICSR
Data EEPROM Control/Status
Register
SPI Data I/O Register
SPI Control Register
SPI Control Status Register
00h R/W
xxh
0xh
00h
R/W
R/W
R/W
17/171
Register and memory map ST7DALIF2
Table 3. Hardware register map (continued)
Address Block
0034h
0035h
ADC
0036h
Register
label
ADCCSR
ADCDRH
ADCDRL
Register name
A/D Control Status Register
A/D Data Register High
A/D Amplifier Control/Data Low
Register
Reset
status
00h
xxh
0xh
0037h ITC EICR External Interrupt Control Register 00h R/W
0038h MCC MCCSR Main Clock Control/Status Register 00h R/W
0039h
003Ah
Clock
and
Reset
RCCR
SICSR
RC oscillator Control Register
System Integrity Control/Status
Register
FFh
0000 0xx0b
003Bh Reserved area (1 byte)
003Ch ITC EISR External Interrupt Selection Register 0Ch R/W
003Dh to
003Fh
0040h
0041h
0042h
0043h
0044h
0045h
0046h to
0048h
0049h
004Ah
DALI
AWU
DCMCLK
DCMFA
DCMFD
DCMBD
DCMCR
DCMCSR
AWUPR
AWUCSR
Reserved area (3 bytes)
DALI Clock Register
DALI Forward Address Register
DALI Forward Data Register
DALI Backward Data Register
DALI Control Register
DALI Control/Status Register
Reserved area (3 bytes)
AWU Prescaler Register
AWU Control/Status Register
00h
00h
00h
00h
00h
00h
FFh
00h
Remarks
R/W
Read Only
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
(3)
DMCR
DMSR
DMBK1H
DMBK1L
DMBK2H
DMBK2L
004Bh
004Ch
004Dh
004Eh
004Fh
0050h
DM
0051h to
007Fh
1. The contents of the I/O port DR registers are readable only in output configuration. In input configuration,
the values of the I/O pins are returned instead of the DR register contents.
2. The bits associated with unavailable pins must always keep their reset value.
3. For a description of the Debug Module registers, see ST7 ICC Protocol Reference Manual.
DM Control Register
DM Status Register
DM Breakpoint Register 1 High
DM Breakpoint Register 1 Low
DM Breakpoint Register 2 High
DM Breakpoint Register 2 Low
Reserved area (47 bytes)
00h
00h
00h
00h
00h
00h
R/W
R/W
R/W
R/W
R/W
R/W
Legend: x=undefined, R/W=read/write
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ST7DALIF2 Flash program memory
6 Flash program memory
6.1 Introduction
The ST7 single voltage extended Flash (XFlash) is a non-volatile memory that can be
electrically erased and programmed either on a byte-by-byte basis or up to 32 bytes in
parallel.
The XFlash devices can be programmed off-board (plugged in a programming tool) or onboard using In-Circuit Programming or In-Application Programming.
The array matrix organization allows each sector to be erased and reprogrammed without
affecting other sectors.
6.2 Main features
● ICP (In-Circuit Programming)
● IAP (In-Application Programming)
● ICT (In-Circuit Testing) for downloading and executing user application test patterns in
RAM
● Sector 0 size configurable by option byte
● Readout and write protection
6.3 Programming modes
The ST7 can be programmed in three different ways:
● Insertion in a programming tool. In this mode, FLASH sectors 0 and 1, option byte row
and data EEPROM (if present) can be programmed or erased.
● In-Circuit Programming. In this mode, FLASH sectors 0 and 1, option byte row and data
EEPROM (if present) can be programmed or erased without removing the device from
the application board.
● In-Application Programming. In this mode, sector 1 and data EEPROM (if present) can
be programmed or erased without removing the device from the application board and
while the application is running.
6.3.1 In-circuit programming (ICP)
ICP uses a protocol called ICC (In-Circuit Communication) which allows an ST7 plugged on
a printed circuit board (PCB) to communicate with an external programming device
connected via cable. ICP is performed in three steps:
Switch the ST7 to ICC mode (In-Circuit Communications). This is done by driving a specific
signal sequence on the ICCCLK/DATA pins while the RESET pin is pulled low. When the
ST7 enters ICC mode, it fetches a specific RESET vector which points to the ST7 System
Memory containing the ICC protocol routine. This routine enables the ST7 to receive bytes
from the ICC interface.
● Download ICP Driver code in RAM from the ICCDATA pin
● Execute ICP Driver code in RAM to program the FLASH memory
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Flash program memory ST7DALIF2
Depending on the ICP Driver code downloaded in RAM, FLASH memory programming can
be fully customized (number of bytes to program, program locations, or selection of the
serial communication interface for downloading).
6.3.2 In application programming (IAP)
This mode uses an IAP Driver program previously programmed in Sector 0 by the user (in
ICP mode).
This mode is fully controlled by user software. This allows it to be adapted to the user
application, (user-defined strategy for entering programming mode, choice of
communications protocol used to fetch the data to be stored etc.).
IAP mode can be used to program any memory areas except Sector 0, which is write/erase
protected to allow recovery in case errors occur during the programming operation.
6.4 ICC interface
ICP needs a minimum of 4 and up to 6 pins to be connected to the programming tool. These
pins are:
● RESET: device reset
● V
● ICCCLK: ICC output serial clock pin
● ICCDATA: ICC input serial data pin
● CLKIN/PB4: main clock input for external source
● V
Note: 1 If the ICCCLK or ICCDATA pins are only used as outputs in the application, no signal
isolation is necessary. As soon as the Programming Tool is plugged to the board, even if an
ICC session is not in progress, the ICCCLK and ICCDATA pins are not available for the
application. If they are used as inputs by the application, isolation such as a serial resistor
has to be implemented in case another device forces the signal. Refer to the Programming
Tool documentation for recommended resistor values.
2 During the ICP session, the programming tool must control the RESET
conflicts between the programming tool and the application reset circuit if it drives more than
5mA at high level (push pull output or pull-up resistor<1K). A schottky diode can be used to
isolate the application RESET circuit in this case. When using a classical RC network with
R>1K or a reset management IC with open drain output and pull-up resistor>1K, no
additional components are needed. In all cases the user must ensure that no external reset
is generated by the application during the ICC session.
3 The use of Pin 7 of the ICC connector depends on the Programming Tool architecture. This
pin must be connected when using most ST Programming Tools (it is used to monitor the
application power supply). Please refer to the Programming Tool manual.
4 Pin 9 has to be connected to the CLKIN/PB4 pin of the ST7 when the clock is not available
in the application or if the selected clock option is not programmed in the option byte. ST7
devices with multi-oscillator capability need to have OSC1 and OSC2 grounded in this case.
5 With any programming tool, while the ICP option is disabled, the external clock has to be
provided on PB4.
: device power supply ground
SS
: application board power supply (optional, see Note 3)
DD
pin. This can lead to
Caution: During normal operation the ICCCLK pin must be pulled- up, internally or externally
(external pull-up of 10k mandatory in noisy environment). This is to avoid entering ICC
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ST7DALIF2 Flash program memory
ICC CONNECTOR
ICCDATA
ICCCLK
RESET
V
DD
HE10 CONNECTOR TYPE
APPLICATION
POWER SUPPLY
1
246810
975 3
PROGRAMMING TOOL
ICC CONNECTOR
APPLICATION BOARD
ICC Cable
(See Note 3)
ST7
OPTIONAL
See Note 1 and Caution
See Note 2
APPLICATION
RESET SOURCE
APPLICATION
I/O
(See Note 4)
(See Note 5)
CLKIN/PB4
mode unexpectedly during a reset. In the application, even if the pin is configured as output,
any reset will put it back in input pull-up.
Figure 4. Typical ICC interface
6.5 Memory protection
There are two different types of memory protection: Read Out Protection and Write/Erase
Protection which can be applied individually.
6.5.1 Readout protection
Readout protection, when selected provides a protection against program memory content
extraction and against write access to Flash memory. Even if no protection can be
considered as totally unbreakable, the feature provides a very high level of protection for a
general purpose microcontroller. Both program and data E
In flash devices, this protection is removed by reprogramming the option. In this case, both
program and data E
2
memory are automatically erased and the device can be
reprogrammed.
Readout protection selection depends on the device type:
● In Flash devices it is enabled and removed through the FMP_R bit in the option byte.
● In ROM devices it is enabled by mask option specified in the Option List.
6.5.2 Flash write/erase protection
Write/erase protection, when set, makes it impossible to both overwrite and erase program
memory. It does not apply to E
applications and prevent any change being made to the memory content.
Caution: Once set, Write/erase protection can never be removed. A write-protected flash device is no
longer reprogrammable.
Write/erase protection is enabled through the FMP_W bit in the option byte.
2
data. Its purpose is to provide advanced security to
21/171
2
memory are protected.
Flash program memory ST7DALIF2
6.6 Related documentation
For details on Flash programming and ICC protocol, refer to the ST7 Flash Programming
Reference Manual and to the ST7 ICC Protocol Reference Manual
.
6.7 Register description
6.7.1 Flash control/status register (FCSR)
This register is reserved for programming using ICP, IAP or other programming methods. It
controls the XFlash programming and erasing operations.
When an EPB or another programming tool is used (in socket or ICP mode), the RASS keys
are sent automatically.
1st RASS Key: 0101 0110 (56h)
2nd RASS Key: 1010 1110 (AEh)
FCSR Reset value:0000 0000 (00h)
76543210
00000OPTLATPGM
R/W R/W R/W R/W R/W R/W R/W R/W
Table 4. Flash control/status register address and reset value
Address (Hex) Register label 7 6 5 4 3 2 1 0
002Fh FCSR reset value 0 0 0 0 0 0 0 0
22/171
ST7DALIF2 Data EEPROM
EECSR
HIGH VOLTAGE
PUMP
0 E2LAT00 0 0 0 E2PGM
EEPROM
MEMORY MATRIX
(1 ROW = 32 x 8 BITS)
ADDRESS
DECODER
DATA
MULTIPLEXER
32 x 8 BITS
DATA LATCHES
ROW
DECODER
DATA BUS
4
4
4
128128
ADDRESS BUS
7 Data EEPROM
7.1 Introduction
The Electrically Erasable Programmable Read Only Memory can be used as a non volatile
back-up for storing data. Using the EEPROM requires a basic access protocol described in
this chapter.
7.2 Main features
■ Up to 32 Bytes programmed in the same cycle
■ EEPROM mono-voltage (charge pump)
■ Chained erase and programming cycles
■ Internal control of the global programming cycle duration
■ Wait mode management
■ Readout protection
Figure 5. EEPROM block diagram
7.3 Memory access
The Data EEPROM memory read/write access modes are controlled by the E2LAT bit of the
EEPROM Control/Status register (EECSR). The flowchart in Figure 6 describes these
different memory access modes.
Read operation (E2LAT=0)
The EEPROM can be read as a normal ROM location when the E2LAT bit of the EECSR
register is cleared.
23/171
Data EEPROM ST7DALIF2
READ MODE
E2LAT=0
E2PGM=0
WRITE MODE
E2LAT=1
E2PGM=0
READ BYTES
IN EEPROM AREA
WRITE UP TO 32 BYTES
IN EEPROM AREA
(with the same 11 MSB of the address)
START PROGRAMMING CYCLE
E2LAT=1
E2PGM=1 (set by software)
E2LAT
01
CLEARED BY HARDWARE
On this device, Data EEPROM can also be used to execute machine code. Take care not to
write to the Data EEPROM while executing from it. This would result in an unexpected code
being executed.
Write operation (E2LAT=1)
To access the write mode, the E2LAT bit has to be set by software (the E2PGM bit remains
cleared). When a write access to the EEPROM area occurs, the value is latched inside the
32 data latches according to its address.
When PGM bit is set by the software, all the previous bytes written in the data latches (up to
32) are programmed in the EEPROM cells. The effective high address (row) is determined
by the last EEPROM write sequence. To avoid wrong programming, the user must take care
that all the bytes written between two programming sequences have the same high address:
only the five Least Significant Bits of the address can change.
At the end of the programming cycle, the PGM and LAT bits are cleared simultaneously.
Note: Care should be taken during the programming cycle. Writing to the same memory location
will over-program the memory (logical AND between the two write access data result)
because the data latches are only cleared at the end of the programming cycle and by the
falling edge of the E2LAT bit.
It is not possible to read the latched data.
This note is illustrated by Figure 8.
Figure 6. Data EEPROM programming flowchart
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ST7DALIF2 Data EEPROM
Byte 1 Byte 2 Byte 32
PHASE 1
Programming cycle
Read operation impossible
PHASE 2
Read operation possible
E2LAT bit
E2PGM bit
Writing data latches Waiting E2PGM and E2LAT to fall
Set by USER application
Cleared by hardware
⇓ Row / Byte ⇒ 0 1 2 3 ... 30 31 Physical address
0 00h...1Fh
1 20h...3Fh
...
N Nx20h...Nx20h+1Fh
ROW
DEFINITION
Figure 7. Data EEPROM write operation
Note: If a programming cycle is interrupted (by a reset action), the integrity of the data in memory
is not guaranteed.
7.4 Power saving modes
Wait mode
The data EEPROM can enter Wait mode on execution of the WFI instruction of the
microcontroller or when the microcontroller enters Active-Halt mode.The data EEPROM will
immediately enter this mode if there is no programming in progress, otherwise the data
EEPROM will finish the cycle and then enter Wait mode.
Active-halt mode
Refer to Wait mode.
Halt mode
The data EEPROM immediately enters Halt mode if the microcontroller executes the HALT
instruction. Therefore the EEPROM will stop the function in progress, and data may be
corrupted.
7.5 Access error handling
If a read access occurs while E2LAT=1, then the data bus will not be driven.
If a write access occurs while E2LAT=0, then the data on the bus will not be latched.
25/171
Data EEPROM ST7DALIF2
LAT
ERASE CYCLE WRITE CYCLE
PGM
t
PROG
READ OPERATION NOT POSSIBLE
WRITE OF
DATA LATCHES
READ OPERATION POSSIBLE
INTERNAL
PROGRAMMING
VOLTAGE
If a programming cycle is interrupted (by a RESET action), the memory data will not be
guaranteed.
7.6 Data EEPROM readout protection
The readout protection is enabled through an option bit (see Section 22.1 on page 161).
When this option is selected, the programs and data stored in the EEPROM memory are
protected against readout (including a re-write protection). In Flash devices, when this
protection is removed by reprogramming the Option Byte, the entire Program memory and
EEPROM is first automatically erased.
Note: Both Program Memory and data EEPROM are protected using the same option bit.
Figure 8. Data EEPROM programming cycle
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ST7DALIF2 Data EEPROM
7.7 Register description
7.8 EEPROM control/status register (EECSR)
Read/Write
Reset Value: 0000 0000 (00h)
7 0
000000E2LATE2PGM
Bits 7:2 = Reserved, forced by hardware to 0.
Bit 1 = E2LAT Latch Access Transfer
This bit is set by software. It is cleared by hardware at the end of the programming cycle. It
can only be cleared by software if the E2PGM bit is cleared.
0: Read mode
1: Write mode
Bit 0 = E2PGM Programming control and status
This bit is set by software to begin the programming cycle. At the end of the programming
cycle, this bit is cleared by hardware.
0: Programming finished or not yet started
1: Programming cycle is in progress
Note: If the E2PGM bit is cleared during the programming cycle, the memory data is not
guaranteed
Table 5. Data EEPROM register map and reset values
Address
(Hex.)
0030h
Register
label
EECSR
Reset
Valu e
76543210
E2LAT0E2PGM
000000
0
27/171
Central processing unit (CPU) ST7DALIF2
Accumulator
X index register
Y index register
Stack pointer
Condition code register
Program counter
70
1C1I1HI0NZ
Reset value = reset vector @ FFFEh-FFFFh
70
70
70
0
7
15 8
PCH
PCL
15
87 0
Reset value = stack higher address
Reset value = 1 X11X1XX
Reset value = XXh
Reset value = XXh
Reset value = XXh
X = undefined value
8 Central processing unit (CPU)
8.1 Introduction
This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8bit data manipulation.
8.2 Main features
● Enable executing 63 basic instructions
● Fast 8-bit by 8-bit multiply
● 17 main addressing modes (with indirect addressing mode)
● Two 8-bit index registers
● 16-bit stack pointer
● Low power Halt and Wait modes
● Priority maskable hardware interrupts
● Non-maskable software/hardware interrupts
8.3 CPU registers
The six CPU registers shown in Figure 9 are not present in the memory mapping and are
accessed by specific instructions.
Figure 9. CPU registers
28/171
ST7DALIF2 Central processing unit (CPU)
8.3.1 Accumulator (A)
The Accumulator is an 8-bit general purpose register used to hold operands and the results
of the arithmetic and logic calculations and to manipulate data.
8.3.2 Index registers (X and Y)
These 8-bit registers are used to create effective addresses or as temporary storage areas
for data manipulation. (The Cross-Assembler generates a precede instruction (PRE) to
indicate that the following instruction refers to the Y register.)
The Y register is not affected by the interrupt automatic procedures.
8.3.3 Program counter (PC)
The program counter is a 16-bit register containing the address of the next instruction to be
executed by the CPU. It is made of two 8-bit registers PCL (Program Counter Low which is
the LSB) and PCH (Program Counter High which is the MSB).
8.3.4 Condition code register (CC)
The 8-bit Condition Code register contains the interrupt masks and four flags representative
of the result of the instruction just executed. This register can also be handled by the PUSH
and POP instructions. These bits can be individually tested and/or controlled by specific
instructions.
CC Reset value: 111x1xxx
76543210
11I1HI0NZC
R/W R/W R/W R/W R/W R/W R/W R/W
Table 6. Arithmetic management bits
BIt Name Function
Half carry
This bit is set by hardware when a carry occurs between bits 3 and 4 of the ALU
during an ADD or ADC instructions. It is reset by hardware during the same
4H
2N
instructions.
0: No half carry has occurred.
1: A half carry has occurred.
This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD
arithmetic subroutines.
Negative
This bit is set and cleared by hardware. It is representative of the result sign of the last
arithmetic, logical or data manipulation. It is a copy of the result 7th bit.
0: The result of the last operation is positive or null.
1: The result of the last operation is negative (that is, the most significant bit is a logic
1.
This bit is accessed by the JRMI and JRPL instructions.
29/171
Central processing unit (CPU) ST7DALIF2
Table 6. Arithmetic management bits (continued)
BIt Name Function
Zero (Arithmetic Management bit)
This bit is set and cleared by hardware. This bit indicates that the result of the last
1Z
0C
Table 7. Software interrupt bits
BIt Name Function
5I1
3I0
Table 8. Interrupt software priority selection
arithmetic, logical or data manipulation is zero.
0: The result of the last operation is different from zero.
1: The result of the last operation is zero.
This bit is accessed by the JREQ and JRNE test instructions.
Carry/borrow
This bit is set and cleared by hardware and software. It indicates an overflow or an
underflow has occurred during the last arithmetic operation.
0: No overflow or underflow has occurred.
1: An overflow or underflow has occurred.
This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC
instructions. It is also affected by the ‘bit test and branch’, shift and rotate instructions.
Software Interrupt Priority 1
The combination of the I1 and I0 bits determines the current interrupt software priority
(see Ta b le 8 ).
Software Interrupt Priority 0
The combination of the I1 and I0 bits determines the current interrupt software priority
(see Ta b le 8 ).
Interrupt software priority Level I1 I0
Level 0 (main)
Low
10
Level 1 01
Level 2 00
Level 3 (= interrupt disable) 1 1
High
These two bits are set/cleared by hardware when entering in interrupt. The loaded value is
given by the corresponding bits in the interrupt software priority registers (ISPRx). They can
be also set/cleared by software with the RIM, SIM, IRET, HALT, WFI and PUSH/POP
instructions.
See Section 10: Interrupts on page 45 for more details.
30/171
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