ST ST7580 User Manual

FSK, PSK multi-mode power line networking

VFQFPN 7x7x1.0 48L

(pitch 0.50)

Features

■ Fully integrated narrow-band power line

networking system-on-chip

■ High-performing PHY processor with

embedded turnkey firmware featuring: – B-FSK modulation up to 9.6 kbps – B-PSK, Q-PSK, 8-PSK modulations up to

28.8 kbps – Dual channel operation mode – Convolutional error correction coding – Signal-to-noise ratio estimation – B-PSK with PNA mode against impulsive

noise

■ Protocol engine embedding turnkey

communication protocol –Framing service – Error detection – Sniffer functionality

■ Host controller UART interface up to 57.6 kbps

■ AES-128 based authentication and

confidentiality services

■ Fully integrated analog front end:

– ADC and DAC – Digital transmission level control – PGA with automatic gain control – High sensitivity receiver

■ Fully integrated single-ended power amplifier

for line driving – Up to 1 A RMS, 14 V p-p output – Configurable active filtering topology – Very high linearity – Embedded temperature sensor – Current control feature

■ 8 to 18 V power amplifier supply

■ 3.3 V or 5 V digital I/O supply

■ Zero crossing detection

ST7580

system-on-chip

■ Suitable for EN50065, FCC part 15 and ARIB

compliant applications

■ Communication carrier frequency

programmable up to 250 kHz

■ VFQFPN48 7x7x1.0 48L exposed pad

package

■ -40 °C to +85 °C temperature range

Applications

■ Smart metering applications

■ Street lighting control

■ Command and control networking

Description

The ST7580 is a flexible power line networking system-on-chip combining a high performing PHY processor core and a protocol controller with a fully integrated analog front end (AFE) and line driver for a scalable future-proof, cost effective, single chip, narrow-band power line communication solution.

Table 1. Device summary

Order codes Package Packaging

ST7580

VFQFPN48

ST7580TR Tape and reel

Tube

January 2012 Doc ID 022644 Rev 1 1/33

www.st.com

Contents ST7580

Contents

1 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2.1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

5 Analog front end (AFE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5.1 Reception path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5.2 Transmission path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5.3 Power amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5.4 Current and voltage control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

5.5 Thermal shutdown and temperature control . . . . . . . . . . . . . . . . . . . . . . . 17

5.6 Zero crossing comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

6 Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

6.1 Ground connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

7 Clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

8 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

8.1 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

9 Physical layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

9.1 PSK modulations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

9.1.1 PSK modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

9.1.2 PSK physical frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

9.2 FSK modulations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

9.2.1 FSK options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

9.2.2 FSK physical frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

2/33 Doc ID 022644 Rev 1

ST7580 Contents

9.2.3 FSK settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

9.3 Channel and modulation selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

10 Data link layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

10.1 Data link frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

10.2 Error detection and sniffer mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

10.3 Security services . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

11 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Doc ID 022644 Rev 1 3/33

Device overview ST7580

AM02502v1

WATCHDOG

TIMERS

Power Management

ADC

PGA

DAC

GAIN CTRL

DDS

Zero Crossing

Detection

Line Driver

Thermal

Management

Clock Management

Protocol

Controller

TX AFE

PHY processor

BPF

Output Current

Control

SPI0/UART

ADC

RX AFE

TX_OUT

RX_IN

PA_OUT

PA_IN-

PA_IN+

VCC

(8-18V)

VDD

(1.8V)

ZC_IN

VDD_PLL

(1.8V)

XIN

VCCA

(5V)

T_REQ

RXD

TXD

BR0

BR1

VDDIO

(5 / 3.3V)

ON-CHIP

Memories

ON-CHIP

Memories

128bit

AES

PL_RX_ON

PL_TX_ON

XOUT

1 Device overview

Made using multi-power technology with state-of-the-art VLSI CMOS lithography, the ST7580 is based on dual digital core architecture (a PHY processor engine and a protocol controller core) to guarantee outstanding communication performance with a high level of flexibility for either open standards or customized implementations.

A HW 128-bit AES encryption block with customizable key management is available on chip when secure communication is requested.

The on-chip analog front end featuring analog to digital and digital to analog conversion, automatic gain control, plus the integrated power amplifier delivering up to 1 A RMS output current makes the ST7580 a unique system-on-chip for power line communication.

Line coupling network design is also simplified, leading to a very low cost BOM.

Robust and performing operations are guaranteed while keeping power consumption and signal distortion levels very low; this makes the ST7580 an ideal platform for the most stringent application requirements and regulatory standards compliance.

Figure 1. Block diagram

4/33 Doc ID 022644 Rev 1

ST7580 Pin connection

AM02503v1

48 47 46 45 44 43 42 41 40 39 38 37

13 14 15 16 17 18 19 20 21 22 23 24

TXD

VDDIO

TRSTN

TMS

TCK

TDO

TDI

RESETN

VDD

XIN

CL_SEL

VSSA

VDDIO

GND

RESERVED0

VDDIO

VDD_REG_1V8

PA_OUT

VSS

RESERVED5

RESERVED4

VDD

GND

RESERVED3

RESERVED2

RESERVED1

PL_TX_ON

BR0

BR1

T_REQ

PL_RX_ON

XOUT

GND

VSSA

VDD_PLL

VCCA

ZC_IN

RX_IN

TX_OUT

PA_IN+

PA_IN-

VCC

GND

RXD

2 Pin connection

Figure 2. Pinout top view

Doc ID 022644 Rev 1 5/33

Pin connection ST7580

2.1 Pin description

Table 2. Pin description

Pin Name Type Reset state

1 TXD Digital output High Z Disabled

2 RXD Digital input High Z Disabled UART data in

3 VDDIO Power - - 3.3 V – 5 V I/O supply

4 TRSTN Digital input Input Enabled System JTAG interface reset (active low)

5 TMS Digital input Input Enabled System JTAG interface mode select

6 GND Power - - Digital ground

7 TCK Digital input High Z Disabled

8 TDO Digital output High Z Disabled System JTAG interface data out

9 TDI Digital input Input Enabled System JTAG interface data in

10 RESETN Digital input Input Disabled System reset (active low)

11 VDD Power - - 1.8 V digital supply

12 XIN Analog - - Crystal oscillator input / external clock input

13 XOUT Analog - -

Internal

Pull-up

Description

UART data out. External pull-up to VDDIO required

System JTAG interface clock. External pull-up to VDDIO required

Crystal oscillator output (if external clock is supplied on XIN, XOUT must be

left floating)

14 GND Power - - Digital ground

15 VSSA Power - - Analog ground

16 VDD_PLL Power - - 1.8 V PLL supply voltage (connect to VDD)

17 VCCA Power - -

18 ZC_IN Analog input - -

19 RX_IN Analog input - - Reception analog input

20 TX_OUT Analog output - - Transmission analog output

21 PA_IN+ Analog input - -

22 PA_IN- Analog input - -

23 CL Analog input - - Current limit sense input

24 VCC Power - - Power supply

25 VSS Power - - Power ground

26 PA_OUT Analog output - - Power amplifier output

5 V analog supply / internal regulator output. Externally accessible for filtering purposes only.

Zero crossing input If not used connect to VSSA

Power amplifier Non-inverting input

Power amplifier Inverting input

6/33 Doc ID 022644 Rev 1

ST7580 Pin connection

Table 2. Pin description (continued)

Pin Name Type Reset state

27 VDD_REG_1V8 Power - -

28 VDDIO Power - - 3.3 V - 5 V I/O supply

29 NC - - - Not used, leave floating

30 NC - - - Not used, leave floating

31 RESERVED0 Power - - Pull-up to VDDIO.

32 NC - - - Not used, leave floating

33 GND Power - - Digital ground

34 VDDIO Power - - 3.3 V – 5 V I/O supply

35 VSSA Power - - Analog ground

36 CL_SEL Digital output High Z Disabled Current limit resistor selection output

37 PL_RX_ON Digital output High Z Disabled Reception in progress output

38 T_REQ Digital input High Z Disabled UART communication control line

39 BR1 Digital input High Z Disabled

40 BR0 Digital Input High Z Disabled

41 PL_TX_ON Digital output High Z Disabled Transmission in progress output

Internal

Pull-up

Description

1.8 V digital supply / internal regulator output. Externally accessible for filtering purposes only

UART baud rate selection (sampled after each reset event) see Table 3.

42 RESERVED1 - - - Pull up to VDDIO

43 RESERVED2 - - - Pull up to VDDIO

44 RESERVED3 - - - Pull up to VDDIO

45 GND Power - - Digital ground

46 VDD Power - - 1.8 V digital supply

47 RESERVED4 - - - Connect to VDDIO

48 RESERVED5 - - - Pull up to VDDIO

Electrically connected to VSSA. It is recommended

- Exposed pad - - -

that the exposed pad be thermally connected to a copper ground plane for enhanced electrical and thermal performance.

Table 3. UART baud rate selection

BR0 BR1 Baud rate

0 0 9600

0 1 19200

1 0 38400

1 1 57600

Doc ID 022644 Rev 1 7/33

Maximum ratings ST7580

3 Maximum ratings

3.1 Absolute maximum ratings

Figure 3. Absolute maximum ratings

Val ue

Symbol Parameter

Min. Max.

VCC Power supply voltage -0.3 20 V

VSSA-GND Voltage between VSSA and GND -0.3 0.3 V

VDDIO I/O supply voltage -0.3 5.5 V

VI Digital input voltage GND-0.3 VDDIO+0.3 V

VO Digital output voltage GND-0.3 VDDIO+0.3 V

V(PA_IN) PA inputs voltage range VSS-0.3 VCC+0.3 V

V(PA_OUT) PA_OUT voltage range VSS-0.3 VCC+0.3 V

V(RX_IN) RX_IN voltage range -(VCCA+0.3) VCC+0.3 V

Unit

V(ZC_IN) ZC_IN voltage range -(VCCA+0.3) VCCA+0.3 V

V(TX_OUT, CL) TX_OUT, CL voltage range VSSA-0.3 VCCA+0.3 V

V(XIN) XIN voltage range GND-0.3 VDDIO+0.3 V

I(PA_OUT)

amb

stg

V(ESD)

Power amplifier output non-repetitive pulse current

Power amplifier output non-repetitive RMS current

Operating ambient temperature -40 85 ºC

Storage temperature -50 150 ºC

Maximum withstanding voltage range Test condition: CDF-AEC-Q100-002 “human

body model” acceptance criteria: “normal performance”

3.2 Thermal data

Table 4. Thermal characteristics

Symbol Parameter Value Unit

thJA1

thJA2

1. Mounted on a 2-side + vias PCB with a ground dissipating area on the bottom side.

2. Same conditions as in Note 1, with maximum transmission duration limited to 100 s.

Maximum thermal resistance junction-ambient steady-state

5 A peak

1.4

-2 +2 kV

(1)

(2)

50 °C/W

42 °C/W

RMS

8/33 Doc ID 022644 Rev 1

9/33 Doc ID 022644 Rev 1

4 Electrical characteristics

TA = -40 to +85 °C, TJ < 125 °C, VCC = 18 V unless otherwise specified.

Table 5. Electrical characteristics

Symbol Parameter Note Min. Typ. Max. Unit

Power supply

VCC Power supply voltage 8 13 18 V

I(VCC) RX Power supply current - Rx mode VCCA externally supplied 0.35 0.5 mA

I(VCC) TX Power supply current - Tx mode, no load VCCA externally supplied 22 30 mA

VCC UVLO_TL VCC undervoltage lockout low threshold 6.1 6.5 6.95 V

VCC UVLO_TH VCC undervoltage lockout high threshold 6.8 7.2 7.5 V

VCC UVLO_HYST VCC undervoltage lockout hysteresis 250

I(VCCA) RX Analog supply current - Rx mode 5 6 mA

I(VCCA) TX Analog supply current - Tx mode V(TX_OUT) =5 V p-p, no load 8 10 mA

VDD Digital core supply voltage Externally supplied -10% 1.8 +10% V

I(VDD) Digital core supply current 35 41 mA

(1)

700 mV

Electrical characteristics ST7580

I(VDD) RESET Digital core supply current in RESET state 8 mA

VDD_PLL PLL supply voltage VDD V

I(VDD_PLL) PLL supply current 0.4 0.5 mA

VDDIO Digital I/O supply voltage Externally supplied -10% 3.3 or 5 +10% V

VDDIO

UVLO_TL

VDDIO

UVLO_TH

VDDIO

UVLO_HYST

VDDIO undervoltage lockout low threshold 2.2 2.4 2.6 V

VDDIO undervoltage lockout high threshold 2.45 2.65 2.85 V

VDDIO undervoltage lockout hysteresis 180 240 mV

Table 5. Electrical characteristics (continued)

Symbol Parameter Note Min. Typ. Max. Unit

Power amplifier

V(PA_OUT) BIAS Power amplifier output bias voltage - Rx mode VCC/2 V

GBWP Power amplifier gain-bandwidth product 100 MHz

I(PA_OUT) MAX Power amplifier maximum output current 1000 mA rms

V(PA_OUT) TOL Power amplifier output tolerance

V(PA_OUT) HD2 Power amplifier output 2

V(PA_OUT) HD3 Power amplifier output 3rd harmonic distortion -66 -63 dBc

Doc ID 022644 Rev 1 10/33

V(PA_OUT) THD Power amplifier output total harmonic distortion 0.1 0.15 %

C(PA_IN) Power amplifier input capacitance

PSRR Power supply rejection ratio

Analog front end

(2)

VCC=18 V,

harmonic distortion -70 -63 dBc

V(PA_OUT)

-3% +3%

= 14 V p-p (typ.), V(PA_OUT) BIAS = VCC/2, RLOAD=50 Ω

- See Figure 4

(3)

10 pF

PA_IN+ vs. VSS

PA_IN- vs. VSS

50 Hz 100 dB

1 kHz 93 dB

100 kHz 70 dB

ST7580 Electrical characteristics

CL_TH Current sense high threshold on CL pin 2.25 2.35 2.4 V

CL_RATIO Ratio between PA_OUT and CL output current 80

Transmitter

V(TX_OUT) BIAS Transmitter output bias voltage - Rx mode VCCA/2 V

V(TX_OUT) MAX Transmitter output maximum voltage swing TX_GAIN = 31, no load 4.8 4.95 VCCA V p-p

TX_GAIN Transmitter output digital gain range 0 31

TX_GAIN TOL Transmitter output digital gain tolerance -0.35 0.35 dB

R(TX_OUT) Transmitter output resistance 1 kΩ

V(TX_OUT) HD2 Transmitter output 2

harmonic distortion

V(TX_OUT) = V(TX_OUT) Max. no load, T = 25 °C

-72 -67 dBc

+ 23 hidden pages