Datasheet ST7540 Datasheet (ST)

General features

■ Half-duplex frequency shift keying (FSK)

transceiver

■ Integrated power line driver with programmable

voltage and current control

■ Programmable mains access:

– Synchronous
– Asynchronous

■ Single supply voltage (from 7.5V up to 13.5V)

■ Very low power consumption (I

■ Integrates 5V voltage regulator (up to 50mA)

with short circuit protection

■ Integrated 3.3V voltage regulator (up to 50mA)

with short circuit protection

■ 3.3V or 5V digital supply

■ 8 Programmable transmission frequencies

■ Programmable baud rate up to 4800BPS

■ Receiving sensitivity up to 250µV

■

Suitable for applications in accordance with EN
50065 Cenelec specification

■ Carrier or preamble detection

■ Band in use detection

■ Programmable control register

■ Watchdog timer

■ 8 or 16 Bit header recognition

■ ST7537 and ST7538 compatible

■ UART/SPI host interface

= 5mA)

q

RMS

ST7540

FSK power line transceiver

HTSSOP28 Exposed Pad

Description

The ST7540 is a Half Duplex
synchronous/asynchronous FSK Modem
designed for power line communication network
applications. It operates from a single supply
voltage and integrates a line driver and two linear
regulators for 5V and 3.3V. The device operation
is controlled by means of an internal register,
programmable through the synchronous serial
interface. Additional functions as watchdog, clock
output, output voltage and current control,
preamble detection, time-out and band in use are
included. Realized in Multipower BCD5
technology that allows to integrate DMOS, Bipolar
and CMOS structures in the same chip.

Order codes

Part number Package Packaging

ST7540 HTSSOP28 (Exposed Pad) Tube

ST7540TR HTSSOP28 (Exposed Pad) Tape and reel

September 2006 Rev 2 1/44

www.st.com

44

Contents ST7540

Contents

1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.1 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3.1 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3.3 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

5 Crystal resonator and external clock . . . . . . . . . . . . . . . . . . . . . . . . . . 15

6 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

6.1 Carrier frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

6.2 Baud rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

6.3 Mark and space frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

6.4 ST7540 Mains access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

6.5 Host processor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

6.5.1 Communication between Host and ST7540 . . . . . . . . . . . . . . . . . . . . . 20

6.5.2 Control register access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

6.6 Receiving mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

6.7 Transmission mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

6.8 Control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

2/44

ST7540 Contents

7 Auxiliary analog and digital functions . . . . . . . . . . . . . . . . . . . . . . . . . 36

7.1 Band in use . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

7.2 Time out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

7.3 Reset & watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

7.4 Output clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

7.5 Output voltage level freeze . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

7.6 Extended control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

7.7 Under voltage lock out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

7.8 Thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

7.9 5V Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

7.10 3.3V Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

7.11 Power-up procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

8 Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

3/44

Block diagram ST7540

1 Block diagram

Figure 1. Block diagram

TEST2

TEST1 BU/THERM

CD/PD

RxD

CLR/T

UART/SPI

REG/DATA

RxTx

TxD

SERIAL

INTERFACE

OSC

X1 WD

X2

CARRIER

DETECTION

PLL

TIME BASE

RSTO MCLK

DIGITAL

FILTER

CONTROL

REGISTER

FSK

MODULATOR

FSK

DEMOD

DAC

TEST

VREG

GND

IF

FILTER

FILTER

V

DD

BU

FILTER

TX

VREG

SV

ALC

PA_IN+

Vdc

SS

AGC

AMPL

CURRENT
CONTROL

VOLTAGE

CONTROL

PA_IN-

FILTER

+

-

PA

RX_IN

CL

Vsense

TX_OUT

CC

V

PA_OUT

V

SS

D03IN1407A

4/44

ST7540 Pin settings

2 Pin settings

2.1 Pin connection

Figure 2. Pin connection (top view)

REG_DATA

BU/THERM

UART/SPI

2.2 Pin description

CD_PD

GND

RxD

RxTx

TxD

CLR/T

V

DD

MCLK

RSTO

WD

PA_IN-

1

2

3

4

5

6

7

8

9

10

11

12

13

14

28

27

26

25

24

23

22

21

20

19

18

17

16

15

TEST2

TEST1

VDC

RX_IN

CL

Vsense

X2

X1_OSCIN

SS

SV

TX_OUT

PA_IN+

CC

V

V

SS

PA_OUT

Table 1. Pin description

N° Name Type Description

Carrier, preamble or frame header detect output.

1 CD_PD Digital/Output

2REG_DATA

3 GND Supply Digital ground

4 RxD Digital/Output RX data output.

5 RxTx

6TxD

Digital/Input
with internal pull-down

Digital/Input
with internal pull-up

Digital/Input
with internal pull-down

"1" No carrier, preamble or frame header detected
"0" Carrier, preamble or frame header detected

Mains or control register access selector
"1" - Control register access
"0" - Mains access

Rx or Tx mode selection input.
"1" - RX Session
"0" - TX Session

TX data input.

5/44

Pin settings ST7540

Table 1. Pin description (continued)

N° Name Type Description

Band in use/Thermal Shutdown event detection output.
In Rx mode:
"1" Signal within the programmed band

7 BU/THERM Digital/Output

8 CLR/T Digital/Output

9

V

DD

Supply/Power Digital supply voltage or 3.3V voltage regulator output

10 MCLK Digital/Output Master clock output

11 RSTO Digital/Output Power ON or watchdog reset output

"0" No signal within the programmed band
In Tx mode:
"1" - Thermal Shutdown event occurred
"0" - No Thermal Shutdown event occurred
(signal not latched)

Synchronous mains access clock or
control register access clock

Interface type:
“0” - Serial peripheral interface
“1” - UART interface

Watchdog input. The internal watchdog counter is
cleared on the falling edges.

12 UART/SPI

13 WD

Digital/Input
with internal pull-down

Digital/Input
with internal pull-up

14 PA_IN- Analog/Input Power line amplifier inverting input

15 PA_OUT Power/Output Power line amplifier output

16

17

V

SS

V

CC

Supply Power analog ground

Supply Power supply voltage

18 PA_IN+ Analog/Input Power line amplifier not inverting input

19 TX_OUT Analog/Output Small signal analog transmit output

20

SV

SS

Supply Analog signal ground

21 X1 Analog/Output Crystal oscillator output

22 X2 Analog/Input Crystal oscillator input - or external clock input

SENSE

(1)

Analog/Input Output voltage sensing input for the voltage control loop

23

V

Current limiting feedback.

24

CL

(2)

Analog/Input

A resistor between CL and SVSS sets the PLI current
limiting value. An integrated 80pF filtering input

capacitance is present on this pin.

25 RX_IN Analog/Input Receiving analog input

26 VDC Power 5V voltage regulator output

27 TEST1

Digital/Input
with internal pull-down

28 TEST2 Analog/Input

1. Cannot be left floating

2. Cannot be left floating

6/44

Test input. Must be connected to GND.

Test input. Must be connected SV

SS

ST7540 Electrical data

3 Electrical data

3.1 Maximum ratings

Table 2. Absolute maximum ratings

Symbol Parameter Value Unit

V

CC

V

DD

SVSS/GND Voltage between SVSS and GND

Power supply voltage -0.3 to + 14 V

Digital supply voltage -0.3 to +5.5 V

-0.3 to +0.3 V

V

I

V

O

I

O

,

V

sense

X2,PA_IN-

,PA_IN+, CL

Digital input voltage

Digital output voltage

GND - 0.3 to V

GND - 0.3 to V

Digital output current -2 to +2 mA

Voltage range at Vsense, X2, PA_IN-, PA_IN+, CL
Inputs

SVSS - 0.3 to 5.6

DD

DD

+0.3

+0.3

RX_IN Voltage range at RX_IN input -5.6 to 5.6 V

TX_OUT, X1 Voltage range at TX_OUT, X1 outputs

PA_OUT Voltage range at powered PA_OUT Output

I(PA_OUT)

T

A

T

STG

RxD,

PA _ OU T Pi n

Power line driver output current

Operating ambient temperature -40 to +85 °C

Storage temperature -50 to 150 °C

Maximum withstanding voltage range
Test condition: CDF-AEC-Q100-002- “Human

(1)

SVSS - 0.3 to 5.6

V

- 0.3 to +VCC +0.3

SS

650 mArms

±1750 V

Body Model”

Other pins ±2000 V

1. This current is intended as not repetitive pulse current

Acceptance criteria: “Normal Performance”

V

V

V

V

V

3.2 Thermal data

Table 3. Thermal data

Symbol Parameter

R

thJA1

R

thJA2

1. Mounted on Multilayer PCB with a dissipating surface on the bottom side of the PCB

2. It is the same condition of the point above, without any heatsinking surface on the board.

Maximum thermal resistance junction-ambient steady

(1)

state

Maximum thermal resistance junction-ambient Steady

(2)

State

HTSSOP28

Exposed Pad

Unit

35 ° C/W

70 ° C/W

7/44

Electrical data ST7540

3.3 Recommended operating conditions

Table 4. Recommended operating conditions

Symbol Parameter Test Condition Value Unit

V

CC

I(VCC)

- V

V

CC

DD

V

PA _O U T

I(PA_OUT)

Max allowed slope during
Power-up

Powered analog supply
Current with digital supply
provided externally

Maximum voltage
Difference between V

CC

and VDD during power-up
sequence

Output voltage swing for
PA_OUT pin

Maximum output
transmitting current in
programmable current
limiting

100 V/ms

Maximum total current 650 mArms

< 4.75V with 5V

V

DD

Digital supply provided

1.2 V

externally

-4.5 V

V

= 1.4kΩ; R

R

cl

LOAD

(as in Figure 17)

=1Ω

CC

500 mArms

PP

8/44

ST7540 Electrical characteristics

4 Electrical characteristics

Table 5. Electrical characteristics

(

VDD = +5V,

unless otherwise specified)

Symbol Parameter Test condition Min. Typ. Max. Unit

V

DD

VCC =+9 V,

V

SS

Digital supply voltages

= S

VSS = GND = 0V,-40°C ≤ TA ≤ 85°C, TJ < 125°C,

5V Digital supply
provided externally

4.75 5 5.25 V

I(V

V

CC

DD

Power supply voltage 7.5 13.5 V

Digital input supply

)

current

Power supply current

I(V

CC

current with digital

)

supply provided
externally

UVLO

UVLO

HYS

Under voltage lock out
Threshold on V

UVLO Hysteresis on
V

CC

Digital I/O

R

down

R

up

Internal pull down
resistor

Internal pull up resistor -30% 100 +30% kΩ

Digital I/O - 5V digital supply

CC

Transmission &
receiving mode
(MCLK = 4MHz),no load

Transmission &
Receiving mode
(MCLK = OFF), no load

TX mode, no load 60 mArms

RX mode 5 mArms

3.7 3.9 4.1 V

340 mV

-30% 100 +30% kΩ

3.5 mA

1.5 mA

V

IH

V

IL

V

OH

V

OL

High logic level input
voltage

Low logic level input
voltage

High logic level output
voltage

Low logic level output
voltage

Digital I/O - 3.3V digital supply

V

IH

V

IL

High logic level input
voltage

Low logic level input
voltage

2 V

1.2 V

-

V

I

I

OH

OL

= -2mA

= 2mA

DD

0.45

GND
+ 0.3

V

V

1.4 V

0.8 V

9/44

Electrical characteristics ST7540

Table 5. Electrical characteristics (continued)

(

VDD = +5V,

VCC =+9 V,

V

= S

VSS = GND = 0V,-40°C ≤ TA ≤ 85°C, TJ < 125°C,

SS

unless otherwise specified)

Symbol Parameter Test condition Min. Typ. Max. Unit

V

V

OH

V

OL

Oscillator

High logic level output
voltage

Low logic level output
voltage

IOH= -2mA

= 2mA

I

OL

DD

0.75

-

GND
+ 0.4

V

V

External Clock X2 voltage swing External clock. Figure 4 5

External Clock

X2 DC voltage level External clock. Figure 4 2.5 V

DC XTAL Clock duty cycle External clock. 40 60 %

Xtal

Xtal

ESR

Crystal oscillator
frequency

External oscillator esr
resistance

fundamental 16 MHz

External oscillator

Xtal

CL

stabilization

Figure 6 16 pF

capacitance

Transmitter

I

TX_OUT

V

TX_OUT

V

TX_OUTDC

HD2

TX_OUT

HD3

TX_OUT

G accuracy

Output transmitting
current on TX_OUT

Max carrier output AC
voltage

Output DC voltage on
TX_OUT

Second harmonic
distortion on TX_OUT

Third harmonic
distortion on TX_OUT

Accuracy on voltage
control loop active

= 1.4kΩ

R

CL

Vsense = 0V

TX_OUT

= 2VPP;

V
Fc = 86KHz, no load

TX_OUT

= 2VPP;

V
Fc = 86KHz, no load

= 0Ω

R

CL

1.75 2.3 3.5

1.7 2.1 2.5 V

-1 +1 GST

V

pp

40 Ω

1mArms

V

PP

-42

-49

dB

dB

c

c

G

ST

ALC gain step control
loop gain step

DRNG ALC dynamic range 30 dB

C

CL

Input capacitance on
CL pin

Voltage control loop

V

senseTH

reference threshold on

pin

V

sense

Figure 17 160 180 200

Hysteresis on voltage

V

senseHYST

loop reference

Figure 17 ±18 mV

threshold

10/44

0.6 1 1.4 dB

80 pF

mV

PK

ST7540 Electrical characteristics

Table 5. Electrical characteristics (continued)

(

VDD = +5V,

VCC =+9 V,

V

= S

VSS = GND = 0V,-40°C ≤ TA ≤ 85°C, TJ < 125°C,

SS

unless otherwise specified)

Symbol Parameter Test condition Min. Typ. Max. Unit

V

SENSE

CL

CL

T

RxTx

T

T

TH

HYST

ALC

ST

V

SENSE

Input

impedance

Current control loop
reference threshold on
CL pin

Hysteresis on current
loop reference
threshold

Carrier activation time

Carrier stabilization
time
from STEP 16 to zero
or from step 16 to step
31,

Tstep

36 kΩ

Figure 17 1.80 1.90 2.00 V

Figure 17 210 250 290 mV

Figure 21 - 600

Baud Xtal = 16MHz

Figure 21- 1200 Baud

Xtal = 16MHz

Figure 21- 2400 Baud

Xtal = 16MHz

Figure 21- 4800 Baud

Xtal = 16MHz

Figure 21

Xtal = 16MHz

Figure 21

Xtal = 16MHz

1.6 ms

800 µs

400 µs

200 µs

3.2 ms

200 µs

Power amplifier

PA

IN(Offset)

GBWP

R

IN

C

IN

CMRR

Input terminals
OFFSET

Gain bandwidth
product

Input resistance at
PA_IN+ and PA_IN­pins

Input capacitance at
PA_IN+ and PA_IN­pins

Common mode
rejection ratio

±18 mV

100 MHz

PA_IN+ vs. Vss

PA_IN- vs. Vss

PA_IN+ vs. Vss

PA_IN- vs. Vss

(1)

(1)

(1)

(1)

1 MΩ

1 MΩ

5pF

5pF

40 dB

11/44

Electrical characteristics ST7540

Table 5. Electrical characteristics (continued)

(

VDD = +5V,

VCC =+9 V,

V

= S

VSS = GND = 0V,-40°C ≤ TA ≤ 85°C, TJ < 125°C,

SS

unless otherwise specified)

Symbol Parameter Test condition Min. Typ. Max. Unit

HD2

HD3

Receiver

V

V

R

PA_ O U T

PA_ O U T

IN

IN

IN

Second harmonic
distortion on PA_OUT

V
V
R
Carrier frequency:

PA _O U T

= 12V

CC

LOAD

= 5.6V

= 30Ω

PP

,

-63

dB

86KHz

Figure 3

Third harmonic
distortion on PA_OUT
pin

PA _O U T

= 12V

CC

LOAD

= 5.6V

= 30Ω

V
V
R
Carrier frequency:

86KHz

PP

,

- 63

dB

Figure 3

Input sensitivity
(Normal Mode)

Input sensitivity
(High Sens.)

Input sensitivity (TxD
line forced to “1”)

0.5 2

250

V

BU

Maximum input signal 2

mV

µV

dB/

µVrms

V

rms

Input impedance 80 100 140 kΩ

Carrier detection
sensitivity

0.5 2

mV

(Normal Mode)

c

c

rms

rms

rms

Carrier detection

V

CD

sensitivity
(High Sensitivity Mode)

Carrier detection
sensitivity
(TxD forced to “1”)

V

BU

Band in Use Detection
Level

12/44

250

V

BU

83.5 86

µV

rms

dB/

µVrms

dB/

µVrms

ST7540 Electrical characteristics

Table 5. Electrical characteristics (continued)

(

VDD = +5V,

VCC =+9 V,

V

= S

VSS = GND = 0V,-40°C ≤ TA ≤ 85°C, TJ < 125°C,

SS

unless otherwise specified)

Symbol Parameter Test condition Min. Typ. Max. Unit

5V Voltage regulator

VDC

Linear regulator output
voltage

3.3V Voltage regulator

V

DD

Linear regulator output
voltage

Other functions

T

RSTO

T

T

T

T

T

T

OFFD

T

T

M

WD

WM

WO

OUT

OFF

CD

DCD

CLK

Reset time

Watch-dog pulse width See Figure 23 125 ns

Watch-dog pulse
period

Watch-dog time out See Figure 23 1.5 s

TX time out

Time Out OFF time Figure 22 125 ms

RxTx 0->1 vs. time out
delay

Carrier detection time
selectable by register

CD_PD Propagation
delay

Master clock output
selectable by register

0 < Io < 50mA

7.5V < V

CC

< 13.5V

0 < Io < 50mA

7.5V < V

CC

< 13.5V

See Figure 23;
Xtal = 16MHz

Minimum value.
See Figure 23

Maximum value.
See Figure 23

Control register bit 7
and bit 8

-5% 5.05 +5% V

-5% 3.3 +5% V

50 ms

250 ns

1490 ms

1
3

Figure 22 20 µs

Control register
bit 9 and bit10

Figure 14

500

1
3
5

µs
ms
ms
ms

Figure 14 300 500 µs

Control register
bit 15 and bit 16
See Ta bl e 1 2

fclock
fclock/2
fclock/4

off

MHz

s

BAUD Baud rate

Control register
bit 3 and bit 4
See Ta bl e 1 2

600
1200
2400
4800

Baud

13/44

Electrical characteristics ST7540

6

Table 5. Electrical characteristics (continued)
(

VDD = +5V,

VCC =+9 V,

V

= S

VSS = GND = 0V,-40°C ≤ TA ≤ 85°C, TJ < 125°C,

SS

unless otherwise specified)

Symbol Parameter Test condition Min. Typ. Max. Unit

Serial Interface

1667

T

B

Baud rate Bit Time
(1/BAUD)

Control register bit 3
and bit 4
(See Figure 13)

833

417

208

µs

Ts Setup time

T

H

T

CR

T

CC

T

DS

T

DH

T

CRP

1. Not tested, guaranteed by design

Hold time

CLR/T vs. REG_DATA
or RxTx

CLR/T vs. CLR/T

Setup time

Hold time

see Figures 8, 9, 10, 11
& 12

see Figures 8, 9, 10, 11
& 12

see Figures 8, 9, 10, 11
& 12

see Figures 8, 9, 10, 11
& 12

see Figures 8, 9, 10, 11
& 12

see Figures 8, 9, 10, 11
& 12

T

B

/4 TB/2

T

B

/4 TB/2

T

B

T

H

Figure 3. PLI configuration for PA_OUT distortions measurement

150 pF 100 pF

5 k

2.7 kΩ

Ω

5ns

2ns

/4

T

B

2*T

B

TB/2

PA_IN -

PA

V

AC

V

DC

10 kΩ

= 2Vpp
= 1.9 V

PA_IN +

14/44

Vcc

Vss

PA_OUT

1uF

30 Ω

D03IN142

Measurement point

ST7540 Crystal resonator and external clock

5 Crystal resonator and external clock

Figure 4. External clock waveform

X2

SWING

OFFSET

SVss

Figure 5. Crystal Resonator

32 pF 32 pF

X1 X2

Exter nal C loc k

D03IN1425A

External Clock

15/44

Functional description ST7540

6 Functional description

6.1 Carrier frequencies

ST7540 is a multi frequency device: eight programmable Carrier Frequencies are available
(see Ta bl e 6 ).
Only one Carrier can be used a time. The communication channel could be varied during
the normal working Mode to realize a multi frequency communication.
Selecting the desired frequency in the Control Register the Transmission and Reception
filters are accordingly tuned.

Table 6. Channels List

FCarrier F (KHz)

F0 60

F1 66

F2 72

F3 76

F4 82.05

F5 86

1. Default value

6.2 Baud rates

ST7540 is a multi Baud rate device: four Baud Rate are available (See Tab le 8 ).

Table 7. ST7540 mark and space tones frequency distance Vs. baud rate and deviation

Baud Rate [Baud]

600 600

1200

2400

4800

1. Frequency deviation

2. Deviation = ∆F / (Baud Rate)

3. Deviation 0.5 not allowed

4. Default value

F6 110

(1)

F7

(1)

∆F

(Hz)

600

1200

(4)

(4)

1200

2400

2400
4800

132.5

Deviation

(3)

1

0.5
1

0.5
1

0.5
1

(2)

16/44

ST7540 Functional description

6.3 Mark and space frequencies

Mark and Space Communication Frequencies are defined by the following formula:

F ("0") = FCarrier + [∆F]/2

F ("1") = FCarrier - [∆F]/2

∆F is the Frequency Deviation.

With Deviation = “0.5” the difference in terms of frequency between the mark and space
tones is half the Baudrate value (∆F=0.5*BAudrate). When the Deviation = “1” the difference
is the Baudrate itself (∆F= Baudrate). The minimal Frequency Deviation is 600Hz.

Table 8. ST7540 synthesized frequencies

Carrier

frequency

(KHz)

60

Baud

rate

600

1200

2400

4800

600

Exact frequency

Deviation

--

1 59733 60221 1 81706 82357

0.5 59733 60221

1 59408 60547 1 81380 82682

0.5 59408 60547

1 58757 61198 1 80892 83171

0.5 58757 61198

1 57617 62337 1 79590 84473

--

1 65755 66243 1 85775 86263

[Hz]

(Clock=16MHz)

“1” “0” “1” “0”

Carrier

frequency

(KHz)

82.05

Baud

rate

600

1200

2400

4800

600

Deviation

--

0.5 81706 82357

0.5 81380 82682

0.5 80892 83171

--

Exact frequency

[Hz]

(Clock=16MHz)

66

72

1200

2400

4800

600

1200

2400

4800

0.5 65755 66243
1200

1 65430 66569 1 85449 86589

86

0.5 65430 66569
2400

1 64779 67220 1 84798 87240

0.5 64779 67220
4800

1 63639 68359 1 83659 88379

-­600

1 71777 72266 1 109701 110352

0.5 71777 72266
1200

1 71452 72591 1 109375 110677

110

0.5 71452 72591
2400

1 70801 73242 1 108724 111165

0.5 70801 73242
4800

1 69661 74382 1 107585 112467

17/44

0.5 85775 86263

0.5 85449 86589

0.5 84798 87240

--

0.5 109701 110352

0.5 109375 110677

0.5 108724 111165

Functional description ST7540

Table 8. ST7540 synthesized frequencies

--

0.5 132161 132813

0.5 131836 133138

0.5 131348 133626

76

600

1200

2400

4800

-­600

1 75684 76335 1 132161 132813

0.5 75684 76335
1200

1 75358 76660 1 131836 133138

132.5

0.5 75358 76660
2400

1 74870 77148 1 131348 133626

0.5 74870 77148
4800

1 73568 78451 1 130046 134928

6.4 ST7540 Mains access

ST7540 can access the Mains in two different ways:

● Synchronous access

● Asynchronous access

The choice between the two types of access can be performed by means of Control
Register bit 14(see Tab le 1 2) and affects the ST7540 data flow in Transmission Mode as in
Reception Mode (for how to set the communication Mode, see Section 6.5).

In data transmission mode:

● Synchronous Mains access: on clock signal provided by ST7540 (CLR/T line) rising

edge, data transmission line (TxD line) value is read and sent to the FSK Modulator.
ST7540 manages the Transmission timing according to the BaudRate Selected.

● Asynchronous Mains access: data transmission line (TxD line) value enters directly to

the FSK Modulator. The Host Controller manages the Transmission timing (CLR/T line
should be neglected).

In data reception mode:

● Synchronous Mains access: on clock signal recovered by a PLL from ST7540 (CLR/T

line) rising edge, value on FSK Demodulator is read and put to the data reception line
(RxD line). ST7540 recovers the bit timing timing according to the BaudRate Selected.

● Asynchronous Mains access: Value on FSK Demodulator is sent directly to the data

reception line (RxD line). The Host Controller recovers the communication timing
(CLR/T line should be neglected).

18/44

ST7540 Functional description

6.5 Host processor interface

ST7540 exchanges data with the host processor through a serial interface.

The data transfer is managed by REG_DATA and RxTx Lines, while data are exchanged
using RxD, TxD and CLR/T lines.

Four are the ST7540 working modes:

● Data Reception

● Data Transmission

● Control Register Read

● Control Register Write

REG_DATA and RxTx lines are level sensitive inputs.

Table 9. Data and Control register access bits configuration

REG_DATA RxTx

Data Transmission 0 0

Data Reception 0 1

Control Register Read 1 1

Control Register Write 1 0

ST7540 features two type of Host Communication Interfaces:

● SPI

● UART

The selection can be done through the UART/SPI pin. If UART/SPI pin is forced to “0” SPI
interface is selected while if UART/SPI pin is forced to “1” UART interface is selected. The
type of interface affects the Data Reception by setting the idle state of RxD line. When
ST7540 is in Receiving mode (REG_DATA=”0” and RxTx =“1”) and no data are available on
mains (or RxD is forced to an idle state, i.e. with a conditioned Detection Method), the RxD
line is forced to “0” when UART/SPI pin is forced to ”0” or it is forced to “1” when UART/SPI
pin is forced to ”1”.

The UART interface allows to connect an UART compatible device while SPI interface
allows to connect an SPI compatible device. The allowed combinations of Host
Interface/ST7540 Mains Access are:

Table 10. Host interface / ST7540 mains access combinations

Host device

interface type

UART “1” Transmission X

UART “1” Reception X

SPI “0” Transmission X

SPI “0” Reception X

UART/SPI pin

Communication

mode

Asynchronous Synchronous

Mains access

19/44

Functional description ST7540

Figure 6. Synchronous and Asynchronous ST7540/Host Controller interfaces

UART/Asynchronous

Data Interface

RxD

TxD

RxTx

CLR/T

REG_DATA

ST7540Host Controller

ST7540 allows to interface the Host Controller using a five line interface (RxD,TxD,RxTx,
CLR/T, & REG_DATA) in case of Synchronous mains access or using a 3 line interface
(RxD,TxD & RxTx) in Asynchronous mains access. Since Control Register is not accessible
in Asynchronous mode, in this case REG_DATA pin must be tied to GND.

6.5.1 Communication between Host and ST7540

The Host can achieve the Mains access by selecting REG_DATA=”0” and the choice
between Data Transmission or Data Reception is performed by selecting RxTx line (if RxTx
=“1” ST7540 receives data from mains, if RxTx=”0” ST7540 transmits data over the mains).

SPI/Synchronous

Data Interface

D03IN1415

RxD

TxD

RxTx

CLR/T

REG_DATA

ST7540Host Controller

Communication between Host and ST7540 is different in Asynchronous and Synchronous
mode:

● Asynchronous mode:

In Asynchronous Mode, data are exchanged without any data Clock reference. The
host controller has to recover the clock reference in receiving Mode and control the Bit
time in transmission mode.

If RxTx line is set to “1” & REG_DATA=”0” (Data Reception), ST7540 enters in an Idle
State. After Tcc time the modem starts providing received data on RxD line.

If RxTx line is set to “0” & REG_DATA=”0” (Data Transmission), ST7540 enters in an
Idle State and transmission circuitry is switched on. After Tcc time the modem starts
transmitting data present on TxD line.

20/44

ST7540 Functional description

● Synchronous mode:

In Synchronous Mode ST7540 is always the master of the communication and provides
the clock reference on CLR/T line. When ST7540 is in receiving mode an internal PLL
recovers the clock reference. Data on RxD line are stable on CLR/T rising Edge.

When ST7540 is in transmitting mode the clock reference is internally generated and
TxD line is sampled on CLR/T rising Edge.

If RxTx line is set to “1” & REG_DATA=”0” (Data Reception), ST7540 enters in an Idle
State and CLR/T line is forced Low. After Tcc time the modem starts providing received
data on RxD line.

If RxTx line is set to “0” & REG_DATA=”0” (Data Transmission), ST7540 enters in an
Idle State and transmission circuitry is switched on. After Tcc time the modem starts
transmitting data present on TxD line (Figure 8) .

Figure 7. Receiving and transmitting data/recovered clock timing

Transmitting Bit Synchronization

CLR/T

RxD

Receiving Bit Synchronization

CLR/T

TxD

D03IN1416

Figure 8. Data reception -> data transmission -> data reception

CLR_T

RxD

REG_DATA

RxTx

TxD

T

CC

T

T

DS

DH

T

CR

TST

H

T

CC

T

CR

TST

H

T

B

D03IN1402

21/44

Functional description ST7540

6.5.2 Control register access

The communication with ST7540 Control Register is always synchronous. The access is
achieved using the same lines of the Mains interface (RxD, TxD, RxTx and CLR/T) plus
REG_DATA Line.

With REG_DATA = 1 and RxTx = 0, the data present on TxD are loaded into the Control
Register MSB first. The ST7540 samples the TxD line on CLR/T rising edges. The control
Register content is updated at the end of the register access section (REG_DATA falling
edge).

In Normal Control Register mode (Control Register bit 21 = ”0”, see Tab le 1 2 ) if more than
24 bits are transferred to ST7540 only latest 24 bits are stored inside the Control Register. If
less than 24 bits are transferred to ST7540 the Control Register writing is aborted.

In order to avoid undesired Control Register writings caused by REG_DATA line fluctuations
(for example because of surge or burst on mains), in Extended Control Register mode
(Control Register bit 21 = ”1” see Tab le 1 2 ) exactly 24 or 48 bits must be transferred to
ST7540 in order to properly write the Control Register, otherwise writing is aborted. If 24 bits
are transferred, only the first 24 Control Register bits (from 23 to 0) are written.

With REG_DATA = 1 and RxTx = 1, the content of the Control Register is sent on RxD port.
The Data on RxD are stable on CLR/T rising edges MSB First. In Normal Control Register
mode 24 bits are transferred from ST7540 to the Host. In Extended Control Register mode
24 or 48 bits are transferred from ST7540 to the Host depending on content of Control
Register bit 18 (with bit 18 = ”0” the first 24 bits are transferred, otherwise all 48 bits are
transferred, see Tab l e 1 2 ).

Figure 9. Data reception

CLR_T

TDST

DH

RxD

T

REG_DATA

RxTx

CR

Figure 10. data reception

CLR_T

RxD

REG_DATA

RxTx

TxD

TDHT

DS

T

CR

➨ control register read ➨ data reception timing diagram

T

CC

TDST

DH

BIT23 BIT22

➨ control register write ➨ data reception timing diagram

T

CC

T

CR

TST

H

BIT23 BIT22

T

CR

T

CC

T

B

T

CR

D03IN1404

T

CC

T

B

T

CR

D03IN1403

22/44

ST7540 Functional description

Figure 11. Data transmission ➨ control register read ➨ data reception timing diagram

CLR_T

RxD

T

CC

T

B

TDST

BIT23 BIT22

DH

T

CC

TDST

DH

REG_DATA

RxTx

TxD

TST

H

Figure 12. Data transmission

CLR_T

TxD

REG_DATA

RxTx

RxD

TST

T

B

H

6.6 Receiving mode

The receive section is active when RxTx Pin =”1” and REG_DATA=0.
The input signal is read on RX_IN Pin using SV
by a Band pass Filter (62kHz max bandwidth at -3dB). The Pre-Filter can be inserted setting
one bit in the Control Register. The Input Stage features a wide dynamic range to receive
Signal with a Very Low Signal to Noise Ratio. The Amplitude of the applied waveform is
automatically adapted by an Automatic Gain Control block (AGC) and then filtered by a
Narrow Band Band-Pass Filter centered around the Selected Channel Frequency (14kHz
max at -3dB). The resulting signal is down-converted by a mixer using a sinewave generated
by the FSK Modulator. Finally an Intermediate Frequency Band Pass-Filter (IF Filter)
improves the Signal to Noise ration before sending the signal to the FSK demodulator. The
FSK demodulator then send the signal to the RX Logic for final digital filtering. Digital
filtering Removes Noise spikes far from the BAUD rate frequency and Reduces the Signal
Jitter. RxD Line is forced to “0” or “1” (according the UART/SPI pin level) when neither mark
or space frequencies are detected on RX_IN Pin.
Mark and Space Frequency in Receiving Mode must be distant at least BaudRate/2 to have
a correct demodulation.
While ST7540 is in Receiving Mode (RxTx pin =”1”), the transmit circuitry, Power Line
Interface included, is turned off. This allows the device to achieve a very low current
consumption (5mA typ).

T

CR

T

CR

➨ control register write ➨ data reception timing diagram

T

CC

TST

H

BIT23 BIT22

T

CR

as ground reference and then pre-filtered

SS

T

CR

D03IN1405

T

CC

T

CR

T

CR

T

T

DS

DH

D03IN1401

23/44

Functional description ST7540

● Receiving Sensitivity Level Selection

It is possible to select the ST7540 Receiving Sensitivity Level by Control Register (see

Ta bl e 1 2) or setting to ‘1’ the TxD pin during reception phase (this condition overcomes

the control register setting the sensitivity equal to BU threshold). Increasing the device
sensitivity allows to improve the communication reliability when the ST7540 sensitivity
is the limiting factor.

● Synchronization Recovery System (PLL)

ST7540 embeds a Clock Recovery System to feature a Synchronous data exchange
with the Host Controller. The clock recovery system is realized by means of a second
order PLL. In Synchronous mode, data on the data line (RxD) are stable on CLR/T line
rising edge (CLR/T Falling edge synchronized to RxD line transitions ± LOCK-IN
Range). The PLL Lock-in and Lock-out Range is ±π/2. When the PLL is in the unlock
condition RxD line is forced to “0” or “1” according to the UART/SPI pin level and CLR/T
is forced to “0” only if the Detection Method “Preamble Detection With Conditioning” is
selected.When PLL is in unlock condition it is sensitive to RxD Rising and Falling
Edges. The maximum number of transition required to reach the lock-in condition is 5.
When in lock-in condition the PLL is sensitive only to RxD rising Edges to reduce the
CLR/T Jitter. ST7540 PLL is forced in the un-lock condition, when more than 32 equal
symbols are received.Due to the fact that the PLL, in lock-in condition, is sensitive only
to RxD rising edge, sequences equal or longer than 15 equal symbols can put the PLL
into the un-lock condition.

Figure 13. ST7540 PLL lock-in range

CLR/T

RxD

D03IN1417

LOCK-IN RANGE

● Carrier/Preamble Detection

The Carrier/Preamble Block is a digital Frequency detector Circuit.
It can be used to manage the MAINS access and to detect an incoming signal.
Two are the possible setting:

– Carrier Detection

– Preamble Detection

24/44

ST7540 Functional description

● Carrier Detection

The Carrier/Preamble detection Block notifies to the host controller the presence of a
Carrier when it detects on the RX_IN Input a signal with an harmonic component close
to the programmed Carrier Frequency. The CD_PD signal sensitivity is identical to the
data reception sensitivity (0.5mVrms Typ. in Normal Sensitivity Mode). When the
device sensitivity is set by the TxD line (Sensitivity level equal to BU threshold) the
CD_PD signal is conditioned to the BU signal.
The CD_PD line is forced to a logic level low when a Carrier is detected.

● Preamble Detection

The Carrier/Preamble detection Block notifies to the host controller the presence of a
Carrier modulated at the Programmed Baud Rate for at least 4 Consecutive Symbols
(“1010” or “0101” are the symbols sequences detected).
CD_PD line is forced low till a Carrier signal is detected and PLL is in the lock-in range.

To reinforce the effectiveness of the information given by CD_PD Block, a digital
filtering is applied on Carrier or Preamble notification signal (see Section 6.8: Control

register). The Detection Time Bits in the Control Register define the filter performance.

Increasing the Detection Time reduced the false notifications caused by noise on main
line. The Digital filter adds a delay to CD_PD notification equal to the programmed
Detection Time. When the carrier frequency disappears, CD_PD line is held low for a
period equal to the detection time and then forced high. During this time, some
spurious data caused by noise can be demodulated and sent over RxD line.

● Header Recognition

In Control Register Extended Mode (Control Register bit 21=”1”, see Ta bl e 1 2) the
CD_PD line can be used to recognize if an header has been sent during the
transmission. With Header Recognition function enable (Control Register bit 18=”1”,
see Ta bl e 1 2), CD_PD line is forced low when a Frame Header is detected. If Frame
Length Count function is enabled, CD_PD is held low and a number of 16 bit word
equal to the Frame Length selected is sent to the host controller. In this case, CLR/T is
forced to “0” and RxD is forced to “0” or “1” (according the UART/SPI pin level) when
Header has not been detected or after the Frame Length has been reached.
If Frame Length Count function is disabled, an header recognition is signaled by forcing
CD_PD low for one period of CLR/T line. In this case, CLR/T and RxD signal are
always present, even if no header has been recognized.

25/44

Functional description ST7540

8

Figure 14. CD_PD Timing during RX

CD_PD

RX_IN

RxD (UART/SPI="1")

T

DCD

T

CD

demodulation active on RxD pin

T

DCD

noise demodulated

T

CD

RxD (UART/SPI="0")

Figure 15. Receiving path block diagram

RxD

CLR/T

CD_PD

BU/THERM

4

Bits 3-4 &14

8

Bit s 18-21 &

24-47

HEADER

1

RECOGN.

7

PLL

Bits 3-4

Low Pass Band Pass

DIGITAL

FILTER

Bits 9-10

Low Pass

Bits 3-4 & 22

FSK

DEMODULATOR

Bits 12-13 & 22

CARRIER/
PREAMBLE
DETECTION

IF FILTER

Bits 0-2

MIXER

Band Pass

CHANNEL

LOCAL

Bits 0 -2

Carrier Detection

FILTER

OSC

noise demodulated

AGC

GAIN

CONTROL

BAND

IN

USE

D03IN141

Bit 23

Band Pass

PRE-FILTER

D03IN1419

25

RX_IN

6.7 Transmission mode

The transmission mode is set when RxTx Pin =”0” and REG_DATA Pin =”0”. In transmitting
mode the FSK Modulator and the Power Line Interface are turned ON. The transmit Data
(TxD) enter synchronously or asynchronously to the FSK modulator.

● Synchronous Mains access: on CLR/T rising edge, TxD Line Value is read and sent to

the FSK Modulator. ST7540 manages the Transmission timing according to the
BaudRate Selected

● Asynchronous Mains access: TxD data enter directly to the FSK Modulator.The Host

Controller manages the Transmission timing

In both conditions no Protocol Bits are added by ST7540.

The FSK frequencies are synthesized in the FSK modulator from a 16 MHz crystal oscillator
by direct digital synthesis technique. The frequencies Table in different Configuration is
reported in Ta bl e 8 . The frequencies precision is same as external crystal one’s.

26/44

ST7540 Functional description

In the analog domain, the signal is filtered in order to reduce the output signal spectrum and
to reduce the harmonic distortion. The transition between a symbol and the following is done
at the end of the on-going half FSK sinewave cycle.

Figure 16. Transmitting path block diagram

Bits 7-8

TxD

CLR/T

7

6

D-TYPE

FLOP

8

BU/THERM

● Automatic Level Control (ALC)

Bit 14

FLIP

CLR/T GENERATOR

THERMAL

SENSOR

Bits 0-5

FSK

MODULATOR

TIMER

Bits 0-2

DAC

Band Pass

TRANSMISSION

FILTER

ALC

Bits 17 & 21

VOLTAGE

LOOP

CURRENT

LOOP

+

PA

-

D03IN1420

The Automatic Level Control Block (ALC) is a variable gain amplifier (with 32 non linear
discrete steps) controlled by two analog feed backs acting at the same time. The ALC
gain range is 0dB to 30 dB and the gain change is clocked at 5KHz. Each step
increases or reduces the voltage of 1dB (Typ).
Two are the control loops acting to define the ALC gain:

– A Voltage Control loop

– A Current Control Loop

The Voltage control loop

acts to keep the Peak-to-Peak Voltage constant on Vsense.
The gain adjustment is related to the result of a peak detection between the Voltage
waveform on Vsense and two internal Voltage references. It is possible to protect the
Voltage Control Loop against noise by freezing the output level (see Section 7.5:

Output voltage level freeze).

23

24

15

14

18

19

Vsense

CL

PA_OUT

PA_IN-

PA_IN+

TX_OUT

– If Vsense < Vsense

–If Vsense

- Vsense

TH

– If Vsense > Vsense

- Vsense

TH

< Vsense < VsenseTH + Vsense

HYST

+ Vsense

TH

The next gain level is increased by 1 step

HYST

The next gain level is decreased by 1 step

HYST

27/44

No Gain Change

HYST

Functional description ST7540

The Current control loop acts to limit the maximum Peak Output current inside
PA _O U T.
The current control loop acts through the voltage control loop decreasing the Output
Peak-to-Peak Amplitude to reduce the Current inside the Power Line Interface.
The current sensing is done by mirroring the current in the High side MOS of the Power
Amplifier (not dissipating current Sensing). The Output Current Limit (up to 500mrms),
is set by means of an external resistor (R

) connected between CL and VSS. The

CL

resistor converts the current sensed into a voltage signal. The Peak current sensing
block works as the Output Voltage sensing Block:

–If V(CL) < CL

–If CL

TH

- CL

–If V(CL) > CL

- CL

TH

< V(CL) < CLTH + CL

HYST

+ CL

TH

Voltage Control Loop Acting

HYST

The next gain level is decreased by 1 step

HYST

No Gain Change

HYST

Figure 17 shows the typical connection of Current anVoltage control loops.

Figure 17. Voltage and current feedback external interconnection example

ALC

VOLTAGE

LOOP

CURRENT

LOOP

Voltage Control Loop Formula

V

OUTPK

80pF typ.

D03IN1421

R1R2+

--------------------

R

2

PA_OUT/TX_OUT

Vsense

10nF

CL

RCL

AVss

Vsense

R1

R2

TH

Vout

Vsense

±()⋅≅

HYST

Vout

Vsense

Vsense

PK

TH

HYST

1.865V (Typ)

VCL

HYST

VCL

TH

28/44

ST7540 Functional description

Table 11. V

Vout (Vr m s ) Vou t ( d B µV) (R1+R2)/R2 R2 (KΩ) R1 (KΩ)

0.150 103.5 1.1 7.5 1.0

0.250 108.0 1.9 5.1 3.9

0.350 110.9 2.7 3.6 5.6

0.500 114.0 3.7 3.3 8.2

0.625 115.9 4.7 3.3 11.0

0.750 117.5 5.8 2.7 12.0

0.875 118.8 6.6 2.0 11.0

1.000 120.0 7.6 1.6 10.0

1.250 121.9 9.5 1.6 13.0

1.500 123.5 10.8 1.6 15.0

Vs. R1 & R2 resistors value

OUT

Note: Notes: The rate of R2 takes in account the input resistance on the V

capacitor effect has been neglected.

Figure 18. Typical output current vs RCL

Irms

(mA)

1220
1120
1020

920
820
720
620
520
420
320
220
120

0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1

● Integrated Power Line Interface (PLI)

The Power Amplifier (PA) is a CMOS AB Class Power Amplifier. The PA requires, to
ensure a proper

operation, a regulated and well filtered Supply Voltage. Vcc Voltage and PA_OUT
Voltage must fulfil

the following formulas to work without clipping phenomena:

pin (36KΩ). 10nF

SENSE

D01IN1311

Rcl(kΩ)

VPAOUT AC()

V

--------------------------------------- - VPOUT DC()3V++≥

CC

VPOUT DC()

2

VPAOUT AC()

--------------------------------------- -

2

1.5V≥–

29/44

Functional description ST7540

Figure 19. PA_OUT and V

relationship

CC

V

Vcc

≤

3V

V

PA_OUT(AC)

≤

1.5V

V

PA_OUT(DC)

Vss

t

D03IN1425

Inputs and outputs of PA are available on pins PA_IN-,PA_IN+ and PA_OUT. User can easily
select an appropriate active filtering topology to filter the signal present on TX_OUT pin.
TX_OUT output has a current capability much lower than PA_OUT.

30/44

ST7540 Functional description

Figure 20. Power line interface topology

Vcc

PA_IN-

ALC

-

+

VOLTAGE

LOOP

CURRENT

LOOP

80pF typ.

D03IN1422

PA_OUT

PA_IN+

TX_OUT

Vss

Vsense

CL

R3

R4

RCL

Figure 21. Power line interface startup timing diagram

RxTx

T

ALC

Z2

Z1

AC LINE

R1

R2

TX_OUT

T

RXTX

T

ST

2.1V

0V

STEP NUMBER 16 17 18 31

D03IN1408

31/44

Functional description ST7540

6.8 Control register

The ST7540 is a multi-channel and multifunction transceiver. An internal 24 or 48 Bits (in
Extended mode) Control Register allows to manage all the programmable parameters
(Ta bl e 1 2).
The programmable functions are:

● Channel Frequency

● Baud Rate

● Deviation

● Watchdog

● Transmission Timeout

● Frequency Detection Time

● Detection Method

● Mains Interfacing Mode

● Output Clock

● Sensitivity Mode

● Input Pre-Filter

In addition to these functions the Extended mode provides 24 additional bits and others
functions:

● Output Level Freeze

● Frame Header Recognizes (one 16 bits header of or two 8 bits headers) with support to

Frame Length Bit count

32/44

ST7540 Functional description

Table 12. Control register functions

Function Value Selection Note Default

Bit2 Bit1 Bit0

0 to 2 Frequencies

3 to 4 Baud rate

5Deviation

60 KHz
66 KHz
72 KHz
76 KHz

82.05 KHz
86 KHz

110 KHz

132.5 KHz

600
1,200
2,400
4,800

0.5
1

0

0

0

0

0

1

0

1

1

0

1

0

1

1

1

1

Bit 4 Bit 3

0
0
1
1

0
1
0
1

Bit 5

0
1

0
1
0
1
0
1
0
1

132.5 kHz

2400

0.5

Bit 6

6 Watchdog

7 to 8

9 to 10

11 Reserved Do not force a different value 0

Transmission

time out

Frequency

detection time

Disabled

Enabled (1.5 s)

Disabled

1 s
3 s

Not Used

500 µs

1 ms
3 ms
5 ms

0
1

Bit 8 Bit 7

0
0
1
1

Bit 10 Bit 9

0
0
1
1

0
1
0
1

0
1
0
1

Enabled

1 sec

1 ms

33/44

Functional description ST7540

Table 12. Control register functions

Function Value Selection Note Default

Bit 13 Bit 12

Preamble detection
notification on CD_PD Line

12 to 13

Detection

method

Preamble detection
without conditioning

Preamble detection
with conditioning

Carrier detection
without conditioning

00

01

10

CLR/T and RxD signal always
present In UART Mode
(UART/SPI pin set to 1) this
configuration is not allowed.

Preamble Detection
notification on CD_PD Line.
CLR/T and RxD line are
forced to "0" when Preamble
has not been detected or PLL
is in Unlock condition. In
UART Mode (UART/SPI pin
set to 1) this configuration is
not allowed.

Carrier detection notification
on CD_PD Line
CLR/T and RxD signal always
present

Carrier

detection

without

conditioning

Mains

14

15 to 16 Output Clock

17

18

19

Interfacing

Mode

Output

Voltage Level

Freeze

Header

Recognition

Frame Length

Count

Carrier detection
with conditioning

Synchronous

Asynchronous

16 MHz

8 MHz
4 MHz

Clock OFF

Enabled
Disabled

Disabled
Enabled

Disabled
Enabled

Carrier detection notification
on CD_PD Line
CLR/T Line is forced to “0”

11

Bit 14

0
1

Bit 16 Bit 15

0
0
1
1

Bit 17

0
1

Bit 18

0
1

Bit 19 Active only if header

0
1

and RxD Line is forced to “0”
or “1” (according the
UART/SPI pin level) when
carrier is not detected

0
1
0
1

Active only if extended control
register is enable (Bit 21=”1”)

Active only if extended control
register is enable (Bit 21=”1”)

recognition function (Bit
18=”1”) and extended control
register (Bit 21=”1”)
are enable

Asynchronous

4 MHz

Disabled

Disabled

Disabled

34/44

ST7540 Functional description

Table 12. Control register functions

Function Value Selection Note Default

Bit 20

Active only if Extended
Control Register is enable (Bit
21=”1”)

Extended Register enables
Functions on Bit 17, 18,19 and
20

16 bits

Disabled

(24 bits)

20

21

Header

Length

Extended

Register

8 bits

16 bits

Disable (24 bits)

Enabled (48 bits)

0
1

Bit 21

0
1

Bit 22

22

23 Input Filter

24 to 39

40 to 47 Frame Length from 01h to FFh

Sensitivity

Mode

Frame

Header

Normal Sensitivity

High Sensitivity

Disabled
Enabled

from 0000h to

FFFFh

0
1

Bit 23

0
1

One 16 bits Header or two 8
bits Headers (MSB first)
depending on Bit 20

Number of 16 bits words
expected

Normal

Disabled

9B58h

08h

35/44

Auxiliary analog and digital functions ST7540

7 Auxiliary analog and digital functions

7.1 Band in use

The Band in Use Block has a Carrier Detection like function but with a different Input
Sensitivity (83.5 dBµV Typ.) and with a different BandPass filter Selectivity (40dB/Dec).

BU/THERM line is forced High when a signal in band is detected.
To prevent BU/THERM line false transition, Band in Use signal is conditioned to Carrier
Detection Internal Signal. This function is enabled only in Receiving mode (in Transmission
mode the BU/THERM pin is used for Thermal shutdown signaling, see Section 7.8: Thermal

shutdown).

7.2 Time out

Time Out Function is a protection against a too long data transmission. When Time Out
function is enabled after 1 or 3 second of continuos transmission the transceiver is forced in
receiving mode. This function allows ST7540 to automatically manage the CENELEC
Medium Access specification. When a time-out event occur, the transmission section is
disabled for at least 125 ms. To Unlock the Time Out condition RxTx should be forced High.
During the time out period only register access or reception mode are enabled.

During Reset sequence if RxTx line =”0” & REG_DATA line =”0”, Time Out protection is
suddenly enabled and ST7540 must be configured in data reception after the reset event
before starting a new data transmission.
Time Out time is programmable using Control Register bits 7 and 8 (Ta b le 1 2 ).

Figure 22. Time-out timing and unlock sequence

RxTx

Time Out function

T

OUT

T

OFFTOFFD

D03IN1409

36/44

ST7540 Auxiliary analog and digital functions

7.3 Reset & watchdog

RSTO Output is a reset generator for the application circuitry. During the ST7540 startup
sequence is forced low. RSTO becomes high after a T
startup sequence.
Inside ST7540 is also embedded a watchdog function. The watchdog function is used to
detect the occurrence of a software fault of the Host Controller. The watchdog circuitry
generates an internal and external reset (RSTO low for T
watchdog timer. The watchdog timer reset can be achieved applying a negative pulse on
WD pin (see Figure 23).

Figure 23. Reset and Watchdog Timing

delay from the end of oscillator

RSTO

time) on expiry of the internal

RSTO

T

RSTO

RSTO

WD

T

WM

T

WD

7.4 Output clock

MCLK is the master clock output. The clock frequency sourced can be programmed through
the Control Register to be a ratio of the crystal oscillator frequency (Fosc, Fosc/2 Fosc/4).
The transition between one frequency and another is done only at the end of the ongoing
cycle. The oscillator can be disabled using Control Register bits 15 and 16 (Ta bl e 1 2).

7.5 Output voltage level freeze

The Output Level Freeze function, when enabled, turns off the Voltage Control Loop once
the ALC stays in a stable condition for about 3 periods of control loop, and maintains a
constant gain until the end of transmission. Output Level Freeze can be enabled using
Control Register bit 17 (Ta bl e 1 2 ). This function is available only using the Extended Control
Register (Control Register bit 21=”1”).

T

WO

T

RSTO

D03IN1410

7.6 Extended control register

When Extended Control Register function is enabled, all the 48 bits of Control Register are
programmable. Otherwise, only the first 24 bits of Control Register are programmable. The
functions Header Recognition, Frame Bit Count and Output Voltage Freeze are available
only if Extended Control Register function is enabled. Extended Control Register can be
enabled using Control Register bit 21(Tab le 1 2 ).

37/44

Auxiliary analog and digital functions ST7540

7.7 Under voltage lock out

The UVLO function turns off the device if the VCC voltage falls under 4V. Hysteresis is
340mV typically.

7.8 Thermal shutdown

The ST7540 is provided of a thermal protection which turn off the PLI when the junction
temperature exceeds 170°C ±10% . Hysteresis is around 30°C.

When shutdown threshold is overcome, PLI interface is switched OFF.

Thermal Shutdown event is notified to the HOST controller using BU/THERM line. When
BU/THERM line is High, ST7540 junction temperature exceed the shutdown threshold (Not
Latched). This function is enabled only in Transmission mode (in Receiving mode the
BU/THERM pin is used for Band in Use signaling, see Band in Use function Section 7.1:

Band in use).

7.9 5V Voltage regulator

ST7540 has an embedded 5V linear regulator externally available (on pin VDC) to supply
the application circuitry. The 5V linear regulator has a very low quiescent current (50µA) and
a current capability of 50mA. The regulator is protected against short circuitry events.

7.10 3.3V Voltage regulator

The VDD pin can act either as 3.3V Voltage Output or as Input Digital Supply. When the VDD
pin is externally forced to 5V all the Digital I/Os operate at 5V, otherwise all the Digital I/Os
are internally supplied at 3.3V. The V
components. The 3.3V linear regulator has a very low quiescent current (50µA) and a
current capability of 50mA. The regulator is protected against short circuitry events.

7.11 Power-up procedure

To ensure ST7540 proper power-Up sequence, VCC and VDD Supply has to fulfil the
following rules:

1. V

2. When V

When V
can be ignored if VDC load < 50mA and if the filtering capacitor on VDC < 100uF.

If V
50mA and the filtering capacitor on V

rising slope must not exceed 100V/ms.

CC

is below 5V/3.3V: VCC-VDD < 1.2V.

DD

supply is connected to VDC (5V Digital Supply) the above mentioned relation

DD

is not forced to 5V, the Digital I/Os are internally supplied at 3.3 V and if VDD load <

DD

pin can also source 3.3V voltage to supply external

DD

< 100uF the second relation can be ignored .

DD

38/44

ST7540 Auxiliary analog and digital functions

Figure 24. Power-up sequence

CC-VDD

V

Voltage

5V/3.3V

V

CC

V

DD

D03IN1424

Time

39/44

Auxiliary analog and digital functions ST7540

Figure 25. Application schematic example with coupling transformer.

AC/DC

Converter

SINGLE SUPPY

CC

V

17

20

SVss

No External Components

for POWER LINE DRIVER

Z1

Z2

PA_IN-

14

PA_OUT

PA_IN+

15

18

RX_IN

25

AC LINE

R3

TX_OUT

19

R4

R1

VSS

16

C1

Vsense

23

R2

Voltage

Regulation

&

CL

Current

Protection

RCL

24

D03IN1412A

X222X1_OSCIN

21

12

UART/SPI

26

VDC

5V Supply

9

DD

V

for Host Controller

28

TEST227TEST1

13

WD

40/44

ST7540

7

BU/THERM

HOST

1

CD/PD

CONTROLLER

RxD

456

TxD

RxTx

8

CLR/T

REG/DATA

2

5 Lines

Serial Interface

10

MCLK

3

11

RSTO

Clock & Reset for

GND

Host Controller

ST7540 Mechanical data

8 Mechanical data

In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect . The category of
second level interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com

41/44

Mechanical data ST7540

Table 13. HTSSOP28 Mechanical data

mm. inch

Dim.

Min. Typ. Max. Min. Typ. Max.

A 1.2 0.047

A1 0.15 0.006

A2 0.8 1.0 1.05 0.031 0.039 0.041

b 0.19 0.3 0.007 0.012

c 0.09 0.2 0.003 0.008

D (*) 9.6 9.7 9.8 0.377 0.382 0.385

D1 3.3 0.130

E 6.2 6.4 6.6 0.244 0.252 0.260

E1 (*) 4.3 4.4 4.5 0.169 0.173 0.177

E2 1.5

e 0.65 0.026

L 0.45 0.6 0.75 0.018 0.024 0.029

L1 1.0 0.039

k 0° (min), 8° (max)

aaa 0.1 0.004

Figure 26. Package dimensions

42/44

ST7540 Revision history

9 Revision history

Table 14. Revision history

Date Revision Changes

15-Mar-2006 1 Initial release.

25-Sep-2006 2 Updated Electrical Characteristics and Power Amplifier description

43/44

ST7540

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