ST ST7540 User Manual

General features

■ Half-duplex frequency shift keying (FSK)

transceiver

■ Integrated power line driver with programmable

voltage and current control

■ Programmable mains access:

– Synchronous
– Asynchronous

■ Single supply voltage (from 7.5V up to 13.5V)

■ Very low power consumption (I

■ Integrates 5V voltage regulator (up to 50mA)

with short circuit protection

■ Integrated 3.3V voltage regulator (up to 50mA)

with short circuit protection

■ 3.3V or 5V digital supply

■ 8 Programmable transmission frequencies

■ Programmable baud rate up to 4800BPS

■ Receiving sensitivity up to 250µV

■

Suitable for applications in accordance with EN
50065 Cenelec specification

■ Carrier or preamble detection

■ Band in use detection

■ Programmable control register

■ Watchdog timer

■ 8 or 16 Bit header recognition

■ ST7537 and ST7538 compatible

■ UART/SPI host interface

= 5mA)

q

RMS

ST7540

FSK power line transceiver

HTSSOP28 Exposed Pad

Description

The ST7540 is a Half Duplex
synchronous/asynchronous FSK Modem
designed for power line communication network
applications. It operates from a single supply
voltage and integrates a line driver and two linear
regulators for 5V and 3.3V. The device operation
is controlled by means of an internal register,
programmable through the synchronous serial
interface. Additional functions as watchdog, clock
output, output voltage and current control,
preamble detection, time-out and band in use are
included. Realized in Multipower BCD5
technology that allows to integrate DMOS, Bipolar
and CMOS structures in the same chip.

Order codes

Part number Package Packaging

ST7540 HTSSOP28 (Exposed Pad) Tube

ST7540TR HTSSOP28 (Exposed Pad) Tape and reel

September 2006 Rev 2 1/44

www.st.com

44

Contents ST7540

Contents

1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.1 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3.1 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3.3 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

5 Crystal resonator and external clock . . . . . . . . . . . . . . . . . . . . . . . . . . 15

6 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

6.1 Carrier frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

6.2 Baud rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

6.3 Mark and space frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

6.4 ST7540 Mains access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

6.5 Host processor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

6.5.1 Communication between Host and ST7540 . . . . . . . . . . . . . . . . . . . . . 20

6.5.2 Control register access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

6.6 Receiving mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

6.7 Transmission mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

6.8 Control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

2/44

ST7540 Contents

7 Auxiliary analog and digital functions . . . . . . . . . . . . . . . . . . . . . . . . . 36

7.1 Band in use . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

7.2 Time out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

7.3 Reset & watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

7.4 Output clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

7.5 Output voltage level freeze . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

7.6 Extended control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

7.7 Under voltage lock out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

7.8 Thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

7.9 5V Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

7.10 3.3V Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

7.11 Power-up procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

8 Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

3/44

Block diagram ST7540

1 Block diagram

Figure 1. Block diagram

TEST2

TEST1 BU/THERM

CD/PD

RxD

CLR/T

UART/SPI

REG/DATA

RxTx

TxD

SERIAL

INTERFACE

OSC

X1 WD

X2

CARRIER

DETECTION

PLL

TIME BASE

RSTO MCLK

DIGITAL

FILTER

CONTROL

REGISTER

FSK

MODULATOR

FSK

DEMOD

DAC

TEST

VREG

GND

IF

FILTER

FILTER

V

DD

BU

FILTER

TX

VREG

SV

ALC

PA_IN+

Vdc

SS

AGC

AMPL

CURRENT
CONTROL

VOLTAGE

CONTROL

PA_IN-

FILTER

+

-

PA

RX_IN

CL

Vsense

TX_OUT

CC

V

PA_OUT

V

SS

D03IN1407A

4/44

ST7540 Pin settings

2 Pin settings

2.1 Pin connection

Figure 2. Pin connection (top view)

REG_DATA

BU/THERM

UART/SPI

2.2 Pin description

CD_PD

GND

RxD

RxTx

TxD

CLR/T

V

DD

MCLK

RSTO

WD

PA_IN-

1

2

3

4

5

6

7

8

9

10

11

12

13

14

28

27

26

25

24

23

22

21

20

19

18

17

16

15

TEST2

TEST1

VDC

RX_IN

CL

Vsense

X2

X1_OSCIN

SS

SV

TX_OUT

PA_IN+

CC

V

V

SS

PA_OUT

Table 1. Pin description

N° Name Type Description

Carrier, preamble or frame header detect output.

1 CD_PD Digital/Output

2REG_DATA

3 GND Supply Digital ground

4 RxD Digital/Output RX data output.

5 RxTx

6TxD

Digital/Input
with internal pull-down

Digital/Input
with internal pull-up

Digital/Input
with internal pull-down

"1" No carrier, preamble or frame header detected
"0" Carrier, preamble or frame header detected

Mains or control register access selector
"1" - Control register access
"0" - Mains access

Rx or Tx mode selection input.
"1" - RX Session
"0" - TX Session

TX data input.

5/44

Pin settings ST7540

Table 1. Pin description (continued)

N° Name Type Description

Band in use/Thermal Shutdown event detection output.
In Rx mode:
"1" Signal within the programmed band

7 BU/THERM Digital/Output

8 CLR/T Digital/Output

9

V

DD

Supply/Power Digital supply voltage or 3.3V voltage regulator output

10 MCLK Digital/Output Master clock output

11 RSTO Digital/Output Power ON or watchdog reset output

"0" No signal within the programmed band
In Tx mode:
"1" - Thermal Shutdown event occurred
"0" - No Thermal Shutdown event occurred
(signal not latched)

Synchronous mains access clock or
control register access clock

Interface type:
“0” - Serial peripheral interface
“1” - UART interface

Watchdog input. The internal watchdog counter is
cleared on the falling edges.

12 UART/SPI

13 WD

Digital/Input
with internal pull-down

Digital/Input
with internal pull-up

14 PA_IN- Analog/Input Power line amplifier inverting input

15 PA_OUT Power/Output Power line amplifier output

16

17

V

SS

V

CC

Supply Power analog ground

Supply Power supply voltage

18 PA_IN+ Analog/Input Power line amplifier not inverting input

19 TX_OUT Analog/Output Small signal analog transmit output

20

SV

SS

Supply Analog signal ground

21 X1 Analog/Output Crystal oscillator output

22 X2 Analog/Input Crystal oscillator input - or external clock input

SENSE

(1)

Analog/Input Output voltage sensing input for the voltage control loop

23

V

Current limiting feedback.

24

CL

(2)

Analog/Input

A resistor between CL and SVSS sets the PLI current
limiting value. An integrated 80pF filtering input

capacitance is present on this pin.

25 RX_IN Analog/Input Receiving analog input

26 VDC Power 5V voltage regulator output

27 TEST1

Digital/Input
with internal pull-down

28 TEST2 Analog/Input

1. Cannot be left floating

2. Cannot be left floating

6/44

Test input. Must be connected to GND.

Test input. Must be connected SV

SS

ST7540 Electrical data

3 Electrical data

3.1 Maximum ratings

Table 2. Absolute maximum ratings

Symbol Parameter Value Unit

V

CC

V

DD

SVSS/GND Voltage between SVSS and GND

Power supply voltage -0.3 to + 14 V

Digital supply voltage -0.3 to +5.5 V

-0.3 to +0.3 V

V

I

V

O

I

O

,

V

sense

X2,PA_IN-

,PA_IN+, CL

Digital input voltage

Digital output voltage

GND - 0.3 to V

GND - 0.3 to V

Digital output current -2 to +2 mA

Voltage range at Vsense, X2, PA_IN-, PA_IN+, CL
Inputs

SVSS - 0.3 to 5.6

DD

DD

+0.3

+0.3

RX_IN Voltage range at RX_IN input -5.6 to 5.6 V

TX_OUT, X1 Voltage range at TX_OUT, X1 outputs

PA_OUT Voltage range at powered PA_OUT Output

I(PA_OUT)

T

A

T

STG

RxD,

PA _ OU T Pi n

Power line driver output current

Operating ambient temperature -40 to +85 °C

Storage temperature -50 to 150 °C

Maximum withstanding voltage range
Test condition: CDF-AEC-Q100-002- “Human

(1)

SVSS - 0.3 to 5.6

V

- 0.3 to +VCC +0.3

SS

650 mArms

±1750 V

Body Model”

Other pins ±2000 V

1. This current is intended as not repetitive pulse current

Acceptance criteria: “Normal Performance”

V

V

V

V

V

3.2 Thermal data

Table 3. Thermal data

Symbol Parameter

R

thJA1

R

thJA2

1. Mounted on Multilayer PCB with a dissipating surface on the bottom side of the PCB

2. It is the same condition of the point above, without any heatsinking surface on the board.

Maximum thermal resistance junction-ambient steady

(1)

state

Maximum thermal resistance junction-ambient Steady

(2)

State

HTSSOP28

Exposed Pad

Unit

35 ° C/W

70 ° C/W

7/44

Electrical data ST7540

3.3 Recommended operating conditions

Table 4. Recommended operating conditions

Symbol Parameter Test Condition Value Unit

V

CC

I(VCC)

- V

V

CC

DD

V

PA _O U T

I(PA_OUT)

Max allowed slope during
Power-up

Powered analog supply
Current with digital supply
provided externally

Maximum voltage
Difference between V

CC

and VDD during power-up
sequence

Output voltage swing for
PA_OUT pin

Maximum output
transmitting current in
programmable current
limiting

100 V/ms

Maximum total current 650 mArms

< 4.75V with 5V

V

DD

Digital supply provided

1.2 V

externally

-4.5 V

V

= 1.4kΩ; R

R

cl

LOAD

(as in Figure 17)

=1Ω

CC

500 mArms

PP

8/44

ST7540 Electrical characteristics

4 Electrical characteristics

Table 5. Electrical characteristics

(

VDD = +5V,

unless otherwise specified)

Symbol Parameter Test condition Min. Typ. Max. Unit

V

DD

VCC =+9 V,

V

SS

Digital supply voltages

= S

VSS = GND = 0V,-40°C ≤ TA ≤ 85°C, TJ < 125°C,

5V Digital supply
provided externally

4.75 5 5.25 V

I(V

V

CC

DD

Power supply voltage 7.5 13.5 V

Digital input supply

)

current

Power supply current

I(V

CC

current with digital

)

supply provided
externally

UVLO

UVLO

HYS

Under voltage lock out
Threshold on V

UVLO Hysteresis on
V

CC

Digital I/O

R

down

R

up

Internal pull down
resistor

Internal pull up resistor -30% 100 +30% kΩ

Digital I/O - 5V digital supply

CC

Transmission &
receiving mode
(MCLK = 4MHz),no load

Transmission &
Receiving mode
(MCLK = OFF), no load

TX mode, no load 60 mArms

RX mode 5 mArms

3.7 3.9 4.1 V

340 mV

-30% 100 +30% kΩ

3.5 mA

1.5 mA

V

IH

V

IL

V

OH

V

OL

High logic level input
voltage

Low logic level input
voltage

High logic level output
voltage

Low logic level output
voltage

Digital I/O - 3.3V digital supply

V

IH

V

IL

High logic level input
voltage

Low logic level input
voltage

2 V

1.2 V

-

V

I

I

OH

OL

= -2mA

= 2mA

DD

0.45

GND
+ 0.3

V

V

1.4 V

0.8 V

9/44

Electrical characteristics ST7540

Table 5. Electrical characteristics (continued)

(

VDD = +5V,

VCC =+9 V,

V

= S

VSS = GND = 0V,-40°C ≤ TA ≤ 85°C, TJ < 125°C,

SS

unless otherwise specified)

Symbol Parameter Test condition Min. Typ. Max. Unit

V

V

OH

V

OL

Oscillator

High logic level output
voltage

Low logic level output
voltage

IOH= -2mA

= 2mA

I

OL

DD

0.75

-

GND
+ 0.4

V

V

External Clock X2 voltage swing External clock. Figure 4 5

External Clock

X2 DC voltage level External clock. Figure 4 2.5 V

DC XTAL Clock duty cycle External clock. 40 60 %

Xtal

Xtal

ESR

Crystal oscillator
frequency

External oscillator esr
resistance

fundamental 16 MHz

External oscillator

Xtal

CL

stabilization

Figure 6 16 pF

capacitance

Transmitter

I

TX_OUT

V

TX_OUT

V

TX_OUTDC

HD2

TX_OUT

HD3

TX_OUT

G accuracy

Output transmitting
current on TX_OUT

Max carrier output AC
voltage

Output DC voltage on
TX_OUT

Second harmonic
distortion on TX_OUT

Third harmonic
distortion on TX_OUT

Accuracy on voltage
control loop active

= 1.4kΩ

R

CL

Vsense = 0V

TX_OUT

= 2VPP;

V
Fc = 86KHz, no load

TX_OUT

= 2VPP;

V
Fc = 86KHz, no load

= 0Ω

R

CL

1.75 2.3 3.5

1.7 2.1 2.5 V

-1 +1 GST

V

pp

40 Ω

1mArms

V

PP

-42

-49

dB

dB

c

c

G

ST

ALC gain step control
loop gain step

DRNG ALC dynamic range 30 dB

C

CL

Input capacitance on
CL pin

Voltage control loop

V

senseTH

reference threshold on

pin

V

sense

Figure 17 160 180 200

Hysteresis on voltage

V

senseHYST

loop reference

Figure 17 ±18 mV

threshold

10/44

0.6 1 1.4 dB

80 pF

mV

PK

ST7540 Electrical characteristics

Table 5. Electrical characteristics (continued)

(

VDD = +5V,

VCC =+9 V,

V

= S

VSS = GND = 0V,-40°C ≤ TA ≤ 85°C, TJ < 125°C,

SS

unless otherwise specified)

Symbol Parameter Test condition Min. Typ. Max. Unit

V

SENSE

CL

CL

T

RxTx

T

T

TH

HYST

ALC

ST

V

SENSE

Input

impedance

Current control loop
reference threshold on
CL pin

Hysteresis on current
loop reference
threshold

Carrier activation time

Carrier stabilization
time
from STEP 16 to zero
or from step 16 to step
31,

Tstep

36 kΩ

Figure 17 1.80 1.90 2.00 V

Figure 17 210 250 290 mV

Figure 21 - 600

Baud Xtal = 16MHz

Figure 21- 1200 Baud

Xtal = 16MHz

Figure 21- 2400 Baud

Xtal = 16MHz

Figure 21- 4800 Baud

Xtal = 16MHz

Figure 21

Xtal = 16MHz

Figure 21

Xtal = 16MHz

1.6 ms

800 µs

400 µs

200 µs

3.2 ms

200 µs

Power amplifier

PA

IN(Offset)

GBWP

R

IN

C

IN

CMRR

Input terminals
OFFSET

Gain bandwidth
product

Input resistance at
PA_IN+ and PA_IN­pins

Input capacitance at
PA_IN+ and PA_IN­pins

Common mode
rejection ratio

±18 mV

100 MHz

PA_IN+ vs. Vss

PA_IN- vs. Vss

PA_IN+ vs. Vss

PA_IN- vs. Vss

(1)

(1)

(1)

(1)

1 MΩ

1 MΩ

5pF

5pF

40 dB

11/44

Electrical characteristics ST7540

Table 5. Electrical characteristics (continued)

(

VDD = +5V,

VCC =+9 V,

V

= S

VSS = GND = 0V,-40°C ≤ TA ≤ 85°C, TJ < 125°C,

SS

unless otherwise specified)

Symbol Parameter Test condition Min. Typ. Max. Unit

HD2

HD3

Receiver

V

V

R

PA_ O U T

PA_ O U T

IN

IN

IN

Second harmonic
distortion on PA_OUT

V
V
R
Carrier frequency:

PA _O U T

= 12V

CC

LOAD

= 5.6V

= 30Ω

PP

,

-63

dB

86KHz

Figure 3

Third harmonic
distortion on PA_OUT
pin

PA _O U T

= 12V

CC

LOAD

= 5.6V

= 30Ω

V
V
R
Carrier frequency:

86KHz

PP

,

- 63

dB

Figure 3

Input sensitivity
(Normal Mode)

Input sensitivity
(High Sens.)

Input sensitivity (TxD
line forced to “1”)

0.5 2

250

V

BU

Maximum input signal 2

mV

µV

dB/

µVrms

V

rms

Input impedance 80 100 140 kΩ

Carrier detection
sensitivity

0.5 2

mV

(Normal Mode)

c

c

rms

rms

rms

Carrier detection

V

CD

sensitivity
(High Sensitivity Mode)

Carrier detection
sensitivity
(TxD forced to “1”)

V

BU

Band in Use Detection
Level

12/44

250

V

BU

83.5 86

µV

rms

dB/

µVrms

dB/

µVrms

ST7540 Electrical characteristics

Table 5. Electrical characteristics (continued)

(

VDD = +5V,

VCC =+9 V,

V

= S

VSS = GND = 0V,-40°C ≤ TA ≤ 85°C, TJ < 125°C,

SS

unless otherwise specified)

Symbol Parameter Test condition Min. Typ. Max. Unit

5V Voltage regulator

VDC

Linear regulator output
voltage

3.3V Voltage regulator

V

DD

Linear regulator output
voltage

Other functions

T

RSTO

T

T

T

T

T

T

OFFD

T

T

M

WD

WM

WO

OUT

OFF

CD

DCD

CLK

Reset time

Watch-dog pulse width See Figure 23 125 ns

Watch-dog pulse
period

Watch-dog time out See Figure 23 1.5 s

TX time out

Time Out OFF time Figure 22 125 ms

RxTx 0->1 vs. time out
delay

Carrier detection time
selectable by register

CD_PD Propagation
delay

Master clock output
selectable by register

0 < Io < 50mA

7.5V < V

CC

< 13.5V

0 < Io < 50mA

7.5V < V

CC

< 13.5V

See Figure 23;
Xtal = 16MHz

Minimum value.
See Figure 23

Maximum value.
See Figure 23

Control register bit 7
and bit 8

-5% 5.05 +5% V

-5% 3.3 +5% V

50 ms

250 ns

1490 ms

1
3

Figure 22 20 µs

Control register
bit 9 and bit10

Figure 14

500

1
3
5

µs
ms
ms
ms

Figure 14 300 500 µs

Control register
bit 15 and bit 16
See Ta bl e 1 2

fclock
fclock/2
fclock/4

off

MHz

s

BAUD Baud rate

Control register
bit 3 and bit 4
See Ta bl e 1 2

600
1200
2400
4800

Baud

13/44

Electrical characteristics ST7540

6

Table 5. Electrical characteristics (continued)
(

VDD = +5V,

VCC =+9 V,

V

= S

VSS = GND = 0V,-40°C ≤ TA ≤ 85°C, TJ < 125°C,

SS

unless otherwise specified)

Symbol Parameter Test condition Min. Typ. Max. Unit

Serial Interface

1667

T

B

Baud rate Bit Time
(1/BAUD)

Control register bit 3
and bit 4
(See Figure 13)

833

417

208

µs

Ts Setup time

T

H

T

CR

T

CC

T

DS

T

DH

T

CRP

1. Not tested, guaranteed by design

Hold time

CLR/T vs. REG_DATA
or RxTx

CLR/T vs. CLR/T

Setup time

Hold time

see Figures 8, 9, 10, 11
& 12

see Figures 8, 9, 10, 11
& 12

see Figures 8, 9, 10, 11
& 12

see Figures 8, 9, 10, 11
& 12

see Figures 8, 9, 10, 11
& 12

see Figures 8, 9, 10, 11
& 12

T

B

/4 TB/2

T

B

/4 TB/2

T

B

T

H

Figure 3. PLI configuration for PA_OUT distortions measurement

150 pF 100 pF

5 k

2.7 kΩ

Ω

5ns

2ns

/4

T

B

2*T

B

TB/2

PA_IN -

PA

V

AC

V

DC

10 kΩ

= 2Vpp
= 1.9 V

PA_IN +

14/44

Vcc

Vss

PA_OUT

1uF

30 Ω

D03IN142

Measurement point