ST72T331N2B3S
ST72E331
ST72T331
8-BIT MCU WITH 8 TO 16K OTP/EPROM, 256 EEPROM, 384 TO 512 BYTES RAM, ADC, WDG, SCI, SPI AND 2 TIMERS
■User Program Memory (OTP/EPROM): 8 to 16K bytes
■User EEPROM: 256 bytes
■Data RAM: 384 to 512 bytes including 256 bytes of stack
■Master Reset and Power-On Reset
■Low Voltage Detector (LVD) Reset option
■Run and Power Saving modes
■44 or 32 multifunctional bidirectional I/O lines:
–15 or 9 programmable interrupt inputs
–8 or 4 high sink outputs
–8 or 6 analog alternate inputs
–13 alternate functions
–EMI filtering
■Software or Hardware Watchdog (WDG)
■Two 16-bit Timers, each featuring:
–2 Input Captures 1)
–2 Output Compares 1)
–External Clock input (on Timer A)
–PWM and Pulse Generator modes
■Synchronous Serial Peripheral Interface (SPI)
■Asynchronous Serial Communications Interface (SCI)
■8-bit ADC with 8 channels 2)
■8-bit Data Manipulation
■63 basic Instructions and 17 main Addressing Modes
■8 x 8 Unsigned Multiply Instruction
■True Bit Manipulation
■Complete Development Support on DOS/ WINDOWSTM Real-Time Emulator
■Full Software Package on DOS/WINDOWSTM (C-Compiler, Cross-Assembler, Debugger)
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DATASHEET |
PSDIP42 |
CSDIP42W |
PSDIP56 |
CSDIP56W |
TQFP64 |
TQFP44 |
(See ordering information at the end of datashe |
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Notes: |
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1.One only on Timer A.
2.Six channels only for ST72T331J.
Device Summary
Features |
ST72T331J2 |
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ST72T331J4 |
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ST72T331N2 |
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ST72T331N4 |
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Program Memory - bytes |
8K |
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16K |
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8K |
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16K |
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EEPROM - bytes |
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256 |
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RAM (stack) - bytes |
384 (256) |
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512 (256) |
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384 (256) |
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512 (256) |
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Peripherals |
Watchdog, Timers, SPI, SCI, ADC and optional Low Voltage Detector Reset |
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Operating Supply |
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3 to 5.5 V |
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CPU Frequency |
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8MHz max (16MHz oscillator) - 4MHz max over 85°C |
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Temperature Range |
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- 40°C to + 125°C |
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Package |
TQFP44 - SDIP42 |
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TQFP64 - SDIP56 |
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Note: The ROM versions are supported by the ST72334 family. |
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Rev. 1.8 |
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May 2001 |
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1/107 |
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1
Table of Contents
ST72E331
ST72T331 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 5 |
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1.1 |
INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
5 |
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1.2 |
PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
6 |
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1.3 |
EXTERNAL CONNECTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
10 |
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1.4 |
MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
11 |
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1.5 |
OPTION BYTE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
14 |
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2 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
15 |
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2.1 |
INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
15 |
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2.2 |
MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
15 |
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2.3 |
CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
15 |
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3 CLOCKS, RESET, INTERRUPTS & POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . |
18 |
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3.1 |
CLOCK SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
18 |
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3.1.1 |
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
18 |
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3.1.2 |
External Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
18 |
3.2 |
RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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3.2.1 |
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
19 |
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3.2.2 |
External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
19 |
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3.2.3 |
Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
19 |
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3.2.4 |
Low Voltage Detector Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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4 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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4.1 |
NON MASKABLE SOFTWARE INTERRUPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
21 |
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4.2 |
EXTERNAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
21 |
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4.3 |
PERIPHERAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
21 |
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4.4 |
POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
24 |
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4.4.1 |
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
24 |
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4.4.2 |
Slow Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
24 |
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4.4.3 |
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
24 |
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4.4.4 |
Halt Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
25 |
4.5 |
MISCELLANEOUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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5 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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5.1 |
I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
27 |
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5.1.1 |
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
27 |
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5.1.2 |
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
27 |
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5.1.3 |
I/O Port Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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5.1.4 |
Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
31 |
5.2 |
EEPROM (EEP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
33 |
5.2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.2.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.2.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.2.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5.2.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5.2.6 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
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Table of Contents
5.3 WATCHDOG TIMER (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
37 |
5.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
5.3.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
5.3.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
5.3.4 Hardware Watchdog Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
5.3.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
5.3.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
5.3.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
5.4 16-BIT TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
5.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 5.4.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 5.4.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 5.4.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 5.4.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 5.4.6 Summary of Timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 5.4.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
5.5 SERIAL COMMUNICATIONS INTERFACE (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
5.5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
5.5.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
5.5.3 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
5.5.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
5.5.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
5.5.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
5.5.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
5.6 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
5.6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 5.6.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 5.6.3 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 5.6.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 5.6.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 5.6.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 5.6.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
5.7 8-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
5.7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
5.7.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
5.7.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
5.7.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
5.7.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
5.7.6 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
6 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
86 |
6.1 ST7 ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
86 |
6.1.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 6.1.2 Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 6.1.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 6.1.4 Indexed (No Offset, Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 6.1.5 Indirect (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 6.1.6 Indirect Indexed (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 6.1.7 Relative Mode (Direct, Indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
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ST72E331 ST72T331
6.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
89 |
7 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
7.1 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 7.2 RECOMMENDED OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 7.3 RESET CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 7.4 OSCILLATOR CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 7.5 DC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 7.6 PERIPHERAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
8 GENERAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
102 |
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8.1 |
EPROM ERASURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
102 |
8.2 |
PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
103 |
8.3 |
ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
106 |
9 SUMMARY OF CHANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
107 |
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ST72E331 ST72T331
1 GENERAL DESCRIPTION
1.1 INTRODUCTION
The ST72T331 HCMOS Microcontroller Unit (MCU) is a member of the ST7 family. The device is based on an industry-standard 8-bit core and features an enhanced instruction set. The device is normally operated at a 16 MHz oscillator frequency. Under software control, the ST72T331 may be placed in either Wait, Slow or Halt modes, thus reducing power consumption. The enhanced instruction set and addressing modes afford real programming potential. In addition to standard 8-bit data management, the ST72T331 features true bit manipulation, 8x8 unsigned multiplication and indirect addressing modes on the whole memory. The device includes a low consumption and
Figure 1. ST72T331 Block Diagram
fast start on-chip oscillator, CPU, program memory (OTP/EPROM versions), EEPROM, RAM, 44 (QFP64 and SDIP56) or 32 (QFP44 and SDIP42) I/O lines, a Low Voltage Detector (LVD) and the following on-chip peripherals: Analog-to-Digital converter (ADC) with 8 (QFP64, SDIP56) or 6 (QFP44, SDIP42) multiplexed analog inputs, industry standard synchronous SPI and asynchronous SCI serial interfaces, digital Watchdog, two independent 16-bit Timers, one featuring an External Clock Input, and both featuring Pulse Generator capabilities, 2 Input Captures and 2 Output Compares (only 1 Input Capture and 1 Output Compare on Timer A).
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OSCIN |
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OSC |
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OSCOUT |
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RESET |
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CONTROL |
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AND LVD |
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8-BIT CORE |
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ALU |
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PROGRAM |
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MEMORY |
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(8 - 16K Bytes) |
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EEPROM |
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(256 Bytes) |
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Internal
CLOCK
BUS DATA AND ADDRESS
PORT A |
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PA0 -> PA7 |
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(8 bits for ST72T331N) |
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(5 bits for ST72T331J) |
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PB0 -> PB7 |
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PORT B |
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(8 bits for ST72T331N) |
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TIMER B |
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(5 bits for ST72T331J) |
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PORT C |
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PC0 -> PC7 |
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(8 bits) |
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SPI |
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PORT D |
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PD0 -> PD7 |
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8-BIT ADC |
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(8 bits for ST72T331N) |
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(6 bits for ST72T331J) |
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RAM |
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PORT E |
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(384 - 512 Bytes) |
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PE0 -> PE7 |
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SCI |
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(6 bits for ST72T331N) |
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(2 bits for ST72T331J) |
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PF0 -> PF2,4,6,7 |
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PORT F |
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(6 bits) |
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WATCHDOG |
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VDDA |
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VDD |
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TIMER A |
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VSSA |
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VSS |
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POWER |
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SUPPLY |
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5/107
5
ST72E331 ST72T331
1.2 PIN DESCRIPTION
Figure 2. 64-Pin Thin QFP Package Pinout
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1) |
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PE1/RDI PE0/TDO |
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OSCOUT |
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PP |
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NC |
NC |
V OSCIN |
V NC |
NC |
RESET |
TEST/V |
PA7 PA6 |
PA5 PA4 |
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DD_2 |
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SS_2 |
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64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 |
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PE4 |
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1 |
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48 |
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VSS_1 |
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PE5 |
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2 |
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47 |
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VDD_1 |
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PE6 |
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3 |
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(EI0) 46 |
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PA3 |
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PE7 |
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4 |
(EI2) |
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(EI0) 45 |
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PA2 |
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PB0 |
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5 |
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(EI0) 44 |
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PA1 |
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PB1 |
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6 |
(EI2) |
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(EI0) 43 |
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PA0 |
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PB2 |
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7 |
(EI2) |
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42 |
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PC7/SS |
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PB3 |
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8 |
(EI2) |
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41 |
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PC6/SCK |
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PB4 |
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9 |
(EI3) |
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40 |
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PC5/MOSI |
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PB5 |
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10(EI3) |
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39 |
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PC4/MISO |
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PB6 |
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11(EI3) |
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38 |
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PC3/ICAP1_B |
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PB7 |
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12(EI3) |
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37 |
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PC2/ICAP2_B |
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AIN0/PD0 |
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13 |
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36 |
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PC1/OCMP1_B |
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AIN1/PD1 |
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14 |
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(EI1) |
(EI1) |
(EI1) |
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35 |
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PC0/OCMP2_B |
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AIN2/PD2 |
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15 |
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34 |
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VSS_0 |
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AIN3/PD3 |
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16 |
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33 |
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VDD_0 |
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17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 |
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DDA |
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SSA |
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DD_3 |
SS_3 |
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OCMP1 A/PF4 |
NC ICAP1 A/PF6 EXTCLK A/PF7 |
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AIN4/PD4 AIN5/PD5 |
AIN6/PD6 |
AIN7/PD7 V |
V |
V |
V CLKOUT/PF0 |
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PF1 |
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PF2 NC |
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1.V on EPROM/OTP only PP
Figure 4. 44-Pin Thin QFP Package Pinout
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OSCOUT |
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1) |
PP |
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PE0/TD0 V |
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OSCIN |
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V |
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RESET |
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TEST/V |
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PA7 |
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PA6 |
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PA5 |
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PA4 |
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DD2 |
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SS 2 |
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PE1/RDI |
44 43 42 41 40 39 38 37 36 35 34 |
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VSS_1 |
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1 |
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33 |
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PB0 |
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2 (EI2) |
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32 |
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VDD_1 |
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PB1 |
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3 (EI2) |
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(EI0) 31 |
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PA3 |
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PB2 |
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4 (EI2) |
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30 |
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PC7/SS |
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PB3 |
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5 (EI2) |
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29 |
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PC6/SCK |
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PB4 |
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6 (EI3) |
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28 |
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PC5/MOSI |
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AIN0/PD0 |
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7 |
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27 |
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PC4/MISO |
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AIN1/PD1 |
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8 |
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26 |
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PC3/ICAP1_B |
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AIN2/PD2 |
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9 |
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25 |
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PC2/ICAP2_B |
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AIN3/PD3 |
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10 |
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(EI1) |
(EI1) |
(EI1) |
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24 |
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PC1/OCMP1_B |
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AIN4/PD4 |
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11 |
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23 |
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PC0/OCMP2_B |
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12 13 14 15 16 17 18 19 20 21 22 |
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DDA |
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SSA |
CLKOUT/PF0 |
PF1 |
PF2 |
OCMP1 A/PF4 |
ICAP1 A/PF6 |
EXTCLK A/PF7 |
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DD 0 |
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SS 0 |
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AIN5/PD5 V |
V |
V |
V |
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1.V on EPROM/OTP only PP
Figure 3. 56-Pin Shrink DIP Package Pinout
PB4 |
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1 (EI3) |
(EI2) 56 |
PB3 |
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PB5 |
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2 (EI3) |
(EI2) 55 |
PB2 |
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PB6 |
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3 (EI3) |
(EI2) 54 |
PB1 |
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PB7 |
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4 (EI3) |
(EI2) 53 |
PB0 |
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AIN0/PD0 |
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5 |
52 |
PE7 |
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AIN1/PD1 |
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6 |
51 |
PE6 |
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AIN2/PD2 |
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7 |
50 |
PE5 |
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AIN3/PD3 |
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8 |
49 |
PE4 |
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AIN4/PD4 |
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9 |
48 |
PE1/RDI |
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AIN5/PD5 |
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10 |
47 |
PE0/TD0 |
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AIN6/PD6 |
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11 |
46 |
VDD_2 |
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AIN7/PD7 |
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12 |
45 |
OSCIN |
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VDDA |
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13 |
44 |
OSCOUT |
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VSSA |
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14 |
43 |
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V |
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CLKOUT/PF0 |
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15 (EI1) |
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SS_2 |
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42 |
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RESET |
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PF1 |
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16 (EI1) |
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1) |
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41 |
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TEST/VPP |
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PF2 |
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17 (EI1) |
40 |
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PA7 |
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OCMP1_A/PF4 |
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18 |
39 |
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PA6 |
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ICAP1_A/PF6 |
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19 |
38 |
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PA5 |
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EXTCLK_A/PF7 |
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20 |
37 |
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PA4 |
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VDD_0 |
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21 |
36 |
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VSS_1 |
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VSS_0 |
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22 |
35 |
VDD_1 |
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PC0/OCMP2_B |
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23 |
(EI0) 34 |
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PA3 |
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PC1/OCMP1_B |
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24 |
(EI0) 33 |
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PA2 |
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PC2/ICAP2_B |
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25 |
(EI0) 32 |
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PA1 |
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PC3/ICAP1_B |
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26 |
(EI0) 31 |
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PA0 |
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PC4/MISO |
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27 |
30 |
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PC7/SS |
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PC5/MOSI |
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28 |
29 |
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PC6/SCK |
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1.V on EPROM/OTP only PP
Figure 5. 42-Pin Shrink DIP Package Pinout
PB4 |
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1 |
(EI3) |
(EI2) 42 |
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PB3 |
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AIN0/PD0 |
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2 |
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(EI2) 41 |
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PB2 |
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AIN1/PD1 |
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3 |
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(EI2) 40 |
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PB1 |
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AIN2/PD2 |
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4 |
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(EI2) 39 |
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PB0 |
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AIN3/PD3 |
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5 |
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38 |
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PE1/RDI |
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AIN4/PD4 |
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6 |
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37 |
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PE0/TD0 |
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AIN5/PD5 |
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7 |
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36 |
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VDD_2 |
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VDDA |
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8 |
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35 |
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OSCIN |
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VSSA |
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9 |
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34 |
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OSCOUT |
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CLKOUT/PF0 |
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10 (EI1) |
33 |
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VSS_2 |
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PF1 |
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11 (EI1) |
32 |
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RESET |
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PF2 |
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12 (EI1) |
31 |
1) |
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TEST/VPP |
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OCMP1_A/PF4 |
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13 |
30 |
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PA7 |
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ICAP1_A/PF6 |
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14 |
29 |
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PA6 |
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EXTCLK_A/PF7 |
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15 |
28 |
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PA5 |
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PC0/OCMP2_B |
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16 |
27 |
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PA4 |
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PC1/OCMP1_B |
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17 |
26 |
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VSS_1 |
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PC2/ICAP2_B |
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18 |
25 |
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VDD_1 |
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PC3/ICAP1_B |
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19 |
(EI0)24 |
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PA3 |
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PC4/MISO |
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20 |
23 |
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PC7/SS |
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PC5/MOSI |
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21 |
22 |
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PC6/SCK |
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1.V on EPROM/OTP only PP
6/107
6
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ST72E331 ST72T331 |
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Table 1. ST72T331Nx Pin Description |
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Pin n° |
Pin n° |
Pin Name |
Type |
Description |
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Remarks |
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QFP64 |
SDIP56 |
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1 |
49 |
PE4 |
I/O |
Port E4 |
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High Sink |
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2 |
50 |
PE5 |
I/O |
Port E5 |
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High Sink |
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3 |
51 |
PE6 |
I/O |
Port E6 |
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High Sink |
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4 |
52 |
PE7 |
I/O |
Port E7 |
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High Sink |
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5 |
53 |
PB0 |
I/O |
Port B0 |
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External Interrupt: EI2 |
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6 |
54 |
PB1 |
I/O |
Port B1 |
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External Interrupt: EI2 |
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7 |
55 |
PB2 |
I/O |
Port B2 |
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External Interrupt: EI2 |
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8 |
56 |
PB3 |
I/O |
Port B3 |
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External Interrupt: EI2 |
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9 |
1 |
PB4 |
I/O |
Port B4 |
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External Interrupt: EI3 |
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10 |
2 |
PB5 |
I/O |
Port B5 |
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External Interrupt: EI3 |
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11 |
3 |
PB6 |
I/O |
Port B6 |
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External Interrupt: EI3 |
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12 |
4 |
PB7 |
I/O |
Port B7 |
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External Interrupt: EI3 |
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13 |
5 |
PD0/AIN0 |
I/O |
Port D0 or ADC Analog Input 0 |
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14 |
6 |
PD1/AIN1 |
I/O |
Port D1 or ADC Analog Input 1 |
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15 |
7 |
PD2/AIN2 |
I/O |
Port D2 or ADC Analog Input 2 |
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16 |
8 |
PD3/AIN3 |
I/O |
Port D3 or ADC Analog Input 3 |
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17 |
9 |
PD4/AIN4 |
I/O |
Port D4 or ADC Analog Input 4 |
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18 |
10 |
PD5/AIN5 |
I/O |
Port D5 or ADC Analog Input 5 |
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19 |
11 |
PD6/AIN6 |
I/O |
Port D6 or ADC Analog Input 6 |
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20 |
12 |
PD7/AIN7 |
I/O |
Port D7 or ADC Analog Input 7 |
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21 |
13 |
VDDA |
S |
Power Supply for analog peripheral (ADC) |
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22 |
14 |
VSSA |
S |
Ground for analog peripheral (ADC) |
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23 |
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VDD_3 |
S |
Main power supply |
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24 |
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VSS_3 |
S |
Ground |
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25 |
15 |
PF0/CLKOUT |
I/O |
Port F0 or CPU Clock Output |
|
External Interrupt: EI1 |
||
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26 |
16 |
PF1 |
I/O |
Port F1 |
|
External Interrupt: EI1 |
||
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27 |
17 |
PF2 |
I/O |
Port F2 |
|
External Interrupt: EI1 |
||
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28 |
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NC |
|
Not Connected |
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29 |
18 |
PF4/OCMP1_A |
I/O |
Port F4 or Timer A Output Compare 1 |
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30 |
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NC |
|
Not Connected |
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31 |
19 |
PF6/ICAP1_A |
I/O |
Port F6 or Timer A Input Capture 1 |
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32 |
20 |
PF7/EXTCLK_A |
I/O |
Port F7 or External Clock on Timer A |
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33 |
21 |
VDD_0 |
S |
Main power supply |
|
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34 |
22 |
VSS_0 |
S |
Ground |
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35 |
23 |
PC0/OCMP2_B |
I/O |
Port C0 or Timer B Output Compare 2 |
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36 |
24 |
PC1/OCMP1_B |
I/O |
Port C1 or Timer B Output Compare 1 |
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37 |
25 |
PC2/ICAP2_B |
I/O |
Port C2 or Timer B Input Capture 2 |
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38 |
26 |
PC3/ICAP1_B |
I/O |
Port C3 or Timer B Input Capture 1 |
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39 |
27 |
PC4/MISO |
I/O |
Port C4 or SPI Master In / Slave Out Data |
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40 |
28 |
PC5/MOSI |
I/O |
Port C5 or SPI Master Out / Slave In Data |
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41 |
29 |
PC6/SCK |
I/O |
Port C6 or SPI Serial Clock |
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42 |
30 |
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I/O |
Port C7 or SPI Slave Select |
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PC7/SS |
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43 |
31 |
PA0 |
I/O |
Port A0 |
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External Interrupt: EI0 |
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7/107 |
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7
ST72E331 ST72T331
Pin n° |
Pin n° |
|
Pin Name |
Type |
Description |
Remarks |
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QFP64 |
SDIP56 |
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44 |
32 |
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PA1 |
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I/O |
Port A1 |
External Interrupt: EI0 |
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45 |
33 |
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PA2 |
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I/O |
Port A2 |
External Interrupt: EI0 |
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46 |
34 |
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PA3 |
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I/O |
Port A3 |
External Interrupt: EI0 |
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47 |
35 |
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VDD_1 |
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S |
Main power supply |
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48 |
36 |
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VSS_1 |
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S |
Ground |
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49 |
37 |
|
PA4 |
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I/O |
Port A4 |
High Sink |
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50 |
38 |
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PA5 |
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I/O |
Port A5 |
High Sink |
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51 |
39 |
|
PA6 |
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I/O |
Port A6 |
High Sink |
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52 |
40 |
|
PA7 |
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I/O |
Port A7 |
High Sink |
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1) |
|
Test mode pin . In the EPROM programming |
This pin must be tied |
53 |
41 |
|
TEST/V |
S |
mode, this pin acts as the programming voltage |
|||
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PP |
|
input VPP. |
low in user mode |
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54 |
42 |
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I/O |
Bidirectional. Active low. Top priority non maskable interrupt. |
|
RESET |
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55 |
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NC |
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Not Connected |
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56 |
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NC |
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Not Connected |
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57 |
43 |
|
VSS_2 |
|
S |
Ground |
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58 |
44 |
|
OSCOUT |
|
O |
Input/Output Oscillator pin. These pins connect a parallel-resonant |
||
59 |
45 |
|
OSCIN |
|
I |
crystal, or an external source to the on-chip oscillator. |
||
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60 |
46 |
|
VDD_2 |
|
S |
Main power supply |
|
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61 |
47 |
|
PE0/TDO |
|
I/O |
Port E1 or SCI Transmit Data Out |
|
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62 |
48 |
|
PE1/RDI |
|
I/O |
Port E1 or SCI Receive Data In |
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63 |
|
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NC |
|
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Not Connected |
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64 |
|
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NC |
|
|
Not Connected |
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|
Note 1: VPP on EPROM/OTP only.
Table 2. ST72T331Jx Pin Description
Pin n° |
Pin n° |
Pin Name |
Type |
Description |
Remarks |
|
QFP44 |
SDIP42 |
|||||
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|||
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|
1 |
38 |
PE1/RDI |
I/O |
Port E1 or SCI Receive Data In |
|
|
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|
|
2 |
39 |
PB0 |
I/O |
Port B0 |
External Interrupt: EI2 |
|
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|
3 |
40 |
PB1 |
I/O |
Port B1 |
External Interrupt: EI2 |
|
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|
|
4 |
41 |
PB2 |
I/O |
Port B2 |
External Interrupt: EI2 |
|
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5 |
42 |
PB3 |
I/O |
Port B3 |
External Interrupt: EI2 |
|
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6 |
1 |
PB4 |
I/O |
Port B4 |
External Interrupt: EI3 |
|
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|
7 |
2 |
PD0/AIN0 |
I/O |
Port D0 or ADC Analog Input 0 |
|
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8 |
3 |
PD1/AIN1 |
I/O |
Port D1 or ADC Analog Input 1 |
|
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9 |
4 |
PD2/AIN2 |
I/O |
Port D2 or ADC Analog Input 2 |
|
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|
10 |
5 |
PD3/AIN3 |
I/O |
Port D3 or ADC Analog Input 3 |
|
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|
11 |
6 |
PD4/AIN4 |
I/O |
Port D4 or ADC Analog Input 4 |
|
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|
12 |
7 |
PD5/AIN5 |
I/O |
Port D5 or ADC Analog Input 5 |
|
|
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|
|
|
|
|
|
13 |
8 |
VDDA |
S |
Power Supply for analog peripheral (ADC) |
|
|
14 |
9 |
VSSA |
S |
Ground for analog peripheral (ADC) |
|
|
15 |
10 |
PF0/CLKOUT |
I/O |
Port F0 or CPU Clock Output |
External Interrupt: EI1 |
|
|
|
|
|
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|
|
16 |
11 |
PF1 |
I/O |
Port F1 |
External Interrupt: EI1 |
|
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|
|
17 |
12 |
PF2 |
I/O |
Port F2 |
External Interrupt: EI1 |
|
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|
8/107 |
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8
|
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|
ST72E331 ST72T331 |
|
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|
|
|
|
|
|
|
|
|
|
Pin n° |
Pin n° |
|
|
Pin Name |
Type |
Description |
|
Remarks |
||
QFP44 |
SDIP42 |
|
|
|
||||||
|
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||
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|||
18 |
13 |
|
PF4/OCMP1_A |
I/O |
Port F4 or Timer A Output Compare 1 |
|
|
|||
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|
|||
19 |
14 |
|
PF6/ICAP1_A |
I/O |
Port F6 or Timer A Input Capture 1 |
|
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|||
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|
|||
20 |
15 |
|
PF7/EXTCLK_A |
I/O |
Port F7 or External Clock on Timer A |
|
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|||
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|||
21 |
|
|
VDD_0 |
S |
Main power supply |
|
|
|||
22 |
|
|
VSS_0 |
S |
Ground |
|
|
|||
23 |
16 |
|
PC0/OCMP2_B |
I/O |
Port C0 or Timer B Output Compare 2 |
|
|
|||
|
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|
|||
24 |
17 |
|
PC1/OCMP1_B |
I/O |
Port C1 or Timer B Output Compare 1 |
|
|
|||
|
|
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|
|
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|
|||
25 |
18 |
|
PC2/ICAP2_B |
I/O |
Port C2 or Timer B Input Capture 2 |
|
|
|||
|
|
|
|
|
|
|
|
|||
26 |
19 |
|
PC3/ICAP1_B |
I/O |
Port C3 or Timer B Input Capture 1 |
|
|
|||
|
|
|
|
|
|
|
|
|||
27 |
20 |
|
PC4/MISO |
I/O |
Port C4 or SPI Master In / Slave Out Data |
|
|
|||
|
|
|
|
|
|
|
|
|||
28 |
21 |
|
PC5/MOSI |
I/O |
Port C5 or SPI Master Out / Slave In Data |
|
|
|||
|
|
|
|
|
|
|
|
|||
29 |
22 |
|
PC6/SCK |
I/O |
Port C6 or SPI Serial Clock |
|
|
|||
|
|
|
|
|
|
|
|
|
|
|
30 |
23 |
|
|
|
|
|
I/O |
Port C7 or SPI Slave Select |
|
|
PC7/SS |
|
|
|
|||||||
|
|
|
|
|
|
|
|
|||
31 |
24 |
|
PA3 |
I/O |
Port A3 |
|
External Interrupt: EI0 |
|||
|
|
|
|
|
|
|
|
|||
32 |
25 |
|
VDD_1 |
S |
Main power supply |
|
|
|||
33 |
26 |
|
VSS_1 |
S |
Ground |
|
|
|||
34 |
27 |
|
PA4 |
I/O |
Port A4 |
|
High Sink |
|||
|
|
|
|
|
|
|
|
|||
35 |
28 |
|
PA5 |
I/O |
Port A5 |
|
High Sink |
|||
|
|
|
|
|
|
|
|
|||
36 |
29 |
|
PA6 |
I/O |
Port A6 |
|
High Sink |
|||
|
|
|
|
|
|
|
|
|||
37 |
30 |
|
PA7 |
I/O |
Port A7 |
|
High Sink |
|||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
1) |
|
Test mode pin. In the EPROM programming |
This pin must be tied |
||||
|
|
|
|
|
|
|||||
38 |
31 |
|
TEST/VPP |
S |
mode, this pin acts as the programming |
|
low in user mode |
|||
|
|
|
|
|
|
|
|
voltage input VPP. |
|
|
39 |
32 |
|
|
|
|
I/O |
Bidirectional. Active low. Top priority non maskable interrupt. |
|||
RESET |
||||||||||
|
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|
|
|
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|
|||
40 |
33 |
|
VSS_2 |
S |
Ground |
|
|
|||
41 |
34 |
|
OSCOUT |
O |
Input/Output Oscillator pin. These pins connect a parallel-resonant |
|||||
42 |
35 |
|
OSCIN |
I |
crystal, or an external source to the on-chip oscillator. |
|||||
|
|
|
|
|
|
|
|
|||
43 |
36 |
|
VDD_2 |
S |
Main power supply |
|
|
|||
44 |
37 |
|
PE0/TDO |
I/O |
Port E0 or SCI Transmit Data Out |
|
|
|||
|
|
|
|
|
|
|
|
|
|
|
Note 1: VPP on EPROM/OTP only.
9/107
9
ST72E331 ST72T331
1.3 EXTERNAL CONNECTIONS
The following figure shows the recommended external connections for the device.
The VPP pin is only used for programming OTP and EPROM devices and must be tied to ground in user mode.
The 10 nF and 0.1 µF decoupling capacitors on the power supply lines are a suggested EMC performance/cost tradeoff.
Figure 6. Recommended External Connections
The external reset network is intended to protect the device against parasitic resets, especially in noisy environments.
Unused I/Os should be tied high to avoid any unnecessary power consumption on floating lines. An alternative solution is to program the unused ports as inputs with pull-up.
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VDD |
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VPP |
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VDD |
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+ |
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0.1µF |
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10nF |
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VSS |
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VDDA |
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See |
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A/D Converter |
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Optional if Low Voltage |
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Section |
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VSSA |
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Detector (LVD) is used |
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VDD |
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4.7K |
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0.1µF |
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EXTERNAL RESET CIRCUIT |
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RESET |
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0.1µF |
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OSCIN |
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See |
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Clocks |
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Section |
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OSCOUT |
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|||||||
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Or configure unused I/O ports |
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by software as input with pull-up |
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VDD |
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10K |
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Unused I/O |
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10/107
10
ST72E331 ST72T331
1.4 MEMORY MAP
Figure 7. Program Memory Map
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0080h |
Short Addressing |
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0000h |
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HW Registers |
00FFh |
RAM (zero page) |
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(see Table 4) |
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007Fh |
0100h |
256 Bytes Stack/ |
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0080h |
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16-bit Addressing RAM |
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384 Bytes RAM |
01FFh |
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01FFh |
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027Fh |
512 Bytes RAM |
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0200h / 0280h |
Reserved |
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0080h |
Short Addressing |
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0BFFh |
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00FFh |
RAM (zero page) |
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0C00h |
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256 Bytes EEPROM |
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0CFFh |
0100h |
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0D00h |
Reserved |
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256 Bytes Stack/ |
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BFFFh |
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16-bit Addressing RAM |
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C000h |
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01FFh |
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16K Bytes |
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0200h |
16-bit Addressing |
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Program |
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RAM |
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E000h |
8K Bytes |
Memory |
027Fh |
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Program |
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FFDFh |
Memory |
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FFE0h |
Interrupt & Reset Vectors |
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FFFFh |
(see Table 3) |
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Table 3. Interrupt Vector Map
Vector Address |
Description |
Remarks |
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FFE0-FFE1h |
Not Used |
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FFE2-FFE3h |
Not Used |
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FFE4-FFE5h |
EEPROM Interrupt Vector |
Internal Interrupt |
FFE6-FFE7h |
SCI Interrupt Vector |
Internal Interrupt |
FFE8-FFE9h |
TIMER B Interrupt Vector |
Internal Interrupt |
FFEA-FFEBh |
TIMER A Interrupt Vector |
Internal Interrupt |
FFEC-FFEDh |
SPI interrupt vector |
Internal Interrupt |
FFEE-FFEFh |
Not Used |
|
FFF0-FFF1h |
External Interrupt Vector EI3 |
External Interrupt |
FFF2-FFF3h |
External Interrupt Vector EI2 |
External Interrupt |
FFF4-FFF5h |
External Interrupt Vector EI1 |
External Interrupt |
FFF6-FFF7h |
External Interrupt Vector EI0 |
External Interrupt |
FFF8-FFF9h |
Not Used |
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FFFA-FFFBh |
Not Used |
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FFFC-FFFDh |
TRAP (software) Interrupt Vector |
CPU Interrupt |
FFFE-FFFFh |
RESET Vector |
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11/107
11
ST72E331 ST72T331
Table 4. Hardware Register Memory Map
Address |
Block |
Register |
Register Name |
Reset |
Remarks |
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Label |
Status |
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0000h |
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PADR |
Data Register |
00h |
R/W |
|
0001h |
Port A |
PADDR |
Data Direction Register |
00h |
R/W |
|
0002h |
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PAOR |
Option Register |
00h |
R/W 1) |
|
0003h |
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Reserved Area (1 byte) |
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0004h |
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PCDR |
Data Register |
00h |
R/W |
|
0005h |
Port C |
PCDDR |
Data Direction Register |
00h |
R/W |
|
0006h |
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PCOR |
Option Register |
00h |
R/W |
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0007h |
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Reserved Area (1 byte) |
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0008h |
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PBDR |
Data Register |
00h |
R/W |
|
0009h |
Port B |
PBDDR |
Data Direction Register |
00h |
R/W |
|
000Ah |
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PBOR |
Option Register |
00h |
R/W 1) |
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000Bh |
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Reserved Area (1 byte) |
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000Ch |
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PEDR |
Data Register |
00h |
R/W |
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000Dh |
Port E |
PEDDR |
Data Direction Register |
00h |
R/W |
|
000Eh |
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PEOR |
Option Register |
0Ch |
R/W 1) |
|
000Fh |
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Reserved Area (1 byte) |
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0010h |
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PDDR |
Data Register |
00h |
R/W |
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0011h |
Port D |
PDDDR |
Data Direction Register |
00h |
R/W |
|
0012h |
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PDOR |
Option Register |
00h |
R/W 1) |
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0013h |
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Reserved Area (1 byte) |
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0014h |
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PFDR |
Data Register |
00h |
R/W |
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0015h |
Port F |
PFDDR |
Data Direction Register |
00h |
R/W |
|
0016h |
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PFOR |
Option Register |
28h |
R/W 1) |
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0017h to |
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Reserved Area (9 bytes) |
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001Fh |
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0020h |
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MISCR |
Miscellaneous Register |
00h |
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0021h |
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SPIDR |
SPI Data I/O Register |
xxh |
R/W |
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0022h |
SPI |
SPICR |
SPI Control Register |
xxh |
R/W |
|
0023h |
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SPISR |
SPI Status Register |
00h |
Read Only |
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0024h to |
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Reserved Area (6 bytes) |
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0029h |
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002Ah |
WDG |
WDGCR |
Watchdog Control Register |
7Fh |
R/W |
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002Bh |
WDGSR |
Watchdog Status Register |
00h |
R/W3) |
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002Ch |
EEPROM |
EEPCR |
EEPROM Control Register |
00h |
R/W Register |
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002Dh to |
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Reserved Area (4 bytes) |
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0030h |
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12/107
12
ST72E331 ST72T331
Address |
Block |
Register |
Register Name |
Reset |
Remarks |
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Label |
Status |
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0031h |
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TACR2 |
Control Register2 |
00h |
R/W |
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0032h |
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TACR1 |
Control Register1 |
00h |
R/W |
|
0033h |
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TASR |
Status Register |
xxh |
Read Only |
|
0034h-0035h |
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TAIC1HR |
Input Capture1 High Register |
xxh |
Read Only |
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TAIC1LR |
Input Capture1 Low Register |
xxh |
Read Only |
|
0036h-0037h |
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TAOC1HR |
Output Compare1 High Register |
80h |
R/W |
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TAOC1LR |
Output Compare1 Low Register |
00h |
R/W |
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0038h-0039h |
Timer A |
TACHR |
Counter High Register |
FFh |
Read Only |
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TACLR |
Counter Low Register |
FCh |
Read Only |
|
003Ah-003Bh |
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TAACHR |
Alternate Counter High Register |
FFh |
Read Only |
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TAACLR |
Alternate Counter Low Register |
FCh |
Read Only |
|
003Ch-003Dh |
|
TAIC2HR |
Input Capture2 High Register |
xxh |
Read Only2) |
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TAIC2LR |
Input Capture2 Low Register |
xxh |
Read Only2) |
|
003Eh-003Fh |
|
TAOC2HR |
Output Compare2 High Register |
80h |
R/W2) |
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TAOC2LR |
Output Compare2 Low Register |
00h |
R/W2) |
|
0040h |
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Reserved Area (1 byte) |
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0041h |
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TBCR2 |
Control Register2 |
00h |
R/W |
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0042h |
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TBCR1 |
Control Register1 |
00h |
R/W |
|
0043h |
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TBSR |
Status Register |
xxh |
Read Only |
|
0044h-0045h |
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TBIC1HR |
Input Capture1 High Register |
xxh |
Read Only |
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TBIC1LR |
Input Capture1 Low Register |
xxh |
Read Only |
|
0046h-0047h |
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TBOC1HR |
Output Compare1 High Register |
80h |
R/W |
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TBOC1LR |
Output Compare1 Low Register |
00h |
R/W |
|
0048h-0049h |
Timer B |
TBCHR |
Counter High Register |
FFh |
Read Only |
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TBCLR |
Counter Low Register |
FCh |
Read Only |
|
004Ah-004Bh |
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TBACHR |
Alternate Counter High Register |
FFh |
Read Only |
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TBACLR |
Alternate Counter Low Register |
FCh |
Read Only |
|
004Ch-004Dh |
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TBIC2HR |
Input Capture2 High Register |
xxh |
Read Only |
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TBIC2LR |
Input Capture2 Low Register |
xxh |
Read Only |
|
004Eh-004Fh |
|
TBOC2HR |
Output Compare2 High Register |
80h |
R/W |
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TBOC2LR |
Output Compare2 Low Register |
00h |
R/W |
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0050h |
|
SCISR |
SCI Status Register |
C0h |
Read Only |
|
0051h |
|
SCIDR |
SCI Data Register |
xxh |
R/W |
|
0052h |
|
SCIBRR |
SCI Baud Rate Register |
00x----xb |
R/W |
|
0053h |
SCI |
SCICR1 |
SCI Control Register 1 |
xxh |
R/W |
|
0054h |
SCICR2 |
SCI Control Register 2 |
00h |
R/W |
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0055h |
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SCIERPR |
SCI Extended Receive Prescaler Register |
00h |
R/W |
|
0056h |
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Reserved |
--- |
Reserved |
|
0057h |
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SCIETPR |
SCI Extended Transmit Prescaler Register |
00h |
R/W |
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0058h to |
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Reserved Area (24 bytes) |
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006Fh |
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0070h |
ADC |
ADCDR |
ADC Data Register |
00h |
Read Only |
|
0071h |
ADCCSR |
ADC Control/Status Register |
00h |
R/W |
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0072h to |
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Reserved Area (14 bytes) |
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007Fh |
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Notes:
1.The bits corresponding to unavailable pins are forced to 1 by hardware, this affects the reset status value.
2.External pin not available.
3.Not used in versions without Low Voltage Detector Reset.
13/107
13
ST72E331 ST72T331
1.5 OPTION BYTE
The user has the option to select software watchdog or hardware watchdog (see description in the Watchdog chapter). When programming EPROM or OTP devices, this option is selected in a menu by the user of the EPROM programmer before burning the EPROM/OTP. The Option Byte is located in a non-user map. No address has to be specified. The Option Byte is at FFh after UV erasure and must be properly programmed to set desired options.
14/107
OPTBYTE
7 |
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0 |
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- |
- |
- |
- |
b3 |
b2 |
- |
WDG |
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Bit 7:4 = Not used
Bit 3 = Reserved, must be cleared.
Bit 2 = Reserved, must be set on ST72T331N devices and must be cleared on ST72T331J devices.
Bit 1 = Not used
Bit 0 = WDG Watchdog disable
0:The Watchdog is enabled after reset (Hardware Watchdog).
1:The Watchdog is not enabled after reset (Software Watchdog).
14
ST72E331 ST72T331
2 CENTRAL PROCESSING UNIT
2.1 INTRODUCTION
This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8-bit data manipulation.
Accumulator (A)
The Accumulator is an 8-bit general purpose register used to hold operands and the results of the arithmetic and logic calculations and to manipulate data.
2.2 MAIN FEATURES
■63 basic instructions
■Fast 8-bit by 8-bit multiply
■17 main addressing modes
■Two 8-bit index registers
■16-bit stack pointer
■Low power modes
■Maskable hardware interrupts
■Non-maskable software interrupt
2.3 CPU REGISTERS
The 6 CPU registers shown in Figure 1 are not present in the memory mapping and are accessed by specific instructions.
Figure 8. CPU Registers
Index Registers (X and Y)
In indexed addressing modes, these 8-bit registers are used to create either effective addresses or temporary storage areas for data manipulation. (The Cross-Assembler generates a precede instruction (PRE) to indicate that the following instruction refers to the Y register.)
The Y register is not affected by the interrupt automatic procedures (not pushed to and popped from the stack).
Program Counter (PC)
The program counter is a 16-bit register containing the address of the next instruction to be executed by the CPU. It is made of two 8-bit registers PCL (Program Counter Low which is the LSB) and PCH (Program Counter High which is the MSB).
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7 |
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0 |
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ACCUMULATOR |
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RESET VALUE = XXh |
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7 |
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0 |
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X INDEX REGISTER |
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RESET VALUE = XXh |
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7 |
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0 |
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Y INDEX REGISTER |
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RESET VALUE = XXh |
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PCH |
8 |
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7 |
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PCL |
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0 |
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PROGRAM COUNTER |
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15 |
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RESET VALUE = RESET VECTOR @ FFFEh-FFFFh |
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7 |
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0 |
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1 |
1 |
1 |
H |
I |
N |
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Z |
C |
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CONDITION CODE REGISTER |
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RESET VALUE = 1 |
1 |
1 |
X |
1 |
X |
X |
X |
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15 |
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8 |
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0 |
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STACK POINTER |
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7 |
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RESET VALUE = STACK HIGHER ADDRESS |
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X = Undefined Value
15/107
15
ST72E331 ST72T331
CPU REGISTERS (Cont’d)
CONDITION CODE REGISTER (CC)
Read/Write
Reset Value: 111x1xxx
7 |
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0 |
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1 |
1 |
1 |
H |
I |
N |
Z |
C |
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The 8-bit Condition Code register contains the interrupt mask and four flags representative of the result of the instruction just executed. This register can also be handled by the PUSH and POP instructions.
These bits can be individually tested and/or controlled by specific instructions.
Bit 4 = H Half carry.
This bit is set by hardware when a carry occurs between bits 3 and 4 of the ALU during an ADD or ADC instruction. It is reset by hardware during the same instructions.
0:No half carry has occurred.
1:A half carry has occurred.
This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD arithmetic subroutines.
Bit 3 = I Interrupt mask.
This bit is set by hardware when entering in interrupt or by software to disable all interrupts except the TRAP software interrupt. This bit is cleared by software.
0:Interrupts are enabled.
1:Interrupts are disabled.
This bit is controlled by the RIM, SIM and IRET instructions and is tested by the JRM and JRNM instructions.
Note: Interrupts requested while I is set are latched and can be processed when I is cleared. By default an interrupt routine is not interruptable
16/107
because the I bit is set by hardware at the start of the routine and reset by the IRET instruction at the end of the routine. If the I bit is cleared by software in the interrupt routine, pending interrupts are serviced regardless of the priority level of the current interrupt routine.
Bit 2 = N Negative.
This bit is set and cleared by hardware. It is representative of the result sign of the last arithmetic, logical or data manipulation. It is a copy of the 7th bit of the result.
0:The result of the last operation is positive or null.
1:The result of the last operation is negative (i.e. the most significant bit is a logic 1).
This bit is accessed by the JRMI and JRPL instructions.
Bit 1 = Z Zero.
This bit is set and cleared by hardware. This bit indicates that the result of the last arithmetic, logical or data manipulation is zero.
0:The result of the last operation is different from zero.
1:The result of the last operation is zero.
This bit is accessed by the JREQ and JRNE test instructions.
Bit 0 = C Carry/borrow.
This bit is set and cleared by hardware and software. It indicates an overflow or an underflow has occurred during the last arithmetic operation.
0:No overflow or underflow has occurred.
1:An overflow or underflow has occurred.
This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC instructions. It is also affected by the “bit test and branch”, shift and rotate instructions.
16
ST72E331 ST72T331
CENTRAL PROCESSING UNIT (Cont’d)
Stack Pointer (SP)
Read/Write
Reset Value: 01FFh
15 |
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1 |
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SP7 |
SP6 |
SP5 |
SP4 |
SP3 |
SP2 |
SP1 |
SP0 |
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The Stack Pointer is a 16-bit register which is always pointing to the next free location in the stack. It is then decremented after data has been pushed onto the stack and incremented before data is popped from the stack (see Figure 9).
Since the stack is 256 bytes deep, the 8th most significant bits are forced by hardware. Following an MCU Reset, or after a Reset Stack Pointer instruction (RSP), the Stack Pointer contains its reset value (the SP7 to SP0 bits are set) which is the stack higher address.
The least significant byte of the Stack Pointer (called S) can be directly accessed by a LD instruction.
Note: When the lower limit is exceeded, the Stack Pointer wraps around to the stack upper limit, without indicating the stack overflow. The previously stored information is then overwritten and therefore lost. The stack also wraps in case of an underflow.
The stack is used to save the return address during a subroutine call and the CPU context during an interrupt. The user may also directly manipulate the stack by means of the PUSH and POP instructions. In the case of an interrupt, the PCL is stored at the first location pointed to by the SP. Then the other registers are stored in the next locations as shown in Figure 9.
–When an interrupt is received, the SP is decremented and the context is pushed on the stack.
–On return from interrupt, the SP is incremented and the context is popped from the stack.
A subroutine call occupies two locations and an interrupt five locations in the stack area.
Figure 9. Stack Manipulation Example
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CALL |
Interrupt |
PUSH Y |
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POP Y |
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IRET |
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RET |
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Subroutine |
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Event |
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or RSP |
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@ 0100h |
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SP |
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SP |
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SP |
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CC |
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CC |
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CC |
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A |
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A |
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A |
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X |
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X |
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X |
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SP |
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PCH |
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PCH |
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PCH |
SP |
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PCL |
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PCL |
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PCL |
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PCH |
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PCH |
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PCH |
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PCH |
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PCH |
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SP |
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@ 01FFh PCL |
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PCL |
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PCL |
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PCL |
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PCL |
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Stack Higher Address = 01FFh
Stack Lower Address = 0100h
17/107
17
ST72E331 ST72T331
3 CLOCKS, RESET, INTERRUPTS & POWER SAVING MODES
3.1 CLOCK SYSTEM
3.1.1 General Description |
Figure 10. External Clock Source Connections |
The MCU accepts either a crystal or ceramic resonator, or an external clock signal to drive the internal oscillator. The internal clock (fCPU) is derived from the external oscillator frequency (fOSC). The
external Oscillator clock is first divided by 2, and an additional division factor of 2, 4, 8, or 16 can be applied, in Slow Mode, to reduce the frequency of the fCPU; this clock signal is also routed to the onchip peripherals. The CPU clock signal consists of a square wave with a duty cycle of 50%.
The internal oscillator is designed to operate with an AT-cut parallel resonant quartz crystal resonator in the frequency range specified for fosc. The circuit shown in Figure 11 is recommended when using a crystal, and Table 5 lists the recommended capacitance and feedback resistance values. The crystal and associated components should be mounted as close as possible to the input pins in order to minimize output distortion and start-up stabilisation time.
Use of an external CMOS oscillator is recommended when crystals outside the specified frequency ranges are to be used.
3.1.2 External Clock
An external clock may be applied to the OSCIN input with the OSCOUT pin not connected, as shown on Figure 10.
Table 5 |
Recommended |
Values for |
16 MHz |
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Crystal Resonator (C0 < 7pF) |
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RSMAX |
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40 Ω |
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60 Ω |
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150 Ω |
COSCIN |
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56pF |
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47pF |
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22pF |
COSCOUT |
56pF |
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47pF |
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22pF |
RSMAX: Parasitic series resistance of the quartz crystal (upper limit).
C0: Parasitic shunt capacitance of the quartz crystal (upper limit 7pF).
COSCOUT, COSCIN: Maximum total capacitance on pins OSCIN and OSCOUT (the value includes the
external capacitance tied to the pin plus the parasitic capacitance of the board and of the device).
OSCIN OSCOUT
NC
EXTERNAL
CLOCK
Figure 11. Crystal/Ceramic Resonator
OSCIN OSCOUT
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COSCIN |
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COSCOUT |
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Figure 12. Clock Prescaler Block Diagram
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%2 |
% 2, 4, 8, 16 |
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fCPU |
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OSCIN |
OSCOUT |
to CPU and |
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Peripherals |
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COSCIN |
C |
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OSCOUT |
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18/107
18
ST72E331 ST72T331
3.2 RESET
3.2.1 Introduction
There are four sources of Reset:
–RESET pin (external source)
–Power-On Reset (Internal source)
–WATCHDOG (Internal Source)
–Low Voltage Detection Reset (internal source)
The Reset Service Routine vector is located at address FFFEh-FFFFh.
3.2.2 External Reset
The RESET pin is both an input and an open-drain output with integrated pull-up resistor. When one of the internal Reset sources is active, the Reset
pin is driven low for a duration of tRESET to reset the whole application.
3.2.3 Reset Operation
The duration of the Reset state is a minimum of 4096 internal CPU Clock cycles. During the Reset state, all I/Os take their reset value.
A Reset signal originating from an external source must have a duration of at least tPULSE in order to
be recognised. This detection is asynchronous and therefore the MCU can enter Reset state even in Halt mode.
At the end of the Reset cycle, the MCU may be held in the Reset state by an External Reset signal. The RESET pin may thus be used to ensure VDD has risen to a point where the MCU can operate correctly before the user program is run. Following a Reset event, or after exiting Halt mode, a 4096 CPU Clock cycle delay period is initiated in order to allow the oscillator to stabilise and to ensure that recovery has taken place from the Reset state.
In the high state, the RESET pin is connected internally to a pull-up resistor (RON). This resistor can be pulled low by external circuitry to reset the device.
The RESET pin is an asynchronous signal which plays a major role in EMS performance. In a noisy environment, it is recommended to use the external connections shown in Figure 6.
Figure 13. Reset Block Diagram
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INTERNAL |
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RESET |
OSCILLATOR |
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SIGNAL |
COUNTER |
TO ST7 |
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RESET |
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RESET |
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VDD |
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RON |
POWER-ON RESET |
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WATCHDOG RESET |
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LOW VOLTAGE DETECTOR RESET |
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19/107 |
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19 |
ST72E331 ST72T331
RESET (Cont’d)
3.2.4 Low Voltage Detector Reset
The on-chip Low Voltage Detector (LVD) generates a static reset when the supply voltage is below a reference value. The LVD functions both during power-on as well as when the power supply drops (brown-out). The reference value for a voltage drop is lower than the reference value for pow- er-on in order to avoid a parasitic reset when the MCU starts running and sinks current on the supply (hysteresis).
The LVD Reset circuitry generates a reset when VDD is below:
VLVDUP when VDD is rising VLVDDOWN when VDD is falling
Provided the minimun VDD value (guaranteed for
the oscillator frequency) is above VLVDDOWN , the MCU can only be in two modes:
-under full software control or
-in static safe reset
In this condition, secure operation is always ensured for the application without the need for external reset hardware.
During a Low Voltage Detector Reset, the RESET pin is held low, thus permitting the MCU to reset other devices.
In noisy environments, the power supply may drop for short periods and cause the Low Voltage Detector to generate a Reset too frequently. In such
cases, it is recommended to use devices without the LVD Reset option and to rely on the watchdog function to detect application runaway conditions.
Figure 14. Low Voltage Detector Reset Function
LOW VOLTAGE |
VDD |
DETECTOR RESET |
RESET |
FROM |
WATCHDOG |
RESET |
Figure 15. Low Voltage Detector Reset Signal
VLVDUP |
VLVDDOWN |
VDD |
RESET |
Note: See electrical characteristics for values of VLVDUP and VLVDDOWN
Figure 16. Temporization timing diagram after an internal Reset
VLVDUP
VDD
Temporization (4096 CPU clock cycles)
Addresses |
$FFFE |
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20/107
20
ST72E331 ST72T331
4 INTERRUPTS
The ST7 core may be interrupted by one of two different methods: maskable hardware interrupts as listed in the Interrupt Mapping Table and a nonmaskable software interrupt (TRAP). The Interrupt processing flowchart is shown in Figure 1.
The maskable interrupts must be enabled by clearing the I bit in order to be serviced. However, disabled interrupts may be latched and processed when they are enabled (see external interrupts subsection).
Note: After reset, all interrupts are disabled.
When an interrupt has to be serviced:
–Normal processing is suspended at the end of the current instruction execution.
–The PC, X, A and CC registers are saved onto the stack.
–The I bit of the CC register is set to prevent additional interrupts.
–The PC is then loaded with the interrupt vector of the interrupt to service and the first instruction of the interrupt service routine is fetched (refer to the Interrupt Mapping Table for vector addresses).
The interrupt service routine should finish with the IRET instruction which causes the contents of the saved registers to be recovered from the stack.
Note: As a consequence of the IRET instruction, the I bit will be cleared and the main program will resume.
Priority Management
By default, a servicing interrupt cannot be interrupted because the I bit is set by hardware entering in interrupt routine.
In the case when several interrupts are simultaneously pending, an hardware priority defines which one will be serviced first (see the Interrupt Mapping Table).
Interrupts and Low Power Mode
All interrupts allow the processor to leave the WAIT low power mode. Only external and specifically mentioned interrupts allow the processor to leave the HALT low power mode (refer to the “Exit from HALT“ column in the Interrupt Mapping Table).
4.1 NON MASKABLE SOFTWARE INTERRUPT
This interrupt is entered when the TRAP instruction is executed regardless of the state of the I bit.
It will be serviced according to the flowchart on Figure 1.
4.2 EXTERNAL INTERRUPTS
External interrupt vectors can be loaded into the PC register if the corresponding external interrupt occurred and if the I bit is cleared. These interrupts allow the processor to leave the Halt low power mode.
The external interrupt polarity is selected through the miscellaneous register or interrupt register (if available).
An external interrupt triggered on edge will be latched and the interrupt request automatically cleared upon entering the interrupt service routine.
If several input pins, connected to the same interrupt vector, are configured as interrupts, their signals are logically ANDed and inverted before entering the edge/level detection block.
Caution: The type of sensitivity defined in the Miscellaneous or Interrupt register (if available) applies to the ei source. In case of an ANDed source (as described on the I/O ports section), a low level on an I/O pin configured as input with interrupt, masks the interrupt request even in case of risingedge sensitivity.
4.3 PERIPHERAL INTERRUPTS
Different peripheral interrupt flags in the status register are able to cause an interrupt when they are active if both:
–The I bit of the CC register is cleared.
–The corresponding enable bit is set in the control register.
If any of these two conditions is false, the interrupt is latched and thus remains pending.
Clearing an interrupt request is done by:
–Writing “0” to the corresponding bit in the status register or
–Access to the status register while the flag is set followed by a read or write of an associated register.
Note: the clearing sequence resets the internal latch. A pending interrupt (i.e. waiting for being enabled) will therefore be lost if the clear sequence is executed.
21/107
21
ST72E331 ST72T331
INTERRUPTS (Cont’d)
Figure 17. Interrupt Processing Flowchart
FROM RESET
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I BIT SET? |
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INTERRUPT |
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PENDING? |
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Y |
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FETCH NEXT INSTRUCTION |
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IRET? |
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STACK PC, X, A, CC |
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SET I BIT |
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LOAD PC FROM INTERRUPT VECTOR |
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EXECUTE INSTRUCTION
RESTORE PC, X, A, CC FROM STACK
THIS CLEARS I BIT BY DEFAULT
22/107
22
ST72E331 ST72T331
Table 6. Interrupt Mapping
Source |
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Register |
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Exit |
Vector |
Priority |
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Description |
Flag |
from |
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Block |
Label |
Address |
Order |
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HALT |
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RESET |
Reset |
N/A |
N/A |
yes |
FFFEh-FFFFh |
Highest |
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TRAP |
Software |
N/A |
N/A |
no |
FFFCh-FFFDh |
Priority |
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NOT USED |
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FFFAh-FFFBh |
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NOT USED |
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FFF8h-FFF9h |
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EI0 |
Ext. Interrupt (Ports PA0:PA3) |
N/A |
N/A |
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FFF6h-FFF7h |
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EI1 |
Ext. Interrupt (Ports PF0:PF2) |
N/A |
N/A |
yes |
FFF4h-FFF5h |
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EI2 |
Ext. Interrupt (Ports PB0:PB3) |
N/A |
N/A |
FFF2h-FFF3h |
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EI3 |
Ext. Interrupt (Ports PB4:PB7) |
N/A |
N/A |
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FFF0h-FFF1h |
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NOT USED |
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FFEEh-FFEFh |
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SPI |
Transfer Complete |
SPISR |
SPIF |
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FFECh-FFEDh |
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Mode Fault |
MODF |
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Input Capture 1 |
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ICF1_A |
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Output Compare 1 |
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OCF1_A |
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TIMER A |
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TASR |
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FFEAh-FFEBh |
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Input Capture 2 |
ICF2_A |
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Output Compare 2 |
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Timer Overflow |
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TOF_A |
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Input Capture 1 |
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ICF1_B |
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Output Compare 1 |
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OCF1_B |
no |
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TIMER B |
Input Capture 2 |
TBSR |
ICF2_B |
FFE8h-FFE9h |
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Output Compare 2 |
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Timer Overflow |
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TOF_B |
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Transmit Buffer Empty |
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TDRE |
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SCI |
Transmit Complete |
SCISR |
TC |
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FFE6h-FFE7h |
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Receive Buffer Full |
RDRF |
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Idle Line Detect |
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IDLE |
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Lowest |
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Overrun |
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OR |
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Priority |
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EEPROM |
EEPROM End of Programming |
EEPCR |
E2ITE |
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FFE4h-FFE5h |
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NOT USED |
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FFE2h-FFE3h |
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NOT USED |
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FFE0h-FFE1h |
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23/107
23
ST72E331 ST72T331
4.4 POWER SAVING MODES
4.4.1 Introduction
There are three Power Saving modes. Slow Mode is selected by setting the relevant bits in the Miscellaneous register. Wait and Halt modes may be entered using the WFI and HALT instructions.
4.4.2 Slow Mode
In Slow mode, the oscillator frequency can be divided by a value defined in the Miscellaneous Register. The CPU and peripherals are clocked at this lower frequency. Slow mode is used to reduce power consumption, and enables the user to adapt clock frequency to available supply voltage.
4.4.3 Wait Mode
Wait mode places the MCU in a low power consumption mode by stopping the CPU. All peripherals remain active. During Wait mode, the I bit (CC Register) is cleared, so as to enable all interrupts. All other registers and memory remain unchanged. The MCU will remain in Wait mode until an Interrupt or Reset occurs, whereupon the Program Counter branches to the starting address of the Interrupt or Reset Service Routine.
The MCU will remain in Wait mode until a Reset or an Interrupt occurs, causing it to wake up.
Refer to Figure 18 below.
24/107
Figure 18. WAIT Flow Chart
WFI INSTRUCTION
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OSCILLATOR |
ON |
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PERIPH. CLOCK |
ON |
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CPU CLOCK |
OFF |
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I-BIT |
CLEARED |
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N |
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RESET |
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N |
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INTERRUPT |
Y |
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Y |
OSCILLATOR |
ON |
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PERIPH. CLOCK |
ON |
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CPU CLOCK |
ON |
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I-BIT |
SET |
4096 CPU CLOCK CYCLES DELAY
OSCILLATOR |
ON |
PERIPH. CLOCK |
ON |
CPU CLOCK |
ON |
I-BIT |
SET |
FETCH RESET VECTOR
OR SERVICE INTERRUPT
Note: Before servicing an interrupt, the CC register is pushed on the stack. The I-Bit is set during the interrupt routine and cleared when the CC register is popped.
24
ST72E331 ST72T331
POWER SAVING MODES (Cont’d)
4.4.4 Halt Mode
The Halt mode is the MCU lowest power consumption mode. The Halt mode is entered by executing the HALT instruction. The internal oscillator is then turned off, causing all internal processing to be stopped, including the operation of the on-chip peripherals. The Halt mode cannot be used when the watchdog is enabled, if the HALT instruction is executed while the watchdog system is enabled, a watchdog reset is generated thus resetting the entire MCU.
When entering Halt mode, the I bit in the CC Register is cleared so as to enable External Interrupts. If an interrupt occurs, the CPU becomes active.
The MCU can exit the Halt mode upon reception of an interrupt or a reset. Refer to the Interrupt Mapping Table. The oscillator is then turned on and a stabilization time is provided before releasing CPU operation. The stabilization time is 4096 CPU clock cycles.
After the start up delay, the CPU continues operation by servicing the interrupt which wakes it up or by fetching the reset vector if a reset wakes it up.
Figure 19. HALT Flow Chart
HALT INSTRUCTION
WATCHDOG |
Y |
WDG |
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RESET |
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ENABLED? |
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N |
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OSCILLATOR |
OFF |
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PERIPH. CLOCK |
OFF |
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CPU CLOCK |
OFF |
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I-BIT |
CLEARED |
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N |
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RESET |
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N |
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EXTERNAL |
Y |
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INTERRUPT1) |
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Y |
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OSCILLATOR |
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ON |
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PERIPH. CLOCK2) |
OFF |
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CPU CLOCK |
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ON |
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I-BIT |
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SET |
4096 CPU CLOCK CYCLES DELAY
OSCILLATOR ON
PERIPH. CLOCK |
ON |
CPU CLOCK |
ON |
I-BIT |
SET |
FETCH RESET VECTOR
OR SERVICE INTERRUPT
1)or some specific interrupts
2)if reset PERIPH. CLOCK = ON ; if interrupt PERIPH. CLOCK = OFF
Note: Before servicing an interrupt, the CC register is pushed on the stack. The I-Bit is set during the interrupt routine and cleared when the CC register is popped.
25/107
25
ST72E331 ST72T331
4.5 MISCELLANEOUS REGISTER
The Miscellaneous register allows to select the SLOW operating mode, the polarity of external interrupt requests and to output the internal clock.
Register Address: 0020h — Read/Write
Reset Value: 0000 0000 (00h)
7 |
0 |
PEI3 PEI2 MCO PEI1 PEI0 PSM1 PSM0 SMS
Bit 7:6 = PEI[3:2] External Interrupt EI3 and EI2 Polarity Options.
These bits are set and cleared by software. They determine which event on EI2 and EI3 causes the external interrupt according to Table 7.
Table 7. EI2 and EI3 External Interrupt Polarity
Options
MODE |
PEI3 |
PEI2 |
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Falling edge and low level |
0 |
0 |
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(Reset state) |
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Falling edge only |
1 |
0 |
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Rising edge only |
0 |
1 |
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Rising and falling edge |
1 |
1 |
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Note: Any modification of one of these two bits resets the interrupt request related to this interrupt vector.
Bit 5 = MCO Main Clock Out
This bit is set and cleared by software. When set, it enables the output of the Internal Clock on the PPF0 I/O port.
0 - PF0 is a general purpose I/O port.
1 - MCO alternate function (fCPU is output on PF0 pin).
26/107
Bit 4:3 = PEI[1:0] External Interrupt EI1 and EI0 Polarity Options.
These bits are set and cleared by software. They determine which event on EI0 and EI1 causes the external interrupt according to Table 8.
Table 8. EI0 and EI1 External Interrupt Polarity
Options
MODE |
PEI1 |
PEI0 |
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Falling edge and low level |
0 |
0 |
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(Reset state) |
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Falling edge only |
1 |
0 |
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Rising edge only |
0 |
1 |
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Rising and falling edge |
1 |
1 |
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Note: Any modification of one of these two bits resets the interrupt request related to this interrupt vector.
Bit 2:1 = PSM[1:0] Prescaler for Slow Mode
These bits are set and cleared by software. They determine the CPU clock when the SMS bit is set according to the following table.
Table 9. fCPU Value in Slow Mode
fCPU Value |
PSM1 |
PSM0 |
fOSC / 4 |
0 |
0 |
fOSC / 16 |
0 |
1 |
fOSC / 8 |
1 |
0 |
fOSC / 32 |
1 |
1 |
Bit 0 = SMS Slow Mode Select
This bit is set and cleared by software.
0:Normal Mode - fCPU = fOSC/ 2 (Reset state)
1:Slow Mode - the fCPU value is determined by the PSM[1:0] bits.
26
ST72E331 ST72T331
5 ON-CHIP PERIPHERALS
5.1 I/O PORTS
5.1.1 Introduction
The I/O ports offer different functional modes:
–transfer of data through digital inputs and outputs and for specific pins:
–analog signal input (ADC)
–alternate signal input/output for the on-chip peripherals.
–external interrupt generation
An I/O port is composed of up to 8 pins. Each pin can be programmed independently as digital input (with or without interrupt generation) or digital output.
5.1.2 Functional Description
Each port is associated to 2 main registers:
–Data Register (DR)
–Data Direction Register (DDR)
and some of them to an optional register:
– Option Register (OR)
Each I/O pin may be programmed using the corresponding register bits in DDR and OR registers: bit X corresponding to pin X of the port. The same correspondence is used for the DR register.
The following description takes into account the OR register, for specific ports which do not provide this register refer to the I/O Port Implementation Section 4.1.3. The generic I/O block diagram is shown on Figure 21.
5.1.2.1 Input Modes
The input configuration is selected by clearing the corresponding DDR register bit.
In this case, reading the DR register returns the digital value applied to the external I/O pin.
Different input modes can be selected by software through the OR register.
Notes:
1.All the inputs are triggered by a Schmitt trigger.
2.When switching from input mode to output mode, the DR register should be written first to output the correct value as soon as the port is configured as an output.
Interrupt function
When an I/O is configured in Input with Interrupt, an event on this I/O can generate an external Interrupt request to the CPU. The interrupt polarity is given independently according to the description mentioned in the Miscellaneous register or in the interrupt register (where available).
Each pin can independently generate an Interrupt request.
Each external interrupt vector is linked to a dedicated group of I/O port pins (see Interrupts section). If several input pins are configured as inputs to the same interrupt vector, their signals are logically ANDed before entering the edge/level detection block. For this reason if one of the interrupt pins is tied low, it masks the other ones.
5.1.2.2 Output Mode
The pin is configured in output mode by setting the corresponding DDR register bit.
In this mode, writing “0” or “1” to the DR register applies this digital value to the I/O pin through the latch. Then reading the DR register returns the previously stored value.
Note: In this mode, the interrupt function is disabled.
5.1.2.3 Digital Alternate Function
When an on-chip peripheral is configured to use a pin, the alternate function is automatically selected. This alternate function takes priority over standard I/O programming. When the signal is coming from an on-chip peripheral, the I/O pin is automatically configured in output mode (push-pull or open drain according to the peripheral).
When the signal is going to an on-chip peripheral, the I/O pin has to be configured in input mode. In this case, the pin’s state is also digitally readable by addressing the DR register.
Notes:
1.Input pull-up configuration can cause an unexpected value at the input of the alternate peripheral input.
2.When the on-chip peripheral uses a pin as input and output, this pin must be configured as an input (DDR = 0).
Warning: The alternate function must not be activated as long as the pin is configured as input with interrupt, in order to avoid generating spurious interrupts.
27/107
27
ST72E331 ST72T331
I/O PORTS (Cont’d)
5.1.2.4 Analog Alternate Function
When the pin is used as an ADC input the I/O must be configured as input, floating. The analog multiplexer (controlled by the ADC registers) switches the analog voltage present on the selected pin to the common analog rail which is connected to the ADC input.
It is recommended not to change the voltage level or loading on any port pin while conversion is in progress. Furthermore it is recommended not to have clocking pins located close to a selected analog pin.
Warning: The analog input voltage level must be within the limits stated in the Absolute Maximum Ratings.
5.1.3 I/O Port Implementation
The hardware implementation on each I/O port depends on the settings in the DDR and OR registers and specific feature of the I/O port such as ADC Input (see Figure 21) or true open drain. Switching these I/O ports from one state to another should be done in a sequence that prevents unwanted side effects. Recommended safe transitions are illustrated in Figure 20. Other transitions are potentially risky and should be avoided, since they are likely to present unwanted side-effects such as spurious interrupt generation.
Figure 20. Recommended I/O State Transition Diagram
INPUT |
INPUT |
OUTPUT |
OUTPUT |
with interrupt |
no interrupt |
open-drain |
push-pull |
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28/107
28
ST72E331 ST72T331
I/O PORTS (Cont’d)
Figure 21. I/O Block Diagram
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ALTERNATE ENABLE |
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ALTERNATE |
1 |
M |
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VDD |
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OUTPUT |
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U |
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0 |
X |
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P-BUFFER |
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(SEE TABLE BELOW) |
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DR |
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ALTERNATE |
PULL-UP |
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LATCH |
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ENABLE |
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PULL-UP |
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VDD |
ANALOG RAIL |
DATA BUS |
DDR |
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DIODE |
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CONDITION |
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(SEE TABLE BELOW) |
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LATCH |
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OR |
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PAD |
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ANALOG ENABLE |
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LATCH |
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(ADC) |
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COMMON |
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(SEE TABLE BELOW) |
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ANALOG |
GND |
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OR SEL |
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SWITCH |
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(SEE NOTE BELOW) |
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DDR SEL |
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N-BUFFER |
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ALTERNATE |
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DR SEL |
1 |
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ENABLE |
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M |
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U |
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X |
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GND |
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0 |
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ALTERNATE INPUT |
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CMOS |
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POLARITY |
FROM |
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SCHMITT TRIGGER |
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EXTERNAL |
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SEL |
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OTHER |
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INTERRUPT |
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BITS |
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SOURCE (EIx) |
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Table 10. Port Mode Configuration
Configuration Mode |
Pull-up |
P-buffer |
VDD Diode |
Floating |
0 |
0 |
1 |
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Pull-up |
1 |
0 |
1 |
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Push-pull |
0 |
1 |
1 |
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True Open Drain |
not present |
not present |
not present |
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Open Drain (logic level) |
0 |
0 |
1 |
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Legend:
0 - present, not activated
1 - present and activated
Notes:
–No OR Register on some ports (see register map).
–ADC Switch on ports with analog alternate functions.
29/107
29
ST72E331 ST72T331
I/O PORTS (Cont’d)
Table 11. Port Configuration
Port |
Pin name |
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Input (DDR = 0) |
Output (DDR = 1) |
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OR = 0 |
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OR = 1 |
OR = 0 |
OR =1 |
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PA0:PA2 1) |
floating* |
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pull-up with interrupt |
open-drain |
push-pull |
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Port A |
PA3 |
floating* |
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pull-up with interrupt |
open-drain |
push-pull |
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PA4:PA7 |
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floating* |
open drain, high sink capability |
|||
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Port B |
PB0:PB4 |
floating* |
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pull-up with interrupt |
open-drain |
push-pull |
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PB5:PB7 1) |
floating* |
|
pull-up with interrupt |
open-drain |
push-pull |
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Port C |
PC0:PC7 |
floating* |
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pull-up |
open-drain |
push-pull |
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Port D |
PD0:PD5 |
floating* |
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pull-up |
open-drain |
push-pull |
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PD6:PD7 1) |
floating* |
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pull-up |
open-drain |
push-pull |
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Port E |
PE0:PE1 |
floating* |
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pull-up |
open-drain |
push-pull |
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PE4:PE7 1) |
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floating*2) |
open drain, high sink capability3) |
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Port F |
PF0:PF2 |
floating* |
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pull-up with interrupt |
open-drain |
push-pull |
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PF4, PF6, PF7 |
floating* |
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pull-up |
open-drain |
push-pull |
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Notes:
1.ST72T331N only
2.For OTP/EPROM version, when OR=0: floating & when OR=1: reserved
3.For OTP/EPROM version, when OR=0: open-drain, high sink capability & when OR=1: reserved
* Reset state (The bits corresponding to unavailable pins are forced to 1 by hardware, this affects the reset status value).
Warning: All bits of the DDR register which correspond to unconnected I/Os must be left at their reset value. They must not be modified by the user otherwise a spurious interrupt may be generated.
30/107
30