Program memory - bytesFlash 60KFlash 32KROM 60KROM 32K
RAM (stack) - bytes2048 (256)1024 (256)2048 (256)1024 (256)
Operating Voltage 3.8V to 5.5V
Temp. Rangeup to -40°C to +125 °C
The ST72F521 and ST72521B devices are members of the ST7 microcontroller family designed for
mid-range applications with a CAN bus interface
(Controller Area Network).
All devices are based on a common industrystandard 8-bit core, featuring an enhan ced instruction set and are available with FLASH or ROM program memory.
Under software control, all devices can be placed
in WAIT, SLOW, ACTIVE-HALT or HALT mode,
Figure 1. Device Block Diagram
8-BIT CORE
ALU
RESET
V
PP
TLI
V
SS
V
DD
EVD
OSC1
OSC2
CONTROL
LVD
AVD
OSC
MCC/RTC/BEEP
reducing power consumption when the application
is in idle or stand-by state.
The enhanced instruction set and addressing
modes of the ST7 offer both power and flexibility to
software developers, enabling the design of highly
efficient and compact application code. In addition
to standard 8-bit data management, all ST7 micr ocontrollers feature true bit manipulation, 8x8 unsigned multiplication and indirect addressing
modes.
Related Documentation
AN1131: Migrating applications from ST72511/
311/314 to ST72521/321/324
PROGRAM
MEMORY
(32K - 60K Bytes)
RAM
(1024-2048 Bytes)
WATCHDOG
ADDRESS AND DATA BUS
I2C
PORT A
PA7:0
(8-bits)
PF7:0
(8-bits)
PE7:0
(8-bits)
PD7:0
(8-bits)
V
AREF
V
SSA
PORT F
TIMER A
BEEP
PORT E
CAN
SCI
PORT D
10-BIT ADC
PORT B
PWM ART
PORT C
TIMER B
SPI
1
PORT G
1
PORT H
1
On some devices only, see Device Summary on page 1
– Output: OD = open drain
Refer to “I/O PORTS” on page 47 for more details on the software configuration of the I/O ports.
The RESET configuration of each pin is shown in bold. This configuration is valid as long as the device is
9-PG0 I/OT
10-PG1 I/O T
11-PG2 I/O T
12-PG3 I/O T
139PB4 (HS)/ARTCLKI/O C
14 10 PB5/ARTIC1I/O C
15 11 PB6/ARTIC2I/O C
16 12 PB7I/O C
17 13 PD0 /AIN0I/O C
18 14 PD1/AIN1I/O C
19 15 PD2/AIN2I/O C
20 16 PD3/AIN3I/O C
21-PG6 I/O T
22-PG7 I/O T
23 17 PD4/AIN4I/O C
External clock input or Resonator oscillator inverter input
XXXXPort E0SCI Transmi t Data Out
XXXXPort E1SCI Receive Data In
XPort E2CAN Transmit Data Output
XXXXPort E3CAN Receive Data Input
ICC Clock
Output
ADC Analog
Input 15
Notes:
1. In the interrupt input column, “eiX” de fines the as sociate d extern al interrup t vector . If the weak pull-up
12/215
ST72F521, ST72521B
column (wpu) is merged with the interrupt column (int), then the I/O configuration is pull-up inter rupt input,
else the configuration is floating interrupt input.
2. In the open drain output column, “T” defines a true open drain I/O (P- Buffer and protection dio de to V
are not implemented). See See “I/O PORTS” on pa ge 47. and Section 12.8 I/O PORT PIN CHARACTER-
ISTICS for more details.
3. OSC1 and OSC2 pins connect a crystal/ceramic resonator, or an external source to the on-chip oscillator; see Section 1 INTRODUCTION and Section 12.5 CLOCK AND TIMING CHARACTERISTICS for
more details.
4. On the chip, each I/O port may have up to 8 pads. Pa ds that are not bond ed to external pins a re in input
pull-up configuration after reset. The configur ation of these pads must be kept at reset st ate to avoid added current consumption.
DD
13/215
ST72F521, ST72521B
3 REGISTER & MEMORY MAP
As shown in Figure 4, the MCU is capable of addressing 64K bytes of memories and I/O registers.
The available memory locations consist of 128
bytes of register locations, up to 2Kbytes of RAM
and up to 60Kbytes of user program memor y. The
RAM space includes up to 256 bytes for the stack
from 0100h to 01FFh.
The highest address bytes contain the user reset
and interrupt vectors.
Figure 4. Memory Map
0000h
007Fh
0080h
087Fh
0880h
0FFFh
1000h
FFDFh
FFE0h
FFFFh
HW Registers
(see Table 2)
RAM
(2048 or 1024 Bytes)
Reserved
Program Memory
(60K or 32K)
Interrupt & Reset Vectors
(see Table 7)
0080h
00FFh
0100h
01FFh
0200h
or 047Fh
or 067Fh
or 087Fh
IMPORTANT: Memory locations marked as “Reserved” must never be accessed. Accessing a reseved area can have unpredicta ble effects on the
device.
Related Documentation
AN 985: Executing Code in ST7 RAM
Short Addressing
RAM (zero page)
256 Bytes Stack
16-bit Addressing
1000h
RAM
8000h
FFFFh
60 KBytes
32 KBytes
14/215
Table 2. Hardware Register Map
ST72F521, ST72521B
AddressBlock
0000h
0001h
Port A
0002h
0003h
0004h
Port B
0005h
0006h
0007h
Port C
0008h
0009h
000Ah
Port D
000Bh
000Ch
000Dh
Port E
000Eh
000Fh
0010h
Port F
0011h
0012h
0013h
Port G
0014h
Register
Label
PADR
PADDR
PAOR
PBDR
PBDDR
PBOR
PCDR
PCDDR
PCOR
PDDR
PDDDR
PDOR
PEDR
PEDDR
PEOR
PFDR
PFDDR
PFOR
PGDR
2)
PGDDR
PGOR
Port A Data Register
Port A Data Direction Register
Port A Option Register
Port B Data Register
Port B Data Direction Register
Port B Option Register
Port C Data Register
Port C Data Direction Register
Port C Option Register
Port D Data Register
Port D Data Direction Register
Port D Option Register
Port E Data Register
Port E Data Direction Register
Port E Option Register
Port F Data Register
Port F Data Direction Register
Port F Option Register
Port G Data Register
Port G Data Direction Register
Port G Option Register
Register Name
Reset
Status
1)
00h
00h
00h
1)
00h
00h
00h
1)
00h
00h
00h
1)
00h
00h
00h
1)
00h
00h
00h
1)
00h
00h
00h
1)
00h
00h
00h
Remarks
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
2)
R/W
2)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0015h
0016h
0017h
0018h
0019h
001Ah
001Bh
001Ch
001Dh
001Eh
001Fh
0020h
0021h
0022h
0023h
Port H
2
C
I
SPI
1)
PHDR
2)
PHDDR
PHOR
I2CCR
I2CSR1
I2CSR2
I2CCCR
I2COAR1
I2COAR2
I2CDR
Port H Data Register
Port H Data Direction Register
Port H Option Register
2
I
C Control Register
2
C Status Register 1
I
2
I
C Status Register 2
2
C Clock Control Register
I
2
C Own Address Register 1
I
2
C Own Address Register2
I
2
C Data Register
I
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
R/W
R/W
R/W
R/W
Read Only
Read Only
R/W
R/W
R/W
R/W
Reserved Area (2 Bytes)
SPIDR
SPICR
SPICSR
SPI Data I/O Register
SPI Control Register
SPI Control/Status Register
xxh
0xh
00h
R/W
R/W
R/W
15/215
ST72F521, ST72521B
AddressBlock
0024h
0025h
0026h
0027h
0028hEICRExternal Interrupt Control Register00hR/W
0029hFLASHFCSRFlash Control/Status Register00hR/W
002AhWATCHDOGWDGCRWatchdog Control Register7FhR/W
002BhSICSRSystem Integrity Control/Status Register000x 000x b R/W
002Ch
Main Clock Control / Status Register
Main Clock Controller: Beep Control Register
Reserved Area (3 Bytes)
Timer A Control Register 2
Timer A Control Register 1
Timer A Control/Status Register
Timer A Input Capture 1 High Register
Timer A Input Capture 1 Low Register
Timer A Output Compare 1 High Register
Timer A Output Compare 1 Low Register
Timer A Counter High Register
Timer A Counter Low Register
Timer A Alternate Counter High Register
Timer A Alternate Counter Low Register
Timer A Input Capture 2 High Register
Timer A Input Capture 2 Low Register
Timer A Output Compare 2 High Register
Timer A Output Compare 2 Low Register
Reset
Status
FFh
FFh
FFh
FFh
00h
00h
00h
00h
xxxx x0xx b
xxh
xxh
80h
00h
FFh
FCh
FFh
FCh
xxh
xxh
80h
00h
Remarks
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Read Only
Read Only
R/W
R/W
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
R/W
Timer B Control Register 2
Timer B Control Register 1
Timer B Control/Status Register
Timer B Input Capture 1 High Register
Timer B Input Capture 1 Low Register
Timer B Output Compare 1 High Register
Timer B Output Compare 1 Low Register
Timer B Counter High Register
Timer B Counter Low Register
Timer B Alternate Counter High Register
Timer B Alternate Counter Low Register
Timer B Input Capture 2 High Register
Timer B Input Capture 2 Low Register
Timer B Output Compare 2 High Register
Timer B Output Compare 2 Low Register
00h
00h
xxxx x0xx b
xxh
xxh
80h
00h
FFh
FCh
FFh
FCh
xxh
xxh
80h
00h
R/W
R/W
R/W
Read Only
Read Only
R/W
R/W
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
R/W
R/W
ST72F521, ST72521B
AddressBlock
0050h
0051h
0052h
0053h
0054h
0055h
0056h
0057h
0058h
0059h
005Ah
005Bh
005Ch
005Dh
005Eh
005Fh
0060h
to
006Fh
0070h
0071h
0072h
SCI
CAN
ADC
Register
Label
SCISR
SCIDR
SCIBRR
SCICR1
SCICR2
SCIERPR
SCIETPR
CANISR
CANICR
CANCSR
CANBRPR
CANBTR
CANPSR
ADCCSR
ADCDRH
ADCDRL
Register Name
SCI Status Register
SCI Data Register
SCI Baud Rate Register
SCI Control Register 1
SCI Control Register 2
SCI Extended Receive Prescaler Register
Reserved area
SCI Extended Transmit Prescaler Register
Reserved Area (2 Bytes)
CAN Interrupt Status Register
CAN Interrupt Control Register
CAN Control / Status Register
CAN Baud Rate Prescaler Register
CAN Bit Timing Register
CAN Page Selection Register
First address
to
Last address of CAN page x
Control/Status Register
Data High Register
Data Low Register
PWM AR Timer Duty Cycle Register 3
PWM AR Timer Duty Cycle Register 2
PWM AR Timer Duty Cycle Register 1
PWM AR Timer Duty Cycle Register 0
PWM AR Timer Control Register
Auto-Reload Timer Control/Status Register
Auto-Reload Timer Counter Access Register
Auto-Reload Timer Auto-Reload Register
AR Timer Input Capture Control/Status Reg.
AR Timer Input Capture Register 1
AR Timer Input Capture Register 1
Reserved Area (2 Bytes)
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Read Only
Read Only
Legend: x=undefined, R/W=read/write
Notes:
1. The contents of the I/O port DR registers are readable only in output configuration. In input configuration, the values of the I/O pins are returned instead of the DR register contents.
2. The bits associated with unavailable pins must always keep their reset value.
17/215
ST72F521, ST72521B
4 FLASH PROGRAM MEMORY
4.1 Introduction
The ST7 dual voltage High Density Flash
(HDFlash) is a non-volatile memory that can be
electrically erased as a single block or by individual sectors and programmed on a Byte-by-Byte basis using an external V
supply.
PP
The HDFlash devices can be programmed and
erased off-board (plugged in a programming tool)
or on-board using ICP (In-Circuit Programming) or
IAP (In-Application Programming).
The array matrix organisation allows each sector
to be erased and reprogrammed without affecting
other sectors.
4.2 Main Features
■ Three Flash programming modes:
– Insertion in a programming tool. In this mode,
all sectors including option bytes can be programmed or erased.
– ICP (In-Circuit Programming). In this mode, all
sectors including option bytes can be programmed or erased without removing the device from the application board.
– IAP (In-Application Programming) In this
mode, all sectors except Sector 0, can be pr ogrammed or erased without removing the device from the application board and while the
application is running.
■ ICT (In-Circuit Testing) for downloading and
executing user application test patterns in RAM
■ Read-out protection
■ Register Access Security System (RASS) to
prevent accidental programming or erasing
4.3 Structure
The Flash memory is organised in sectors and can
be used for both code and data storage.
Depending on the overall Flash memory size in the
microcontroller device, there are up to three user
sectors (see Table 3). Each of these sectors can
be erased independently to avoid unnecessary
erasing of the whole Flash memory when only a
partial erasing is required.
The first two sectors have a fixed size of 4 Kbytes
(see Figure 5). They are mapped in the upper par t
of the ST7 addressing space so the reset and interrupt vectors are located in Sector 0 (F000hFFFFh).
Table 3. Sectors available in Flash devices
Flash Size (bytes)Available Sectors
4KSector 0
8KSectors 0,1
> 8KSectors 0,1, 2
4.3.1 Read-out Protection
Read-out protection, when selected, provides a
protection against Program Memory content extraction and against write access to Flash memory. Even if no protection can be considered as totally unbreakable, the feature provides a very high
level of protection for a general purpose microcontroller.
In flash devices, this protection is removed by reprogramming the option. In this case, the entire
program memory is first automatically erased and
the device can be reprogrammed.
Read-out protection selection depends on the device type:
– In Flash devices it is enabled and removed
through the FMP_R bit in the option byte.
– In ROM devices it is enabled by mask option
specified in the Option List.
Note: In flash devices, the LVD is not supported if
read-out protection is enabled.
Figure 5. Memory Map and Sector Address
4K10K24K48K
1000h
3FFFh
7FFFh
9FFFh
BFFFh
D7FFh
DFFFh
EFFFh
FFFFh
18/215
8K16K32K60K
2Kbytes
8Kbytes40 Kbytes
16 Kbytes
4 Kbytes
4 Kbytes
24 Kbytes
FLASH
MEMORY SIZE
SECTOR 2
52 Kbytes
SECTOR 1
SECTOR 0
FLASH PROGRAM MEMORY (Cont’d)
ST72F521, ST72521B
4.4 ICC Interface
ICC needs a minimum of 4 and up to 6 pins to be
connected to the programming tool (see Figure 6 ).
These pins are:
– RESET
–V
: device reset
: device power supply ground
SS
Figure 6. Typical ICC Interface
PROGRAMMING TOOL
APPLICATION
POWER SUPPLY
(See Note 3)
C
L2
DD
V
OPTIONAL
(See Note 4)
C
L1
OSC1
OSC2
ST7
Notes:
1. If the ICCCLK or ICCDATA pins are only used
as outputs in the application, no signal isolation is
necessary. As soon as the Programming Tool is
plugged to the board, even if an ICC session is not
in progress, the ICCCLK and ICCDATA pins are
not available for the application. If they are used as
inputs by the application, isolation such as a serial
resistor has to implemented in case another device forces the signal. Refer to the Programming
Tool documentation for recommended resistor values.
2. During the ICC session, the programming tool
must control the RESET
flicts between the programming tool and the application reset circuit if it drives more than 5mA at
high level (push pull output or pull-up resistor<1K).
A schottky diode can be used to isolate the ap plication RESET circuit in this case. When using a
classical RC network with R>1K or a reset man-
pin. This can lead to con-
– ICCCLK: ICC output serial clock pin
– ICCDATA: ICC input/output serial data pin
– ICCSEL/V
: programming voltage
PP
– OSC1(or OSCIN): main clock input for exter-
nal source (optional)
: application board power supply (option-
–V
DD
al, see Figure 6, Note 3)
ICC CONNECTOR
975 3
10kΩ
SS
V
ICCSEL/VPP
ICC Cable
1
246810
RESET
ICCCLK
HE10 CONNECTOR TYPE
ICCDATA
APPLICATION BOARD
ICC CONNECTOR
APPLICATION
RESET SOURCE
See Note 2
See Note 1
APPLICATION
I/O
agement IC with open drain output and pull-up resistor>1K, no additional components are needed.
In all cases the user must ensure that no ex ternal
reset is generated by the application during the
ICC session.
3. The use of Pin 7 of the ICC connector depends
on the Programming Tool architecture. This pin
must be connected when using most ST Programming Tools (it is used to monitor the application
power supply). Please refer to the Programming
Tool manual.
4. Pin 9 has to be connected to the OSC1 or OSCIN pin of the ST7 when the clock is not available
in the application or if the selected clock option is
not programmed in the option byte. ST7 devices
with multi-oscillator capability need to have OSC2
grounded in this case.
19/215
ST72F521, ST72521B
FLASH PROGRAM MEMORY (Cont’d)
4.5 ICP (In-Circuit Programming)
To perform ICP the microcontroller must be
switched to ICC (In-Circuit Communication) mode
by an external controller or programming tool.
Depending on the ICP code downlo aded in RAM,
Flash memory programming can be fully customized (number of bytes to program, program locations, or selection serial communication interface
for downloading).
When using an STMicroelectronics or third-party
programming tool that supports ICP and the specific microcontroller device, the user needs only to
implement the ICP hardware interface on the application board (see Figure 6). For more details on
the pin locations, refer to the device pinout description.
4.6 IAP (In-Application Programming)
This mode uses a BootLoader program previously
stored in Sector 0 by the user (in ICP mode or by
plugging the device in a programming tool).
This mode is fully controlled by user software. This
allows it to be adapted to the user application, (user-defined strategy for entering programming
mode, choice of communications protocol used to
fetch the data to be stored, etc.). For exampl e, it is
possible to download code from the SPI, SCI, USB
or CAN interface and program it in the Flash. IAP
mode can be used to program any of the Flash
sectors except Sector 0, which is write/erase protected to allow recovery in case errors occur during the programming operation.
4.7 Related Documentation
For details on Flash programming and ICC protocol, refer to the ST7 Flash Programming Reference Manual and to the ST7 ICC Protocol Reference Manual
This register is reserved for use by Programming
Tool software. It controls the Flash programming
and erasing operations.
Figure 7. Flash Control/Status Register Address and Reset Value
Address
(Hex.)
0029h
Register
Label
FCSR
Reset Value00000000
76543210
20/215
5 CENTRAL PROCESSING UNIT
ST72F521, ST72521B
5.1 INTRODUCTION
This CPU has a full 8-bit architecture and contains
six internal registers allowing efficient 8-bit data
manipulation.
5.2 MAIN FEATURES
■ Enable executing 63 basic instructions
■ Fast 8-bit by 8-bit multiply
■ 17 main addressing modes (with indirect
addressing mode)
■ Two 8-bit index registers
■ 16-bit stack pointer
■ Low power HALT and WAIT modes
■ Priority maskable hardware interrupts
■ Non-maskable software/ha r dwa r e in te r ru pt s
Figure 8. CPU Registers
5.3 CPU REGISTERS
The 6 CPU registers shown in Figure 8 are not
present in the memory mapping and are acce ssed
by specific instructions.
Accumulator (A)
The Accumulator is an 8-bit general purpose register used to hold operands and the results of the
arithmetic and logic calculations and to manipulate
data.
Index Registers (X and Y)
These 8-bit registers are used to create effective
addresses or as temporary storage areas for data
manipulation. (The Cross-Assem bler generates a
precede instruction (PRE) to indicate that the following instruction refers to the Y register.)
The Y register is not affected by the interrupt automatic procedures.
Program Counter (PC)
The program counter is a 16-bit register conta ining
the address of the next instruction to be executed
by the CPU. It is made of two 8-bit registers PCL
(Program Counter Low which is the LSB) and PCH
(Program Counter High which is the MSB).
70
RESET VALUE = XXh
70
RESET VALUE = XXh
70
RESET VALUE = XXh
158
RESET VALUE = RESET VECTOR @ FFFEh-FFFFh
15
RESET VALUE = STACK HIGHER ADDRESS
PCH
RESET VALUE =
7
70
1C1I1HI0NZ
1X11X1XX
70
8
PCL
0
ACCUMULATOR
X INDEX REGISTER
Y INDEX REGISTER
PROGRAM COUNTER
CONDITION CODE REGISTER
STACK POINTER
X = Undefined Value
21/215
ST72F521, ST72521B
CENTRAL PROCESSING UNIT (Cont’d)
Condition Code Register (CC)
Read/Write
Reset Value: 111x1xxx
70
11I1HI0NZ
C
The 8-bit Condition Code register contains the interrupt masksand four flags representative of the
result of the instruction just executed. This reg ister
can also be handled by the PUSH and POP instructions.
These bits can be individually tested and/or controlled by specific instructions.
Arithmetic Management Bits
Bit 4 = H Half carry.
This bit is set by hardware when a carry occurs be-
tween bits 3 and 4 of the ALU during an ADD or
ADC instructions. It is reset by hardware during
the same instructions.
0: No half carry has occurred.
1: A half carry has occurred.
This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD arithmetic subroutines.
Bit 2 = N Negative.
This bit is set and cleared by hardware. I t is r epr e-
sentative of the result sign of th e last arithmetic,
logical or data manipulation. It’s a copy of the re-
th
bit.
sult 7
0: The result of the last operation is positive or null.
1: The result of the last operation is negative
(i.e. the most significant bit is a logic 1).
This bit is accessed by the JRMI and JRPL instructions.
Bit 1 = Z Zero.
This bit is set and cleared by hardware. This bit in-
dicates that the result of the last arithmetic, logical
or data manipulation is zero.
0: The result of the last operation is different from
zero.
1: The result of the last operation is zero.
This bit is accessed by the JREQ and JRNE test
instructions.
Bit 0 = C Carry/borrow.
This bit is set and cleared by hardware and software. It indicates an overflow or an underflow has
occurred during the last arithmetic operation.
0: No overflow or underflow has occurred.
1: An overflow or underflow has occurred.
This bit is driven by the SCF and RCF instructions
and tested by the JRC and JRNC instructions. It is
also affected by the “bit test and branch”, shift and
rotate instructions.
Interrupt Management Bits
Bit 5,3 = I1, I0 Interrupt
The combination of the I1 and I0 bits gives t he cur-
These two bits are set/cleared by hardware when
entering in interrupt. The loaded value is given by
the corresponding bits in the interrupt software priority registers (IxSPR). They can be also set/
cleared by software with the RIM, SIM, IRET,
HALT, WFI and PUSH/POP instructions.
See the interrupt management chapter for more
details.
22/215
CENTRAL PROCESSING UNIT (Cont’d)
ST72F521, ST72521B
Stack Pointer (SP)
Read/Write
Reset Value: 01 FFh
158
00000001
The least significant byte of the Stack Pointer
(called S) can be directly accessed by a LD instruction.
Note: When the lower limit is exceeded, the Stack
Pointer wraps around to the stack upper limit, without indicating the stack overflow. The previously
stored information is then overwritten and therefore lost. The stack also wraps in case of an underflow.
70
SP7SP6SP5SP4SP3SP2SP1
SP0
The stack is used to save the return address during a subroutine call and the CPU context during
an interrupt. The user may also directly manipulate
the stack by means of the PUSH and POP instruc-
The Stack Pointer is a 16-bit register whic h is always pointing to the next free location in the stack.
It is then decremented after d ata has been pushed
onto the stack and incremented before data is
popped from the stack (see Figure 9).
Since the stack is 256 bytes deep, the 8 most significant bits are forced by hardware. Following an
MCU Reset, or after a Reset Stack Pointer instruction (RSP), the Stack Pointer contains its reset value (the SP7 to SP0 bits are set) which is the stack
tions. In the case of an interrupt, the PCL is st ored
at the first location pointed to by the SP . Then th e
other registers are stored in the next locations as
shown in Figure 9.
– When an interrup t is received, the SP is decre-
mented and the context is pushed on the stack.
– On return from interrupt, the SP is incremented
and the context is popped from the stack.
A subroutine call occupies two locations and an interrupt five locations in the stack area.
The device includes a range of utility features for
securing the application in critical situations (for
example in case of a power brown-out), and reducing the number of external components. An
overview is shown in Figure 11.
For more details, refer to dedicated parametric
section.
– Main supply Low voltage detection (LVD)
– Auxiliary Voltage detector (AVD) with interrupt
capability for monitoring the main supply or
the EVD pin
Figure 11. Clock, Reset and Supply Block Diagram
6.1 PHASE LOCKED LOOP
If the clock frequency input to the PLL is in the
range 2 to 4 MHz, the PLL can be used to m ult iply
the frequency by two to obtain an f
OSC2
of 4 to 8
MHz. The PLL is enabled by option byte. If the PLL
is disabled, then f
OSC2 = fOSC
/2.
Caution: The PLL is not recommended for applications where timing accuracy is required. See
“PLL Characteristics” on page 177.
Figure 10. PLL Block Diagram
f
OSC
PLL x 2
/ 2
0
1
PLL OPTION BIT
f
OSC2
OSC2
OSC1
RESET
V
SS
V
DD
EVD
MULTI-
OSCILLATOR
(MO)
RESET SEQUENCE
MANAGER
(RSM)
f
OSC
PLL
(option)
SYSTEM INTEGRITY MANAGEMENT
AVD Interrupt Request
SICSR
AVD
AVD AVD
S
0
1
IE
LVD
0
F
RF
LOW VOLTAGE
DETECTOR
AUXILIARY VOLTAGE
DETECTOR
00
(LVD)
(AVD)
f
OSC2
WDG
RF
MAIN CLOCK
CONTROLLER
WITH REALTIME
CLOCK (MCC/RTC)
WATCHDOG
TIMER (WDG)
f
CPU
24/215
6.2 MULTI-OSCILLATOR (MO)
ST72F521, ST72521B
The main clock of the ST7 can be generated by
three different source types coming fro m the multioscillator block:
■ an external source
■ 4 crystal or ceramic resonator oscillators
■ an internal high frequency RC oscillator
Each oscillator is optimized for a given frequency
range in terms of consumption and is selectable
through the option byte. The associated hardware
configurations are shown in Table 4. Refer to the
electrical characteristics section for more details.
Caution: The OSC1 and/or OSC2 pins must not
be left unconnected. For the purposes of Failure
Mode and Effect Analysis, it should be noted that if
the OSC1 and/or OSC2 pins are left unconnected,
the ST7 main oscillator may start and, in this configuration, could generate an f
clock frequency
OSC
in excess of the allowed maximum (>16MHz.),
putting the ST7 in an unsafe/undefined state. The
product behaviour must therefore be considered
undefined when the OSC pins are left unconnected.
External Clock Source
In this external clock mode, a clock signal (square,
sinus or triangle) with ~50% duty cycle has to drive
the OSC1 pin while the OSC2 pin is tied to ground.
Crystal/Ceramic Oscillators
This family of oscillators has the advantage of producing a very accurate rate on the main clock of
the ST7. The selection within a list of 4 oscillators
with different frequency ranges has to be done by
option byte in order to reduce consumption (refer
to se ction 14.1 on page 201 for more details on the
frequency ranges). In this mode of the multi-oscillator, the resonator and the load capacitors have
to be placed as close as possible to the oscillator
pins in order to minimize output distortion and
start-up stabilization time. The loading capacitance values must be adjusted according to the
selected oscillator.
These oscillators are not stopped during the
RESET phase to avoid losing time in the oscillator
start-up phase.
Internal RC Oscillator
This oscillator allows a low cost solution for the
main clock of the ST7 using only an internal resistor and capacitor. Internal RC oscillator mode has
the drawback of a lower frequency accuracy and
should not be used in applications that require accurate timing.
In this mode, the two oscillator pins have to be tied
to ground.
The reset sequence manager includes three RESET sources as shown in Figure 13:
■ External RESET source pulse
■ Internal LVD RESET (Low Voltage Detection)
■ Internal WATCHDOG RESET
These sources act on the RESET
pin and it is al-
ways kept low during the delay phase.
The RESET service routine vector is fixed at ad-
dresses FFFEh-FFFFh in the ST7 memory map.
The basic RESET sequence consists of 3 phases
as shown in Figure 12:
■ Active Phase depending on the RESET source
■ 256 or 4096 CPU clock cycle delay (selected by
option byte)
■ RESET vector fetch
The 256 or 4096 CPU clock cycle delay allows the
oscillator to stabilise and ensures that recovery
has taken place from the Reset state. The shorter
or longer clock cycle delay should be selected by
option byte to correspond to the stabilization time
of the external oscillator used in the application
(see section 14.1 on page 201).
Figure 13. Reset Block Diagram
The RESET vector fetch phase duration is 2 clock
cycles.
Figure 12. RESET Sequence Phases
RESET
Active Phase
INTERNAL RESET
256 or 4096 CLOCK CYCLES
6.3.2 Asynchronous External RESET
The RESET
output with integrated R
pin is both an input and an open-drain
weak pull-up resistor.
ON
FETCH
VECTOR
pin
This pull-up has no fixed value but varies in accordance with the input voltage. It
can be pulled
low by external circuitry to reset the device. See
“CONTROL PIN CHARACTERISTICS” on
page 185 for more details.
A RESET signal originating from an external
source must have a duration of at least t
h(RSTL)in
in
order to be recognized (see Figure 14). This detection is asynchronous and therefore the MCU
can enter reset state even in HALT mode.
RESET
V
DD
R
ON
Filter
PULSE
GENERATOR
INTERNAL
RESET
WATCHDOG RESET
LVD RESET
26/215
RESET SEQUENCE MANAGER (Cont’d)
The RESET
pin is an asynchronous signal which
plays a major role in EMS performance. In a noisy
environment, it is recommended to follow the
guidelines mentioned in the electrical characteristics section.
If the external RESET
t
w(RSTL)out
(see short ext. Reset in Figure 14), the
signal on the RESET
pulse is shorter than
pin may be stretched. Otherwise the delay will not be applied (see long ext.
Reset in Figure 14). Starting from the external RESET pulse recognition, the device RESET
pin acts
as an output that is pulled low during at least
t
w(RSTL)out
.
6.3.3 External Power-On RESET
If the LVD is disabled by option byte, to st art up the
microcontroller correctly, the user must ensure by
means of an external reset circuit that the reset
signal is held low until V
level specified for the selected f
is over the minimum
DD
frequency.
OSC
(see “OPERATING CONDITIONS” on page 167)
Figure 14. RESET Sequences
V
DD
ST72F521, ST72521B
A proper reset signal for a slow rising V
can generally be provided by an external RC network connected to the RESET
pin.
6.3.4 Internal Low Voltage Detector (LVD)
RESET
Two different RESET sequences caused by the internal LVD circuitry can be distinguished:
■ Power-On RESET
■ Voltage Drop RESET
The device RESET
pulled low when V
V
DD<VIT-
(falling edge) as shown in Figure 14.
The LVD filters spikes on V
pin acts as an output that is
DD<VIT+
(rising edge) or
larger than t
DD
avoid parasitic resets.
6.3.5 Internal Watchdog RESET
The RESET sequence generated by a internal
Watchdog counter overflow is shown in Figure 14.
Starting from the Watchdog counter under flow, the
device RESET
low during at least t
pin acts as an output that is pulled
w(RSTL)out
.
supply
DD
g(VDD)
to
V
IT+(LVD)
V
IT-(LVD)
EXTERNAL
RESET
SOURCE
RESET PIN
WATCHDOG
RESET
RUN
LVD
RESET
ACTIVE PHASE
RUN
t
w(RSTL)out
t
h(RSTL)in
SHORT EXT.
RESET
ACTIVE
PHASE
LONG EXT.
RESET
RUNRUNRUN
t
w(RSTL)out
t
h(RSTL)in
DELAY
ACTIVE
PHASE
WATCHDOG UNDERFLOW
INTERNAL RESET (256 or 4096 T
VECTOR FETCH
WATCHDOG
ACTIVE
PHASE
RESET
t
w(RSTL)out
CPU
)
27/215
ST72F521, ST72521B
6.4 SYSTEM INTEGRITY MANAGEMENT (SI)
The System Integrity Management block contains
the Low Voltage Detector (LVD) and Auxiliary Voltage Detector (AVD) functions. It is managed by
the SICSR register.
6.4.1 Low Voltage Detector (LVD)
The Low Voltage Detector function (LVD) generates a static reset when the V
below a V
reference value. This means that it
IT-
supply voltage is
DD
secures the power-up as well as the po wer-down
keeping the ST7 in reset.
The V
than the V
reference value for a voltage drop is lower
IT-
reference value for power-on in order
IT+
to avoid a parasitic reset when the MCU starts running and sinks current on the supply (hysteresis).
The LVD Reset circuitry generates a reset when
is below:
V
DD
when VDD is rising
–V
IT+
when VDD is falling
–V
IT-
The LVD function is illustrated in Figure 15.
The voltage threshold can be configured by option
byte to be low, medium or high.
Provided the minimum V
the oscillator frequency) is above V
value (guaranteed for
DD
, the MCU
IT-
can only be in two modes:
– under full software control
– in static safe reset
In these conditions, secure operation is always ensured for the application without the need for external reset hardware.
During a Low Voltage Detector Reset, the RESET
pin is held low, thus permitting the MCU to reset
other devices.
Notes:
The LVD allows the device to be used without any
external RESET circuitry.
If the medium or low thresholds are se lected, the
detection may occur outside the specified operating voltage range. Below 3.8V, device operation is
not guaranteed.
The LVD is an optional function which can be selected by option byte.
It is recommended to make sure that the V
DD
supply voltage rises monotonously when the device is
exiting from Reset, to ensure the application functions properly.
Figure 15. Low Voltage Detector vs Reset
V
DD
V
IT+
V
IT-
RESET
V
hys
28/215
SYSTEM INTEGRITY MANAGEMENT (Cont’d)
6.4.2 Auxiliary Voltage Detector (AVD)
The Voltage Detector function (AVD) is based on
an analog comparison between a V
V
IT+(AVD)
reference value and the VDD main sup-
IT-(AVD)
ply or the external EVD pin voltage level (V
The V
than the V
reference value for falling voltage is lower
IT-
reference value for rising voltage in
IT+
and
EVD
order to avoid parasitic detection (hysteresis).
The output of the AVD comparator is directly read-
able by the application software through a real
time status bit (AVDF) in the SICSR register. This
bit is read only.
Caution: The AVD function is active only if the
LVD is enabled through the option byte.
6.4.2.1 Monitoring the V
Main Supply
DD
This mode is selected by clearing the AVDS bit in
the SICSR register.
The AVD voltage threshold value is relative to the
selected LVD threshold configured by option byte
(see section 14.1 on page 201).
If the AVD interrupt is enabled, an interrupt is generated when the voltage crosses the V
V
IT-(AVD)
threshold (AVDF bit toggles).
Figure 16. Using the AVD to Monitor V
IT+(AVD)
or
(AVDS bit=0)
DD
ST72F521, ST72521B
In the case of a drop in voltage, the AVD interrupt
acts as an early warning, allowing soft ware to shut
down safely before the LVD resets the microcontroller. See Figure 16.
).
The interrupt on the rising edge is used to inform
the application that the V
If the voltage rise time t
CPU cycles (depending on the reset delay selected by option byte), no AVD interrupt will be generated when V
is greater than 256 or 4096 cycles then:
If t
rv
IT+(AVD)
is reached.
– If the AVD interrupt is enabled before the
V
IT+(AVD)
threshold is reached, then 2 AVD interrupts will be received: the first when the AVDIE
bit is set, and the second when the threshold is
reached.
– If the AVD interrupt is enabled after the V
threshold is reached then only one AVD interrupt
will occur.
warning state is over.
DD
is less than 256 or 4096
rv
IT+(AVD)
V
DD
Early Warning Interrupt
(Power has dropped, MCU not
not yet in reset)
V
V
IT+(AVD)
V
IT-(AVD)
V
IT+(LVD)
V
IT-(LVD)
AVDF bit00RESET VALUE
AVD INTERRUPT
REQUEST
IF AVDIE bit = 1
LVD RESET
1
hyst
INTERRUPT PROCESS
t
VOLTAGE RISE TIME
rv
1
INTERRUPT PROCESS
29/215
ST72F521, ST72521B
SYSTEM INTEGRITY MANAGEMENT (Cont’d)
6.4.2.2 Monitoring a Voltage on the EVD pin
This mode is selected by setting the AVDS bit in
the SICSR register.
The AVD circuitry can generate an interrupt when
the AVDIE bit of the SICSR register is set. Th is interrupt is generated on the rising and falling edges
Figure 17. Using the Voltage Detector to Monitor the EVD pin (AVDS bit=1)
V
EVD
V
V
IT+(EVD)
V
IT-(EVD)
hyst
of the comparator output. This me ans it is generated when either one of these two events occur:
–V
–V
rises up to V
EVD
falls down to V
EVD
IT+(EVD)
The EVD function is illustrated in Figure 17.
For more details, refer to the Electric al Charact er-
istics section.
IT-(EVD)
AVDF001
AVD INTERRUPT
REQUEST
IF AVDIE = 1
INTERRUPT PROCESS
INTERRUPT PROCESS
30/215
SYSTEM INTEGRITY MANAGEMENT (Cont’d)
6.4.3 Low Power Modes
Mode Description
WAIT
HALTThe CRSR register is frozen.
No effect on SI. AVD interrupts cause the
device to exit from Wait mode.
6.4.3.1 Interrupts
The AVD interrupt event generates an interrupt if
the corresponding Enable Control Bit (AVDIE) is
ST72F521, ST72521B
set and the interrupt mask in the CC register is reset (RIM instruction).
Flag
Enable
Control
Bit
Interrupt Event
AVD event AVDF AVDIEYesNo
Event
Exit
from
Wait
Exit
from
Halt
31/215
ST72F521, ST72521B
SYSTEM INTEGRITY MANAGEMENT (Cont’d)
6.4.4 Register Description
SYSTEM INTEGRITY (SI) CONTROL/STATUS REGISTER (SICSR)
Read /Write
Reset Value: 000x 000x (00h)
70
AVD
AVD
S
IE
AVDFLVD
RF
000
WDG
RF
ed by the LVD block. It is set by hardware (LVD reset) and cleared by software (writing zero). See
WDGRF flag description for more details. When
the LVD is disabled by OPTION BYTE, the LVDRF
bit value is undefined.
Bits 3:1 = Reserved, must be kept cleared.
Bit 7 = AVDS Voltage Detection selection
This bit is set and cleared by software. Voltage Detection is available only if the LVD is enabled by
option byte.
0: Voltage detection on V
supply
DD
1: Voltage detection on EVD pin
Bit 6 = AVDIE Voltage Detector interrupt enable
This bit is set and cleared by software. It enables
an interrupt to be generated when the AVDF flag
changes (toggles). The pending interrupt information is automatically cleared when software enters
the AVD interrupt routine.
0: AVD interrupt disabled
1: AVD interrupt enabled
Bit 5 = AVDF Voltage Detector flag
This read-only bit is set and cleared by hardware.
If the AVDIE bit is set, an interrup t requ est is gen erated when the AVDF bit changes value. Refer to
Figure 16 and to Section 6.4.2.1 for additional de-
tails.
0: V
1: V
DD
DD
or V
or V
EVD
EVD
over V
under V
IT+(AVD)
IT-(AVD)
threshold
threshold
Bit 4 = LVDRF LVD reset flag
This bit indicates that the last Reset was generat-
Bit 0 = WDGRF Watchdog reset flag
This bit indicates that the last Reset was generated by the Watchdog peripheral. It is set by hardware (watchdog reset) and cleared by software
(writing zero) or an LVD Reset (to ensure a stable
cleared state of the WDGRF flag when CPU
starts).
Combined with the LVDRF flag information, the
flag description is given by the following table.
RESET SourcesLVDRFWDGRF
External RESET
Watchdog01
LVD1X
pin00
Application notes
The LVDRF flag is not cleared when another RESET type occurs (external or watchdog), the
LVDRF flag remains set to keep trace of the original failure.
In this case, a watchdog re set c an b e de tect ed by
software while an external reset can not.
CAUTION: When the LVD is not activated with the
associated option byte, the WDGRF flag can not
be used in the application.
32/215
7 INTERRUPTS
ST72F521, ST72521B
7.1 INTRODUCTION
The ST7 enhanced interrupt management provides the following features:
■ Hardware interrupts
■ Software interrupt (TRAP)
■ Nested or concurrent interrupt management
with flexible interrupt priority and level
management:
– Up to 4 software programmable nesting levels
– Up to 16 interrupt vectors fixed by hardware
– 2 non maskable events: RESET, TRAP
– 1 maskable Top Level event: TLI
This interrupt management is based on:
– Bit 5 and bit 3 of the CPU CC register (I1:0),
– Interrupt software priority registers (ISPRx),
– Fixed interrupt vector addresses located at the
high addresses of the memory map (FFE0h to
FFFFh) sorted by hardware priority order.
This enhanced interrupt controller guarantees full
upward compatibility with the standard (not nested) ST7 interrupt controller.
7.2 MASKING AND PROCESSING FLOW
The interrupt masking is managed by the I1 and I0
bits of the CC register and the ISPRx registers
which give the interrupt software priority level of
each interrupt vector (see Table 5). The processing flow is shown in Figure 18
When an interrupt request has to be serviced:
– Normal processing is suspended at the end of
the current instruction execution.
– The PC, X, A and CC registers are saved onto
the stack.
– I1 and I0 bits of CC register are set according to
the corresponding values in the ISPRx registers
of the serviced interrupt vector.
– The PC is then loaded with the interrupt vector of
the interrupt to service and the first instruction of
the interrupt service routine is fetched (refer to
“Interrupt Mapping” table for vector addresses).
The interrupt service routine should end with the
IRET instruction which causes the contents of the
saved registers to be recovered from the stack.
Note: As a consequence of the IRET instruction,
the I1 and I0 bits will be restored from the stack
and the program in the previous level will resume.
As several interrupts can be pending at the same
time, the interrupt to be taken into account is determined by the following two-step process:
– the highest software priority interrupt is serviced,
– if several interrupts have the same software pri-
ority then the interrupt with the highest hardware
priority is serviced first.
Figure 19 describes this decision process.
Figure 19. Priority Decision Process
PENDING
INTERRUPTS
Same
HIGHEST HARDWARE
PRIORITY SERVICED
SOFTWARE
PRIORITY
HIGHEST SOFTWARE
PRIORITY SERVICED
Different
When an interrupt request is not serviced immediately, it is latched and then processed when its
software priority combined with the hardware priority becomes the highest one.
Note 1: The hardware priority is exclusive while
the software one is not. This allows the previous
process to succeed with only one interrupt.
Note 2: TLI, RESET and TRAP can be considered
as having the highest software p riority in th e decision process.
Different Interrupt Vector Sources
Two interrupt source types are managed by the
ST7 interrupt controller: the non-maskable type
(RESET, TRAP) and the maskable type (external
or from internal peripherals).
Non-Maskable Sources
These sources are processed regardless of the
state of the I1 and I0 bits of the CC register (see
Figure 18). After stacking the PC, X, A and CC
registers (except for RESET), the corresponding
vector is loaded in the PC register and the I1 and
I0 bits of the CC are set to disable interrupts (level
3). These sources allow the processor to exit
HALT mode.
■ TRAP (Non Maskable Software Interrupt)
This software interrupt is serviced when the TRAP
instruction is executed. It will be serviced according to the flowchart in Figure 18.
Caution: TRAP can be interrupted by a TLI.
■ RESET
The RESET source has the highest priority in the
ST7. This means that the first current routine has
the highest software priority (level 3) and th e highest hardware priority.
See the RESET chapter for more details.
Maskable Sources
Maskable interrupt vector sources can be serviced
if the corresponding interrupt is enabled and if its
own interrupt software priority (in ISPRx registers)
is higher than the one currently being serviced (I1
and I0 in CC register). If any of these two conditions is false, the interrupt is latched and thus remains pending.
■ TLI (Top Level Hardware Interrupt)
This hardware interrupt occurs when a specific
edge is detected on the dedicated TLI pin. It will be
serviced according to the flowchart in Figure 18 as
a trap.
Caution: A TRAP instruction must not be used in a
TLI service routine.
■ External Interrupts
External interrupts allow the processor to exit from
HALT low power mode. External interrup t sensitivity is software selectable through the External Interrupt Control register (EICR).
External interrupt triggered on edge will be latched
and the interrupt request automatically cleared
upon entering the interrupt service routine.
If several input pins of a group connected to the
same interrupt line are selected simultaneously,
these will be logically ORed.
■ Peripheral Interrupts
Usually the peripheral interrupts cause the MCU to
exit from HALT mode except those mentioned in
the “Interrupt Mapping” table. A peripheral interrupt occurs when a specific flag is se t in the peripheral status registers and if the corresponding
enable bit is set in the peripheral control register.
The general sequence for clearing an interrupt is
based on an access to the status register followed
by a read or write to an associated register.
Note: The clearing sequence resets the internal
latch. A pending interrupt (i.e. waiting for being
serviced) will therefore be lost if the clear sequence is executed.
34/215
INTERRUPTS (Cont’d)
ST72F521, ST72521B
7.3 INTERRUPTS AND LOW POWER MODES
All interrupts allow the processor to exit the WAIT
low power mode. On the contrary, only external
and other specified interrupts allow the processor
to exit from the HALT modes (see column “Exit
from HALT” in “Interrupt Mapping” table). When
several pending interrupts are present wh ile exiting HALT mode, the first one serviced can only be
an interrupt with exit from HALT mode capability
and it is selected through the same decision proc ess shown in Figure 19.
Note: If an interrupt, that is not able to Exit from
HALT mode, is pending with the highest priority
when exiting HALT mode, this interrupt is serviced
after the first one serviced.
Figure 20. Concurrent Interrupt Management
TRAP
IT0
TRAP
IT1
RIM
IT2
IT2
IT1
IT4
IT3
IT1
HARDWARE PRIORITY
MAIN
11 / 10
7.4 CONCURRENT & NESTED MANAGEMENT
The following Figure 20 and Figure 21 show two
different interrupt management modes. Th e f irst is
called concurrent mode and does not allow an interrupt to be interrupted, unlike the nested mode in
Figure 21. The interrupt hardware priority is given
in this order from the lowest to the highest: MAIN,
IT4, IT3, IT2, IT1, IT0, TLI. The software priority is
given for each interrupt.
Warning: A stack overflow may occur without notifying the software of the failure.
SOFTWARE
PRIORITY
LEVEL
IT0
IT3
IT4
MAIN
3
3
3
3
3
3
3/0
I1
11
11
11
11
11
11
10
I0
USED STACK = 10 BYTES
Figure 21. Nested Interrupt Management
IT4
IT3
TRAP
TRAP
IT0
HARDWARE PRIORITY
MAIN
RIM
IT2
IT2
IT1
IT1
IT4
11 / 10
IT4
IT0
IT3
IT1
SOFTWARE
PRIORITY
LEVEL
IT2
10
MAIN
I1I0
3
3
2
1
3
3
3/0
11
11
00
01
11
11
USED STACK = 20 BYTES
35/215
ST72F521, ST72521B
INTERRUPTS (Cont’d)
7.5 INTERRUPT REGISTER DESCRIPTION
INTERRUPT SOFTWARE PRIORITY REGISTERS (ISPRX)
CPU CC REGISTER INTERRUPT BITS
Read /Write
Reset Value: 111x 1010 (xAh)
70
11I1HI0NZC
Bit 5, 3 = I1, I0 Software Interrupt Priority
These two bits indicate the current interrupt soft-
These two bits are set/cleared by hardware when
entering in interrupt. The loaded value is given by
the corresponding bits in the interrupt software p riority registers (ISPRx).
They can be also set/cleared by software with the
RIM, SIM, HALT, WFI, IRET and PUSH/POP instructions (see “Interrupt Dedicated Instruction
Set” table).
*Note: TLI, TRAP and RESET events can interrupt
a level 3 program.
Read/Write (bit 7:4 of ISPR3 are read only)
Reset Value: 1111 1111 (FFh)
70
ISPR0I1_3 I0_3 I1_2 I0_2 I1_1 I0_1 I1_0 I0_0
ISPR1I1_7 I0_7 I1_6 I0_6 I1_5 I0_5 I1_4 I0_4
ISPR2I1_11 I0_11 I1_10 I0_10 I1_9 I0_9 I1_8 I0_8
ISPR31111I1_13 I0_13 I1_12 I0_12
These four registers contain the interrupt software
priority of each interrupt vector.
– Each interrupt vector (except RESET and TRAP)
has corresponding bits in these registers where
its own software priority is stored. This correspondance is shown in the following table.
Vector addressISPRx bits
FFFBh-FFFAhI1_0 and I0_0 bits*
FFF9h-FFF8hI1_1 and I0_1 bits
......
FFE1h-FFE0hI1_13 and I0_13 bits
– Each I1_x and I0_x bit value in the ISPRx regis-
ters has the same meaning as the I1 and I0 bits
in the CC register.
– Level 0 can not be written (I1_x=1, I0_x=0). In
this case, the previously stored value is kep t. (example: previous=CFh, write=64h, result=44h)
The TLI, RESET, and TRAP vectors have no software priorities. When one is serviced, the I1 and I0
bits of the CC register are both set.
*Note: Bits in the ISPRx registers which correspond to the TLI can be read and written but they
are not significant in the interrupt process management.
Caution: If the I1_x and I0_x bits are modified
while the interrupt x is executed the following behaviour has to be considered: If the interrupt x is
still pending (new interrupt or flag not cleared) and
the new software priority is higher than the previous one, the interrupt x is re-entered. Otherwise,
the software priority stays unchanged up to the
next interrupt request (after th e IRET of the interrupt x).
HALTEntering Halt mode10
IRETInterrupt routine returnPop CC, A, X, PCI1HI0NZC
JRMJump if I1:0=11 (level 3)I1:0=11 ?
JRNMJump if I1:0<>11I1:0<>11 ?
POP CCPop CC from the StackMem => CCI1HI0NZC
RIMEnable interrupt (level 0 set)Load 10 in I1:0 of CC10
SIMDisable interrupt (level 3 set)Load 11 in I1:0 of CC11
TRAPSoftware trapSoftware NMI11
WFIWait for interrupt10
Note: During the execution of an interrupt routine, the HALT, POPCC, RIM, SIM and WFI instructions change the current
software priority up to the next IRET instruction or one of the previously mentioned instructions.
37/215
ST72F521, ST72521B
INTERRUPTS (Cont’d)
Table 7. Interrupt Mapping
Exit
N°
0TLIExternal top level interruptEICRyesFFFAh-FFFBh
1MCC/RTCMain clock controller time base interruptMCCSR
2ei0External interrupt port A3..0
3ei1External interrupt port F2..0yesFFF4h-FFF5h
4ei2External interrupt port B3..0yesFFF2h-FFF3h
5ei3External interrupt port B7..4yesFFF0h-FFF1h
6CANCAN peripheral interruptsCANISRyesFFEEh-FFEFh
7SPISPI peripheral interruptsSPICSRyes
8TIMER ATIMER A peripheral interruptsTASRnoFFEAh-FFEBh
9TIMER BTIMER B peripheral interruptsTBSRnoFFE8h-FFE9h
10SCISCI Peripheral interruptsSCISR
11AVDAuxiliary Voltage detector interruptSICSRnoFFE4h-FFE5h
12I2CI2C Peripheral interrupts(see periph)noFFE2h-FFE3h
13PWM ARTPWM ART interruptARTCSRyes
Source
Block
RESETReset
TRAPSoftware interruptnoFFFCh-FFFDh
Description
Register
Label
N/A
N/A
Priority
Order
Higher
Priority
Lower
Priority
from
HALT/
ACTIVE
HALT
yesFFFE h-FFFFh
yesFFF8h-FFF9h
yesFFF6h-FFF7h
1
noFFE6h-FFE7h
2
Address
Vector
3)
FFECh-FFEDh
FFE0h-FFE1h
Notes:
1. Exit from HALT possible when SPI is in slave mode.
2. Exit from HALT possible when PWM ART is in external clock mode.
3. In Flash devices only a RESET or MCC/RTC interrupt can be used to wake-up from Active Halt mode.
7.6 EXTERNAL INTERRUPTS
7.6.1 I/O Port Interrupt Sensitivity
The external interrupt sensitivity is controlled by
the IPA, IPB and ISxx bits of the EICR register
(Figure 22). This control allows to have up to 4 fully
independent external interrupt source sensitivities.
Each external interrupt source can be generated
on four (or five) different events on the pin:
■ Falling edge
■ Rising edge
■ Falling and rising edge
■ Falling edge and low level
■ Rising edge and high level (only for ei0 and ei 2)
To guarantee correct functionality, the sensitivity
bits in the EICR register can be modified only
when the I1 and I0 bits of the CC register are both
set to 1 (level 3). This means that inte rrupts must
be disabled before changing sensitivity.
The pending interrupts are cleared by writ ing a different value in the ISx[1:0], IPA or IPB bits of the
EICR.
38/215
INTERRUPTS (Cont’d)
Figure 22. External Interrupt Control bits
ST72F521, ST72521B
PORT A [3:0] INTERRUPTS
PAOR.3
PADDR.3
PA3
IPA BIT
PORT F [2:0] INTERRUPTS
PFOR.2
PFDDR.2
PF2
PORT B [3:0] INTERRUPTS
PBOR.3
PBDDR.3
PB3
IPB BIT
EICR
IS20IS21
SENSITIVITY
CONTROL
EICR
IS20IS21
SENSITIVITY
CONTROL
EICR
IS10IS11
SENSITIVITY
CONTROL
PA3
PA2
PA1
PA0
PF2
PF1
PF0
PB3
PB2
PB1
PB0
ei0 INTERRUPT SOURCE
ei1 INTERRUPT SOURCE
ei2 INTERRUPT SOURCE
PORT B [7:4] INTERRUPTS
PBOR.7
PBDDR.7
PB7
EICR
IS10IS11
SENSITIVITY
CONTROL
PB7
PB6
PB5
PB4
ei3 INTERRUPT SOURCE
39/215
ST72F521, ST72521B
7.7 EXTERNAL INTERRUPT CONTROL REGISTER (EICR)
Read /Write
Reset Value: 0000 0000 (00h)
70
IS11 IS10IPBIS21 IS20IPATLIS TLIE
Bit 7:6 = IS1[1:0] ei2 and ei3 sensitivity
The interrupt sensitivity, defined using the IS1[1: 0]
bits, is applied to the following external interrupts:
- ei0 (port A3..0)
IS21 IS20
00
01Rising edge onlyFalling edge only
10Falling edge onlyRising edge only
11Rising and falling edge
External Interrupt Sensitivity
IPA bit =0IPA bit =1
Falling edge &
low level
- ei2 (port B3..0)
IS11 IS10
00
01Rising edge onlyFalling edge only
10Falling edge onlyRising edge only
11Rising and falling edge
External Interrupt Sensitivity
IPB bit =0IPB bit =1
Falling edge &
low level
Rising edge
& high level
- ei3 (port B7..4)
IS11 IS10External Interrupt Sensitivity
00Falling edge & low level
01Rising edge only
10Falling edge only
11Rising and falling edge
- ei1 (port F2..0)
IS21 IS20External Interrupt Sensitivity
00Falling edge & low level
01Rising edge only
10Falling edge only
11Rising and falling edge
These 2 bits can be written only when I1 and I0 of
the CC register are both set to 1 (level 3).
Bit 2 = IPA Interrupt polarity for port A
This bit is used to invert the sensitivity of the port A
[3:0] external interrupts. It can be set and cleared
by software only when I1 and I0 of the CC r egister
are both set to 1 (level 3).
0: No sensitivity inversion
These 2 bits can be written only when I1 and I0 of
1: Sensitivity inversion
the CC register are both set to 1 (level 3).
Bit 5 = IPB Interrupt polarity for port B
This bit is used to invert the sensitivity of the port B
[3:0] external interrupts. It can be set and cleared
by software only when I1 and I0 of th e CC r egi ster
are both set to 1 (level 3).
0: No sensitivity inversion
Bit 1 = TLIS TLI sensitivity
This bit allows to toggle the TLI edge sensitivity. It
can be set and cleared by software only when
TLIE bit is cleared.
0: Falling edge
1: Rising edge
1: Sensitivity inversion
Bit 0 = TLIE TLI enable
Bit 4:3 = IS2[1:0] ei0 and ei1 sensitivity
The interrupt sensitivity, defined using the IS2[1: 0]
bits, is applied to the following external interrupts:
This bit allows to enable or disable the TLI capability on the dedicated pin. It is set and cleared by
software.
0: TLI disabled
1: TLI enabled
Note: a parasitic interrupt can be generated when
clearing the TLIE bit.
To give a large measure of flexibility to the application in terms of power consumption, four main
power saving modes are implemen ted in the ST7
(see Figure 23): SLOW, WAIT (SLOW WAIT), ACTIVE HALT and HALT.
After a RESET the normal operating mode is selected by default (RUN mode). This mode drives
the device (CPU and embedded peripherals) by
means of a master clock which is based on the
main oscillator frequency divided or multiplied by 2
).
(f
OSC2
From RUN mode, the different power saving
modes may be selected by setting the relevant
register bits or by calling the specific ST7 software
instruction whose action depends on the oscillator
status.
Figure 23. Power Saving Mode Transitions
High
RUN
SLOW
WAIT
8.2 SLOW MODE
This mode has two targets:
– To reduce power consumption by decreasing the
internal clock in the device,
– To adapt the internal clock frequency (f
CPU
) to
the available supply voltage.
SLOW mode is controlled by three bits in the
MCCSR register: the SMS bit which enables or
disables Slow mode and two CPx bits which select
the internal slow frequency (f
In this mode, the master clock frequency (f
CPU
).
OSC2
can be divided by 2, 4, 8 or 16. The CPU and peripherals are clocked at this lower frequency
).
(f
CPU
Note: SLOW-WAIT mode is activated when ente ring the WAIT mode while the device is already in
SLOW mode.
Figure 24. SLOW Mode Clock Transitions
f
MCCSR
f
CPU
f
OSC2
CP1:0
SMS
/2f
OSC2
0001
OSC2
/4f
OSC2
)
42/215
SLOW WAIT
ACTIVE HALT
HALT
Low
POWER CONSUMPTION
NEW SLOW
FREQUENCY
REQUEST
NORMAL RUN MODE
REQUEST
POWER SAVING MODES (Cont’d)
ST72F521, ST72521B
8.3 WAIT MODE
WAIT mode places the MCU in a low power consumption mode by stopping the CPU.
This power saving mode is selected by calling the
‘WFI’ instruction.
All peripherals remain active. During WAIT mode,
the I[1:0] bits of the CC register are forced to ‘10’,
to enable all interrupts. All other registers and
memory remain unchanged. The MCU remains in
WAIT mode until an interrupt or RESET occurs,
whereupon the Program Counter branches to the
starting address of the interrupt or Reset service
routine.
The MCU will remain in WAIT mode until a Reset
or an Interrupt occurs, causing it to wake up.
Refer to Figure 25.
Figure 25. WAIT Mode Flow-chart
OSCILLATOR
WFI INSTRUCTION
N
INTERRUPT
Y
PERIPHERALS
CPU
I[1:0] BITS
N
RESET
Y
OSCILLATOR
PERIPHERALS
CPU
I[1:0] BITS
256 OR 4096 CPU CLOCK
CYCLE DELAY
OSCILLATOR
PERIPHERALS
CPU
I[1:0] BITS
ON
ON
OFF
10
ON
OFF
ON
10
ON
ON
ON
XX
1)
FETCH RESET VECTOR
OR SERVICE INTERRUPT
Note:
1. Before servicing an interrupt, the CC register is
pushed on the stack. The I[1:0] bits of the CC register are set to the current software priority level of
the interrupt routine and recovered when the CC
register is popped.
43/215
ST72F521, ST72521B
POWER SAVING MODES (Cont’d)
8.4 ACTIVE-HALT AND HALT MODES
ACTIVE-HALT and HALT modes are the two lowest power consumption modes of the MCU. They
are both entered by executing the ‘HALT’ instruction. The decision to enter either in ACTIVE-HALT
or HALT mode is given by the MCC/RTC interrupt
enable flag (OIE bit in MCCSR register).
MCCSR
OIE bit
Power Saving Mode entered when HALT
instruction is executed
0HALT mode
1ACTIVE-HALT mode
8.4.1 ACTIVE-HALT MODE
ACTIVE-HALT mode is the lowest power consumption mode of the MCU with a real time clock
available. It is entered by executing the ‘HALT’ instruction when the OIE bit of the Main Clock Controller Status register (MCCSR) is set (see section
10.2 on page 58 for more details on the MCCSR
register).
The MCU can exit ACTIVE-HALT mode on recep-
tion of an MCC/RTC interrupt or a RESET. In ROM
devices, external interrupts can be used to wakeup the MCU. When exiting ACTIVE-HALT mode
by means of an interrupt, no 256 or 4096 CPU cycle delay occurs. The CPU resumes operation by
servicing the interrupt or by fetching the re set ve ctor which woke it up (see Figure 27).
When entering ACTIVE-HALT mode, the I[1:0] bits
in the CC register are forced to ‘10b’ to enable interrupts. Therefore, if an interrupt is pending, the
MCU wakes up immediately.
In ACTIVE-HALT mode, only the main oscillator
and its associated counter (MCC/RTC) are running to keep a wake-up time base. All oth er peripherals are not clocked except those which get their
clock supply from another clock generator (such
as external or auxiliary oscillator).
The safeguard against staying locked in ACTIVEHALT mode is provided by the oscillator interrupt.
Note: As soon as the interrupt capability of one of
the oscillators is selected (MCCSR.OIE bit set),
entering ACTIVE-HALT mode while the Watchdog
is active does not generate a RESET.
This means that the device cannot spend more
than a defined delay in this power saving mode.
CAUTION: When exiting ACTIVE-HALT mode following an MCC/RTC interrupt, OIE bit of MCCSR
register must not be cleared before t
the interrupt occurs (t
= 256 or 4096 t
DELAY
DELAY
CPU
after
de-
lay depending on option byte). Otherwise, the ST7
enters HALT mode for the remaining t
DELAY
peri-
od.
Figure 26. ACTIVE-HALT Timing Overview
ACTIVE
HALTRUNRUN
HALT
INSTRUCTION
[MCCSR.OIE=1]
256 OR 4096 CPU
CYCLE DELAY
RESET
OR
INTERRUPT
1)
FETCH
VECTOR
Figure 27. ACTIVE-HALT Mode Flow-chart
HALT INSTRUCTION
(MCCSR.OIE=1)
N
INTERRUPT
Y
OSCILLATOR
PERIPHERALS
CPU
I[1:0] BITS
N
4)
OSCILLATOR
PERIPHERALS
CPU
I[1:0] BITS
256OR4096CPUCLOCK
OSCILLATOR
PERIPHERALS
CPU
I[1:0] BITS
FETCH RESET VECTOR
OR SERVICE INTERRUPT
RESET
Y
CYCLE DELAY
ON
2)
OFF
OFF
10
ON
OFF
ON
3)
XX
ON
ON
ON
3)
XX
Notes:
1. This delay occurs only if the MCU exits ACTIVEHALT mode by means of a RESET.
2. Peripheral clocked with an external clock source
can still be active.
3. Before servicing an interrupt, the CC register is
pushed on the stack. The I[1:0] bits of the CC register are set to the current software priority level of
the interrupt routine and restored when the CC
register is popped.
4. In flash devices only the MCC/RTC interrupt can
exit the MCU from ACTIVE-HALT mode.
44/215
POWER SAVING MODES (Cont’d)
8.4.2 HALT MODE
The HALT mode is the lowest power consumption
mode of the MCU. It is entered by ex ecuting the
‘HALT’ instruction when the OIE bit of the Main
Clock Controller Status register (MCCSR) is
cleared (see section 10.2 on page 58 for more details on the MCCSR register).
The MCU can exit HALT mode on reception of either a specific interrupt (see Table 7, “Interrupt
Mapping,” on page 38) or a RESET. When exiting
HALT mode by means of a RESET or an interrupt,
the oscillator is immediately turned on and the 256
or 4096 CPU cycle delay is used to stabilize the
oscillator. After the start up delay, the CPU
resumes operation by servicing the interrupt or by
fetching the reset vector which woke it up (see Fig-
ure 29).
When entering HALT mode, the I[1:0] bits in the
CC register are forced to ‘10b’to ena ble int errupts.
Therefore, if an interrupt is pending, the MCU
wakes up immediately.
In HALT mode, the main oscillator is turned off
causing all internal processing to be stopped, including the operation of the on-chip peripherals.
All peripherals are not clocked except the ones
which get their clock supply from another clock
generator (such as an external or auxiliary oscillator).
The compatibility of Watchdog operation with
HALT mode is configured by the “WDGHALT” option bit of the option byte. The HALT instruction
when executed while the Watchdog system is enabled, can generate a Watchdog RESET (see sec-
tion 14.1 on page 201 for more details).
Figure 28. HALT Timing Overview
HALTRUNRUN
HALT
INSTRUCTION
[MCCSR.OIE=0]
256 OR 4096 CPU
CYCLE DELAY
RESET
OR
INTERRUPT
FETCH
VECTOR
ST72F521, ST72521B
Figure 29. HALT Mode Flow-chart
HALT INSTRUCTION
(MCCSR.OIE=0)
ENABLE
WDGHALT
1
WATCHDOG
RESET
N
INTERRUPT
Y
1)
0
OSCILLATOR
PERIPHERALS
CPU
I[1:0] BITS
N
3)
OSCILLATOR
PERIPHERALS
CPU
I[1:0] BITS
256 OR 4096 CPU CLOCK
OSCILLATOR
PERIPHERALS
CPU
I[1:0] BITS
FETCH RESET VECTOR
OR SERVICE INTERRUPT
Notes:
1. WDGHALT is an option bit. See option byte section for more details.
2. Peripheral clocked with an external clock source
can still be active.
3. Only some specific interrupts can exit the MCU
from HALT mode (such as external interrupt). Refer to Table 7, “Inter rupt M apping,” o n pag e 38 for
more details.
4. Before servicing an interrupt, the CC register is
pushed on the stack. The I[1:0] bits of the CC register are set to the current software priority level of
the interrupt routine and recovered when the CC
register is popped.
WATCHDOG
RESET
Y
CYCLE
DISABLE
2)
DELAY
OFF
OFF
OFF
10
ON
OFF
ON
XX
ON
ON
ON
XX
4)
4)
45/215
ST72F521, ST72521B
POWER SAVING MODES (Cont’d)
8.4.2.1 Halt Mode Recommendations
– Make sure that an external event is available to
wake up the microcontroller from Halt mode.
– When using an external interrupt to wake up the
microcontroller, reinitialize the corresponding I/O
as “Input Pull-up with Interrupt” before executing
the HALT instruction. The main reason for this is
that the I/O may be wrongly configured d ue to external interference or by an unforeseen logical
condition.
– For the same reason, reinitialize the level sensi-
tiveness of each external interrupt as a precautionary measure.
– The opcode for the HALT instruction is 0x8E. To
avoid an unexpected HALT instruction due to a
program counter failure, it is advised to clear all
occurrences of the data value 0x8E from memo-
ry. For example, avoid defining a constant in
ROM with the value 0x8E.
– As the HALT instruction clears the interrupt mask
in the CC register to allow interrupts, the user
may choose to clear all pending interrupt bits before executing the HALT instruction. This avoids
entering other peripheral interrupt routines after
executing the external interrupt routine corresponding to the wake-up event (reset or external
interrupt).
Related Documentation
AN 980: ST7 Keypad Decoding Techniques, Implementing Wake-Up on Keystroke
AN1014: How to Minimize the ST7 Power Consumption
AN1605: Using an active RC to wakeup the
ST7LITE0 from power saving mode
46/215
9 I/O PORTS
ST72F521, ST72521B
9.1 INTRODUCTION
The I/O ports offer different functional mode s:
– transfer of data through digital inputs and outputs
and for specific pins:
– external interrupt generation
– alternate signal input/output for the on-chip pe-
ripherals.
An I/O port contains up to 8 pins. Each pin can be
programmed independently as digital in put (with or
without interrupt generation) or digital output.
9.2 FUNCTIONAL DESCRIPTION
Each port has 2 main registers:
– Data Register (DR)
– Data Direction Register (DDR)
and one optional register:
– Option Register (OR)
Each I/O pin may be programmed using the corre-
sponding register bits in the DDR and OR registers: bit X corresponding to pin X of the port. The
same correspondence is used for the DR register.
The following description takes into account the
OR register, (for specific ports which do not provide this register refer to the I/O Port Impleme ntation section). The generic I/O block diagram is
shown in Figure 30
9.2.1 Input Modes
The input configuration is selected by clearing the
corresponding DDR register bit.
In this case, reading the DR register returns the
digital value applied to the external I/O pin.
Different input modes can be selected by soft ware
through the OR register.
Notes:
1. Writing the DR register modifies the latch value
but does not affect the pin status.
2. When switching from input to output mode, the
DR register has to be written first to drive the correct level on the pin as soon as the port is configured as an output.
3. Do not use read/modify/write instructions (BSET
or BRES) to modify the DR register
External interrupt function
When an I/O is configured as Input with Interrupt,
an event on this I/O can generate an external inte rrupt request to the CPU.
Each pin can independently generate an interrupt
request. The interrupt sensitivity is independently
programmable using the sensitivity bits in the
EICR register.
Each external interrupt vector is linked to a dedicated group of I/O port p ins (see pinout descr iption
and interrupt section). If several input pins are selected simultaneously as interrupt sources, these
are first detected according to the sensitivity b its in
the EICR register and then logically ORed.
The external interrupts are hardware interrupts,
which means that the request la tch (not accessible
directly by the application) is automatically cleared
when the corresponding interrupt vector is
fetched. To clear an unwanted pending interrupt
by software, the sensitivity bits in the EICR register
must be modified.
9.2.2 Output Modes
The output configuration is selected by setting the
corresponding DDR register bit. In this case, writing the DR register applies this digital value to the
I/O pin through the latch. Then read ing the DR register returns the previously stored value.
Two different output modes can be selected by
software through the OR register: Output push-pull
and open-drain.
DR register value and output pin status:
DRPush-pullOpen-drain
0V
1V
SS
DD
Vss
Floating
9.2.3 Alternate Functions
When an on-chip peripheral is configured to use a
pin, the alternate function is automatically selected. This alternate function takes pr iority over the
standard I/O programming.
When the signal is coming from an on-chip peripheral, the I/O pin is automatically configured in output mode (push-pull or open drain according to the
peripheral).
When the signal is going to an on-chip peripheral,
the I/O pin must be configured in input mode. In
this case, the pin state is also digitally readable by
addressing the DR register.
Note: Input pull-up configuration can cause unexpected value at the input of the alternate p eripheral
input. When an on-chip peripheral use a pin as input and output, this pin has to be configured in input floating mode.
47/215
ST72F521, ST72521B
I/O PORTS (Cont’d)
Figure 30. I/O Port General Block Diagram
REGISTER
ACCESS
DATA BUS
DDR SEL
DR
DDR
OR
OR SEL
DR SEL
ALTERNATE
OUTPUT
ALTERNATE
ENABLE
If implemented
1
1
0
PULL-UP
CONDITION
N-BUFFER
V
DD
CMOS
SCHMITT
TRIGGER
P-BUFFER
(see table below)
PULL-UP
(see table below)
V
DD
PAD
DIODES
(see table below)
ANALOG
INPUT
0
EXTERNAL
INTERRUPT
SOURCE (eix)
Table 9. I/O Port Mode Options
Configuration ModePull-UpP-Buffer
Input
Output
Floating with/without InterruptOff
Pull-up with/without InterruptOn
Push-pull
Open Drain (logic level)Off
True Open DrainNININI (see note)
Legend: NI - not implemented
Off - implemented not activated
On - implemented and activated
ALTERNATE
INPUT
Diodes
to V
DD
Off
Off
On
Note: The diode to V
true open drain pads. A local protection between
the pad and V
vice against positive stress.
is implemented to protect the de-
SS
On
is not implemented in the
DD
to V
SS
On
48/215
I/O PORTS (Cont’d)
Table 10. I/O Port Configurations
ST72F521, ST72521B
Hardware Configuration
NOT IMPLEMENTED IN
TRUE OPEN DRAIN
I/O PORTS
1)
INPUT
NOT IMPLEMENTED IN
TRUE OPEN DRAIN
2)
I/O PORTS
OPEN-DRAIN OUTPUT
PAD
PAD
V
DD
R
PU
V
DD
R
PU
PULL-UP
CONDITION
INTERRUPT
CONDITION
DR REGISTER ACCESS
DR
REGISTER
EXTERNAL INTERRUPT
SOURCE (eix)
ENABLEOUTPUT
W
R
DR REGISTER ACCESS
DR
REGISTER
ALTERNATEALTERNATE
ALTERNATE INPUT
ANALOG INPUT
R/W
DATA BUS
DATA BUS
NOT IMPLEMENTED IN
TRUE OPEN DRAIN
2)
I/O PORTS
PUSH-PULL OUTPUT
PAD
V
DD
R
PU
ENABLEOUTPUT
DR REGISTER ACCESS
DR
REGISTER
ALTERNATEALTERNATE
R/W
DATA BUS
Notes:
1. When the I/O port is in input configuration an d the associated alternate function is enabled as an output,
reading the DR register will read the alternate function output status.
2. When the I/O port is in output configurat ion and the associated alterna te function is enabled as an input ,
the alternate function reads the pin status given by the DR register content.
49/215
ST72F521, ST72521B
I/O PORTS (Cont’d)
CAUTION: The alternate function must not be ac-
tivated as long as the pin is configured as input
with interrupt, in order to avoid genera ting spurious
interrupts.
Analog alternate function
When the pin is used as an ADC input, the I/O
must be configured as floating input. The analog
multiplexer (controlled by the ADC registers)
switches the analog voltage present on the se lected pin to the common analog rail which is connected to the ADC input.
It is recommended not to change the voltage level
or loading on any port pin while conversion is in
progress. Furthermore it is recommended not to
have clocking pins located close to a selected analog pin.
WARNING: The analog input voltage level must
be within the limits stated in the absolute maximum ratings.
9.3 I/O PORT IMPLEMENTATION
The hardware implementation o n each I/O port depends on the settings in the DDR and OR registers
and specific feature of the I/O port such as ADC Input or true open drain.
Switching these I/O ports from one state to another should be done in a sequence that prevents unwanted side effects. Recommended safe transitions are illustrated in Figure 31 Other transitions
are potentially risky and should be avoided, since
they are likely to present unwanted side-effects
such as spurious interrupt generation.
Figure 31. Interrupt I/O Port State Transition s
01
INPUT
floating/pull-up
interrupt
00
INPUT
floating
(reset state)
10
OUTPUT
open-drain
XX
11
OUTPUT
push-pull
= DDR, OR
9.4 LOW POWER MODES
Mode Description
WAIT
HALT
No effect on I/O ports. External interrupts
cause the device to exit from WAIT mode.
No effect on I/O ports. External interrupts
cause the device to exit from HALT mode.
9.5 INTERRUPTS
The external interrupt event generates an interrupt
if the corresponding configuration is selected with
DDR and OR registers and the interrupt mask in
the CC register is not active (RIM instruction).
Interrupt Event
External interrupt on
selected external
event
Event
Flag
-
Enable
Control
Bit
DDRx
ORx
Exit
from
Wait
YesYes
Exit
from
Halt
50/215
I/O PORTS (Cont’d)
9.5.1 I/O Port Implementation
The I/O port register configurations are summarised as follows.
Standard Ports
PA5:4, PC7:0, PD7:0, PE7:34,
PE1:0, PF7:3, PG7:0, PH7:0
MODEDDROR
floating input00
pull-up input01
open drain output10
push-pull output11
I/O PORTS (Cont’d)
Table 12. I/O Port Register Map and Reset Values
Address
(Hex.)
Reset Value
of all I/O port registers
0000hPADR
0002hPAOR
0003hPBDR
0005hPBOR
0006hPCDR
0008hPCOR
0009hPDDR
000BhPDOR
000ChPEDR
000EhPEOR
000FhPFDR
0011hPFOR
0012hPGDR
0014hPGOR
0015hPHDR
0017hPHOR
Register
Label
76543210
00000000
MSBLSB0001hPADDR
MSBLSB0004hPBDDR
MSBLSB0007hPCDDR
MSBLSB000AhPDDDR
MSBLSB000DhPEDDR
MSBLSB0010hPFDDR
MSBLSB0013hPGDDR
MSBLSB0016hPHDDR
Related Documentation
AN 970: SPI Communication between ST7 and
EEPROM
52/215
AN1045: S/W implementation of I2C bus master
AN1048: Software LCD driver
10 ON-CHIP PERIPHERALS
10.1 WATCHDOG TIMER (WDG)
ST72F521, ST72521B
10.1.1 Introduction
The Watchdog timer is used to detect the occurrence of a software fault, usually generated by external interference or by unforeseen logical conditions, which causes the application program to
abandon its normal sequence. The Watchdog circuit generates an MCU reset on expiry of a programmed time period, unless the program refreshes the counter’s contents before the T6 bit becomes cleared.
10.1.2 Main Features
■ Programmable free-running downcounter
■ Programmable reset
■ Reset (if watchdog activated) when the T6 bit
reaches zero
■ Optional reset on HALT instruction
(configurable by option byte)
■ Hardware Watchdog selectable by option byte
10.1.3 Functional Description
The counter value stored in the Watchdog Control
register (WDGCR bits T[6:0]), is decremented
every 16384 f
cycles (approx.), and the
OSC2
length of the timeout period can be programmed
by the user in 64 increments.
If the watchdog is activated (the WDGA bit is set)
and when the 7-bit timer (bits T[6:0]) rolls over
from 40h to 3Fh (T6 becomes cleared), it initiates
a reset cycle pulling low the reset pin for typically
500ns.
The application program must write in the
WDGCR register at regular intervals during normal
operation to prevent an MCU reset. This downcounter is free-running: it counts down even if the
watchdog is disabled. The value to be stored in the
WDGCR register must be between FFh and C0h:
– The WDGA bit is set (watchdog enabled)
– The T6 bit is set to prevent generating an imme-
diate reset
– The T[5:0] bits contain the number of increments
which represents the time delay before the
watchdog produces a reset (see Figure 33. Ap-
proximate Timeout Duration). The timing varies
between a minimum and a maximum value due
to the unknown status of the prescaler when writing to the WDGCR register (see Figure 34).
Following a reset, the watchdog is disabled. Once
activated it cannot be disabled, except by a reset.
The T6 bit can be used to generate a software reset (the WDGA bit is set and the T6 bit is cleared) .
If the watchdog is activated, the HALT instr uction
will generate a Reset.
Figure 32. Watchdog Block Diagram
f
OSC2
MCC/RTC
DIV 64
12-BIT MCC
RTC COUNTER
MSB
11
LSB
6
5
TB[1:0] bits
(MCCSR
0
Register)
WDGA
RESET
WATCHDOG CONTROL REGISTER (WDGCR)
T5
T6
T4
T3
6-BIT DOWNCOUNTER (CNT)
WDG PRESCALER
DIV 4
T2
T1
T0
53/215
ST72F521, ST72521B
WATCHDOG TIMER (Cont’d)
10.1.4 How to Program the Watchdog Timeout
Figure 33 shows the linear relationship between
the 6-bit value to be loaded in the Watchdog Counter (CNT) and the resulting timeout duration in milliseconds. This can be used for a quick calculation
without taking the timing variations into account. If
Figure 33. Approximate Timeout Duration
3F
38
30
28
more precision is needed, use the formulae in Fig-
ure 34.
Caution: When writing to the WDGCR register, always write 1 in the T6 bit to avoid generating an
immediate reset.
20
18
CNT Value (hex.)
10
08
00
1.565
5034188298114
Watchdog timeout (ms) @ 8 MHz. f
128
OSC2
54/215
WATCHDOG TIMER (Cont’d)
ST72F521, ST72521B
Figure 34. Exact Timeout Duration (t
min
and t
max
)
WHERE:
= (LSB + 128) x 64 x t
t
min0
t
= 16384 x t
max0
t
OSC2
= 125ns if f
OSC2
OSC2
OSC2
=8 MHz
CNT = Value of T[5:0] bits in the WDGCR register (6 bits)
MSB and LSB are values from the table below depending on the timebase selected by the TB[1:0] bits
in the MCCSR register
TB1 Bit
(MCCSR Reg.)
002ms459
014ms853
1010ms2035
1125ms4954
To calculate the minimum Watchdog Timeout (t
IFTHEN
CNT
<
MSB
------------4
To calculate the maximum Watchdog Timeout (t
TB0 Bit
(MCCSR Reg.)
t
ELSE
t
mintmin0
Selected MCCSR
Timebase
=
mintmin0
MSBLSB
):
min
16384CNTt
×192 LSB+()64
16384CNT
××+
osc2
max
–
):
4CNT
---------------- MSB
+t
⎛⎞
⎝⎠
××
4CNT
---------------- MSB
×+=
osc2
IFTHEN
CNT
MSB
-------------
≤t
4
ELSE
maxtmax0
t
maxtmax0
16384CNTt
16384CNT
×192 LSB+()64
××+=
osc2
–
4CNT
---------------- MSB
+t
⎛⎞
⎝⎠
××
4CNT
---------------- MSB
Note: In the above formulae, division results must be rounded down to the next integer value.
Example:
With 2ms timeout selected in MCCSR register
Value of T[5:0] Bits in
WDGCR Register (Hex.)
001.4962.048
3F128128.552
Min. Watchdog
Timeout (ms)
t
min
Max. Watchdog
Timeout (ms)
t
max
×+=
osc2
55/215
ST72F521, ST72521B
WATCHDOG TIMER (Cont’d)
10.1.5 Low Power Modes
Mode Description
SLOWNo effect on Watchdog.
WAITNo ef fect on Watchdog.
OIE bit in
MCCSR
register
00
HALT
01A reset is generated.
1x
WDGHALT bit
in Option
Byte
No Watchdog reset is generated. The MCU enters Halt mode. The Watchdog counter is decremented once and then stops counting and is no longer
able to generate a watchdog reset until the MCU receives an external interrupt or a reset.
If an external interrupt is received, the Watchdog restarts counting after 256
or 4096 CPU clocks. If a reset is generated, the Watchdog is disabled (reset
state) unless Hardware Watchdog is selected by option byte. For application recommendations see Section 10.1.7 below.
No reset is generated. The MCU enters Active Halt mode. The Watchdog
counter is not decremented. It stop counting. When the MCU receives an
oscillator interrupt or external interrupt, the Watchdog restarts counting immediately. When the MCU receives a reset the Watchdog restarts counting
after 256 or 4096 CPU clocks.
10.1.6 Hardware Watchdog Option
If Hardware Watchdog is selected by option byte,
the watchdog is always active and the WDGA bit in
the WDGCR is not used. Refer to the Option Byte
description.
10.1.7 Using Halt Mode with the WDG
(WDGHALT option)
The following recommendation applies if Halt
mode is used when the watchdog is enabled.
– Before executing the HALT instruction, refresh
the WDG counter, to avoid an unexpect ed WDG
reset immediately after waking up the microcontroller.
10.1.8 Interrupts
None.
10.1.9 Register Description
CONTROL REGISTER (WDGCR)
Read/Write
Reset Value: 0111 1111 (7Fh)
70
WDGAT6T5T4T3T2T1T0
Bit 7 = WDGA Activation bit.
This bit is set by software and only cleared by
hardware after a reset. When WDGA = 1, the
watchdog can generate a reset.
0: Watchdog disabled
1: Watchdog enabled
Note: This bit is not used if the hardware watchdog option is enabled by option byte.
Bit 6:0 = T[6:0] 7-bit counter (MSB to LSB).
These bits contain the value of the watchdog
counter. It is decremented every 16384 f
OSC2
cycles (approx.). A reset is produced when it rolls
over from 40h to 3Fh (T6 becomes cleared).
56/215
Table 13. Watchdog Timer Register Map and Reset Values
ST72F521, ST72521B
Address
(Hex.)
002Ah
Register
Label
WDGCR
Reset Value
76543210
WDGA
0
T6
T5
1
1
T4
T3
1
1
T2
T1
1
1
T0
1
57/215
ST72F521, ST72521B
10.2 MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK AND BEEPER (MCC/RTC)
The Main Clock Controller consists of three different functions:
■
a programmable CPU clock prescaler
■
a clock-out signal to supply external devices
■
a real time clock timer with interrupt capability
Each function can be used independently and simultaneously.
10.2.1
Programmable CPU Clock Prescaler
The programmable CPU clock prescaler supplies
the clock for the ST7 CPU and its internal peripherals. It manages SLOW power saving mode (See
Section 8.2 SLOW MODE for more details).
The prescaler selects the f
main clock frequen-
CPU
cy and is controlled by three bits in the MCCSR
register: CP[1:0] and SMS.
10.2.2
Clock-out Capability
The clock-out capability is an alternate function of
an I/O port pin that outputs a f
Figure 35.
Main Clock Controller (MCC/RTC) Block Diagram
clock to drive
CPU
BC1 BC0
external devices. It is controlled by the MCO bit in
the MCCSR register.
CAUTION: When selected, the clock out pin suspends the clock during ACTIVE-HALT mode.
10.2.3
Real Time Clock Timer (RTC)
The counter of the real time clock timer allows an
interrupt to be generated based on an accurate
real time clock. Four different time bases depending directly on f
are available. The whole
OSC2
functionality is controlled by four bits of the MCCSR register: TB[1:0], OIE and OIF.
When the RTC interrupt is enabled (OIE bit set),
the ST7 enters ACTIVE-HALT mode when the
HALT instruction is executed. See Sect ion 8.4 AC-
TIVE-HALT AND HALT MODES for more details.
10.2.4
Beeper
The beep function is controlled by the MCCBCR
register. It can output t hree selectab le f reque ncies
on the BEEP pin (I/O port alternate function).
f
OSC2
MCCBCR
DIV 64
MCO
MCCSR
DIV 2, 4, 8, 16
BEEP SIGNAL
SELECTION
12-BIT MCC RTC
COUNTER
SMSCP1 CP0TB1 TB0 OIE OIF
1
0
TO
WATCHDOG
TIMER
MCC/RTC INTERRUPT
f
CPU
BEEP
MCO
CPU CLOCK
TO CPU AND
PERIPHERALS
58/215
MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK (Cont’d)
10.2.5
Low Power Modes
Mode Description
No effect on MCC/RTC peripheral.
WAIT
ACTIVEHALT
HALT
MCC/RTC interrupt cause the device to exit
from WAIT mode.
No effect on MCC/RTC counter (OIE bit is
set), the registers are frozen.
MCC/RTC interrupt cause the device to exit
from ACTIVE-HALT mode.
MCC/RTC counter and registers are frozen.
MCC/RTC operation resumes when the
MCU is woken up by an interrupt with “exit
from HALT” capability.
Bit 6:5 = CP[1:0] CPU clock prescaler
These bits select the CPU clock prescaler which is
applied in the different slow modes. Their action is
conditioned by the setting of the SMS bit. These
two bits are set and cleared by software
f
in SLOW modeCP1CP0
CPU
f
OSC2
f
OSC2
f
OSC2
f
OSC2
ST72F521, ST72521B
/ 200
/ 401
/ 810
/ 1611
10.2.6
Interrupts
The MCC/RTC interrupt event generates an interrupt if the OIE bit of the MCCSR register is set and
the interrupt mask in the CC register is not active
(RIM instruction).
Interrupt Event
Time base overflow
event
Event
Enable
Control
Flag
OIFOIEYesNo
Bit
Exit
from
Wait
Exit
from
Halt
1)
Note:
The MCC/RTC interrupt wakes up the MCU from
ACTIVE-HALT mode, not from HALT mode.
10.2.7
Register Description
MCC CONTROL/STATUS REGISTER (MCCSR)
Read /Write
Reset Value: 0000 0000 (00h
)
Bit 4 = SMS Slow mode select
This bit is set and cleared by software.
0: Normal mode. f
1: Slow mode. f
= f
CPU
CPU
OSC2
is given by CP1, CP0
See Section 8.2 SLOW MODE and Section 10.2
MAIN CLOCK CONTROLLER WITH REAL TIME
CLOCK AND BEEPER (MCC/RTC) for more de-
tails.
Bit 3:2 = TB[1:0] Time base control
These bits select the programmable divider time
base. They are set and cleared by software.
Counter
Prescaler
160004ms2ms00
320008ms4ms01
8000020ms10ms10
20000050ms25ms11
f
OSC2
Time Base
=4MHz f
OSC2
A modification of the time base is taken into account at the end of the current period (previously
70
set) to avoid an unwanted time shift. This allows to
use this time base as a real time clock.
MCO CP1CP0 SMSTB1TB0OIEOIF
Bit 7 = MCO Main clock out selection
This bit enables the MCO alternate functio n on the
PF0 I/O port. It is set and cleared by software.
0: MCO alternate function disabled (I/O pin free f or
general-purpose I/O)
1: MCO alternate function enabled (f
CPU
on I/O
port)
Note: To reduce power consumption, the MCO
Bit 1 = OIE Oscillator interrupt enable
This bit set and cleared by software.
0: Oscillator interrupt disabled
1: Oscillator interrupt enabled
This interrupt can be used to exit from ACTIVEHALT mode.
When this bit is set, calling the ST7 software HALT
instruction enters the ACTIVE-HALT power saving
.
mode
function is not active in ACTIVE-HALT mode.
=8MHz
TB1TB0
59/215
ST72F521, ST72521B
MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK (Cont’d)
Bit 0 = OIF Oscillator interrupt flag
This bit is set by hardware and cleared by software
reading the MCCSR register. It indicates when set
that the main oscillator has reached the selected
elapsed time (TB1:0).
0: Timeout not reached
1: Timeout reached
CAUTION: The BRES and BSET instructions
must not be used on the MCCSR register to avoid
unintentionally clearing the OIF bit.
MCC BEEP CONTROL REGISTER (MCCBCR)
Read/Write
Reset Value: 0000 0000 (00h)
70
000000BC1BC0
Bit 7:2 = Reserved, must be kept cleared.
Bit 1:0 = BC[1:0] Beep control
These 2 bits select the PF1 pin beep capability.
BC1BC0Beep mode with f
00Off
01 ~2-KHz
10 ~1-KHz
11~500-Hz
The beep output signal is available in ACTIVEHALT mode but has to be disabled to reduce the
consumption.
Table 14. Main Clock Controller Register Map and Reset Values
Address
(Hex.)
002Bh
002Ch
002Dh
Register
Label
SICSR
Reset Value
MCCSR
Reset Value
MCCBCR
Reset Value000000
76543210
AVDS0AVDIE0AVDF0LVDRF
x000
MCO
0
CP1
0
CP0
0
SMS
0
TB1
0
TB0
0
=8MHz
OSC2
Output
Beep signal
~50% duty cycle
WDGRF
OIE
0
BC1
0
OIF
BC0
x
0
0
60/215
10.3 PWM AUTO-RELOAD TIMER (ART)
10.3.1 Introduction
The Pulse Width Modulated Auto-Reload Timer
on-chip peripheral consists of an 8-bit auto reload
counter with compare/capture capabilities and of a
7-bit prescaler clock source.
These resources allow five possible operating
modes:
– Generation of up to 4 independent PWM signals
– Output compare and Time base interrupt
Figure 36. PWM Auto-Reload Timer Block Diagram
ST72F521, ST72521B
– Up to two input capture functions
– External even t de te cto r
– Up to two external interrupt sources
The three first modes can be used together with a
single counter frequency.
The timer can be used to wake up the MCU from
WAIT and HALT modes.
PWMx
ARTICx
ARTCLK
PWMCR
ALTERNATE
FUNCTION
f
EXT
f
CPU
OEx
PORT
INPUT CAPTURE
MUX
ARR
REGISTER
CONTROL
ICIEx
OPx
POLARITY
CONTROL
ICFxICSx
f
COUNTER
LOAD
ICCSR
OCRx
REGISTER
COMPARE
8-BIT COUNTER
(CAR REGISTER)
ICRx
REGISTER
ICx INTERRUPT
DCRx
REGISTER
LOAD
LOAD
f
INPUT
EXCL CC2CC1CC0TCE FCRLOIEOVF
PROGRAMMABLE
PRESCALER
ARTCSR
OVF INTERRUPT
61/215
ST72F521, ST72521B
PWM AUTO-RELOAD TIMER (Cont’d)
10.3.2 Functional Description
Counter
The free running 8-bit co unter is fed by the outpu t
of the prescaler, and is incremented on every rising edge of the clock signal.
It is possible to read or write the contents of the
counter on the fly by reading or writing the Counter
Access register (ARTCAR).
When a counter overflow occurs, the counter is
automatically reloaded with the contents of the
ARTARR register (the prescaler is not affected).
Counter clock and prescaler
The counter clock frequency is given by:
f
COUNTER
= f
INPUT
The timer counter’s input clock (f
/ 2
CC[2:0]
INPUT
) feeds the
7-bit programmable prescaler, which selects one
of the 8 available taps of the prescaler, as defin e d
by CC[2:0] bits in the Control/Status Register
(ARTCSR). Thus the division factor of the prescaler can be set to 2
This f
INPUT
n
(where n = 0, 1,..7).
frequency source is selected through
the EXCL bit of the ARTCSR register and can be
either the f
or an external input frequency f
CPU
EXT
The clock input to the counter is enabled by the
TCE (Timer Counter Enable) bit in the ARTCSR
register. When TCE is reset, the counter is
stopped and the prescaler and counter contents
are frozen. When TCE is set, the counter runs at
the rate of the selected clock source.
Counter and Prescaler Initialization
After RESET, the counter and the prescaler are
cleared and f
INPUT
= f
CPU
.
The counter can be initialized by:
– Writing to the ARTARR register and then setting
the FCRL (Force Counter Re-Load) and the TCE
(Timer Counter Enable) bits in the ARTCSR reg-
ister.
– Writing to the ARTCAR counter access register,
In both cases the 7-bit prescaler is also cleared,
whereupon counting will start from a known value.
Direct access to the prescaler is not possible.
Output compare control
The timer compare function is based on four different comparisons with the counter (one for each
PWMx output). Each comparison is made between the counter value and an output compare
register (OCRx) value. This OCRx register can not
be accessed directly, it is loaded from the duty cycle register (PWMDCRx) at each overflow of the
counter.
.
This double buffering method avoids glitch generation when changing the duty cycle on the fly.
Figure 37. Output compare control
f
COUNTER
ARTARR=FDh
COUNTER
OCRx
PWMDCRx
PWMx
62/215
FDhFEhFFhFDhFEhFFhFDhFEh
FDh
FDh
FFh
FEh
FEh
PWM AUTO-RELOAD TIMER (Cont’d)
ST72F521, ST72521B
Independent PWM signal generation
This mode allows up to four Pulse Width Modulated signals to be generated on the PWMx output
pins with minimum core processing overhead.
This function is stopped during HALT mode.
Each PWMx output signal can be selected independently using the corresponding OEx bit in the
PWM Control register (PWMCR). When this bit is
set, the corresponding I/O pin is configured as output push-pull alternate function.
The PWM signals all have the same frequency
which is controlled by the counter period and the
ARTARR register value.
f
PWM
= f
COUNTER
/ (256 - ARTARR)
When a counter overflow occurs, the PWMx pin
level is changed depending on the corresponding
OPx (output polarity) bit in the PWMCR register.
Figure 38. PWM Auto-reload Timer Function
255
DUTY CYCLE
REGISTER
(PWMDCRx)
When the counter reaches the value contained in
one of the output compare register (OCRx) the
corresponding PWMx pin level is restored.
It should be noted that the reload values will also
affect the value and the resolution of the duty cycle
of the PWM output signal. To obtain a signal on a
PWMx pin, the contents of the OCRx register must
be greater than the contents of the ARTARR register.
The maximum available resolution for the PWMx
duty cycle is:
Resolution = 1 / (256 - ARTARR)
Note: To get the maximum resolution (1/256), the
ARTARR register must be 0. With this maximum
resolution, 0% and 100% can be obtained by
changing the polarity.
AUTO-RELOAD
COUNTER
REGISTER
(ARTARR)
000
WITH OEx=1
AND OPx=0
WITH OEx=1
AND OPx=1
PWMx OUTPUT
Figure 39. PWM Signal from 0% to 100% Duty Cycle
f
COUNTER
ARTARR=FDh
PWMx OUTPUT
WITH OEx=1
COUNTER
OCRx=FCh
OCRx=FDh
OCRx=FEh
AND OPx=0
OCRx=FFh
FDhFEhFFhFDhFEhFFhFDhFEh
t
t
63/215
ST72F521, ST72521B
PWM AUTO-RELOAD TIMER (Cont’d)
Output compare and Time base interrupt
On overflow, the OVF flag of the ARTCSR register
is set and an overflow interrupt request is gene rated if the overflow interrupt enable bit, OIE, in the
ARTCSR register, is set. The OVF flag must be reset by the user software. This interrupt can be
External clock and event detector mode
Using the f
auto-reload timer can be used as an external clock
event detector. In this mode, the ARTARR register
is used to select the n
be counted before setting the OVF flag.
used as a time base in the application.
Caution: The external clock function is no t available in HALT mode. If HALT mode is used in the application, prior to executing the HALT instruction,
the counter must be disabled by cleari ng the TCE
bit in the ARTCSR register to avoid spurious counter increments.
Figure 40. External Event Detector Example (3 counts)
f
EXT=fCOUNTER
ARTARR=FDh
COUNTER
OVF
FDhFEhFFhFDh
external prescaler input clock, the
EXT
EVENT
n
FEhFFhFDh
= 256 - ARTARR
EVENT
number of events to
INTERRUPT
IF OIE=1
ARTCSR READ
ARTCSR READ
INTERRUPT
IF OIE=1
t
64/215
PWM AUTO-RELOAD TIMER (Cont’d)
Input capture function
This mode allows the measurement of external
signal pulse widths through ARTICRx registers.
Each input capture can generate an inte rrupt independently on a selected input signal transition.
This event is flagged by a set of the corresponding
CFx bits of the Input Capture Control/Status register (ARTICCSR).
These input capture interrupts are enabled
through the CIEx bits of the ARTICCSR register.
The active transition (falling or rising edge) is software programmable through the CSx bits of the
ARTICCSR register.
The read only input capture registers (ARTICRx)
are used to latch the auto-reload counter value
when a transition is detected on the ARTICx pin
(CFx bit set in ARTICCSR register). After fe tching
the interrupt vector, the CFx flags can be read to
identify the interrupt source.
Note: After a capture detection, data transfer in
the ARTICRx register is inhibited until it is read
(clearing the CFx bit).
The timer interrupt remains pending while the CFx
flag is set when the interrupt is enabled (CIEx bit
set). This means, the ARTICRx register has to be
read at each capture event to clear the CFx flag.
ST72F521, ST72521B
External interrupt capability
This mode allows the Input capture capabilities to
be used as external interrup t sources. The interrupts are generated on the edge of the ARTICx
signal.
The edge sensitivity of the external interrupts is
programmable (CSx bit of ARTICCSR register)
and they are independently enabled through CIEx
bits of the ARTICCSR register. A fter fetching the
interrupt vector, the CFx flags can be read to identify the interrupt source.
During HALT mode, the external interrupts can be
used to wake up the micro (if the CIEx bit is set).
The timing resolution is given by auto-reloa d counter cycle time (1/f
COUNTER
).
Note: During HALT mode, if both input capture
and external clock are enabled, the ARTICRx register value is not guaranteed if the input capture
pin and the external clock change simultaneously.
Figure 41. Input Capture Timing Diagram
f
COUNTER
COUNTER
ARTICx PIN
CFx FLAG
ICRx REGISTER
01h
02h03h05h06h07h
xxh
04h
INTERRUPT
04h
t
65/215
ST72F521, ST72521B
PWM AUTO-RELOAD TIMER (Cont’d)
10.3.3 Register Description
CONTROL / STATUS REGISTER (ARTCSR)
Read /Write
Reset Value: 0000 0000 (00h)
70
0: New transition not yet reached
1: Transition reached
COUNTER ACCESS REGISTER (ARTCAR)
Read/Write
Reset Value: 0000 0000 (00h)
EXCLCC2CC1CC0TCEFCRLOIEOVF
Bit 7 = EXCL
External Clock
70
CA7CA6CA5CA4CA3CA2CA1CA0
This bit is set and cleared by software. It selects the
input clock for the 7-bit prescaler.
0: CPU clock.
1: External clock.
Bit 6:4 = CC[2:0] Counter Clock Control
These bits are set and cleared by software. They
determine the prescaler division ratio from f
f
COUNTER
f
INPUT
f
INPUT
f
INPUT
f
INPUT
f
INPUT
f
INPUT
f
INPUT
f
INPUT
/ 2
/ 4
/ 8
/ 16
/ 32
/ 64
/ 128
With f
=8 MHz CC2 CC1 CC0
INPUT
8 MHz
4 MHz
2 MHz
1 MHz
500 KHz
250 KHz
125 KHz
62.5 KHz
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
INPUT
0
1
0
1
0
1
0
1
Bit 7:0 = CA[7:0] Counter Access Data
These bits can be set and cleared either by hard-
ware or by software. The ARTCAR register is used
to read or write the auto-reload counter “o n the fly”
(while it is counting).
.
AUTO-RELOAD REGISTER (ARTARR)
Read/Write
Reset Value: 0000 0000 (00h)
70
AR7AR6AR5AR4AR3AR2AR1AR0
Bit 3 = TCE Timer Counter Enable
This bit is set and cleared by software. It puts the
timer in the lowest power consumption mode.
0: Counter stopped (prescaler and counter frozen).
1: Counter running.
Bit 2 = FCRL
Force Counter Re-Load
This bit is write-only and any attempt to read it will
yield a logical zero. When set, it causes the contents
of ARTARR register to be loaded into the counter,
and the content of the prescaler register to be
cleared in order to initialize the timer before starting
to count.
Bit 1 = OIE
Overflow Interrupt Enable
This bit is set and cleared by software. It allows to
enable/disable the interrupt which is generated
when the OVF bit is set.
0: Overflow Interrupt disable.
1: Overflow Interrupt enable.
Bit 0 = OVF
Overflow Flag
This bit is set by hardware and cleared by software
reading the ARTCSR register. It indicates th e transition of the counter from FFh to the ARTARR val-
.
ue
Bit 7:0 =
AR[7:0]
Counter Auto-Reload Data
These bits are set and cleared by software. They
are used to hold the auto-reload value which is automatically loaded in the counter when an over flow
occurs. At the same time, the PWM output levels
are changed according to the corresponding OPx
bit in the PWMCR register.
This register has two PWM management functions:
– Adjusting the PWM frequency
– Setting the PWM duty cycle resolution
Bit 7:4 = OE[3:0] PWM Output Enable
These bits are set and cleared by software. They
enable or disable the PWM output channels independently acting on the corresponding I/O pin.
0: PWM output disabled.
1: PWM output enabled.
Bit 3:0 = OP[3:0] PWM Output Polarity
These bits are set and cleared by software. They
independently select the polarity of the four PWM
DUTY CYCLE REGISTERS (PWMDCRx)
Read/Write
Reset Value: 0000 0000 (00h)
70
DC7DC6DC5DC4DC3DC2DC1DC0
Bit 7:0 = DC[7:0] Duty Cycle Data
These bits are set and cleared by software.
A PWMDCRx register is associated with the OCRx
register of each PWM channel to determine the
second edge location of the PWM signal (the first
edge location is common to all channels and given
by the ARTARR register). These PWMDCR registers allow the duty cycle to be set independently
for each PWM channel.
output signals.
PWMx output level
Counter <= OCRxCounter > OCRx
100
011
OPx
Note: When an OPx bit is modified, the PWMx out-
put signal polarity is immediately revers ed .
67/215
ST72F521, ST72521B
PWM AUTO-RELOAD TIMER (Cont’d)
INPUT CAPTURE
CONTROL / STATUS REGISTER (ARTICCSR)
Read /Write
INPUT CAPTURE REGISTERS (ARTICRx)
Read only
Reset Value: 0000 0000 (00h)
Reset Value: 0000 0000 (00h)
70
70
IC7IC6IC5IC4IC3IC2IC1IC0
00CS2CS1CIE2CIE1CF2CF1
Bit 7:0 = IC[7:0] Input Capture Dat a
Bit 7:6 = Reserved, always read as 0.
These read only bits are set and cleared by hard-
ware. An ARTICRx register contains the 8-bit
Bit 5:4 = CS[2:1] Capture Sensitivity
These bits are set and cleared by software. They
auto-reload counter value transferred by the input
capture channel x event.
determine the trigger ev ent polarity on the corresponding input capture channel.
0: Falling edge triggers capture on channel x.
1: Rising edge triggers capture on channel x.
Bit 3:2 = CIE[2:1] Capture Interrupt Enable
These bits are set and cleared by software. They
enable or disable the Input capture channel interrupts independently.
0: Input capture channel x interrupt disabled.
1: Input capture channel x interrupt enabled .
Bit 1:0 = CF[2:1] Capture Flag
These bits are set by hardware and cleared by
software reading the corresponding ARTICRx register. Each CFx bit indicates that an input capture x
has occurred.
0: No input capture on channel x.
1: An input capture has occured on channel x.
The timer consists of a 16-bit free-running counter
driven by a programmable prescaler.
It may be used for a variety of purposes, including
pulse length measurement of up to two input signals (input capture) or generation of up to two output waveforms (output compare and PWM).
Pulse lengths and waveform periods can be modulated from a few microseconds to several milliseconds using the timer prescaler and the CPU
clock prescaler.
Some ST7 devices have two on-chip 16-bit timers.
They are completely independent, and do not
share any resources. They are synchronized after
a MCU reset as long as the timer c lock frequencies are not modified.
This description covers one or two 16-bit t imers. In
ST7 devices with two timers, register names are
prefixed with TA (Timer A) or TB (Timer B).
Note: If IC, OC and TO interrupt requests have separate vectors
then the last OR is not present (S ee device Interrupt Vector Table)
OCMP1
pin
OCMP2
pin
EXEDG
71/215
ST72F521, ST72521B
16-BIT TIMER (Cont’d)
16-bit read sequence: (from either the Counter
Register or the Alternate Counter Register).
Beginning of the sequence
Read
At t0
MS Byte
Other
instructions
Read
At t0 +∆t
LS Byte
Sequence completed
The user must read the MS Byte first , the n th e LS
Byte value is buffered automatically.
This buffered value remains unchanged until the
16-bit read sequence is completed, even if the
user reads the MS Byte several times.
After a complete reading sequence, if only the
CLR register or ACLR register are read, they return the LS Byte of the count value at the time of
the read.
Whatever the timer mode used (inpu t capture, output compare, one pulse mode or PWM mode) an
overflow occurs when the counter rolls over from
FFFFh to 0000h then:
– The TOF bit of the SR register is set.
– A timer interrupt is generated if:
– TOIE bit of the CR1 register is set and
– I bit of the CC register is cleared.
If one of these conditions is false, the interrupt remains pending to be issued as soon as they are
both true.
LS Byte
is buffered
Returns the buffered
LS Byte value at t0
Clearing the overflow interrupt request is done in
two steps:
1.Reading the SR register while the TOF bit is set.
2.An access (read or write) to the CLR register.
Notes: The TOF bit is not cleared by accesses to
ACLR register. The advantage of accessing the
ACLR register rather than the CLR register is that
it allows simultaneous use of the overflow function
and reading the free running counter at random
times (for example, to measure elapsed time) without the risk of clearing the TOF bit erroneously.
The timer is not affected by WAIT mode.
In HALT mode, the counter stops counting until the
mode is exited. Counting then resumes from the
previous count (MCU awakened by an interrupt) or
from the reset count (MCU awakened by a Reset) .
10.4.3.2 External Clock
The external clock (where available) is selected if
CC0=1 and CC1=1 in the CR2 register.
The status of the EXEDG bit in the CR2 register
determines the type of level transition on the external clock pin EXTCLK that will trigger the free running counter.
The counter is synchronized with the falling edge
of the internal CPU clock.
A minimum of four falling edges of the CPU clock
must occur between two consecutive active edges
of the external clock; thus the external clock frequency must be less than a quarter of the CPU
clock frequency.
Figure 44. Counter Timing Diagram, internal clock divided by 4
CPU CLOCK
INTERNAL RESET
TIMER CLOCK
COUNTER REGISTER
TIMER OVERFLOW FLAG (TOF)
FFFCFFFD00000001
Figure 45. Counter Timing Diagram, internal clock divided by 8
CPU CLOCK
INTERNAL RESET
TIMER CLOCK
COUNTER REGISTER
TIMER OVERFLOW FLAG (TOF)
FFFCFFFD
0000
Note: The MCU is in reset state when the internal reset signal is high, when it is low the MCU is running.
73/215
ST72F521, ST72521B
16-BIT TIMER (Cont’d)
10.4.3.3 Input Capture
In this section, the index, i, may be 1 or 2 becau se
there are 2 input capture functions in the 16-bit
timer.
The two 16-bit input capture registers (IC1R and
IC2R) are used to latch the value of the free running counter after a transition is detected on the
ICAPi pin (see figure 5).
MS ByteLS Byte
ICiRICiHRICiLR
ICiR register is a read-only register.
The active transition is software programmable
through the IEDGi bit of Control Registers (CRi).
Timing resolution is one count of the free running
f
counter: (
Procedure:
To use the input capture function select the following in the CR2 register:
– Select the t imer clock (CC[1:0]) (see Table 16
Clock Control Bits).
– Select the edge of the active transition on the
ICAP2 pin with the IEDG2 bit (the ICAP2 pin
must be configured as floating input or input with
pull-up without interrupt if this configuration is
available).
And select the following in the CR1 register:
– Set the ICIE bit to generate an interrupt after an
input capture coming from either the ICAP1 pin
or the ICAP2 pin
– Select the edge of the active transition on the
ICAP1 pin with the IEDG1 bit (the ICAP1pin must
be configured as floating input or input with pull-
up without interrupt if this configuration is availa-
ble).
CPU
/CC[1:0]).
When an input capture occurs:
– ICFi bit is set.
– The ICiR register contains the value of the free
running counter on the active transition on the
ICAPi pin (see Figure 47).
– A timer interrupt is generated if the ICIE bit is set
and the I bit is cleared in the CC register . Other wise, the interrupt remains pending until both
conditions become true.
Clearing the Input Capture interrupt request (i.e.
clearing the ICFi bit) is done in two steps:
1. Reading the SR register while the ICFi bit is set.
2. An access (read or write) to the ICiLR register.
Notes:
1. After reading the ICiHR register, transfer of
input capture data is inhibited and ICFi will
never be set until the ICiLR register is also
read.
2. The ICiR register contains the free running
counter value which corresponds to the most
recent input capture.
3. The 2 input capture functions can be used
together even if the timer also uses the 2 output
compare functions.
4. In One pulse Mode and PWM mode only Input
Capture 2 can be used.
5. The alternate inputs (ICAP1 & ICAP2) are
always directly connected to th e timer. So any
transitions on these pins activates the input
capture function.
Moreover if one of the ICAPi pins is configured
as an input and the second one as an output,
an interrupt can be generated if the user toggles the output pin and if the ICIE bit is set.
This can be avoided if the input capture function i is disabled by reading the ICiHR (see note
1).
6. The TOF bit can be used with interrupt generation in order to measure events that go beyond
the timer range (FFFFh).
In this section, the index, i, may be 1 or 2 becau se
there are 2 output compare functions in the 16-bit
timer.
This function can be used to control an output
waveform or indicate when a period of time has
elapsed.
When a match is found between the Output Compare register and the free running counter, the ou tput compare function:
– Assigns pins with a programmable value if the
OCiE bit is set
– Sets a flag in the status register
– Generates an interrupt if enabled
Two 16-bit registers Output Compare Register 1
(OC1R) and Output Compare Register 2 (OC2R)
contain the value to be compared to the counter
register each timer clock c ycle.
MS ByteLS Byte
OCiROCiHROCiLR
These registers are readable and writable and are
not affected by the timer hardware . A reset event
changes the OC
Timing resolution is one count of the free running
counter: (
Procedure:
To use the output compare function, select the following in the CR2 register:
– Set the OCiE bit if an output is needed then the
OCMPi pin is dedicated to the output compare i
signal.
– Select the t imer clock (CC[1:0]) (see Table 16
Clock Control Bits).
And select the following in the CR1 register:
– Select the OLVLi bit to applied to the OCMPi pins
after the match occurs.
– Set the OCIE bit to generate an interrupt if it is
needed.
When a match is found between OCRi register
and CR register:
– OCFi bit is set.
iR value to 8000h.
f
CC[1:0]
CPU/
).
– The OCMPi pin takes OLVLi bit value (OCMPi
pin latch is forced low during reset).
– A timer interrupt is generated if the OCIE bit is
set in the CR1 register and the I bit is cleared in
the CC register (CC).
The OC
iR register value required for a specific ti m-
ing application can be calculated using the following formula:
∆t * f
∆ OCiR =
CPU
PRESC
Where:
∆t = Output compare period (in seconds)
f
= CPU clock frequency (in hertz)
CPU
PRESC
= Timer prescaler factor (2, 4 or 8 de-
pending on CC[1:0] bits, see Table 16
Clock Control Bits)
If the timer clock is an external clock, the fo rmula
is:
∆ OCiR = ∆t
* fEXT
Where:
∆t = Output compare period (in seconds)
= External timer clock frequency (in hertz)
f
EXT
Clearing the output compare interru pt re qu est ( i. e.
clearing the OCFi bit) is done by:
1. Reading the SR register while the OCFi bit is
set.
2. An access (read or write) to the OCiLR regi ster .
The following procedure is recommended to prevent the OCFi bit from being set between the time
it is read and the write to the OC
– Write to the OCiHR register (further compares
are inhibited).
– Read the SR register (first step of the clearance
of the OCFi bit, which may be already set).
– Write to the OCiLR register (enables the output
compare function and clears the OCFi bit).
iR register:
76/215
16-BIT TIMER (Cont’d)
Notes:
1. After a processor write cycle to the OCiHR reg-
ister, the output compare function is inhibited
until the OCiLR register is also written.
2. If the OCiE bit is not set, the OCMPi pin is a
general I/O port and the OLVLi bit will not
appear when a match is found but an interrupt
could be generated if the OCIE bit is set.
3. When the timer clock is f
/2, OCFi and
CPU
OCMPi are set while the counter value equals
the OCiR register value (see Figure 49 on page
78). This behaviour is the same in OPM or
PWM mode.
When the timer clock is f
CPU
/4, f
CPU
/8 or in
external clock mode, OCFi and OCMPi are set
while the counter value equals the OC iR register value plus 1 (see Figure 50 on page 78).
4. The output compare functions ca n be used both
for generating external events on the OCMPi
pins even if the input capture mode is also
used.
5. The value in the 16-bit OC
iR register and the
OLVi bit should be changed after each successful comparison in order to control an output
waveform or establish a new elapsed timeout.
ST72F521, ST72521B
Forced Compare Output capability
When the FOLVi bit is set by software, the OLVLi
bit is copied to the OCMPi pin. The OLVi bit has to
be toggled in order to toggle the OCMPi pin when
it is enabled (OCiE bit=1). The OCFi bit is then not
set by hardware, and thus no interrupt request is
generated.
The FOLVLi bits have no effect in both one pulse
mode and PWM mode.
Figure 48. Output Compare Block Diagram
16 BIT FREE RUNNING
COUNTER
16-bit
OUTPUT COMPARE
CIRCUIT
16-bit
OC1R Register
16-bit
OC2R Register
OC1ECC0CC1
OC2E
(Control Register 2) CR2
(Control Register 1) CR1
FOLV1
FOLV2
(Status Register) SR
OLVL1OLVL2OCIE
000OCF2OCF1
Latch
1
Latch
2
OCMP1
Pin
OCMP2
Pin
77/215
ST72F521, ST72521B
16-BIT TIMER (Cont’d)
Figure 49. Output Compare Timing Diagram, f
INTERNAL CPU CLOCK
TIMER CLOCK
TIMER
=f
CPU
/2
COUNTER REGISTER
OUTPUT COMPARE REGISTER i (OCRi)
OUTPUT COMPARE FLAG i (OCFi)
OCMPi PIN (OLVLi=1)
Figure 50. Output Compare Timing Diagram, f
INTERNAL CPU CLOCK
TIMER CLOCK
COUNTER REGISTER
OUTPUT COMPARE REGISTER i (OCRi)
COMPARE REGISTER i LATCH
OUTPUT COMPARE FLAG i (OCFi)
OCMPi PIN (OLVLi=1)
2ED0 2ED1 2ED2
=f
TIMER
CPU
2ED0 2ED1 2ED2
/4
2ED3
2ED3
2ED3
2ED3
2ED42ECF
2ED42ECF
78/215
16-BIT TIMER (Cont’d)
10.4.3.5 One Pulse Mode
One Pulse mode enables the generation of a
pulse when an external event occurs. This mode is
selected via the OPM bit in the CR2 register.
The one pulse mode uses the Input Capture1
function and the Output Compare1 function.
Procedure:
To use one pulse mode:
1. Load the OC1R register with the value corresponding to the length of the pulse (see the formula in the opposite column).
2. Select the following in the CR1 register:
– Using the OLVL1 bit, select the level to be ap-
plied to the OCMP1 pin after the pulse.
– Using the OLVL2 bit, select the level to be ap-
plied to the OCMP1 pin during the pulse.
– Select the edge of the active transition on the
ICAP1 pin with the IEDG1 bit (the ICAP1 pi n
must be configured as floating input).
3. Select the following in the CR2 register:
– Set the OC1E bit, the OCMP1 pin is then ded-
icated to the Output Compare 1 function.
– Set the OPM bit.
– Select the timer clock CC[1:0] (see Table 16
Clock Control Bits).
ST72F521, ST72521B
Clearing the Input Capture interrupt request (i.e.
clearing the ICFi bit) is done in two steps:
1. Reading the SR register while the ICFi bit is set.
2. An access (read or write) to the ICiLR register.
The OC1R register value required for a specific
timing application can be calculated using the following formula:
t
f
*
OCiR Value =
CPU
PRESC
Where:
t = Pulse period (in seconds)
= CPU clock frequency (in hertz)
f
CPU
PRESC
= Timer prescaler factor (2, 4 or 8 depend-
ing on the CC[1:0] bits, see Table 16
Clock Control Bits)
If the timer clock is an external clock the formula is:
OCiR = t
* fEXT
-5
Where:
t = Pulse period (in seconds)
= External timer clock frequency (in hertz)
f
EXT
When the value of the counter is equal to the value
of the contents of the OC 1R register, the OLVL1
bit is output on the OCMP1 pin, (See Figure 51).
- 5
One pulse mode cycle
When
event occurs
on ICAP1
ICR1 = Counter
OCMP1 = OLVL2
Counter is reset
to FFFCh
ICF1 bit is set
When
Counter
= OC1R
OCMP1 = OLVL1
Then, on a valid event on the ICAP1 pin, the co unter is initialized to FFFCh and OLVL2 bit is loaded
on the OCMP1 pin, the ICF1 bit is set and the value FFFDh is loaded in the IC1R register.
Because the ICF1 bit is set when an active edge
occurs, an interrupt can be generated if the ICIE
bit is set.
Notes:
1. The OCF1 bit cannot be set by hard wa re in one
pulse mode but the OCF2 bit can generate an
Output Compare interrupt.
2. When the Pulse Width Modulation (PWM) and
One Pulse Mode (OPM) bits are both set, the
PWM mode is the only active one.
3. If OLVL1=OLVL2 a continuous signal will be
seen on the OCMP1 pin.
4. The ICAP1 pin can not be used to pe rform input
capture. The ICAP2 pin can be used to perform
input capture (ICF2 can be set and IC2R ca n be
loaded) but the user must take care that the
counter is reset each time a valid edge occurs
on the ICAP1 pin and ICF1 can also generates
interrupt if ICIE is set.
5. When one pulse mode is used OC1R is dedicated to this mode. Nevertheless OC2R and
OCF2 can be used to indicate a period of time
has been elapsed but cannot generate an output waveform because the level OLVL2 is dedicated to the one pulse mode.
79/215
ST72F521, ST72521B
16-BIT TIMER (Cont’d)
Figure 51. One Pulse Mode Timing Example
IC1R
COUNTER
ICAP1
OCMP1
01F8
FFFC
FFFD FFFE2ED0
OLVL2
01F8
2ED1
2ED2
2ED3
2ED3
FFFC FFFD
OLVL2OLVL1
compare1
Note: IEDG1=1, OC1R=2ED0h, OLVL1=0, OLVL2=1
Figure 52. Pulse Width Modulation Mode Timing Example with 2 Output Compare Functions
COUNTER
OCMP1
FFFC FFFD FFFE
34E2
OLVL2
2ED0 2ED1 2ED2
OLVL1
34E2 FFFC
OLVL2
compare2compare1compare2
Note: OC1R=2ED0h, OC2R=34E2, OLVL1=0, OLVL2= 1
Note: On timers with only 1 Out put Compare register, a f ixed frequency PWM signal can be g enerated us-
ing the output compare and the counter overflow to define the pulse length.
80/215
16-BIT TIMER (Cont’d)
10.4.3.6 Pulse Width Modulation Mode
Pulse Width Modulation (PWM) mode enables the
generation of a signal with a frequency and pulse
length determined by the value of the OC1R and
OC2R registers.
Pulse Width Modulation mode uses the complete
Output Compare 1 function plus the OC2R register, and so this functionality can not be used when
PWM mode is activated.
In PWM mode, double buffering is implemen ted on
the output compare registers. Any new values written in the OC1R and OC2R registers are taken
into account only at the end of the PWM period
(OC2) to avoid spikes on the PWM output pin
(OCMP1).
Procedure
To use pulse width modulation mode:
1. Load the OC2R register with the value corresponding to the period of the signal using the
formula in the opposite column.
2. Load the OC1R register with the value corresponding to the period of the pulse if (OLVL1=0
and OLVL2=1) using the formula in the opposite column.
3. Select the following in the CR1 register:
– Using the OLVL1 bit, select the level to be ap-
plied to the OCMP1 pin after a successful
comparison with the OC1R register.
– Using the OLVL2 bit, select the level to be ap-
plied to the OCMP1 pin after a successful
comparison with the OC2R register.
4. Select the following in the CR2 register:
– Set OC1E bit: the OCMP1 pin is then dedi cat-
ed to the output compare 1 function.
– Set the PWM bit.
– Select the timer clock (CC[1:0]) (see T able 16
Clock Control Bits).
Pulse Width Modulation cycle
When
Counter
OCMP1 = OLVL1
= OC1R
When
Counter
= OC2R
OCMP1 = OLVL2
Counter is reset
to FFFCh
ST72F521, ST72521B
If OLVL1=1 and OLVL2=0 the length of the positive pulse is the difference between t he OC2R and
OC1R registers.
If OLVL1=OLVL2 a continuous signal will be seen
on the OCMP1 pin.
The OC
ing application can be calculated using the following formula:
Where:
t = Signal or pulse period (in seconds)
f
CPU
PRESC
If the timer clock is an external clock the formula is:
Where:
t = Signal or pulse period (in seconds)
f
EXT
The Output Compare 2 event causes the counter
to be initialized to FFFCh (See Figure 52)
Notes:
1. After a write instruction to the OCiHR register,
2. The OCF1 and OCF2 bits cannot be set by
3. The ICF1 bit is set by hardware when the coun-
4. In PWM mode the ICAP1 pin can not be used
5. When the Pulse Width Modulation (PWM) and
iR register value required for a specific ti m-
t
f
*
OCiR Value =
CPU
PRESC
- 5
= CPU clock frequency (in hertz)
= Timer prescaler factor (2, 4 or 8 depend-
ing on CC[1:0] bits, see Table 16 Clock
Control Bits)
OCiR = t
* fEXT
-5
= External timer clock frequency (in hertz)
the output compare function is inhibited until the
OCiLR register is also written.
hardware in PWM mode therefore the Output
Compare interrupt is inhibited.
ter reaches the OC2R value and can produce a
timer interrupt if the ICIE bit is set and the I bit is
cleared.
to perform input capture because it is disconnected to the timer. The ICAP2 pin can be used
to perform input capture (ICF2 can be set and
IC2R can be loaded) but the user must take
care that the counter is reset each period and
ICF1 can also generates interrupt if ICIE is set.
One Pulse Mode (OPM) bits are both set, the
PWM mode is the only active one.
ICF1 bit is set
81/215
ST72F521, ST72521B
16-BIT TIMER (Cont’d)
10.4.4 Low Power Modes
Mode Description
WAIT
HALT
10.4.5 Interrupts
Input Capture 1 event/Counter reset in PWM modeICF1
Input Capture 2 eventICF2YesNo
Output Compare 1 event (not available in PWM mode)OCF1
Output Compare 2 event (not available in PWM mode)OCF2YesNo
Timer Overflow eventTOFTOIEYesNo
No effect on 16-bit Timer.
Timer interrupts cause the device to exit from WAIT mode.
16-bit Timer registers are frozen.
In HALT mode, the counter stops counting until Halt mode is exited. Counting resumes from the previous
count when the MCU is woken up by an interrupt with “exit from HALT mode” capability or from the counter
reset value when the MCU is woken up by a RESET.
If an input capture event occurs on the ICAPi pin, the input capture detection circuitry is armed. Consequently, when the MCU is woken up by an interrupt with “exit from HALT mode” capability, the ICFi bit is set, and
the counter value present when exiting from HALT mode is captured into the ICiR register.
Interrupt Event
Event
Flag
Enable
Control
Bit
ICIE
OCIE
Exit
from
Wait
YesNo
YesNo
Exit
from
Halt
Note: The 16-bit Timer interrupt events are connected to the same interrupt vector (see Interrupts chap-
ter). These events generate an int errupt if the corresponding Enable Control Bit is set and the interrupt
mask in the CC register is reset (RIM instruction).
3) See note 4 in Section 10.4.3.6 Pulse Width Modulation Mode
82/215
16-BIT TIMER (Cont’d)
10.4.7 Register Description
Each Timer is associated with three control and
status registers, and with six pairs of data registers
(16-bit values) relating to the two input captures,
the two output compares, the counter and the alternate counter.
ST72F521, ST72521B
Bit 4 = FOLV2 Forced Output Compare 2.
This bit is set and cleared by software.
0: No effect on the OCMP2 pin.
1:Forces the OLVL2 bit to be copied to the
OCMP2 pin, if the OC2E bit is set and even if
there is no successful comparison.
CONTROL REGISTER 1 (CR1)
Read/Write
Reset Value: 0000 0000 (00h)
70
ICIE O C IE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1
Bit 3 = FOLV1 Forced Output Compare 1.
This bit is set and cleared by software.
0: No effect on the OCMP1 pin.
1: Forces OLVL1 to be copied to the OCMP1 pin, if
the OC1E bit is set and even if there is no successful comparison.
Bit 2 = OLVL2 Output Level 2.
Bit 7 = ICIE Input Capture Interrupt Enable.
0: Interrupt is inhibited.
1: A timer interrupt is generated whenever the
ICF1 or ICF2 bit of the SR register is set.
Bit 6 = OCIE Output Compare Interrupt Enable.
0: Interrupt is inhibited.
1: A timer interrupt is generated whenever the
OCF1 or OCF2 bit of the SR register is set.
This bit is copied to the OCMP2 pin whenever a
successful comparison occurs with the OC2R register and OCxE is set in the CR2 register. This value is copied to the OCMP1 pin in One Pulse Mode
and Pulse Width Modulation mode.
Bit 1 = IEDG1 Input Edge 1.
This bit determines which type of level transition
on the ICAP1 pin will trigger the capture.
0: A falling edge triggers the capture.
1: A rising edge triggers the capture.
Bit 5 = TOIE Timer Overflow Interrupt Enable.
0: Interrupt is inhibited.
1: A timer interrupt is enabled whenever the TOF
bit of the SR register is set.
Bit 0 = OLVL1 Output Level 1.
The OLVL1 bit is copied to the OCMP1 pin whenever a successful comparison occurs with the
OC1R register and the OC1E bit is set in the CR2
register.
83/215
ST72F521, ST72521B
16-BIT TIMER (Cont’d)
CONTROL REGISTER 2 (CR2)
Read/Write
Reset Value: 0000 0000 (00h)
70
OC1E OC2E OPM PWM CC1 CC0 IEDG2 EXEDG
Bit 4 = PWM Pulse Width Modulation.
0: PWM mode is not active.
1: PWM mode is active, the OCMP1 pin outputs a
programmable cyclic signal; the length of the
pulse depends on the value of OC1R register;
the period depends on the value of OC2R register.
Bit 7 = OC1E Output Compare 1 Pin Enable.
This bit is used only to output the signal from the
timer on the OCMP1 pin (OLV1 in Output Compare mode, both OLV1 and OLV2 in PWM and
one-pulse mode). Whatever the value of the OC1E
bit, the Output Compare 1 function of the timer remains active.
0: OCMP1 pin alternate function disabled (I/O pin
free for general-purpose I/O).
1: OCMP1 pin alternate function enabled.
Bit 6 = OC2E Output Compare 2 Pin Enable.
This bit is used only to output the signal from the
timer on the OCMP2 pin (OLV2 in Output Compare mode). Whatever the value of the OC2E bit,
the Output Compare 2 function of the timer remains active.
0: OCMP2 pin alternate function disabled (I/O pin
free for general-purpose I/O).
1: OCMP2 pin alternate function enabled.
Bit 5 = OPM One Pulse Mode.
0: One Pulse Mode is not active.
1: One Pulse Mode is active, the ICAP1 pin can be
used to trigger one pulse on the OCMP1 pin; the
active transition is given by the IEDG1 bit. The
length of the generated pulse depends on the
contents of the OC1R register.
Bit 3, 2 = CC[1:0] Clock Control.
The timer clock mode depends on these bits:
Table 16. Clock Control Bits
Timer ClockCC1CC0
f
/ 400
CPU
f
/ 201
CPU
f
/ 810
CPU
External Clock (where
available)
11
Note: If the external clock pin is not available , programming the external clock configuration stops
the counter.
Bit 1 = IEDG2 Input Edge 2.
This bit determines which type of level transition
on the ICAP2 pin will trigger the capture.
0: A falling edge triggers the capture.
1: A rising edge triggers the capture.
Bit 0 = EXEDG External Clock Edge.
This bit determines which type of level transition
on the external clock pin EXTCLK will trigger the
counter register.
0: A falling edge triggers the counter register.
1: A rising edge triggers the counter register.
Bit 7 = ICF1 Input Capture Flag 1.
0: No input capture (reset value).
1: An input capture has occurred on the ICAP1 pin
or the counter has reached the OC2R value in
PWM mode. To clear this bit, first read the SR
register, then read or write the low byte of the
IC1R (IC1LR) register.
Bit 6 = OCF1 Output Compare Flag 1.
0: No match (reset value).
1: The content of the free running counter has
matched the content of the OC1R register. To
clear this bit, first read the SR register, then read
or write the low byte of the OC1R (OC1LR) register.
Bit 5 = TOF Timer Overflow Flag.
0: No timer overflow (reset value).
1:The free running counter rolled over from FFFFh
to 0000h. To clear this bit, first read the SR register, then read or write the low byte of the CR
(CLR) register.
Note: Reading or writing the ACLR register does
not clear TOF.
Bit 4 = ICF2 Input Capture Flag 2.
0: No input capture (reset value).
1: An input capture has occurred on the ICAP2
pin. To clear this bit, first read the SR register,
then read or write the low byte of the IC2R
(IC2LR) register.
Bit 3 = OCF2 Output Compare Flag 2.
0: No match (reset value).
1: The content of the free running counter has
matched the content of the OC2R register. To
clear this bit, first read the SR register, then read
or write the low byte of the OC2R (OC2LR) register.
Bit 2 = TIMD Timer disable.
This bit is set and cleared by software. When set, it
freezes the timer presca ler and counter an d disabled the output functions (OCMP1 and OCMP2
pins) to reduce power consumption. Access to the
timer registers is still available, allowing the timer
configuration to be changed, or the counter reset,
while it is disabled.
0: Timer enabled
1: Timer prescaler, counter and outputs disabled
Bits 1:0 = Reserved, must be kept cleared.
85/215
ST72F521, ST72521B
16-BIT TIMER (Cont’d)
INPUT CAPTURE 1 HIGH REGISTER (IC1HR)
Read Only
Reset Value: Undefined
This is an 8-bit read only register that contains the
high part of the counter value (transferred by the
input capture 1 event).
OUTPUT COMPARE 1 HIGH REGISTER
(OC1HR)
Read/Write
Reset Value: 1000 0000 (80h)
This is an 8-bit register that contains the high part
of the value to be compared to the CHR register.
70
MSBLSB
INPUT CAPTURE 1 LOW REGISTER (IC1LR)
Read Only
Reset Value: Undefined
This is an 8-bit read only register that contains the
low part of the counter value (transferred by the input capture 1 event).
70
MSBLSB
70
MSBLSB
OUTPUT COMPARE 1 LOW REGISTER
(OC1LR)
Read/Write
Reset Value: 0000 0000 (00h)
This is an 8-bit register that contains the low part of
the value to be compared to the CLR register.
70
MSBLSB
86/215
16-BIT TIMER (Cont’d)
OUTPUT COMPARE 2 HIGH REGISTER
(OC2HR)
Read/Write
Reset Value: 1000 0000 (80h)
This is an 8-bit register that contains the high part
of the value to be compared to the CHR register.
ST72F521, ST72521B
ALTERNATE COUNTER HIGH REGISTER
(ACHR)
Read Only
Reset Value: 1111 1111 (FFh)
This is an 8-bit register that contains the high part
of the counter value.
70
MSBLSB
OUTPUT COMPARE 2 LOW REGISTER
(OC2LR)
Read/Write
Reset Value: 0000 0000 (00h)
This is an 8-bit register that contains the low part of
the value to be compared to the CLR register.
70
70
MSBLSB
ALTERNATE COUNTER LOW REGISTER
(ACLR)
Read Only
Reset Value: 1111 1100 (FCh)
This is an 8-bit register that contains the low part of
the counter value. A write to this register resets the
counter. An access to this register aft er an access
to CSR register does not clear the TOF bit in the
CSR register.
MSBLSB
COUNTER HIGH REGISTER (CHR)
70
MSBLSB
Read Only
Reset Value: 1111 1111 (FFh)
This is an 8-bit register that contains the high part
of the counter value.
70
INPUT CAPTURE 2 HIGH REGISTER (IC2HR)
Read Only
Reset Value: Undefined
This is an 8-bit read only register that conta ins the
high part of the counter value (transferred by the
MSBLSB
Input Capture 2 event).
70
COUNTER LOW REGISTER (CLR)
MSBLSB
Read Only
Reset Value: 1111 1100 (FCh)
This is an 8-bit register that contains the low part of
the counter value. A write to this register resets the
counter. An access to this register after accessing
the CSR register clears the TOF bit.
70
INPUT CAPTURE 2 LOW REGISTER (IC2LR)
Read Only
Reset Value: Undefined
This is an 8-bit read only register that conta ins the
low part of the counter value (transferred by the Input Capture 2 event).
true 0 or 100 per cent duty cycle
AN1504: Starting a PWM signal directly at high
level using the ST7 16-Bit timer
10.5 SERIAL PERIPHERAL INTERFACE (SPI)
ST72F521, ST72521B
10.5.1 Introduction
The Serial Peripheral Interface (SPI) allows fullduplex, synchronous, serial communication with
external devices. An SPI system may consist of a
master and one or more slaves however the SPI
interface can not be a master in a multi-master
system.
10.5.2 Main Features
■ Full duplex synchronous transfers (on 3 lines)
■ Simplex synchronous transfers (on 2 lines)
■ Master or slave operation
■ Six master mode frequencies (f
■ f
/2 max. slave mode frequency (see note)
CPU
■ SS Management by software or hardware
■ Programmable clock polarity and phase
■ End of transfer interrupt flag
■ Write collision, Master Mode Fa ult a nd Ov erru n
CPU
/4 max.)
flags
Figure 53. Serial Peripheral Interface Block Diagram
Data/Address Bus
SPIDR
Read Buffer
Read
Note: In slave mode, continuous transmission is
not possible at maximum frequency due to the
software overhead for clearing st atus flags and to
initiate the next transmission sequence.
10.5.3 General Description
Figure 53 shows the serial peripheral interface
(SPI) block diagram. There are 3 registers:
– SPI Control Register (SPICR)
– SPI Control/Status Register (SPICSR)
– SPI Data Register (SPIDR)
The SPI is connected to external devices through
4 pins:
– MISO: Master In / Slave Out data
– MOSI: Master Out / Slave In data
– SCK: Serial Clock out by SPI masters an d in-
put by SPI slaves
Interrupt
request
MOSI
MISO
SCK
SS
SOD
bit
8-Bit Shift Register
Write
MASTER
CONTROL
SERIAL CLOCK
GENERATOR
SPIF WCOLMODF
SPIE SPE
OVRSSISSMSOD
SPI
STATE
CONTROL
MSTR
SPR2
0
CPOL
SS
CPHA
SPICSR
1
0
SPICR
SPR1
07
07
SPR0
89/215
ST72F521, ST72521B
SERIAL PERIPHERAL INTERFACE (Cont’d)
–SS
: Slave select:
This input signal acts as a ‘chip select’ to let
the SPI master communicate with slaves individually and to avoid contention on the data
lines. Slave SS
ard I/O ports on the master MCU.
10.5.3.1 Functional Description
A basic example of interconnections between a
single master and a single slave is illustrated in
Figure 54.
The MOSI pins are connected together and the
MISO pins are connected together. In this way
data is transferred serially between master and
slave (most significant bit first).
Figure 54. Single Master/ Single Slave Application
inputs can be driven by stand-
The communication is always initiated by the master. When the master device transmits data to a
slave device via MOSI pin, the slave device responds by sending data to the master device via
the MISO pin. This implies full duplex communication with both data out and data in synchronized
with the same clock signal (which is provided by
the master device via the SCK pin).
To use a single data line, the MISO and MOSI p ins
must be connected at each node ( in this case only
simplex communication is possible).
Four possible data/clock timing relationships may
be chosen (see Figure 57) but master and slave
must be programmed with the same timing mode.
MASTER
MSBitLSBitMSBitLSBit
8-BIT SHIFT REGISTER
SPI
CLOCK
GENERATOR
MISO
MOSI
SCK
SS
+5V
MISO
MOSI
SCK
SS
8-BIT SHIFT REGISTER
SLAVE
Not used if SS is managed
by software
90/215
SERIAL PERIPHERAL INTERFACE (Cont’d)
10.5.3.2 Slave Select Management
As an alternative to using the SS
pin to control the
Slave Select signal, the application can choose to
manage the Slave Select signal by software. This
is configured by the SSM bit in the SPICSR register (see Figure 56)
In software management, the external SS
pin is
free for other application uses and th e intern al SS
signal level is driven by writing to the SSI bit in the
SPICSR register.
In Master mode:
–SS
internal must be held high continuously
ST72F521, ST72521B
In Slave Mode:
There are two cases depending on the data/clock
timing relationship (see Figure 55):
If CPHA=1 (data latched on 2nd clock edge):
–SS
internal must be held low during the entire
transmission. This implies that in single slave
applications the SS
V
, or made free for standard I/O b y mana g-
SS
ing the SS
function by software (SSM= 1 and
SSI=0 in the in the SPICSR register)
If CPHA=0 (data latched on 1st clock edge):
–SS
internal must be held low during byte
transmission and pulled high between each
byte to allow the slave to write to the shift register. If SS
is not pulled high, a Write Collision
error will occur when the s lave writes to the
shift register (see Section 10.5.5.3).
In master mode, the serial clock is output on the
SCK pin. The clock frequency, polarity and phase
are configured by software (refer to the description
of the SPICSR register).
Note: The idle state of SCK must correspond to
the polarity selected in the SPICSR register (by
pulling up SCK if CPOL=1 or pulling down SCK if
CPOL=0).
To operate the SPI in master mode, perform the
following steps in order (if the SPICSR register is
not written first, the SPICR register setting (M STR
bit) may be not taken into account):
1. Write to the SPICR register:
– Select the clock frequency by configuring the
SPR[2:0]bits.
– Select the clock polarity and c lock phase by
configuring the CPOL and CPHA bits. Figure
57 shows the four possible configurations.
Note: T he slave must have the same CPOL
and CPHA settings as the master.
2. Write to the SPICSR register:
– Either set the SSM bit and set the SSI bit or
clear the SSM bit and t ie the SS
the complete byte transmit sequence.
3. Write to the SPICR register:
– Set the MSTR and SPE bits
Note: MSTR and SPE bits remain set only if
SS
is high).
The transmit sequence begins when software
writes a byte in the SPIDR register.
10.5.3.4 Master Mode Transmit Sequence
When software writes to t he SPIDR register, the
data byte is loaded into the 8-bit shift register and
then shifted out serially to the MOSI pin most significant bit first.
When data transfer is complete:
– The SPIF bit is set by hardware
– An interrupt request is generated if the SPIE
bit is set and the interrupt mask in the CCR
register is cleared.
Clearing the SPIF bit is performed by the following
software sequence:
1. An access to the SPICSR register while the
SPIF bit is set
2. A read to the SPIDR register.
pin high for
Note: While the SPIF bit is set, all writes to the
SPIDR register are inhibited until the SPICSR register is read.
10.5.3.5 Slave Mode Operation
In slave mode, the serial clock is received on the
SCK pin from the master device.
To operate the SPI in slave mode:
1. Write to the SPICSR register to perform the following actions:
– Select the clock polarity and clock phase by
configuring the CPOL and CPHA bits (see
Figure 57).
Note: The slave must have the sa me CPOL
and CPHA settings as the master.
– Manage the SS
10.5.3.2 and Figure 55. If CPHA=1 SS
be held low continuously. If CPHA=0 SS
be held low during byte transmission and
pulled up between each byte to let the slave
write in the shift register.
2. Write to the SPICR register to clear the MSTR
bit and set the SPE bit to enable the SPI I/O
functions.
10.5.3.6 Slave Mode Transmit Sequence
When software writes to the SPIDR register, the
data byte is loaded into the 8-bit shift register and
then shifted out serially to the MISO pin most significant bit first.
The transmit sequence begins when the s lav e de vice receives the clock signal and the most significant bit of the data on its MOSI pin.
When data transfer is complete:
– The SPIF bit is set by hardware
– An interrupt request is generated if SPIE bit is
set and interrupt mask in the CCR register is
cleared.
Clearing the SPIF bit is performed by the following
software sequence:
1. An access to the SPICSR register while the
SPIF bit is set.
2. A write or a read to the SPIDR register .
Notes: While the SPIF bit is set, all writes to the
SPIDR register are inhibited until the SPICSR register is read.
The SPIF bit can be cleared during a second
transmission; however, it must be cleared before
the second SPIF bit in order to prevent an Overrun
condition (see Section 10.5.5.2).
pin as described in Section
must
must
92/215
SERIAL PERIPHERAL INTERFACE (Cont’d)
10.5.4 Clock Phase and Clock Polarity
Four possible timing relationships may be chosen
by software, using the CPOL and CPHA bits (See
Figure 57).
Note: The idle state of SCK must correspond to
the polarity selected in the SPICSR register (by
pulling up SCK if CPOL=1 or pulling down SCK if
CPOL=0).
The combination of the CPOL clock polarity and
CPHA (clock phase) bits selects the data capture
clock edge
Figure 57. Data Clock Timing Diagram
SCK
(CPOL = 1)
SCK
(CPOL = 0)
ST72F521, ST72521B
Figure 57, shows an SPI transfer with the four
combinations of the CPHA and CPOL bits. The diagram may be interpreted as a master or slave
timing diagram where the SCK pin, the MISO pin,
the MOSI pin are directly connected between the
master and the slave device.
Note: If CPOL is changed at the communication
byte boundaries, the SPI must be disabled by resetting the SPE bit.
CPHA =1
MISO
(from master)
MOSI
(from slave)
SS
(to slave)
CAPTURE STROBE
SCK
(CPOL = 1)
SCK
(CPOL = 0)
MISO
(from master)
MOSI
(from slave)
SS
(to slave)
CAPTURE STROBE
MSBitBit 6Bit 5
MSBitBit 6Bit 5
MSBitBit 6Bit 5
MSBitBit 6Bit 5
Bit 4Bit3Bit 2Bit 1LSBit
Bit 4 Bit3Bit 2Bit 1LSBit
CPHA =0
Bit 4Bit3Bit 2Bit 1LSBit
Bit 4Bit3Bit 2Bit 1LSBit
Note: This figure should not be used as a replacement for parametric information.
Refer to the Electrical Characteristics chapter.
93/215
ST72F521, ST72521B
SERIAL PERIPHERAL INTERFACE (Cont’d)
10.5.5 Error Flags
10.5.5.1 Master Mode Fault (MODF)
Master mode fault occurs when the master device
has its SS
When a Master mode fault occurs:
– The MODF bit is set and an SPI interrupt re-
– The SPE bit is reset. This blocks all output
– The MSTR bit is reset, thus forcing the device
Clearing the MODF bit is done through a software
sequence:
1. A read access to the SPICSR register while the
2. A write to the SPICR register.
Notes: To avoid any conflicts in an application
with multiple slaves, the SS
high during the MODF bit clearing sequence. The
SPE and MSTR bits may be restored to their original state during or after this clearing sequence.
Hardware does not allow the user to set the SPE
and MSTR bits while the MODF bit is set except in
the MODF bit clearing sequence.
10.5.5.2 Overrun Condition (OVR)
An overrun condition occurs, when the master device has sent a data byte and the slave device has
pin pulled low.
quest is generated if the SPIE bit is set.
from the device and disables the SPI peripheral.
into slave mode.
MODF bit is set.
pin must be pulled
not cleared the SPIF bit issued from the previously
transmitted byte.
When an Overrun occurs:
– The OVR bit is set and an interrupt request is
generated if the SPIE bit is set.
In this case, the receiver buffer contains the byte
sent after the SPIF bit was last cleared. A read to
the SPIDR register returns this byte. All other
bytes are lost.
The OVR bit is cleared by reading the SPICSR
register.
10.5.5.3 Write Collision Error (WCOL)
A write collision occurs when the software tries to
write to the SPIDR register while a data transfer is
taking place with an external device. When this
happens, the transfer continues uninterrupted;
and the software write will be unsuccessful.
Write collisions can occur both in master and slave
mode. See also Section 10.5.3.2 Slave Select
Management.
Note: a "read collision" will never occur since the
received data byte is placed in a buffer in which
access is always synchronous with the MCU operation.
The WCOL bit in the SPICSR register is set if a
write collision occurs.
No SPI interrupt is generated when the WCOL bit
is set (the WCOL bit is a status flag only).
Clearing the WCOL bit is done through a software
sequence (see Figure 58).
Figure 58. Clearing the WCOL bit (Write Collision Flag) Software Sequence
Clearing sequence after SPIF = 1 (end of a data byte transfer)
1st Step
2nd Step
Read SPICSR
Read SPIDR
RESULT
SPIF =0
WCOL=0
Clearing sequence before SPIF = 1 (during a data byte transfer)
1st Step
2nd Step
94/215
Read SPICSR
Read SPIDR
RESULT
WCOL=0
Note: Writin g to the SPIDR register instead of reading it does no t
reset the WCOL bit
SERIAL PERIPHERAL INTERFACE (Cont’d)
10.5.5.4 Single Master Systems
A typical single master system may be configured,
using an MCU as the master and four MCUs as
slaves (see Figure 59).
The master device selects the individual slave devices by using four pins of a parallel port to co ntro l
the four SS
The SS
master device ports will be forced to be inputs at
that time, thus disabling the slave devices.
Figure 59. Single Master / Multiple Slave Configuration
pins of the slave devices.
pins are pulled high during reset since the
Note: To prevent a bus conflict on the MISO line
the master allows only one active slave device
during a transmission.
For more security, the slave device may respond
to the master with the received data byte. Then the
master will receive the previous byte back from the
slave device if all MISO and MOSI pins are connected and the slave has not written to its SPIDR
register.
Other transmission security methods can use
ports for handshake lines or data bytes with command fields.
ST72F521, ST72521B
5V
SCK
MOSI
MOSI
SCK
Master
MCU
SS
SSSS
SCK
Slave
MCU
MOSIMOSIMOSIMISOMISOMISOMISO
MISO
Ports
Slave
MCU
SS
SCKSCK
Slave
MCU
SS
Slave
MCU
95/215
ST72F521, ST72521B
SERIAL PERIPHERAL INTERFACE (Cont’d)
10.5.6 Low Power Modes
Mode Description
WAIT
HALT
10.5.6.1 Using the SPI to wakeup the MCU f rom
Halt mode
In slave configuration, the SPI is able to wakeup
the ST7 device from HALT mode through a SPIF
interrupt. The data received is subsequently read
from the SPIDR register when the software is running (interrupt vector fetch). If multiple data transfers have been performed before software clears
the SPIF bit, then the OVR bit is set by hardware.
No effect on SPI.
SPI interrupt events cause the device to exit
from WAIT mode.
SPI registers are frozen.
In HALT mode, the SPI is inactive. SPI operation resumes when the MCU is woken up by
an interrupt with “exit from HALT mode” capability. The data received is subsequently
read from the SPIDR register when the software is running (interrupt vector fetching). If
several data are received before the wakeup event, then an overrun error is generated.
This error can be detected after the fetch of
the interrupt routine that woke up the device.
Note: When waking up from Halt mode, if the SPI
remains in Slave mode, it is recommended to perform an extra communications cycle to bring the
SPI from Halt mode state to normal state. If the
SPI exits from Slave mode, it returns to normal
state immediately.
Caution: The SPI can wake up the ST7 from Halt
mode only if the Slave Select signal (external SS
pin or the SSI bit in the SPICSR register) is low
when the ST7 enters Halt mode. So if Slave selection is configured as external (see Section
10.5.3.2), make sure the master drives a low level
on the SS
pin when the slave enters Halt mode.
10.5.7 Interrupts
Interrupt Event
SPI End of Transfer
Event
Master Mode Fault
Event
Overrun ErrorOVRYesNo
Event
Flag
SPIF
MODFYesNo
Enable
Control
Bit
SPIE
Exit
from
Wait
YesYes
Exit
from
Halt
Note: The SPI interrupt events are connected to
the same interrupt vector (see Interrupts chapter).
They generate an interrupt if the corresponding
Enable Control Bit is set and the interrupt mask in
96/215
ST72F521, ST72521B
SERIAL PERIPHERAL INTERFACE (Cont’d)
10.5.8 Register Description
CONTROL REGISTER (SPICR)
Read/Write
Reset Value: 0000 xxxx (0xh)
70
SPIE SPE SPR2 MSTR CPOL CPHA SPR1 SPR0
Bit 7 = SPIE Serial Peripheral Interrupt Enable.
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SPI interrupt is generated whenever
SPIF=1, MODF=1 or OVR=1 in the SPICSR
register
Bit 6 = SPE Serial Peripheral Output Enable.
This bit is set and cleared by software. It is also
cleared by hardware when, in master mode, SS
=0
(see Section 10.5.5.1 Master Mode Fault
(MODF)). The SPE bit is cleared by reset, so the
SPI peripheral is not initially connected to the external pins.
0: I/O pins free for general purpose I/O
1: SPI I/O pin alternate functions enabled
Bit 5 = SPR2 Divider Enable.
This bit is set and cleared by software and is
cleared by reset. It is used with the SPR[1:0] bits to
set the baud rate. Refer to Table 18 SPI Master
mode SCK Frequency.
0: Divider by 2 enabled
1: Divider by 2 disabled
Note: This bit has no effect in slave mode.
Bit 4 = MSTR Master Mode.
This bit is set and cleared by software. It is also
cleared by hardware when, in master mode, SS
=0
(see Section 10.5.5.1 Master Mode Fault
(MODF)).
0: Slave mode
1: Master mode. The function of the SCK pin
changes from an input to an output and the fun ctions of the MISO and MOSI pins are reversed.
Bit 3 = CPOL Clock Polarity.
This bit is set and cleared by software. T his bit determines the idle state of the serial Clock. The
CPOL bit affects both the master and slave
modes.
0: SCK pin has a low level idle state
1: SCK pin has a high level idle state
Note: If CPOL is changed at the communication
byte boundaries, the SPI must be disabled by resetting the SPE bit.
Bit 2 = CPHA Clock Phase.
This bit is set and cleared by software.
0: The first clock transition is the first data capture
edge.
1: The second clock transition is the first capture
edge.
Note: The slave must have the same CPOL and
CPHA settings as the master.
Bits 1:0 = SPR[1:0] Serial Clock Frequency.
These bits are set and cleared by software. Used
with the SPR2 bit, they select th e ba ud rat e of the
SPI serial clock SCK output by the SPI in master
mode.
Note: These 2 bits have no effect in slave mode.
Table 18. SPI Master mode SCK Frequency
Serial ClockSPR2SPR1SPR0
f
/4100
CPU
f
/8000
CPU
f
/16001
CPU
f
/32110
CPU
f
/64010
CPU
f
/128011
CPU
97/215
ST72F521, ST72521B
SERIAL PERIPHERAL INTERFACE (Cont’d)
CONTROL/STATUS REGISTER (SPICSR)
This bit is set by hardware when a transfer has
been completed. An interrupt is generated if
SPIE=1 in the SPICR register. It is cleared by a
software sequence (an access to the SPICSR
register followed by a write or a read to the
SPIDR register).
0: Data transfer is in progress or the flag h as been
cleared.
1: Data transfer between the device and an exter-
nal device has been completed.
Note: While the SPIF bit is set, all writes to the
SPIDR register are inhibited until the SPICSR register is read.
Bit 6 = WCOL Write Collision status (Read only).
This bit is set by hardware when a write to the
SPIDR register is done during a transmit sequence. It is cleared by a software sequence (see
Figure 58).
0: No write collision occurred
1: A write collision has been detected
Bit 5 = OVR SPI Overrun error (Read only).
This bit is set by hardware when the byte currently
being received in the shift register is ready to be
transferred into the SPIDR regist er while SPIF = 1
(See Section 10.5.5.2). An interrupt is generated if
SPIE = 1 in SPICR register. The OVR bit is cleared
by software reading the SPICSR register .
0: No overrun error
1: Overrun error detected
Bit 4 = MODF Mode Fault flag (Read only).
This bit is set by hardware when the SS
pin is
pulled low in master mode (see Section 10.5.5.1
Master Mode Fault (MODF)). An SPI interrupt can
be generated if SPIE=1 in the SPICSR register.
This bit is cleared by a software sequence (An access to the SPICR register while MODF=1 followed by a write to the SPICR register).
0: No master mode fault detected
1: A fault in master mode has been detected
Bit 3 = Reserved, must be kept cleared.
Bit 2 = SOD SPI Output Disable.
This bit is set and cleared by software. When set, it
disables the alternate function of the SPI output
(MOSI in master mode / MISO in slave mode)
0: SPI output enabled (if SPE=1)
1: SPI output disabled
Bit 1 = SSM SS
Management.
This bit is set and cleared by software. When set, it
disables the alternate function of the SPI SS
and uses the SSI bit value instead. See Section
10.5.3.2 Slave Select Management.
0: Hardware management (S S
nal pin)
1: Software management (internal SS
trolled by SSI bit. External SS
al-purpose I/O)
Bit 0 = SSI SS
Internal Mode.
This bit is set and cleared by software. It acts as a
‘chip select’ by controlling the level of the SS
select signal when the SSM bit is set.
0 : Slave selected
1 : Slave deselected
DATA I/O REGISTER (SPIDR)
Read/Write
Reset Value: Undefined
70
D7D6D5D4D3D2D1D0
The SPIDR register is used to transmit and receive
data on the serial bus. In a master device, a write
to this register will initiate transmission/reception
of another byte.
Notes: During the last clock cycle the SPIF bit is
set, a copy of the received data byte in the shift
register is moved to a buffer. When the user reads
the serial peripheral data I/O register, the buffer is
actually being read.
While the SPIF bit is set, all writes to the SPIDR
register are inhibited until the SPICSR register is
read.
Warning: A write to the SPIDR register places
data directly into the shift register for transmission.
A read to the SPIDR register returns the value located in the buffer and not the content of the shift
register (see Figure 53).
pin
managed by exter-
signal con-
pin free for gener-
slave
98/215
SERIAL PERIPHERAL INTERFACE (Cont’d)
Table 19. SPI Register Map and Reset Values
ST72F521, ST72521B
Address
(Hex.)
0021h
0022h
0023h
Register
Label
SPIDR
Reset Value
SPICR
Reset Value
SPICSR
Reset Value
76543210
MSB
xxxxxxx
SPIE
0
SPIF
0
SPE
0
WCOL
0
SPR20MSTR0CPOL
x
OR
0
MODF
00
CPHA
x
SOD
0
SPR1
x
SSM
0
LSB
x
SPR0
x
SSI
0
99/215
ST72F521, ST72521B
10.6 SERIAL COMMUNICATIONS INTERFACE (SCI)
10.6.1 Introduction
The Serial Communications Interface (SCI) offers
a flexible means of full-duplex data exchange with
external equipment requiring an industry standard
NRZ asynchronous serial data format. The SCI offers a very wide range of baud rates using two
baud rate generator systems.
10.6.2 Main Features
■ Full duplex, asynchronous communications
■ NRZ standard format (Mark/Space)
■ Dual baud rate generator systems
■ Independently programmable transmit and
receive baud rates up to 500K baud.
■ Programmable data word length (8 or 9 bits)
■ Receive buffer full, Transmit buffer empty and
End of Transmission flags
■ Two receiver wake-up modes:
– Address bit (MSB)
– Idle line
■ Muting function for multiprocessor configura tions
– Transmit data register empty
– Transmission complete
– Receive data register full
– Idle line received
– Overrun error detected
■ Parity control:
– Transmits parity bit
– Checks parity of received data byte
■ Reduced power consumption mode
10.6.3 General Description
The interface is externally connected to another
device by two pins (see Figure 61):
– TDO: Transmit Data Output. When the transmit-
ter and the receiver are disabled, the output pin
returns to its I/O port configuration. When the
transmitter and/or the receiver are enabled and
nothing is to be transmitted, the TDO pin is at
high level.
– RDI: Receive Data Input is the serial data input.
Oversampling techniques are used for data re covery by discriminating between valid incoming
data and noise.
Through these pins, serial data is transmitted and
received as frames comprising:
– An Idle Line prior to transmission or reception
– A start bit
– A data word (8 or 9 bits) least significant bit first
– A Stop bit indicating that the frame is complete.
This interface uses two types of baud rate generator:
– A conventional type for commonly-used baud
rates,
– An extended type with a prescaler offering a very
wide range of baud rates even with non-stand ard
oscillator frequencies.
100/215
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