ST ST7260K2, ST7260K1, ST7260E2, ST7260E1 User Manual

Low speed USB 8-bit MCU family with up to 8K Flash

SO24

QFN40

(6x6)

Features

■ Memories

– 4 or 8 Kbytes program memory: high

density Flash (HDFlash), or FastROM with readout and write protection

– In-application programming (IAP) and in-

circuit programming (ICP)

– 384 bytes RAM memory (128-byte stack)

■ Clock, reset and supply management

– Run, Wait, Slow and Halt CPU modes – 12 or 24 MHz oscillator – RAM Retention mode – Optional low voltage detector (LVD)

■ USB (Universal Serial Bus) interface

– DMA for low speed applications compliant

with USB 1.5 Mbs (version 2.0) and HID specifications (version 1.0)

– Integrated 3.3 V voltage regulator and

transceivers – Supports USB DFU class specification – Suspend and Resume operations – 3 Endpoints with programmable In/Out

configuration

■ Up to 19 I/O ports

– Up to 8 high sink I/Os (10 mA at 1.3 V)

Table 1. Device summary

ST7260xx

and serial communications interface

– 2 very high sink true open drain I/Os (25

mA at 1.5 V)

– Up to 8 lines with interrupt capability

■ 2 timers

– Programmable Watchdog – 16-bit Timer with 2 Input Captures, 2

Output Compares, PWM output and clock input

■ Communications interface

– Asynchronous serial communications

interface (SCI)

■ Instruction set

– 63 basic instructions – 17 main addressing modes – 8 x 8 unsigned multiply instruction

■ Development tools

– Versatile development tools including ,

software library, hardware emulator, programming boards, HID and DFU software layer

Features ST7260K2 ST7260K1 ST7260E2 ST7260E1

Flash program memory bytes

RAM (stack) - bytes 384 (128)

Peripherals Watchdog timer, 16-bit timer, USB, SCI

Operating supply 4.0 V to 5.5 V

CPU frequency 8 MHz (with 24 MHz oscillator) or 4 MHz (with 12 MHz oscillator)

Operating temperature 0 °C to +70 °C

Packages QFN40 (6x6) SO24

February 2009 Rev 3 1/139

8 K4 K8 K4 K

www.st.com

139

Contents ST7260xx

Contents

1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

4 Register & memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5 Flash program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

5.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

5.3 Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

5.3.1 Readout protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5.4 ICC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

5.5 ICP (in-circuit programming) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

5.6 IAP (in-application programming) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

5.7 Related documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

5.7.1 Flash control/status register (FCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

6 Central processing unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

6.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

6.3 CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

6.3.1 Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

6.3.2 Index registers (X and Y) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

6.3.3 Program counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

6.3.4 Condition code register (CC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

6.3.5 Stack pointer register (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

7 Reset and clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

7.1 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

7.2 Low voltage detector (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

7.2.1 Watchdog reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

7.2.2 External reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

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7.3 Clock system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

7.3.1 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

7.3.2 External clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

8 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

8.0.1 Interrupt register (ITRFRE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

9 Power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

9.2 Halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

9.3 Slow mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

9.4 Wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

10 I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

10.2 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

10.2.1 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

10.2.2 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

10.2.3 Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

10.2.4 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

10.2.5 Data register (PxDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

10.2.6 Data direction register (PxDDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

10.2.7 Related documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

11 Miscellaneous register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

12 Watchdog timer (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

12.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

12.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

12.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

12.3.1 Software watchdog option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

12.3.2 Hardware watchdog option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

12.3.3 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

12.3.4 Using Halt mode with the WDG (option) . . . . . . . . . . . . . . . . . . . . . . . . 46

12.3.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

12.3.6 Control register (WDGCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

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12.4 16-bit timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

12.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

12.4.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

12.4.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

12.4.4 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

12.4.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

12.4.6 Summary of timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

12.4.7 16-bit timer registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

13 Serial communications interface (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . 71

13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

13.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

13.2.1 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

13.2.2 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

13.2.3 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

13.2.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

13.3 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

13.3.1 Status register (SCISR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

13.3.2 Control register 1 (SCICR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

13.3.3 Control register 2 (SCICR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

13.3.4 Data register (SCIDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

13.3.5 Baud rate register (SCIBRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

14 USB interface (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

14.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

14.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

14.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

14.4 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

14.4.1 DMA address register (DMAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

14.4.2 Interrupt/DMA register (IDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

14.4.3 PID register (PIDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

14.4.4 Interrupt status register (ISTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

14.4.5 Interrupt mask register (IMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

14.4.6 Control register (CTLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

14.4.7 Device address register (DADDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

14.4.8 Endpoint n register A (EPnRA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

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14.4.9 Endpoint n register B (EPnRB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

14.4.10 Endpoint 0 register B (EP0RB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

14.5 Programming considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

14.5.1 Initializing the registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

14.5.2 Initializing DMA buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

14.5.3 Endpoint initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

14.5.4 Interrupt handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

15 Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

15.1 ST7 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

15.1.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

15.1.2 Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

15.1.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

15.1.4 Indexed (no offset, short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

15.1.5 Indirect (short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

15.1.6 Indirect indexed (short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

15.1.7 Relative mode (direct, indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

15.2 Instruction groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

16 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

16.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

16.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

16.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

16.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

16.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

16.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

16.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

16.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

16.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

16.3.2 Operating conditions with low voltage detector (LVD) . . . . . . . . . . . . . 113

16.4 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

16.5 Clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

16.5.1 General timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

16.5.2 Control timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

16.5.3 External clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

16.6 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

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16.6.1 RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

16.6.2 Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

16.7 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

16.7.1 Functional EMS (electromagnetic susceptibility) . . . . . . . . . . . . . . . . . 118

16.7.2 Designing hardened software to avoid noise problems . . . . . . . . . . . . 118

16.7.3 Electro magnetic interference (EMI) . . . . . . . . . . . . . . . . . . . . . . . . . . 119

16.7.4 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 119

16.7.5 Electrostatic discharge (ESD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

16.8 I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

16.8.1 General characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

16.8.2 Output driving current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

16.9 Control pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

16.9.1 Asynchronous RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

16.9.2 USB - universal bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

16.9.3 SCI - serial communications interface . . . . . . . . . . . . . . . . . . . . . . . . . 128

17 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

17.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

17.1.1 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

18 Device configuration and ordering information . . . . . . . . . . . . . . . . . 131

18.1 Option byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

18.2 Device ordering information and transfer of customer code . . . . . . . . . . 132

18.3 Development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

19 Known limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

19.1 PA2 limitation with OCMP1 enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

19.2 Unexpected reset fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

19.3 SCI wrong break duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

20 Device marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

21 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

6/139

ST7260xx Description

1 Description

The ST7260xx devices are members of the ST7 microcontroller family designed for USB applications running from 4.0 to 5.5 V. Different package options offer up to 19 I/O pins.

All devices are based on a common industry-standard 8-bit core, featuring an enhanced instruction set and are available with Flash program memory. The ST7 family architecture offers both power and flexibility to software developers, enabling the design of highly efficient and compact application code.

The on-chip peripherals include a low speed USB interface and an asynchronous SCI interface. For power economy, the microcontroller can switch dynamically into, Slow, Wait, Active Halt or Halt mode when the application is in idle or stand-by state.

Typical applications include consumer, home, office and industrial products.

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Block diagram ST7260xx

8-BIT CORE

ALU

ADDRESS AND DATA BUS

OSCIN

OSCOUT

RESET

PORT B

16-bit TIMER

PORT A

PORT C

PB[7:0]

(8 bits)

PC[2:0]

(3 bits)

OSCILLATOR

INTERNAL CLOCK

CONTROL

RAM

(384 bytes)

PA[7:0]

(8 bits)

POWER SUPPLY

SCI

PROGRAM

(8 Kbytes)

MEMORY

(UART)

USB SIE

OSC/3

LVD

WATCHDOG

SSA

DDA

VPP/TEST

USB DMA

USBDP USBDM USBVCC

OSC/4 or OSC/2

for USB

12 or 24 MHz OSCIN frequency required to generate 6 MHz USB clock.

2 Block diagram

Figure 1. General block diagram

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ST7260xx Pin description

11 12 15 16 17 18 19 20

3132333437383940

3536

13 14

DDA

OSCOUT

OSCIN

VSS

USBOE/PC2

SSA

USBDP

USBDM

USBV

IT8/PB7

(10 mA)

IT7/PB6(10 mA)

TDO/PC1

RDI/PC0

RESET

IT6/PB5

(10 mA)

/TEST

PA7/OCMP2/IT4

PB0

(10 mA)

PB1(10 mA)

PB2(10 mA)

PB3(10 mA)

PB4(10 mA)/IT5

PA3/EXTCLK

PA4/ICAP1/IT1

PA5/ICAP2/IT2

PA6/OCMP1/IT3

NCNCNCNCNCNCPA2

(25 mA)/ICCCLK

PA1

(25 mA)/ICCDATA

PA0/MCO

Note: NC=Do not connect

PA2(25 mA)/ICCCLK

PA1

(25 mA)/ICCDATA

PA0/MCO

SSA

PA7/OCMP2/IT4

PA5/ICAP2/IT2

PA4/ICAP1/IT1

RDI/PC0

TDO/PC1

PA3/EXTCLK

IT7/PB6

(10mA)

VPP/TEST

PB3

(10 mA)

PB2(10 mA)

USBDP

RESET

OSCOUT

USBOE/PB1

(10 mA)

PB0(10 mA)

OSCIN

USBDM

USBVcc

3 Pin description

Figure 2. 40-lead QFN package pinout

Figure 3. 24-pin SO package pinout

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Pin description ST7260xx

RESET (see Note 1): Bidirectional. This active low signal forces the initialization of the MCU.

This event is the top priority non maskable interrupt. This pin is switched low when the Watchdog is triggered or the V

is low. It can be used to reset external peripherals.

OSCIN/OSCOUT: Input/Output Oscillator pin. These pins connect a parallel-resonant crystal, or an external source, to the on-chip oscillator.

DD/VSS

DDA/VSSA

(see Note 2): Main power supply and ground voltages.

(see Note 2): Power supply and ground voltages for analog peripherals.

Alternate functions: Several pins of the I/O ports assume software programmable alternate functions as shown in the pin description.

Note: 1 Note 1: Adding two 100 nF decoupling capacitors on the Reset pin (respectively connected

to VDD and VSS) will significantly improve product electromagnetic susceptibility performance.

2 To enhance the reliability of operation, it is recommended that V

together on the application board. This also applies to V

and VSS.

SSA

and VDD be connected

DDA

3 The USBOE alternate function is mapped on Port C2 in QFN40 devices. In SO24 devices it

is mapped on Port B1.

4 The timer OCMP1 alternate function is mapped on Port A6 in QFN40 pin devices. In SO24

devices it is not available.

Legend / abbreviations for Figure 2, Figure 3 and Ta bl e 2 , Tab l e 3 :

Type: I = input, O = output, S = supply

In/Output level: CT = CMOS 0.3 V

/ 0.7 VDD with input trigger

Output level: 10 mA = 10 mA high sink (Fn N-buffer only)

25 mA = 25 mA very high sink (on N-buffer only)

Port and control configuration:

● Input: float = floating, wpu = weak pull-up, int = interrupt

● Output: OD = open drain, PP = push-pull, T = True open drain

The RESET configuration of each pin is shown in bold. This configuration is kept as long as the device is under reset state.

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ST7260xx Pin description

Table 2. Device pin description (QFN40)

Pin n° Pin name

)

Level Port / control

Type

Input

Output

float

Input Output

int

wpu

function

Main

(after

reset)

Alternate function

1 PA0/MCO I/O CT X X Port A0 Main Clock Output

SSA

S Analog ground

3 USBDP I/O USB bidirectional data (data +)

4 USBDM I/O USB bidirectional data (data -)

5 USBVCC O USB power supply

DDA

S Analog supply voltage

S Power supply voltage (4V - 5.5V)

8 OSCOUT O Oscillator output

9 OSCIN I Oscillator input

10 V

S Digital ground

11 PC2/USBOE I/O CT X X Port C2 USB Output Enable

12 PC1/TDO I/O CT X X Port C1

13 PC0/RDI I/O CT X X Port C0

SCI Transmit Data Output

SCI Receive Data Input

14 RESET I/O X X Reset

15 NC -- Not connected

16 NC -- Not connected

17 PB7/IT8 I/O CT 10 mA X X X Port B7

18 PB6/IT7 I/O CT 10 mA X X X Port B6

19 V

/TEST S Programming supply

20 PB5/IT6 I/O CT 10 mA X X X Port B5

21 PB4/IT5 I/O CT 10 mA X X X Port B4

22 PB3 I/O CT 10 mA X X Port B3

23 PB2 I/O CT 10 mA X X Port B2

24 PB1 I/O CT 10 mA X X Port B1

25 PB0 I/O CT 10 mA X X Port B0

26 PA7/OCMP2/IT4 I/O CT X X X Port A7

27 PA6/OCMP1/IT3 I/O CT X X X Port A6

Timer Output Compare 2

Timer Output Compare 1

28 PA5/ICAP2/IT2 I/O CT X X X Port A5 Timer Input Capture 2

29 PA4/ICAP1/IT1 I/O CT X X X Port A4 Timer Input Capture 1

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Pin description ST7260xx

Table 2. Device pin description (QFN40) (continued)

Level Port / control

Pin n° Pin name

30 PA3/EXTCLK I/O CT X X Port A3 Timer External Clock

31 PA2/ICCCLK I/O C

32 NC -- Do not connect

33 NC -- Do not connect

34 NC -- Do not connect

35 NC -- Do not connect

36 NC -- Do not connect

37 NC -- Do not connect

38 NC -- Do not connect

39 NC -- Do not connect

40 PA1/ICCDATA I/O CT 25 mA X T Port A1 ICC Data

Type

Input

Output

25 mA X T Port A2 ICC Clock

Input Output

int

float

wpu

function

Main

(after

reset)

Alternate function

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ST7260xx Pin description

Level Port / control

Input Output

Type

Input

Output

float

wpu

int

Main

function

(after

reset)

Power supply voltage (4 V - 5.5 V)

Table 3. Device pin description (SO24)

Pin n° Pin name

2 OSCOUT O Oscillator output

3 OSCIN I Oscillator input

S Digital ground

5 PC1/TDO I/O CT X X Port C1

6 PC0/RDI I/O CT X X Port C0

7 RESET I/O X X Reset

8 PB6/IT7 I/O CT 10 mA X X X Port B6

/TEST S Programming supply

Alternate function

SCI Transmit Data Output

SCI Receive Data Input

10 PB3 I/O CT 10 mA X X Port B3

11 PB2 I/O CT 10 mA X X Port B2

12 PB1/USBOE I/O CT 10 mA X X Port B1 USB Output Enable

13 PB0 I/O CT 10 mA X X Port B0

14 PA7/OCMP2/IT4 I/O CT X X X Port A7

15 PA5/ICAP2/IT2 I/O CT X X X Port A5

16 PA4/ICAP1/IT1 I/O CT X X X Port A4

Timer Output Compare 2

Timer Input Capture 2

Timer Input Capture 1

17 PA3/EXTCLK I/O CT X X Port A3 Timer External Clock

18 PA2/ICCCLK I/O C

25 mA X T Port A2 ICC Clock

19 PA1/ICCDATA I/O CT 25 mA X T Port A1 ICC Data

20 PA0/MCO I/O CT X X Port A0 Main Clock Output

21 V

SSA

S Analog ground

22 USBDP I/O USB bidirectional data (data +)

23 USBDM I/O USB bidirectional data (data -)

24 USBVCC O USB power supply

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0000h

RAM

Program memory

(4 / 8 KBytes)

Interrupt & reset vectors

HW registers

0040h

003Fh

FFDFh

FFE0h

FFFFh

Reserved

Stack

(128 Bytes)

0100h

017Fh

01C0h

00FFh

0040h

0180h

01BFh

Short addressing RAM (192 bytes)

16-bit addressing

RAM

8000h

7FFFh

(384 Bytes)

FFDFh

F000h

E000h

8 KBytes

4 KBytes

01BFh

(See Table 5)

(See Table 4)

4 Register & memory map

As shown in Figure 4, the MCU is capable of addressing 8 Kbytes of memories and I/O registers.

The available memory locations consist of up to 384 bytes of RAM including 64 bytes of register locations, and up to 8 Kbytes of user program memory in which the upper 32 bytes are reserved for interrupt vectors. The RAM space includes up to 128 bytes for the stack from 0100h to 017Fh.

The highest address bytes contain the user reset and interrupt vectors.

Note: Important: memory locations noted “Reserved” must never be accessed. Accessing a

reserved area can have unpredictable effects on the device.

Figure 4. Memory map

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ST7260xx Register & memory map

Table 4. Interrupt vector map

Vector address Description Masked by Remarks

FFE0h-FFEDh FFEEh-FFEFh

FFF0h-FFF1h FFF2h-FFF3h FFF4h-FFF5h FFF6h-FFF7h

FFF8h-FFF9h FFFAh-FFFBh FFFCh-FFFDh FFFEh-FFFFh

Table 5. Hardware register memory map

Address Block Register label Register name

0000h 0001h

0002h 0003h

0004h 0005h

Reserved area

USB interrupt vector

SCI interrupt vector

Reserved area

TIMER interrupt vector

IT1 to IT8 interrupt vector USB end suspend mode interrupt vector Flash start programming interrupt vector

TRAP (software) interrupt vector

RESET vector

Por t A

Por t B

Por t C

PA DR

PA DD R

PBDR

PBDDR

PCDR

PCDDR

I- bit I- bit

I- bit I- bit I- bit

I- bit None None

Port A Data Register

Port A Data Direction Register

Port B Data Register

Port B Data Direction Register

Port C Data Register

Port C Data Direction Register

Exit from Halt

Internal interrupt Internal interrupt

Internal interrupt

External interrupt

External interrupts

Internal interrupt

CPU interrupt

Reset

status

00h 00h

1111 x000b 1111 x000b

0006h

Reserved (2 bytes)

0007h

0008h ITC ITIFRE Interrupt Register 00h R/W

mode

No No

No Ye s Ye s Ye s

No Ye s

Remarks

R/W

0009h MISC MISCR Miscellaneous Register 00h R/W

000Ah

Reserved (2 bytes)

000Bh

000Ch WDG WDGCR Watchdog Control Register 7Fh R/W

000Dh to

0010h

Reserved (4 bytes)

15/139

Table 5. Hardware register memory map (continued)

Address Block Register label Register name

0011h 0012h 0013h 0014h 0015h 0016h 0017h 0018h

0019h 001Ah 001Bh 001Ch 001Dh 001Eh 001Fh

0020h

0021h

0022h

0023h

0024h

TIM

SCI

TCR2 TCR1

TCSR

TIC1HR

TIC1LR

TOC1HR

TOC1LR

TCHR

TCLR

TACHR

TAC LR

TIC2HR

TIC2LR

TOC2HR

TOC2LR

SCISR SCIDR

SCIBRR

SCICR1 SCICR2

Timer Control Register 2 Timer Control Register 1

Timer Control/Status Register

Timer Input Capture High Register 1

Timer Input Capture Low Register 1

Timer Output Compare High Register 1

Timer Output Compare Low Register 1

Timer Counter High Register

Timer Counter Low Register

Timer Alternate Counter High Register

Timer Alternate Counter Low Register

Timer Input Capture High Register 2

Timer Input Capture Low Register 2

Timer Output Compare High Register 2

Timer Output Compare Low Register 2

SCI Status Register

SCI Data Register

SCI Baud Rate Register

SCI Control Register 1 SCI Control Register 2

Reset

status

00h 00h 00h xxh xxh 80h 00h

FFh FCh FFh FCh

xxh

80h

00h

C0h

xxh

00h

x000 0000b

00h

Remarks

R/W R/W

R/W Read only Read only

R/W

R/W Read only

R/W Read only Read only

R/W

Read only

R/W

0025h 0026h 0027h 0028h

0029h 002Ah 002Bh 002Ch 002Dh 002Eh 002Fh

0030h

0031h

0032h

0036h

0037h Flash FCSR Flash Control /Status Register 00h R/W

0038h

003Fh

USB

USBPIDR

USBDMAR

USBIDR

USBISTR

USBIMR

USBCTLR

USBDADDR

USBEP0RA USBEP0RB USBEP1RA USBEP1RB USBEP2RA USBEP2RB

USB PID Register

USB DMA address Register

USB Interrupt/DMA Register

USB Interrupt Status Register

USB Interrupt Mask Register

USB Control Register

USB Device Address Register

USB Endpoint 0 Register A USB Endpoint 0 Register B USB Endpoint 1 Register A USB Endpoint 1 Register B USB Endpoint 2 Register A USB Endpoint 2 Register B

Reserved (5 Bytes)

Reserved (8 bytes)

x0h xxh x0h 00h 00h 06h 00h

0000 xxxxb

80h 0000 xxxxb 0000 xxxxb 0000 xxxxb 0000 xxxxb

Read only

R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

16/139

ST7260xx Flash program memory

5 Flash program memory

5.1 Introduction

The ST7 dual voltage High Density Flash (HDFlash) is a non-volatile memory that can be electrically erased as a single block or by individual sectors and programmed on a byte-bybyte basis using an external V

The HDFlash devices can be programmed and erased off-board (plugged in a programming tool) or on-board using ICP (in-circuit programming) or IAP (in-application programming).

The array matrix organization allows each sector to be erased and reprogrammed without affecting other sectors.

5.2 Main features

● 3 Flash programming modes:

– Insertion in a programming tool. In this mode, all sectors including option bytes

can be programmed or erased.

– ICP (in-circuit programming). In this mode, all sectors including option bytes can

be programmed or erased without removing the device from the application board.

– IAP (in-application programming). In this mode, all sectors, except Sector 0, can

be programmed or erased without removing the device from the application board and while the application is running.

● ICT (in-circuit testing) for downloading and executing user application test patterns in

RAM

● Readout protection

● Register Access Security System (RASS) to prevent accidental programming or

erasing

supply.

5.3 Structure

The Flash memory is organized in sectors and can be used for both code and data storage.

Depending on the overall Flash memory size in the microcontroller device, there are up to three user sectors (seeTa bl e 6 ). Each of these sectors can be erased independently to avoid unnecessary erasing of the whole Flash memory when only a partial erasing is required.

The first two sectors have a fixed size of 4 Kbytes (see Figure 5). They are mapped in the upper part of the ST7 addressing space so the reset and interrupt vectors are located in Sector 0 (F000h-FFFFh).

Table 6. Sectors available in Flash devices

Flash size (bytes) Available sectors

4K Sector 0

8K Sectors 0, 1

>8K Sectors 0, 1, 2

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Flash program memory ST7260xx

4Kbytes

Sector 1

Sector 0

Sector 2

8K 16K

32K

Flash

FFFFh

EFFFh

DFFFh

7FFFh

24 Kbytes

memory size

8Kbytes

BFFFh

5.3.1 Readout protection

Readout protection, when selected, provides a protection against program memory content extraction and against write access to Flash memory. Even if no protection can be considered as totally unbreakable, the feature provides a very high level of protection for a general purpose microcontroller.

In Flash devices, this protection is removed by reprogramming the option. In this case, the entire program memory is first automatically erased.

Readout protection is enabled and removed through the FMP_R bit in the option byte.

Figure 5. Memory map and sector address

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ST7260xx Flash program memory

ICC connector

ICCDATA

ICCCLK

RESET

HE10 connector type

Application power supply

246810

975 3

Programming tool

ICC connector

Application board

ICC cable

(See note 3)

10kΩ

ICCSEL/VPP

ST7

OSC1

OSC2

See note 1

See note 2

Application

reset source

Application

I/O

(see note 4)

Optional

5.4 ICC interface

ICC needs a minimum of 4 and up to 6 pins to be connected to the programming tool (see

Figure 6). These pins are:

– RESET –V – ICCCLK: ICC output serial clock pin – ICCDATA: ICC input/output serial data pin – ICCSEL/V – OSC1 (or OSCIN): main clock input for external source (optional) –V

Figure 6. Typical ICC interface

: device reset

: device power supply ground

: programming voltage

: application board power supply (see Figure 6, Note 3).

1. If the ICCCLK or ICCDATA pins are only used as outputs in the application, no signal isolation is necessary. As soon as the programming tool is plugged to the board, even if an ICC session is not in progress, the ICCCLK and ICCDATA pins are not available for the application. If they are used as inputs by the application, isolation such as a serial resistor has to be implemented in case another device forces the signal. Refer to the Programming Tool documentation for recommended resistor values.

2. During the ICC session, the programming tool must control the RESET between the programming tool and the application reset circuit if it drives more than 5mA at high level (PUSH-pull output or pull-up resistor <1K). A schottky diode can be used to isolate the application reset circuit in this case. When using a classical RC network with R>1K or a reset management IC with open drain output and pull-up resistor >1K, no additional components are needed. In all cases the user must ensure that no external reset is generated by the application during the ICC session.

3. The use of Pin 7 of the ICC connector depends on the programming tool architecture. This pin must be connected when using most ST programming tools (it is used to monitor the application power supply). Please refer to the programming tool manual.

4. Pin 9 has to be connected to the OSC1 (OSCIN) pin of the ST7 when the clock is not available in the application or if the selected clock option is not programmed in the option byte. ST7 devices with multioscillator capability need to have OSC2 grounded in this case.

19/139

pin. This can lead to conflicts

Flash program memory ST7260xx

5.5 ICP (in-circuit programming)

To perform ICP the microcontroller must be switched to ICC (in-circuit communication) mode by an external controller or programming tool.

Depending on the ICP code downloaded in RAM, Flash memory programming can be fully customized (number of bytes to program, program locations, or selection serial communication interface for downloading).

When using an STMicroelectronics or third-party programming tool that supports ICP and the specific microcontroller device, the user needs only to implement the ICP hardware interface on the application board (see Figure 6). For more details on the pin locations, refer to the device pinout description.

5.6 IAP (in-application programming)

This mode uses a BootLoader program previously stored in Sector 0 by the user (in ICP mode or by plugging the device in a programming tool).

This mode is fully controlled by user software. This allows it to be adapted to the user application, (such as user-defined strategy for entering programming mode, choice of communications protocol used to fetch the data to be stored). For example, it is possible to download code from the SCI, or USB interface and program it in the Flash. IAP mode can be used to program any of the Flash sectors except Sector 0, which is write/erase protected to allow recovery in case errors occur during the programming operation.

5.7 Related documentation

For details on Flash programming and ICC protocol, refer to the ST7 Flash Programming Reference Manual and to the ST7 ICC Protocol Reference Manual

5.7.1 Flash control/status register (FCSR)

This register is reserved for use by programming tool software. It controls the Flash programming and erasing operations.

FCSR Reset value:0000 0000 (00h)

76543210

00000000

R/W R/W R/W R/W R/W R/W R/W R/W

Table 7. Flash control/status register address and reset value

Address (Hex) Register label 7 6 5 4 3 2 1 0

0037hFCSR reset value00000000

20/139

ST7260xx Central processing unit (CPU)

Accumulator

X index register

Y index register

Stack pointer

Condition code register

Program counter

1C11HI NZ

Reset value = reset vector @ FFFEh-FFFFh

15 8

PCH

PCL

87 0

Reset value = stack higher address

Reset value = 1 X11X1XX

Reset value = XXh

X = undefined value

6 Central processing unit (CPU)

6.1 Introduction

This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8bit data manipulation.

6.2 Main features

● 63 basic instructions

● Fast 8-bit by 8-bit multiply

● 17 main addressing modes

● Two 8-bit index registers

● 16-bit stack pointer

● Low power modes

● Maskable hardware interrupts

● Non-maskable software interrupt

6.3 CPU registers

The six CPU registers shown in Figure 7 are not present in the memory mapping and are accessed by specific instructions.

Figure 7. CPU registers

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Central processing unit (CPU) ST7260xx

6.3.1 Accumulator (A)

The Accumulator is an 8-bit general purpose register used to hold operands and the results of the arithmetic and logic calculations and to manipulate data.

6.3.2 Index registers (X and Y)

In indexed addressing modes, these 8-bit registers are used to create effective addresses or as temporary storage areas for data manipulation. (The Cross-Assembler generates a precede instruction (PRE) to indicate that the following instruction refers to the Y register.)

The Y register is not affected by the interrupt automatic procedures (not pushed to and popped from the stack).

6.3.3 Program counter (PC)

The program counter is a 16-bit register containing the address of the next instruction to be executed by the CPU. It is made of two 8-bit registers PCL (Program Counter Low which is the LSB) and PCH (Program Counter High which is the MSB).

6.3.4 Condition code register (CC)

The 8-bit Condition Code register contains the interrupt mask and four flags representative of the result of the instruction just executed. This register can also be handled by the PUSH and POP instructions. These bits can be individually tested and/or controlled by specific instructions.

CC Reset value: 111x1xxx

76543210

111HINZC

R/W R/W R/W R/W R/W

Table 8. CC register description

BIt Name Function

Half carry

This bit is set by hardware when a carry occurs between bits 3 and 4 of the ALU during an ADD or ADC instructions. It is reset by hardware during the same

instructions. 0: No half carry has occurred. 1: A half carry has occurred. This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD arithmetic subroutines.

22/139

ST7260xx Central processing unit (CPU)

Table 8. CC register description

BIt Name Function

Interrupt mask

This bit is set by hardware when entering in interrupt or by software to disable all interrupts except the TRAP software interrupt. This bit is cleared by software.

0: Interrupts are enabled. 1: Interrupts are disabled.

This bit is controlled by the RIM, SIM and IRET instructions and is tested by the JRM and JRNM instructions. Note: Interrupts requested while I is set are latched and can be processed when I is cleared. By default an interrupt routine is not interruptible because the I bit is set by hardware at the start of the routine and reset by the IRET instruction at the end of the routine. If the I bit is cleared by software in the interrupt routine, pending interrupts are serviced regardless of the priority level of the current interrupt routine

Negative

This bit is set and cleared by hardware. It is representative of the result sign of the last arithmetic, logical or data manipulation. It is a copy of the result 7th bit. 0: The result of the last operation is positive or null. 1: The result of the last operation is negative (that is, the most significant bit is a logic

1. This bit is accessed by the JRMI and JRPL instructions.

Zero (Arithmetic Management bit)

This bit is set and cleared by hardware. This bit indicates that the result of the last arithmetic, logical or data manipulation is zero. 0: The result of the last operation is different from zero. 1: The result of the last operation is zero. This bit is accessed by the JREQ and JRNE test instructions.

Carry/borrow

This bit is set and cleared by hardware and software. It indicates an overflow or an underflow has occurred during the last arithmetic operation. 0: No overflow or underflow has occurred. 1: An overflow or underflow has occurred. This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC instructions. It is also affected by the ‘bit test and branch’, shift and rotate instructions.

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Central processing unit (CPU) ST7260xx

PCH PCL

PCH

PCL

PCH

PCH PCL

PCL

PCH

PCL

PCH

PCH PCL

Call

subroutine

Interrupt

event

Push Y Pop Y IRET

RET

or RSP

@ 01FFh

@ 0100h

Stack Higher Address = 017Fh Stack Lower Address =

0100h

6.3.5 Stack pointer register (SP)

SP Reset value: 01 7Fh

1514131211109876543210

000000010SP6SP5SP4SP3SP2SP1SP0

R/W R/W R/W R/W R/W R/W R/W

The Stack Pointer is a 16-bit register which is always pointing to the next free location in the stack. It is then decremented after data has been pushed onto the stack and incremented before data is popped from the stack (see Figure 8).

Since the stack is 128 bytes deep, the 9 most significant bits are forced by hardware. Following an MCU reset, or after a Reset Stack Pointer instruction (RSP), the Stack Pointer contains its reset value (the SP7 to SP0 bits are set) which is the stack higher address.

The least significant byte of the Stack Pointer (called S) can be directly accessed by an LD instruction.

Note: When the lower limit is exceeded, the Stack Pointer wraps around to the stack upper limit,

without indicating the stack overflow. The previously stored information is then overwritten and therefore lost. The stack also wraps in case of an underflow.

The stack is used to save the return address during a subroutine call and the CPU context during an interrupt. The user may also directly manipulate the stack by means of the PUSH and POP instructions. In the case of an interrupt, the PCL is stored at the first location pointed to by the SP. Then the other registers are stored in the next locations as shown in

Figure 8.

● When an interrupt is received, the SP is decremented and the context is pushed on the

stack.

● On return from interrupt, the SP is incremented and the context is popped from the

stack.

A subroutine call occupies two locations and an interrupt five locations in the stack area.

Figure 8. Stack manipulation example

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ST7260xx Reset and clock management

7 Reset and clock management

7.1 Reset

The Reset procedure is used to provide an orderly software start-up or to exit low power modes.

Three reset modes are provided: a low voltage (LVD) reset, a watchdog reset and an external reset at the RESET

A reset causes the reset vector to be fetched from addresses FFFEh and FFFFh in order to be loaded into the PC and with program execution starting from this point.

An internal circuitry provides a 4096 CPU clock cycle delay from the time that the oscillator becomes active.

Caution: When the ST7 is unprogrammed or fully erased, the Flash is blank and the RESET vector is

not programmed. For this reason, it is recommended to keep the RESET until programming mode is entered, in order to avoid unwanted behavior

7.2 Low voltage detector (LVD)

pin.

pin in low state

Low voltage reset circuitry generates a reset when VDD is:

● below V

During low voltage reset, the RESET devices.

It is recommended to make sure that the V device is exiting from Reset, to ensure the application functions properly.

when VDD is rising,

IT+

when VDD is falling.

IT-

7.2.1 Watchdog reset

When a watchdog reset occurs, the RESET pin is pulled low permitting the MCU to reset other devices in the same way as the low voltage reset (Figure 9).

7.2.2 External reset

The external reset is an active low input signal applied to the RESET pin of the MCU. As shown in Figure 12, the RESET CPU clock cycles.

An internal Schmitt trigger at the RESET

pin is held low, thus permitting the MCU to reset other

supply voltage rises monotonously when the

signal must stay low for a minimum of one and a half

pin is provided to improve noise immunity.

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Reset and clock management ST7260xx

LOW VOLTAGE

FROM

WATCHDOG

RESET

INTERNAL

DETECTOR

RESET

IT+

IT-

Addresses

$FFFE

Temporization (4096 CPU clock cycles)

IT+

Figure 9. Low voltage detector functional diagram

Figure 10. Low voltage reset signal output

Note: Hysteresis (V

IT+-VIT-

) = V

hys

Figure 11. Temporization timing diagram after an internal reset

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ST7260xx Reset and clock management

OSCIN

CPU

FFFF

FFFE

RESET

WATCHDOG RESET

DDR

OXOV

4096 CPU

CLOCK

CYCLES

DELAY

Figure 12. Reset timing diagram

Note: Refer to Electrical Characteristics for values of t

DDR

, t

OXOV

, V

IT+

, V

IT-

and V

hys

7.3 Clock system

7.3.1 General description

The MCU accepts either a crystal or ceramic resonator, or an external clock signal to drive the internal oscillator. The internal clock (f frequency (f

), which is divided by 3 (and by 2 or 4 for USB, depending on the external

OSC

clock used). The internal clock is further divided by 2 by setting the SMS bit in the Miscellaneous Register. Using the OSC24/12 bit in the option byte, a 12 MHz or a 24 MHz external clock can be used to provide an internal frequency of either 2, 4 or 8 MHz while maintaining a 6 MHz for the USB (refer to Figure 15).

The internal clock signal (f

) is also routed to the on-chip peripherals. The CPU clock

CPU

signal consists of a square wave with a duty cycle of 50%.

The internal oscillator is designed to operate with an AT-cut parallel resonant quartz or ceramic resonator in the frequency range specified for f recommended when using a crystal, and Ta bl e 9 lists the recommended capacitance. The crystal and associated components should be mounted as close as possible to the input pins in order to minimize output distortion and start-up stabilisation time.

) is derived from the external oscillator

CPU

. The circuit shown in Figure 14 is

osc

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Reset and clock management ST7260xx

OSCIN

OSCOUT

EXTERNAL

CLOCK

OSCIN

OSCOUT

OSCIN

OSCOUT

Table 9. Recommended values for 24 MHz crystal resonator

Symbol Values

(1)

1. R

SMAX

OSCIN

OSCOUT

is the equivalent serial resistor of the crystal (see crystal specification).

SMAX

20 Ω 25 Ω 70 Ω

56pF 47pF 22pF

1-10 MΩ 1-10 MΩ 1-10 MΩ

7.3.2 External clock

An external clock may be applied to the OSCIN input with the OSCOUT pin not connected, as shown on Figure 13. The t input. The equivalent specification of the external clock source should be used instead of t

(see Section 16.5: Clock and timing characteristics).

OXOV

Figure 13. External clock source connections

specifications do not apply when using an external clock

OXOV

Figure 14. Crystal/ceramic resonator

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ST7260xx Reset and clock management

CPU and

8, 4 or 2 MHz

6 MHz (USB)

24 or

peripherals)

12 MHz

Crystal

OSC24/12

SMS

Figure 15. Clock block diagram

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Interrupts ST7260xx

8 Interrupts

The ST7 core may be interrupted by one of two different methods: maskable hardware interrupts as listed in Table 10: Interrupt mapping and a non-maskable software interrupt (TRAP). The Interrupt processing flowchart is shown in Figure 16.

The maskable interrupts must be enabled clearing the I bit in order to be serviced. However, disabled interrupts may be latched and processed when they are enabled (see external interrupts subsection).

When an interrupt has to be serviced:

● Normal processing is suspended at the end of the current instruction execution.

● The PC, X, A and CC registers are saved onto the stack.

● The I bit of the CC register is set to prevent additional interrupts.

The PC is then loaded with the interrupt vector of the interrupt to service and the first instruction of the interrupt service routine is fetched (refer to Table 10: Interrupt mapping for vector addresses).

The interrupt service routine should finish with the IRET instruction which causes the contents of the saved registers to be recovered from the stack.

Note: As a consequence of the IRET instruction, the I bit will be cleared and the main program will

resume.

Priority management

By default, a servicing interrupt cannot be interrupted because the I bit is set by hardware entering in interrupt routine.

In the case several interrupts are simultaneously pending, a hardware priority defines which one will be serviced first (see Table 10: Interrupt mapping).

Non-maskable software interrupts

This interrupt is entered when the TRAP instruction is executed regardless of the state of the I bit. It will be serviced according to the flowchart on Figure 16.

Interrupts and low power mode

All interrupts allow the processor to leave the Wait low power mode. Only external and specific mentioned interrupts allow the processor to leave the Halt low power mode (refer to the “Exit from HALT“ column in Table 10: Interrupt mapping).

External interrupts

The pins ITi/PAk and ITj/PBk (i=1,2; j= 5,6; k=4,5) can generate an interrupt when a rising edge occurs on this pin. Conversely, the ITl/PAn and ITm/PBn pins (l=3,4; m= 7,8; n=6,7) can generate an interrupt when a falling edge occurs on this pin.

Interrupt generation will occur if it is enabled with the ITiE bit (i=1 to 8) in the ITRFRE register and if the I bit of the CCR is reset.

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