Datasheet ST7260K2, ST7260K1, ST7260E2, ST7260E1 Datasheet (ST)

Download

Low speed USB 8-bit MCU family with up to 8K Flash

SO24

QFN40

(6x6)

Features

■ Memories

– 4 or 8 Kbytes program memory: high

density Flash (HDFlash), or FastROM with readout and write protection

– In-application programming (IAP) and in-

circuit programming (ICP)

– 384 bytes RAM memory (128-byte stack)

■ Clock, reset and supply management

– Run, Wait, Slow and Halt CPU modes – 12 or 24 MHz oscillator – RAM Retention mode – Optional low voltage detector (LVD)

■ USB (Universal Serial Bus) interface

– DMA for low speed applications compliant

with USB 1.5 Mbs (version 2.0) and HID specifications (version 1.0)

– Integrated 3.3 V voltage regulator and

transceivers – Supports USB DFU class specification – Suspend and Resume operations – 3 Endpoints with programmable In/Out

configuration

■ Up to 19 I/O ports

– Up to 8 high sink I/Os (10 mA at 1.3 V)

Table 1. Device summary

ST7260xx

and serial communications interface

– 2 very high sink true open drain I/Os (25

mA at 1.5 V)

– Up to 8 lines with interrupt capability

■ 2 timers

– Programmable Watchdog – 16-bit Timer with 2 Input Captures, 2

Output Compares, PWM output and clock input

■ Communications interface

– Asynchronous serial communications

interface (SCI)

■ Instruction set

– 63 basic instructions – 17 main addressing modes – 8 x 8 unsigned multiply instruction

■ Development tools

– Versatile development tools including ,

software library, hardware emulator, programming boards, HID and DFU software layer

Features ST7260K2 ST7260K1 ST7260E2 ST7260E1

Flash program memory bytes

RAM (stack) - bytes 384 (128)

Peripherals Watchdog timer, 16-bit timer, USB, SCI

Operating supply 4.0 V to 5.5 V

CPU frequency 8 MHz (with 24 MHz oscillator) or 4 MHz (with 12 MHz oscillator)

Operating temperature 0 °C to +70 °C

Packages QFN40 (6x6) SO24

February 2009 Rev 3 1/139

8 K4 K8 K4 K

www.st.com

139

Contents ST7260xx

Contents

1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

4 Register & memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5 Flash program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

5.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

5.3 Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

5.3.1 Readout protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5.4 ICC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

5.5 ICP (in-circuit programming) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

5.6 IAP (in-application programming) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

5.7 Related documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

5.7.1 Flash control/status register (FCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

6 Central processing unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

6.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

6.3 CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

6.3.1 Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

6.3.2 Index registers (X and Y) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

6.3.3 Program counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

6.3.4 Condition code register (CC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

6.3.5 Stack pointer register (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

7 Reset and clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

7.1 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

7.2 Low voltage detector (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

7.2.1 Watchdog reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

7.2.2 External reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

2/139

ST7260xx Contents

7.3 Clock system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

7.3.1 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

7.3.2 External clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

8 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

8.0.1 Interrupt register (ITRFRE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

9 Power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

9.2 Halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

9.3 Slow mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

9.4 Wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

10 I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

10.2 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

10.2.1 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

10.2.2 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

10.2.3 Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

10.2.4 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

10.2.5 Data register (PxDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

10.2.6 Data direction register (PxDDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

10.2.7 Related documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

11 Miscellaneous register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

12 Watchdog timer (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

12.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

12.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

12.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

12.3.1 Software watchdog option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

12.3.2 Hardware watchdog option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

12.3.3 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

12.3.4 Using Halt mode with the WDG (option) . . . . . . . . . . . . . . . . . . . . . . . . 46

12.3.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

12.3.6 Control register (WDGCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

3/139

Contents ST7260xx

12.4 16-bit timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

12.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

12.4.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

12.4.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

12.4.4 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

12.4.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

12.4.6 Summary of timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

12.4.7 16-bit timer registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

13 Serial communications interface (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . 71

13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

13.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

13.2.1 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

13.2.2 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

13.2.3 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

13.2.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

13.3 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

13.3.1 Status register (SCISR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

13.3.2 Control register 1 (SCICR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

13.3.3 Control register 2 (SCICR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

13.3.4 Data register (SCIDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

13.3.5 Baud rate register (SCIBRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

14 USB interface (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

14.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

14.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

14.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

14.4 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

14.4.1 DMA address register (DMAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

14.4.2 Interrupt/DMA register (IDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

14.4.3 PID register (PIDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

14.4.4 Interrupt status register (ISTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

14.4.5 Interrupt mask register (IMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

14.4.6 Control register (CTLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

14.4.7 Device address register (DADDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

14.4.8 Endpoint n register A (EPnRA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

4/139

ST7260xx Contents

14.4.9 Endpoint n register B (EPnRB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

14.4.10 Endpoint 0 register B (EP0RB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

14.5 Programming considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

14.5.1 Initializing the registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

14.5.2 Initializing DMA buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

14.5.3 Endpoint initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

14.5.4 Interrupt handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

15 Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

15.1 ST7 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

15.1.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

15.1.2 Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

15.1.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

15.1.4 Indexed (no offset, short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

15.1.5 Indirect (short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

15.1.6 Indirect indexed (short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

15.1.7 Relative mode (direct, indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

15.2 Instruction groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

16 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

16.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

16.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

16.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

16.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

16.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

16.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

16.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

16.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

16.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

16.3.2 Operating conditions with low voltage detector (LVD) . . . . . . . . . . . . . 113

16.4 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

16.5 Clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

16.5.1 General timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

16.5.2 Control timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

16.5.3 External clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

16.6 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

5/139

Contents ST7260xx

16.6.1 RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

16.6.2 Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

16.7 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

16.7.1 Functional EMS (electromagnetic susceptibility) . . . . . . . . . . . . . . . . . 118

16.7.2 Designing hardened software to avoid noise problems . . . . . . . . . . . . 118

16.7.3 Electro magnetic interference (EMI) . . . . . . . . . . . . . . . . . . . . . . . . . . 119

16.7.4 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 119

16.7.5 Electrostatic discharge (ESD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

16.8 I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

16.8.1 General characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

16.8.2 Output driving current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

16.9 Control pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

16.9.1 Asynchronous RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

16.9.2 USB - universal bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

16.9.3 SCI - serial communications interface . . . . . . . . . . . . . . . . . . . . . . . . . 128

17 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

17.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

17.1.1 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

18 Device configuration and ordering information . . . . . . . . . . . . . . . . . 131

18.1 Option byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

18.2 Device ordering information and transfer of customer code . . . . . . . . . . 132

18.3 Development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

19 Known limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

19.1 PA2 limitation with OCMP1 enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

19.2 Unexpected reset fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

19.3 SCI wrong break duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

20 Device marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

21 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

6/139

ST7260xx Description

1 Description

The ST7260xx devices are members of the ST7 microcontroller family designed for USB applications running from 4.0 to 5.5 V. Different package options offer up to 19 I/O pins.

All devices are based on a common industry-standard 8-bit core, featuring an enhanced instruction set and are available with Flash program memory. The ST7 family architecture offers both power and flexibility to software developers, enabling the design of highly efficient and compact application code.

The on-chip peripherals include a low speed USB interface and an asynchronous SCI interface. For power economy, the microcontroller can switch dynamically into, Slow, Wait, Active Halt or Halt mode when the application is in idle or stand-by state.

Typical applications include consumer, home, office and industrial products.

7/139

Block diagram ST7260xx

8-BIT CORE

ALU

ADDRESS AND DATA BUS

OSCIN

OSCOUT

RESET

PORT B

16-bit TIMER

PORT A

PORT C

PB[7:0]

(8 bits)

PC[2:0]

(3 bits)

OSCILLATOR

INTERNAL CLOCK

CONTROL

RAM

(384 bytes)

PA[7:0]

(8 bits)

POWER SUPPLY

SCI

PROGRAM

(8 Kbytes)

MEMORY

(UART)

USB SIE

OSC/3

LVD

WATCHDOG

SSA

DDA

VPP/TEST

USB DMA

USBDP USBDM USBVCC

OSC/4 or OSC/2

for USB

12 or 24 MHz OSCIN frequency required to generate 6 MHz USB clock.

2 Block diagram

Figure 1. General block diagram

8/139

ST7260xx Pin description

11 12 15 16 17 18 19 20

3132333437383940

3536

13 14

DDA

OSCOUT

OSCIN

VSS

USBOE/PC2

SSA

USBDP

USBDM

USBV

IT8/PB7

(10 mA)

IT7/PB6(10 mA)

TDO/PC1

RDI/PC0

RESET

IT6/PB5

(10 mA)

/TEST

PA7/OCMP2/IT4

PB0

(10 mA)

PB1(10 mA)

PB2(10 mA)

PB3(10 mA)

PB4(10 mA)/IT5

PA3/EXTCLK

PA4/ICAP1/IT1

PA5/ICAP2/IT2

PA6/OCMP1/IT3

NCNCNCNCNCNCPA2

(25 mA)/ICCCLK

PA1

(25 mA)/ICCDATA

PA0/MCO

Note: NC=Do not connect

PA2(25 mA)/ICCCLK

PA1

(25 mA)/ICCDATA

PA0/MCO

SSA

PA7/OCMP2/IT4

PA5/ICAP2/IT2

PA4/ICAP1/IT1

RDI/PC0

TDO/PC1

PA3/EXTCLK

IT7/PB6

(10mA)

VPP/TEST

PB3

(10 mA)

PB2(10 mA)

USBDP

RESET

OSCOUT

USBOE/PB1

(10 mA)

PB0(10 mA)

OSCIN

USBDM

USBVcc

3 Pin description

Figure 2. 40-lead QFN package pinout

Figure 3. 24-pin SO package pinout

9/139

Pin description ST7260xx

RESET (see Note 1): Bidirectional. This active low signal forces the initialization of the MCU.

This event is the top priority non maskable interrupt. This pin is switched low when the Watchdog is triggered or the V

is low. It can be used to reset external peripherals.

OSCIN/OSCOUT: Input/Output Oscillator pin. These pins connect a parallel-resonant crystal, or an external source, to the on-chip oscillator.

DD/VSS

DDA/VSSA

(see Note 2): Main power supply and ground voltages.

(see Note 2): Power supply and ground voltages for analog peripherals.

Alternate functions: Several pins of the I/O ports assume software programmable alternate functions as shown in the pin description.

Note: 1 Note 1: Adding two 100 nF decoupling capacitors on the Reset pin (respectively connected

to VDD and VSS) will significantly improve product electromagnetic susceptibility performance.

2 To enhance the reliability of operation, it is recommended that V

together on the application board. This also applies to V

and VSS.

SSA

and VDD be connected

DDA

3 The USBOE alternate function is mapped on Port C2 in QFN40 devices. In SO24 devices it

is mapped on Port B1.

4 The timer OCMP1 alternate function is mapped on Port A6 in QFN40 pin devices. In SO24

devices it is not available.

Legend / abbreviations for Figure 2, Figure 3 and Ta bl e 2 , Tab l e 3 :

Type: I = input, O = output, S = supply

In/Output level: CT = CMOS 0.3 V

/ 0.7 VDD with input trigger

Output level: 10 mA = 10 mA high sink (Fn N-buffer only)

25 mA = 25 mA very high sink (on N-buffer only)

Port and control configuration:

● Input: float = floating, wpu = weak pull-up, int = interrupt

● Output: OD = open drain, PP = push-pull, T = True open drain

The RESET configuration of each pin is shown in bold. This configuration is kept as long as the device is under reset state.

10/139

ST7260xx Pin description

Table 2. Device pin description (QFN40)

Pin n° Pin name

)

Level Port / control

Type

Input

Output

float

Input Output

int

wpu

function

Main

(after

reset)

Alternate function

1 PA0/MCO I/O CT X X Port A0 Main Clock Output

SSA

S Analog ground

3 USBDP I/O USB bidirectional data (data +)

4 USBDM I/O USB bidirectional data (data -)

5 USBVCC O USB power supply

DDA

S Analog supply voltage

S Power supply voltage (4V - 5.5V)

8 OSCOUT O Oscillator output

9 OSCIN I Oscillator input

10 V

S Digital ground

11 PC2/USBOE I/O CT X X Port C2 USB Output Enable

12 PC1/TDO I/O CT X X Port C1

13 PC0/RDI I/O CT X X Port C0

SCI Transmit Data Output

SCI Receive Data Input

14 RESET I/O X X Reset

15 NC -- Not connected

16 NC -- Not connected

17 PB7/IT8 I/O CT 10 mA X X X Port B7

18 PB6/IT7 I/O CT 10 mA X X X Port B6

19 V

/TEST S Programming supply

20 PB5/IT6 I/O CT 10 mA X X X Port B5

21 PB4/IT5 I/O CT 10 mA X X X Port B4

22 PB3 I/O CT 10 mA X X Port B3

23 PB2 I/O CT 10 mA X X Port B2

24 PB1 I/O CT 10 mA X X Port B1

25 PB0 I/O CT 10 mA X X Port B0

26 PA7/OCMP2/IT4 I/O CT X X X Port A7

27 PA6/OCMP1/IT3 I/O CT X X X Port A6

Timer Output Compare 2

Timer Output Compare 1

28 PA5/ICAP2/IT2 I/O CT X X X Port A5 Timer Input Capture 2

29 PA4/ICAP1/IT1 I/O CT X X X Port A4 Timer Input Capture 1

11/139

Pin description ST7260xx

Table 2. Device pin description (QFN40) (continued)

Level Port / control

Pin n° Pin name

30 PA3/EXTCLK I/O CT X X Port A3 Timer External Clock

31 PA2/ICCCLK I/O C

32 NC -- Do not connect

33 NC -- Do not connect

34 NC -- Do not connect

35 NC -- Do not connect

36 NC -- Do not connect

37 NC -- Do not connect

38 NC -- Do not connect

39 NC -- Do not connect

40 PA1/ICCDATA I/O CT 25 mA X T Port A1 ICC Data

Type

Input

Output

25 mA X T Port A2 ICC Clock

Input Output

int

float

wpu

function

Main

(after

reset)

Alternate function

12/139

ST7260xx Pin description

Level Port / control

Input Output

Type

Input

Output

float

wpu

int

Main

function

(after

reset)

Power supply voltage (4 V - 5.5 V)

Table 3. Device pin description (SO24)

Pin n° Pin name

2 OSCOUT O Oscillator output

3 OSCIN I Oscillator input

S Digital ground

5 PC1/TDO I/O CT X X Port C1

6 PC0/RDI I/O CT X X Port C0

7 RESET I/O X X Reset

8 PB6/IT7 I/O CT 10 mA X X X Port B6

/TEST S Programming supply

Alternate function

SCI Transmit Data Output

SCI Receive Data Input

10 PB3 I/O CT 10 mA X X Port B3

11 PB2 I/O CT 10 mA X X Port B2

12 PB1/USBOE I/O CT 10 mA X X Port B1 USB Output Enable

13 PB0 I/O CT 10 mA X X Port B0

14 PA7/OCMP2/IT4 I/O CT X X X Port A7

15 PA5/ICAP2/IT2 I/O CT X X X Port A5

16 PA4/ICAP1/IT1 I/O CT X X X Port A4

Timer Output Compare 2

Timer Input Capture 2

Timer Input Capture 1

17 PA3/EXTCLK I/O CT X X Port A3 Timer External Clock

18 PA2/ICCCLK I/O C

25 mA X T Port A2 ICC Clock

19 PA1/ICCDATA I/O CT 25 mA X T Port A1 ICC Data

20 PA0/MCO I/O CT X X Port A0 Main Clock Output

21 V

SSA

S Analog ground

22 USBDP I/O USB bidirectional data (data +)

23 USBDM I/O USB bidirectional data (data -)

24 USBVCC O USB power supply

13/139

0000h

RAM

Program memory

(4 / 8 KBytes)

Interrupt & reset vectors

HW registers

0040h

003Fh

FFDFh

FFE0h

FFFFh

Reserved

Stack

(128 Bytes)

0100h

017Fh

01C0h

00FFh

0040h

0180h

01BFh

Short addressing RAM (192 bytes)

16-bit addressing

RAM

8000h

7FFFh

(384 Bytes)

FFDFh

F000h

E000h

8 KBytes

4 KBytes

01BFh

(See Table 5)

(See Table 4)

4 Register & memory map

As shown in Figure 4, the MCU is capable of addressing 8 Kbytes of memories and I/O registers.

The available memory locations consist of up to 384 bytes of RAM including 64 bytes of register locations, and up to 8 Kbytes of user program memory in which the upper 32 bytes are reserved for interrupt vectors. The RAM space includes up to 128 bytes for the stack from 0100h to 017Fh.

The highest address bytes contain the user reset and interrupt vectors.

Note: Important: memory locations noted “Reserved” must never be accessed. Accessing a

reserved area can have unpredictable effects on the device.

Figure 4. Memory map

14/139

ST7260xx Register & memory map

Table 4. Interrupt vector map

Vector address Description Masked by Remarks

FFE0h-FFEDh FFEEh-FFEFh

FFF0h-FFF1h FFF2h-FFF3h FFF4h-FFF5h FFF6h-FFF7h

FFF8h-FFF9h FFFAh-FFFBh FFFCh-FFFDh FFFEh-FFFFh

Table 5. Hardware register memory map

Address Block Register label Register name

0000h 0001h

0002h 0003h

0004h 0005h

Reserved area

USB interrupt vector

SCI interrupt vector

Reserved area

TIMER interrupt vector

IT1 to IT8 interrupt vector USB end suspend mode interrupt vector Flash start programming interrupt vector

TRAP (software) interrupt vector

RESET vector

Por t A

Por t B

Por t C

PA DR

PA DD R

PBDR

PBDDR

PCDR

PCDDR

I- bit I- bit

I- bit I- bit I- bit

I- bit None None

Port A Data Register

Port A Data Direction Register

Port B Data Register

Port B Data Direction Register

Port C Data Register

Port C Data Direction Register

Exit from Halt

Internal interrupt Internal interrupt

Internal interrupt

External interrupt

External interrupts

Internal interrupt

CPU interrupt

Reset

status

00h 00h

1111 x000b 1111 x000b

0006h

Reserved (2 bytes)

0007h

0008h ITC ITIFRE Interrupt Register 00h R/W

mode

No No

No Ye s Ye s Ye s

No Ye s

Remarks

R/W

0009h MISC MISCR Miscellaneous Register 00h R/W

000Ah

Reserved (2 bytes)

000Bh

000Ch WDG WDGCR Watchdog Control Register 7Fh R/W

000Dh to

0010h

Reserved (4 bytes)

15/139

Table 5. Hardware register memory map (continued)

Address Block Register label Register name

0011h 0012h 0013h 0014h 0015h 0016h 0017h 0018h

0019h 001Ah 001Bh 001Ch 001Dh 001Eh 001Fh

0020h

0021h

0022h

0023h

0024h

TIM

SCI

TCR2 TCR1

TCSR

TIC1HR

TIC1LR

TOC1HR

TOC1LR

TCHR

TCLR

TACHR

TAC LR

TIC2HR

TIC2LR

TOC2HR

TOC2LR

SCISR SCIDR

SCIBRR

SCICR1 SCICR2

Timer Control Register 2 Timer Control Register 1

Timer Control/Status Register

Timer Input Capture High Register 1

Timer Input Capture Low Register 1

Timer Output Compare High Register 1

Timer Output Compare Low Register 1

Timer Counter High Register

Timer Counter Low Register

Timer Alternate Counter High Register

Timer Alternate Counter Low Register

Timer Input Capture High Register 2

Timer Input Capture Low Register 2

Timer Output Compare High Register 2

Timer Output Compare Low Register 2

SCI Status Register

SCI Data Register

SCI Baud Rate Register

SCI Control Register 1 SCI Control Register 2

Reset

status

00h 00h 00h xxh xxh 80h 00h

FFh FCh FFh FCh

xxh

80h

00h

C0h

xxh

00h

x000 0000b

00h

Remarks

R/W R/W

R/W Read only Read only

R/W

R/W Read only

R/W Read only Read only

R/W

Read only

R/W

0025h 0026h 0027h 0028h

0029h 002Ah 002Bh 002Ch 002Dh 002Eh 002Fh

0030h

0031h

0032h

0036h

0037h Flash FCSR Flash Control /Status Register 00h R/W

0038h

003Fh

USB

USBPIDR

USBDMAR

USBIDR

USBISTR

USBIMR

USBCTLR

USBDADDR

USBEP0RA USBEP0RB USBEP1RA USBEP1RB USBEP2RA USBEP2RB

USB PID Register

USB DMA address Register

USB Interrupt/DMA Register

USB Interrupt Status Register

USB Interrupt Mask Register

USB Control Register

USB Device Address Register

USB Endpoint 0 Register A USB Endpoint 0 Register B USB Endpoint 1 Register A USB Endpoint 1 Register B USB Endpoint 2 Register A USB Endpoint 2 Register B

Reserved (5 Bytes)

Reserved (8 bytes)

x0h xxh x0h 00h 00h 06h 00h

0000 xxxxb

80h 0000 xxxxb 0000 xxxxb 0000 xxxxb 0000 xxxxb

Read only

R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

16/139

ST7260xx Flash program memory

5 Flash program memory

5.1 Introduction

The ST7 dual voltage High Density Flash (HDFlash) is a non-volatile memory that can be electrically erased as a single block or by individual sectors and programmed on a byte-bybyte basis using an external V

The HDFlash devices can be programmed and erased off-board (plugged in a programming tool) or on-board using ICP (in-circuit programming) or IAP (in-application programming).

The array matrix organization allows each sector to be erased and reprogrammed without affecting other sectors.

5.2 Main features

● 3 Flash programming modes:

– Insertion in a programming tool. In this mode, all sectors including option bytes

can be programmed or erased.

– ICP (in-circuit programming). In this mode, all sectors including option bytes can

be programmed or erased without removing the device from the application board.

– IAP (in-application programming). In this mode, all sectors, except Sector 0, can

be programmed or erased without removing the device from the application board and while the application is running.

● ICT (in-circuit testing) for downloading and executing user application test patterns in

RAM

● Readout protection

● Register Access Security System (RASS) to prevent accidental programming or

erasing

supply.

5.3 Structure

The Flash memory is organized in sectors and can be used for both code and data storage.

Depending on the overall Flash memory size in the microcontroller device, there are up to three user sectors (seeTa bl e 6 ). Each of these sectors can be erased independently to avoid unnecessary erasing of the whole Flash memory when only a partial erasing is required.

The first two sectors have a fixed size of 4 Kbytes (see Figure 5). They are mapped in the upper part of the ST7 addressing space so the reset and interrupt vectors are located in Sector 0 (F000h-FFFFh).

Table 6. Sectors available in Flash devices

Flash size (bytes) Available sectors

4K Sector 0

8K Sectors 0, 1

>8K Sectors 0, 1, 2

17/139

Flash program memory ST7260xx

4Kbytes

Sector 1

Sector 0

Sector 2

8K 16K

32K

Flash

FFFFh

EFFFh

DFFFh

7FFFh

24 Kbytes

memory size

8Kbytes

BFFFh

5.3.1 Readout protection

Readout protection, when selected, provides a protection against program memory content extraction and against write access to Flash memory. Even if no protection can be considered as totally unbreakable, the feature provides a very high level of protection for a general purpose microcontroller.

In Flash devices, this protection is removed by reprogramming the option. In this case, the entire program memory is first automatically erased.

Readout protection is enabled and removed through the FMP_R bit in the option byte.

Figure 5. Memory map and sector address

18/139

ST7260xx Flash program memory

ICC connector

ICCDATA

ICCCLK

RESET

HE10 connector type

Application power supply

246810

975 3

Programming tool

ICC connector

Application board

ICC cable

(See note 3)

10kΩ

ICCSEL/VPP

ST7

OSC1

OSC2

See note 1

See note 2

Application

reset source

Application

I/O

(see note 4)

Optional

5.4 ICC interface

ICC needs a minimum of 4 and up to 6 pins to be connected to the programming tool (see

Figure 6). These pins are:

– RESET –V – ICCCLK: ICC output serial clock pin – ICCDATA: ICC input/output serial data pin – ICCSEL/V – OSC1 (or OSCIN): main clock input for external source (optional) –V

Figure 6. Typical ICC interface

: device reset

: device power supply ground

: programming voltage

: application board power supply (see Figure 6, Note 3).

1. If the ICCCLK or ICCDATA pins are only used as outputs in the application, no signal isolation is necessary. As soon as the programming tool is plugged to the board, even if an ICC session is not in progress, the ICCCLK and ICCDATA pins are not available for the application. If they are used as inputs by the application, isolation such as a serial resistor has to be implemented in case another device forces the signal. Refer to the Programming Tool documentation for recommended resistor values.

2. During the ICC session, the programming tool must control the RESET between the programming tool and the application reset circuit if it drives more than 5mA at high level (PUSH-pull output or pull-up resistor <1K). A schottky diode can be used to isolate the application reset circuit in this case. When using a classical RC network with R>1K or a reset management IC with open drain output and pull-up resistor >1K, no additional components are needed. In all cases the user must ensure that no external reset is generated by the application during the ICC session.

3. The use of Pin 7 of the ICC connector depends on the programming tool architecture. This pin must be connected when using most ST programming tools (it is used to monitor the application power supply). Please refer to the programming tool manual.

4. Pin 9 has to be connected to the OSC1 (OSCIN) pin of the ST7 when the clock is not available in the application or if the selected clock option is not programmed in the option byte. ST7 devices with multioscillator capability need to have OSC2 grounded in this case.

19/139

pin. This can lead to conflicts

Flash program memory ST7260xx

5.5 ICP (in-circuit programming)

To perform ICP the microcontroller must be switched to ICC (in-circuit communication) mode by an external controller or programming tool.

Depending on the ICP code downloaded in RAM, Flash memory programming can be fully customized (number of bytes to program, program locations, or selection serial communication interface for downloading).

When using an STMicroelectronics or third-party programming tool that supports ICP and the specific microcontroller device, the user needs only to implement the ICP hardware interface on the application board (see Figure 6). For more details on the pin locations, refer to the device pinout description.

5.6 IAP (in-application programming)

This mode uses a BootLoader program previously stored in Sector 0 by the user (in ICP mode or by plugging the device in a programming tool).

This mode is fully controlled by user software. This allows it to be adapted to the user application, (such as user-defined strategy for entering programming mode, choice of communications protocol used to fetch the data to be stored). For example, it is possible to download code from the SCI, or USB interface and program it in the Flash. IAP mode can be used to program any of the Flash sectors except Sector 0, which is write/erase protected to allow recovery in case errors occur during the programming operation.

5.7 Related documentation

For details on Flash programming and ICC protocol, refer to the ST7 Flash Programming Reference Manual and to the ST7 ICC Protocol Reference Manual

5.7.1 Flash control/status register (FCSR)

This register is reserved for use by programming tool software. It controls the Flash programming and erasing operations.

FCSR Reset value:0000 0000 (00h)

76543210

00000000

R/W R/W R/W R/W R/W R/W R/W R/W

Table 7. Flash control/status register address and reset value

Address (Hex) Register label 7 6 5 4 3 2 1 0

0037hFCSR reset value00000000

20/139

ST7260xx Central processing unit (CPU)

Accumulator

X index register

Y index register

Stack pointer

Condition code register

Program counter

1C11HI NZ

Reset value = reset vector @ FFFEh-FFFFh

15 8

PCH

PCL

87 0

Reset value = stack higher address

Reset value = 1 X11X1XX

Reset value = XXh

X = undefined value

6 Central processing unit (CPU)

6.1 Introduction

This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8bit data manipulation.

6.2 Main features

● 63 basic instructions

● Fast 8-bit by 8-bit multiply

● 17 main addressing modes

● Two 8-bit index registers

● 16-bit stack pointer

● Low power modes

● Maskable hardware interrupts

● Non-maskable software interrupt

6.3 CPU registers

The six CPU registers shown in Figure 7 are not present in the memory mapping and are accessed by specific instructions.

Figure 7. CPU registers

21/139

Central processing unit (CPU) ST7260xx

6.3.1 Accumulator (A)

The Accumulator is an 8-bit general purpose register used to hold operands and the results of the arithmetic and logic calculations and to manipulate data.

6.3.2 Index registers (X and Y)

In indexed addressing modes, these 8-bit registers are used to create effective addresses or as temporary storage areas for data manipulation. (The Cross-Assembler generates a precede instruction (PRE) to indicate that the following instruction refers to the Y register.)

The Y register is not affected by the interrupt automatic procedures (not pushed to and popped from the stack).

6.3.3 Program counter (PC)

The program counter is a 16-bit register containing the address of the next instruction to be executed by the CPU. It is made of two 8-bit registers PCL (Program Counter Low which is the LSB) and PCH (Program Counter High which is the MSB).

6.3.4 Condition code register (CC)

The 8-bit Condition Code register contains the interrupt mask and four flags representative of the result of the instruction just executed. This register can also be handled by the PUSH and POP instructions. These bits can be individually tested and/or controlled by specific instructions.

CC Reset value: 111x1xxx

76543210

111HINZC

R/W R/W R/W R/W R/W

Table 8. CC register description

BIt Name Function

Half carry

This bit is set by hardware when a carry occurs between bits 3 and 4 of the ALU during an ADD or ADC instructions. It is reset by hardware during the same

instructions. 0: No half carry has occurred. 1: A half carry has occurred. This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD arithmetic subroutines.

22/139

ST7260xx Central processing unit (CPU)

Table 8. CC register description

BIt Name Function

Interrupt mask

This bit is set by hardware when entering in interrupt or by software to disable all interrupts except the TRAP software interrupt. This bit is cleared by software.

0: Interrupts are enabled. 1: Interrupts are disabled.

This bit is controlled by the RIM, SIM and IRET instructions and is tested by the JRM and JRNM instructions. Note: Interrupts requested while I is set are latched and can be processed when I is cleared. By default an interrupt routine is not interruptible because the I bit is set by hardware at the start of the routine and reset by the IRET instruction at the end of the routine. If the I bit is cleared by software in the interrupt routine, pending interrupts are serviced regardless of the priority level of the current interrupt routine

Negative

This bit is set and cleared by hardware. It is representative of the result sign of the last arithmetic, logical or data manipulation. It is a copy of the result 7th bit. 0: The result of the last operation is positive or null. 1: The result of the last operation is negative (that is, the most significant bit is a logic

1. This bit is accessed by the JRMI and JRPL instructions.

Zero (Arithmetic Management bit)

This bit is set and cleared by hardware. This bit indicates that the result of the last arithmetic, logical or data manipulation is zero. 0: The result of the last operation is different from zero. 1: The result of the last operation is zero. This bit is accessed by the JREQ and JRNE test instructions.

Carry/borrow

This bit is set and cleared by hardware and software. It indicates an overflow or an underflow has occurred during the last arithmetic operation. 0: No overflow or underflow has occurred. 1: An overflow or underflow has occurred. This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC instructions. It is also affected by the ‘bit test and branch’, shift and rotate instructions.

23/139

Central processing unit (CPU) ST7260xx

PCH PCL

PCH

PCL

PCH

PCH PCL

PCL

PCH

PCL

PCH

PCH PCL

Call

subroutine

Interrupt

event

Push Y Pop Y IRET

RET

or RSP

@ 01FFh

@ 0100h

Stack Higher Address = 017Fh Stack Lower Address =

0100h

6.3.5 Stack pointer register (SP)

SP Reset value: 01 7Fh

1514131211109876543210

000000010SP6SP5SP4SP3SP2SP1SP0

R/W R/W R/W R/W R/W R/W R/W

The Stack Pointer is a 16-bit register which is always pointing to the next free location in the stack. It is then decremented after data has been pushed onto the stack and incremented before data is popped from the stack (see Figure 8).

Since the stack is 128 bytes deep, the 9 most significant bits are forced by hardware. Following an MCU reset, or after a Reset Stack Pointer instruction (RSP), the Stack Pointer contains its reset value (the SP7 to SP0 bits are set) which is the stack higher address.

The least significant byte of the Stack Pointer (called S) can be directly accessed by an LD instruction.

Note: When the lower limit is exceeded, the Stack Pointer wraps around to the stack upper limit,

without indicating the stack overflow. The previously stored information is then overwritten and therefore lost. The stack also wraps in case of an underflow.

The stack is used to save the return address during a subroutine call and the CPU context during an interrupt. The user may also directly manipulate the stack by means of the PUSH and POP instructions. In the case of an interrupt, the PCL is stored at the first location pointed to by the SP. Then the other registers are stored in the next locations as shown in

Figure 8.

● When an interrupt is received, the SP is decremented and the context is pushed on the

stack.

● On return from interrupt, the SP is incremented and the context is popped from the

stack.

A subroutine call occupies two locations and an interrupt five locations in the stack area.

Figure 8. Stack manipulation example

24/139

ST7260xx Reset and clock management

7 Reset and clock management

7.1 Reset

The Reset procedure is used to provide an orderly software start-up or to exit low power modes.

Three reset modes are provided: a low voltage (LVD) reset, a watchdog reset and an external reset at the RESET

A reset causes the reset vector to be fetched from addresses FFFEh and FFFFh in order to be loaded into the PC and with program execution starting from this point.

An internal circuitry provides a 4096 CPU clock cycle delay from the time that the oscillator becomes active.

Caution: When the ST7 is unprogrammed or fully erased, the Flash is blank and the RESET vector is

not programmed. For this reason, it is recommended to keep the RESET until programming mode is entered, in order to avoid unwanted behavior

7.2 Low voltage detector (LVD)

pin.

pin in low state

Low voltage reset circuitry generates a reset when VDD is:

● below V

During low voltage reset, the RESET devices.

It is recommended to make sure that the V device is exiting from Reset, to ensure the application functions properly.

when VDD is rising,

IT+

when VDD is falling.

IT-

7.2.1 Watchdog reset

When a watchdog reset occurs, the RESET pin is pulled low permitting the MCU to reset other devices in the same way as the low voltage reset (Figure 9).

7.2.2 External reset

The external reset is an active low input signal applied to the RESET pin of the MCU. As shown in Figure 12, the RESET CPU clock cycles.

An internal Schmitt trigger at the RESET

pin is held low, thus permitting the MCU to reset other

supply voltage rises monotonously when the

signal must stay low for a minimum of one and a half

pin is provided to improve noise immunity.

25/139

Reset and clock management ST7260xx

LOW VOLTAGE

FROM

WATCHDOG

RESET

INTERNAL

DETECTOR

RESET

IT+

IT-

Addresses

$FFFE

Temporization (4096 CPU clock cycles)

IT+

Figure 9. Low voltage detector functional diagram

Figure 10. Low voltage reset signal output

Note: Hysteresis (V

IT+-VIT-

) = V

hys

Figure 11. Temporization timing diagram after an internal reset

26/139

ST7260xx Reset and clock management

OSCIN

CPU

FFFF

FFFE

RESET

WATCHDOG RESET

DDR

OXOV

4096 CPU

CLOCK

CYCLES

DELAY

Figure 12. Reset timing diagram

Note: Refer to Electrical Characteristics for values of t

DDR

, t

OXOV

, V

IT+

, V

IT-

and V

hys

7.3 Clock system

7.3.1 General description

The MCU accepts either a crystal or ceramic resonator, or an external clock signal to drive the internal oscillator. The internal clock (f frequency (f

), which is divided by 3 (and by 2 or 4 for USB, depending on the external

OSC

clock used). The internal clock is further divided by 2 by setting the SMS bit in the Miscellaneous Register. Using the OSC24/12 bit in the option byte, a 12 MHz or a 24 MHz external clock can be used to provide an internal frequency of either 2, 4 or 8 MHz while maintaining a 6 MHz for the USB (refer to Figure 15).

The internal clock signal (f

) is also routed to the on-chip peripherals. The CPU clock

CPU

signal consists of a square wave with a duty cycle of 50%.

The internal oscillator is designed to operate with an AT-cut parallel resonant quartz or ceramic resonator in the frequency range specified for f recommended when using a crystal, and Ta bl e 9 lists the recommended capacitance. The crystal and associated components should be mounted as close as possible to the input pins in order to minimize output distortion and start-up stabilisation time.

) is derived from the external oscillator

CPU

. The circuit shown in Figure 14 is

osc

27/139

Reset and clock management ST7260xx

OSCIN

OSCOUT

EXTERNAL

CLOCK

OSCIN

OSCOUT

OSCIN

OSCOUT

Table 9. Recommended values for 24 MHz crystal resonator

Symbol Values

(1)

1. R

SMAX

OSCIN

OSCOUT

is the equivalent serial resistor of the crystal (see crystal specification).

SMAX

20 Ω 25 Ω 70 Ω

56pF 47pF 22pF

1-10 MΩ 1-10 MΩ 1-10 MΩ

7.3.2 External clock

An external clock may be applied to the OSCIN input with the OSCOUT pin not connected, as shown on Figure 13. The t input. The equivalent specification of the external clock source should be used instead of t

(see Section 16.5: Clock and timing characteristics).

OXOV

Figure 13. External clock source connections

specifications do not apply when using an external clock

OXOV

Figure 14. Crystal/ceramic resonator

28/139

ST7260xx Reset and clock management

CPU and

8, 4 or 2 MHz

6 MHz (USB)

24 or

peripherals)

12 MHz

Crystal

OSC24/12

SMS

Figure 15. Clock block diagram

29/139

Interrupts ST7260xx

8 Interrupts

The ST7 core may be interrupted by one of two different methods: maskable hardware interrupts as listed in Table 10: Interrupt mapping and a non-maskable software interrupt (TRAP). The Interrupt processing flowchart is shown in Figure 16.

The maskable interrupts must be enabled clearing the I bit in order to be serviced. However, disabled interrupts may be latched and processed when they are enabled (see external interrupts subsection).

When an interrupt has to be serviced:

● Normal processing is suspended at the end of the current instruction execution.

● The PC, X, A and CC registers are saved onto the stack.

● The I bit of the CC register is set to prevent additional interrupts.

The PC is then loaded with the interrupt vector of the interrupt to service and the first instruction of the interrupt service routine is fetched (refer to Table 10: Interrupt mapping for vector addresses).

The interrupt service routine should finish with the IRET instruction which causes the contents of the saved registers to be recovered from the stack.

Note: As a consequence of the IRET instruction, the I bit will be cleared and the main program will

resume.

Priority management

By default, a servicing interrupt cannot be interrupted because the I bit is set by hardware entering in interrupt routine.

In the case several interrupts are simultaneously pending, a hardware priority defines which one will be serviced first (see Table 10: Interrupt mapping).

Non-maskable software interrupts

This interrupt is entered when the TRAP instruction is executed regardless of the state of the I bit. It will be serviced according to the flowchart on Figure 16.

Interrupts and low power mode

All interrupts allow the processor to leave the Wait low power mode. Only external and specific mentioned interrupts allow the processor to leave the Halt low power mode (refer to the “Exit from HALT“ column in Table 10: Interrupt mapping).

External interrupts

The pins ITi/PAk and ITj/PBk (i=1,2; j= 5,6; k=4,5) can generate an interrupt when a rising edge occurs on this pin. Conversely, the ITl/PAn and ITm/PBn pins (l=3,4; m= 7,8; n=6,7) can generate an interrupt when a falling edge occurs on this pin.

Interrupt generation will occur if it is enabled with the ITiE bit (i=1 to 8) in the ITRFRE register and if the I bit of the CCR is reset.

30/139

ST7260xx Interrupts

BIT I SET

IRET

FROM RESET

LOAD PC FROM INTERRUPT VECTOR

STACK PC, X, A, CC

SET I BIT

FETCH NEXT INSTRUCTION

EXECUTE INSTRUCTION

THIS CLEARS I BIT BY DEFAULT

RESTORE PC, X, A, CC FROM STACK

INTERRUPT

Peripheral interrupts

Different peripheral interrupt flags in the status register are able to cause an interrupt when they are active if both:

● The I bit of the CC register is cleared.

● The corresponding enable bit is set in the control register.

If any of these two conditions is false, the interrupt is latched and thus remains pending.

Clearing an interrupt request is done by one of the two following operations:

● Writing “0” to the corresponding bit in the status register.

● Accessing the status register while the flag is set followed by a read or write of an

associated register.

Note: 1 The clearing sequence resets the internal latch. A pending interrupt (i.e. waiting to be

enabled) will therefore be lost if the clear sequence is executed.

2 All interrupts allow the processor to leave the Wait low power mode.

3 Exit from Halt mode may only be triggered by an External Interrupt on one of the ITi ports

(PA4-PA7 and PB4-PB7), an end suspend mode Interrupt coming from USB peripheral, or a reset.

Figure 16. Interrupt processing flowchart

31/139

Interrupts ST7260xx

Table 10. Interrupt mapping

N°

Source

block

Description

RESET Reset

TRAP Software Interrupt no FFFCh-FFFDh

label

N/A

Priority

order

Highest

Priority

Exit from

Halt

yes FFFEh-FFFFh

Vector

address

FLASH Flash Start Programming Interrupt yes FFFAh-FFFBh

USB End Suspend Mode ISTR

FFF8h-FFF9h

yes

1 ITi External Interrupts ITRFRE FFF6h-FFF7h

2 TIMER Timer Peripheral Interrupts TIMSR

FFF4h-FFF5h

3 Reserved FFF2h-FFF3h

4 SCI SCI Peripheral Interrupts SCISR FFF0h-FFF1h

Lowest Priority

5 USB USB Peripheral Interrupts ISTR FFEEh-FFEFh

8.0.1 Interrupt register (ITRFRE)

ITRFRE Reset value: 0000 0000 (00h)

76543210

IT8E IT7E IT6E IT5E IT4E IT3E IT2E IT1E

R/W R/W R/W R/W R/W R/W R/W R/W

Table 11. ITRFRE register description

Bit Name Function

Interrupt enable control bits

If an ITiE bit is set, the corresponding interrupt is generated when: – a rising edge occurs on the pin PA4/IT1 or PA5/IT2 or PB4/IT5 or PB5/IT6 or – a falling edge occurs on the pin PA6/IT3 or PA7/IT4 or PB6/IT7 or PB7/IT8

7:0

ITiE

(i=1 to

No interrupt is generated elsewhere..

Table 12. Interrupt register map and reset values

Address (Hex.)Register label76543210

0008h

ITRFRE reset value

IT8E0IT7E0IT6E0IT5E0IT4E0IT3E0IT2E0IT1E

32/139

ST7260xx Power saving modes

9 Power saving modes

9.1 Introduction

To give a large measure of flexibility to the application in terms of power consumption, two main power saving modes are implemented in the ST7.

After a RESET, the normal operating mode is selected by default (RUN mode). This mode drives the device (CPU and embedded peripherals) by means of a master clock which is based on the main oscillator frequency divided by 3 (f

From Run mode, the different power saving modes may be selected by setting the relevant register bits or by calling the specific ST7 software instruction whose action depends on the oscillator status.

9.2 Halt mode

The MCU consumes the least amount of power in Halt mode. The Halt mode is entered by executing the HALT instruction. The internal oscillator is then turned off, causing all internal processing to be stopped, including the operation of the on-chip peripherals.

CPU

When entering Halt mode, the I bit in the Condition Code Register is cleared. Thus, all external interrupts (ITi or USB end suspend mode) are allowed and if an interrupt occurs, the CPU clock becomes active.

The MCU can exit Halt mode on reception of either an external interrupt on ITi, an end suspend mode interrupt coming from USB peripheral, or a reset. The oscillator is then turned on and a stabilization time is provided before releasing CPU operation. The stabilization time is 4096 CPU clock cycles.

After the start up delay, the CPU continues operation by servicing the interrupt which wakes it up or by fetching the reset vector if a reset wakes it up.

33/139

Power saving modes ST7260xx

EXTERNAL

INTERRUPT*

RESET

HALT INSTRUCTION

4096 CPU CLOCK

FETCH RESET VECTOR

OR SERVICE INTERRUPT

CYCLES DELAY

CPU CLOCK

OSCILLATOR PERIPH. CLOCK

I-BIT

SET

CPU CLOCK

OSCILLATOR PERIPH. CLOCK

I-BIT

OFF

CLEARED

OFF

Figure 17. Halt mode flowchart

Note: Before servicing an interrupt, the CC register is pushed on the stack. The I-Bit is set during

the interrupt routine and cleared when the CC register is popped.

9.3 Slow mode

In Slow mode, the oscillator frequency can be divided by 2 as selected by the SMS bit in the Miscellaneous Register. The CPU and peripherals are clocked at this lower frequency. Slow mode is used to reduce power consumption, and enables the user to adapt the clock frequency to the available supply voltage.

9.4 Wait mode

Wait mode places the MCU in a low power consumption mode by stopping the CPU.

This power saving mode is selected by calling the “WFI” ST7 software instruction.

All peripherals remain active. During Wait mode, the I bit of the CC register is forced to 0 to enable all interrupts. All other registers and memory remain unchanged. The MCU remains in Wait mode until an interrupt or Reset occurs, whereupon the Program Counter branches to the starting address of the interrupt or Reset service routine.

34/139

ST7260xx Power saving modes

WFI INSTRUCTION

RESET

INTERRUPT

CPU CLOCK

OSCILLATOR PERIPH. CLOCK

I-BIT

CLEARED

OFF

CPU CLOCK

OSCILLATOR PERIPH. CLOCK

I-BIT

SET

FETCH RESET VECTOR

OR SERVICE INTERRUPT

4096 CPU CLOCK

CYCLES DELAY

IF RESET

The MCU will remain in Wait mode until a Reset or an Interrupt occurs, causing it to wake up.

Refer to Figure 18.

Figure 18. Wait mode flowchart

Note: Before servicing an interrupt, the CC register is pushed on the stack. The I-Bit is set during

the interrupt routine and cleared when the CC register is popped.

35/139

I/O ports ST7260xx

10 I/O ports

10.1 Introduction

The I/O ports offer different functional modes:

● Transfer of data through digital inputs and outputs and for specific pins

● Alternate signal input/output for the on-chip peripherals

● External interrupt generation

An I/O port consists of up to 8 pins. Each pin can be programmed independently as a digital input (with or without interrupt generation) or a digital output.

10.2 Functional description

Each port is associated to 2 main registers:

● Data register (DR)

● Data direction register (DDR)

Each I/O pin may be programmed using the corresponding register bits in DDR register: bit X corresponding to pin X of the port. The same correspondence is used for the DR register.

Table 13. I/O pin functions

DDR Mode

0 Input

1 Output

Input modes

The input configuration is selected by clearing the corresponding DDR register bit.

In this case, reading the DR register returns the digital value applied to the external I/O pin.

Note: 1 All the inputs are triggered by a Schmitt trigger.

2 When switching from input mode to output mode, the DR register should be written first to

output the correct value as soon as the port is configured as an output.

Interrupt function

When an I/O is configured as an Input with Interrupt, an event on this I/O can generate an external Interrupt request to the CPU. The interrupt sensitivity is given independently according to the description mentioned in the ITRFRE interrupt register.

Each pin can independently generate an Interrupt request.

Each external interrupt vector is linked to a dedicated group of I/O port pins (see Interrupts section). If more than one input pin is selected simultaneously as an interrupt source, this is logically ORed. For this reason if one of the interrupt pins is tied low, the other ones are masked.

Output mode

The pin is configured in output mode by setting the corresponding DDR register bit (see

Ta bl e 1 3).

36/139

ST7260xx I/O ports

In this mode, writing “0” or “1” to the DR register applies this digital value to the I/O pin through the latch. Therefore, the previously saved value is restored when the DR register is read.

Note: The interrupt function is disabled in this mode.

Alternate function

When an on-chip peripheral is configured to use a pin, the alternate function is automatically selected. This alternate function takes priority over standard I/O programming. When the signal is coming from an on-chip peripheral, the I/O pin is automatically configured in output mode (push-pull or open drain according to the peripheral).

When the signal is going to an on-chip peripheral, the I/O pin has to be configured in input mode. In this case, the pin’s state is also digitally readable by addressing the DR register.

Note: 1 Input pull-up configuration can cause an unexpected value at the input of the alternate

peripheral input.

2 When the on-chip peripheral uses a pin as input and output, this pin must be configured as

an input (DDR = 0).

Caution: The alternate function must not be activated as long as the pin is configured as an input with

interrupt in order to avoid generating spurious interrupts.

10.2.1 Port A

Table 14. Port A0, A3, A4, A5, A6, A7 description

Port A

PA0 with pull-up push-pull

PA3 with pull-up push-pull Timer EXTCLK

PA4 with pull-up

PA5 with pull-up

PA 6

PA7 with pull-up

(2)

(1)

Input

with pull-up

I/O Alternate function

Output Signal Condition

MCO (Main Clock

Output)

CC0 = 1 (Timer CR2)

Timer ICAP1

push-pull

IT1 Schmitt triggered

input

Timer ICAP2

IT2 Schmitt triggered

input

Timer OCMP1 OC1E = 1

IT3 Schmitt triggered

input

Timer OCMP2 OC2E = 1

IT4 Schmitt triggered

input

MCO = 1 (MISCR)

CC1 =1

IT1E = 1 (ITIFRE)

IT2E = 1 (ITIFRE)

IT3E = 1 (ITIFRE)

IT4E = 1 (ITIFRE)

1. Reset state

2. Not available on SO24

37/139

I/O ports ST7260xx

DDR

LATCH

DR SEL

DDR SEL

PA D

ALTERNATE ENABLE

ALTERNATE

ALTERNATE INPUT

PULL-UP

OUTPUT

P-BUFFER

N-BUFFER

CMOS SCHMITT TRIGGER

DIODES

DATA BUS

Figure 19. PA0, PA3, PA4, PA5, PA6, PA7 configuration

Table 15. PA1, PA2 description

Port A

Input

PA1 without pull-up

PA2 without pull-up

1. Reset state

(1)

I/O Alternate function

Output Signal Condition

Very High Current open drain

38/139

ST7260xx I/O ports

DDR

LATCH

DR SEL

DDR SEL

PA D

ALTERNATE ENABLE

ALTERNATE OUTPUT

N-BUFFER

CMOS SCHMITT TRIGGER

DATA BUS

Figure 20. PA1, PA2 configuration

10.2.2 Port B

Table 16. Port B description

Port B

PB0 without pull-up push-pull

PB1 without pull-up push-pull

PB2 without pull-up push-pull

PB3 without pull-up push-pull

PB4 without pull-up push-pull

PB5 without pull-up push-pull

PB6 without pull-up push-pull

Input

I/O Alternate function

(1)

Output Signal Condition

USBOE (USB output enable)

IT5 Schmitt triggered input

IT6 Schmitt triggered input

IT7 Schmitt triggered input

USBOE =1

(2)

(MISCR)

IT4E = 1 (ITIFRE)

IT5E = 1 (ITIFRE)

IT6E = 1 (ITIFRE)

39/139

I/O ports ST7260xx

DDR

LATCH

DR SEL

DDR SEL

PA D

ALTERNATE ENABLE

DIGITAL ENABLE

ALTERNATE ENABLE

ALTERNATE

ALTERNATE INPUT

OUTPUT

P-BUFFER

N-BUFFER

DATA BUS

DIODES

Table 16. Port B description (continued)

I/O Alternate function

Port B

Input

(1)

Output Signal Condition

PB7 without pull-up push-pull

1. Reset state

2. On SO24 only

Figure 21. Port B configuration

IT8 Schmitt triggered input

IT7E = 1 (ITIFRE)

10.2.3 Port C

Table 17. Port C description

Port C

PC0 with pull-up push-pull RDI (SCI input)

PC1 with pull-up push-pull TDO (SCI output) SCI enable

(2)

PC2

1. Reset state

2. Not available on SO24

with pull-up push-pull

40/139

Input

(1)

I/O Alternate function

Output Signal Condition

USBOE =1 (MISCR)

USBOE (USB output enable)

ST7260xx I/O ports

DDR

LATCH

DR SEL

DDR SEL

PA D

ALTERNATE ENABLE

ALTERNATE

ALTERNATE INPUT

PULL-UP

OUTPUT

P-BUFFER

N-BUFFER

CMOS SCHMITT TRIGGER

DATA BUS

DIODES

Figure 22. Port C configuration

10.2.4 Register description

10.2.5 Data register (PxDR)

PA DR PBDR PCDR

76543210

D7 D6 D5 D4 D3 D2 D1 D0

R/W R/W R/W R/W R/W R/W R/W R/W

Table 18. PxDR register description

Bit Name Function

Data bits

The DR register has a specific behavior according to the selected input/output configuration. Writing the DR register is always taken into account even if the pin is configured as an input. Reading the DR register returns either the DR register latch content (pin configured as output) or the digital value applied to the I/O pin (pin configured as input).

– When using open-drain I/Os in output configuration, the value read in DR is the

digital value applied to the I/O pin.

– For Port C, unused bits (7-3) are not accessible

7:0

D[7:0]

Reset value: 0000 0000 (00h) Reset value: 0000 0000 (00h) Reset value: 1111 x000 (Fxh)

41/139

I/O ports ST7260xx

10.2.6 Data direction register (PxDDR)

PADDR PBDDR PCDDR

76543210

DD7 DD6 DD5 DD4 DD3 DD2 DD1 DD0

R/W R/W R/W R/W R/W R/W R/W R/W

Table 19. PxDDR register description

Bit Name Function

Data Direction bits

The DDR register gives the input/output direction configuration of the pins. Each bit is set and cleared by software.

7:0

[7:0]

0: Input mode 1: Output mode For Port C, unused bits (7-3) are not accessible

Table 20. I/O port register map and reset values

Reset value: 0000 0000 (00h) Reset value: 0000 0000 (00h) Reset value: 1111 x000 (Fxh)

Address (Hex.)Register label76543210

0000h

0001h

0002h

0003h

0004h

0005h

PA DR reset value

PADDR reset value

PBDR reset value

PBDDR reset value

PCDR reset value

PCDDR reset value

0006h Reserved

0007h Reserved

10.2.7 Related documentation

● AN 970: SPI Communication between ST7 and EEPROM

● AN1048: Software LCD driver

DD70DD60DD50DD40DD30DD20DD10DD0

DD7

DD60DD50DD40DD30DD20DD10DD0

42/139

ST7260xx Miscellaneous register

11 Miscellaneous register

MISCR Reset value: 0000 0000 (00h)

76543210

-----SMSUSBOEMCO

R/W R/W R/W

Table 21. MISCR register description

Bit Name Function

7:3 Reserved

Slow mode select

This bit is set by software and only cleared by hardware after a reset. If this bit is set, it

SMS

USB

enables the use of an internal divide-by-2 clock divider (refer to Figure 15 on page 29). The SMS bit has no effect on the USB frequency.

0: Divide-by-2 disabled and CPU clock frequency is standard 1: Divide-by-2 enabled and CPU clock frequency is halved

USB enable

If this bit is set, the port PC2 (PB1 on SO24) outputs the USB output enable signal (at

“1” when the ST7 USB is transmitting data). Unused bits 7-4 are set.

Main clock out selection

This bit enables the MCO alternate function on the PA0 I/O port. It is set and cleared

MCO

by software.

0: MCO alternate function disabled (I/O pin free for general-purpose I/O) 1: MCO alternate function enabled (f

Table 22. Miscellaneous register map and reset values

on I/O port)

CPU

Address (Hex.)Register label76543210

USB

0009h MISCR

reset value

SMS

OE0MCO

43/139

Watchdog timer (WDG) ST7260xx

12 Watchdog timer (WDG)

12.1 Introduction

The Watchdog timer is used to detect the occurrence of a software fault, usually generated by external interference or by unforeseen logical conditions, which causes the application program to abandon its normal sequence. The Watchdog circuit generates an MCU reset on expiry of a programmed time period, unless the program refreshes the counter’s contents before the T6 bit becomes cleared.

12.2 Main features

● Programmable free-running counter (64 increments of 49,152 CPU cycles)

● Programmable reset

● Reset (if watchdog activated) when the T6 bit reaches zero

● Optional reset on HALT instruction (configurable by option byte)

● Hardware Watchdog selectable by option byte.

12.3 Functional description

The counter value stored in the CR register (bits T6:T0), is decremented every 49,152 machine cycles, and the length of the timeout period can be programmed by the user in 64 increments.

If the watchdog is activated (the WDGA bit is set) and when the 7-bit timer (bits T6:T0) rolls over from 40h to 3Fh (T6 becomes cleared), it initiates a reset cycle pulling low the reset pin for a period of t

The application program must write in the CR register at regular intervals during normal operation to prevent an MCU reset. This downcounter is free-running: it counts down even if the watchdog is disabled. The value to be stored in the CR register must be between FFh and C0h (see Table 23: Watchdog timing (f

● The WDGA bit is set (watchdog enabled)

● The T6 bit is set to prevent generating an immediate reset

● The T5:T0 bits contain the number of increments which represents the time delay

before the watchdog produces a reset.

(see Table 62: Control timings on page 114).

DOG

= 8 MHz) on page 45):

CPU

44/139

ST7260xx Watchdog timer (WDG)

RESET

WDGA

7-BIT DOWNCOUNTER

CPU

CLOCK DIVIDER

WATCHDOG CONTROL REGISTER (CR)

÷49152

Figure 23. Watchdog block diagram

Table 23. Watchdog timing (f

CR register initial value WDG timeout period (ms)

Max FFh 393.216

Min C0h 6.144

= 8 MHz)

CPU

Note: 1 Following a reset, the watchdog is disabled. Once activated it cannot be disabled, except by

a reset.

2 The T6 bit can be used to generate a software reset (the WDGA bit is set and the T6 bit is

cleared).

12.3.1 Software watchdog option

If Software Watchdog is selected by option byte, the watchdog is disabled following a reset. Once activated it cannot be disabled, except by a reset.

The T6 bit can be used to generate a software reset (the WDGA bit is set and the T6 bit is cleared).

12.3.2 Hardware watchdog option

If Hardware Watchdog is selected by option byte, the watchdog is always active and the WDGA bit in the CR is not used.

45/139

Watchdog timer (WDG) ST7260xx

12.3.3 Low power modes

WAIT Instruction

No effect on Watchdog.

HALT Instruction

If the Watchdog reset on HALT option is selected by option byte, a HALT instruction causes an immediate reset generation if the Watchdog is activated (WDGA bit is set).

12.3.4 Using Halt mode with the WDG (option)

If the Watchdog reset on HALT option is not selected by option byte, the Halt mode can be used when the watchdog is enabled.

In this case, the HALT instruction stops the oscillator. When the oscillator is stopped, the WDG stops counting and is no longer able to generate a reset until the microcontroller receives an external interrupt or a reset.

If an external interrupt is received, the WDG restarts counting after 4096 CPU clocks. If a reset is generated, the WDG is disabled (reset state).

Recommendations

● Make sure that an external event is available to wake up the microcontroller from Halt

mode.

● Before executing the HALT instruction, refresh the WDG counter, to avoid an

unexpected WDG reset immediately after waking up the microcontroller.

● When using an external interrupt to wake up the microcontroller, reinitialize the

corresponding I/O as “Input Pull-up with Interrupt” before executing the HALT instruction. The main reason for this is that the I/O may be wrongly configured due to external interference or by an unforeseen logical condition.

● For the same reason, reinitialize the level sensitiveness of each external interrupt as a

precautionary measure.

● The opcode for the HALT instruction is 0x8E. To avoid an unexpected HALT instruction

due to a program counter failure, it is advised to clear all occurrences of the data value 0x8E from memory. For example, avoid defining a constant with the value 0x8E.

● As the HALT instruction clears the I bit in the CC register to allow interrupts, the user

may choose to clear all pending interrupt bits before executing the HALT instruction. This avoids entering other peripheral interrupt routines after executing the external interrupt routine corresponding to the wake-up event (reset or external interrupt).

12.3.5 Interrupts

None.

46/139

ST7260xx Watchdog timer (WDG)

12.3.6 Control register (WDGCR)

WDGCR Reset value: 0111 1111 (7Fh)

76543210

WDGA T[6:0]

R/W R/W

Table 24. WDGCR register description

Bit Name Function

Activation bit

This bit is set by software and only cleared by hardware after a reset. When

7WDGA

6:0 T[6:0]

Table 25. Watchdog timer register map and reset values

WDGA = 1, the watchdog can generate a reset. 0: Watchdog disabled 1: Watchdog enabled

Note: This bit is not used if the hardware watchdog option is enabled by option byte.

7-bit counter (MSB to LSB)

These bits contain the value of the Watchdog counter. A reset is produced when it rolls over from 40h to 3Fh (T6 is cleared).

Address (Hex.)Register label76543210

000Ch

WDGCR reset value

WDGA0T6

47/139

Watchdog timer (WDG) ST7260xx

12.4 16-bit timer

12.4.1 Introduction

The timer consists of a 16-bit free-running counter driven by a programmable prescaler.

It may be used for a variety of purposes, including pulse length measurement of up to two input signals (input capture) or generation of up to two output waveforms (output compare and PWM).

Pulse lengths and waveform periods can be modulated from a few microseconds to several milliseconds using the timer prescaler and the CPU clock prescaler.

Some ST7 devices have two on-chip 16-bit timers. They are completely independent, and do not share any resources. They are synchronized after a MCU reset as long as the timer clock frequencies are not modified.

This description covers one or two 16-bit timers. In ST7 devices with two timers, register names are prefixed with TA (Timer A) or TB (Timer B).

12.4.2 Main features

● Programmable prescaler: f

● Overflow status flag and maskable interrupt

● External clock input (must be at least four times slower than the CPU clock speed) with

divided by 2, 4 or 8

CPU

the choice of active edge

● 1 or 2 output compare functions each with:

– 2 dedicated 16-bit registers – 2 dedicated programmable signals – 2 dedicated status flags – 1 dedicated maskable interrupt

● 1 or 2 input capture functions each with:

– 2 dedicated 16-bit registers – 2 dedicated active edge selection signals – 2 dedicated status flags – 1 dedicated maskable interrupt

● Pulse width modulation mode (PWM)

● One pulse mode

● Reduced power mode

● 5 alternate functions on I/O ports (ICAP1, ICAP2, OCMP1, OCMP2, EXTCLK)

(a)

The timer block diagram is shown in Figure 24.

a. Some timer pins may not be available (not bonded) in some ST7 devices. Refer to Section 3: Pin description.

When reading an input signal on a non-bonded pin, the value will always be ‘1’.

48/139

ST7260xx Watchdog timer (WDG)

12.4.3 Functional description

Counter

The main block of the programmable timer is a 16-bit free running upcounter and its associated 16-bit registers. The 16-bit registers are made up of two 8-bit registers called high and low.

● Counter Register (CR)

– Counter High Register (CHR) is the most significant byte (MSB) – Counter Low Register (CLR) is the least significant byte (LSB)

● Alternate Counter Register (ACR)

– Alternate Counter High Register (ACHR) is the most significant byte (MSB) – Alternate Counter Low Register (ACLR) is the least significant byte (LSB)

These two read-only 16-bit registers contain the same value but with the difference that reading the ACLR register does not clear the TOF bit (timer overflow flag), located in the Status register (SR) (see note at the end of paragraph entitled 16-bit read sequence).

Writing in the CLR register or ACLR register resets the free running counter to the FFFCh value. Both counters have a reset value of FFFCh (this is the only value which is reloaded in the 16-bit timer). The reset value of both counters is also FFFCh in one pulse mode and PWM mode.

The timer clock depends on the clock control bits of the CR2 register, as illustrated in

Ta bl e 3 2. The value in the counter register repeats every 131072, 262144 or 524288 CPU

clock cycles depending on the CC[1:0] bits. The timer frequency can be f f

/8 or an external frequency.

CPU

/2, f

CPU

/4,

49/139

Watchdog timer (WDG) ST7260xx

MCU-peripheral interface

Counter

Alternate

Output

Compare

Output Compare

Edge Detect

Overflow

Detect

circuit

1/2 1/4 1/8

8-bit

buffer

ST7 internal bus

Latch 1

OCMP1

ICAP1

EXTCLK

fCPU

Timer interrupt

ICF2ICF1 TIMD 0 0OCF2OCF1 TOF

PWMOC1E

EXEDG

IEDG2CC0CC1

OC2E

OPM

FOLV2ICIE OLVL1IEDG1OLVL2FOLV1OCIE TOIE

ICAP2

Latch 2

OCMP2

8 low

8 high

16 16

(Control register 1) CR1

(Control register 2) CR2

(Control/Status register) CSR

8 8 8

88 8

high

low

high

low

EXEDG

Timer internal bus

circuit 1

Edge Detect

circuit 2

circuit

Output

Compare

Input

Capture

Input

Capture

CC[1:0]

(See note 1)

Counter register

Figure 24. Timer block diagram

1. If IC, OC and TO interrupt requests have separate vectors then the last OR is not present (see Table 10:

Interrupt mapping on page 32).

50/139

ST7260xx Watchdog timer (WDG)

Read

At t0

Read

Returns the buffered

LSB value at t0

At t0 +Δt

Other

instructions

Beginning of the sequence

Sequence completed

LSB is buffered

LSB

MSB

16-bit read sequence

The 16-bit read sequence (from either the Counter register or the Alternate Counter register) is illustrated in the following Figure 25.

Figure 25.

16-bit read sequence

The user must first read the MSB, afterwhich the LSB value is automatically buffered.

This buffered value remains unchanged until the 16-bit read sequence is completed, even if the user reads the MSB several times.

After a complete reading sequence, if only the CLR register or ACLR register are read, they return the LSB of the count value at the time of the read.

Whatever the timer mode used (input capture, output compare, one pulse mode or PWM mode) an overflow occurs when the counter rolls over from FFFFh to 0000h then:

● The TOF bit of the SR register is set.

● A timer interrupt is generated if:

– TOIE bit of the CR1 register is set and – I bit of the CC register is cleared.

If one of these conditions is false, the interrupt remains pending to be issued as soon as they are both true.

Clearing the overflow interrupt request is done in two steps:

1. Reading the SR register while the TOF bit is set.

2. An access (read or write) to the CLR register.

Note: The TOF bit is not cleared by access to the ACLR register. The advantage of accessing the

ACLR register rather than the CLR register is that it allows simultaneous use of the overflow function and reading the free running counter at random times (for example, to measure elapsed time) without the risk of clearing the TOF bit erroneously.

The timer is not affected by Wait mode.

In Halt mode, the counter stops counting until the mode is exited. Counting then resumes from the previous count (MCU awakened by an interrupt) or from the reset count (MCU awakened by a reset).

51/139

Watchdog timer (WDG) ST7260xx

CPU clock

FFFD FFFE FFFF 0000 0001 0002 0003

Internal reset

Timer clock

Counter register

Timer Overflow Flag (TOF)

FFFC FFFD 0000 0001

CPU clock

Internal reset

Timer clock

Counter register

Timer Overflow Flag (TOF)

CPU clock

Internal reset

Timer clock

Counter register

Timer Overflow Flag (TOF)

FFFC FFFD

0000

External clock

The external clock (where available) is selected if CC0 = 1 and CC1 = 1 in the CR2 register.

The status of the EXEDG bit in the CR2 register determines the type of level transition on the external clock pin EXTCLK that will trigger the free running counter.

The counter is synchronized with the falling edge of the internal CPU clock.

A minimum of four falling edges of the CPU clock must occur between two consecutive active edges of the external clock; thus the external clock frequency must be less than a quarter of the CPU clock frequency.

Figure 26. Counter timing diagram, internal clock divided by 2

Figure 27. Counter timing diagram, internal clock divided by 4

Figure 28. Counter timing diagram, internal clock divided by 8

Note: The MCU is in reset state when the internal reset signal is high, when it is low the MCU is

running.

52/139

ST7260xx Watchdog timer (WDG)

Input capture

In this section, the index, i, may be 1 or 2 because there are two input capture functions in the 16-bit timer.

The two 16-bit input capture registers (IC1R/IC2R) are used to latch the value of the free running counter after a transition is detected on the ICAPi pin (see Figure 30).

Table 26. Input capture byte distribution

ICiR ICiHR ICiLR

The ICiR registers are read-only registers.

The active transition is software programmable through the IEDGi bit of Control Registers (CRi).

Timing resolution is one count of the free running counter: (

/CC[1:0]).

CPU

Procedure

To use the input capture function select the following in the CR2 register:

● Select the timer clock (CC[1:0]) (see Tab le 3 2 ).

● Select the edge of the active transition on the ICAP2 pin with the IEDG2 bit (the ICAP2

pin must be configured as floating input or input with pull-up without interrupt if this configuration is available).

Select the following in the CR1 register:

● Set the ICIE bit to generate an interrupt after an input capture coming from either the

ICAP1 pin or the ICAP2 pin

● Select the edge of the active transition on the ICAP1 pin with the IEDG1 bit (the

ICAP1pin must be configured as floating input or input with pull-up without interrupt if this configuration is available).

When an input capture occurs:

● ICFi bit is set.

● The ICiR register contains the value of the free running counter on the active transition

on the ICAPi pin (see Figure 30).

● A timer interrupt is generated if the ICIE bit is set and the I bit is cleared in the CC

Clearing the Input Capture interrupt request (that is, clearing the ICFi bit) is done in two steps:

1. Reading the SR register while the ICFi bit is set

2. An access (read or write) to the ICiLR register

53/139

Watchdog timer (WDG) ST7260xx

ICIE

CC0CC1

16-bit free running

counter

IEDG1

(Control register 1) CR1

(Control register 2) CR2

ICF2

ICF1 000

(Status register) SR

IEDG2

ICAP1

ICAP2

Edge Detect

circuit 2

16-bit

IC1R register

Edge Detect

circuit 1

IC2R register

FF01

FF02

FF03

Timer clock

Counter register

ICAPi pin

ICAPi flag

ICAPi register

Note: The rising edge is the active edge.

Note: 1 After reading the ICiHR register, transfer of input capture data is inhibited and ICFi will never

be set until the ICiLR register is also read.

2 The ICiR register contains the free running counter value which corresponds to the most

recent input capture.

3 The two input capture functions can be used together even if the timer also uses the two

output compare functions.

4 In One pulse mode and PWM mode only Input Capture 2 can be used.

5 The alternate inputs (ICAP1 and ICAP2) are always directly connected to the timer. So any

transitions on these pins activates the input capture function. Moreover if one of the ICAPi pins is configured as an input and the second one as an output, an interrupt can be generated if the user toggles the output pin and if the ICIE bit is set. This can be avoided if the input capture function i is disabled by reading the ICiHR (see note 1).

6 The TOF bit can be used with interrupt generation in order to measure events that go

beyond the timer range (FFFFh).

Figure 29. Input capture block diagram

Figure 30. Input capture timing diagram

54/139

ST7260xx Watchdog timer (WDG)

Δ OCiR =

Δt * f

CPU

PRESC

Output compare

In this section, the index, i, may be 1 or 2 because there are two output compare functions in the 16-bit timer.

This function can be used to control an output waveform or indicate when a period of time has elapsed.

When a match is found between the Output Compare register and the free running counter, the output compare function:

– Assigns pins with a programmable value if the OCiE bit is set – Sets a flag in the status register – Generates an interrupt if enabled

Two 16-bit registers Output Compare register 1 (OC1R) and Output Compare register 2 (OC2R) contain the value to be compared to the counter register each timer clock cycle.

Table 27. Output compare byte distribution

OCiR OCiHR OCiLR

These registers are readable and witable and are not affected by the timer hardware. A reset event changes the OC

iR value to 8000h.

Timing resolution is one count of the free running counter: (f

/CC[1:0]).

CPU

Procedure

To use the Output Compare function, select the following in the CR2 register:

● Set the OCiE bit if an output is needed then the OCMPi pin is dedicated to the output

compare i signal.

● Select the timer clock (CC[1:0]) (see Tab le 3 2 ).

And select the following in the CR1 register:

● Select the OLVLi bit to applied to the OCMPi pins after the match occurs.

● Set the OCIE bit to generate an interrupt if it is needed.

When a match is found between OCRi register and CR register:

● OCFi bit is set

● The OCMPi pin takes OLVLi bit value (OCMPi pin latch is forced low during reset)

● A timer interrupt is generated if the OCIE bit is set in the CR1 register and the I bit is

cleared in the CC register (CC).

The OC

iR register value required for a specific timing application can be calculated using

the following formula:

Where:

Δt = Output compare period (in seconds) f

= CPU clock frequency (in hertz)

CPU

PRESC

= Timer prescaler factor (2, 4 or 8 depending on CC[1:0] bits; see Ta bl e 3 2 )

55/139

Watchdog timer (WDG) ST7260xx

Δ OCiR = Δt * f

EXT

If the timer clock is an external clock, the formula is:

Where:

Δt = Output compare period (in seconds) f

= External timer clock frequency (in hertz)

EXT

Clearing the output compare interrupt request (that is, clearing the OCFi bit) is done by:

1. Reading the SR register while the OCFi bit is set.

2. An access (read or write) to the OCiLR register.

The following procedure is recommended to prevent the OCFi bit from being set between the time it is read and the write to the OC

● Write to the OCiHR register (further compares are inhibited).

● Read the SR register (first step of the clearance of the OCFi bit, which may be already

iR register:

set).

● Write to the OCiLR register (enables the output compare function and clears the OCFi

bit).

Note: 1 After a processor write cycle to the OCiHR register, the output compare function is inhibited

until the OCiLR register is also written.

2 If the OCiE bit is not set, the OCMPi pin is a general I/O port and the OLVLi bit will not

appear when a match is found but an interrupt could be generated if the OCIE bit is set.

3 In both internal and external clock modes, OCFi and OCMPi are set while the counter value

equals the OCiR register value (see Figure 32 on page 57 for an example with f

Figure 33 on page 57 for an example with f

/4). This behavior is the same in OPM or

CPU

/2 and

PWM mode.

4 The output compare functions can be used both for generating external events on the

OCMPi pins even if the input capture mode is also used.

5 The value in the 16-bit OC

iR register and the OLVi bit should be changed after each

successful comparison in order to control an output waveform or establish a new elapsed timeout.

Forced output compare capability

When the FOLVi bit is set by software, the OLVLi bit is copied to the OCMPi pin. The OLVi bit has to be toggled in order to toggle the OCMPi pin when it is enabled (OCiE bit = 1). The OCFi bit is then not set by hardware, and thus no interrupt request is generated.

The FOLVLi bits have no effect in both one pulse mode and PWM mode.

56/139

ST7260xx Watchdog timer (WDG)

Output compare

16-bit

circuit

OC1R register

16-bit free running counter

OC1E CC0CC1OC2E

OLVL1OLVL2OCIE

(Control Register 1) CR1

(Control Register 2) CR2

000OCF2OCF1

(Status register) SR

16-bit

OCMP1

OCMP2

Latch

OC2R register

FOLV2FOLV1

Internal CPU clock

Timer clock

Counter register

Output Compare register i (OCRi)

Output Compare flag i (OCFi)

OCMPi pin (OLVLi =1)

2ED3

2ED0 2ED1 2ED2

2ED3

2ED42ECF

Internal CPU clock

Timer clock

Counter register

Output Compare register i (OCRi)

2ED3

2ED0 2ED1 2ED2

2ED3

2ED42ECF

Output Compare flag i (OCFi)

OCMPi pin (OLVLi =1)

Figure 31. Output compare block diagram

Figure 32. Output compare timing diagram, f

Figure 33. Output compare timing diagram, f

TIMER

CPU

57/139

Watchdog timer (WDG) ST7260xx

event occurs

counter =

OC1R

OCMP1 = OLVL1

When

on ICAP1

OCMP1 = OLVL2

Counter is reset

to FFFCh

ICF1 bit is set

ICR1 = Counter

One pulse mode

One Pulse mode enables the generation of a pulse when an external event occurs. This mode is selected via the OPM bit in the CR2 register.

The one pulse mode uses the Input Capture1 function and the Output Compare1 function.

Procedure

To use One Pulse mode:

1. Load the OC1R register with the value corresponding to the length of the pulse (see the

formula below).

2. Select the following in the CR1 register:

– Using the OLVL1 bit, select the level to be applied to the OCMP1 pin after the

pulse.

– Using the OLVL2 bit, select the level to be applied to the OCMP1 pin during the

pulse.

– Select the edge of the active transition on the ICAP1 pin with the IEDG1 bit (the

ICAP1 pin must be configured as floating input).

3. Select the following in the CR2 register:

– Set the OC1E bit, the OCMP1 pin is then dedicated to the Output Compare 1

function. – Set the OPM bit. – Select the timer clock CC[1:0] (see Ta bl e 3 2).

Figure 34. One pulse mode cycle

Then, on a valid event on the ICAP1 pin, the counter is initialized to FFFCh and OLVL2 bit is loaded on the OCMP1 pin, the ICF1 bit is set and the value FFFDh is loaded in the IC1R register.

Because the ICF1 bit is set when an active edge occurs, an interrupt can be generated if the ICIE bit is set.

Clearing the Input Capture interrupt request (that is, clearing the ICFi bit) is done in two steps:

1. Reading the SR register while the ICFi bit is set.

2. An access (read or write) to the ICiLR register.

58/139

ST7260xx Watchdog timer (WDG)

OCiR value =

* fCPU

PRESC

- 5

OCiR = t * f

EXT

- 5

Counter

FFFC FFFD FFFE 2ED0 2ED1 2ED2

2ED3

FFFC FFFD

OLVL2

OLVL2OLVL1

ICAP1

OCMP1

Compare1

01F8

2ED3

IC1R

The OC1R register value required for a specific timing application can be calculated using the following formula:

Where:

t = Pulse period (in seconds) f

= CPU clock frequnency (in hertz)

CPU

PRESC = Timer prescaler factor (2, 4 or 8 depending on the CC[1:0] bits; see Ta bl e 3 2)

If the timer clock is an external clock the formula is:

Where:

t = Pulse period (in seconds) f

EXT

= External timer clock frequency (in hertz)

When the value of the counter is equal to the value of the contents of the OC1R register, the OLVL1 bit is output on the OCMP1 pin (see Figure 35).

Note: 1 The OCF1 bit cannot be set by hardware in one pulse mode but the OCF2 bit can generate

an Output Compare interrupt.

2 When the Pulse Width Modulation (PWM) and One Pulse Mode (OPM) bits are both set, the

PWM mode is the only active one.

3 If OLVL1 = OLVL2 a continuous signal will be seen on the OCMP1 pin.

4 The ICAP1 pin can not be used to perform input capture. The ICAP2 pin can be used to

perform input capture (ICF2 can be set and IC2R can be loaded) but the user must take care that the counter is reset each time a valid edge occurs on the ICAP1 pin and ICF1 can also generates interrupt if ICIE is set.

5 When one pulse mode is used OC1R is dedicated to this mode. Nevertheless OC2R and

OCF2 can be used to indicate a period of time has been elapsed but cannot generate an output waveform because the level OLVL2 is dedicated to the one pulse mode.

Figure 35. One Pulse mode timing example

(1)

1. IEDG1 = 1, OC1R = 2ED0h, OLVL1 = 0, OLVL2 = 1

59/139

Watchdog timer (WDG) ST7260xx

Counter

34E2

34E2 FFFC

OLVL2

OLVL1

OCMP1

compare2 compare1 compare2

FFFC FFFD FFFE

2ED0

2ED1

2ED2

Figure 36. Pulse width modulation mode timing example with two output compare

functions

1. OC1R = 2ED0h, OC2R = 34E2, OLVL1 = 0, OLVL2 = 1

2. On timers with only one Output Compare register, a fixed frequency PWM signal can be generated using the output compare and the counter overflow to define the pulse length.

(1)(2)

Pulse width modulation mode

Pulse Width Modulation (PWM) mode enables the generation of a signal with a frequency and pulse length determined by the value of the OC1R and OC2R registers.

Pulse Width Modulation mode uses the complete Output Compare 1 function plus the OC2R register, and so this functionality can not be used when PWM mode is activated.

In PWM mode, double buffering is implemented on the output compare registers. Any new values written in the OC1R and OC2R registers are taken into account only at the end of the PWM period (OC2) to avoid spikes on the PWM output pin (OCMP1).

Procedure

To use Pulse Width Modulation mode:

1. Load the OC2R register with the value corresponding to the period of the signal using

the formula below.

2. Load the OC1R register with the value corresponding to the period of the pulse if

(OLVL1 = 0 and OLVL2 = 1) using the formula in the opposite column.

3. Select the following in the CR1 register:

– Using the OLVL1 bit, select the level to be applied to the OCMP1 pin after a

successful comparison with the OC1R register.

– Using the OLVL2 bit, select the level to be applied to the OCMP1 pin after a

successful comparison with the OC2R register.

4. Select the following in the CR2 register:

– Set OC1E bit: the OCMP1 pin is then dedicated to the output compare 1 function. – Set the PWM bit. – Select the timer clock (CC[1:0]) (see Ta bl e 3 2).

60/139

ST7260xx Watchdog timer (WDG)

counter

OCMP1 = OLVL2

counter

= OC2R

OCMP1 = OLVL1

When

= OC1R

counter is reset

to FFFCh

ICF1 bit is set

OCiR value =

* fCPU

PRESC

- 5

OCiR = t * f

EXT

- 5

Figure 37. Pulse width modulation cycle

If OLVL1 = 1 and OLVL2 = 0, the length of the positive pulse is the difference between the OC2R and OC1R registers.

If OLVL1 = OLVL2, a continuous signal will be seen on the OCMP1 pin.

The OC1R register value required for a specific timing application can be calculated using the following formula:

Where:

t = Signal or pulse period (in seconds) f

= CPU clock frequnency (in hertz)

CPU

PRESC = Timer prescaler factor (2, 4 or 8 depending on the CC[1:0] bits; see Ta bl e 3 2)

If the timer clock is an external clock the formula is:

Where:

t = Signal or pulse period (in seconds) f

EXT

= External timer clock frequency (in hertz)

The Output Compare 2 event causes the counter to be initialized to FFFCh (see Figure 36).

Note: 1 After a write instruction to the OCiHR register, the output compare function is inhibited until

the OCiLR register is also written.

2 The OCF1 and OCF2 bits cannot be set by hardware in PWM mode therefore the Output

Compare interrupt is inhibited.

3 The ICF1 bit is set by hardware when the counter reaches the OC2R value and can produce

a timer interrupt if the ICIE bit is set and the I bit is cleared.

4 In PWM mode the ICAP1 pin can not be used to perform input capture because it is

disconnected to the timer. The ICAP2 pin can be used to perform input capture (ICF2 can be set and IC2R can be loaded) but the user must take care that the counter is reset each period and ICF1 can also generates interrupt if ICIE is set.

5 When the Pulse Width Modulation (PWM) and One Pulse Mode (OPM) bits are both set, the

PWM mode is the only active one.

61/139

Watchdog timer (WDG) ST7260xx

12.4.4 Low power modes

Table 28. Effect of low power modes on 16-bit timer

Mode Description

Wait

Halt

12.4.5 Interrupts

Table 29. 16-bit timer interrupt control/wake-up capability

Interrupt event Event flag Enable control bit Exit from Wait Exit from Halt

Input Capture 1 event/counter reset in PWM mode

Input Capture 2 event ICF2

Output Compare 1 event (not available in PWM mode)

Output Compare 2 event (not available in PWM mode)

No effect on 16-bit timer. Timer interrupts cause the device to exit from Wait mode.

16-bit timer registers are frozen. In Halt mode, the counter stops counting until Halt mode is exited. Counting resumes

from the previous count when the MCU is woken up by an interrupt with Exit from Halt mode capability or from the counter reset value when the MCU is woken up by a reset.

If an input capture event occurs on the ICAPi pin, the input capture detection circuitry is armed. Consequently, when the MCU is woken up by an interrupt with Exit from Halt mode capability, the ICFi bit is set, and the counter value present when exiting from Halt mode is captured into the ICiR register.

(1)

ICF1

ICIE

OCF1

Ye s N o

OCIE

OCF2

Timer Overflow event TOF TOIE

1. The 16-bit timer interrupt events are connected to the same interrupt vector (see Section 8: Interrupts). These events generate an interrupt if the corresponding Enable Control bit is set and the interrupt mask in the CC register is reset (RIM instruction).

62/139

ST7260xx Watchdog timer (WDG)

12.4.6 Summary of timer modes

Table 30. Summary of timer modes

Timer resources

Mode

Input

capture 1

Input

capture 2

Output

compare 1

Output

compare 2

Input Capture (1 and/or 2)

Ye s Ye s Ye s Ye s

Output Compare (1 and/or 2)

One Pulse mode

Not recommended

PWM mode Not recommended

1. See note 4 in One pulse mode on page 58.

2. See note 5 in One pulse mode on page 58.

3. See note 4 in Pulse width modulation mode on page 60.

(1)

(3)

Partially

(2)

12.4.7 16-bit timer registers

Each timer is associated with three control and status registers, and with six pairs of data registers (16-bit values) relating to the two input captures, the two output compares, the counter and the alternate counter.

Control Register 1 (CR1)

CR1 Reset value: 0000 0000 (00h)

76543210

ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1

R/W R/W R/W R/W R/W R/W R/W R/W

Table 31. CR1 register description

Bit Name Function

Input Capture Interrupt Enable

7ICIE

6OCIE

5TOIE

0: Interrupt is inhibited. 1: A timer interrupt is generated whenever the ICF1 or ICF2 bit of the SR register is set.

Output Compare Interrupt Enable

0: Interrupt is inhibited. 1: A timer interrupt is generated whenever the OCF1 or OCF2 bit of the SR register is set.

Timer Overflow Interrupt Enable

0: Interrupt is inhibited. 1: A timer interrupt is enabled whenever the TOF bit of the SR register is set.

63/139

Watchdog timer (WDG) ST7260xx

Table 31. CR1 register description (continued)

Bit Name Function

Forced Output compare 2

This bit is set and cleared by software.

4FOLV2

3FOLV1

2OLVL2

1IEDG1

0OLVL1

0: No effect on the OCMP2 pin. 1: Forces the OLVL2 bit to be copied to the OCMP2 pin, if the OC2E bit is set and even if there is no successful comparison.

Forced Output compare 1

This bit is set and cleared by software. 0: No effect on the OCMP1 pin. 1: Forces OLVL1 to be copied to the OCMP1 pin, if the OC1E bit is set and even if there is no successful comparison.

Output Level 2

This bit is copied to the OCMP2 pin whenever a successful comparison occurs with the OC2R register and OCxE is set in the CR2 register. This value is copied to the OCMP1 pin in One Pulse mode and Pulse Width modulation mode.

Input Edge 1

This bit determines which type of level transition on the ICAP1 pin will trigger the capture. 0: A falling edge triggers the capture. 1: A rising edge triggers the capture.

Output Level 1

The OLVL1 bit is copied to the OCMP1 pin whenever a successful comparison occurs with the OC1R register and the OC1E bit is set in the CR2 register.

Control Register 2 (CR2)

CR2 Reset value: 0000 0000 (00h)

76543210

OC1E OC2E OPM PWM CC[1:0] IEDG2 EXEDG

R/W R/W R/W R/W R/W R/W R/W

Table 32. CR2 register description

Bit Name Function

Output Compare 1 Pin Enable This bit is used only to output the signal from the timer on the OCMP1 pin (OLV1 in

Output Compare mode, both OLV1 and OLV2 in PWM and One-Pulse mode).

7OCIE

6OC2E

Whatever the value of the OC1E bit, the Output Compare 1 function of the timer remains active. 0: OCMP1 pin alternate function disabled (I/O pin free for general-purpose I/O). 1: OCMP1 pin alternate function enabled.

Output Compare 2 Pin Enable This bit is used only to output the signal from the timer on the OCMP2 pin (OLV2 in

Output Compare mode). Whatever the value of the OC2E bit, the Output Compare 2 function of the timer remains active. 0: OCMP2 pin alternate function disabled (I/O pin free for general-purpose I/O). 1: OCMP2 pin alternate function enabled.

64/139

ST7260xx Watchdog timer (WDG)

Table 32. CR2 register description (continued)

Bit Name Function

One Pulse Mode

0: One Pulse mode is not active.

5OPM

4PWM

3:2 CC[1:0]

1IEDG2

0 EXEDG

1: One Pulse mode is active, the ICAP1 pin can be used to trigger one pulse on the OCMP1 pin; the active transition is given by the IEDG1 bit. The length of the generated pulse depends on the contents of the OC1R register.

Pulse Width Modulation

0: PWM mode is not active. 1: PWM mode is active, the OCMP1 pin outputs a programmable cyclic signal; the length of the pulse depends on the value of OC1R register; the period depends on the value of OC2R register.

Clock Control

The timer clock mode depends on these bits. 00: Timer clock = f 01: Timer clock = f 10: Timer clock = f

CPU CPU CPU

/4 /2 /8

11: Timer clock = external clock (where available)

Note: If the external clock pin is not available, programming the external clock configuration stops the counter.

Input Edge 2

This bit determines which type of level transition on the ICAP2 pin will trigger the capture. 0: A falling edge triggers the capture. 1: A rising edge triggers the capture.

External Clock Edge

This bit determines which type of level transition on the external clock pin EXTCLK will trigger the counter register. 0: A falling edge triggers the counter register. 1: A rising edge triggers the counter register.

Control/Status Register (CSR)

CSR Reset value: xxxx x0xx (xxh)

76543210

ICF1 OCF1 TOF ICF2 OCF2 TIMD Reserved

RO RO RO RO RO R/W -

Table 33. CSR register description

Bit Name Function

Input Capture Flag 1

0: No Input Capture (reset value).

7ICF1

1: An Input Capture has occurred on the ICAP1 pin or the counter has reached the OC2R value in PWM mode. To clear this bit, first read the SR register, then read or write the low byte of the IC1R (IC1LR) register.

65/139

Watchdog timer (WDG) ST7260xx

Table 33. CSR register description (continued)

Bit Name Function

Output Compare Flag 1

0: No match (reset value).

6OCF1

5TOF

4ICF2

3OCF2

2TIMD

1:0 - Reserved, must be kept cleared.

1: The content of the free running counter has matched the content of the OC1R register. To clear this bit, first read the SR register, then read or write the low byte of the OC1R (OC1LR) register.

Timer Overflow Flag

0: No timer overflow (reset value). 1: The free running counter rolled over from FFFFh to 0000h. To clear this bit, first read the SR register, then read or write the low byte of the CR (CLR) register.

Note: Reading or writing the ACLR register does not clear TOF.

Input Capture Flag 2

0: No input capture (reset value). 1: An Input Capture has occurred on the ICAP2 pin. To clear this bit, first read the SR register, then read or write the low byte of the IC2R (IC2LR) register.

Output Compare Flag 2

0: No match (reset value). 1: The content of the free running counter has matched the content of the OC2R register. To clear this bit, first read the SR register, then read or write the low byte of the OC2R (OC2LR) register.

Timer Disable

This bit is set and cleared by software. When set, it freezes the timer prescaler and counter and disabled the output functions (OCMP1 and OCMP2 pins) to reduce power consumption. Access to the timer registers is still available, allowing the timer configuration to be changed, or the counter reset, while it is disabled. 0: Timer enabled. 1: Timer prescaler, counter and outputs disabled.

Input capture 1 high register (IC1HR)

This is an 8-bit register that contains the high part of the counter value (transferred by the input capture 1 event).

IC1HR Reset value: undefined

76543210

MSB LSB

RO RO RO RO RO RO RO RO

66/139

ST7260xx Watchdog timer (WDG)

Input capture 1 low register (IC1LR)

This is an 8-bit register that contains the low part of the counter value (transferred by the input capture 1 event).

IC1LR Reset value: undefined

76543210

MSB LSB

RO RO RO RO RO RO RO RO

Output compare 1 high register (OC1HR)

This is an 8-bit register that contains the high part of the value to be compared to the CHR register.

OC1HR Reset value: 1000 0000 (80h)

76543210

MSB LSB

R/W R/W R/W R/W R/W R/W R/W R/W

Output compare 1 low register (OC1LR)

This is an 8-bit register that contains the low part of the value to be compared to the CLR register.

OC1LR Reset value: 0000 0000 (00h)

76543210

MSB LSB

R/W R/W R/W R/W R/W R/W R/W R/W

Output compare 2 high register (OC2HR)

This is an 8-bit register that contains the high part of the value to be compared to the CHR register.

OC2HR Reset value: 1000 0000 (80h)

76543210

MSB LSB

R/W R/W R/W R/W R/W R/W R/W R/W

67/139

Watchdog timer (WDG) ST7260xx

Output compare 2 low register (OC2LR)

This is an 8-bit register that contains the low part of the value to be compared to the CLR register.

OC2LR Reset value: 0000 0000 (00h)

76543210

MSB LSB

R/W R/W R/W R/W R/W R/W R/W R/W

Counter high register (CHR)

This is an 8-bit register that contains the high part of the counter value.

CHR Reset value: 1111 1111 (FFh)

76543210

MSB LSB

RO RO RO RO RO RO RO RO

Counter low register (CLR)

This is an 8-bit register that contains the low part of the counter value. A write to this register resets the counter. An access to this register after accessing the CSR register clears the TOF bit.

CLR Reset value: 1111 1100 (FCh)

76543210

MSB LSB

RO RO RO RO RO RO RO RO

Alternate counter high register (ACHR)

This is an 8-bit register that contains the high part of the counter value.

ACHR Reset value: 1111 1111 (FFh)

76543210

MSB LSB

RO RO RO RO RO RO RO RO

68/139

ST7260xx Watchdog timer (WDG)

Alternate counter low register (ACLR)

This is an 8-bit register that contains the low part of the counter value. A write to this register resets the counter. An access to this register after an access to CSR register does not clear the TOF bit in the CSR register.

ACLR Reset value: 1111 1100 (FCh)

76543210

MSB LSB

RO RO RO RO RO RO RO RO

Input capture 2 high register (IC2HR)

This is an 8-bit register that contains the high part of the counter value (transferred by the Input Capture 2 event).

1C2HR Reset value: undefined

76543210

MSB LSB

RO RO RO RO RO RO RO RO

Input capture 2 low register (IC2LR)

This is an 8-bit register that contains the low part of the counter value (transferred by the Input Capture 2 event).

1C2LR Reset value: undefined

76543210

MSB LSB

RO RO RO RO RO RO RO RO

69/139

Watchdog timer (WDG) ST7260xx

Table 34. 16-bit timer register map and reset values

Address

(Hex.)

label

CR1 Reset value

CR2 Reset value

CSR Reset value

IC1HR Reset value

IC1LR Reset value

OC1HR Reset value

OC1LR Reset value

CHR Reset value

CLR Reset value

ACHR Reset value

ACLR Reset value

76543210

ICIE

OC1E0OC2E

ICF1

OCIE

OCF1

TOIE0FOLV20FOLV10OLVL20IEDG10OLVL1

OPM

TOF

MSB

xxxxxxx

MSB

xxxxxxx

MSB

1000000

MSB

0000000

MSB

1111111

MSB

1111110

MSB

1111111

MSB

1111110

PWM

ICF2

CC1

CC00IEDG20EXEDG

OCF2xTIMD

LSB

IC2HR Reset value

IC2LR Reset value

OC2HR Reset value

OC2LR Reset value

MSB

xxxxxxx

MSB

xxxxxxx

MSB

1000000

MSB

0000000

LSB

70/139

ST7260xx Serial communications interface (SCI)

13 Serial communications interface (SCI)

13.1 Introduction

The Serial Communications Interface (SCI) offers a flexible means of full-duplex data exchange with external equipment requiring an industry standard NRZ asynchronous serial data format. The SCI offers a very wide range of baud rates using two baud rate generator systems.

13.2 Main features

● Full duplex, asynchronous communications

● NRZ standard format (Mark/Space)

● Independently programmable transmit and receive baud rates up to 250K baud.

● Programmable data word length (8 or 9 bits)

● Receive buffer full, Transmit buffer empty and End of Transmission flags

● Two receiver wake-up modes:

– Address bit (MSB) – Idle line

● Muting function for multiprocessor configurations

● Separate enable bits for Transmitter and Receiver

● Four error detection flags:

– Overrun error – Noise error –Frame error – Parity error

● Six interrupt sources with flags:

– Transmit data register empty – Transmission complete – Receive data register full – Idle line received – Overrun error detected – Parity error

● Parity control:

– Transmits parity bit – Checks parity of received data byte

● Reduced power consumption mode

71/139

Serial communications interface (SCI) ST7260xx

13.2.1 General description

The interface is externally connected to another device by two pins (see Figure 39):

● TDO: Transmit Data Output. When the transmitter and the receiver are disabled, the

output pin returns to its I/O port configuration. When the transmitter and/or the receiver are enabled and nothing is to be transmitted, the TDO pin is at high level.

● RDI: Receive Data Input is the serial data input. Oversampling techniques are used for

data recovery by discriminating between valid incoming data and noise.

Through these pins, serial data is transmitted and received as frames comprising:

● An Idle Line prior to transmission or reception

● A start bit

● A data word (8 or 9 bits) least significant bit first

● A Stop bit indicating that the frame is complete.

This interface uses two types of baud rate generator:

● A conventional type for commonly-used baud rates.

72/139

ST7260xx Serial communications interface (SCI)

WAKE

UNIT

RECEIVER

CONTROL

TRANSMIT

CONTROL

TDRE TC RDRF IDLE OR NF FE PE

SCI

CONTROL

INTERRUPT

CR1

R8 T8 SCID M WAKE PCE PS PIE

Received Data Register (RDR)

Received Shift Register

Read

Transmit Data Register (TDR)

Transmit Shift Register

Write

RDI

TDO

(DATA REGISTER) DR

TRANSMITTER

CLOCK

RECEIVER

CLOCK

RECEIVER RATE

TRANSMITTER RATE

BRR

SCP1

CPU

CONTROL

SCP0

SCT2

SCT1 SCT0 SCR2 SCR1SCR0

/PR

/16

BAUD RATE GENERATOR

SBKRWURETEILIERIETCIETIE

CR2

Figure 38. SCI block diagram

13.2.2 Functional description

The block diagram of the Serial Control Interface, is shown in Figure 38. It contains 6 dedicated registers:

● Two control registers (SCICR1 & SCICR2)

● A status register (SCISR)

● A baud rate register (SCIBRR)

Refer to the register descriptions in Section 13.3 for the definitions of each bit.

73/139

Serial communications interface (SCI) ST7260xx

Bit0

Bit1

Bit2

Bit3

Bit4

Bit5

Bit6

Bit7

Bit8

Start

Bit

Stop

Bit

Start

Bit

Idle Frame

Bit0

Bit1

Bit2

Bit3

Bit4

Bit5

Bit6

Bit7

Start

Bit

Stop

Bit

Start

Bit

Start

Bit

Idle Frame

Start

Bit

9-bit Word length (M bit is set)

8-bit Word length (M bit is reset)

Possible

Parity

Bit

Possible

Parity

Bit

Break Frame

Start

Bit

Extra

’1’

Data Frame

Break Frame

Start

Bit

Extra

’1’

Data Frame

Next Data Frame

Serial data format

Word length may be selected as being either 8 or 9 bits by programming the M bit in the SCICR1 register (see Figure 38).

The TDO pin is in low state during the start bit.

The TDO pin is in high state during the stop bit.

An Idle character is interpreted as an entire frame of “1”s followed by the start bit of the next frame which contains data.

A Break character is interpreted on receiving “0”s for some multiple of the frame period. At the end of the last break frame the transmitter inserts an extra “1” bit to acknowledge the start bit.

Transmission and reception are driven by their own baud rate generator.

Figure 39. Word length programming

Transmitter

The transmitter can send data words of either 8 or 9 bits depending on the M bit status. When the M bit is set, word length is 9 bits and the 9th bit (the MSB) has to be stored in the T8 bit in the SCICR1 register.

Character Transmission

During an SCI transmission, data shifts out least significant bit first on the TDO pin. In this mode, the SCIDR register consists of a buffer (TDR) between the internal bus and the transmit shift register (see Figure 38).

74/139

ST7260xx Serial communications interface (SCI)

Procedure

● Select the M bit to define the word length.

● Select the desired baud rate using the SCIBRR and the SCIETPR registers.

● Set the TE bit to assign the TDO pin to the alternate function and to send a idle frame

as first transmission.

● Access the SCISR register and write the data to send in the SCIDR register (this

sequence clears the TDRE bit). Repeat this sequence for each data to be transmitted.

Clearing the TDRE bit is always performed by the following software sequence:

1. An access to the SCISR register

2. A write to the SCIDR register

The TDRE bit is set by hardware and it indicates:

● The TDR register is empty.

● The data transfer is beginning.

● The next data can be written in the SCIDR register without overwriting the previous

data.

This flag generates an interrupt if the TIE bit is set and the I bit is cleared in the CCR register.

When a transmission is taking place, a write instruction to the SCIDR register stores the data in the TDR register and which is copied in the shift register at the end of the current transmission.

When no transmission is taking place, a write instruction to the SCIDR register places the data directly in the shift register, the data transmission starts, and the TDRE bit is immediately set.

When a frame transmission is complete (after the stop bit or after the break frame) the TC bit is set and an interrupt is generated if the TCIE is set and the I bit is cleared in the CCR register.

Clearing the TC bit is performed by the following software sequence:

1. An access to the SCISR register

2. A write to the SCIDR register

Note: The TDRE and TC bits are cleared by the same software sequence.

Break characters

Setting the SBK bit loads the shift register with a break character. The break frame length depends on the M bit (see Figure 39).

As long as the SBK bit is set, the SCI send break frames to the TDO pin. After clearing this bit by software the SCI insert a logic 1 bit at the end of the last break frame to guarantee the recognition of the start bit of the next frame.

Idle characters

Setting the TE bit drives the SCI to send an idle frame before the first data frame.

Clearing and then setting the TE bit during a transmission sends an idle frame after the current word.

75/139

Serial communications interface (SCI) ST7260xx

Note: Resetting and setting the TE bit causes the data in the TDR register to be lost. Therefore the

best time to toggle the TE bit is when the TDRE bit is set i.e. before writing the next byte in the SCIDR.

Receiver

The SCI can receive data words of either 8 or 9 bits. When the M bit is set, word length is 9 bits and the MSB is stored in the R8 bit in the SCICR1 register.

Character reception

During a SCI reception, data shifts in least significant bit first through the RDI pin. In this mode, the SCIDR register consists or a buffer (RDR) between the internal bus and the received shift register (see <Blue HT>Figure 38).

Procedure

● Select the M bit to define the word length.

● Select the desired baud rate using the SCIBRR and the SCIERPR registers.

● Set the RE bit, this enables the receiver which begins searching for a start bit.

When a character is received:

● The RDRF bit is set. It indicates that the content of the shift register is transferred to the

RDR.

● An interrupt is generated if the RIE bit is set and the I bit is cleared in the CCR register.

● The error flags can be set if a frame error, noise or an overrun error has been detected

during reception.

Clearing the RDRF bit is performed by the following software sequence done by:

1. An access to the SCISR register

2. A read to the SCIDR register

The RDRF bit must be cleared before the end of the reception of the next character to avoid an overrun error.

Break Character

When a break character is received, the SCI handles it as a framing error.

Idle Character

When a idle frame is detected, there is the same procedure as a data received character plus an interrupt if the ILIE bit is set and the I bit is cleared in the CCR register.

Overrun Error

An overrun error occurs when a character is received when RDRF has not been reset. Data can not be transferred from the shift register to the RDR register as long as the RDRF bit is not cleared.

When a overrun error occurs:

● The OR bit is set.

● The RDR content will not be lost.

● The shift register will be overwritten.

● An interrupt is generated if the RIE bit is set and the I bit is cleared in the CCR register.

The OR bit is reset by an access to the SCISR register followed by a SCIDR register read operation.

76/139

ST7260xx Serial communications interface (SCI)

Noise error

Oversampling techniques are used for data recovery by discriminating between valid incoming data and noise. Normal data bits are considered valid if three consecutive samples (8th, 9th, 10th) have the same bit value, otherwise the NF flag is set. In the case of start bit detection, the NF flag is set on the basis of an algorithm combining both valid edge detection and three samples (8th, 9th, 10th). Therefore, to prevent the NF flag getting set during start bit reception, there should be a valid edge detection as well as three valid samples.

When noise is detected in a frame:

● The NF flag is set at the rising edge of the RDRF bit.

● Data is transferred from the Shift register to the SCIDR register.

● No interrupt is generated. However this bit rises at the same time as the RDRF bit

which itself generates an interrupt.

The NF flag is reset by a SCISR register read operation followed by a SCIDR register read operation.

During reception, if a false start bit is detected (e.g. 8th, 9th, 10th samples are 011,101,110), the frame is discarded and the receiving sequence is not started for this frame. There is no RDRF bit set for this frame and the NF flag is set internally (not accessible to the user). This NF flag is accessible along with the RDRF bit when a next valid frame is received.

Note: If the application Start Bit is not long enough to match the above requirements, then the NF

Flag may get set due to the short Start Bit. In this case, the NF flag may be ignored by the application software when the first valid byte is received.

Table 35. Frame formats

M bit PCE bit SCI frame

0 0 | SB | 8 bit data | STB |

0 1 | SB | 7-bit data | PB | STB |

1 0 | SB | 9-bit data | STB |

1 1 | SB | 8-bit data PB | STB |

Legend: SB = Start Bit, STB = Stop Bit, PB = Parity Bit

Note: In case of wake up by an address mark, the MSB bit of the data is taken into account and

not the parity bit

Even parity: the parity bit is calculated to obtain an even number of “1s” inside the frame made of the 7 or 8 LSB bits (depending on whether M is equal to 0 or 1) and the parity bit.

Ex: data=00110101; 4 bits set => parity bit will be 0 if even parity is selected (PS bit = 0).

Odd parity: the parity bit is calculated to obtain an odd number of “1s” inside the frame made of the 7 or 8 LSB bits (depending on whether M is equal to 0 or 1) and the parity bit.

Ex: data=00110101; 4 bits set => parity bit will be 1 if odd parity is selected (PS bit = 1).

Transmission mode: If the PCE bit is set then the MSB bit of the data written in the data register is not transmitted but is changed by the parity bit.

Reception mode: If the PCE bit is set then the interface checks if the received data byte has an even number of “1s” if even parity is selected (PS=0) or an odd number of “1s” if odd parity is selected (PS=1). If the parity check fails, the PE flag is set in the SCISR register and an interrupt is generated if PIE is set in the SCICR1 register.

SCI clock tolerance

During reception, each bit is sampled 16 times. The majority of the 8th, 9th and 10th samples is considered as the bit value. For a valid bit detection, all the three samples should have the same value otherwise the noise flag (NF) is set. For example: if the 8th, 9th and 10th samples are 0, 1 and 1 respectively, then the bit value will be “1”, but the Noise Flag bit is be set because the three samples values are not the same.

Consequently, the bit length must be long enough so that the 8th, 9th and 10th samples have the desired bit value. This means the clock frequency should not vary more than 6/16 (37.5%) within one bit. The sampling clock is resynchronized at each start bit, so that when receiving 10 bits (one start bit, 1 data byte, 1 stop bit), the clock deviation must not exceed

3.75%.

Note: The internal sampling clock of the microcontroller samples the pin value on every falling

edge. Therefore, the internal sampling clock and the time the application expects the sampling to take place may be out of sync. For example: If the baud rate is 15.625 kbaud (bit length is 64 µs), then the 8th, 9th and 10th samples will be at 28 µs, 32 µs & 36 µs respectively (the first sample starting ideally at 0µs). But if the falling edge of the internal

79/139

Serial communications interface (SCI) ST7260xx

clock occurs just before the pin value changes, the samples would then be out of sync by ~4 µs. This means the entire bit length must be at least 40 µs (36µs for the 10th sample + 4 µs for synchronization with the internal sampling clock).

Clock deviation causes

The causes which contribute to the total deviation are:

● D

: Deviation due to transmitter error (Local oscillator error of the transmitter or the

TRA

transmitter is transmitting at a different baud rate).

● D

: Error due to the baud rate quantisation of the receiver.

QUANT

: Deviation of the local oscillator of the receiver: This deviation can occur during

REC

the reception of one complete SCI message assuming that the deviation has been compensated at the beginning of the message.

● D

: Deviation due to the transmission line (generally due to the transceivers)

TCL

All the deviations of the system should be added and compared to the SCI clock tolerance:

TRA

+ D

QUANT

+ D

REC

+ D

< 3.75%

TCL

Noise error causes

See also description of Noise error in Receiver on page 76.

Start bit

The noise flag (NF) is set during start bit reception if one of the following conditions occurs:

Note: 1 A valid falling edge is not detected. A falling edge is considered to be valid if the 3

consecutive samples before the falling edge occurs are detected as '1' and, after the falling edge occurs, during the sampling of the 16 samples, if one of the samples numbered 3, 5 or 7 is detected as a “1”.

2 During sampling of the 16 samples, if one of the samples numbered 8, 9 or 10 is detected as

a “1”.

Therefore, a valid Start Bit must satisfy both the above conditions to prevent the Noise Flag getting set.

Data bits

The noise flag (NF) is set during normal data bit reception if the following condition occurs:

● During the sampling of 16 samples, if all three samples numbered 8, 9 and10 are not

the same. The majority of the 8th, 9th and 10th samples is considered as the bit value.

Therefore, a valid Data Bit must have samples 8, 9 and 10 at the same value to prevent the Noise Flag getting set.

80/139

ST7260xx Serial communications interface (SCI)

RDI LINE

Sample clock

12345678910111213 14 15 16

sampled values

One bit time

6/16

7/16

Figure 40. Bit sampling in reception mode

13.2.3 Low power modes

Table 36. Effect of low power modes on SCI

Mode Description

No effect on SCI.

Wait

SCI interrupts cause the device to exit from Wait mode.

SCI registers are frozen.

Halt

In Halt mode, the SCI stops transmitting/receiving until Halt mode is exited.

13.2.4 Interrupts

The SCI interrupt events are connected to the same interrupt vector.

These events generate an interrupt if the corresponding Enable Control bit is set and the interrupt mask in the CC register is reset (RIM instruction).

Table 37. SCI interrupt control/wake-up capability

Interrupt event Event flag Enable control bit Exit from Wait Exit from Halt

Transmit data register empty TDRE TIE Yes No

Transmission complete TC TCIE Yes No

Received data ready to be read RDRF

Overrun error detected OR Yes No

Idle line detected IDLE ILIE Yes No

Parity error PE PIE Yes No

RIE

Ye s N o

81/139

Serial communications interface (SCI) ST7260xx

13.3 Register description

13.3.1 Status register (SCISR)

SCISR Reset value: 1100 0000 (C0h)

76543210

TDRE TC RDRF IDLE OR NF FE PE

RRRRRRRR

Table 38. SCISR register description

Bit Name Function

Transmit Data Register Empty

This bit is set by hardware when the content of the TDR register has been transferred into the shift register. An interrupt is generated if the TIE bit = 1 in the SCICR2

7 TDRE

6TC

5 RDRF

4IDLE

register. It is cleared by a software sequence (an access to the SCISR register followed by a write to the SCIDR register). 0: Data is not transferred to the shift register. 1: Data is transferred to the shift register.

Note: Data will not be transferred to the shift register unless the TDRE bit is cleared.

Transmission Complete

This bit is set by hardware when transmission of a frame containing data is complete. An interrupt is generated if TCIE = 1 in the SCICR2 register. It is cleared by a software sequence (an access to the SCISR register followed by a write to the SCIDR register). 0: Transmission is not complete 1: Transmission is complete

Note: TC is not set after the transmission of a Preamble or a Break.

Received Data Ready Flag

This bit is set by hardware when the content of the RDR register has been transferred to the SCIDR register. An interrupt is generated if RIE = 1 in the SCICR2 register. It is cleared by a software sequence (an access to the SCISR register followed by a read to the SCIDR register). 0: Data is not received 1: Received data is ready to be read

Idle line detect

This bit is set by hardware when a Idle Line is detected. An interrupt is generated if the ILIE = 1 in the SCICR2 register. It is cleared by a software sequence (an access to the SCISR register followed by a read to the SCIDR register). 0: No idle line is detected 1: Idle line is detected

Note: The IDLE bit is not reset until the RDRF bit has itself been set (that is, a new idle line occurs).

82/139

ST7260xx Serial communications interface (SCI)

Table 38. SCISR register description (continued)

Bit Name Function

Overrun error

This bit is set by hardware when the word currently being received in the shift register is ready to be transferred into the RDR register while RDRF = 1. An interrupt is

3OR

2NF

1FE

generated if RIE = 1 in the SCICR2 register. It is cleared by a software sequence (an access to the SCISR register followed by a read to the SCIDR register). 0: No overrun error 1: Overrun error is detected

Note: When this bit is set RDR register content is not lost but the shift register is overwritten.

Noise Flag

This bit is set by hardware when noise is detected on a received frame. It is cleared by a software sequence (an access to the SCISR register followed by a read to the SCIDR register). 0: No noise is detected 1: Noise is detected

Note: This bit does not generate interrupt as it appears at the same time as the RDRF bit which itself generates an interrupt.

Framing Error

This bit is set by hardware when a desynchronization, excessive noise or a break character is detected. It is cleared by a software sequence (an access to the SCISR register followed by a read to the SCIDR register). 0: No framing error is detected 1: Framing error or break character is detected

Note: This bit does not generate interrupt as it appears at the same time as the RDRF bit which itself generates an interrupt. If the word currently being transferred causes both Frame Error and Overrun error, it is transferred and only the OR bit will be set.

0PE

Parity Error

This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by a software sequence (a read to the status register followed by an access to the SCIDR data register). An interrupt is generated if PIE = 1 in the SCICR1 register. 0: No parity error 1: Parity error

83/139

Serial communications interface (SCI) ST7260xx

13.3.2 Control register 1 (SCICR1)

SCICR1 Reset value: x000 0000 (x0h)

76543210

R8 T8 SCID M WAKE PCE PS PIE

R/W R/W R/W R/W R/W R/W R/W R/W

Table 39. SCICR1 register description

Bit Name Function

7R8

6T8

5SCID

3WAKE

2PCE

Receive data bit 8

This bit is used to store the 9th bit of the received word when M = 1.

Transmit data bit 8

This bit is used to store the 9th bit of the transmitted word when M = 1.

Disabled for low power consumption

When this bit is set the SCI prescalers and outputs are stopped and the end of the current byte transfer in order to reduce power consumption.This bit is set and cleared by software. 0: SCI enabled 1: SCI prescaler and outputs disabled

Word length

This bit determines the word length. It is set or cleared by software. 0: 1 Start bit, 8 data bits, 1 Stop bit 1: 1 Start bit, 9 data bits, 1 Stop bit

Note: The M bit must not be modified during a data transfer (both transmission and reception).

Wake-Up method

This bit determines the SCI Wake-Up method, it is set or cleared by software. 0: Idle line 1: Address mark

Parity Control Enable

This bit selects the hardware parity control (generation and detection). When the parity control is enabled, the computed parity is inserted at the MSB position (9th bit if M = 1; 8th bit if M = 0) and parity is checked on the received data. This bit is set and cleared by software. Once it is set, PCE is active after the current byte (in reception and in transmission). 0: Parity control disabled 1: Parity control enabled

84/139

ST7260xx Serial communications interface (SCI)

Table 39. SCICR1 register description (continued)

Bit Name Function

Parity Selection

This bit selects the odd or even parity when the parity generation/detection is

1PS

enabled (PCE bit set). It is set and cleared by software. The parity will be selected after the current byte. 0: Even parity 1: Odd parity

Parity Interrupt Enable

This bit enables the interrupt capability of the hardware parity control when a parity

0PIE

error is detected (PE bit set). It is set and cleared by software. 0: Parity error interrupt disabled 1: Parity error interrupt enabled

13.3.3 Control register 2 (SCICR2)

SCICR2 Reset value: 0000 0000 (00h)

76543210

TIE TCIE RIE ILIE TE RE RWU SBK

R/W R/W R/W R/W R/W R/W R/W R/W

Table 40. SCICR2 register description

Bit Name Function

Transmitter Interrupt Enable

7TIE

This bit is set and cleared by software. 0: Interrupt is inhibited 1: An SCI interrupt is generated whenever TDRE = 1 in the SCISR register.

Transmission Complete Interrupt Enable

6TCIE

This bit is set and cleared by software. 0: Interrupt is inhibited 1: An SCI interrupt is generated whenever TC = 1 in the SCISR register.

Receiver interrupt Enable

This bit is set and cleared by software.

5RIE

0: Interrupt is inhibited 1: An SCI interrupt is generated whenever OR = 1 or RDRF = 1 in the SCISR register.

Idle Line Interrupt Enable

4ILIE

This bit is set and cleared by software. 0: Interrupt is inhibited 1: An SCI interrupt is generated whenever IDLE = 1 in the SCISR register.

85/139

Serial communications interface (SCI) ST7260xx

Table 40. SCICR2 register description (continued)

Bit Name Function

Transmitter Enable

This bit enables the transmitter. It is set and cleared by software. 0: Transmitter is disabled 1: Transmitter is enabled

3TE

2RE

1RWU

0SBK

Notes:

- During transmission, a ‘0’ pulse on the TE bit (‘0’ followed by ‘1’) sends a preamble (Idle line) after the current word.

- When TE is set there is a 1 bit-time delay before the transmission starts.

Caution: The TDO pin is free for general purpose I/O only when the TE and RE bits are both cleared (or if TE is never set).

Receiver Enable

This bit enables the receiver. It is set and cleared by software. 0: Receiver is disabled 1: Receiver is enabled and begins searching for a start bit

Note: Before selecting Mute mode (setting the RWU bit), the SCI must first receive some data, otherwise it cannot function in Mute mode with Wake-Up by Idle line detection.

Receiver Wake-Up

This bit determines if the SCI is in mute mode or not. It is set and cleared by software and can be cleared by hardware when a wake-up sequence is recognized. 0: Receiver in Active mode 1: Receiver in Mute mode

Send Break

This bit set is used to send break characters. It is set and cleared by software. 0: No break character is transmitted. 1: Break characters are transmitted.

Note: If the SBK bit is set to ‘1’ and then to ‘0’, the transmitter will send a Break word at the end of the current word.

13.3.4 Data register (SCIDR)

SCIDR Reset value: undefined (xxh)

76543210

DR7 DR6 DR5 DR4 DR3 DR2 DR1 DR0

R/W R/W R/W R/W R/W R/W R/W R/W

Contains the Received or Transmitted data character, depending on whether it is read from or written to.

The Data register performs a double function (read and write) since it is composed of two registers, one for transmission (TDR) and one for reception (RDR). The TDR register provides the parallel interface between the internal bus and the output shift register (see Figure 38). The RDR register provides the parallel interface between the input shift register and the internal bus (see Figure 38).

86/139

ST7260xx Serial communications interface (SCI)

13.3.5 Baud rate register (SCIBRR)

SCIBRR Reset value: 0000 0000 (00h)

76543210

SCP[1:0] SCT[2:0] SCR[2:0]

R/W R/W R/W

Table 41. SCIBRR register description

Bit Name Function

First SCI Prescaler

These 2 prescaling bits allow several standard clock division ranges.

7:6 SCP[1:0]

5:3 SCT[2:0]

2:0 SCR[2:0]

Table 42. SCI register map and reset values

00: PR prescaling factor = 1 01: PR prescaling factor = 3 10: PR prescaling factor = 4 11: PR prescaling factor = 13

SCI Transmitter rate divisor

These 3 bits, in conjunction with the SCP1 and SCP0 bits, define the total division applied to the bus clock to yield the transmit rate clock in conventional baud rate generator mode. 000: TR dividing factor = 1 001: TR dividing factor = 2 010: TR dividing factor = 4 011: TR dividing factor = 8 100: TR dividing factor = 16 101: TR dividing factor = 32 110: TR dividing factor = 64 111: TR dividing factor = 128

SCI Receiver rate divisor

These 3 bits, in conjunction with the SCP[1:0] bits, define the total division applied to the bus clock to yield the receive rate clock in conventional baud rate generator mode. 000: RR dividing factor = 1 001: RR dividing factor = 2 010: RR dividing factor = 4 011: RR dividing factor = 8 100: RR dividing factor = 16 101: RR dividing factor = 32 110: RR dividing factor = 64 111: RR dividing factor = 128

Address

(Hex.)

Label

SCISR Reset Value

SCIDR Reset Value

76543210

TDRE1TC1RDRF0IDLE

DR7xDR6

DR5xDR4xDR3xDR2xDR1

DR0

87/139

Serial communications interface (SCI) ST7260xx

Table 42. SCI register map and reset values

Address

(Hex.)

Label

SCIBRR Reset Value

SCICR1 Reset Value

SCICR2 Reset Value

76543210

SCP10SCP00SCT2xSCT1xSCT0xSCR2xSCR1xSCR0

TIE0TCIE

SCID

RIE

ILIE

WAKExPCE

RWU0SBK

PIE

88/139

ST7260xx USB interface (USB)

14 USB interface (USB)

14.1 Introduction

The USB Interface implements a low-speed function interface between the USB and the ST7 microcontroller. It is a highly integrated circuit which includes the transceiver, 3.3 voltage regulator, SIE and DMA. No external components are needed apart from the external pull-up on USBDM for low speed recognition by the USB host. The use of DMA architecture allows the endpoint definition to be completely flexible. Endpoints can be configured by software as in or out.

14.2 Main features

● USB specification version 1.1 compliant

● Supports Low-Speed USB protocol

● Two or three Endpoints (including default one) depending on the device (see device

feature list and register map)

● CRC generation/checking, NRZI encoding/decoding and bit-stuffing

● USB Suspend/Resume operations

● DMA data transfers

● On-chip 3.3V regulator

● On-chip USB transceiver

14.3 Functional description

The block diagram in Figure 41, gives an overview of the USB interface hardware.

For general information on the USB, refer to the “Universal Serial Bus Specifications” document available at http//:www.usb.org.

Serial interface engine

The SIE (Serial Interface Engine) interfaces with the USB, via the transceiver.

The SIE processes tokens, handles data transmission/reception, and handshaking as required by the USB standard. It also performs frame formatting, including CRC generation and checking.

Endpoints

The Endpoint registers indicate if the microcontroller is ready to transmit/receive, and how many bytes need to be transmitted.

DMA

When a token for a valid Endpoint is recognized by the USB interface, the related data transfer takes place, using DMA. At the end of the transaction, an interrupt is generated.

Interrupts

By reading the Interrupt Status register, application software can know which USB event has occurred.

89/139

USB interface (USB) ST7260xx

CPU

MEMORY

Transceiver

3.3V Voltage Regulator

SIE

ENDPOINT

DMA

INTERRUPT

Address,

and interrupts

USBDM

USBDP

USBVCC

6 MHz

REGISTERS

data buses

USBGND

Figure 41. USB block diagram

14.4 Register description

14.4.1 DMA address register (DMAR)

DMAR Reset value: undefined (xxh)

76543210

DA15 DA14 DA13 DA12 DA11 DA10 DA9 DA8

R/W R/W R/W R/W R/W R/W R/W R/W

Bits 7:0=DA[15:8] DMA address bits 15-8. Software must write the start address of the DMA memory area whose most significant bits are given by DA15-DA6. The remaining 6 address bits are set by hardware. See the description of the IDR register and Figure 42.

14.4.2 Interrupt/DMA register (IDR)

IDR Reset value: xxxx 0000 (x0h)

76543210

DA7 DA6 EP1 EP0 CNT3 CNT2 CNT1 CNT0

R/W R/W R/W R/W R/W R/W R/W R/W

Bits 7:6 = DA[7:6] DMA address bits 7-6. Software must reset these bits. See the description of the DMAR register and Figure 42.

Bits 5:4 = EP[1:0] Endpoint number (read-only). These bits identify the endpoint which required attention. 00: Endpoint 0 01: Endpoint 1 10: Endpoint 2

90/139

ST7260xx USB interface (USB)

Endpoint 0 RX

Endpoint 0 TX

Endpoint 2 RX

Endpoint 1 TX

000000

000111

001000

001111

010000

010111

011000

011111

DA15-6,000000

Endpoint 1 RX

Endpoint 2 TX

100000

100111

101000

101111

When a CTR interrupt occurs (see register ISTR) the software should read the EP bits to identify the endpoint which has sent or received a packet.

Bits 3:0 = CNT[3:0] Byte count (read only). This field shows how many data bytes have been received during the last data reception.

Note: Not valid for data transmission.

Figure 42. DMA buffers

14.4.3 PID register (PIDR)

PIDR Reset value: xxxx 0000 (x0h)

76543210

TP3TP2000

RRRRRRRR

Bits 7:6 = TP[3:2] Token PID bits 3 & 2. USB token PIDs are encoded in four bits. TP[3:2] correspond to the variable token PID bits 3 & 2.

Note: PID bits 1 & 0 have a fixed value of 01.

When a CTR interrupt occurs (see register ISTR) the software should read the TP3 and TP2 bits to retrieve the PID name of the token received. The USB standard defines TP bits as:

Table 43. TP bits

TP3 TP2 PID name

00 OUT

10 IN

1 1 SETUP

Bits 5:3 Reserved. Forced by hardware to 0.

RX_ SEZ

91/139

RXD 0

USB interface (USB) ST7260xx

Bit 2 = RX_SEZ Received single-ended zero This bit indicates the status of the RX_SEZ transceiver output. 0: No SE0 (single-ended zero) state 1: USB lines are in SE0 (single-ended zero) state

Bit 1 = RXD Received data 0: No K-state 1: USB lines are in K-state

This bit indicates the status of the RXD transceiver output (differential receiver output).

Note: If the environment is noisy, the RX_SEZ and RXD bits can be used to secure the

application. By interpreting the status, software can distinguish a valid End Suspend event from a spurious wake-up due to noise on the external USB line. A valid End Suspend is followed by a Resume or Reset sequence. A Resume is indicated by RXD=1, a Reset is indicated by RX_SEZ=1.

Bit 0 = Reserved. Forced by hardware to 0.

14.4.4 Interrupt status register (ISTR)

ISTR Reset value: 0000 0000 (00h)

76543210

SUSP DOVR CTR ERR IOVR ESUSP RESET SOF

R/W R/W R/W R/W R/W R/W R/W R/W

When an interrupt occurs these bits are set by hardware. Software must read them to determine the interrupt type and clear them after servicing.

Note: These bits cannot be set by software.

Bit 7 = SUSP Suspend mode request. This bit is set by hardware when a constant idle state is present on the bus line for more than 3 ms, indicating a suspend mode request from the USB bus. The suspend request check is active immediately after each USB reset event and its disabled by hardware when suspend mode is forced (FSUSP bit of CTLR register) until the end of resume sequence.

Bit 6 = DOVR DMA over/underrun. This bit is set by hardware if the ST7 processor can’t answer a DMA request in time. 0: No over/underrun detected 1: Over/underrun detected

Bit 5 = CTR Correct Transfer. This bit is set by hardware when a correct transfer operation is performed. The type of transfer can be determined by looking at bits TP3-TP2 in register PIDR. The Endpoint on which the transfer was made is identified by bits EP1-EP0 in register IDR. 0: No Correct Transfer detected 1: Correct Transfer detected

Note: A transfer where the device sent a NAK or STALL handshake is considered not correct (the

host only sends ACK handshakes). A transfer is considered correct if there are no errors in the PID and CRC fields, if the DATA0/DATA1 PID is sent as expected, if there were no data overruns, bit stuffing or framing errors.

Bit 4 = ERR Error. This bit is set by hardware whenever one of the errors listed below has occurred:

92/139

ST7260xx USB interface (USB)

0: No error detected 1: Timeout, CRC, bit stuffing or nonstandard framing error detected

Bit 3 = IOVR Interrupt overrun. This bit is set when hardware tries to set ERR, or SOF before they have been cleared by software. 0: No overrun detected 1: Overrun detected

Bit 2 = ESUSP End suspend mode. This bit is set by hardware when, during suspend mode, activity is detected that wakes the USB interface up from suspend mode.

This interrupt is serviced by a specific vector, in order to wake up the ST7 from HALT mode. 0: No End Suspend detected 1: End Suspend detected

Bit 1 = RESET USB reset. This bit is set by hardware when the USB reset sequence is detected on the bus. 0: No USB reset signal detected 1: USB reset signal detected

Note: The DADDR, EP0RA, EP0RB, EP1RA, EP1RB, EP2RA and EP2RB registers are reset by a

USB reset.

Bit 0 = SOF Start of frame. This bit is set by hardware when a low-speed SOF indication (keep-alive strobe) is seen on the USB bus. It is also issued at the end of a resume sequence. 0: No SOF signal detected 1: SOF signal detected

Note: To avoid spurious clearing of some bits, it is recommended to clear them using a load

instruction where all bits which must not be altered are set, and all bits to be cleared are reset. Avoid read-modify-write instructions like AND , XOR..

14.4.5 Interrupt mask register (IMR)

IMR Reset value: 0000 0000 (00h)

76543210

SUSPM DOVRM CTRM ERRM IOVRM ESUSPM RESETM SOFM

R/W R/W R/W R/W R/W R/W R/W R/W

Bits 7:0 = These bits are mask bits for all interrupt condition bits included in the ISTR. Whenever one of the IMR bits is set, if the corresponding ISTR bit is set, and the I bit in the CC register is cleared, an interrupt request is generated. For an explanation of each bit, please refer to the corresponding bit description in ISTR.

93/139

USB interface (USB) ST7260xx

14.4.6 Control register (CTLR)

CTLR Reset value: 0000 0110 (06h)

76543210

0000RESUMEPDWNFSUSPFRES

R/W R/W R/W R/W R/W R/W R/W R/W

Bits 7:4 = Reserved. Forced by hardware to 0.

Bit 3 = RESUME Resume. This bit is set by software to wake-up the Host when the ST7 is in suspend mode. 0: Resume signal not forced 1: Resume signal forced on the USB bus.

Software should clear this bit after the appropriate delay.

Bit 2 = PDWN Power down. This bit is set by software to turn off the 3.3V on-chip voltage regulator that supplies the external pull-up resistor and the transceiver. 0: Voltage regulator on 1: Voltage regulator off

Note: After turning on the voltage regulator, software should allow at least 3 µs for stabilisation of

the power supply before using the USB interface.

Bit 1 = FSUSP Force suspend mode. This bit is set by software to enter Suspend mode. The ST7 should also be halted allowing at least 600 ns before issuing the HALT instruction. 0: Suspend mode inactive 1: Suspend mode active

When the hardware detects USB activity, it resets this bit (it can also be reset by software).

Bit 0 = FRES Force reset. This bit is set by software to force a reset of the USB interface, just as if a RESET sequence came from the USB. 0: Reset not forced 1: USB interface reset forced.

The USB is held in RESET state until software clears this bit, at which point a “USB-RESET” interrupt will be generated if enabled.

94/139

ST7260xx USB interface (USB)

14.4.7 Device address register (DADDR)

DADDR Reset value: 0000 0000 (00h)

76543210

0 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0

R/W R/W R/W R/W R/W R/W R/W R/W

Bit 7 = Reserved. Forced by hardware to 0.

Bits 6:0 = ADD[6:0] Device address, 7 bits.

Software must write into this register the address sent by the host during enumeration.

Note: This register is also reset when a USB reset is received from the USB bus or forced through

bit FRES in the CTLR register.

14.4.8 Endpoint n register A (EPnRA)

EPnRA Reset value: 0000 xxxx (0xh)

76543210

ST_

OUT

R/W R/W R/W R/W R/W R/W R/W R/W

DTOG

_TX

STAT _TX1

STAT _TX0

TBC3 TBC2 TBC1 TBC0

These registers (EP0RA, EP1RA and EP2RA) are used for controlling data transmission. They are also reset by the USB bus reset.

Note: Endpoint 2 and the EP2RA register are not available on some devices (see device feature

list and register map).

Bit 7 = ST_OUT Status out. This bit is set by software to indicate that a status out packet is expected: in this case, all nonzero OUT data transfers on the endpoint are STALLed instead of being ACKed. When ST_OUT is reset, OUT transactions can have any number of bytes, as needed.

Bit 6 = DTOG_TX Data Toggle, for transmission transfers. It contains the required value of the toggle bit (0=DATA0, 1=DATA1) for the next transmitted data packet. This bit is set by hardware at the reception of a SETUP PID. DTOG_TX toggles only when the transmitter has received the ACK signal from the USB host. DTOG_TX and also DTOG_RX (see EPnRB) are normally updated by hardware, at the receipt of a relevant PID. They can be also written by software.

Bits 5:4 = STAT_TX[1:0] Status bits, for transmission transfers. These bits contain the information about the endpoint status, which are listed below:

95/139

USB interface (USB) ST7260xx

Table 44. STAT_TX bits

STAT_TX1 STAT_TX0 Meaning

11VAL ID: this endpoint is enabled for transmission.

DISABLED: transmission transfers cannot be

executed.

STALL: the endpoint is stalled and all transmission

requests result in a STALL handshake.

NAK: the endpoint is naked and all transmission

requests result in a NAK handshake.

These bits are written by software. Hardware sets the STAT_TX bits to NAK when a correct transfer has occurred (CTR=1) related to a IN or SETUP transaction addressed to this endpoint; this allows the software to prepare the next set of data to be transmitted.

Bits 3:0 = TBC[3:0] Transmit byte count for Endpoint n. Before transmission, after filling the transmit buffer, software must write in the TBC field the transmit packet size expressed in bytes (in the range 0-8).

Caution: Any value outside the range 0-8 willinduce undesired effects (such as continuous data

transmission).

14.4.9 Endpoint n register B (EPnRB)

EPnRB Reset value: 0000 xxxx (0xh)

76543210

CTRL

R/W R/W R/W R/W R/W R/W R/W R/W

DTOG

_RX

STAT

_RX1

STAT _RX0

EA3 EA2 EA1 EA0

These registers (EP1RB and EP2RB) are used for controlling data reception on Endpoints 1 and 2. They are also reset by the USB bus reset.

Note: Endpoint 2 and the EP2RB register are not available on some devices (see device feature

list and register map).

Bit 7 = CTRL Control. This bit should be 0.

Note: If this bit is 1, the Endpoint is a control endpoint. (Endpoint 0 is always a control Endpoint,

but it is possible to have more than one control Endpoint).

Bit 6 = DTOG_RX Data toggle, for reception transfers. It contains the expected value of the toggle bit (0=DATA0, 1=DATA1) for the next data packet. This bit is cleared by hardware in the first stage (Setup Stage) of a control transfer (SETUP transactions start always with DATA0 PID). The receiver toggles DTOG_RX only if it receives a correct data packet and the packet’s data PID matches the receiver sequence bit.

Bits 5:4 = STAT_RX [1:0] Status bits, for reception transfers. These bits contain the information about the endpoint status, which are listed below:

96/139

ST7260xx USB interface (USB)

Table 45. STAT_RX bits

STAT_RX1 STAT_RX0 Meaning

11VAL ID: this endpoint is enabled for reception.

These bits are written by software. Hardware sets the STAT_RX bits to NAK when a correct transfer has occurred (CTR=1) related to an OUT or SETUP transaction addressed to this endpoint, so the software has the time to elaborate the received data before acknowledging a new transaction.

Bits 3:0 = EA[3:0] Endpoint address. Software must write in this field the 4-bit address used to identify the transactions directed to this endpoint. Usually EP1RB contains “0001” and EP2RB contains “0010”.

14.4.10 Endpoint 0 register B (EP0RB)

EP0RB Reset value: 1000 0000 (80h)

76543210

DTOG

STAT

RX1

STAT

RX0

DISABLED: reception transfers cannot be executed.

STALL: the endpoint is stalled and all reception requests result in a STALL handshake.

NAK: the endpoint is naked and all reception requests result in a NAK handshake.

0000

R/W R/W R/W R/W R/W R/W R/W R/W

This register is used for controlling data reception on Endpoint 0. It is also reset by the USB bus reset.

Bit 7 = Forced by hardware to 1.

Bits 6:4 = Refer to the EPnRB register for a description of these bits.

Bits 3:0 = Forced by hardware to 0.

14.5 Programming considerations

The interaction between the USB interface and the application program is described below. Apart from system reset, action is always initiated by the USB interface, driven by one of the USB events associated with the Interrupt Status Register (ISTR) bits.

14.5.1 Initializing the registers

At system reset, the software must initialize all registers to enable the USB interface to properly generate interrupts and DMA requests.

97/139

USB interface (USB) ST7260xx

1. Initialize the DMAR, IDR, and IMR registers (choice of enabled interrupts, address of DMA buffers). Refer the paragraph titled initializing the DMA Buffers.

2. Initialize the EP0RA and EP0RB registers to enable accesses to address 0 and endpoint 0 to support USB enumeration. Refer to the paragraph titled Endpoint Initialization.

3. When addresses are received through this channel, update the content of the DADDR.

4. If needed, write the endpoint numbers in the EA fields in the EP1RB and EP2RB register.

14.5.2 Initializing DMA buffers

The DMA buffers are a contiguous zone of memory whose maximum size is 48 bytes. They can be placed anywhere in the memory space to enable the reception of messages. The 10 most significant bits of the start of this memory area are specified by bits DA15-DA6 in registers DMAR and IDR, the remaining bits are 0. The memory map is shown in Figure 42.

Each buffer is filled starting from the bottom (last 3 address bits=000) up.

14.5.3 Endpoint initialization

To be ready to receive:

Set STAT_RX to VALID (11b) in EP0RB to enable reception.

To be ready to transmit:

1. Write the data in the DMA transmit buffer.

2. In register EPnRA, specify the number of bytes to be transmitted in the TBC field

3. Enable the endpoint by setting the STAT_TX bits to VALID (11b) in EPnRA.

Note: Once transmission and/or reception are enabled, registers EPnRA and/or EPnRB

(respectively) must not be modified by software, as the hardware can change their value on the fly.

When the operation is completed, they can be accessed again to enable a new operation.

14.5.4 Interrupt handling

Start of frame (SOF)

The interrupt service routine may monitor the SOF events for a 1 ms synchronization event to the USB bus. This interrupt is generated at the end of a resume sequence and can also be used to detect this event.

USB reset (RESET)

When this event occurs, the DADDR register is reset, and communication is disabled in all endpoint registers (the USB interface will not respond to any packet). Software is responsible for reenabling endpoint 0 within 10 ms of the end of reset. To do this, set the STAT_RX bits in the EP0RB register to VALID.

Suspend (SUSP)

The CPU is warned about the lack of bus activity for more than 3 ms, which is a suspend request. The software should set the USB interface to suspend mode and execute an ST7 HALT instruction to meet the USB-specified power constraints.

98/139

ST7260xx USB interface (USB)

End suspend (ESUSP)

The CPU is alerted by activity on the USB, which causes an ESUSP interrupt. The ST7 automatically terminates HALT mode.

Correct transfer (CTR)

1. When this event occurs, the hardware automatically sets the STAT_TX or STAT_RX to NAK.

Note: Every valid endpoint is NAKed until software clears the CTR bit in the ISTR register,

independently of the endpoint number addressed by the transfer which generated the CTR interrupt.

Note: If the event triggering the CTR interrupt is a SETUP transaction, both STAT_TX and

STAT_RX are set to NAK.

2. Read the PIDR to obtain the token and the IDR to get the endpoint number related to the last transfer.

Note: When a CTR interrupt occurs, the TP3-TP2 bits in the PIDR register and EP1-EP0 bits in

the IDR register stay unchanged until the CTR bit in the ISTR register is cleared.

3. Clear the CTR bit in the ISTR register.

Table 46. USB register map and reset values

Address

(Hex.)

name

PIDR

Reset Value

DMAR

Reset Value

IDR

Reset Value

ISTR

Reset Value

IMR

Reset Value

CTLR

Reset Value

DADDR

Reset Value

EP0RA

Reset Value

EP0RB

Reset Value

7 6 5 4 3210

TP3

DA15

DA7

SUSP

SUSPM0DOVRM

0 0

ST_OUT

1 1

TP2

DA14

DA6

DOVR

0 0

ADD6

DTOG_TX

DTOG_RX

0 0

DA13

EP1

CTR

CTRM

0 0

ADD5

STAT_TX10STAT_TX00TBC3

STAT_RX

1 0

0 0

DA12

EP0

ERR

ERRM0IOVRM

0 0

ADD4

STAT_RX

0 0

DA11

CNT3

IOVR0ESUSP0RESET0SOF

RESUM

ADD30ADD20ADD10ADD0

0 0

E 0

0 0

RX_SEZ0RXD

DA10

CNT2

ESUSP

PDWN1FSUSP1FRES

TBC2

0 0

DA9

CNT10CNT0

RESET

TBC1xTBC0

0 0

DA8

SOFM

0 0

99/139

USB interface (USB) ST7260xx

Table 46. USB register map and reset values (continued)

Address

(Hex.)

name

EP1RA

Reset Value

EP1RB

Reset Value

EP2RA

Reset Value

EP2RB

Reset Value

7 6 5 4 3210

ST_OUT0DTOG_TX0STAT_TX10STAT_TX00TBC3

CTRL0DTOG_RX

ST_OUT0DTOG_TX0STAT_TX10STAT_TX00TBC3

CTRL0DTOG_RX

STAT_RX

1 0

STAT_RX

1 0

STAT_RX

0 0

STAT_RX

0 0

EA3

TBC2

EA2

TBC2

EA2

TBC1xTBC0

EA1

TBC1xTBC0

EA1

EA0

100/139

Datasheet ST7260K2, ST7260K1, ST7260E2, ST7260E1 Datasheet (ST)

Specifications and Main Features

Frequently Asked Questions

User Manual

Table 1. Device summary

1 Description

2 Block diagram

Figure 1. General block diagram

3 Pin description

Figure 2. 40-lead QFN package pinout

Figure 3. 24-pin SO package pinout

Table 2. Device pin description (QFN40)

Table 3. Device pin description (SO24)

4 Register & memory map

Figure 4. Memory map

Table 4. Interrupt vector map

Table 5. Hardware register memory map

5 Flash program memory

5.1 Introduction

5.2 Main features

5.3 Structure

Table 6. Sectors available in Flash devices

5.3.1 Readout protection

Figure 5. Memory map and sector address

5.4 ICC interface

Figure 6. Typical ICC interface

5.5 ICP (in-circuit programming)

5.6 IAP (in-application programming)

5.7 Related documentation

5.7.1 Flash control/status register (FCSR)

Table 7. Flash control/status register address and reset value

6 Central processing unit (CPU)

6.1 Introduction

6.2 Main features

6.3 CPU registers

Figure 7. CPU registers

6.3.1 Accumulator (A)

6.3.2 Index registers (X and Y)

6.3.3 Program counter (PC)

6.3.4 Condition code register (CC)

Table 8. CC register description

6.3.5 Stack pointer register (SP)

Figure 8. Stack manipulation example

7 Reset and clock management

7.1 Reset

7.2 Low voltage detector (LVD)

7.2.1 Watchdog reset

7.2.2 External reset

Figure 9. Low voltage detector functional diagram

Figure 10. Low voltage reset signal output

Figure 11. Temporization timing diagram after an internal reset

Figure 12. Reset timing diagram

7.3 Clock system

7.3.1 General description

Table 9. Recommended values for 24 MHz crystal resonator

7.3.2 External clock

Figure 13. External clock source connections

Figure 14. Crystal/ceramic resonator

Figure 15. Clock block diagram

8 Interrupts

Figure 16. Interrupt processing flowchart

Table 10. Interrupt mapping

8.0.1 Interrupt register (ITRFRE)

Table 11. ITRFRE register description

Table 12. Interrupt register map and reset values

9 Power saving modes

9.1 Introduction

9.2 Halt mode

Figure 17. Halt mode flowchart

9.3 Slow mode

9.4 Wait mode

Figure 18. Wait mode flowchart

10 I/O ports

10.1 Introduction

10.2 Functional description

Table 13. I/O pin functions

10.2.1 Port A

Table 14. Port A0, A3, A4, A5, A6, A7 description

Figure 19. PA0, PA3, PA4, PA5, PA6, PA7 configuration

Table 15. PA1, PA2 description