ST ST7232A User Manual

8-BIT MICROCONTROLLER WITH 8K FLASH/ROM,

ADC, 4 TIMERS, SPI, SCI INTERFACE

■ Memories

– 8K dual voltage High Density Flash (HDFlash)

or ROM with read-out protection capability. In­Application Programming and In-Circuit Pro-

gramming for HDFlash devices
– 384 bytes RAM
– HDFlash endurance: 100 cycles, data reten-

tion: 40 years at 85°C

■ Clock, Reset And Supply Management

– Clock sources: crystal/ceramic resonator os-

cillators and bypass for external clock
– PLL for 2x frequency multiplication
– Four Power Saving Modes: Halt, Active-Halt,

Wait and Slow

■ Interrupt Management

– Nested interrupt controller
– 14 interrupt vectors plus TRAP and RESET
– 6 external interrupt lines (on 4 vectors)

■ Up to 32 I/O Ports

– 32/24 multifunctional bidirectional I/O lines
– 22/17 alternate function lines
– 12/10 high sink outputs

■ 4Timers

– Main Clock Controller with: Real time base,

Beep and Clock-out capabilities
– Configurable watchdog timer
– Two 16-bit Timers with: 2 input captures, 2

output compares, PWM and pulse generator

modes

■ 2 Communications Interfaces

– SPI synchronous serial interface
– SCI asynchronous serial interface

ST7232A

TQFP32

7 x 7

TQFP44

■ 1 Analog peripheral (low current coupling)

– 10-bit ADC with up to 12 robust input ports

■ Instruction Set

– 8-bit Data Manipulation
– 63 Basic Instructions
– 17 main Addressing Modes
– 8 x 8 Unsigned Multiply Instruction

■ Development Tools

– Full hardware/software development package
– In-Circuit Testing capability

SDIP32

400mil

SDIP42

Device Summary

Features

Program memory

- bytes
RAM (stack) -

bytes
Operating Voltage 3.8V to 5.5V 3.8V to 5.5V
Temp. Range up to -40°C to +125°C up to -40°C to +125°C

Package

ST72F32AK1 ST72F32AK2 ST72F32AJ1 ST72F32AJ2 ST7232AK1 ST7232AK2 ST7232AJ1 ST7232AJ2

FLASH 4K FLASH 8K FLASH 4K FLASH 8K ROM 4K ROM 8K ROM 4K ROM 8K

384 (256) 384 (256)

SDIP32 400mils /

TQFP32 7x7

SDIP42 600mils /

TQFP44 10x10

SDIP32 400mils /

TQFP32 7x7

SDIP42 600mils /

TQFP44 10x10

Rev. 2

December 2005 1/157

1

Table of Contents

1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3 REGISTER & MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4 FLASH PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.3 STRUCTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.3.1 Read-out Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.4 ICC INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4.5 ICP (IN-CIRCUIT PROGRAMMING) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4.6 IAP (IN-APPLICATION PROGRAMMING) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4.7 RELATED DOCUMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4.7.1 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

5 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

5.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

5.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

5.3 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

6 SUPPLY, RESET AND CLOCK MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

6.1 PHASE LOCKED LOOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

6.2 MULTI-OSCILLATOR (MO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

6.3 RESET SEQUENCE MANAGER (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

6.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

6.3.2 Asynchronous External RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

6.3.3 External Power-On RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

6.3.4 Internal Watchdog RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

6.4 SYSTEM INTEGRITY MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

6.4.1 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

7 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

7.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

7.2 MASKING AND PROCESSING FLOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

7.3 INTERRUPTS AND LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

7.4 CONCURRENT & NESTED MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

7.5 INTERRUPT REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

7.6 EXTERNAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

7.6.1 I/O Port Interrupt Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

7.7 EXTERNAL INTERRUPT CONTROL REGISTER (EICR) . . . . . . . . . . . . . . . . . . . . . . . 35

8 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

8.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

8.2 SLOW MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

8.3 WAIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

8.4 ACTIVE-HALT AND HALT MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

8.4.1 ACTIVE-HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

8.4.2 HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

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9 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

9.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

9.2 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

9.2.1 Input Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

9.2.2 Output Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

9.2.3 Alternate Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

9.3 I/O PORT IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

9.4 LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

9.5 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

9.5.1 I/O Port Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

10 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

10.1 WATCHDOG TIMER (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

10.1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

10.1.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

10.1.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

10.1.4 How to Program the Watchdog Timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

10.1.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

10.1.6 Hardware Watchdog Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

10.1.7 Using Halt Mode with the WDG (WDGHALT option) . . . . . . . . . . . . . . . . . . . . . . . 51

10.1.8 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

10.1.9 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

10.2 MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK AND BEEPER (MCC/RTC) . 53

10.2.1 Programmable CPU Clock Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

10.2.2 Clock-out Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

10.2.3 Real Time Clock Timer (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

10.2.4 Beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

10.2.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

10.2.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

10.2.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

10.3 16-BIT TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

10.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

10.3.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

10.3.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

10.3.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

10.3.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

10.3.6 Summary of Timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

10.3.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

10.4 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

10.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

10.4.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

10.4.3 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

10.4.4 Clock Phase and Clock Polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

10.4.5 Error Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

10.4.6 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

10.4.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

10.4.8 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

10.5 SERIAL COMMUNICATIONS INTERFACE (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

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10.5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

10.5.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

10.5.3 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

10.5.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

10.5.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

10.5.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

10.5.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

10.6 10-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

10.6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

10.6.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

10.6.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

10.6.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

10.6.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

10.6.6 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

11 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

11.1 CPU ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

11.1.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

11.1.2 Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

11.1.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

11.1.4 Indexed (No Offset, Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

11.1.5 Indirect (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

11.1.6 Indirect Indexed (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

11.1.7 Relative mode (Direct, Indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

11.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

12 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

12.1 PARAMETER CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

12.1.1 Minimum and Maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

12.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

12.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

12.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

12.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

12.2 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

12.2.1 Voltage Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

12.2.2 Current Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

12.2.3 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

12.3 OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

12.3.1 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

12.4 SUPPLY CURRENT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

12.4.1 CURRENT CONSUMPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

12.4.2 Supply and Clock Managers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

12.4.3 On-Chip Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

12.5 CLOCK AND TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

12.5.1 General Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

12.5.2 External Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

12.5.3 Crystal and Ceramic Resonator Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

12.5.4 PLL Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

12.6 MEMORY CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

157

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12.6.1 RAM and Hardware Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

12.6.2 FLASH Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

12.7 EMC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

12.7.1 Functional EMS (Electro Magnetic Susceptibility) . . . . . . . . . . . . . . . . . . . . . . . . 125

12.7.2 Electro Magnetic Interference (EMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

12.7.3 Absolute Maximum Ratings (Electrical Sensitivity) . . . . . . . . . . . . . . . . . . . . . . . . 127

12.8 I/O PORT PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

12.8.1 General Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

12.8.2 Output Driving Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

12.9 CONTROL PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

12.9.1 Asynchronous RESET Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

12.9.2 ICCSEL/VPP Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

12.10 TIMER PERIPHERAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

12.10.116-Bit Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

12.11 COMMUNICATION INTERFACE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . 135

12.11.1SPI - Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

12.12 10-BIT ADC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

12.12.1Analog Power Supply and Reference Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

12.12.2General PCB Design Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

12.12.3ADC Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

13 PACKAGE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

13.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

13.2 THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

13.3 SOLDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

14 ST7232A DEVICE CONFIGURATION AND ORDERING INFORMATION . . . . . . . . . . . . . . . 145

14.1 FLASH OPTION BYTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

14.2 ROM DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE 147

14.3 VERSION-SPECIFIC SALES CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

14.4 FLASH DEVICE ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

14.5 DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

14.5.1 Socket and Emulator Adapter Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

14.6 ST7 APPLICATION NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

15 KNOWN LIMITATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

15.1 ALL FLASH AND ROM DEVICES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

15.1.1 Safe Connection of OSC1/OSC2 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

15.1.2 Unexpected Reset Fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

15.1.3 Clearing active interrupts outside interrupt routine . . . . . . . . . . . . . . . . . . . . . . . . 154

15.1.4 16-bit Timer PWM Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

15.1.5 SCI Wrong Break duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

15.1.6 39-Pulse ICC Entry Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

15.2 ROM DEVICES ONLY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

15.2.1 I/O Port A and F Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

15.2.2 External clock source with PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

16 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

157

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Table of Contents

To obtain the most recent version of this datasheet,

please check at www.st.com>products>technical literature>datasheet.

Please also pay special attention to the Section “KNOWN LIMITATIONS” on page 154.

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157

ST7232A

1 INTRODUCTION

The ST72F32A and ST7232A devices are mem­bers of the ST7 microcontroller family designed for
the 5V operating range.

The 32 and 44-pin devices are designed for mid­range applications

All devices are based on a common industry­standard 8-bit core, featuring an enhanced instruc­tion set and are available with FLASH or ROM pro­gram memory.

Figure 1. Device Block Diagram

8-BIT CORE

ALU

RESET

V

PP

V

SS

V

DD

OSC1
OSC2

CONTROL

OSC

MCC/RTC/BEEP

PORT F

Under software control, all devices can be placed
in WAIT, SLOW, ACTIVE-HALT or HALT mode,
reducing power consumption when the application
is in idle or stand-by state.

The enhanced instruction set and addressing
modes of the ST7 offer both power and flexibility to
software developers, enabling the design of highly
efficient and compact application code. In addition
to standard 8-bit data management, all ST7 micro­controllers feature true bit manipulation, 8x8 un­signed multiplication and indirect addressing
modes.

PROGRAM

MEMORY
(8K Bytes)

RAM

(384 Bytes)

WATCHDOG

ADDRESS AND DATA BUS

PORT A

V

AREF

V

SSA

TIMER A

BEEP

PORT E

SCI

PORT D

10-BIT ADC

PORT B

PORT C

TIMER B

SPI

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3

ST7232A

2 PIN DESCRIPTION

Figure 2. 32-Pin SDIP Package Pinout

(HS) PB4

AIN0 / PD0
AIN1 / PD1

V

AREF

V

SSA

MCO / AIN8 / PF0

BEEP / (HS) PF1

OCMP1_A / AIN10 / PF4

ICAP1_A / (HS) PF6

EXTCLK_A / (HS) PF7

AIN12 / OCMP2_B / PC0
AIN13 / OCMP1_B / PC1

ICAP2_B / (HS) PC2
ICAP1_B / (HS) PC3

ICCDATA/ MISO / PC4

AIN14 / MOSI / PC5

Figure 3. 32-Pin TQFP 7x7 Package Pinout

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

ei3

ei1

ei0

ei2

PB3

32

PB0

31

PE1 / RDI

30

PE0 / TDO

29

V

28
27
26
25
24
23
22
21
20
19
18
17

DD

OSC1
OSC2

VSS_2
RESET

V

PP

PA7 (HS)
PA6 (HS)

PA4 (HS)
PA3 (HS)
PC7 / SS / AIN15

PC6 / SCK / ICCCLK

_2

/ ICCSEL

(HS) 20mA high sink capability
eix associated external interrupt vector

8/157

V

AREF

V

MCO / AIN8 / PF0

BEEP / (HS) PF1

OCMP1_A / AIN10 / PF4

ICAP1_A / (HS) PF6

EXTCLK_A / (HS) PF7

AIN12 / OCMP2_B / PC0

SSA

PB0

PD1 / AIN1

PD0 / AIN0

PB4 (HS)

32 31 30 29 28 27 26 25

1

ei3

2
3

ei1

4
5
6
7
8

9 10111213141516

ICAP2_B / (HS) PC2

ICAP1_B / (HS) PC3

AIN13 / OCMP1_B / PC1

PB3

ei2

ICCDATA / MISO / PC4

AIN14 / MOSI / PC5

PE1 / RDI

ICCCLK / SCK / PC6

PE0 / TDO

ei0

AIN15 / SS / PC7

_2

V

DD

24
23
22
21
20
19
18
17

(HS) PA3

OSC1
OSC2
VSS_2
RESET
V

/ ICCSEL

PP

PA7 (HS)
PA6 (HS)
PA4 (HS)

(HS) 20mA high sink capability
eix associated external interrupt vector

PIN DESCRIPTION (Cont’d)

Figure 4. 42-Pin SDIP and 44-Pin TQFP Package Pinouts

ST7232A

RDI / PE1

(HS) PB4
AIN0 / PD0
AIN1 / PD1
AIN2 / PD2
AIN3 / PD3
AIN4 / PD4

PB0

PB1

PB2
PB3

1
2
3
4
5
6
7
8
9
10
11

(HS) PB4

AIN0 / PD0
AIN1 / PD1
AIN2 / PD2
AIN3 / PD3
AIN4 / PD4
AIN5 / PD5

V

AREF

V

SSA

MCO / AIN8 / PF0

BEEP / (HS) PF1

(HS) PF2

AIN10 / OCMP1_A / PF4

ICAP1_A / (HS) PF6

EXTCLK_A / (HS) PF7
AIN12 / OCMP2_B / PC0
AIN13 / OCMP1_B / PC1

ICAP2_B/ (HS) PC2

ICAP1_B / (HS) PC3

ICCDATA / MISO / PC4

AIN14 / MOSI / PC5

_2

DD

PE0 / TDO

V

OSC1

OSC2

_2
V

/ ICCSEL

SS

PP

RESET

V

PA7 (HS)

PA6 (HS)

PA5 (HS)

44 43 42 41 40 39 38 37 36 35 34

ei2

ei0

ei3

ei1

12 13 14 15 16 17 18 19 20 21 22

AIN5 / PD5

SSA

AREF

V

V

(HS) PF2

BEEP / (HS) PF1

MCO / AIN8 / PF0

OCMP1_A / AIN10 / PF4

1

ei3
2
3

ei2

4
5
6
7
8
9
10
11

ei1
12
13
14
15
16
17
18
19

ei0
20
21

DD_0

V

ICAP1_A / (HS) PF6

EXTCLK_A / (HS) PF7

42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22

PA4 (HS)

V

33

SS_1

V

32

DD_1

PA3 (HS)

31

PC7 / SS / AIN15

30

PC6 / SCK / ICCCLK

29

PC5 / MOSI / AIN14

28

PC4 / MISO / ICCDATA

27

PC3 (HS) / ICAP1_B

26

PC2 (HS) / ICAP2_B

25

PC1 / OCMP1_B / AIN13

24

PC0 / OCMP2_B / AIN12

23

SS_0

V

PB3
PB2
PB1
PB0
PE1 / RDI
PE0 / TDO
VDD_2

OSC1

OSC2
VSS_2
RESET
V

/ ICCSEL

PP

PA7 (HS)
PA6 (HS)
PA5 (HS)
PA4 (HS)
V

SS_1

V

DD_1

PA3 (HS)
PC7 / SS

/ AIN15

PC6 / SCK / ICCCLK

(HS) 20mA high sink capability
eix associated external interrupt vector

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1

ST7232A

PIN DESCRIPTION (Cont’d)

For external pin connection guidelines, refer to See “ELECTRICAL CHARACTERISTICS” on page 113.

Legend / Abbreviations for Table 1:

Type: I = input, O = output, S = supply
Input level: A = Dedicated analog input
In/Output level: C = CMOS 0.3V

CT= CMOS 0.3VDD/0.7VDD with input trigger

Output level: HS = 20mA high sink (on N-buffer only)
Port and control configuration:

– Input: float = floating, wpu = weak pull-up, int = interrupt

– Output: OD = open drain
Refer to “I/O PORTS” on page 42 for more details on the software configuration of the I/O ports.
The RESET configuration of each pin is shown in bold. This configuration is valid as long as the device is

in reset state.

Table 1. Device Pin Description

/0.7V

DD

2)

DD

, PP = push-pull

1)

, ana = analog ports

Pin n°

TQFP44

SDIP42

TQFP32

Pin Name

SDIP32

Level Port

Type

Input

Output

float

Input Output

wpu

int

ana

OD

function

(after

reset)

PP

Main

6 1 30 1 PB4 (HS) I/O CTHS X ei3 X X Port B4

7 2 31 2 PD0/AIN0 I/O C

8 3 32 3 PD1/AIN1 I/O C

9 4 PD2/AIN2 I/O C

10 5 PD3/AIN3 I/O C
11 6 PD4/AIN4 I/O C
12 7 PD5/AIN5 I/O C
13 8 1 4 V
14 9 2 5 V

AREF

SSA

S Analog Reference Voltage for ADC
S Analog Ground Voltage

15 10 3 6 PF0/MCO/AIN8 I/O C

16 11 4 7 PF1 (HS)/BEEP I/O C
17 12 PF2 (HS) I/O C

18 13 5 8

PF4/OCMP1_A/
AIN10

I/O C

19 14 6 9 PF6 (HS)/ICAP1_A I/O C

20 15 7 10

21 V
22 V

23 16 8 11

PF7 (HS)/
EXTCLK_A

DD_0

SS_0

PC0/OCMP2_B/
AIN12

I/O C

S Digital Main Supply Voltage
S Digital Ground Voltage

I/O C

T

T

T

T

T

T

T

T

T

T

T

T

T

X X X X X Port D0 ADC Analog Input 0
X X X X X Port D1 ADC Analog Input 1
X X X X X Port D2 ADC Analog Input 2
X X X X X Port D3 ADC Analog Input 3
X X X X X Port D4 ADC Analog Input 4
X X X X X Port D5 ADC Analog Input 5

X ei1 X X X Port F0

HS X ei1 X X Port F1 Beep signal output
HS X ei1 X X Port F2

X XXXXPort F4

HS X X X X Port F6 Timer A Input Capture 1

HS X XXXPort F7

X XXXXPort C0

Alternate Function

)

ADC Analog
Input 8

ADC Analog
Input 10

Main clock
out (f

CPU

Timer A Out­put Com­pare 1

Timer A External Clock
Source

Timer B Out­put Com­pare 2

ADC Analog
Input 12

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1

ST7232A

Pin n°

Pin Name

SDIP42

TQFP44

24 17 9 12

SDIP32

TQFP32

PC1/OCMP1_B/
AIN13

25 18 10 13 PC2 (HS)/ICAP2_B I/O C
26 19 11 14 PC3 (HS)/ICAP1_B I/O C

27 20 12 15

PC4/MISO/ICCDA­TA

28 21 13 16 PC5/MOSI/AIN14 I/O C

29 22 14 17 PC6/SCK/ICCCLK I/O C

30 23 15 18 PC7/SS/AIN15 I/O C

31 24 16 19 PA3 (HS) I/O C
32 25 V
33 26 V

DD_1

SS_1

34 27 17 20 PA4 (HS) I/O C
35 28 PA5 (HS) I/O C
36 29 18 21 PA6 (HS) I/O C
37 30 19 22 PA7 (HS) I/O CTHS X TPort A7

Level Port

Type

Input

Output

float

Input Output

wpu

int

ana

OD

function

(after

reset)

PP

Main

Alternate Function

Timer B Out-

I/O C

T

X XXXXPort C1

put Com­pare 1

HS X X X X Port C2 Timer B Input Capture 2

T

HS X X X X Port C3 Timer B Input Capture 1

T

SPI Master

I/O C

T

X XXXPort C4

In / Slave
Out Data

SPI Master

T

X XXXXPort C5

Out / Slave
In Data

T

X XXXPort C6

SPI Serial
Clock

SPI Slave

T

X XXXXPort C7

Select (ac­tive low)

HS X ei0 X X Port A3

T

S Digital Main Supply Voltage
S Digital Ground Voltage

HS X XXXPort A4

T

HS X XXXPort A5

T

HS X TPort A6

T

1)

1)

ADC Analog
Input 13

ICC Data In­put

ADC Analog
Input 14

ICC Clock
Output

ADC Analog
Input 15

Must be tied low. In the flash pro­gramming mode, this pin acts as the

38 31 20 23 V

/ICCSEL I

PP

programming voltage input V

Section 12.9.2 for more details. High

PP

. See

voltage must not be applied to ROM

devices.
39 32 21 24 RESET
40 33 22 25 V

SS_2

I/O C

T

S Digital Ground Voltage

Top priority non maskable interrupt.

41 34 23 26 OSC2 O Resonator oscillator inverter output

42 35 24 27 OSC1 I

43 36 25 28 V

DD_2

S Digital Main Supply Voltage

44 37 26 29 PE0/TDO I/O C

1 382730 PE1/RDI I/OC

T

T

X X X X Port E0 SCI Transmit Data Out
X X X X Port E1 SCI Receive Data In

External clock input or Resonator os-

cillator inverter input

Caution: Negative cur-

2 392831 PB0 I/OC

3 40 PB1 I/O C
4 41 PB2 I/O C
5 422932 PB3 I/OC

T

T

T

T

X ei2 X X Port B0

X ei2 X X Port B1
X ei2 X X Port B2
X ei2 X X Port B3

rent injection not al­lowed on this pin

5)

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1

ST7232A

Notes:

1. In the interrupt input column, “eiX” defines the associated external interrupt vector. If the weak pull-up
column (wpu) is merged with the interrupt column (int), then the I/O configuration is pull-up interrupt input,
else the configuration is floating interrupt input.

2. In the open drain output column, “T” defines a true open drain I/O (P-Buffer and protection diode to V
are not implemented). See See “I/O PORTS” on page 42. and Section 12.8 I/O PORT PIN CHARACTER-

ISTICS for more details.

3. OSC1 and OSC2 pins connect a crystal/ceramic resonator, or an external source to the on-chip oscil­lator; see Section 1 INTRODUCTION and Section 12.5 CLOCK AND TIMING CHARACTERISTICS for
more details.

4. On the chip, each I/O port has 8 pads. Pads that are not bonded to external pins are in input pull-up con­figuration after reset. The configuration of these pads must be kept at reset state to avoid added current
consumption.

5. For details refer to Section 12.8.1 on page 128

DD

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1

3 REGISTER & MEMORY MAP

ST7232A

As shown in Figure 5, the MCU is capable of ad­dressing 64K bytes of memories and I/O registers.

The available memory locations consist of 128
bytes of register locations, up to 384 bytes of RAM
and up to 8 Kbytes of user program memory. The
RAM space includes up to 256 bytes for the stack
from 0100h to 01FFh.

Figure 5. Memory Map

0000h

007Fh
0080h

047Fh
0480h

E000h

FFDFh
FFE0h

FFFFh

HW Registers

(see Table 2)

RAM

(384 Bytes)

Reserved

Program Memory

(4K or 8K)

Interrupt & Reset Vectors

(see Table 8)

0080h

00FFh

0100h

01FFh

0200h

027Fh

or 047Fh

The highest address bytes contain the user reset
and interrupt vectors.

IMPORTANT: Memory locations marked as “Re­served” must never be accessed. Accessing a re­served area can have unpredictable effects on the
device.

Short Addressing
RAM (zero page)

256 Bytes Stack

Reserved

E000h

8 KBytes

F000h

4 Kbytes

FFFFh

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1

ST7232A

Table 2. Hardware Register Map

Address Block

0000h
0001h

Port A

0002h

0003h
0004h

Port B

0005h

0006h
0007h

Port C

0008h

0009h
000Ah

Port D

000Bh

000Ch
000Dh

Port E

000Eh

000Fh
0010h

Port F

0011h

0012h

to

0020h

Register

Label

2)

PADR
PADDR
PAOR

2)

PBDR
PBDDR
PBOR

PCDR
PCDDR
PCOR

PDADR

2)

PDDDR
PDOR

2)

PEDR
PEDDR
PEOR

2)

PFDR
PFDDR
PFOR

Port A Data Register
Port A Data Direction Register
Port A Option Register

Port B Data Register
Port B Data Direction Register
Port B Option Register

Port C Data Register
Port C Data Direction Register
Port C Option Register

Port D Data Register
Port D Data Direction Register
Port D Option Register

Port E Data Register
Port E Data Direction Register
Port E Option Register

Port F Data Register
Port F Data Direction Register
Port F Option Register

Register Name

Reset

Status

1)

00h

00h
00h

1)

00h

00h
00h

1)

00h

00h
00h

1)

00h

00h
00h

1)

00h

00h
00h

1)

00h

00h
00h

Remarks

R/W
R/W
R/W

R/W
R/W
R/W

R/W
R/W
R/W

R/W
R/W
R/W

R/W

2)

R/W

2)

R/W

R/W
R/W
R/W

Reserved Area (15 Bytes)

0021h
0022h
0023h

0024h
0025h
0026h
0027h

SPI

ITC

SPIDR
SPICR
SPICSR

ISPR0
ISPR1
ISPR2
ISPR3

SPI Data I/O Register
SPI Control Register
SPI Control/Status Register

Interrupt Software Priority Register 0
Interrupt Software Priority Register 1
Interrupt Software Priority Register 2
Interrupt Software Priority Register 3

xxh
0xh
00h

FFh
FFh
FFh
FFh

0028h EICR External Interrupt Control Register 00h R/W

0029h FLASH FCSR Flash Control/Status Register 00h R/W

002Ah WATCHDOG WDGCR Watchdog Control Register 7Fh R/W

002Bh Reserved Area (1 Byte)

002Ch
002Dh

MCC

MCCSR
MCCBCR

Main Clock Control / Status Register
Main Clock Controller: Beep Control Register

00h
00h

002Eh

to

Reserved Area (3 Bytes)

0030h

14/157

R/W
R/W
R/W

R/W
R/W
R/W
R/W

R/W
R/W

1

ST7232A

Address Block

0031h
0032h
0033h
0034h
0035h
0036h
0037h
0038h
0039h
003Ah
003Bh
003Ch
003Dh
003Eh
003Fh

0040h Reserved Area (1 Byte)

0041h
0042h
0043h
0044h
0045h
0046h
0047h
0048h
0049h
004Ah
004Bh
004Ch
004Dh
004Eh
004Fh

TIMER A

TIMER B

Register

Label

TACR2
TACR1
TACSR
TAIC1HR
TAIC1LR
TAOC1HR
TAOC1LR
TACHR
TACLR
TAACHR
TAACLR
TAIC2HR
TAIC2LR
TAOC2HR
TAOC2LR

TBCR2
TBCR1
TBCSR
TBIC1HR
TBIC1LR
TBOC1HR
TBOC1LR
TBCHR
TBCLR
TBACHR
TBACLR
TBIC2HR
TBIC2LR
TBOC2HR
TBOC2LR

Register Name

Timer A Control Register 2
Timer A Control Register 1
Timer A Control/Status Register
Timer A Input Capture 1 High Register
Timer A Input Capture 1 Low Register
Timer A Output Compare 1 High Register
Timer A Output Compare 1 Low Register
Timer A Counter High Register
Timer A Counter Low Register
Timer A Alternate Counter High Register
Timer A Alternate Counter Low Register
Timer A Input Capture 2 High Register
Timer A Input Capture 2 Low Register
Timer A Output Compare 2 High Register
Timer A Output Compare 2 Low Register

Timer B Control Register 2
Timer B Control Register 1
Timer B Control/Status Register
Timer B Input Capture 1 High Register
Timer B Input Capture 1 Low Register
Timer B Output Compare 1 High Register
Timer B Output Compare 1 Low Register
Timer B Counter High Register
Timer B Counter Low Register
Timer B Alternate Counter High Register
Timer B Alternate Counter Low Register
Timer B Input Capture 2 High Register
Timer B Input Capture 2 Low Register
Timer B Output Compare 2 High Register
Timer B Output Compare 2 Low Register

Reset

Status

00h
00h

xxxx x0xxb

xxh

xxh
80h
00h
FFh
FCh
FFh
FCh

xxh

xxh
80h
00h

00h
00h

xxxx x0xxb

xxh

xxh
80h
00h
FFh
FCh
FFh
FCh

xxh

xxh
80h
00h

Remarks

R/W
R/W
R/W
Read Only
Read Only
R/W
R/W
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
R/W
R/W

R/W
R/W
R/W
Read Only
Read Only
R/W
R/W
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
R/W
R/W

0050h
0051h
0052h
0053h
0054h
0055h
0056h
0057h

0058h

to

006Fh

0070h
0071h
0072h

0073h
007Fh

SCI

ADC

SCISR
SCIDR
SCIBRR
SCICR1
SCICR2
SCIERPR

SCIETPR

ADCCSR
ADCDRH
ADCDRL

Legend: x=undefined, R/W=read/write

SCI Status Register
SCI Data Register
SCI Baud Rate Register
SCI Control Register 1
SCI Control Register 2
SCI Extended Receive Prescaler Register
Reserved area
SCI Extended Transmit Prescaler Register

Reserved Area (24 Bytes)

Control/Status Register
Data High Register
Data Low Register

Reserved Area (13 Bytes)

C0h

xxh
00h

x000 0000h

00h
00h

---

00h

00h
00h
00h

Read Only
R/W
R/W
R/W
R/W
R/W

R/W

R/W
Read Only
Read Only

15/157

1

ST7232A

Notes:

1. The contents of the I/O port DR registers are readable only in output configuration. In input configura­tion, the values of the I/O pins are returned instead of the DR register contents.

2. The bits associated with unavailable pins must always keep their reset value.

16/157

1

4 FLASH PROGRAM MEMORY

ST7232A

4.1 Introduction

The ST7 dual voltage High Density Flash
(HDFlash) is a non-volatile memory that can be
electrically erased as a single block or by individu­al sectors and programmed on a Byte-by-Byte ba­sis using an external V

supply.

PP

The HDFlash devices can be programmed and
erased off-board (plugged in a programming tool)
or on-board using ICP (In-Circuit Programming) or
IAP (In-Application Programming).

The array matrix organisation allows each sector
to be erased and reprogrammed without affecting
other sectors.

4.2 Main Features

■ Three Flash programming modes:

– Insertion in a programming tool. In this mode,

all sectors including option bytes can be pro­grammed or erased.

– ICP (In-Circuit Programming). In this mode, all

sectors including option bytes can be pro­grammed or erased without removing the de­vice from the application board.

– IAP (In-Application Programming) In this

mode, all sectors except Sector 0, can be pro­grammed or erased without removing the de­vice from the application board and while the
application is running.

■ ICT (In-Circuit Testing) for downloading and

executing user application test patterns in RAM

■ Read-out protection

■ Register Access Security System (RASS) to

prevent accidental programming or erasing

4.3 Structure

The Flash memory is organised in sectors and can
be used for both code and data storage.

Depending on the overall Flash memory size in the
microcontroller device, there are up to three user
sectors (see Table 3). Each of these sectors can
be erased independently to avoid unnecessary
erasing of the whole Flash memory when only a
partial erasing is required.

The first two sectors have a fixed size of 4 Kbytes
(see Figure 6). They are mapped in the upper part
of the ST7 addressing space so the reset and in­terrupt vectors are located in Sector 0 (F000h­FFFFh).

Table 3. Sectors available in Flash devices

Flash Size (bytes) Available Sectors

4K Sector 0
8K Sectors 0,1

> 8K Sectors 0,1, 2

4.3.1 Read-out Protection

Read-out protection, when selected, provides a
protection against Program Memory content ex­traction and against write access to Flash memo­ry. Even if no protection can be considered as to­tally unbreakable, the feature provides a very high
level of protection for a general purpose microcon­troller.

In flash devices, this protection is removed by re­programming the option. In this case, the entire
program memory is first automatically erased.

Read-out protection selection depends on the de­vice type:

– In Flash devices it is enabled and removed

through the FMP_R bit in the option byte.

– In ROM devices it is enabled by mask option

specified in the Option List.

Figure 6. Memory Map and Sector Address

4K 10K 24K 48K

1000h
3FFFh

7FFFh

9FFFh

BFFFh

D7FFh

DFFFh

EFFFh

FFFFh

8K 16K 32K 60K

2Kbytes

8Kbytes 40 Kbytes

16 Kbytes
4 Kbytes
4 Kbytes

24 Kbytes

FLASH
MEMORY SIZE

SECTOR 2

52 Kbytes

SECTOR 1
SECTOR 0

17/157

1

ST7232A

FLASH PROGRAM MEMORY (Cont’d)

4.4 ICC Interface

ICC needs a minimum of 4 and up to 6 pins to be
connected to the programming tool (see Figure 7).
These pins are:

– RESET
–V

: device reset

: device power supply ground

SS

Figure 7. Typical ICC Interface

PROGRAMMING TOOL

APPLICATION
POWER SUPPLY

(See Note 3)

C

L2

DD

V

OSC2

(See caution)

C

L1

OSC1

ST7

Notes:

1. If the ICCCLK or ICCDATA pins are only used
as outputs in the application, no signal isolation is
necessary. As soon as the Programming Tool is
plugged to the board, even if an ICC session is not
in progress, the ICCCLK and ICCDATA pins are
not available for the application. If they are used as
inputs by the application, isolation such as a serial
resistor has to implemented in case another de­vice forces the signal. Refer to the Programming
Tool documentation for recommended resistor val­ues.

2. During the ICC session, the programming tool
must control the RESET
flicts between the programming tool and the appli­cation reset circuit if it drives more than 5mA at
high level (push pull output or pull-up resistor<1K).
A schottky diode can be used to isolate the appli­cation RESET circuit in this case. When using a

pin. This can lead to con-

– ICCCLK: ICC output serial clock pin
– ICCDATA: ICC input/output serial data pin
– ICCSEL/V

: programming voltage

PP

– OSC1(or OSCIN): main clock input for exter-

nal source (optional)

: application board power supply (option-

–V

DD

al, see Figure 7, Note 3)

ICC CONNECTOR

975 3

10kΩ

SS

V

ICCSEL/VPP

ICC Cable

RESET

ICCCLK

HE10 CONNECTOR TYPE

1

246810

ICCDATA

APPLICATION BOARD

ICC CONNECTOR

APPLICATION
RESET SOURCE

See Note 2

See Note 1

APPLICATION

I/O

classical RC network with R>1K or a reset man­agement IC with open drain output and pull-up re­sistor>1K, no additional components are needed.
In all cases the user must ensure that no external
reset is generated by the application during the
ICC session.

3. The use of Pin 7 of the ICC connector depends
on the Programming Tool architecture. This pin
must be connected when using most ST Program­ming Tools (it is used to monitor the application
power supply). Please refer to the Programming
Tool manual.

Caution: External clock ICC entry mode is man­datory. Pin 9 must be connected to the OSC1 or
OSCIN pin of the ST7 and OSC2 must be ground­ed.

18/157

1

FLASH PROGRAM MEMORY (Cont’d)

ST7232A

4.5 ICP (In-Circuit Programming)

To perform ICP the microcontroller must be
switched to ICC (In-Circuit Communication) mode
by an external controller or programming tool.

Depending on the ICP code downloaded in RAM,
Flash memory programming can be fully custom­ized (number of bytes to program, program loca­tions, or selection serial communication interface
for downloading).

When using an STMicroelectronics or third-party
programming tool that supports ICP and the spe­cific microcontroller device, the user needs only to
implement the ICP hardware interface on the ap­plication board (see Figure 7). For more details on
the pin locations, refer to the device pinout de­scription.

4.6 IAP (In-Application Programming)

This mode uses a BootLoader program previously
stored in Sector 0 by the user (in ICP mode or by
plugging the device in a programming tool).

This mode is fully controlled by user software. This
allows it to be adapted to the user application, (us­er-defined strategy for entering programming
mode, choice of communications protocol used to
fetch the data to be stored, etc.). For example, it is

possible to download code from the SPI, SCI, USB
or CAN interface and program it in the Flash. IAP
mode can be used to program any of the Flash
sectors except Sector 0, which is write/erase pro­tected to allow recovery in case errors occur dur­ing the programming operation.

4.7 Related Documentation

For details on Flash programming and ICC proto­col, refer to the ST7 Flash Programming Refer­ence Manual and to the ST7 ICC Protocol Refer­ence Manual

.

4.7.1 Register Description FLASH CONTROL/STATUS REGISTER (FCSR)

Read/Write
Reset Value: 0000 0000 (00h)

70

00000000

This register is reserved for use by Programming
Tool software. It controls the Flash programming
and erasing operations.

Table 4. Flash Control/Status Register Address and Reset Value

Address

(Hex.)

0029h

Register

Label

FCSR

Reset Value00000000

76543210

19/157

1

ST7232A

5 CENTRAL PROCESSING UNIT

5.1 INTRODUCTION

This CPU has a full 8-bit architecture and contains
six internal registers allowing efficient 8-bit data
manipulation.

5.2 MAIN FEATURES

■ Enable executing 63 basic instructions

■ Fast 8-bit by 8-bit multiply

■ 17 main addressing modes (with indirect

addressing mode)

■ Two 8-bit index registers

■ 16-bit stack pointer

■ Low power HALT and WAIT modes

■ Priority maskable hardware interrupts

■ Non-maskable software/hardware interrupts

Figure 8. CPU Registers

5.3 CPU REGISTERS

The 6 CPU registers shown in Figure 8 are not
present in the memory mapping and are accessed
by specific instructions.

Accumulator (A)

The Accumulator is an 8-bit general purpose reg­ister used to hold operands and the results of the
arithmetic and logic calculations and to manipulate
data.

Index Registers (X and Y)

These 8-bit registers are used to create effective
addresses or as temporary storage areas for data
manipulation. (The Cross-Assembler generates a
precede instruction (PRE) to indicate that the fol­lowing instruction refers to the Y register.)

The Y register is not affected by the interrupt auto­matic procedures.

Program Counter (PC)

The program counter is a 16-bit register containing
the address of the next instruction to be executed
by the CPU. It is made of two 8-bit registers PCL
(Program Counter Low which is the LSB) and PCH
(Program Counter High which is the MSB).

70

RESET VALUE = XXh

70

RESET VALUE = XXh

70

RESET VALUE = XXh

15 8

RESET VALUE = RESET VECTOR @ FFFEh-FFFFh

15

RESET VALUE = STACK HIGHER ADDRESS

PCH

RESET VALUE =

7

70

1C1I1HI0NZ

1X11X1XX

70

8

PCL

0

ACCUMULATOR

X INDEX REGISTER

Y INDEX REGISTER

PROGRAM COUNTER

CONDITION CODE REGISTER

STACK POINTER

X = Undefined Value

20/157

1

CENTRAL PROCESSING UNIT (Cont’d)

Condition Code Register (CC)

Read/Write
Reset Value: 111x1xxx

70

Bit 1 = Z Zero.
This bit is set and cleared by hardware. This bit in-

dicates that the result of the last arithmetic, logical
or data manipulation is zero.
0: The result of the last operation is different from

zero.

11I1HI0NZ

C

1: The result of the last operation is zero.

This bit is accessed by the JREQ and JRNE test
The 8-bit Condition Code register contains the in­terrupt masks and four flags representative of the
result of the instruction just executed. This register
can also be handled by the PUSH and POP in­structions.

These bits can be individually tested and/or con­trolled by specific instructions.

Arithmetic Management Bits

Bit 4 = H Half carry.
This bit is set by hardware when a carry occurs be-

tween bits 3 and 4 of the ALU during an ADD or
ADC instructions. It is reset by hardware during
the same instructions.

0: No half carry has occurred.
1: A half carry has occurred.

This bit is tested using the JRH or JRNH instruc­tion. The H bit is useful in BCD arithmetic subrou­tines.

Bit 2 = N Negative.
This bit is set and cleared by hardware. It is repre-

sentative of the result sign of the last arithmetic,
logical or data manipulation. It’s a copy of the re-

th

sult 7

bit.
0: The result of the last operation is positive or null.
1: The result of the last operation is negative

(i.e. the most significant bit is a logic 1).

This bit is accessed by the JRMI and JRPL instruc­tions.

instructions.
Bit 0 = C Carry/borrow.

This bit is set and cleared by hardware and soft­ware. It indicates an overflow or an underflow has
occurred during the last arithmetic operation.
0: No overflow or underflow has occurred.
1: An overflow or underflow has occurred.

This bit is driven by the SCF and RCF instructions
and tested by the JRC and JRNC instructions. It is
also affected by the “bit test and branch”, shift and
rotate instructions.

Interrupt Management Bits

Bit 5,3 = I1, I0 Interrupt
The combination of the I1 and I0 bits gives the cur-

rent interrupt software priority.

Interrupt Software Priority I1 I0

Level 0 (main) 1 0
Level 1 0 1
Level 2 0 0
Level 3 (= interrupt disable) 1 1

These two bits are set/cleared by hardware when
entering in interrupt. The loaded value is given by
the corresponding bits in the interrupt software pri­ority registers (IxSPR). They can be also set/
cleared by software with the RIM, SIM, IRET,
HALT, WFI and PUSH/POP instructions.

See the interrupt management chapter for more
details.

ST7232A

21/157

1

ST7232A

CENTRAL PROCESSING UNIT (Cont’d)

Stack Pointer (SP)

Read/Write
Reset Value: 01 FFh

15 8

00000001

The least significant byte of the Stack Pointer
(called S) can be directly accessed by a LD in­struction.

Note: When the lower limit is exceeded, the Stack
Pointer wraps around to the stack upper limit, with­out indicating the stack overflow. The previously
stored information is then overwritten and there­fore lost. The stack also wraps in case of an under­flow.

70

SP7 SP6 SP5 SP4 SP3 SP2 SP1

SP0

The stack is used to save the return address dur­ing a subroutine call and the CPU context during
an interrupt. The user may also directly manipulate
the stack by means of the PUSH and POP instruc-

The Stack Pointer is a 16-bit register which is al­ways pointing to the next free location in the stack.
It is then decremented after data has been pushed
onto the stack and incremented before data is
popped from the stack (see Figure 9).

Since the stack is 256 bytes deep, the 8 most sig­nificant bits are forced by hardware. Following an
MCU Reset, or after a Reset Stack Pointer instruc­tion (RSP), the Stack Pointer contains its reset val­ue (the SP7 to SP0 bits are set) which is the stack

tions. In the case of an interrupt, the PCL is stored
at the first location pointed to by the SP. Then the
other registers are stored in the next locations as
shown in Figure 9.

– When an interrupt is received, the SP is decre-

mented and the context is pushed on the stack.

– On return from interrupt, the SP is incremented

and the context is popped from the stack.

A subroutine call occupies two locations and an in­terrupt five locations in the stack area.

higher address.

Figure 9. Stack Manipulation Example

CALL

Subroutine

Interrupt

Event

PUSH Y POP Y IRET

RET

or RSP

@ 0100h

SP

@ 01FFh

SP

CC

A

X
PCH
PCL

PCH
PCL

Stack Higher Address = 01FFh
Stack Lower Address =

PCH
PCL

0100h

SP

Y

CC

A
X

PCH

PCL

PCH

PCL

SP

CC

A
X

PCH

PCL

PCH

PCL

SP

PCH
PCL

SP

22/157

1

6 SUPPLY, RESET AND CLOCK MANAGEMENT

ST7232A

The device includes a range of utility features for
securing the application in critical situations (for
example in case of a power brown-out), and re­ducing the number of external components. An
overview is shown in Figure 11.

For more details, refer to dedicated parametric
section.

Main features

■ Optional PLL for multiplying the frequency by 2

■ Reset Sequence Manager (RSM)

■ Multi-Oscillator Clock Management (MO)

– 5 Crystal/Ceramic resonator oscillators

6.1 PHASE LOCKED LOOP

If the clock frequency input to the PLL is in the
range 2 to 4 MHz, the PLL can be used to multiply

Figure 11. Clock, Reset and Supply Block Diagram

OSC2

OSC1

MULTI-

OSCILLATOR

(MO)

f

OSC

PLL

(option)

SYSTEM INTEGRITY MANAGEMENT

the frequency by two to obtain an f

OSC2

of 4 to 8
MHz. The PLL is enabled by option byte. If the PLL
is disabled, then f

OSC2 = fOSC

/2.

Caution: The PLL is not recommended for appli­cations where timing accuracy is required.

Figure 10. PLL Block Diagram

f

OSC

PLL x 2

/ 2

f

OSC2

0

1

PLL OPTION BIT

MAIN CLOCK

CONTROLLER

WITH REALTIME

CLOCK (MCC/RTC)

f

OSC2

f

CPU

RESET

V

SS

V

DD

RESET SEQUENCE

MANAGER

(RSM)

SICSR

0

WATCHDOG

TIMER (WDG)

0

WDG

00

RF

23/157

1

ST7232A

6.2 MULTI-OSCILLATOR (MO)

The main clock of the ST7 can be generated by
two different source types coming from the multi­oscillator block:

■ an external source

■ 4 crystal or ceramic resonator oscillators

Each oscillator is optimized for a given frequency
range in terms of consumption and is selectable
through the option byte. The associated hardware
configurations are shown in Table 5. Refer to the
electrical characteristics section for more details.

Caution: The OSC1 and/or OSC2 pins must not
be left unconnected. For the purposes of Failure
Mode and Effect Analysis, it should be noted that if
the OSC1 and/or OSC2 pins are left unconnected,
the ST7 main oscillator may start and, in this con­figuration, could generate an f

clock frequency

OSC

in excess of the allowed maximum (>16MHz.),
putting the ST7 in an unsafe/undefined state. The
product behaviour must therefore be considered
undefined when the OSC pins are left unconnect­ed.

External Clock Source

In this external clock mode, a clock signal (square,
sinus or triangle) with ~50% duty cycle has to drive
the OSC1 pin while the OSC2 pin is tied to ground.

Crystal/Ceramic Oscillators

This family of oscillators has the advantage of pro­ducing a very accurate rate on the main clock of
the ST7. The selection within a list of 4 oscillators
with different frequency ranges has to be done by
option byte in order to reduce consumption (refer
to Section 14.1 on page 145 for more details on

the frequency ranges). In this mode of the multi­oscillator, the resonator and the load capacitors
have to be placed as close as possible to the oscil­lator pins in order to minimize output distortion and
start-up stabilization time. The loading capaci­tance values must be adjusted according to the
selected oscillator.

These oscillators are not stopped during the
RESET phase to avoid losing time in the oscillator
start-up phase.

Table 5. ST7 Clock Sources

Hardware Configuration

ST7

OSC1 OSC2

External ClockCrystal/Ceramic Resonators

EXTERNAL

SOURCE

OSC1 OSC2

C

L1

CAPACITORS

ST7

LOAD

C

L2

24/157

1

6.3 RESET SEQUENCE MANAGER (RSM)

ST7232A

6.3.1 Introduction

The reset sequence manager includes two RE­SET sources as shown in Figure 13:

■ External RESET source pulse

■ Internal WATCHDOG RESET

These sources act on the RESET

pin and it is al-

ways kept low during the delay phase.
The RESET service routine vector is fixed at ad-

dresses FFFEh-FFFFh in the ST7 memory map.
The basic RESET sequence consists of 3 phases

as shown in Figure 12:

■ Active Phase depending on the RESET source

■ 256 or 4096 CPU clock cycle delay (selected by

option byte)

■ RESET vector fetch

The 256 or 4096 CPU clock cycle delay allows the
oscillator to stabilise and ensures that recovery
has taken place from the Reset state. The shorter
or longer clock cycle delay should be selected by
option byte to correspond to the stabilization time
of the external oscillator used in the application.

Figure 13. Reset Block Diagram

The RESET vector fetch phase duration is 2 clock
cycles.

Figure 12. RESET Sequence Phases

RESET

Active Phase

INTERNAL RESET

256 or 4096 CLOCK CYCLES

6.3.2 Asynchronous External RESET

The RESET
output with integrated R

pin is both an input and an open-drain

weak pull-up resistor.

ON

FETCH

VECTOR

pin

This pull-up has no fixed value but varies in ac­cordance with the input voltage. It

can be pulled
low by external circuitry to reset the device. See
Electrical Characteristic section for more details.

A RESET signal originating from an external
source must have a duration of at least t

h(RSTL)in

in
order to be recognized (see Figure 14). This de­tection is asynchronous and therefore the MCU
can enter reset state even in HALT mode.

RESET

V

DD

R

ON

Filter

PULSE

GENERATOR

WATCHDOG RESET

INTERNAL
RESET

25/157

1

ST7232A

RESET SEQUENCE MANAGER (Cont’d)

The RESET
plays a major role in EMS performance. In a noisy
environment, it is recommended to follow the
guidelines mentioned in the electrical characteris­tics section.

6.3.3 External Power-On RESET

To start up the microcontroller correctly, the user
must ensure by means of an external reset circuit
that the reset signal is held low until V
the minimum level specified for the selected f
frequency.

Figure 14. RESET Sequences

pin is an asynchronous signal which

is over

DD

OSC

A proper reset signal for a slow rising V

supply

DD

can generally be provided by an external RC net­work connected to the RESET

pin.

6.3.4 Internal Watchdog RESET

The RESET sequence generated by a internal
Watchdog counter overflow is shown in Figure 14.

Starting from the Watchdog counter underflow, the
device RESET
low during at least t

pin acts as an output that is pulled

w(RSTL)out

.

EXTERNAL
RESET
SOURCE

RESET PIN

WATCHDOG
RESET

RUN

t

h(RSTL)in

EXTERNAL

RESET

ACTIVE
PHASE

WATCHDOG UNDERFLOW

RUN RUN

INTERNAL RESET (256 or 4096 T
VECTOR FETCH

WATCHDOG

RESET

ACTIVE
PHASE

t

w(RSTL)out

CPU

)

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1

6.4 SYSTEM INTEGRITY MANAGEMENT

6.4.1 Register Description SYSTEM INTEGRITY (SI) CONTROL/STATUS REGISTER (SICSR)

Read/Write
Reset Value: 0000 000x (00h)

Bit 0 = WDGRF Watchdog reset flag
This bit indicates that the last Reset was generat-

70

ed by the Watchdog peripheral. It is set by hard­ware (watchdog reset) and cleared by software

0000000

WDG

RF

(writing zero).

Bits 7:1 = Reserved, must be kept cleared.

ST7232A

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1

ST7232A

7 INTERRUPTS

7.1 INTRODUCTION

The ST7 enhanced interrupt management pro­vides the following features:

■ Hardware interrupts

■ Software interrupt (TRAP)

■ Nested or concurrent interrupt management

with flexible interrupt priority and level
management:

– Up to 4 software programmable nesting levels
– Up to 16 interrupt vectors fixed by hardware
– 2 non maskable events: RESET, TRAP

This interrupt management is based on:
– Bit 5 and bit 3 of the CPU CC register (I1:0),
– Interrupt software priority registers (ISPRx),
– Fixed interrupt vector addresses located at the

high addresses of the memory map (FFE0h to
FFFFh) sorted by hardware priority order.

This enhanced interrupt controller guarantees full
upward compatibility with the standard (not nest­ed) ST7 interrupt controller.

7.2 MASKING AND PROCESSING FLOW

The interrupt masking is managed by the I1 and I0
bits of the CC register and the ISPRx registers
which give the interrupt software priority level of
each interrupt vector (see Table 6). The process­ing flow is shown in Figure 15

When an interrupt request has to be serviced:
– Normal processing is suspended at the end of

the current instruction execution.

– The PC, X, A and CC registers are saved onto

the stack.

– I1 and I0 bits of CC register are set according to

the corresponding values in the ISPRx registers
of the serviced interrupt vector.

– The PC is then loaded with the interrupt vector of

the interrupt to service and the first instruction of
the interrupt service routine is fetched (refer to
“Interrupt Mapping” table for vector addresses).

The interrupt service routine should end with the
IRET instruction which causes the contents of the
saved registers to be recovered from the stack.

Note: As a consequence of the IRET instruction,
the I1 and I0 bits will be restored from the stack
and the program in the previous level will resume.

Table 6. Interrupt Software Priority Levels

Interrupt software priority Level I1 I0

Level 0 (main)
Level 1 0 1
Level 2 0 0
Level 3 (= interrupt disable) 1 1

Low

High

10

Figure 15. Interrupt Processing Flowchart

RESET

RESTORE PC, X, A, CC

FROM STACK

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PENDING

INTERRUPT

N

FETCH NEXT

INSTRUCTION

Y

“IRET”

N

EXECUTE

INSTRUCTION

1

Y

THE INTERRUPT

STAYS PENDING

TRAP

Interrupt has the same or a

lower software priority

than current one

STACK PC, X, A, CC

LOAD I1:0 FROM INTERRUPT SW REG.

LOAD PC FROM INTERRUPT VECTOR

N

I1:0

software priority

than current one

Interrupt has a higher

Y

INTERRUPTS (Cont’d)

ST7232A

Servicing Pending Interrupts

As several interrupts can be pending at the same
time, the interrupt to be taken into account is deter­mined by the following two-step process:

– the highest software priority interrupt is serviced,
– if several interrupts have the same software pri-

ority then the interrupt with the highest hardware
priority is serviced first.

Figure 16 describes this decision process.

Figure 16. Priority Decision Process

PENDING

INTERRUPTS

Same

HIGHEST HARDWARE

PRIORITY SERVICED

SOFTWARE

PRIORITY

HIGHEST SOFTWARE

PRIORITY SERVICED

Different

When an interrupt request is not serviced immedi­ately, it is latched and then processed when its
software priority combined with the hardware pri­ority becomes the highest one.

Note 1: The hardware priority is exclusive while
the software one is not. This allows the previous
process to succeed with only one interrupt.
Note 2: RESET and TRAP can be considered as
having the highest software priority in the decision
process.

Different Interrupt Vector Sources

Two interrupt source types are managed by the
ST7 interrupt controller: the non-maskable type
(RESET,TRAP) and the maskable type (external
or from internal peripherals).

Non-Maskable Sources

These sources are processed regardless of the
state of the I1 and I0 bits of the CC register (see

Figure 15). After stacking the PC, X, A and CC

registers (except for RESET), the corresponding

vector is loaded in the PC register and the I1 and
I0 bits of the CC are set to disable interrupts (level

3). These sources allow the processor to exit
HALT mode.

■ TRAP (Non Maskable Software Interrupt)

This software interrupt is serviced when the TRAP
instruction is executed. It will be serviced accord­ing to the flowchart in Figure 15.

■ RESET

The RESET source has the highest priority in the
ST7. This means that the first current routine has
the highest software priority (level 3) and the high­est hardware priority.
See the RESET chapter for more details.

Maskable Sources

Maskable interrupt vector sources can be serviced
if the corresponding interrupt is enabled and if its
own interrupt software priority (in ISPRx registers)
is higher than the one currently being serviced (I1
and I0 in CC register). If any of these two condi­tions is false, the interrupt is latched and thus re­mains pending.

■ External Interrupts

External interrupts allow the processor to exit from
HALT low power mode. External interrupt sensitiv­ity is software selectable through the External In­terrupt Control register (EICR).
External interrupt triggered on edge will be latched
and the interrupt request automatically cleared
upon entering the interrupt service routine.
If several input pins of a group connected to the
same interrupt line are selected simultaneously,
these will be logically ORed.

■ Peripheral Interrupts

Usually the peripheral interrupts cause the MCU to
exit from HALT mode except those mentioned in
the “Interrupt Mapping” table. A peripheral inter­rupt occurs when a specific flag is set in the pe­ripheral status registers and if the corresponding
enable bit is set in the peripheral control register.
The general sequence for clearing an interrupt is
based on an access to the status register followed
by a read or write to an associated register.
Note: The clearing sequence resets the internal
latch. A pending interrupt (i.e. waiting for being
serviced) will therefore be lost if the clear se­quence is executed.

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1

ST7232A

INTERRUPTS (Cont’d)

7.3 INTERRUPTS AND LOW POWER MODES

All interrupts allow the processor to exit the WAIT
low power mode. On the contrary, only external
and other specified interrupts allow the processor
to exit from the HALT modes (see column “Exit
from HALT” in “Interrupt Mapping” table). When
several pending interrupts are present while exit­ing HALT mode, the first one serviced can only be
an interrupt with exit from HALT mode capability
and it is selected through the same decision proc­ess shown in Figure 16.

Note: If an interrupt, that is not able to Exit from
HALT mode, is pending with the highest priority
when exiting HALT mode, this interrupt is serviced
after the first one serviced.

Figure 17. Concurrent Interrupt Management

TRAP

IT0

TRAP

IT1

RIM

IT2

IT2

IT1

IT4

IT3

IT1

HARDWARE PRIORITY

MAIN

11 / 10

7.4 CONCURRENT & NESTED MANAGEMENT

The following Figure 17 and Figure 18 show two
different interrupt management modes. The first is
called concurrent mode and does not allow an in­terrupt to be interrupted, unlike the nested mode in

Figure 18. The interrupt hardware priority is given

in this order from the lowest to the highest: MAIN,
IT4, IT3, IT2, IT1, IT0. The software priority is giv­en for each interrupt.

Warning: A stack overflow may occur without no­tifying the software of the failure.

SOFTWARE
PRIORITY
LEVEL

IT0

IT3

IT4

MAIN

3
3
3
3
3
3
3/0

I1

11
11
11
11
11
11

10

I0

USED STACK = 10 BYTES

Figure 18. Nested Interrupt Management

IT4

IT3

TRAP

TRAP

IT0

HARDWARE PRIORITY

MAIN

RIM

IT2

IT2

IT1

IT1

IT4

11 / 10

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1

IT4

IT0

IT3

IT1

SOFTWARE
PRIORITY
LEVEL

IT2

10

MAIN

I1 I0

3
3
2
1
3
3
3/0

11
11
00
01
11
11

USED STACK = 20 BYTES