ST ST7232A User Manual

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8-BIT MICROCONTROLLER WITH 8K FLASH/ROM,

ADC, 4 TIMERS, SPI, SCI INTERFACE

■ Memories

– 8K dual voltage High Density Flash (HDFlash)

or ROM with read-out protection capability. InApplication Programming and In-Circuit Pro-

gramming for HDFlash devices – 384 bytes RAM – HDFlash endurance: 100 cycles, data reten-

tion: 40 years at 85°C

■ Clock, Reset And Supply Management

– Clock sources: crystal/ceramic resonator os-

cillators and bypass for external clock – PLL for 2x frequency multiplication – Four Power Saving Modes: Halt, Active-Halt,

Wait and Slow

■ Interrupt Management

– Nested interrupt controller – 14 interrupt vectors plus TRAP and RESET – 6 external interrupt lines (on 4 vectors)

■ Up to 32 I/O Ports

– 32/24 multifunctional bidirectional I/O lines – 22/17 alternate function lines – 12/10 high sink outputs

■ 4Timers

– Main Clock Controller with: Real time base,

Beep and Clock-out capabilities – Configurable watchdog timer – Two 16-bit Timers with: 2 input captures, 2

output compares, PWM and pulse generator

modes

■ 2 Communications Interfaces

– SPI synchronous serial interface – SCI asynchronous serial interface

ST7232A

TQFP32

7 x 7

TQFP44

■ 1 Analog peripheral (low current coupling)

– 10-bit ADC with up to 12 robust input ports

■ Instruction Set

– 8-bit Data Manipulation – 63 Basic Instructions – 17 main Addressing Modes – 8 x 8 Unsigned Multiply Instruction

■ Development Tools

– Full hardware/software development package – In-Circuit Testing capability

SDIP32

400mil

SDIP42

Device Summary

Features

Program memory

- bytes RAM (stack) -

bytes Operating Voltage 3.8V to 5.5V 3.8V to 5.5V Temp. Range up to -40°C to +125°C up to -40°C to +125°C

Package

ST72F32AK1 ST72F32AK2 ST72F32AJ1 ST72F32AJ2 ST7232AK1 ST7232AK2 ST7232AJ1 ST7232AJ2

FLASH 4K FLASH 8K FLASH 4K FLASH 8K ROM 4K ROM 8K ROM 4K ROM 8K

384 (256) 384 (256)

SDIP32 400mils /

TQFP32 7x7

SDIP42 600mils /

TQFP44 10x10

SDIP32 400mils /

TQFP32 7x7

SDIP42 600mils /

TQFP44 10x10

Rev. 2

December 2005 1/157

Table of Contents

1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3 REGISTER & MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4 FLASH PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.3 STRUCTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.3.1 Read-out Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.4 ICC INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4.5 ICP (IN-CIRCUIT PROGRAMMING) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4.6 IAP (IN-APPLICATION PROGRAMMING) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4.7 RELATED DOCUMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4.7.1 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

5 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

5.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

5.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

5.3 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

6 SUPPLY, RESET AND CLOCK MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

6.1 PHASE LOCKED LOOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

6.2 MULTI-OSCILLATOR (MO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

6.3 RESET SEQUENCE MANAGER (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

6.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

6.3.2 Asynchronous External RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

6.3.3 External Power-On RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

6.3.4 Internal Watchdog RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

6.4 SYSTEM INTEGRITY MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

6.4.1 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

7 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

7.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

7.2 MASKING AND PROCESSING FLOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

7.3 INTERRUPTS AND LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

7.4 CONCURRENT & NESTED MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

7.5 INTERRUPT REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

7.6 EXTERNAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

7.6.1 I/O Port Interrupt Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

7.7 EXTERNAL INTERRUPT CONTROL REGISTER (EICR) . . . . . . . . . . . . . . . . . . . . . . . 35

8 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

8.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

8.2 SLOW MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

8.3 WAIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

8.4 ACTIVE-HALT AND HALT MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

8.4.1 ACTIVE-HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

8.4.2 HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

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9 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

9.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

9.2 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

9.2.1 Input Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

9.2.2 Output Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

9.2.3 Alternate Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

9.3 I/O PORT IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

9.4 LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

9.5 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

9.5.1 I/O Port Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

10 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

10.1 WATCHDOG TIMER (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

10.1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

10.1.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

10.1.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

10.1.4 How to Program the Watchdog Timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

10.1.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

10.1.6 Hardware Watchdog Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

10.1.7 Using Halt Mode with the WDG (WDGHALT option) . . . . . . . . . . . . . . . . . . . . . . . 51

10.1.8 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

10.1.9 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

10.2 MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK AND BEEPER (MCC/RTC) . 53

10.2.1 Programmable CPU Clock Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

10.2.2 Clock-out Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

10.2.3 Real Time Clock Timer (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

10.2.4 Beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

10.2.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

10.2.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

10.2.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

10.3 16-BIT TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

10.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

10.3.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

10.3.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

10.3.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

10.3.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

10.3.6 Summary of Timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

10.3.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

10.4 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

10.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

10.4.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

10.4.3 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

10.4.4 Clock Phase and Clock Polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

10.4.5 Error Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

10.4.6 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

10.4.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

10.4.8 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

10.5 SERIAL COMMUNICATIONS INTERFACE (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

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10.5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

10.5.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

10.5.3 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

10.5.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

10.5.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

10.5.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

10.5.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

10.6 10-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

10.6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

10.6.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

10.6.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

10.6.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

10.6.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

10.6.6 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

11 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

11.1 CPU ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

11.1.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

11.1.2 Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

11.1.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

11.1.4 Indexed (No Offset, Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

11.1.5 Indirect (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

11.1.6 Indirect Indexed (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

11.1.7 Relative mode (Direct, Indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

11.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

12 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

12.1 PARAMETER CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

12.1.1 Minimum and Maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

12.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

12.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

12.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

12.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

12.2 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

12.2.1 Voltage Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

12.2.2 Current Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

12.2.3 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

12.3 OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

12.3.1 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

12.4 SUPPLY CURRENT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

12.4.1 CURRENT CONSUMPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

12.4.2 Supply and Clock Managers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

12.4.3 On-Chip Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

12.5 CLOCK AND TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

12.5.1 General Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

12.5.2 External Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

12.5.3 Crystal and Ceramic Resonator Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

12.5.4 PLL Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

12.6 MEMORY CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

157

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Table of Contents

12.6.1 RAM and Hardware Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

12.6.2 FLASH Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

12.7 EMC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

12.7.1 Functional EMS (Electro Magnetic Susceptibility) . . . . . . . . . . . . . . . . . . . . . . . . 125

12.7.2 Electro Magnetic Interference (EMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

12.7.3 Absolute Maximum Ratings (Electrical Sensitivity) . . . . . . . . . . . . . . . . . . . . . . . . 127

12.8 I/O PORT PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

12.8.1 General Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

12.8.2 Output Driving Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

12.9 CONTROL PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

12.9.1 Asynchronous RESET Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

12.9.2 ICCSEL/VPP Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

12.10 TIMER PERIPHERAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

12.10.116-Bit Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

12.11 COMMUNICATION INTERFACE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . 135

12.11.1SPI - Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

12.12 10-BIT ADC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

12.12.1Analog Power Supply and Reference Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

12.12.2General PCB Design Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

12.12.3ADC Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

13 PACKAGE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

13.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

13.2 THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

13.3 SOLDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

14 ST7232A DEVICE CONFIGURATION AND ORDERING INFORMATION . . . . . . . . . . . . . . . 145

14.1 FLASH OPTION BYTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

14.2 ROM DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE 147

14.3 VERSION-SPECIFIC SALES CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

14.4 FLASH DEVICE ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

14.5 DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

14.5.1 Socket and Emulator Adapter Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

14.6 ST7 APPLICATION NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

15 KNOWN LIMITATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

15.1 ALL FLASH AND ROM DEVICES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

15.1.1 Safe Connection of OSC1/OSC2 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

15.1.2 Unexpected Reset Fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

15.1.3 Clearing active interrupts outside interrupt routine . . . . . . . . . . . . . . . . . . . . . . . . 154

15.1.4 16-bit Timer PWM Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

15.1.5 SCI Wrong Break duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

15.1.6 39-Pulse ICC Entry Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

15.2 ROM DEVICES ONLY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

15.2.1 I/O Port A and F Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

15.2.2 External clock source with PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

16 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

157

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Table of Contents

To obtain the most recent version of this datasheet,

please check at www.st.com>products>technical literature>datasheet.

Please also pay special attention to the Section “KNOWN LIMITATIONS” on page 154.

6/157

157

ST7232A

1 INTRODUCTION

The ST72F32A and ST7232A devices are members of the ST7 microcontroller family designed for the 5V operating range.

The 32 and 44-pin devices are designed for midrange applications

All devices are based on a common industrystandard 8-bit core, featuring an enhanced instruction set and are available with FLASH or ROM program memory.

Figure 1. Device Block Diagram

8-BIT CORE

ALU

RESET

OSC1 OSC2

CONTROL

OSC

MCC/RTC/BEEP

PORT F

Under software control, all devices can be placed in WAIT, SLOW, ACTIVE-HALT or HALT mode, reducing power consumption when the application is in idle or stand-by state.

The enhanced instruction set and addressing modes of the ST7 offer both power and flexibility to software developers, enabling the design of highly efficient and compact application code. In addition to standard 8-bit data management, all ST7 microcontrollers feature true bit manipulation, 8x8 unsigned multiplication and indirect addressing modes.

PROGRAM

MEMORY (8K Bytes)

RAM

(384 Bytes)

WATCHDOG

ADDRESS AND DATA BUS

PORT A

AREF

SSA

TIMER A

BEEP

PORT E

SCI

PORT D

10-BIT ADC

PORT B

PORT C

TIMER B

SPI

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ST7232A

2 PIN DESCRIPTION

Figure 2. 32-Pin SDIP Package Pinout

(HS) PB4

AIN0 / PD0 AIN1 / PD1

AREF

SSA

MCO / AIN8 / PF0

BEEP / (HS) PF1

OCMP1_A / AIN10 / PF4

ICAP1_A / (HS) PF6

EXTCLK_A / (HS) PF7

AIN12 / OCMP2_B / PC0 AIN13 / OCMP1_B / PC1

ICAP2_B / (HS) PC2 ICAP1_B / (HS) PC3

ICCDATA/ MISO / PC4

AIN14 / MOSI / PC5

Figure 3. 32-Pin TQFP 7x7 Package Pinout

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

ei3

ei1

ei0

ei2

PB3

PB0

PE1 / RDI

PE0 / TDO

28 27 26 25 24 23 22 21 20 19 18 17

OSC1 OSC2

VSS_2 RESET

PA7 (HS) PA6 (HS)

PA4 (HS) PA3 (HS) PC7 / SS / AIN15

PC6 / SCK / ICCCLK

/ ICCSEL

(HS) 20mA high sink capability eix associated external interrupt vector

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AREF

MCO / AIN8 / PF0

BEEP / (HS) PF1

OCMP1_A / AIN10 / PF4

ICAP1_A / (HS) PF6

EXTCLK_A / (HS) PF7

AIN12 / OCMP2_B / PC0

SSA

PB0

PD1 / AIN1

PD0 / AIN0

PB4 (HS)

32 31 30 29 28 27 26 25

ei3

2 3

ei1

4 5 6 7 8

9 10111213141516

ICAP2_B / (HS) PC2

ICAP1_B / (HS) PC3

AIN13 / OCMP1_B / PC1

PB3

ei2

ICCDATA / MISO / PC4

AIN14 / MOSI / PC5

PE1 / RDI

ICCCLK / SCK / PC6

PE0 / TDO

ei0

AIN15 / SS / PC7

24 23 22 21 20 19 18 17

(HS) PA3

OSC1 OSC2 VSS_2 RESET V

/ ICCSEL

PA7 (HS) PA6 (HS) PA4 (HS)

(HS) 20mA high sink capability eix associated external interrupt vector

PIN DESCRIPTION (Cont’d)

Figure 4. 42-Pin SDIP and 44-Pin TQFP Package Pinouts

ST7232A

RDI / PE1

(HS) PB4 AIN0 / PD0 AIN1 / PD1 AIN2 / PD2 AIN3 / PD3 AIN4 / PD4

PB0

PB1

PB2 PB3

1 2 3 4 5 6 7 8 9 10 11

(HS) PB4

AIN0 / PD0 AIN1 / PD1 AIN2 / PD2 AIN3 / PD3 AIN4 / PD4 AIN5 / PD5

AREF

SSA

MCO / AIN8 / PF0

BEEP / (HS) PF1

(HS) PF2

AIN10 / OCMP1_A / PF4

ICAP1_A / (HS) PF6

EXTCLK_A / (HS) PF7 AIN12 / OCMP2_B / PC0 AIN13 / OCMP1_B / PC1

ICAP2_B/ (HS) PC2

ICAP1_B / (HS) PC3

ICCDATA / MISO / PC4

AIN14 / MOSI / PC5

PE0 / TDO

OSC1

OSC2

_2 V

/ ICCSEL

RESET

PA7 (HS)

PA6 (HS)

PA5 (HS)

44 43 42 41 40 39 38 37 36 35 34

ei2

ei0

ei3

ei1

12 13 14 15 16 17 18 19 20 21 22

AIN5 / PD5

SSA

AREF

(HS) PF2

BEEP / (HS) PF1

MCO / AIN8 / PF0

OCMP1_A / AIN10 / PF4

ei3 2 3

ei2

4 5 6 7 8 9 10 11

ei1 12 13 14 15 16 17 18 19

ei0 20 21

DD_0

ICAP1_A / (HS) PF6

EXTCLK_A / (HS) PF7

42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22

PA4 (HS)

SS_1

DD_1

PA3 (HS)

PC7 / SS / AIN15

PC6 / SCK / ICCCLK

PC5 / MOSI / AIN14

PC4 / MISO / ICCDATA

PC3 (HS) / ICAP1_B

PC2 (HS) / ICAP2_B

PC1 / OCMP1_B / AIN13

PC0 / OCMP2_B / AIN12

SS_0

PB3 PB2 PB1 PB0 PE1 / RDI PE0 / TDO VDD_2

OSC1

OSC2 VSS_2 RESET V

/ ICCSEL

PA7 (HS) PA6 (HS) PA5 (HS) PA4 (HS) V

SS_1

DD_1

PA3 (HS) PC7 / SS

/ AIN15

PC6 / SCK / ICCCLK

(HS) 20mA high sink capability eix associated external interrupt vector

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ST7232A

PIN DESCRIPTION (Cont’d)

For external pin connection guidelines, refer to See “ELECTRICAL CHARACTERISTICS” on page 113.

Legend / Abbreviations for Table 1:

Type: I = input, O = output, S = supply Input level: A = Dedicated analog input In/Output level: C = CMOS 0.3V

CT= CMOS 0.3VDD/0.7VDD with input trigger

Output level: HS = 20mA high sink (on N-buffer only) Port and control configuration:

– Input: float = floating, wpu = weak pull-up, int = interrupt

– Output: OD = open drain Refer to “I/O PORTS” on page 42 for more details on the software configuration of the I/O ports. The RESET configuration of each pin is shown in bold. This configuration is valid as long as the device is

in reset state.

Table 1. Device Pin Description

/0.7V

, PP = push-pull

, ana = analog ports

Pin n°

TQFP44

SDIP42

TQFP32

Pin Name

SDIP32

Level Port

Type

Input

Output

float

Input Output

wpu

int

ana

function

(after

reset)

Main

6 1 30 1 PB4 (HS) I/O CTHS X ei3 X X Port B4

7 2 31 2 PD0/AIN0 I/O C

8 3 32 3 PD1/AIN1 I/O C

9 4 PD2/AIN2 I/O C

10 5 PD3/AIN3 I/O C 11 6 PD4/AIN4 I/O C 12 7 PD5/AIN5 I/O C 13 8 1 4 V 14 9 2 5 V

AREF

SSA

S Analog Reference Voltage for ADC S Analog Ground Voltage

15 10 3 6 PF0/MCO/AIN8 I/O C

16 11 4 7 PF1 (HS)/BEEP I/O C 17 12 PF2 (HS) I/O C

18 13 5 8

PF4/OCMP1_A/ AIN10

I/O C

19 14 6 9 PF6 (HS)/ICAP1_A I/O C

20 15 7 10

21 V 22 V

23 16 8 11

PF7 (HS)/ EXTCLK_A

DD_0

SS_0

PC0/OCMP2_B/ AIN12

I/O C

S Digital Main Supply Voltage S Digital Ground Voltage

I/O C

X X X X X Port D0 ADC Analog Input 0 X X X X X Port D1 ADC Analog Input 1 X X X X X Port D2 ADC Analog Input 2 X X X X X Port D3 ADC Analog Input 3 X X X X X Port D4 ADC Analog Input 4 X X X X X Port D5 ADC Analog Input 5

X ei1 X X X Port F0

HS X ei1 X X Port F1 Beep signal output HS X ei1 X X Port F2

X XXXXPort F4

HS X X X X Port F6 Timer A Input Capture 1

HS X XXXPort F7

X XXXXPort C0

Alternate Function

)

ADC Analog Input 8

ADC Analog Input 10

Main clock out (f

CPU

Timer A Output Compare 1

Timer A External Clock Source

Timer B Output Compare 2

ADC Analog Input 12

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ST7232A

Pin n°

Pin Name

SDIP42

TQFP44

24 17 9 12

SDIP32

TQFP32

PC1/OCMP1_B/ AIN13

25 18 10 13 PC2 (HS)/ICAP2_B I/O C 26 19 11 14 PC3 (HS)/ICAP1_B I/O C

27 20 12 15

PC4/MISO/ICCDATA

28 21 13 16 PC5/MOSI/AIN14 I/O C

29 22 14 17 PC6/SCK/ICCCLK I/O C

30 23 15 18 PC7/SS/AIN15 I/O C

31 24 16 19 PA3 (HS) I/O C 32 25 V 33 26 V

DD_1

SS_1

34 27 17 20 PA4 (HS) I/O C 35 28 PA5 (HS) I/O C 36 29 18 21 PA6 (HS) I/O C 37 30 19 22 PA7 (HS) I/O CTHS X TPort A7

Level Port

Type

Input

Output

float

Input Output

wpu

int

ana

function

(after

reset)

Main

Alternate Function

Timer B Out-

I/O C

X XXXXPort C1

put Compare 1

HS X X X X Port C2 Timer B Input Capture 2

HS X X X X Port C3 Timer B Input Capture 1

SPI Master

I/O C

X XXXPort C4

In / Slave Out Data

SPI Master

X XXXXPort C5

Out / Slave In Data

X XXXPort C6

SPI Serial Clock

SPI Slave

X XXXXPort C7

Select (active low)

HS X ei0 X X Port A3

S Digital Main Supply Voltage S Digital Ground Voltage

HS X XXXPort A4

HS X XXXPort A5

HS X TPort A6

ADC Analog Input 13

ICC Data Input

ADC Analog Input 14

ICC Clock Output

ADC Analog Input 15

Must be tied low. In the flash programming mode, this pin acts as the

38 31 20 23 V

/ICCSEL I

programming voltage input V

Section 12.9.2 for more details. High

. See

voltage must not be applied to ROM

devices. 39 32 21 24 RESET 40 33 22 25 V

SS_2

I/O C

S Digital Ground Voltage

Top priority non maskable interrupt.

41 34 23 26 OSC2 O Resonator oscillator inverter output

42 35 24 27 OSC1 I

43 36 25 28 V

DD_2

S Digital Main Supply Voltage

44 37 26 29 PE0/TDO I/O C

1 382730 PE1/RDI I/OC

X X X X Port E0 SCI Transmit Data Out X X X X Port E1 SCI Receive Data In

External clock input or Resonator os-

cillator inverter input

Caution: Negative cur-

2 392831 PB0 I/OC

3 40 PB1 I/O C 4 41 PB2 I/O C 5 422932 PB3 I/OC

X ei2 X X Port B0

X ei2 X X Port B1 X ei2 X X Port B2 X ei2 X X Port B3

rent injection not allowed on this pin

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ST7232A

Notes:

1. In the interrupt input column, “eiX” defines the associated external interrupt vector. If the weak pull-up column (wpu) is merged with the interrupt column (int), then the I/O configuration is pull-up interrupt input, else the configuration is floating interrupt input.

2. In the open drain output column, “T” defines a true open drain I/O (P-Buffer and protection diode to V are not implemented). See See “I/O PORTS” on page 42. and Section 12.8 I/O PORT PIN CHARACTER-

ISTICS for more details.

3. OSC1 and OSC2 pins connect a crystal/ceramic resonator, or an external source to the on-chip oscillator; see Section 1 INTRODUCTION and Section 12.5 CLOCK AND TIMING CHARACTERISTICS for more details.

4. On the chip, each I/O port has 8 pads. Pads that are not bonded to external pins are in input pull-up configuration after reset. The configuration of these pads must be kept at reset state to avoid added current consumption.

5. For details refer to Section 12.8.1 on page 128

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3 REGISTER & MEMORY MAP

ST7232A

As shown in Figure 5, the MCU is capable of addressing 64K bytes of memories and I/O registers.

The available memory locations consist of 128 bytes of register locations, up to 384 bytes of RAM and up to 8 Kbytes of user program memory. The RAM space includes up to 256 bytes for the stack from 0100h to 01FFh.

Figure 5. Memory Map

0000h

007Fh 0080h

047Fh 0480h

E000h

FFDFh FFE0h

FFFFh

HW Registers

(see Table 2)

RAM

(384 Bytes)

Reserved

Program Memory

(4K or 8K)

Interrupt & Reset Vectors

(see Table 8)

0080h

00FFh

0100h

01FFh

0200h

027Fh

or 047Fh

The highest address bytes contain the user reset and interrupt vectors.

IMPORTANT: Memory locations marked as “Reserved” must never be accessed. Accessing a reserved area can have unpredictable effects on the device.

Short Addressing RAM (zero page)

256 Bytes Stack

Reserved

E000h

8 KBytes

F000h

4 Kbytes

FFFFh

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ST7232A

Table 2. Hardware Register Map

Address Block

0000h 0001h

Port A

0002h

0003h 0004h

Port B

0005h

0006h 0007h

Port C

0008h

0009h 000Ah

Port D

000Bh

000Ch 000Dh

Port E

000Eh

000Fh 0010h

Port F

0011h

0012h

0020h

Label

PADR PADDR PAOR

PBDR PBDDR PBOR

PCDR PCDDR PCOR

PDADR

PDDDR PDOR

PEDR PEDDR PEOR

PFDR PFDDR PFOR

Port A Data Register Port A Data Direction Register Port A Option Register

Port B Data Register Port B Data Direction Register Port B Option Register

Port C Data Register Port C Data Direction Register Port C Option Register

Port D Data Register Port D Data Direction Register Port D Option Register

Port E Data Register Port E Data Direction Register Port E Option Register

Port F Data Register Port F Data Direction Register Port F Option Register

Reset

Status

00h

00h 00h

00h

00h 00h

00h

00h 00h

00h

00h 00h

00h

00h 00h

00h

00h 00h

Remarks

R/W R/W R/W

R/W

R/W R/W R/W

Reserved Area (15 Bytes)

0021h 0022h 0023h

0024h 0025h 0026h 0027h

SPI

ITC

SPIDR SPICR SPICSR

ISPR0 ISPR1 ISPR2 ISPR3

SPI Data I/O Register SPI Control Register SPI Control/Status Register

Interrupt Software Priority Register 0 Interrupt Software Priority Register 1 Interrupt Software Priority Register 2 Interrupt Software Priority Register 3

xxh 0xh 00h

FFh FFh FFh FFh

0028h EICR External Interrupt Control Register 00h R/W

0029h FLASH FCSR Flash Control/Status Register 00h R/W

002Ah WATCHDOG WDGCR Watchdog Control Register 7Fh R/W

002Bh Reserved Area (1 Byte)

002Ch 002Dh

MCC

MCCSR MCCBCR

Main Clock Control / Status Register Main Clock Controller: Beep Control Register

00h 00h

002Eh

Reserved Area (3 Bytes)

0030h

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R/W R/W R/W

R/W R/W R/W R/W

R/W R/W

ST7232A

Address Block

0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h 0039h 003Ah 003Bh 003Ch 003Dh 003Eh 003Fh

0040h Reserved Area (1 Byte)

0041h 0042h 0043h 0044h 0045h 0046h 0047h 0048h 0049h 004Ah 004Bh 004Ch 004Dh 004Eh 004Fh

TIMER A

TIMER B

Label

TACR2 TACR1 TACSR TAIC1HR TAIC1LR TAOC1HR TAOC1LR TACHR TACLR TAACHR TAACLR TAIC2HR TAIC2LR TAOC2HR TAOC2LR

TBCR2 TBCR1 TBCSR TBIC1HR TBIC1LR TBOC1HR TBOC1LR TBCHR TBCLR TBACHR TBACLR TBIC2HR TBIC2LR TBOC2HR TBOC2LR

Timer A Control Register 2 Timer A Control Register 1 Timer A Control/Status Register Timer A Input Capture 1 High Register Timer A Input Capture 1 Low Register Timer A Output Compare 1 High Register Timer A Output Compare 1 Low Register Timer A Counter High Register Timer A Counter Low Register Timer A Alternate Counter High Register Timer A Alternate Counter Low Register Timer A Input Capture 2 High Register Timer A Input Capture 2 Low Register Timer A Output Compare 2 High Register Timer A Output Compare 2 Low Register

Timer B Control Register 2 Timer B Control Register 1 Timer B Control/Status Register Timer B Input Capture 1 High Register Timer B Input Capture 1 Low Register Timer B Output Compare 1 High Register Timer B Output Compare 1 Low Register Timer B Counter High Register Timer B Counter Low Register Timer B Alternate Counter High Register Timer B Alternate Counter Low Register Timer B Input Capture 2 High Register Timer B Input Capture 2 Low Register Timer B Output Compare 2 High Register Timer B Output Compare 2 Low Register

Reset

Status

00h 00h

xxxx x0xxb

xxh

xxh 80h 00h FFh FCh FFh FCh

xxh

xxh 80h 00h

00h 00h

xxxx x0xxb

xxh

xxh 80h 00h FFh FCh FFh FCh

xxh

xxh 80h 00h

Remarks

R/W R/W R/W Read Only Read Only R/W R/W Read Only Read Only Read Only Read Only Read Only Read Only R/W R/W

0050h 0051h 0052h 0053h 0054h 0055h 0056h 0057h

0058h

006Fh

0070h 0071h 0072h

0073h 007Fh

SCI

ADC

SCISR SCIDR SCIBRR SCICR1 SCICR2 SCIERPR

SCIETPR

ADCCSR ADCDRH ADCDRL

Legend: x=undefined, R/W=read/write

SCI Status Register SCI Data Register SCI Baud Rate Register SCI Control Register 1 SCI Control Register 2 SCI Extended Receive Prescaler Register Reserved area SCI Extended Transmit Prescaler Register

Reserved Area (24 Bytes)

Control/Status Register Data High Register Data Low Register

Reserved Area (13 Bytes)

C0h

xxh 00h

x000 0000h

00h 00h

---

00h

00h 00h 00h

Read Only R/W R/W R/W R/W R/W

R/W

R/W Read Only Read Only

15/157

ST7232A

Notes:

1. The contents of the I/O port DR registers are readable only in output configuration. In input configuration, the values of the I/O pins are returned instead of the DR register contents.

2. The bits associated with unavailable pins must always keep their reset value.

16/157

4 FLASH PROGRAM MEMORY

ST7232A

4.1 Introduction

The ST7 dual voltage High Density Flash (HDFlash) is a non-volatile memory that can be electrically erased as a single block or by individual sectors and programmed on a Byte-by-Byte basis using an external V

supply.

The HDFlash devices can be programmed and erased off-board (plugged in a programming tool) or on-board using ICP (In-Circuit Programming) or IAP (In-Application Programming).

The array matrix organisation allows each sector to be erased and reprogrammed without affecting other sectors.

4.2 Main Features

■ Three Flash programming modes:

– Insertion in a programming tool. In this mode,

all sectors including option bytes can be programmed or erased.

– ICP (In-Circuit Programming). In this mode, all

sectors including option bytes can be programmed or erased without removing the device from the application board.

– IAP (In-Application Programming) In this

mode, all sectors except Sector 0, can be programmed or erased without removing the device from the application board and while the application is running.

■ ICT (In-Circuit Testing) for downloading and

executing user application test patterns in RAM

■ Read-out protection

■ Register Access Security System (RASS) to

prevent accidental programming or erasing

4.3 Structure

The Flash memory is organised in sectors and can be used for both code and data storage.

Depending on the overall Flash memory size in the microcontroller device, there are up to three user sectors (see Table 3). Each of these sectors can be erased independently to avoid unnecessary erasing of the whole Flash memory when only a partial erasing is required.

The first two sectors have a fixed size of 4 Kbytes (see Figure 6). They are mapped in the upper part of the ST7 addressing space so the reset and interrupt vectors are located in Sector 0 (F000hFFFFh).

Table 3. Sectors available in Flash devices

Flash Size (bytes) Available Sectors

4K Sector 0 8K Sectors 0,1

> 8K Sectors 0,1, 2

4.3.1 Read-out Protection

Read-out protection, when selected, provides a protection against Program Memory content extraction and against write access to Flash memory. Even if no protection can be considered as totally unbreakable, the feature provides a very high level of protection for a general purpose microcontroller.

In flash devices, this protection is removed by reprogramming the option. In this case, the entire program memory is first automatically erased.

Read-out protection selection depends on the device type:

– In Flash devices it is enabled and removed

through the FMP_R bit in the option byte.

– In ROM devices it is enabled by mask option

specified in the Option List.

Figure 6. Memory Map and Sector Address

4K 10K 24K 48K

1000h 3FFFh

7FFFh

9FFFh

BFFFh

D7FFh

DFFFh

EFFFh

FFFFh

8K 16K 32K 60K

2Kbytes

8Kbytes 40 Kbytes

16 Kbytes 4 Kbytes 4 Kbytes

24 Kbytes

FLASH MEMORY SIZE

SECTOR 2

52 Kbytes

SECTOR 1 SECTOR 0

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ST7232A

FLASH PROGRAM MEMORY (Cont’d)

4.4 ICC Interface

ICC needs a minimum of 4 and up to 6 pins to be connected to the programming tool (see Figure 7). These pins are:

– RESET –V

: device reset

: device power supply ground

Figure 7. Typical ICC Interface

PROGRAMMING TOOL

APPLICATION POWER SUPPLY

(See Note 3)

OSC2

(See caution)

OSC1

ST7

Notes:

1. If the ICCCLK or ICCDATA pins are only used as outputs in the application, no signal isolation is necessary. As soon as the Programming Tool is plugged to the board, even if an ICC session is not in progress, the ICCCLK and ICCDATA pins are not available for the application. If they are used as inputs by the application, isolation such as a serial resistor has to implemented in case another device forces the signal. Refer to the Programming Tool documentation for recommended resistor values.

2. During the ICC session, the programming tool must control the RESET flicts between the programming tool and the application reset circuit if it drives more than 5mA at high level (push pull output or pull-up resistor<1K). A schottky diode can be used to isolate the application RESET circuit in this case. When using a

pin. This can lead to con-

– ICCCLK: ICC output serial clock pin – ICCDATA: ICC input/output serial data pin – ICCSEL/V

: programming voltage

– OSC1(or OSCIN): main clock input for exter-

nal source (optional)

: application board power supply (option-

–V

al, see Figure 7, Note 3)

ICC CONNECTOR

975 3

10kΩ

ICCSEL/VPP

ICC Cable

RESET

ICCCLK

HE10 CONNECTOR TYPE

246810

ICCDATA

APPLICATION BOARD

ICC CONNECTOR

APPLICATION RESET SOURCE

See Note 2

See Note 1

APPLICATION

I/O

classical RC network with R>1K or a reset management IC with open drain output and pull-up resistor>1K, no additional components are needed. In all cases the user must ensure that no external reset is generated by the application during the ICC session.

3. The use of Pin 7 of the ICC connector depends on the Programming Tool architecture. This pin must be connected when using most ST Programming Tools (it is used to monitor the application power supply). Please refer to the Programming Tool manual.

Caution: External clock ICC entry mode is mandatory. Pin 9 must be connected to the OSC1 or OSCIN pin of the ST7 and OSC2 must be grounded.

18/157

FLASH PROGRAM MEMORY (Cont’d)

ST7232A

4.5 ICP (In-Circuit Programming)

To perform ICP the microcontroller must be switched to ICC (In-Circuit Communication) mode by an external controller or programming tool.

Depending on the ICP code downloaded in RAM, Flash memory programming can be fully customized (number of bytes to program, program locations, or selection serial communication interface for downloading).

When using an STMicroelectronics or third-party programming tool that supports ICP and the specific microcontroller device, the user needs only to implement the ICP hardware interface on the application board (see Figure 7). For more details on the pin locations, refer to the device pinout description.

4.6 IAP (In-Application Programming)

This mode uses a BootLoader program previously stored in Sector 0 by the user (in ICP mode or by plugging the device in a programming tool).

This mode is fully controlled by user software. This allows it to be adapted to the user application, (user-defined strategy for entering programming mode, choice of communications protocol used to fetch the data to be stored, etc.). For example, it is

possible to download code from the SPI, SCI, USB or CAN interface and program it in the Flash. IAP mode can be used to program any of the Flash sectors except Sector 0, which is write/erase protected to allow recovery in case errors occur during the programming operation.

4.7 Related Documentation

For details on Flash programming and ICC protocol, refer to the ST7 Flash Programming Reference Manual and to the ST7 ICC Protocol Reference Manual

4.7.1 Register Description FLASH CONTROL/STATUS REGISTER (FCSR)

Read/Write Reset Value: 0000 0000 (00h)

00000000

This register is reserved for use by Programming Tool software. It controls the Flash programming and erasing operations.

Table 4. Flash Control/Status Register Address and Reset Value

Address

(Hex.)

0029h

Label

FCSR

Reset Value00000000

76543210

19/157

ST7232A

5 CENTRAL PROCESSING UNIT

5.1 INTRODUCTION

This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8-bit data manipulation.

5.2 MAIN FEATURES

■ Enable executing 63 basic instructions

■ Fast 8-bit by 8-bit multiply

■ 17 main addressing modes (with indirect

addressing mode)

■ Two 8-bit index registers

■ 16-bit stack pointer

■ Low power HALT and WAIT modes

■ Priority maskable hardware interrupts

■ Non-maskable software/hardware interrupts

Figure 8. CPU Registers

5.3 CPU REGISTERS

The 6 CPU registers shown in Figure 8 are not present in the memory mapping and are accessed by specific instructions.

Accumulator (A)

The Accumulator is an 8-bit general purpose register used to hold operands and the results of the arithmetic and logic calculations and to manipulate data.

Index Registers (X and Y)

These 8-bit registers are used to create effective addresses or as temporary storage areas for data manipulation. (The Cross-Assembler generates a precede instruction (PRE) to indicate that the following instruction refers to the Y register.)

The Y register is not affected by the interrupt automatic procedures.

Program Counter (PC)

The program counter is a 16-bit register containing the address of the next instruction to be executed by the CPU. It is made of two 8-bit registers PCL (Program Counter Low which is the LSB) and PCH (Program Counter High which is the MSB).

RESET VALUE = XXh

15 8

RESET VALUE = RESET VECTOR @ FFFEh-FFFFh

RESET VALUE = STACK HIGHER ADDRESS

PCH

RESET VALUE =

1C1I1HI0NZ

1X11X1XX

PCL

ACCUMULATOR

X INDEX REGISTER

Y INDEX REGISTER

PROGRAM COUNTER

CONDITION CODE REGISTER

STACK POINTER

X = Undefined Value

20/157

CENTRAL PROCESSING UNIT (Cont’d)

Condition Code Register (CC)

Read/Write Reset Value: 111x1xxx

Bit 1 = Z Zero. This bit is set and cleared by hardware. This bit in-

dicates that the result of the last arithmetic, logical or data manipulation is zero. 0: The result of the last operation is different from

zero.

11I1HI0NZ

1: The result of the last operation is zero.

This bit is accessed by the JREQ and JRNE test The 8-bit Condition Code register contains the interrupt masks and four flags representative of the result of the instruction just executed. This register can also be handled by the PUSH and POP instructions.

These bits can be individually tested and/or controlled by specific instructions.

Arithmetic Management Bits

Bit 4 = H Half carry. This bit is set by hardware when a carry occurs be-

tween bits 3 and 4 of the ALU during an ADD or ADC instructions. It is reset by hardware during the same instructions.

0: No half carry has occurred. 1: A half carry has occurred.

This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD arithmetic subroutines.

Bit 2 = N Negative. This bit is set and cleared by hardware. It is repre-

sentative of the result sign of the last arithmetic, logical or data manipulation. It’s a copy of the re-

sult 7

bit. 0: The result of the last operation is positive or null. 1: The result of the last operation is negative

(i.e. the most significant bit is a logic 1).

This bit is accessed by the JRMI and JRPL instructions.

instructions. Bit 0 = C Carry/borrow.

This bit is set and cleared by hardware and software. It indicates an overflow or an underflow has occurred during the last arithmetic operation. 0: No overflow or underflow has occurred. 1: An overflow or underflow has occurred.

This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC instructions. It is also affected by the “bit test and branch”, shift and rotate instructions.

Interrupt Management Bits

Bit 5,3 = I1, I0 Interrupt The combination of the I1 and I0 bits gives the cur-

rent interrupt software priority.

Interrupt Software Priority I1 I0

Level 0 (main) 1 0 Level 1 0 1 Level 2 0 0 Level 3 (= interrupt disable) 1 1

These two bits are set/cleared by hardware when entering in interrupt. The loaded value is given by the corresponding bits in the interrupt software priority registers (IxSPR). They can be also set/ cleared by software with the RIM, SIM, IRET, HALT, WFI and PUSH/POP instructions.

See the interrupt management chapter for more details.

ST7232A

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ST7232A

CENTRAL PROCESSING UNIT (Cont’d)

Stack Pointer (SP)

Read/Write Reset Value: 01 FFh

15 8

00000001

The least significant byte of the Stack Pointer (called S) can be directly accessed by a LD instruction.

Note: When the lower limit is exceeded, the Stack Pointer wraps around to the stack upper limit, without indicating the stack overflow. The previously stored information is then overwritten and therefore lost. The stack also wraps in case of an underflow.

SP7 SP6 SP5 SP4 SP3 SP2 SP1

SP0

The stack is used to save the return address during a subroutine call and the CPU context during an interrupt. The user may also directly manipulate the stack by means of the PUSH and POP instruc-

The Stack Pointer is a 16-bit register which is always pointing to the next free location in the stack. It is then decremented after data has been pushed onto the stack and incremented before data is popped from the stack (see Figure 9).

Since the stack is 256 bytes deep, the 8 most significant bits are forced by hardware. Following an MCU Reset, or after a Reset Stack Pointer instruction (RSP), the Stack Pointer contains its reset value (the SP7 to SP0 bits are set) which is the stack

tions. In the case of an interrupt, the PCL is stored at the first location pointed to by the SP. Then the other registers are stored in the next locations as shown in Figure 9.

– When an interrupt is received, the SP is decre-

mented and the context is pushed on the stack.

– On return from interrupt, the SP is incremented

and the context is popped from the stack.

A subroutine call occupies two locations and an interrupt five locations in the stack area.

higher address.

Figure 9. Stack Manipulation Example

CALL

Subroutine

Interrupt

Event

PUSH Y POP Y IRET

RET

or RSP

@ 0100h

@ 01FFh

X PCH PCL

PCH PCL

Stack Higher Address = 01FFh Stack Lower Address =

PCH PCL

0100h

A X

PCH

PCL

PCH

PCL

A X

PCH

PCL

PCH

PCL

PCH PCL

22/157

6 SUPPLY, RESET AND CLOCK MANAGEMENT

ST7232A

The device includes a range of utility features for securing the application in critical situations (for example in case of a power brown-out), and reducing the number of external components. An overview is shown in Figure 11.

For more details, refer to dedicated parametric section.

Main features

■ Optional PLL for multiplying the frequency by 2

■ Reset Sequence Manager (RSM)

■ Multi-Oscillator Clock Management (MO)

– 5 Crystal/Ceramic resonator oscillators

6.1 PHASE LOCKED LOOP

If the clock frequency input to the PLL is in the range 2 to 4 MHz, the PLL can be used to multiply

Figure 11. Clock, Reset and Supply Block Diagram

OSC2

OSC1

MULTI-

OSCILLATOR

(MO)

OSC

PLL

(option)

SYSTEM INTEGRITY MANAGEMENT

the frequency by two to obtain an f

OSC2

of 4 to 8 MHz. The PLL is enabled by option byte. If the PLL is disabled, then f

OSC2 = fOSC

/2.

Caution: The PLL is not recommended for applications where timing accuracy is required.

Figure 10. PLL Block Diagram

OSC

PLL x 2

/ 2

OSC2

PLL OPTION BIT

MAIN CLOCK

CONTROLLER

WITH REALTIME

CLOCK (MCC/RTC)

OSC2

CPU

RESET

RESET SEQUENCE

MANAGER

(RSM)

SICSR

WATCHDOG

TIMER (WDG)

WDG

23/157

ST7232A

6.2 MULTI-OSCILLATOR (MO)

The main clock of the ST7 can be generated by two different source types coming from the multioscillator block:

■ an external source

■ 4 crystal or ceramic resonator oscillators

Each oscillator is optimized for a given frequency range in terms of consumption and is selectable through the option byte. The associated hardware configurations are shown in Table 5. Refer to the electrical characteristics section for more details.

Caution: The OSC1 and/or OSC2 pins must not be left unconnected. For the purposes of Failure Mode and Effect Analysis, it should be noted that if the OSC1 and/or OSC2 pins are left unconnected, the ST7 main oscillator may start and, in this configuration, could generate an f

clock frequency

OSC

in excess of the allowed maximum (>16MHz.), putting the ST7 in an unsafe/undefined state. The product behaviour must therefore be considered undefined when the OSC pins are left unconnected.

External Clock Source

In this external clock mode, a clock signal (square, sinus or triangle) with ~50% duty cycle has to drive the OSC1 pin while the OSC2 pin is tied to ground.

Crystal/Ceramic Oscillators

This family of oscillators has the advantage of producing a very accurate rate on the main clock of the ST7. The selection within a list of 4 oscillators with different frequency ranges has to be done by option byte in order to reduce consumption (refer to Section 14.1 on page 145 for more details on

the frequency ranges). In this mode of the multioscillator, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and start-up stabilization time. The loading capacitance values must be adjusted according to the selected oscillator.

These oscillators are not stopped during the RESET phase to avoid losing time in the oscillator start-up phase.

Table 5. ST7 Clock Sources

Hardware Configuration

ST7

OSC1 OSC2

External ClockCrystal/Ceramic Resonators

EXTERNAL

SOURCE

OSC1 OSC2

CAPACITORS

ST7

LOAD

24/157

6.3 RESET SEQUENCE MANAGER (RSM)

ST7232A

6.3.1 Introduction

The reset sequence manager includes two RESET sources as shown in Figure 13:

■ External RESET source pulse

■ Internal WATCHDOG RESET

These sources act on the RESET

pin and it is al-

ways kept low during the delay phase. The RESET service routine vector is fixed at ad-

dresses FFFEh-FFFFh in the ST7 memory map. The basic RESET sequence consists of 3 phases

as shown in Figure 12:

■ Active Phase depending on the RESET source

■ 256 or 4096 CPU clock cycle delay (selected by

option byte)

■ RESET vector fetch

The 256 or 4096 CPU clock cycle delay allows the oscillator to stabilise and ensures that recovery has taken place from the Reset state. The shorter or longer clock cycle delay should be selected by option byte to correspond to the stabilization time of the external oscillator used in the application.

Figure 13. Reset Block Diagram

The RESET vector fetch phase duration is 2 clock cycles.

Figure 12. RESET Sequence Phases

RESET

Active Phase

INTERNAL RESET

256 or 4096 CLOCK CYCLES

6.3.2 Asynchronous External RESET

The RESET output with integrated R

pin is both an input and an open-drain

weak pull-up resistor.

FETCH

VECTOR

This pull-up has no fixed value but varies in accordance with the input voltage. It

can be pulled low by external circuitry to reset the device. See Electrical Characteristic section for more details.

A RESET signal originating from an external source must have a duration of at least t

h(RSTL)in

in order to be recognized (see Figure 14). This detection is asynchronous and therefore the MCU can enter reset state even in HALT mode.

RESET

Filter

PULSE

GENERATOR

WATCHDOG RESET

INTERNAL RESET

25/157

ST7232A

RESET SEQUENCE MANAGER (Cont’d)

The RESET plays a major role in EMS performance. In a noisy environment, it is recommended to follow the guidelines mentioned in the electrical characteristics section.

6.3.3 External Power-On RESET

To start up the microcontroller correctly, the user must ensure by means of an external reset circuit that the reset signal is held low until V the minimum level specified for the selected f frequency.

Figure 14. RESET Sequences

pin is an asynchronous signal which

is over

OSC

A proper reset signal for a slow rising V

supply

can generally be provided by an external RC network connected to the RESET

pin.

6.3.4 Internal Watchdog RESET

The RESET sequence generated by a internal Watchdog counter overflow is shown in Figure 14.

Starting from the Watchdog counter underflow, the device RESET low during at least t

pin acts as an output that is pulled

w(RSTL)out

EXTERNAL RESET SOURCE

RESET PIN

WATCHDOG RESET

RUN

h(RSTL)in

EXTERNAL

RESET

ACTIVE PHASE

WATCHDOG UNDERFLOW

RUN RUN

INTERNAL RESET (256 or 4096 T VECTOR FETCH

WATCHDOG

RESET

ACTIVE PHASE

w(RSTL)out

CPU

)

26/157

6.4 SYSTEM INTEGRITY MANAGEMENT

6.4.1 Register Description SYSTEM INTEGRITY (SI) CONTROL/STATUS REGISTER (SICSR)

Read/Write Reset Value: 0000 000x (00h)

Bit 0 = WDGRF Watchdog reset flag This bit indicates that the last Reset was generat-

ed by the Watchdog peripheral. It is set by hardware (watchdog reset) and cleared by software

0000000

WDG

(writing zero).

Bits 7:1 = Reserved, must be kept cleared.

ST7232A

27/157

ST7232A

7 INTERRUPTS

7.1 INTRODUCTION

The ST7 enhanced interrupt management provides the following features:

■ Hardware interrupts

■ Software interrupt (TRAP)

■ Nested or concurrent interrupt management

with flexible interrupt priority and level management:

– Up to 4 software programmable nesting levels – Up to 16 interrupt vectors fixed by hardware – 2 non maskable events: RESET, TRAP

This interrupt management is based on: – Bit 5 and bit 3 of the CPU CC register (I1:0), – Interrupt software priority registers (ISPRx), – Fixed interrupt vector addresses located at the

high addresses of the memory map (FFE0h to FFFFh) sorted by hardware priority order.

This enhanced interrupt controller guarantees full upward compatibility with the standard (not nested) ST7 interrupt controller.

7.2 MASKING AND PROCESSING FLOW

The interrupt masking is managed by the I1 and I0 bits of the CC register and the ISPRx registers which give the interrupt software priority level of each interrupt vector (see Table 6). The processing flow is shown in Figure 15

When an interrupt request has to be serviced: – Normal processing is suspended at the end of

the current instruction execution.

– The PC, X, A and CC registers are saved onto

the stack.

– I1 and I0 bits of CC register are set according to

the corresponding values in the ISPRx registers of the serviced interrupt vector.

– The PC is then loaded with the interrupt vector of

the interrupt to service and the first instruction of the interrupt service routine is fetched (refer to “Interrupt Mapping” table for vector addresses).

The interrupt service routine should end with the IRET instruction which causes the contents of the saved registers to be recovered from the stack.

Note: As a consequence of the IRET instruction, the I1 and I0 bits will be restored from the stack and the program in the previous level will resume.

Table 6. Interrupt Software Priority Levels

Interrupt software priority Level I1 I0

Level 0 (main) Level 1 0 1 Level 2 0 0 Level 3 (= interrupt disable) 1 1

Low

High

Figure 15. Interrupt Processing Flowchart

RESET

RESTORE PC, X, A, CC

FROM STACK

28/157

PENDING

INTERRUPT

FETCH NEXT

INSTRUCTION

“IRET”

EXECUTE

INSTRUCTION

THE INTERRUPT

STAYS PENDING

TRAP

Interrupt has the same or a

lower software priority

than current one

STACK PC, X, A, CC

LOAD I1:0 FROM INTERRUPT SW REG.

LOAD PC FROM INTERRUPT VECTOR

I1:0

software priority

than current one

Interrupt has a higher

INTERRUPTS (Cont’d)

ST7232A

Servicing Pending Interrupts

As several interrupts can be pending at the same time, the interrupt to be taken into account is determined by the following two-step process:

– the highest software priority interrupt is serviced, – if several interrupts have the same software pri-

ority then the interrupt with the highest hardware priority is serviced first.

Figure 16 describes this decision process.

Figure 16. Priority Decision Process

PENDING

INTERRUPTS

Same

HIGHEST HARDWARE

PRIORITY SERVICED

SOFTWARE

PRIORITY

HIGHEST SOFTWARE

PRIORITY SERVICED

Different

When an interrupt request is not serviced immediately, it is latched and then processed when its software priority combined with the hardware priority becomes the highest one.

Note 1: The hardware priority is exclusive while the software one is not. This allows the previous process to succeed with only one interrupt. Note 2: RESET and TRAP can be considered as having the highest software priority in the decision process.

Different Interrupt Vector Sources

Two interrupt source types are managed by the ST7 interrupt controller: the non-maskable type (RESET,TRAP) and the maskable type (external or from internal peripherals).

Non-Maskable Sources

These sources are processed regardless of the state of the I1 and I0 bits of the CC register (see

Figure 15). After stacking the PC, X, A and CC

registers (except for RESET), the corresponding

vector is loaded in the PC register and the I1 and I0 bits of the CC are set to disable interrupts (level

3). These sources allow the processor to exit HALT mode.

■ TRAP (Non Maskable Software Interrupt)

This software interrupt is serviced when the TRAP instruction is executed. It will be serviced according to the flowchart in Figure 15.

■ RESET

The RESET source has the highest priority in the ST7. This means that the first current routine has the highest software priority (level 3) and the highest hardware priority. See the RESET chapter for more details.

Maskable Sources

Maskable interrupt vector sources can be serviced if the corresponding interrupt is enabled and if its own interrupt software priority (in ISPRx registers) is higher than the one currently being serviced (I1 and I0 in CC register). If any of these two conditions is false, the interrupt is latched and thus remains pending.

■ External Interrupts

External interrupts allow the processor to exit from HALT low power mode. External interrupt sensitivity is software selectable through the External Interrupt Control register (EICR). External interrupt triggered on edge will be latched and the interrupt request automatically cleared upon entering the interrupt service routine. If several input pins of a group connected to the same interrupt line are selected simultaneously, these will be logically ORed.

■ Peripheral Interrupts

Usually the peripheral interrupts cause the MCU to exit from HALT mode except those mentioned in the “Interrupt Mapping” table. A peripheral interrupt occurs when a specific flag is set in the peripheral status registers and if the corresponding enable bit is set in the peripheral control register. The general sequence for clearing an interrupt is based on an access to the status register followed by a read or write to an associated register. Note: The clearing sequence resets the internal latch. A pending interrupt (i.e. waiting for being serviced) will therefore be lost if the clear sequence is executed.

29/157

ST7232A

INTERRUPTS (Cont’d)

7.3 INTERRUPTS AND LOW POWER MODES

All interrupts allow the processor to exit the WAIT low power mode. On the contrary, only external and other specified interrupts allow the processor to exit from the HALT modes (see column “Exit from HALT” in “Interrupt Mapping” table). When several pending interrupts are present while exiting HALT mode, the first one serviced can only be an interrupt with exit from HALT mode capability and it is selected through the same decision process shown in Figure 16.

Note: If an interrupt, that is not able to Exit from HALT mode, is pending with the highest priority when exiting HALT mode, this interrupt is serviced after the first one serviced.

Figure 17. Concurrent Interrupt Management

TRAP

IT0

TRAP

IT1

RIM

IT2

IT1

IT4

IT3

IT1

HARDWARE PRIORITY

MAIN

11 / 10

7.4 CONCURRENT & NESTED MANAGEMENT

The following Figure 17 and Figure 18 show two different interrupt management modes. The first is called concurrent mode and does not allow an interrupt to be interrupted, unlike the nested mode in

Figure 18. The interrupt hardware priority is given

in this order from the lowest to the highest: MAIN, IT4, IT3, IT2, IT1, IT0. The software priority is given for each interrupt.

Warning: A stack overflow may occur without notifying the software of the failure.

SOFTWARE PRIORITY LEVEL

IT0

IT3

IT4

MAIN

3 3 3 3 3 3 3/0

11 11 11 11 11 11

USED STACK = 10 BYTES

Figure 18. Nested Interrupt Management

IT4

IT3

TRAP

IT0

HARDWARE PRIORITY

MAIN

RIM

IT2

IT1

IT4

11 / 10

30/157

IT4

IT0

IT3

IT1

SOFTWARE PRIORITY LEVEL

IT2

MAIN

I1 I0

3 3 2 1 3 3 3/0

11 11 00 01 11 11

USED STACK = 20 BYTES

INTERRUPTS (Cont’d)

7.5 INTERRUPT REGISTER DESCRIPTION

ST7232A

CPU CC REGISTER INTERRUPT BITS

Read/Write Reset Value: 111x 1010 (xAh)

11I1 H I0 NZC

INTERRUPT SOFTWARE PRIORITY REGISTERS (ISPRX)

Read/Write (bit 7:4 of ISPR3 are read only) Reset Value: 1111 1111 (FFh)

ISPR0 I1_3 I0_3 I1_2 I0_2 I1_1 I0_1 I1_0 I0_0

Bit 5, 3 = I1, I0 Software Interrupt Priority These two bits indicate the current interrupt soft-

ISPR1 I1_7 I0_7 I1_6 I0_6 I1_5 I0_5 I1_4 I0_4

ware priority.

Interrupt Software Priority Level I1 I0

Level 0 (main) Level 1 0 1 Level 2 0 0 Level 3 (= interrupt disable*) 1 1

Low

High

These two bits are set/cleared by hardware when entering in interrupt. The loaded value is given by the corresponding bits in the interrupt software priority registers (ISPRx).

They can be also set/cleared by software with the RIM, SIM, HALT, WFI, IRET and PUSH/POP instructions (see “Interrupt Dedicated Instruction Set” table).

*Note: TRAP and RESET events can interrupt a level 3 program.

ISPR2 I1_11 I0_11 I1_10 I0_10 I1_9 I0_9 I1_8 I0_8

ISPR3 1 1 1 1 I1_13 I0_13 I1_12 I0_12

These four registers contain the interrupt software priority of each interrupt vector.

– Each interrupt vector (except RESET and TRAP)

has corresponding bits in these registers where its own software priority is stored. This correspondance is shown in the following table.

Vector address ISPRx bits

FFFBh-FFFAh I1_0 and I0_0 bits* FFF9h-FFF8h I1_1 and I0_1 bits

... ...

FFE1h-FFE0h I1_13 and I0_13 bits

– Each I1_x and I0_x bit value in the ISPRx regis-

ters has the same meaning as the I1 and I0 bits in the CC register.

– Level 0 can not be written (I1_x=1, I0_x=0). In

this case, the previously stored value is kept. (example: previous=CFh, write=64h, result=44h)

The RESET, and TRAP vectors have no software priorities. When one is serviced, the I1 and I0 bits of the CC register are both set.

Caution: If the I1_x and I0_x bits are modified while the interrupt x is executed the following behaviour has to be considered: If the interrupt x is still pending (new interrupt or flag not cleared) and the new software priority is higher than the previous one, the interrupt x is re-entered. Otherwise, the software priority stays unchanged up to the next interrupt request (after the IRET of the interrupt x).

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ST7232A

INTERRUPTS (Cont’d)

Table 7. Dedicated Interrupt Instruction Set

Instruction New Description Function/Example I1 H I0 N Z C

HALT Entering Halt mode 1 0 IRET Interrupt routine return Pop CC, A, X, PC I1 H I0 N Z C JRM Jump if I1:0=11 (level 3) I1:0=11 ? JRNM Jump if I1:0<>11 I1:0<>11 ? POP CC Pop CC from the Stack Mem => CC I1 H I0 N Z C RIM Enable interrupt (level 0 set) Load 10 in I1:0 of CC 1 0 SIM Disable interrupt (level 3 set) Load 11 in I1:0 of CC 1 1 TRAP Software trap Software NMI 1 1 WFI Wait for interrupt 1 0

Note: During the execution of an interrupt routine, the HALT, POPCC, RIM, SIM and WFI instructions change the current software priority up to the next IRET instruction or one of the previously mentioned instructions.

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INTERRUPTS (Cont’d)

Table 8. Interrupt Mapping

ST7232A

N°

10 SCI SCI Peripheral interrupts SCISR 11 Not used FFE4h-FFE5h

Source

Block

RESET Reset

TRAP Software interrupt no no FFFCh-FFFDh

0 Not used FFFAh-FFFBh

1 MCC/RTC

2 ei0 External interrupt port A3..0 3 ei1 External interrupt port F2..0 yes no FFF4h-FFF5h 4 ei2 External interrupt port B3..0 yes no FFF2h-FFF3h 5 ei3 External interrupt port B7..4 yes no FFF0h-FFF1h 6 Not used FFEEh-FFEFh 7 SPI SPI peripheral interrupts 8 TIMER A TIMER A peripheral interrupts TASR no no FFEAh-FFEBh 9 TIMER B TIMER B peripheral interrupts TBSR no no FFE8h-FFE9h

Main clock controller time base interrupt

Description

Label

N/A

MCCSR

N/A

SPICSR yes

Priority

Order

Higher

Priority

Lower

Priority

Exit

from

HALT

yes yes FFFEh-FFFFh

yes yes FFF8h-FFF9h

yes no FFF6h-FFF7h

no no FFE6h-FFE7h

Exit

from

ACTIVE

HALT

no FFECh-FFEDh

Address

Vector

Note 1: Unexpected exit from HALT may occur when SPI is in slave mode.

7.6 EXTERNAL INTERRUPTS

7.6.1 I/O Port Interrupt Sensitivity

The external interrupt sensitivity is controlled by the IPA, IPB and ISxx bits of the EICR register (Figure 19). This control allows to have up to 4 fully independent external interrupt source sensitivities.

Each external interrupt source can be generated on four (or five) different events on the pin:

■ Falling edge

■ Rising edge

■ Falling and rising edge

■ Falling edge and low level

■ Rising edge and high level (only for ei0 and ei2)

To guarantee correct functionality, the sensitivity bits in the EICR register can be modified only when the I1 and I0 bits of the CC register are both set to 1 (level 3). This means that interrupts must be disabled before changing sensitivity.

The pending interrupts are cleared by writing a different value in the ISx[1:0], IPA or IPB bits of the EICR.

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ST7232A

Figure 19. External Interrupt Control bits

PORT A3 INTERRUPT

PAOR.3

PADDR.3

PA3

IPA BIT

PORT F [2:0] INTERRUPTS

PFOR.2

PFDDR.2

PF2

PORT B [3:0] INTERRUPTS

PBOR.3

PBDDR.3

PB3

IPB BIT

EICR

IS20 IS21

SENSITIVITY

CONTROL

EICR

IS20 IS21

SENSITIVITY

CONTROL

EICR

IS10 IS11

SENSITIVITY

CONTROL

PF2 PF1

PF0

PB3 PB2

PB1 PB0

ei0 INTERRUPT SOURCE

ei1 INTERRUPT SOURCE

ei2 INTERRUPT SOURCE

PORT B [7:4] INTERRUPTS

PBOR.7

PBDDR.7

PB7

EICR

IS10 IS11

SENSITIVITY

CONTROL

PB7 PB6

PB5 PB4

ei3 INTERRUPT SOURCE

34/157

INTERRUPTS (Cont’d)

7.7 EXTERNAL INTERRUPT CONTROL REGISTER (EICR)

ST7232A

Read/Write Reset Value: 0000 0000 (00h)

IS11 IS10 IPB IS21 IS20 IPA 0 0

Bit 4:3 = IS2[1:0] ei0 and ei1 sensitivity The interrupt sensitivity, defined using the IS2[1:0] bits, is applied to the following external interrupts:

- ei0 (port A3..0)

Bit 7:6 = IS1[1:0] ei2 and ei3 sensitivity The interrupt sensitivity, defined using the IS1[1:0] bits, is applied to the following external interrupts:

- ei2 (port B3..0)

IS11 IS10

0 1 Rising edge only Falling edge only 1 0 Falling edge only Rising edge only 1 1 Rising and falling edge

External Interrupt Sensitivity

IPB bit =0 IPB bit =1

Falling edge &

low level

Rising edge & high level

- ei3 (port B4)

IS11 IS10 External Interrupt Sensitivity

0 0 Falling edge & low level 0 1 Rising edge only 1 0 Falling edge only 1 1 Rising and falling edge

IS21 IS20

0 1 Rising edge only Falling edge only 1 0 Falling edge only Rising edge only 1 1 Rising and falling edge

- ei1 (port F2..0)

IS21 IS20 External Interrupt Sensitivity

0 0 Falling edge & low level 0 1 Rising edge only 1 0 Falling edge only 1 1 Rising and falling edge

These 2 bits can be written only when I1 and I0 of the CC register are both set to 1 (level 3).

External Interrupt Sensitivity

IPA bit =0 IPA bit =1

Falling edge &

low level

These 2 bits can be written only when I1 and I0 of the CC register are both set to 1 (level 3).

Bit 5 = IPB Interrupt polarity for port B This bit is used to invert the sensitivity of the port B [3:0] external interrupts. It can be set and cleared by software only when I1 and I0 of the CC register are both set to 1 (level 3). 0: No sensitivity inversion

Bit 2 = IPA Interrupt polarity for port A This bit is used to invert the sensitivity of the port A [3:0] external interrupts. It can be set and cleared by software only when I1 and I0 of the CC register are both set to 1 (level 3). 0: No sensitivity inversion 1: Sensitivity inversion

1: Sensitivity inversion

Bits 1:0 = Reserved, must always be kept cleared.

Rising edge & high level

35/157

ST7232A

INTERRUPTS (Cont’d)

Table 9. Nested Interrupts Register Map and Reset Values

Address

(Hex.)

0024h

0025h

0026h

0027h

0028h

Label

ISPR0

Reset Value

ISPR1

Reset Value

ISPR2

Reset Value

ISPR3

Reset Value1111

EICR

Reset Value

76543210

ei1 ei0 MCC + SI

I1_3

I1_7

I1_11

IS11

I0_3

SPI ei3 ei2

I0_7

AVD SCI TIMER B TIMER A

I0_11

IS10

I1_2

I1_6

I1_10

IPB

I0_2

I0_6

I0_10

I1_13

IS21

I1_1

I1_5

I1_9

IS20

I0_1

111

I0_5

I0_9

I0_13

IPA

000

I1_4

I1_8

I1_12

I0_4

I0_8

I0_12

36/157

8 POWER SAVING MODES

ST7232A

8.1 INTRODUCTION

To give a large measure of flexibility to the application in terms of power consumption, four main power saving modes are implemented in the ST7 (see Figure 20): SLOW, WAIT (SLOW WAIT), ACTIVE HALT and HALT.

After a RESET the normal operating mode is selected by default (RUN mode). This mode drives the device (CPU and embedded peripherals) by means of a master clock which is based on the main oscillator frequency divided or multiplied by 2

OSC2

From RUN mode, the different power saving modes may be selected by setting the relevant register bits or by calling the specific ST7 software instruction whose action depends on the oscillator status.

Figure 20. Power Saving Mode Transitions

High

RUN

SLOW

WAIT

8.2 SLOW MODE

This mode has two targets: – To reduce power consumption by decreasing the

internal clock in the device,

– To adapt the internal clock frequency (f

CPU

) to

the available supply voltage.

SLOW mode is controlled by three bits in the MCCSR register: the SMS bit which enables or disables Slow mode and two CPx bits which select the internal slow frequency (f

In this mode, the master clock frequency (f

CPU

OSC2

can be divided by 2, 4, 8 or 16. The CPU and peripherals are clocked at this lower frequency

CPU

Note: SLOW-WAIT mode is activated when entering the WAIT mode while the device is already in SLOW mode.

Figure 21. SLOW Mode Clock Transitions

MCCSR

CPU

OSC2

CP1:0

SMS

/2 f

OSC2

00 01

OSC2

/4 f

OSC2

)

SLOW WAIT

ACTIVE HALT

HALT

Low

POWER CONSUMPTION

NEW SLOW

FREQUENCY

REQUEST

NORMAL RUN MODE

REQUEST

37/157

ST7232A

POWER SAVING MODES (Cont’d)

8.3 WAIT MODE

WAIT mode places the MCU in a low power consumption mode by stopping the CPU. This power saving mode is selected by calling the ‘WFI’ instruction. All peripherals remain active. During WAIT mode, the I[1:0] bits of the CC register are forced to ‘10’, to enable all interrupts. All other registers and memory remain unchanged. The MCU remains in WAIT mode until an interrupt or RESET occurs, whereupon the Program Counter branches to the starting address of the interrupt or Reset service routine. The MCU will remain in WAIT mode until a Reset or an Interrupt occurs, causing it to wake up.

Refer to Figure 22.

Figure 22. WAIT Mode Flow-chart

OSCILLATOR

WFI INSTRUCTION

INTERRUPT

PERIPHERALS CPU I[1:0] BITS

RESET

OSCILLATOR PERIPHERALS CPU I[1:0] BITS

256 OR 4096 CPU CLOCK

CYCLE DELAY

OSCILLATOR PERIPHERALS CPU I[1:0] BITS

ON ON

OFF

ON ON ON

FETCH RESET VECTOR

OR SERVICE INTERRUPT

Note:

1. Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the CC register are set to the current software priority level of the interrupt routine and recovered when the CC register is popped.

38/157

POWER SAVING MODES (Cont’d)

ST7232A

8.4 ACTIVE-HALT AND HALT MODES

ACTIVE-HALT and HALT modes are the two lowest power consumption modes of the MCU. They are both entered by executing the ‘HALT’ instruction. The decision to enter either in ACTIVE-HALT or HALT mode is given by the MCC/RTC interrupt enable flag (OIE bit in MCCSR register).

MCCSR

OIE bit

Power Saving Mode entered when HALT

instruction is executed

0 HALT mode 1 ACTIVE-HALT mode

8.4.1 ACTIVE-HALT MODE

ACTIVE-HALT mode is the lowest power consumption mode of the MCU with a real time clock available. It is entered by executing the ‘HALT’ instruction when the OIE bit of the Main Clock Controller Status register (MCCSR) is set (see Section

10.2 on page 53 for more details on the MCCSR

tion of either an MCC/RTC interrupt, a specific interrupt (see Table 8, “Interrupt Mapping,” on

page 33) or a RESET. When exiting ACTIVE-

HALT mode by means of an interrupt, no 256 or 4096 CPU cycle delay occurs. The CPU resumes operation by servicing the interrupt or by fetching the reset vector which woke it up (see Figure 24).

When entering ACTIVE-HALT mode, the I[1:0] bits in the CC register are forced to ‘10b’ to enable interrupts. Therefore, if an interrupt is pending, the MCU wakes up immediately.

In ACTIVE-HALT mode, only the main oscillator and its associated counter (MCC/RTC) are running to keep a wake-up time base. All other peripherals are not clocked except those which get their clock supply from another clock generator (such as external or auxiliary oscillator).

The safeguard against staying locked in ACTIVEHALT mode is provided by the oscillator interrupt.

Note: As soon as the interrupt capability of one of the oscillators is selected (MCCSR.OIE bit set), entering ACTIVE-HALT mode while the Watchdog is active does not generate a RESET. This means that the device cannot spend more than a defined delay in this power saving mode.

CAUTION: When exiting ACTIVE-HALT mode following an interrupt, OIE bit of MCCSR register must not be cleared before t rupt occurs (t

= 256 or 4096 t

DELAY

after the inter-

DELAY

CPU

delay de-

pending on option byte). Otherwise, the ST7 enters HALT mode for the remaining t

DELAY

period.

Figure 23. ACTIVE-HALT Timing Overview

ACTIVE

HALTRUN RUN

HALT

INSTRUCTION

[MCCSR.OIE=1]

256 OR 4096 CPU

CYCLE DELAY

RESET

INTERRUPT

FETCH

VECTOR

Figure 24. ACTIVE-HALT Mode Flow-chart

HALT INSTRUCTION

(MCCSR.OIE=1)

INTERRUPT

OSCILLATOR PERIPHERALS CPU I[1:0] BITS

256OR4096CPUCLOCK

OSCILLATOR PERIPHERALS CPU I[1:0] BITS

FETCH RESET VECTOR

OR SERVICE INTERRUPT

RESET

CYCLE DELAY

OFF OFF

OFF

ON ON ON

Notes:

1. This delay occurs only if the MCU exits ACTIVEHALT mode by means of a RESET.

2. Peripheral clocked with an external clock source can still be active.

3. Only the MCC/RTC interrupt and some specific interrupts can exit the MCU from ACTIVE-HALT mode (such as external interrupt). Refer to

Table 8, “Interrupt Mapping,” on page 33 for more

details.

4. Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the CC register are set to the current software priority level of the interrupt routine and restored when the CC register is popped.

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ST7232A

POWER SAVING MODES (Cont’d)

8.4.2 HALT MODE

The HALT mode is the lowest power consumption mode of the MCU. It is entered by executing the ‘HALT’ instruction when the OIE bit of the Main Clock Controller Status register (MCCSR) is cleared (see Section 10.2 on page 53 for more details on the MCCSR register).

The MCU can exit HALT mode on reception of either a specific interrupt (see Table 8, “Interrupt

Mapping,” on page 33) or a RESET. When exiting

HALT mode by means of a RESET or an interrupt, the oscillator is immediately turned on and the 256 or 4096 CPU cycle delay is used to stabilize the oscillator. After the start up delay, the CPU resumes operation by servicing the interrupt or by fetching the reset vector which woke it up (see Fig-

ure 26).

When entering HALT mode, the I[1:0] bits in the CC register are forced to ‘10b’to enable interrupts. Therefore, if an interrupt is pending, the MCU wakes up immediately.

In HALT mode, the main oscillator is turned off causing all internal processing to be stopped, including the operation of the on-chip peripherals. All peripherals are not clocked except the ones which get their clock supply from another clock generator (such as an external or auxiliary oscillator).

The compatibility of Watchdog operation with HALT mode is configured by the “WDGHALT” option bit of the option byte. The HALT instruction when executed while the Watchdog system is enabled, can generate a Watchdog RESET (see

Section 14.1 on page 145) for more details.

Figure 25. HALT Timing Overview

HALTRUN RUN

HALT

INSTRUCTION

[MCCSR.OIE=0]

256 OR 4096 CPU

CYCLE DELAY

RESET

INTERRUPT

FETCH

VECTOR

Figure 26. HALT Mode Flow-chart

HALT INSTRUCTION

(MCCSR.OIE=0)

WDGHALT

WATCHDOG

RESET

INTERRUPT

ENABLE

OSCILLATOR PERIPHERALS CPU I[1:0] BITS

256 OR 4096 CPU CLOCK

OSCILLATOR PERIPHERALS CPU I[1:0] BITS

FETCH RESET VECTOR

OR SERVICE INTERRUPT

WATCHDOG

RESET

CYCLE

DISABLE

DELAY

OFF OFF OFF

OFF

ON ON ON

Notes:

1. WDGHALT is an option bit. See option byte section for more details.

2. Peripheral clocked with an external clock source can still be active.

3. Only some specific interrupts can exit the MCU from HALT mode (such as external interrupt). Refer to Table 8, “Interrupt Mapping,” on page 33 for more details.

40/157

POWER SAVING MODES (Cont’d)

8.4.2.1 Halt Mode Recommendations

– Make sure that an external event is available to

wake up the microcontroller from Halt mode.

– When using an external interrupt to wake up the

microcontroller, reinitialize the corresponding I/O as “Input Pull-up with Interrupt” before executing the HALT instruction. The main reason for this is that the I/O may be wrongly configured due to external interference or by an unforeseen logical condition.

– For the same reason, reinitialize the level sensi-

tiveness of each external interrupt as a precautionary measure.

ST7232A

– The opcode for the HALT instruction is 0x8E. To

avoid an unexpected HALT instruction due to a program counter failure, it is advised to clear all occurrences of the data value 0x8E from memory. For example, avoid defining a constant in ROM with the value 0x8E.

– As the HALT instruction clears the interrupt mask

in the CC register to allow interrupts, the user may choose to clear all pending interrupt bits before executing the HALT instruction. This avoids entering other peripheral interrupt routines after executing the external interrupt routine corresponding to the wake-up event (reset or external interrupt).

41/157

ST7232A

9 I/O PORTS

9.1 INTRODUCTION

The I/O ports offer different functional modes: – transfer of data through digital inputs and outputs

and for specific pins: – external interrupt generation – alternate signal input/output for the on-chip pe-

ripherals.

An I/O port contains up to 8 pins. Each pin can be programmed independently as digital input (with or without interrupt generation) or digital output.

9.2 FUNCTIONAL DESCRIPTION

Each port has 2 main registers: – Data Register (DR) – Data Direction Register (DDR) and one optional register: – Option Register (OR) Each I/O pin may be programmed using the corre-

sponding register bits in the DDR and OR registers: bit X corresponding to pin X of the port. The same correspondence is used for the DR register.

The following description takes into account the OR register, (for specific ports which do not provide this register refer to the I/O Port Implementation section). The generic I/O block diagram is shown in Figure 27

9.2.1 Input Modes

The input configuration is selected by clearing the corresponding DDR register bit.

In this case, reading the DR register returns the digital value applied to the external I/O pin.

Different input modes can be selected by software through the OR register.

Notes:

1. Writing the DR register modifies the latch value but does not affect the pin status.

2. When switching from input to output mode, the DR register has to be written first to drive the correct level on the pin as soon as the port is configured as an output.

3. Do not use read/modify/write instructions (BSET or BRES) to modify the DR register

External interrupt function

When an I/O is configured as Input with Interrupt, an event on this I/O can generate an external interrupt request to the CPU.

Each pin can independently generate an interrupt request. The interrupt sensitivity is independently programmable using the sensitivity bits in the EICR register.

Each external interrupt vector is linked to a dedicated group of I/O port pins (see pinout description and interrupt section). If several input pins are selected simultaneously as interrupt sources, these are first detected according to the sensitivity bits in the EICR register and then logically ORed.

The external interrupts are hardware interrupts, which means that the request latch (not accessible directly by the application) is automatically cleared when the corresponding interrupt vector is fetched. To clear an unwanted pending interrupt by software, the sensitivity bits in the EICR register must be modified.

9.2.2 Output Modes

The output configuration is selected by setting the corresponding DDR register bit. In this case, writing the DR register applies this digital value to the I/O pin through the latch. Then reading the DR register returns the previously stored value.

Two different output modes can be selected by software through the OR register: Output push-pull and open-drain.

DR register value and output pin status:

DR Push-pull Open-drain

0V 1V

SS DD

Vss

Floating

9.2.3 Alternate Functions

When an on-chip peripheral is configured to use a pin, the alternate function is automatically selected. This alternate function takes priority over the standard I/O programming.

When the signal is coming from an on-chip peripheral, the I/O pin is automatically configured in output mode (push-pull or open drain according to the peripheral).

When the signal is going to an on-chip peripheral, the I/O pin must be configured in input mode. In this case, the pin state is also digitally readable by addressing the DR register.

Note: Input pull-up configuration can cause unexpected value at the input of the alternate peripheral input. When an on-chip peripheral use a pin as input and output, this pin has to be configured in input floating mode.

42/157

I/O PORTS (Cont’d)

Figure 27. I/O Port General Block Diagram

ST7232A

DATA BUS

DDR SEL

DDR

OR SEL

DR SEL

ALTERNATE OUTPUT

ALTERNATE ENABLE

If implemented

PULL-UP CONDITION

N-BUFFER

CMOS SCHMITT TRIGGER

P-BUFFER (see table below)

PULL-UP (see table below)

PAD

DIODES (see table below)

ANALOG

INPUT

EXTERNAL INTERRUPT SOURCE (eix)

Table 10. I/O Port Mode Options

Configuration Mode Pull-Up P-Buffer

Input

Output

Floating with/without Interrupt Off Pull-up with/without Interrupt On Push-pull Open Drain (logic level) Off True Open Drain NI NI NI (see note)

Legend: NI - not implemented

Off - implemented not activated On - implemented and activated

ALTERNATE

INPUT

Diodes

to V

Off

Note: The diode to V true open drain pads. A local protection between the pad and V vice against positive stress.

is implemented to protect the de-

is not implemented in the

to V

43/157

ST7232A

I/O PORTS (Cont’d)

Table 11. I/O Port Configurations

Hardware Configuration

NOT IMPLEMENTED IN TRUE OPEN DRAIN I/O PORTS

INPUT

NOT IMPLEMENTED IN TRUE OPEN DRAIN

I/O PORTS

OPEN-DRAIN OUTPUT

PAD

PULL-UP CONDITION

INTERRUPT CONDITION

DR REGISTER ACCESS

EXTERNAL INTERRUPT SOURCE (eix)

ENABLE OUTPUT

ALTERNATE INPUT

ANALOG INPUT

DR REGISTER ACCESS

ALTERNATEALTERNATE

DATA B U S

R/W

DATA B U S

NOT IMPLEMENTED IN TRUE OPEN DRAIN

I/O PORTS

PUSH-PULL OUTPUT

PAD

ENABLE OUTPUT

DR REGISTER ACCESS

ALTERNATEALTERNATE

R/W

DATA B U S

Notes:

1. When the I/O port is in input configuration and the associated alternate function is enabled as an output, reading the DR register will read the alternate function output status.

2. When the I/O port is in output configuration and the associated alternate function is enabled as an input, the alternate function reads the pin status given by the DR register content.

44/157

I/O PORTS (Cont’d) CAUTION: The alternate function must not be ac-

tivated as long as the pin is configured as input with interrupt, in order to avoid generating spurious interrupts.

Analog alternate function

When the pin is used as an ADC input, the I/O must be configured as floating input. The analog multiplexer (controlled by the ADC registers) switches the analog voltage present on the selected pin to the common analog rail which is connected to the ADC input.

It is recommended not to change the voltage level or loading on any port pin while conversion is in progress. Furthermore it is recommended not to have clocking pins located close to a selected analog pin.

WARNING: The analog input voltage level must be within the limits stated in the absolute maximum ratings.

9.3 I/O PORT IMPLEMENTATION

The hardware implementation on each I/O port depends on the settings in the DDR and OR registers and specific feature of the I/O port such as ADC Input or true open drain.

Switching these I/O ports from one state to another should be done in a sequence that prevents unwanted side effects. Recommended safe transitions are illustrated in Figure 28 Other transitions are potentially risky and should be avoided, since they are likely to present unwanted side-effects such as spurious interrupt generation.

ST7232A

Figure 28. Interrupt I/O Port State Transitions

INPUT

floating/pull-up

interrupt

9.4 LOW POWER MODES

Mode Description

WAIT

HALT

9.5 INTERRUPTS

The external interrupt event generates an interrupt if the corresponding configuration is selected with DDR and OR registers and the interrupt mask in the CC register is not active (RIM instruction).

Interrupt Event

External interrupt on selected external event

INPUT floating

(reset state)

No effect on I/O ports. External interrupts cause the device to exit from WAIT mode.

No effect on I/O ports. External interrupts cause the device to exit from HALT mode.

Event

Flag

OUTPUT

open-drain

Enable

Control

Bit

DDRx

ORx

OUTPUT push-pull

= DDR, OR

Exit from Wait

Yes Yes

Exit

from

Halt

45/157

ST7232A

I/O PORTS (Cont’d)

9.5.1 I/O Port Implementation

The I/O port register configurations are summarised as follows.

Standard Ports

PA5:4, PC7:0, PD5:0, PE1:0, PF7:6, 4

MODE DDR OR

floating input 0 0 pull-up input 0 1 open drain output 1 0 push-pull output 1 1

Interrupt Ports PB4, PB2:0, PF1:0 (with pull-up)

MODE DDR OR

floating input 0 0 pull-up interrupt input 0 1 open drain output 1 0 push-pull output 1 1

PA3, PB3, PF2 (without pull-up)

MODE DDR OR

floating input 0 0 floating interrupt input 0 1 open drain output 1 0 push-pull output 1 1

True Open Drain Ports PA7:6

MODE DDR

floating input 0 open drain (high sink ports) 1

Table 12. Port Configuration

Port Pin name

PA7:6 floating true open-drain

Port A

Port B

Port C PC7:0 floating pull-up open drain push-pull Port D PD5:0 floating pull-up open drain push-pull Port E PE1:0 floating pull-up open drain push-pull

Port F

PA5:4 floating pull-up open drain push-pull PA3 floating floating interrupt open drain push-pull PB3 floating floating interrupt open drain push-pull PB4, PB2:0 floating pull-up interrupt open drain push-pull

PF7:6, 4 floating pull-up open drain push-pull PF2 floating floating interrupt open drain push-pull PF1:0 floating pull-up interrupt open drain push-pull

OR = 0 OR = 1 OR = 0 OR = 1

Input Output

46/157

I/O PORTS (Cont’d)

Table 13. I/O Port Register Map and Reset Values

ST7232A

Address

(Hex.)

Reset Value

of all I/O port registers

0000h PADR

0002h PAOR 0003h PBDR

0005h PBOR 0006h PCDR

0008h PCOR 0009h PDDR

000Bh PDOR

000Ch PEDR

000Eh PEOR 000Fh PFDR

0011h PFOR

Label

76543210

00000000

MSB LSB0001h PADDR

MSB LSB0004h PBDDR

MSB LSB0007h PCDDR

MSB LSB000Ah PDDDR

MSB LSB000Dh PEDDR

MSB LSB0010h PFDDR

47/157

ST7232A

10 ON-CHIP PERIPHERALS

10.1 WATCHDOG TIMER (WDG)

10.1.1 Introduction

The Watchdog timer is used to detect the occurrence of a software fault, usually generated by external interference or by unforeseen logical conditions, which causes the application program to abandon its normal sequence. The Watchdog circuit generates an MCU reset on expiry of a programmed time period, unless the program refreshes the counter’s contents before the T6 bit becomes cleared.

10.1.2 Main Features

■ Programmable free-running downcounter

■ Programmable reset

■ Reset (if watchdog activated) when the T6 bit

reaches zero

■ Optional reset on HALT instruction

(configurable by option byte)

■ Hardware Watchdog selectable by option byte

10.1.3 Functional Description

The counter value stored in the Watchdog Control register (WDGCR bits T[6:0]), is decremented every 16384 f

cycles (approx.), and the

OSC2

length of the timeout period can be programmed by the user in 64 increments.

If the watchdog is activated (the WDGA bit is set) and when the 7-bit timer (bits T[6:0]) rolls over from 40h to 3Fh (T6 becomes cleared), it initiates a reset cycle pulling low the reset pin for typically 30µs.

The application program must write in the WDGCR register at regular intervals during normal operation to prevent an MCU reset. This downcounter is free-running: it counts down even if the watchdog is disabled. The value to be stored in the WDGCR register must be between FFh and C0h:

– The WDGA bit is set (watchdog enabled) – The T6 bit is set to prevent generating an imme-

diate reset

– The T[5:0] bits contain the number of increments

which represents the time delay before the watchdog produces a reset (see Figure 30. Ap-

proximate Timeout Duration). The timing varies

between a minimum and a maximum value due to the unknown status of the prescaler when writing to the WDGCR register (see Figure 31).

Following a reset, the watchdog is disabled. Once activated it cannot be disabled, except by a reset.

The T6 bit can be used to generate a software reset (the WDGA bit is set and the T6 bit is cleared).

If the watchdog is activated, the HALT instruction will generate a Reset.

Figure 29. Watchdog Block Diagram

OSC2

MCC/RTC

DIV 64

12-BIT MCC

RTC COUNTER

48/157

MSB

LSB

TB[1:0] bits (MCCSR

WDGA

RESET

WATCHDOG CONTROL REGISTER (WDGCR)

6-BIT DOWNCOUNTER (CNT)

WDG PRESCALER

DIV 4

WATCHDOG TIMER (Cont’d)

10.1.4 How to Program the Watchdog Timeout

Figure 30 shows the linear relationship between

the 6-bit value to be loaded in the Watchdog Counter (CNT) and the resulting timeout duration in milliseconds. This can be used for a quick calculation without taking the timing variations into account. If

Figure 30. Approximate Timeout Duration

ST7232A

more precision is needed, use the formulae in Fig-

ure 31.

Caution: When writing to the WDGCR register, always write 1 in the T6 bit to avoid generating an immediate reset.

CNT Value (hex.)

1.5 65

503418 82 98 114

Watchdog timeout (ms) @ 8 MHz. f

128

OSC2

49/157

ST7232A

WATCHDOG TIMER (Cont’d)

Figure 31. Exact Timeout Duration (t

min

and t

max

)

WHERE:

= (LSB + 128) x 64 x t

min0

= 16384 x t

max0

OSC2

= 125ns if f

OSC2

=8 MHz

CNT = Value of T[5:0] bits in the WDGCR register (6 bits) MSB and LSB are values from the table below depending on the timebase selected by the TB[1:0] bits

in the MCCSR register

TB1 Bit

(MCCSR Reg.)

0 0 2ms 4 59 0 1 4ms 8 53 1 0 10ms 20 35 1 1 25ms 49 54

To calculate the minimum Watchdog Timeout (t

IF THEN

CNT

MSB

------------4

To calculate the maximum Watchdog Timeout (t

TB0 Bit

(MCCSR Reg.)

ELSE

Selected MCCSR

Timebase

mintmin0

MSB LSB

min

16384 CNT t

16384 C N T

××+=

osc2

–

4CNT

----------------MSB

⎛⎞

× 192 L S B+()64

⎝⎠

max

4CNT

-----------------

××+ t

MSB

×+=

osc2

IF THEN

CNT

≤

MSB

------------4

ELSE

maxtmax0

16384 CNT t

16384 C N T

××+=

osc2

–

4CNT

----------------MSB

⎛⎞

× 192 L S B+()64

⎝⎠

4CNT

-----------------

××+ t

MSB

Note: In the above formulae, division results must be rounded down to the next integer value. Example:

With 2ms timeout selected in MCCSR register

Value of T[5:0] Bits in

WDGCR Register (Hex.)

00 1.496 2.048

3F 128 128.552

Min. Watchdog

Timeout (ms)

min

Max. Watchdog

Timeout (ms)

max

×+=

osc2

50/157

WATCHDOG TIMER (Cont’d)

10.1.5 Low Power Modes

Mode Description

SLOW No effect on Watchdog.

WAIT No effect on Watchdog.

OIE bit in

MCCSR register

WDGHALT bit

in Option

Byte

HALT

0 1 A reset is generated.

ST7232A

No Watchdog reset is generated. The MCU enters Halt mode. The Watchdog counter is decremented once and then stops counting and is no longer able to generate a watchdog reset until the MCU receives an external interrupt or a reset.

If an external interrupt is received, the Watchdog restarts counting after 256 or 4096 CPU clocks. If a reset is generated, the Watchdog is disabled (reset state) unless Hardware Watchdog is selected by option byte. For application recommendations see Section 10.1.7 below.

No reset is generated. The MCU enters Active Halt mode. The Watchdog counter is not decremented. It stop counting. When the MCU receives an oscillator interrupt or external interrupt, the Watchdog restarts counting immediately. When the MCU receives a reset the Watchdog restarts counting after 256 or 4096 CPU clocks.

10.1.6 Hardware Watchdog Option

If Hardware Watchdog is selected by option byte, the watchdog is always active and the WDGA bit in the WDGCR is not used. Refer to the Option Byte description.

10.1.7 Using Halt Mode with the WDG (WDGHALT option)

The following recommendation applies if Halt mode is used when the watchdog is enabled.

– Before executing the HALT instruction, refresh

the WDG counter, to avoid an unexpected WDG reset immediately after waking up the microcontroller.

10.1.8 Interrupts

None.

10.1.9 Register Description CONTROL REGISTER (WDGCR)

Read/Write Reset Value: 0111 1111 (7Fh)

WDGA T6 T5 T4 T3 T2 T1 T0

Bit 7 = WDGA Activation bit. This bit is set by software and only cleared by hardware after a reset. When WDGA = 1, the watchdog can generate a reset. 0: Watchdog disabled 1: Watchdog enabled

Note: This bit is not used if the hardware watchdog option is enabled by option byte.

Bit 6:0 = T[6:0] 7-bit counter (MSB to LSB). These bits contain the value of the watchdog counter. It is decremented every 16384 f

OSC2

cycles (approx.). A reset is produced when it rolls over from 40h to 3Fh (T6 becomes cleared).

51/157

ST7232A

Table 14. Watchdog Timer Register Map and Reset Values

Address

(Hex.)

002Ah

Label

WDGCR

Reset Value

76543210

WDGA

52/157

10.2

MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK AND BEEPER (MCC/RTC)

ST7232A

The Main Clock Controller consists of three different functions:

■

a programmable CPU clock prescaler

■

a clock-out signal to supply external devices

■

a real time clock timer with interrupt capability

Each function can be used independently and simultaneously.

10.2.1

Programmable CPU Clock Prescaler

The programmable CPU clock prescaler supplies the clock for the ST7 CPU and its internal peripherals. It manages SLOW power saving mode (See

Section 8.2 SLOW MODE for more details).

The prescaler selects the f

main clock frequen-

CPU

cy and is controlled by three bits in the MCCSR register: CP[1:0] and SMS.

10.2.2

Clock-out Capability

The clock-out capability is an alternate function of an I/O port pin that outputs a f

Figure 32.

Main Clock Controller (MCC/RTC) Block Diagram

clock to drive

OSC2

BC1 BC0

external devices. It is controlled by the MCO bit in the MCCSR register. CAUTION: When selected, the clock out pin suspends the clock during ACTIVE-HALT mode.

10.2.3

Real Time Clock Timer (RTC)

The counter of the real time clock timer allows an interrupt to be generated based on an accurate real time clock. Four different time bases depending directly on f

are available. The whole

OSC2

functionality is controlled by four bits of the MCCSR register: TB[1:0], OIE and OIF.

When the RTC interrupt is enabled (OIE bit set), the ST7 enters ACTIVE-HALT mode when the HALT instruction is executed. See Section 8.4 AC-

TIVE-HALT AND HALT MODES for more details.

10.2.4

Beeper

The beep function is controlled by the MCCBCR register. It can output three selectable frequencies on the BEEP pin (I/O port alternate function).

OSC2

MCCBCR

DIV 64

MCO

MCCSR

DIV 2, 4, 8, 16

BEEP SIGNAL

SELECTION

12-BIT MCC RTC

COUNTER

SMSCP1 CP0 TB1 TB0 OIE OIF

WATCHDOG

TIMER

MCC/RTC INTERRUPT

CPU

BEEP

MCO

CPU CLOCK

TO CPU AND

PERIPHERALS

53/157

ST7232A

MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK (Cont’d)

10.2.5

Low Power Modes

Mode Description

No effect on MCC/RTC peripheral.

WAIT

ACTIVEHALT

HALT

MCC/RTC interrupt cause the device to exit from WAIT mode.

No effect on MCC/RTC counter (OIE bit is set), the registers are frozen. MCC/RTC interrupt cause the device to exit from ACTIVE-HALT mode.

MCC/RTC counter and registers are frozen. MCC/RTC operation resumes when the MCU is woken up by an interrupt with “exit from HALT” capability.

Bit 6:5 = CP[1:0] CPU clock prescaler These bits select the CPU clock prescaler which is applied in the different slow modes. Their action is conditioned by the setting of the SMS bit. These two bits are set and cleared by software

in SLOW mode CP1 CP0

CPU

f f f

OSC2

/ 2 0 0

OSC2

/ 4 0 1

OSC2

/ 8 1 0

OSC2

/ 16 1 1

10.2.6

Interrupts

The MCC/RTC interrupt event generates an interrupt if the OIE bit of the MCCSR register is set and the interrupt mask in the CC register is not active (RIM instruction).

Interrupt Event

Time base overflow event

Event

Enable

Control

Flag

OIF OIE Yes No

Bit

Exit

from

Wait

Exit

from

Halt

Note: The MCC/RTC interrupt wakes up the MCU from

ACTIVE-HALT mode, not from HALT mode.

10.2.7

Register Description

MCC CONTROL/STATUS REGISTER (MCCSR)

Read/Write Reset Value: 0000 0000 (00h

)

Bit 4 = SMS Slow mode select This bit is set and cleared by software. 0: Normal mode. f 1: Slow mode. f

= f

CPU

OSC2

is given by CP1, CP0 See Section 8.2 SLOW MODE and Section 10.2

MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK AND BEEPER (MCC/RTC) for more de-

tails.

Bit 3:2 = TB[1:0] Time base control These bits select the programmable divider time

base. They are set and cleared by software.

Counter

Prescaler

16000 4ms 2ms 0 0 32000 8ms 4ms 0 1 80000 20ms 10ms 1 0

200000 50ms 25ms 1 1

OSC2

Time Base

=4MHz f

OSC2

A modification of the time base is taken into account at the end of the current period (previously

set) to avoid an unwanted time shift. This allows to use this time base as a real time clock.

MCO CP1 CP0 SMS TB1 TB0 OIE OIF

Bit 7 = MCO Main clock out selection This bit enables the MCO alternate function on the PF0 I/O port. It is set and cleared by software. 0: MCO alternate function disabled (I/O pin free for

general-purpose I/O)

1: MCO alternate function enabled (f

CPU

on I/O

port)

Note: To reduce power consumption, the MCO

Bit 1 = OIE Oscillator interrupt enable This bit set and cleared by software. 0: Oscillator interrupt disabled 1: Oscillator interrupt enabled This interrupt can be used to exit from ACTIVEHALT mode. When this bit is set, calling the ST7 software HALT instruction enters the ACTIVE-HALT power saving

mode

function is not active in ACTIVE-HALT mode.

=8MHz

TB1 TB0

54/157

MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK (Cont’d) Bit 0 = OIF Oscillator interrupt flag

This bit is set by hardware and cleared by software reading the MCCSR register. It indicates when set that the main oscillator has reached the selected elapsed time (TB1:0). 0: Timeout not reached

MCC BEEP CONTROL REGISTER (MCCBCR)

Read/Write Reset Value: 0000 0000 (00h)

1: Timeout reached CAUTION: The BRES and BSET instructions

must not be used on the MCCSR register to avoid unintentionally clearing the OIF bit.

000000BC1BC0

Bit 7:2 = Reserved, must be kept cleared.

Bit 1:0 = BC[1:0] Beep control These 2 bits select the PF1 pin beep capability.

ST7232A

BC1 BC0 Beep mode with f

00 Off

01 ~2-KHz

10 ~1-KHz

1 1 ~500-Hz

The beep output signal is available in ACTIVEHALT mode but has to be disabled to reduce the consumption.

Table 15. Main Clock Controller Register Map and Reset Values

Address

(Hex.)

002Ch

002Dh

Label

MCCSR

Reset Value

MCCBCR

Reset Value000000

76543210

MCO

CP1

CP0

SMS

TB1

TB0

=8MHz

OSC2

Output

Beep signal

~50% duty cycle

OIE

BC1

OIF

BC0

55/157

ST7232A

10.3 16-BIT TIMER

10.3.1 Introduction

The timer consists of a 16-bit free-running counter driven by a programmable prescaler.

It may be used for a variety of purposes, including pulse length measurement of up to two input signals (input capture) or generation of up to two output waveforms (output compare and PWM).

Pulse lengths and waveform periods can be modulated from a few microseconds to several milliseconds using the timer prescaler and the CPU clock prescaler.

Some ST7 devices have two on-chip 16-bit timers. They are completely independent, and do not share any resources. They are synchronized after a MCU reset as long as the timer clock frequencies are not modified.

This description covers one or two 16-bit timers. In ST7 devices with two timers, register names are prefixed with TA (Timer A) or TB (Timer B).

10.3.2 Main Features

■ Programmable prescaler: f

■ Overflow status flag and maskable interrupt

■ External clock input (must be at least 4 times

slower than the CPU

clock speed) with the choice

divided by 2, 4 or 8.

CPU

of active edge

■ 1 or 2 Output Compare functions each with:

– 2 dedicated 16-bit registers – 2 dedicated programmable signals – 2 dedicated status flags – 1 dedicated maskable interrupt

■ 1 or 2 Input Capture functions each with:

– 2 dedicated 16-bit registers – 2 dedicated active edge selection signals – 2 dedicated status flags – 1 dedicated maskable interrupt

■ Pulse width modulation mode (PWM)

■ One pulse mode

■ Reduced Power Mode

■ 5 alternate functions on I/O ports (ICAP1, ICAP2,

OCMP1, OCMP2, EXTCLK)*

The Block Diagram is shown in Figure 33. *Note: Some timer pins may not be available (not

bonded) in some ST7 devices. Refer to the device pin out description.

When reading an input signal on a non-bonded pin, the value will always be ‘1’.

10.3.3 Functional Description

10.3.3.1 Counter

The main block of the Programmable Timer is a 16-bit free running upcounter and its associated 16-bit registers. The 16-bit registers are made up of two 8-bit registers called high & low.

Counter Register (CR):

– Counter High Register (CHR) is the most sig-

nificant byte (MS Byte).

– Counter Low Register (CLR) is the least sig-

nificant byte (LS Byte).

Alternate Counter Register (ACR)

– Alternate Counter High Register (ACHR) is

the most significant byte (MS Byte).

– Alternate Counter Low Register (ACLR) is the

least significant byte (LS Byte).

These two read-only 16-bit registers contain the same value but with the difference that reading the ACLR register does not clear the TOF bit (Timer overflow flag), located in the Status register, (SR), (see note at the end of paragraph titled 16-bit read sequence).

Writing in the CLR register or ACLR register resets the free running counter to the FFFCh value. Both counters have a reset value of FFFCh (this is the only value which is reloaded in the 16-bit timer). The reset value of both counters is also FFFCh in One Pulse mode and PWM mode.

The timer clock depends on the clock control bits of the CR2 register, as illustrated in Table 16 Clock

Control Bits. The value in the counter register re-

peats every 131072, 262144 or 524288 CPU clock cycles depending on the CC[1:0] bits. The timer frequency can be f

CPU

/2, f

CPU

/4, f

CPU

or an external frequency.

Caution: In Flash devices, Timer A functionality has the following restrictions:

– TAOC2HR and TAOC2LR registers are write

only – Input Capture 2 is not implemented – The corresponding interrupts cannot be used

(ICF2, OCF2 forced by hardware to zero)

56/157

16-BIT TIMER (Cont’d)

Figure 33. Timer Block Diagram

CPU

ST7232A

ST7 INTERNAL BUS

MCU-PERIPHERAL INTERFACE

EXTCLK

EXEDG

1/2 1/4

1/8

CC[1:0]

8 high

COUNTER

ALTERNATE

COUNTER

OVERFLOW

DETECT CIRCUIT

8 low

8-bit

buffer

high

OUTPUT

COMPARE REGISTER

OUTPUT COMPARE

CIRCUIT

low

high

low

OUTPUT COMPARE REGISTER

TIMER INTERNAL BUS

16 16

88 8

high

INPUT

CAPTURE

EDGE DETECT

CIRCUIT1

EDGE DETECT

CIRCUIT2

8 8 8

low

high

low

INPUT

CAPTURE

ICAP1

ICAP2

(See note)

TIMER INTERRUPT

ICF2ICF1

OCF2OCF1 TOF

TIMD

(Control/Status Register)

CSR

(Control Register 1) CR1

LATCH1

LATCH2

OC2E

PWMOC1E

OPMFOLV2ICIE OLVL1IEDG1OLVL2FOLV1OCIE TOIE

EXEDG

IEDG2CC0CC1

(Control Register 2) CR2

Note: If IC, OC and TO interrupt requests have separate vectors then the last OR is not present (See device Interrupt Vector Table)

OCMP1

OCMP2

57/157

ST7232A

16-BIT TIMER (Cont’d) 16-bit read sequence: (from either the Counter

Beginning of the sequence

Read

At t0

At t0 +∆t

Sequence completed

The user must read the MS Byte first, then the LS Byte value is buffered automatically.

This buffered value remains unchanged until the 16-bit read sequence is completed, even if the user reads the MS Byte several times.

After a complete reading sequence, if only the CLR register or ACLR register are read, they return the LS Byte of the count value at the time of the read.

Whatever the timer mode used (input capture, output compare, one pulse mode or PWM mode) an overflow occurs when the counter rolls over from FFFFh to 0000h then:

– The TOF bit of the SR register is set. – A timer interrupt is generated if:

– TOIE bit of the CR1 register is set and – I bit of the CC register is cleared.

If one of these conditions is false, the interrupt remains pending to be issued as soon as they are both true.

MS Byte

Other

instructions

Read LS Byte

LS Byte

is buffered

Returns the buffered LS Byte value at t0

Clearing the overflow interrupt request is done in two steps:

1. Reading the SR register while the TOF bit is set.

2. An access (read or write) to the CLR register. Notes: The TOF bit is not cleared by accesses to

ACLR register. The advantage of accessing the ACLR register rather than the CLR register is that it allows simultaneous use of the overflow function and reading the free running counter at random times (for example, to measure elapsed time) without the risk of clearing the TOF bit erroneously.

The timer is not affected by WAIT mode. In HALT mode, the counter stops counting until the

mode is exited. Counting then resumes from the previous count (MCU awakened by an interrupt) or from the reset count (MCU awakened by a Reset).

10.3.3.2 External Clock

The external clock (where available) is selected if CC0=1 and CC1=1 in the CR2 register.

The status of the EXEDG bit in the CR2 register determines the type of level transition on the external clock pin EXTCLK that will trigger the free running counter.

The counter is synchronized with the falling edge of the internal CPU clock.

A minimum of four falling edges of the CPU clock must occur between two consecutive active edges of the external clock; thus the external clock frequency must be less than a quarter of the CPU clock frequency.

58/157

16-BIT TIMER (Cont’d)

Figure 34. Counter Timing Diagram, internal clock divided by 2

CPU CLOCK

INTERNAL RESET

TIMER CLOCK

ST7232A

COUNTER REGISTER

TIMER OVERFLOW FLAG (TOF)

FFFD

FFFE FFFF 0000 0001 0002 0003

Figure 35. Counter Timing Diagram, internal clock divided by 4

CPU CLOCK

INTERNAL RESET

TIMER CLOCK

COUNTER REGISTER

TIMER OVERFLOW FLAG (TOF)

FFFC FFFD 0000 0001

Figure 36. Counter Timing Diagram, internal clock divided by 8

CPU CLOCK

INTERNAL RESET

TIMER CLOCK

COUNTER REGISTER

TIMER OVERFLOW FLAG (TOF)

FFFC FFFD

0000

Note: The MCU is in reset state when the internal reset signal is high, when it is low the MCU is running.

59/157

ST7232A

16-BIT TIMER (Cont’d)

10.3.3.3 Input Capture

In this section, the index, i, may be 1 or 2 because there are 2 input capture functions in the 16-bit timer.

The two 16-bit input capture registers (IC1R and IC2R) are used to latch the value of the free running counter after a transition is detected on the ICAPi pin (see figure 5).

MS Byte LS Byte

ICiR ICiHR ICiLR

ICiR register is a read-only register. The active transition is software programmable

through the IEDGi bit of Control Registers (CRi). Timing resolution is one count of the free running

counter: (

Procedure:

To use the input capture function select the following in the CR2 register:

– Select the timer clock (CC[1:0]) (see Table 16

Clock Control Bits).

– Select the edge of the active transition on the

ICAP2 pin with the IEDG2 bit (the ICAP2 pin must be configured as floating input or input with pull-up without interrupt if this configuration is

available). And select the following in the CR1 register: – Set the ICIE bit to generate an interrupt after an

input capture coming from either the ICAP1 pin

or the ICAP2 pin – Select the edge of the active transition on the

ICAP1 pin with the IEDG1 bit (the ICAP1pin must

be configured as floating input or input with pull-

up without interrupt if this configuration is availa-

ble).

CPU

/CC[1:0]).

When an input capture occurs: – ICFi bit is set. – The ICiR register contains the value of the free

running counter on the active transition on the ICAPi pin (see Figure 38).

– A timer interrupt is generated if the ICIE bit is set

and the I bit is cleared in the CC register. Otherwise, the interrupt remains pending until both conditions become true.

Clearing the Input Capture interrupt request (i.e. clearing the ICFi bit) is done in two steps:

1. Reading the SR register while the ICFi bit is set.

2. An access (read or write) to the ICiLR register.

Notes:

1. After reading the ICiHR register, transfer of input capture data is inhibited and ICFi will never be set until the ICiLR register is also read.

2. The ICiR register contains the free running counter value which corresponds to the most recent input capture.

3. The 2 input capture functions can be used together even if the timer also uses the 2 output compare functions.

4. In One pulse Mode and PWM mode only Input Capture 2 can be used.

5. The alternate inputs (ICAP1 & ICAP2) are always directly connected to the timer. So any transitions on these pins activates the input capture function. Moreover if one of the ICAPi pins is configured as an input and the second one as an output, an interrupt can be generated if the user toggles the output pin and if the ICIE bit is set. This can be avoided if the input capture function i is disabled by reading the ICiHR (see note

1).

6. The TOF bit can be used with interrupt generation in order to measure events that go beyond the timer range (FFFFh).

7. In Flash devices, the ICAP2 registers (TAIC2HR, TAIC2LR) are not available on Timer A. The corresponding interrupts cannot be used (ICF2 is forced by hardware to 0).

60/157

16-BIT TIMER (Cont’d)

Figure 37. Input Capture Block Diagram

ST7232A

ICAP1

ICAP2

EDGE DETECT

CIRCUIT2

IC2R Register

16-BIT

16-BIT FREE RUNNING

COUNTER

EDGE DETECT

CIRCUIT1

IC1R Register

Figure 38. Input Capture Timing Diagram

TIMER CLOCK

ICIE

(Control Register 1) CR1

IEDG1

(Status Register) SR

ICF2ICF1 000

(Control Register 2) CR2

IEDG2

CC0

CC1

COUNTER REGISTER

ICAPi PIN

ICAPi FLAG

ICAPi REGISTER

Note: The rising edge is the active edge.

FF01 FF02 FF03

FF03

61/157

ST7232A

16-BIT TIMER (Cont’d)

10.3.3.4 Output Compare

In this section, the index, i, may be 1 or 2 because there are 2 output compare functions in the 16-bit timer.

This function can be used to control an output waveform or indicate when a period of time has elapsed.

When a match is found between the Output Compare register and the free running counter, the output compare function:

– Assigns pins with a programmable value if the

OCiE bit is set – Sets a flag in the status register – Generates an interrupt if enabled

Two 16-bit registers Output Compare Register 1 (OC1R) and Output Compare Register 2 (OC2R) contain the value to be compared to the counter register each timer clock cycle.

MS Byte LS Byte

OCiROCiHR OCiLR

These registers are readable and writable and are not affected by the timer hardware. A reset event changes the OC

Timing resolution is one count of the free running counter: (

Procedure:

To use the output compare function, select the following in the CR2 register:

– Set the OCiE bit if an output is needed then the

OCMPi pin is dedicated to the output compare i signal.

– Select the timer clock (CC[1:0]) (see Table 16

Clock Control Bits).

And select the following in the CR1 register: – Select the OLVLi bit to applied to the OCMPi pins

after the match occurs. – Set the OCIE bit to generate an interrupt if it is

needed. When a match is found between OCRi register

and CR register: – OCFi bit is set.

iR value to 8000h.

CC[1:0]

CPU/

– The OCMPi pin takes OLVLi bit value (OCMPi

pin latch is forced low during reset).

– A timer interrupt is generated if the OCIE bit is

set in the CR1 register and the I bit is cleared in the CC register (CC).

The OC

iR register value required for a specific tim-

ing application can be calculated using the following formula:

∆t * f

∆ OCiR =

CPU

PRESC

Where:

∆t = Output compare period (in seconds)

= CPU clock frequency (in hertz)

CPU

PRESC

= Timer prescaler factor (2, 4 or 8 de-

pending on CC[1:0] bits, see Table 16

Clock Control Bits)

If the timer clock is an external clock, the formula is:

∆ OCiR = ∆t

* fEXT

Where:

∆t = Output compare period (in seconds)

= External timer clock frequency (in hertz)

EXT

Clearing the output compare interrupt request (i.e. clearing the OCFi bit) is done by:

1. Reading the SR register while the OCFi bit is set.

2. An access (read or write) to the OCiLR register.

The following procedure is recommended to prevent the OCFi bit from being set between the time it is read and the write to the OC

– Write to the OCiHR register (further compares

are inhibited).

– Read the SR register (first step of the clearance

of the OCFi bit, which may be already set).

– Write to the OCiLR register (enables the output

compare function and clears the OCFi bit).

iR register:

62/157

16-BIT TIMER (Cont’d) Notes:

1. After a processor write cycle to the OCiHR reg- ister, the output compare function is inhibited until the OCiLR register is also written.

2. If the OCiE bit is not set, the OCMPi pin is a general I/O port and the OLVLi bit will not appear when a match is found but an interrupt could be generated if the OCIE bit is set.

3. When the timer clock is f

/2, OCFi and

CPU

OCMPi are set while the counter value equals the OCiR register value (see Figure 40 on page

64). This behaviour is the same in OPM or

PWM mode. When the timer clock is f

CPU

/4, f

CPU

/8 or in external clock mode, OCFi and OCMPi are set while the counter value equals the OCiR register value plus 1 (see Figure 41 on page 64).

4. The output compare functions can be used both for generating external events on the OCMPi pins even if the input capture mode is also used.

5. The value in the 16-bit OC

iR register and the

OLVi bit should be changed after each successful comparison in order to control an output waveform or establish a new elapsed timeout.

ST7232A

6. In Flash devices, the TAOC2HR, TAOC2LR registers are "write only" in Timer A. The corresponding event cannot be generated (OCF2 is forced by hardware to 0).

Forced Compare Output capability

When the FOLVi bit is set by software, the OLVLi bit is copied to the OCMPi pin. The OLVi bit has to be toggled in order to toggle the OCMPi pin when it is enabled (OCiE bit=1). The OCFi bit is then not set by hardware, and thus no interrupt request is generated.

The FOLVLi bits have no effect in both one pulse mode and PWM mode.

Figure 39. Output Compare Block Diagram

16 BIT FREE RUNNING

COUNTER

16-bit

OUTPUT COMPARE

CIRCUIT

16-bit

OC1R Register

16-bit

OC2R Register

OC1E CC0CC1

OC2E

(Control Register 2) CR2

(Control Register 1) CR1

FOLV1

FOLV2

(Status Register) SR

OLVL1OLVL2OCIE

000OCF2OCF1

Latch

OCMP1

OCMP2

63/157

ST7232A

16-BIT TIMER (Cont’d)

Figure 40. Output Compare Timing Diagram, f

INTERNAL CPU CLOCK

TIMER CLOCK

TIMER

CPU

COUNTER REGISTER

OUTPUT COMPARE REGISTER i (OCRi)

OUTPUT COMPARE FLAG i (OCFi)

OCMPi PIN (OLVLi=1)

Figure 41. Output Compare Timing Diagram, f

INTERNAL CPU CLOCK

TIMER CLOCK

COUNTER REGISTER

OUTPUT COMPARE REGISTER i (OCRi)

COMPARE REGISTER i LATCH

OUTPUT COMPARE FLAG i (OCFi)

OCMPi PIN (OLVLi=1)

2ED0 2ED1 2ED2

TIMER

CPU

2ED0 2ED1 2ED2

2ED3

2ED42ECF

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16-BIT TIMER (Cont’d)

10.3.3.5 One Pulse Mode

One Pulse mode enables the generation of a pulse when an external event occurs. This mode is selected via the OPM bit in the CR2 register.

The one pulse mode uses the Input Capture1 function and the Output Compare1 function.

Procedure:

To use one pulse mode:

1. Load the OC1R register with the value corresponding to the length of the pulse (see the formula in the opposite column).

2. Select the following in the CR1 register: – Using the OLVL1 bit, select the level to be ap-

plied to the OCMP1 pin after the pulse.

– Using the OLVL2 bit, select the level to be ap-

plied to the OCMP1 pin during the pulse.

– Select the edge of the active transition on the

ICAP1 pin with the IEDG1 bit (the ICAP1 pin must be configured as floating input).

3. Select the following in the CR2 register: – Set the OC1E bit, the OCMP1 pin is then ded-

icated to the Output Compare 1 function. – Set the OPM bit. – Select the timer clock CC[1:0] (see Table 16

Clock Control Bits).

One pulse mode cycle

When

event occurs

on ICAP1

ICR1 = Counter

OCMP1 = OLVL2

Counter is reset

to FFFCh

ICF1 bit is set

When

Counter = OC1R

OCMP1 = OLVL1

Then, on a valid event on the ICAP1 pin, the counter is initialized to FFFCh and OLVL2 bit is loaded on the OCMP1 pin, the ICF1 bit is set and the value FFFDh is loaded in the IC1R register.

Because the ICF1 bit is set when an active edge occurs, an interrupt can be generated if the ICIE bit is set.

ST7232A

Clearing the Input Capture interrupt request (i.e. clearing the ICFi bit) is done in two steps:

1. Reading the SR register while the ICFi bit is set.

2. An access (read or write) to the ICiLR register. The OC1R register value required for a specific

timing application can be calculated using the following formula:

OCiR Value =

* fCPU

PRESC

Where: t = Pulse period (in seconds)

= CPU clock frequency (in hertz)

CPU

PRESC

= Timer prescaler factor (2, 4 or 8 depend-

ing on the CC[1:0] bits, see Table 16

Clock Control Bits)

If the timer clock is an external clock the formula is:

OCiR = t

EXT

-5

Where: t = Pulse period (in seconds)

= External timer clock frequency (in hertz)

EXT

When the value of the counter is equal to the value of the contents of the OC1R register, the OLVL1 bit is output on the OCMP1 pin, (See Figure 42).

Notes:

1. The OCF1 bit cannot be set by hardware in one pulse mode but the OCF2 bit can generate an Output Compare interrupt.

2. When the Pulse Width Modulation (PWM) and One Pulse Mode (OPM) bits are both set, the PWM mode is the only active one.

3. If OLVL1=OLVL2 a continuous signal will be seen on the OCMP1 pin.

4. The ICAP1 pin can not be used to perform input capture. The ICAP2 pin can be used to perform input capture (ICF2 can be set and IC2R can be loaded) but the user must take care that the counter is reset each time a valid edge occurs on the ICAP1 pin and ICF1 can also generates interrupt if ICIE is set.

5. When one pulse mode is used OC1R is dedicated to this mode. Nevertheless OC2R and OCF2 can be used to indicate a period of time has been elapsed but cannot generate an output waveform because the level OLVL2 is dedicated to the one pulse mode.

6. In Flash devices, Timer A OCF2 bit is forced by hardware to 0.

- 5

65/157

ST7232A

16-BIT TIMER (Cont’d)

Figure 42. One Pulse Mode Timing Example

IC1R

COUNTER

ICAP1

OCMP1

01F8

FFFC

FFFD FFFE 2ED0

OLVL2

01F8

2ED1

2ED2

2ED3

FFFC FFFD

OLVL2OLVL1

compare1

Note: IEDG1=1, OC1R=2ED0h, OLVL1=0, OLVL2=1

Figure 43. Pulse Width Modulation Mode Timing Example with 2 Output Compare Functions

COUNTER

OCMP1

FFFC FFFD FFFE

34E2

OLVL2

2ED0 2ED1 2ED2

OLVL1

34E2 FFFC

OLVL2

compare2 compare1 compare2

Note: OC1R=2ED0h, OC2R=34E2, OLVL1=0, OLVL2= 1

66/157

16-BIT TIMER (Cont’d)

10.3.3.6 Pulse Width Modulation Mode

Pulse Width Modulation (PWM) mode enables the generation of a signal with a frequency and pulse length determined by the value of the OC1R and OC2R registers.

Pulse Width Modulation mode uses the complete Output Compare 1 function plus the OC2R register, and so this functionality can not be used when PWM mode is activated.

In PWM mode, double buffering is implemented on the output compare registers. Any new values written in the OC1R and OC2R registers are taken into account only at the end of the PWM period (OC2) to avoid spikes on the PWM output pin (OCMP1).

Procedure

To use pulse width modulation mode:

1. Load the OC2R register with the value corresponding to the period of the signal using the formula in the opposite column.

2. Load the OC1R register with the value corresponding to the period of the pulse if (OLVL1=0 and OLVL2=1) using the formula in the opposite column.

3. Select the following in the CR1 register: – Using the OLVL1 bit, select the level to be ap-

plied to the OCMP1 pin after a successful comparison with the OC1R register.

– Using the OLVL2 bit, select the level to be ap-

plied to the OCMP1 pin after a successful comparison with the OC2R register.

4. Select the following in the CR2 register: – Set OC1E bit: the OCMP1 pin is then dedicat-

ed to the output compare 1 function. – Set the PWM bit. – Select the timer clock (CC[1:0]) (see Table 16

Clock Control Bits).

Pulse Width Modulation cycle

When

Counter

OCMP1 = OLVL1

= OC1R

When

Counter = OC2R

OCMP1 = OLVL2

Counter is reset

to FFFCh

ST7232A

If OLVL1=1 and OLVL2=0 the length of the positive pulse is the difference between the OC2R and OC1R registers.

If OLVL1=OLVL2 a continuous signal will be seen on the OCMP1 pin.

The OC ing application can be calculated using the following formula:

Where: t = Signal or pulse period (in seconds)

CPU

PRESC

If the timer clock is an external clock the formula is:

Where: t = Signal or pulse period (in seconds) f

EXT

The Output Compare 2 event causes the counter to be initialized to FFFCh (See Figure 43)

Notes:

1. After a write instruction to the OCiHR register,

2. The OCF1 and OCF2 bits cannot be set by

3. The ICF1 bit is set by hardware when the coun-

4. In PWM mode the ICAP1 pin can not be used

5. When the Pulse Width Modulation (PWM) and

iR register value required for a specific tim-

OCiR Value =

* fCPU

PRESC

- 5

= CPU clock frequency (in hertz)

= Timer prescaler factor (2, 4 or 8 depend-

ing on CC[1:0] bits, see Table 16)

OCiR = t

-5

EXT

= External timer clock frequency (in hertz)

the output compare function is inhibited until the OCiLR register is also written.

hardware in PWM mode therefore the Output Compare interrupt is inhibited.

ter reaches the OC2R value and can produce a timer interrupt if the ICIE bit is set and the I bit is cleared.

to perform input capture because it is disconnected to the timer. The ICAP2 pin can be used to perform input capture (ICF2 can be set and IC2R can be loaded) but the user must take care that the counter is reset each period and ICF1 can also generates interrupt if ICIE is set.

One Pulse Mode (OPM) bits are both set, the PWM mode is the only active one.

ICF1 bit is set

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ST7232A

16-BIT TIMER (Cont’d)

10.3.4 Low Power Modes

Mode Description

WAIT

HALT

10.3.5 Interrupts

Input Capture 1 event/Counter reset in PWM mode ICF1 Input Capture 2 event ICF2 Yes No Output Compare 1 event (not available in PWM mode) OCF1 Output Compare 2 event (not available in PWM mode) OCF2 Yes No Timer Overflow event TOF TOIE Yes No

No effect on 16-bit Timer. Timer interrupts cause the device to exit from WAIT mode.

16-bit Timer registers are frozen. In HALT mode, the counter stops counting until Halt mode is exited. Counting resumes from the previous

count when the MCU is woken up by an interrupt with “exit from HALT mode” capability or from the counter reset value when the MCU is woken up by a RESET.

If an input capture event occurs on the ICAPi pin, the input capture detection circuitry is armed. Consequently, when the MCU is woken up by an interrupt with “exit from HALT mode” capability, the ICFi bit is set, and the counter value present when exiting from HALT mode is captured into the ICiR register.

Interrupt Event

Event

Flag

Enable

Control

Bit

ICIE

OCIE

Exit from Wait

Yes No

Exit

from

Halt

Note: The 16-bit Timer interrupt events are connected to the same interrupt vector (see Interrupts chap-

ter). These events generate an interrupt if the corresponding Enable Control Bit is set and the interrupt mask in the CC register is reset (RIM instruction).

10.3.6 Summary of Timer modes

MODES

Input Capture (1 and/or 2) Yes Yes Output Compare (1 and/or 2) Yes Yes Yes Yes One Pulse Mode No Not Recommended PWM Mode No Not Recommended

Input Capture 1 Input Capture 2 Output Compare 1 Output Compare 2

TIMER RESOURCES

Yes Yes

No Partially No No

1) See note 4 in Section 10.3.3.5 One Pulse Mode

2) See note 5 and 6 in Section 10.3.3.5 One Pulse Mode

3) See note 4 in Section 10.3.3.6 Pulse Width Modulation Mode

68/157

16-BIT TIMER (Cont’d)

10.3.7 Register Description

Each Timer is associated with three control and status registers, and with six pairs of data registers (16-bit values) relating to the two input captures, the two output compares, the counter and the alternate counter.

ST7232A

Bit 4 = FOLV2 Forced Output Compare 2. This bit is set and cleared by software. 0: No effect on the OCMP2 pin. 1: Forces the OLVL2 bit to be copied to the

OCMP2 pin, if the OC2E bit is set and even if there is no successful comparison.

CONTROL REGISTER 1 (CR1)

Read/Write Reset Value: 0000 0000 (00h)

ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1

Bit 3 = FOLV1 Forced Output Compare 1. This bit is set and cleared by software. 0: No effect on the OCMP1 pin. 1: Forces OLVL1 to be copied to the OCMP1 pin, if

the OC1E bit is set and even if there is no successful comparison.

Bit 2 = OLVL2 Output Level 2.

Bit 7 = ICIE Input Capture Interrupt Enable. 0: Interrupt is inhibited. 1: A timer interrupt is generated whenever the

ICF1 or ICF2 bit of the SR register is set.

Bit 6 = OCIE Output Compare Interrupt Enable. 0: Interrupt is inhibited. 1: A timer interrupt is generated whenever the

OCF1 or OCF2 bit of the SR register is set.

This bit is copied to the OCMP2 pin whenever a successful comparison occurs with the OC2R register and OCxE is set in the CR2 register. This value is copied to the OCMP1 pin in One Pulse Mode and Pulse Width Modulation mode.

Bit 1 = IEDG1 Input Edge 1. This bit determines which type of level transition on the ICAP1 pin will trigger the capture. 0: A falling edge triggers the capture. 1: A rising edge triggers the capture.

Bit 5 = TOIE Timer Overflow Interrupt Enable. 0: Interrupt is inhibited. 1: A timer interrupt is enabled whenever the TOF

bit of the SR register is set.

Bit 0 = OLVL1 Output Level 1. The OLVL1 bit is copied to the OCMP1 pin whenever a successful comparison occurs with the OC1R register and the OC1E bit is set in the CR2 register.

69/157

ST7232A

16-BIT TIMER (Cont’d) CONTROL REGISTER 2 (CR2)

Read/Write Reset Value: 0000 0000 (00h)

OC1E OC2E OPM PWM CC1 CC0 IEDG2 EXEDG

Bit 4 = PWM Pulse Width Modulation. 0: PWM mode is not active. 1: PWM mode is active, the OCMP1 pin outputs a

programmable cyclic signal; the length of the pulse depends on the value of OC1R register; the period depends on the value of OC2R register.

Bit 7 = OC1E Output Compare 1 Pin Enable. This bit is used only to output the signal from the timer on the OCMP1 pin (OLV1 in Output Compare mode, both OLV1 and OLV2 in PWM and one-pulse mode). Whatever the value of the OC1E bit, the Output Compare 1 function of the timer remains active. 0: OCMP1 pin alternate function disabled (I/O pin

free for general-purpose I/O).

1: OCMP1 pin alternate function enabled.

Bit 6 = OC2E Output Compare 2 Pin Enable. This bit is used only to output the signal from the timer on the OCMP2 pin (OLV2 in Output Compare mode). Whatever the value of the OC2E bit, the Output Compare 2 function of the timer remains active. 0: OCMP2 pin alternate function disabled (I/O pin

free for general-purpose I/O).

1: OCMP2 pin alternate function enabled.

Bit 5 = OPM One Pulse Mode. 0: One Pulse Mode is not active. 1: One Pulse Mode is active, the ICAP1 pin can be

used to trigger one pulse on the OCMP1 pin; the active transition is given by the IEDG1 bit. The length of the generated pulse depends on the contents of the OC1R register.

Bit 3, 2 = CC[1:0] Clock Control. The timer clock mode depends on these bits:

Table 16. Clock Control Bits

Timer Clock CC1 CC0

/ 4 0 0

CPU

/ 2 0 1

CPU

/ 8 1 0

CPU

External Clock (where

available)

Note: If the external clock pin is not available, programming the external clock configuration stops the counter.

Bit 1 = IEDG2 Input Edge 2. This bit determines which type of level transition on the ICAP2 pin will trigger the capture. 0: A falling edge triggers the capture. 1: A rising edge triggers the capture.

Bit 0 = EXEDG External Clock Edge. This bit determines which type of level transition on the external clock pin EXTCLK will trigger the counter register. 0: A falling edge triggers the counter register. 1: A rising edge triggers the counter register.

70/157

16-BIT TIMER (Cont’d) CONTROL/STATUS REGISTER (CSR)

Read Only (except bit 2 R/W)

Note: Reading or writing the ACLR register does not clear TOF.

Reset Value: xxxx x0xx (xxh)

ICF1 OCF1 TOF ICF2 OCF2 TIMD 0 0

Bit 4 = ICF2 Input Capture Flag 2. 0: No input capture (reset value). 1: An input capture has occurred on the ICAP2

pin. To clear this bit, first read the SR register, then read or write the low byte of the IC2R

Bit 7 = ICF1 Input Capture Flag 1.

(IC2LR) register. 0: No input capture (reset value). 1: An input capture has occurred on the ICAP1 pin

or the counter has reached the OC2R value in PWM mode. To clear this bit, first read the SR register, then read or write the low byte of the IC1R (IC1LR) register.

Bit 3 = OCF2 Output Compare Flag 2. 0: No match (reset value). 1: The content of the free running counter has

matched the content of the OC2R register. To

clear this bit, first read the SR register, then read

or write the low byte of the OC2R (OC2LR) regBit 6 = OCF1 Output Compare Flag 1.

ister. 0: No match (reset value). 1: The content of the free running counter has

matched the content of the OC1R register. To clear this bit, first read the SR register, then read or write the low byte of the OC1R (OC1LR) register.

Bit 2 = TIMD Timer disable. This bit is set and cleared by software. When set, it freezes the timer prescaler and counter and disabled the output functions (OCMP1 and OCMP2 pins) to reduce power consumption. Access to the

timer registers is still available, allowing the timer Bit 5 = TOF Timer Overflow Flag. 0: No timer overflow (reset value). 1: The free running counter rolled over from FFFFh

to 0000h. To clear this bit, first read the SR reg-

configuration to be changed, or the counter reset,

while it is disabled.

0: Timer enabled

1: Timer prescaler, counter and outputs disabled

ister, then read or write the low byte of the CR (CLR) register.

Bits 1:0 = Reserved, must be kept cleared.

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71/157

ST7232A

16-BIT TIMER (Cont’d) INPUT CAPTURE 1 HIGH REGISTER (IC1HR)

Read Only Reset Value: Undefined

This is an 8-bit read only register that contains the high part of the counter value (transferred by the input capture 1 event).

OUTPUT COMPARE 1 HIGH REGISTER

(OC1HR)

Read/Write

Reset Value: 1000 0000 (80h)

This is an 8-bit register that contains the high part

of the value to be compared to the CHR register.

MSB LSB

INPUT CAPTURE 1 LOW REGISTER (IC1LR)

Read Only Reset Value: Undefined

This is an 8-bit read only register that contains the low part of the counter value (transferred by the input capture 1 event).

MSB LSB

OUTPUT COMPARE 1 LOW REGISTER

(OC1LR)

Read/Write

Reset Value: 0000 0000 (00h)

This is an 8-bit register that contains the low part of

the value to be compared to the CLR register.

MSB LSB

72/157

16-BIT TIMER (Cont’d) OUTPUT COMPARE 2 HIGH REGISTER

(OC2HR)

Read/Write Reset Value: 1000 0000 (80h)

This is an 8-bit register that contains the high part of the value to be compared to the CHR register.

MSB LSB

COUNTER HIGH REGISTER (CHR)

Read Only

Reset Value: 1111 1111 (FFh)

This is an 8-bit register that contains the high part

of the counter value.

MSB LSB

COUNTER LOW REGISTER (CLR) OUTPUT COMPARE 2 LOW REGISTER (OC2LR)

Read/Write Reset Value: 0000 0000 (00h)

This is an 8-bit register that contains the low part of the value to be compared to the CLR register.

Read Only

Reset Value: 1111 1100 (FCh)

This is an 8-bit register that contains the low part of

the counter value. A write to this register resets the

counter. An access to this register after accessing

the CSR register clears the TOF bit.

ST7232A

MSB LSB

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ST7232A

16-BIT TIMER (Cont’d) ALTERNATE COUNTER HIGH REGISTER

(ACHR)

Read Only Reset Value: 1111 1111 (FFh)

This is an 8-bit register that contains the high part of the counter value.

INPUT CAPTURE 2 HIGH REGISTER (IC2HR)

Read Only

Reset Value: Undefined

This is an 8-bit read only register that contains the

high part of the counter value (transferred by the

Input Capture 2 event).

MSB LSB

ALTERNATE COUNTER LOW REGISTER (ACLR)

Read Only Reset Value: 1111 1100 (FCh)

This is an 8-bit register that contains the low part of the counter value. A write to this register resets the counter. An access to this register after an access to CSR register does not clear the TOF bit in the

MSB LSB

INPUT CAPTURE 2 LOW REGISTER (IC2LR)

Read Only

Reset Value: Undefined

This is an 8-bit read only register that contains the

low part of the counter value (transferred by the In-

put Capture 2 event).

CSR register.

MSB LSB

74/157

16-BIT TIMER (Cont’d)

Table 17. 16-Bit Timer Register Map and Reset Values

ST7232A

Address

(Hex.)

Timer A: 32 Timer B: 42

Timer A: 31 Timer B: 41

Timer A: 33 Timer B: 43

Timer A: 34 Timer B: 44

Timer A: 35 Timer B: 45

Timer A: 36 Timer B: 46

Timer A: 37 Timer B: 47

Timer A: 3E Timer B: 4E

Timer A: 3F Timer B: 4F

Timer A: 38 Timer B: 48

Timer A: 39 Timer B: 49

Timer A: 3A Timer B: 4A

Timer A: 3B Timer B: 4B

Timer A: 3C Timer B: 4C

Timer A: 3D Timer B: 4D

Label

CR1

Reset Value

CR2

Reset Value

CSR

Reset Value

IC1HR

Reset Value

IC1LR

Reset Value

OC1HR

Reset Value

OC1LR

Reset Value

OC2HR

Reset Value

OC2LR

Reset Value

CHR

Reset Value

CLR

Reset Value

ACHR

Reset Value

ACLR

Reset Value

IC2HR

Reset Value

IC2LR

Reset Value

76543210

ICIE

OC1E

ICF1

MSB

xxxxxxx

MSB

xxxxxxx

MSB

1000000

MSB

0000000

MSB

1000000

MSB

0000000

MSB

1111111

MSB

1111110

MSB

1111111

MSB

1111110

MSB

xxxxxxx

MSB

xxxxxxx

OCIE

OC2E

OCF1

TOIE0FOLV20FOLV10OLVL20IEDG10OLVL1

OPM

TOF

PWM

ICF2

CC1

OCF2

CC0

TIMD

IEDG20EXEDG

LSB

75/157

ST7232A

10.4 SERIAL PERIPHERAL INTERFACE (SPI)

10.4.1 Introduction

The Serial Peripheral Interface (SPI) allows fullduplex, synchronous, serial communication with external devices. An SPI system may consist of a master and one or more slaves however the SPI interface can not be a master in a multi-master system.

10.4.2 Main Features

■ Full duplex synchronous transfers (on 3 lines)

■ Simplex synchronous transfers (on 2 lines)

■ Master or slave operation

■ Six master mode frequencies (f

■ f

■ SS Management by software or hardware

■ Programmable clock polarity and phase

■ End of transfer interrupt flag

■ Write collision, Master Mode Fault and Overrun

/2 max. slave mode frequency (see note)

CPU

/4 max.)

flags

Figure 44. Serial Peripheral Interface Block Diagram

Data/Address Bus

SPIDR

Read Buffer

Read

Note: In slave mode, continuous transmission is

not possible at maximum frequency due to the

software overhead for clearing status flags and to

initiate the next transmission sequence.

10.4.3 General Description

Figure 44 shows the serial peripheral interface

(SPI) block diagram. There are 3 registers:

– SPI Control Register (SPICR) – SPI Control/Status Register (SPICSR) – SPI Data Register (SPIDR)

The SPI is connected to external devices through

4 pins:

– MISO: Master In / Slave Out data – MOSI: Master Out / Slave In data – SCK: Serial Clock out by SPI masters and in-

put by SPI slaves

Interrupt request

MOSI

MISO

SCK

SOD

bit

8-Bit Shift Register

Write

MASTER

CONTROL

SERIAL CLOCK

GENERATOR

SPIF WCOL MODF

SPIE SPE

OVR SSISSMSOD

SPI

STATE

CONTROL

MSTR

SPR2

CPOL

CPHA

SPICSR

SPICR

SPR1

SPR0

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SERIAL PERIPHERAL INTERFACE (Cont’d)

–SS

: Slave select: This input signal acts as a ‘chip select’ to let the SPI master communicate with slaves individually and to avoid contention on the data lines. Slave SS

inputs can be driven by stand-

ard I/O ports on the master MCU.

10.4.3.1 Functional Description

A basic example of interconnections between a single master and a single slave is illustrated in

Figure 45.

The MOSI pins are connected together and the MISO pins are connected together. In this way data is transferred serially between master and slave (most significant bit first).

Figure 45. Single Master/ Single Slave Application

ST7232A

The communication is always initiated by the master. When the master device transmits data to a slave device via MOSI pin, the slave device responds by sending data to the master device via the MISO pin. This implies full duplex communication with both data out and data in synchronized with the same clock signal (which is provided by the master device via the SCK pin).

To use a single data line, the MISO and MOSI pins must be connected at each node ( in this case only simplex communication is possible).

Four possible data/clock timing relationships may be chosen (see Figure 48) but master and slave must be programmed with the same timing mode.

MASTER

MSBit LSBit MSBit LSBit

+5V

MISO

MOSI

SCK

8-BIT SHIFT REGISTER

SPI

CLOCK

GENERATOR

MISO

MOSI

SCK

SLAVE

Not used if SS is managed by software

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ST7232A

SERIAL PERIPHERAL INTERFACE (Cont’d)

10.4.3.2 Slave Select Management

As an alternative to using the SS Slave Select signal, the application can choose to manage the Slave Select signal by software. This is configured by the SSM bit in the SPICSR register (see Figure 47)

In software management, the external SS free for other application uses and the internal SS signal level is driven by writing to the SSI bit in the SPICSR register.

In Master mode:

–SS

internal must be held high continuously

pin to control the

pin is

In Slave Mode:

There are two cases depending on the data/clock timing relationship (see Figure 46):

If CPHA=1 (data latched on 2nd clock edge):

–SS

internal must be held low during the entire transmission. This implies that in single slave applications the SS V

, or made free for standard I/O by manag-

ing the SS

function by software (SSM= 1 and

pin either can be tied to

SSI=0 in the in the SPICSR register)

If CPHA=0 (data latched on 1st clock edge):

–SS

internal must be held low during byte transmission and pulled high between each byte to allow the slave to write to the shift register. If SS

is not pulled high, a Write Collision error will occur when the slave writes to the shift register (see Section 10.4.5.3).

Figure 46. Generic SS

MOSI/MISO

Master SS

Slave SS

(if CPHA=0)

Slave SS

(if CPHA=1)

Timing Diagram

Byte 1 Byte 2

Figure 47. Hardware/Software Slave Select Management

SSM bit

external pin

SSI bit

SS internal

Byte 3

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SERIAL PERIPHERAL INTERFACE (Cont’d)

10.4.3.3 Master Mode Operation

In master mode, the serial clock is output on the SCK pin. The clock frequency, polarity and phase are configured by software (refer to the description of the SPICSR register).

Note: The idle state of SCK must correspond to the polarity selected in the SPICSR register (by pulling up SCK if CPOL=1 or pulling down SCK if CPOL=0).

To operate the SPI in master mode, perform the following steps in order (if the SPICSR register is not written first, the SPICR register setting (MSTR bit) may be not taken into account):

1. Write to the SPICR register: – Select the clock frequency by configuring the

SPR[2:0] bits.

– Select the clock polarity and clock phase by

configuring the CPOL and CPHA bits. Figure

48 shows the four possible configurations.

Note: The slave must have the same CPOL and CPHA settings as the master.

2. Write to the SPICSR register: – Either set the SSM bit and set the SSI bit or

clear the SSM bit and tie the SS the complete byte transmit sequence.

3. Write to the SPICR register: – Set the MSTR and SPE bits

Note: MSTR and SPE bits remain set only if SS

is high).

The transmit sequence begins when software writes a byte in the SPIDR register.

10.4.3.4 Master Mode Transmit Sequence

When software writes to the SPIDR register, the data byte is loaded into the 8-bit shift register and then shifted out serially to the MOSI pin most significant bit first.

When data transfer is complete:

– The SPIF bit is set by hardware – An interrupt request is generated if the SPIE

bit is set and the interrupt mask in the CCR register is cleared.

Clearing the SPIF bit is performed by the following software sequence:

1. An access to the SPICSR register while the SPIF bit is set

2. A read to the SPIDR register.

pin high for

ST7232A

Note: While the SPIF bit is set, all writes to the

SPIDR register are inhibited until the SPICSR register is read.

10.4.3.5 Slave Mode Operation

In slave mode, the serial clock is received on the SCK pin from the master device.

To operate the SPI in slave mode:

1. Write to the SPICSR register to perform the following actions:

– Select the clock polarity and clock phase by

configuring the CPOL and CPHA bits (see

Figure 48).

Note: The slave must have the same CPOL and CPHA settings as the master.

– Manage the SS

10.4.3.2 and Figure 46. If CPHA=1 SS

be held low continuously. If CPHA=0 SS be held low during byte transmission and pulled up between each byte to let the slave write in the shift register.

2. Write to the SPICR register to clear the MSTR bit and set the SPE bit to enable the SPI I/O functions.

10.4.3.6 Slave Mode Transmit Sequence

When software writes to the SPIDR register, the data byte is loaded into the 8-bit shift register and then shifted out serially to the MISO pin most significant bit first.

The transmit sequence begins when the slave device receives the clock signal and the most significant bit of the data on its MOSI pin.

When data transfer is complete:

– The SPIF bit is set by hardware – An interrupt request is generated if SPIE bit is

set and interrupt mask in the CCR register is cleared.

Clearing the SPIF bit is performed by the following software sequence:

1. An access to the SPICSR register while the SPIF bit is set.

2. A write or a read to the SPIDR register.

Notes: While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR register is read.

The SPIF bit can be cleared during a second transmission; however, it must be cleared before the second SPIF bit in order to prevent an Overrun condition (see Section 10.4.5.2).

pin as described in Section

must

79/157

ST7232A

SERIAL PERIPHERAL INTERFACE (Cont’d)

10.4.4 Clock Phase and Clock Polarity

Four possible timing relationships may be chosen by software, using the CPOL and CPHA bits (See

Figure 48).

Note: The idle state of SCK must correspond to the polarity selected in the SPICSR register (by pulling up SCK if CPOL=1 or pulling down SCK if CPOL=0).

The combination of the CPOL clock polarity and CPHA (clock phase) bits selects the data capture clock edge

Figure 48. Data Clock Timing Diagram

SCK (CPOL = 1)

SCK (CPOL = 0)

Figure 48, shows an SPI transfer with the four

combinations of the CPHA and CPOL bits. The diagram may be interpreted as a master or slave timing diagram where the SCK pin, the MISO pin, the MOSI pin are directly connected between the master and the slave device.

Note: If CPOL is changed at the communication byte boundaries, the SPI must be disabled by resetting the SPE bit.

CPHA =1

MISO

(from master)

MOSI

(from slave)

(to slave)

CAPTURE STROBE

SCK (CPOL = 1)

SCK (CPOL = 0)

MISO

(from master)

MOSI

(from slave)

(to slave)

CAPTURE STROBE

MSBit Bit 6 Bit 5

Bit 4 Bit3 Bit 2 Bit 1 LSBit

Bit 4 Bit3Bit 2Bit 1LSBit

CPHA =0

Bit 4 Bit3 Bit 2 Bit 1 LSBit

80/157

Note:

This figure should not be used as a replacement for parametric information.

Refer to the Electrical Characteristics chapter.

SERIAL PERIPHERAL INTERFACE (Cont’d)

10.4.5 Error Flags

10.4.5.1 Master Mode Fault (MODF)

Master mode fault occurs when the master device has its SS

pin pulled low.

When a Master mode fault occurs:

– The MODF bit is set and an SPI interrupt re-

quest is generated if the SPIE bit is set.

– The SPE bit is reset. This blocks all output

from the device and disables the SPI peripheral.

– The MSTR bit is reset, thus forcing the device

into slave mode.

Clearing the MODF bit is done through a software sequence:

1. A read access to the SPICSR register while the MODF bit is set.

2. A write to the SPICR register.

Notes: To avoid any conflicts in an application with multiple slaves, the SS

pin must be pulled high during the MODF bit clearing sequence. The SPE and MSTR bits may be restored to their original state during or after this clearing sequence.

Hardware does not allow the user to set the SPE and MSTR bits while the MODF bit is set except in the MODF bit clearing sequence.

10.4.5.2 Overrun Condition (OVR)

An overrun condition occurs, when the master device has sent a data byte and the slave device has

ST7232A

not cleared the SPIF bit issued from the previously transmitted byte.

When an Overrun occurs: – The OVR bit is set and an interrupt request is

generated if the SPIE bit is set.

In this case, the receiver buffer contains the byte sent after the SPIF bit was last cleared. A read to the SPIDR register returns this byte. All other bytes are lost.

The OVR bit is cleared by reading the SPICSR register.

10.4.5.3 Write Collision Error (WCOL)

A write collision occurs when the software tries to write to the SPIDR register while a data transfer is taking place with an external device. When this happens, the transfer continues uninterrupted; and the software write will be unsuccessful.

Write collisions can occur both in master and slave mode. See also Section 10.4.3.2 Slave Select

Management.

Note: a "read collision" will never occur since the received data byte is placed in a buffer in which access is always synchronous with the MCU operation.

The WCOL bit in the SPICSR register is set if a write collision occurs.

No SPI interrupt is generated when the WCOL bit is set (the WCOL bit is a status flag only).

Clearing the WCOL bit is done through a software sequence (see Figure 49).

Figure 49. Clearing the WCOL bit (Write Collision Flag) Software Sequence

Clearing sequence after SPIF = 1 (end of a data byte transfer)

1st Step

2nd Step

Read SPICSR

Read SPIDR

RESULT

SPIF =0 WCOL=0

Clearing sequence before SPIF = 1 (during a data byte transfer)

1st Step

2nd Step

Read SPICSR

Read SPIDR

RESULT

WCOL=0

Note: Writing to the SPIDR register instead of reading it does not reset the WCOL bit

81/157

ST7232A

SERIAL PERIPHERAL INTERFACE (Cont’d)

10.4.5.4 Single Master Systems

A typical single master system may be configured, using an MCU as the master and four MCUs as slaves (see Figure 50).

The master device selects the individual slave devices by using four pins of a parallel port to control the four SS

The SS master device ports will be forced to be inputs at that time, thus disabling the slave devices.

Figure 50. Single Master / Multiple Slave Configuration

pins of the slave devices.

pins are pulled high during reset since the

Note: To prevent a bus conflict on the MISO line the master allows only one active slave device during a transmission.

For more security, the slave device may respond to the master with the received data byte. Then the master will receive the previous byte back from the slave device if all MISO and MOSI pins are connected and the slave has not written to its SPIDR register.

Other transmission security methods can use ports for handshake lines or data bytes with command fields.

SCK

MOSI

SCK

Master MCU

SS SS

SCK

Slave MCU

MOSI MOSI MOSIMISO MISO MISOMISO

MISO

Ports

Slave MCU

SCK SCK

Slave MCU

Slave

MCU

82/157

SERIAL PERIPHERAL INTERFACE (Cont’d)

10.4.6 Low Power Modes

Mode Description

WAIT

HALT

No effect on SPI. SPI interrupt events cause the device to exit from WAIT mode.

SPI registers are frozen. In HALT mode, the SPI is inactive. SPI operation resumes when the MCU is woken up by an interrupt with “exit from HALT mode” capability. The data received is subsequently read from the SPIDR register when the software is running (interrupt vector fetching). If several data are received before the wakeup event, then an overrun error is generated. This error can be detected after the fetch of the interrupt routine that woke up the device.

10.4.6.1 Using the SPI to wakeup the MCU from Halt mode

In slave configuration, the SPI is able to wakeup the ST7 device from HALT mode through a SPIF interrupt. The data received is subsequently read from the SPIDR register when the software is running (interrupt vector fetch). If multiple data transfers have been performed before software clears the SPIF bit, then the OVR bit is set by hardware.

ST7232A

Note: When waking up from Halt mode, if the SPI

remains in Slave mode, it is recommended to perform an extra communications cycle to bring the SPI from Halt mode state to normal state. If the SPI exits from Slave mode, it returns to normal state immediately.

Caution: The SPI can wake up the ST7 from Halt mode only if the Slave Select signal (external SS pin or the SSI bit in the SPICSR register) is low when the ST7 enters Halt mode. So if Slave selection is configured as external (see Section

10.4.3.2), make sure the master drives a low level

on the SS

10.4.7 Interrupts

Interrupt Event

SPI End of Transfer Event

Master Mode Fault Event

Overrun Error OVR Yes No

Note: The SPI interrupt events are connected to the same interrupt vector (see Interrupts chapter). They generate an interrupt if the corresponding Enable Control Bit is set and the interrupt mask in

pin when the slave enters Halt mode.

Event

Flag

SPIF

MODF Yes No

Enable

Control

Bit

SPIE

Exit from Wait

Yes Yes

from

Exit

Halt

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ST7232A

SERIAL PERIPHERAL INTERFACE (Cont’d)

10.4.8 Register Description CONTROL REGISTER (SPICR)

Read/Write Reset Value: 0000 xxxx (0xh)

SPIE SPE SPR2 MSTR CPOL CPHA SPR1 SPR0

Bit 7 = SPIE Serial Peripheral Interrupt Enable. This bit is set and cleared by software. 0: Interrupt is inhibited 1: An SPI interrupt is generated whenever

SPIF=1, MODF=1 or OVR=1 in the SPICSR register

Bit 6 = SPE Serial Peripheral Output Enable. This bit is set and cleared by software. It is also cleared by hardware when, in master mode, SS

=0 (see Section 10.4.5.1 Master Mode Fault

(MODF)). The SPE bit is cleared by reset, so the

SPI peripheral is not initially connected to the external pins. 0: I/O pins free for general purpose I/O 1: SPI I/O pin alternate functions enabled

Bit 5 = SPR2 Divider Enable. This bit is set and cleared by software and is cleared by reset. It is used with the SPR[1:0] bits to set the baud rate. Refer to Table 18 SPI Master

mode SCK Frequency.

0: Divider by 2 enabled 1: Divider by 2 disabled

Note: This bit has no effect in slave mode.

Bit 4 = MSTR Master Mode. This bit is set and cleared by software. It is also cleared by hardware when, in master mode, SS

=0 (see Section 10.4.5.1 Master Mode Fault

(MODF)).

0: Slave mode 1: Master mode. The function of the SCK pin

changes from an input to an output and the functions of the MISO and MOSI pins are reversed.

Bit 3 = CPOL Clock Polarity. This bit is set and cleared by software. This bit determines the idle state of the serial Clock. The CPOL bit affects both the master and slave modes. 0: SCK pin has a low level idle state 1: SCK pin has a high level idle state

Note: If CPOL is changed at the communication byte boundaries, the SPI must be disabled by resetting the SPE bit.

Bit 2 = CPHA Clock Phase. This bit is set and cleared by software. 0: The first clock transition is the first data capture

edge.

1: The second clock transition is the first capture

edge.

Note: The slave must have the same CPOL and CPHA settings as the master.

Bits 1:0 = SPR[1:0] Serial Clock Frequency. These bits are set and cleared by software. Used with the SPR2 bit, they select the baud rate of the SPI serial clock SCK output by the SPI in master mode.

Note: These 2 bits have no effect in slave mode.

Table 18. SPI Master mode SCK Frequency

Serial Clock SPR2 SPR1 SPR0

/4 1 0 0

CPU

/8 0 0 0

CPU

/16 0 0 1

CPU

/32 1 1 0

CPU

/64 0 1 0

CPU

/128 0 1 1

CPU

84/157

SERIAL PERIPHERAL INTERFACE (Cont’d) CONTROL/STATUS REGISTER (SPICSR)

Bit 3 = Reserved, must be kept cleared. Read/Write (some bits Read Only) Reset Value: 0000 0000 (00h)

Bit 2 = SOD SPI Output Disable.

This bit is set and cleared by software. When set, it

disables the alternate function of the SPI output

SPIF WCOL OVR MODF - SOD SSM SSI

(MOSI in master mode / MISO in slave mode)

0: SPI output enabled (if SPE=1) Bit 7 = SPIF Serial Peripheral Data Transfer Flag

1: SPI output disabled

(Read only).

This bit is set by hardware when a transfer has been completed. An interrupt is generated if SPIE=1 in the SPICR register. It is cleared by a software sequence (an access to the SPICSR register followed by a write or a read to the SPIDR register).

0: Data transfer is in progress or the flag has been

cleared.

1: Data transfer between the device and an exter-

nal device has been completed.

Bit 1 = SSM SS

This bit is set and cleared by software. When set, it

disables the alternate function of the SPI SS

and uses the SSI bit value instead. See Section

10.4.3.2 Slave Select Management.

0: Hardware management (SS

nal pin)

1: Software management (internal SS

trolled by SSI bit. External SS al-purpose I/O)

Management.

Note: While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR register is read.

Bit 0 = SSI SS

This bit is set and cleared by software. It acts as a

Internal Mode.

‘chip select’ by controlling the level of the SS Bit 6 = WCOL Write Collision status (Read only).

This bit is set by hardware when a write to the SPIDR register is done during a transmit se-

select signal when the SSM bit is set.

0 : Slave selected

1 : Slave deselected quence. It is cleared by a software sequence (see

Figure 49).

0: No write collision occurred 1: A write collision has been detected

DATA I/O REGISTER (SPIDR)

Read/Write

Reset Value: Undefined

Bit 5 = OVR SPI Overrun error (Read only). This bit is set by hardware when the byte currently

D7 D6 D5 D4 D3 D2 D1 D0

being received in the shift register is ready to be transferred into the SPIDR register while SPIF = 1 (See Section 10.4.5.2). An interrupt is generated if SPIE = 1 in SPICR register. The OVR bit is cleared by software reading the SPICSR register. 0: No overrun error 1: Overrun error detected

The SPIDR register is used to transmit and receive

data on the serial bus. In a master device, a write

to this register will initiate transmission/reception

of another byte.

Notes: During the last clock cycle the SPIF bit is

set, a copy of the received data byte in the shift Bit 4 = MODF Mode Fault flag (Read only).

This bit is set by hardware when the SS

pin is pulled low in master mode (see Section 10.4.5.1

Master Mode Fault (MODF)). An SPI interrupt can

be generated if SPIE=1 in the SPICSR register. This bit is cleared by a software sequence (An access to the SPICR register while MODF=1 followed by a write to the SPICR register). 0: No master mode fault detected 1: A fault in master mode has been detected

register is moved to a buffer. When the user reads the serial peripheral data I/O register, the buffer is actually being read.

While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR register is read.

Warning: A write to the SPIDR register places data directly into the shift register for transmission.

A read to the SPIDR register returns the value located in the buffer and not the content of the shift register (see Figure 44).

ST7232A

managed by exter-

signal con-

pin free for gener-

slave

85/157

ST7232A

SERIAL PERIPHERAL INTERFACE (Cont’d)

Table 19. SPI Register Map and Reset Values

Address

(Hex.)

0021h

0022h

0023h

Label

SPIDR

Reset Value

SPICR

Reset Value

SPICSR

Reset Value

76543210

MSB

xxxxxxx

SPIE

SPIF

SPE

WCOL

SPR20MSTR0CPOL

MODF

CPHAxSPR1

SOD

SSM

LSB

SPR0

SSI

86/157

10.5 SERIAL COMMUNICATIONS INTERFACE (SCI)

ST7232A

10.5.1 Introduction

The Serial Communications Interface (SCI) offers a flexible means of full-duplex data exchange with external equipment requiring an industry standard NRZ asynchronous serial data format. The SCI offers a very wide range of baud rates using two baud rate generator systems.

10.5.2 Main Features

■ Full duplex, asynchronous communications

■ NRZ standard format (Mark/Space)

■ Dual baud rate generator systems

■ Independently programmable transmit and

receive baud rates up to 500K baud.

■ Programmable data word length (8 or 9 bits)

■ Receive buffer full, Transmit buffer empty and

End of Transmission flags

■ Two receiver wake-up modes:

– Address bit (MSB) – Idle line

■ Muting function for multiprocessor configurations

■ Separate enable bits for Transmitter and

Receiver

■ Four error detection flags:

– Overrun error – Noise error – Frame error – Parity error

■ Five interrupt sources with flags:

– Transmit data register empty – Transmission complete – Receive data register full – Idle line received – Overrun error detected

■ Parity control:

– Transmits parity bit – Checks parity of received data byte

■ Reduced power consumption mode

10.5.3 General Description

The interface is externally connected to another device by two pins (see Figure 52):

– TDO: Transmit Data Output. When the transmit-

ter and the receiver are disabled, the output pin returns to its I/O port configuration. When the transmitter and/or the receiver are enabled and nothing is to be transmitted, the TDO pin is at high level.

– RDI: Receive Data Input is the serial data input.

Oversampling techniques are used for data recovery by discriminating between valid incoming data and noise.

Through these pins, serial data is transmitted and received as frames comprising:

– An Idle Line prior to transmission or reception – A start bit – A data word (8 or 9 bits) least significant bit first – A Stop bit indicating that the frame is complete. This interface uses two types of baud rate generator: – A conventional type for commonly-used baud

rates,

– An extended type with a prescaler offering a very

wide range of baud rates even with non-standard oscillator frequencies.

87/157

ST7232A

SERIAL COMMUNICATIONS INTERFACE (Cont’d)

Figure 51. SCI Block Diagram

TDO

RDI

Write

Transmit Data Register (TDR)

Transmit Shift Register

TRANSMIT

CONTROL

CR2

Read

(DATA REGISTER) DR

Received Data Register (RDR)

Received Shift Register

R8 T8 SCID M WAKE PCE PS PIE

WAKE

UNIT

SBKRWURETEILIERIETCIETIE

RECEIVER

CONTROL

TDRE TC RDRF IDLE OR NF FE PE

CR1

RECEIVER

CLOCK

88/157

SCI

INTERRUPT

CONTROL

TRANSMITTER

CLOCK

CPU

/16

/PR

TRANSMITTER RATE

CONTROL

BRR

SCP1

CONVENTIONAL BAUD RATE GENERATOR

SCP0

SCT2

SCT1 SCT0 SCR2 SCR1SCR0

RECEIVER RATE CONTROL

SERIAL COMMUNICATIONS INTERFACE (Cont’d)

10.5.4 Functional Description

The block diagram of the Serial Control Interface, is shown in Figure 51. It contains 6 dedicated registers:

– Two control registers (SCICR1 & SCICR2) – A status register (SCISR) – A baud rate register (SCIBRR) – An extended prescaler receiver register (SCIER-

PR)

– An extended prescaler transmitter register (SCI-

ETPR)

Refer to the register descriptions in Section

10.5.7for the definitions of each bit.

Figure 52. Word Length Programming

ST7232A

10.5.4.1 Serial Data Format

Word length may be selected as being either 8 or 9 bits by programming the M bit in the SCICR1 register (see Figure 51).

The TDO pin is in low state during the start bit. The TDO pin is in high state during the stop bit. An Idle character is interpreted as an entire frame

of “1”s followed by the start bit of the next frame which contains data.

A Break character is interpreted on receiving “0”s for some multiple of the frame period. At the end of the last break frame the transmitter inserts an extra “1” bit to acknowledge the start bit.

Transmission and reception are driven by their own baud rate generator.

9-bit Word length (M bit is set)

Data Frame

Start

Bit

Bit0

Bit1

Bit2

Bit3

Idle Frame

Break Frame

8-bit Word length (M bit is reset)

Data Frame

Start

Bit

Bit0

Bit1

Bit2

Bit3

Idle Frame

Break Frame

Bit4

Bit5

Bit6

Possible

Parity

Bit7

Possible

Parity

Bit

Bit7

Bit

Bit8

Stop

Bit

Next Data Frame

Next Start

Stop

Bit

Start

Bit

Extra

’1’

Next Data Frame

Next Start

Bit

Start

Bit

Start

Extra

Bit

’1’

Start

Bit

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ST7232A

SERIAL COMMUNICATIONS INTERFACE (Cont’d)

10.5.4.2 Transmitter

The transmitter can send data words of either 8 or 9 bits depending on the M bit status. When the M bit is set, word length is 9 bits and the 9th bit (the MSB) has to be stored in the T8 bit in the SCICR1 register.

Character Transmission

During an SCI transmission, data shifts out least significant bit first on the TDO pin. In this mode, the SCIDR register consists of a buffer (TDR) between the internal bus and the transmit shift register (see Figure 51).

Procedure

– Select the M bit to define the word length. – Select the desired baud rate using the SCIBRR

and the SCIETPR registers.

– Set the TE bit to assign the TDO pin to the alter-

nate function and to send a idle frame as first transmission.

– Access the SCISR register and write the data to

send in the SCIDR register (this sequence clears the TDRE bit). Repeat this sequence for each data to be transmitted.

Clearing the TDRE bit is always performed by the following software sequence:

1. An access to the SCISR register

2. A write to the SCIDR register The TDRE bit is set by hardware and it indicates: – The TDR register is empty. – The data transfer is beginning. – The next data can be written in the SCIDR regis-

ter without overwriting the previous data.

This flag generates an interrupt if the TIE bit is set and the I bit is cleared in the CCR register.

When a transmission is taking place, a write instruction to the SCIDR register stores the data in the TDR register and which is copied in the shift register at the end of the current transmission.

When no transmission is taking place, a write instruction to the SCIDR register places the data directly in the shift register, the data transmission starts, and the TDRE bit is immediately set.

When a frame transmission is complete (after the stop bit) the TC bit is set and an interrupt is generated if the TCIE is set and the I bit is cleared in the CCR register.

Clearing the TC bit is performed by the following software sequence:

1. An access to the SCISR register

2. A write to the SCIDR register Note: The TDRE and TC bits are cleared by the

same software sequence.

Break Characters

Setting the SBK bit loads the shift register with a break character. The break frame length depends on the M bit (see Figure 52).

As long as the SBK bit is set, the SCI send break frames to the TDO pin. After clearing this bit by software the SCI insert a logic 1 bit at the end of the last break frame to guarantee the recognition of the start bit of the next frame.

Idle Characters

Setting the TE bit drives the SCI to send an idle frame before the first data frame.

Clearing and then setting the TE bit during a transmission sends an idle frame after the current word.

Note: Resetting and setting the TE bit causes the data in the TDR register to be lost. Therefore the best time to toggle the TE bit is when the TDRE bit is set i.e. before writing the next byte in the SCIDR.

90/157

SERIAL COMMUNICATIONS INTERFACE (Cont’d)

10.5.4.3 Receiver

The SCI can receive data words of either 8 or 9 bits. When the M bit is set, word length is 9 bits and the MSB is stored in the R8 bit in the SCICR1 register.

Character reception

During a SCI reception, data shifts in least significant bit first through the RDI pin. In this mode, the SCIDR register consists or a buffer (RDR) between the internal bus and the received shift register (see Figure 51).

Procedure

– Select the M bit to define the word length. – Select the desired baud rate using the SCIBRR

and the SCIERPR registers.

– Set the RE bit, this enables the receiver which

begins searching for a start bit. When a character is received: – The RDRF bit is set. It indicates that the content

of the shift register is transferred to the RDR. – An interrupt is generated if the RIE bit is set and

the I bit is cleared in the CCR register. – The error flags can be set if a frame error, noise

or an overrun error has been detected during re-

ception. Clearing the RDRF bit is performed by the following

software sequence done by:

1. An access to the SCISR register

2. A read to the SCIDR register. The RDRF bit must be cleared before the end of the

reception of the next character to avoid an overrun error.

Break Character

When a break character is received, the SPI handles it as a framing error.

Idle Character

When a idle frame is detected, there is the same procedure as a data received character plus an interrupt if the ILIE bit is set and the I bit is cleared in the CCR register.

Overrun Error

An overrun error occurs when a character is received when RDRF has not been reset. Data can not be transferred from the shift register to the

ST7232A

RDR register as long as the RDRF bit is not cleared.

When a overrun error occurs: – The OR bit is set. – The RDR content will not be lost. – The shift register will be overwritten. – An interrupt is generated if the RIE bit is set and

the I bit is cleared in the CCR register.

The OR bit is reset by an access to the SCISR register followed by a SCIDR register read operation.

Noise Error

Oversampling techniques are used for data recovery by discriminating between valid incoming data and noise. Normal data bits are considered valid if three consecutive samples (8th, 9th, 10th) have the same bit value, otherwise the NF flag is set. In the case of start bit detection, the NF flag is set on the basis of an algorithm combining both valid edge detection and three samples (8th, 9th, 10th). Therefore, to prevent the NF flag getting set during start bit reception, there should be a valid edge detection as well as three valid samples.

When noise is detected in a frame: – The NF flag is set at the rising edge of the RDRF

bit.

– Data is transferred from the Shift register to the

SCIDR register.

– No interrupt is generated. However this bit rises

at the same time as the RDRF bit which itself generates an interrupt.

The NF flag is reset by a SCISR register read operation followed by a SCIDR register read operation.

During reception, if a false start bit is detected (e.g. 8th, 9th, 10th samples are 011,101,110), the frame is discarded and the receiving sequence is not started for this frame. There is no RDRF bit set for this frame and the NF flag is set internally (not accessible to the user). This NF flag is accessible along with the RDRF bit when a next valid frame is received.

Note: If the application Start Bit is not long enough to match the above requirements, then the NF Flag may get set due to the short Start Bit. In this case, the NF flag may be ignored by the application software when the first valid byte is received.

10.5.4.4 Conventional Baud Rate Generation

The baud rate for the receiver and transmitter (Rx and Tx) are set independently and calculated as follows:

(16

CPU

PR)*RR

Tx =

(16

CPU

PR)*TR

Rx =

with: PR = 1, 3, 4 or 13 (see SCP[1:0] bits) TR = 1, 2, 4, 8, 16, 32, 64,128 (see SCT[2:0] bits) RR = 1, 2, 4, 8, 16, 32, 64,128 (see SCR[2:0] bits) All these bits are in the SCIBRR register. Example: If f

is 8 MHz (normal mode) and if

CPU

PR=13 and TR=RR=1, the transmit and receive baud rates are 38400 baud.

Note: the baud rate registers MUST NOT be changed while the transmitter or the receiver is enabled.

10.5.4.5 Extended Baud Rate Generation

The extended prescaler option gives a very fine tuning on the baud rate, using a 255 value prescaler, whereas the conventional Baud Rate Generator retains industry standard software compatibility.

The extended baud rate generator block diagram is described in the Figure 53.

The output clock rate sent to the transmitter or to the receiver will be the output from the 16 divider divided by a factor ranging from 1 to 255 set in the SCIERPR or the SCIETPR register.

ST7232A

Note: the extended prescaler is activated by set-

ting the SCIETPR or SCIERPR register to a value other than zero. The baud rates are calculated as follows:

Tx =

CPU

ETPR*(PR*TR)

Rx =

with: ETPR = 1,..,255 (see SCIETPR register) ERPR = 1,.. 255 (see SCIERPR register)

10.5.4.6 Receiver Muting and Wake-up Feature

In multiprocessor configurations it is often desirable that only the intended message recipient should actively receive the full message contents, thus reducing redundant SCI service overhead for all non addressed receivers.

The non addressed devices may be placed in sleep mode by means of the muting function.

Setting the RWU bit by software puts the SCI in sleep mode:

All the reception status bits can not be set. All the receive interrupts are inhibited. A muted receiver may be awakened by one of the

following two ways: – by Idle Line detection if the WAKE bit is reset, – by Address Mark detection if the WAKE bit is set. Receiver wakes-up by Idle Line detection when

the Receive line has recognised an Idle Frame. Then the RWU bit is reset by hardware but the IDLE bit is not set.

Receiver wakes-up by Address Mark detection when it received a “1” as the most significant bit of a word, thus indicating that the message is an address. The reception of this particular word wakes up the receiver, resets the RWU bit and sets the RDRF bit, which allows the receiver to receive this word normally and to use it as an address word.

Caution: In Mute mode, do not write to the SCICR2 register. If the SCI is in Mute mode during the read operation (RWU=1) and a address mark wake up event occurs (RWU is reset) before the write operation, the RWU bit will be set again by this write operation. Consequently the address byte is lost and the SCI is not woken up from Mute mode.

CPU

ERPR*(PR*RR)

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ST7232A

SERIAL COMMUNICATIONS INTERFACE (Cont’d)

10.5.4.7 Parity Control

Parity control (generation of parity bit in transmission and parity checking in reception) can be enabled by setting the PCE bit in the SCICR1 register. Depending on the frame length defined by the M bit, the possible SCI frame formats are as listed in

Table 20.

Table 20. Frame Formats

M bit PCE bit SCI frame

0 0 | SB | 8 bit data | STB | 0 1 | SB | 7-bit data | PB | STB | 1 0 | SB | 9-bit data | STB | 1 1 | SB | 8-bit data PB | STB |

Legend: SB = Start Bit, STB = Stop Bit, PB = Parity Bit

Note: In case of wake up by an address mark, the MSB bit of the data is taken into account and not the parity bit

Even parity: the parity bit is calculated to obtain an even number of “1s” inside the frame made of the 7 or 8 LSB bits (depending on whether M is equal to 0 or 1) and the parity bit.

Ex: data=00110101; 4 bits set => parity bit will be 0 if even parity is selected (PS bit = 0).

Odd parity: the parity bit is calculated to obtain an odd number of “1s” inside the frame made of the 7 or 8 LSB bits (depending on whether M is equal to 0 or 1) and the parity bit.

Ex: data=00110101; 4 bits set => parity bit will be 1 if odd parity is selected (PS bit = 1).

Transmission mode: If the PCE bit is set then the MSB bit of the data written in the data register is not transmitted but is changed by the parity bit.

Reception mode: If the PCE bit is set then the interface checks if the received data byte has an

even number of “1s” if even parity is selected (PS=0) or an odd number of “1s” if odd parity is selected (PS=1). If the parity check fails, the PE flag is set in the SCISR register and an interrupt is generated if PIE is set in the SCICR1 register.

10.5.4.8 SCI Clock Tolerance

During reception, each bit is sampled 16 times. The majority of the 8th, 9th and 10th samples is considered as the bit value. For a valid bit detec- tion, all the three samples should have the same value otherwise the noise flag (NF) is set. For example: if the 8th, 9th and 10th samples are 0, 1 and 1 respectively, then the bit value will be “1”, but the Noise Flag bit is be set because the three samples values are not the same.

Consequently, the bit length must be long enough so that the 8th, 9th and 10th samples have the desired bit value. This means the clock frequency should not vary more than 6/16 (37.5%) within one bit. The sampling clock is resynchronized at each start bit, so that when receiving 10 bits (one start bit, 1 data byte, 1 stop bit), the clock deviation must not exceed 3.75%.

Note: The internal sampling clock of the microcontroller samples the pin value on every falling edge. Therefore, the internal sampling clock and the time the application expects the sampling to take place may be out of sync. For example: If the baud rate is 15.625 kbaud (bit length is 64µs), then the 8th, 9th and 10th samples will be at 28µs, 32µs & 36µs respectively (the first sample starting ideally at 0µs). But if the falling edge of the internal clock occurs just before the pin value changes, the samples would then be out of sync by ~4us. This means the entire bit length must be at least 40µs (36µs for the 10th sample + 4µs for synchronization with the internal sampling clock).

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SERIAL COMMUNICATIONS INTERFACE (Cont’d)

10.5.4.9 Clock Deviation Causes

The causes which contribute to the total deviation are:

–D

: Deviation due to transmitter error (Local

TRA

oscillator error of the transmitter or the transmitter is transmitting at a different baud rate).

–D

tion of the receiver.

–D

: Error due to the baud rate quantisa-

QUANT

: Deviation of the local oscillator of the

REC

receiver: This deviation can occur during the reception of one complete SCI message assuming that the deviation has been compensated at the beginning of the message.

–D

: Deviation due to the transmission line

TCL

(generally due to the transceivers)

All the deviations of the system should be added and compared to the SCI clock tolerance:

TRA

+ D

QUANT

+ D

REC

+ D

< 3.75%

TCL

ST7232A

10.5.4.10 Noise Error Causes

See also description of Noise error in Section

10.5.4.3.

Start bit

The noise flag (NF) is set during start bit reception if one of the following conditions occurs:

1. A valid falling edge is not detected. A falling edge is considered to be valid if the 3 consecutive samples before the falling edge occurs are detected as '1' and, after the falling edge occurs, during the sampling of the 16 samples, if one of the samples numbered 3, 5 or 7 is detected as a “1”.

2. During sampling of the 16 samples, if one of the samples numbered 8, 9 or 10 is detected as a “1”.

Therefore, a valid Start Bit must satisfy both the above conditions to prevent the Noise Flag getting set.

Data Bits

The noise flag (NF) is set during normal data bit reception if the following condition occurs:

– During the sampling of 16 samples, if all three

samples numbered 8, 9 and10 are not the same. The majority of the 8th, 9th and 10th samples is considered as the bit value.

Therefore, a valid Data Bit must have samples 8, 9 and 10 at the same value to prevent the Noise Flag getting set.

Figure 54. Bit Sampling in Reception Mode

RDI LINE

Sample clock

12345678910111213 14 15 16

7/16

sampled values

6/16 7/16

One bit time

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ST7232A

SERIAL COMMUNICATIONS INTERFACE (Cont’d)

10.5.5 Low Power Modes

Mode Description

No effect on SCI.

WAIT

HALT

10.5.6 Interrupts

The SCI interrupt events are connected to the same interrupt vector.

These events generate an interrupt if the corresponding Enable Control Bit is set and the inter-

SCI interrupts cause the device to exit from Wait mode.

SCI registers are frozen.

In Halt mode, the SCI stops transmitting/receiving until Halt mode is exited.

Enable

Interrupt Event

Transmit Data Register Empty

Transmission Complete

Received Data Ready to be Read

Overrun Error Detected OR Yes No Idle Line Detected IDLE ILIE Yes No Parity Error PE PIE Yes No

Event

Control

Flag

TDRE TIE Yes No

TC TCIE Yes No

RDRF

Bit

RIE

Exit from Wait

Exit

from

Halt

Yes No

rupt mask in the CC register is reset (RIM instruction).

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SERIAL COMMUNICATIONS INTERFACE (Cont’d)

10.5.7 Register Description STATUS REGISTER (SCISR)

Read Only

Note: The IDLE bit will not be set again until the RDRF bit has been set itself (i.e. a new idle line occurs).

Reset Value: 1100 0000 (C0h)

TDRE TC RDRF IDLE OR NF FE PE

Bit 3 = OR Overrun error. This bit is set by hardware when the word currently being received in the shift register is ready to be transferred into the RDR register while RDRF=1.

An interrupt is generated if RIE=1 in the SCICR2 Bit 7 = TDRE Transmit data register empty. This bit is set by hardware when the content of the TDR register has been transferred into the shift register. An interrupt is generated if the TIE bit=1 in the SCICR2 register. It is cleared by a software sequence (an access to the SCISR register followed by a write to the SCIDR register). 0: Data is not transferred to the shift register

access to the SCISR register followed by a read to

the SCIDR register).

0: No Overrun error

1: Overrun error is detected

Note: When this bit is set RDR register content will

not be lost but the shift register will be overwritten. 1: Data is transferred to the shift register

Note: Data will not be transferred to the shift register unless the TDRE bit is cleared.

Bit 2 = NF Noise flag.

This bit is set by hardware when noise is detected

on a received frame. It is cleared by a software se-

quence (an access to the SCISR register followed Bit 6 = TC Transmission complete. This bit is set by hardware when transmission of a frame containing Data is complete. An interrupt is generated if TCIE=1 in the SCICR2 register. It is cleared by a software sequence (an access to the SCISR register followed by a write to the SCIDR register).

by a read to the SCIDR register).

0: No noise is detected

1: Noise is detected

Note: This bit does not generate interrupt as it ap-

pears at the same time as the RDRF bit which it-

self generates an interrupt. 0: Transmission is not complete

1: Transmission is complete Note: TC is not set after the transmission of a Pre-

amble or a Break.

Bit 5 = RDRF Received data ready flag. This bit is set by hardware when the content of the RDR register has been transferred to the SCIDR register. An interrupt is generated if RIE=1 in the SCICR2 register. It is cleared by a software sequence (an access to the SCISR register followed by a read to the SCIDR register). 0: Data is not received 1: Received data is ready to be read

Bit 1 = FE Framing error.

This bit is set by hardware when a de-synchroniza-

tion, excessive noise or a break character is de-

tected. It is cleared by a software sequence (an

access to the SCISR register followed by a read to

the SCIDR register).

0: No Framing error is detected

1: Framing error or break character is detected

Note: This bit does not generate interrupt as it ap-

pears at the same time as the RDRF bit which it-

self generates an interrupt. If the word currently

being transferred causes both frame error and

overrun error, it will be transferred and only the OR

bit will be set.

ST7232A

Bit 4 = IDLE Idle line detect. This bit is set by hardware when a Idle Line is detected. An interrupt is generated if the ILIE=1 in the SCICR2 register. It is cleared by a software sequence (an access to the SCISR register followed by a read to the SCIDR register). 0: No Idle Line is detected 1: Idle Line is detected

Bit 0 = PE Parity error.

This bit is set by hardware when a parity error oc-

curs in receiver mode. It is cleared by a software

sequence (a read to the status register followed by

an access to the SCIDR data register). An inter-

rupt is generated if PIE=1 in the SCICR1 register.

0: No parity error

1: Parity error

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ST7232A

SERIAL COMMUNICATIONS INTERFACE (Cont’d) CONTROL REGISTER 1 (SCICR1)

Read/Write Reset Value: x000 0000 (x0h)

R8 T8 SCID M WAKE PCE PS PIE

Bit 7 = R8 Receive data bit 8. This bit is used to store the 9th bit of the received word when M=1.

Bit 6 = T8 Transmit data bit 8. This bit is used to store the 9th bit of the transmitted word when M=1.

Bit 5 = SCID Disabled for low power consumption When this bit is set the SCI prescalers and outputs are stopped and the end of the current byte transfer in order to reduce power consumption.This bit is set and cleared by software. 0: SCI enabled 1: SCI prescaler and outputs disabled

Bit 4 = M Word length. This bit determines the word length. It is set or cleared by software. 0: 1 Start bit, 8 Data bits, 1 Stop bit 1: 1 Start bit, 9 Data bits, 1 Stop bit

Note: The M bit must not be modified during a data transfer (both transmission and reception).

Bit 3 = WAKE Wake-Up method.

This bit determines the SCI Wake-Up method, it is

set or cleared by software.

0: Idle Line

1: Address Mark

Bit 2 = PCE Parity control enable.

This bit selects the hardware parity control (gener-

ation and detection). When the parity control is en-

abled, the computed parity is inserted at the MSB

position (9th bit if M=1; 8th bit if M=0) and parity is

checked on the received data. This bit is set and

cleared by software. Once it is set, PCE is active

after the current byte (in reception and in transmis-

sion).

0: Parity control disabled

1: Parity control enabled

Bit 1 = PS Parity selection.

This bit selects the odd or even parity when the

parity generation/detection is enabled (PCE bit

set). It is set and cleared by software. The parity

will be selected after the current byte.

0: Even parity

1: Odd parity

Bit 0 = PIE Parity interrupt enable.

This bit enables the interrupt capability of the hard-

ware parity control when a parity error is detected

(PE bit set). It is set and cleared by software.

0: Parity error interrupt disabled

1: Parity error interrupt enabled.

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SERIAL COMMUNICATIONS INTERFACE (Cont’d) CONTROL REGISTER 2 (SCICR2)

Read/Write Reset Value: 0000 0000 (00h)

Notes:

– During transmission, a “0” pulse on the TE bit

(“0” followed by “1”) sends a preamble (idle line) after the current word.

– When TE is set there is a 1 bit-time delay before

the transmission starts.

TIE TCIE RIE ILIE TE RE RWU

SBK

Caution: The TDO pin is free for general purpose

I/O only when the TE and RE bits are both cleared Bit 7 = TIE Transmitter interrupt enable.

(or if TE is never set). This bit is set and cleared by software. 0: Interrupt is inhibited 1: An SCI interrupt is generated whenever

TDRE=1 in the SCISR register

Bit 6 = TCIE Transmission complete interrupt ena-

ble

This bit is set and cleared by software. 0: Interrupt is inhibited 1: An SCI interrupt is generated whenever TC=1 in

the SCISR register

Bit 5 = RIE Receiver interrupt enable. This bit is set and cleared by software. 0: Interrupt is inhibited 1: An SCI interrupt is generated whenever OR=1

or RDRF=1 in the SCISR register

Bit 2 = RE Receiver enable.

This bit enables the receiver. It is set and cleared

by software.

0: Receiver is disabled

1: Receiver is enabled and begins searching for a

start bit

Bit 1 = RWU Receiver wake-up.

This bit determines if the SCI is in mute mode or

not. It is set and cleared by software and can be

cleared by hardware when a wake-up sequence is

recognized.

0: Receiver in Active mode

1: Receiver in Mute mode

Note: Before selecting Mute mode (setting the

RWU bit), the SCI must receive some data first,

otherwise it cannot function in Mute mode with Bit 4 = ILIE Idle line interrupt enable.

wakeup by idle line detection. This bit is set and cleared by software.

0: Interrupt is inhibited 1: An SCI interrupt is generated whenever IDLE=1

in the SCISR register.

Bit 0 = SBK Send break.

This bit set is used to send break characters. It is

set and cleared by software.

0: No break character is transmitted Bit 3 = TE Transmitter enable. This bit enables the transmitter. It is set and cleared by software.

0: Transmitter is disabled 1: Transmitter is enabled

1: Break characters are transmitted

Note: If the SBK bit is set to “1” and then to “0”, the

transmitter will send a BREAK word at the end of

the current word.

ST7232A

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ST7232A

SERIAL COMMUNICATIONS INTERFACE (Cont’d) DATA REGISTER (SCIDR)

Read/Write Reset Value: Undefined Contains the Received or Transmitted data char-

acter, depending on whether it is read from or written to.

DR7 DR6 DR5 DR4 DR3 DR2 DR1 DR0

The Data register performs a double function (read and write) since it is composed of two registers, one for transmission (TDR) and one for reception (RDR). The TDR register provides the parallel interface between the internal bus and the output shift register (see Figure 51). The RDR register provides the parallel interface between the input shift register and the internal bus (see Figure 51).

Bits 5:3 = SCT[2:0] SCI Transmitter rate divisor

These 3 bits, in conjunction with the SCP1 & SCP0

bits define the total division applied to the bus

clock to yield the transmit rate clock in convention-

al Baud Rate Generator mode.

TR dividing factor SCT2 SCT1 SCT0

1000 2001 4010

8011 16 1 0 0 32 1 0 1 64 1 1 0

128 1 1 1

Bits 2:0 = SCR[2:0] SCI Receiver rate divisor. These 3 bits, in conjunction with the SCP[1:0] bits define the total division applied to the bus clock to yield the receive rate clock in conventional Baud Rate Generator mode.

BAUD RATE REGISTER (SCIBRR)

Read/Write Reset Value: 0000 0000 (00h)

SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1 SCR0

Bits 7:6= SCP[1:0] First SCI Prescaler These 2 prescaling bits allow several standard

RR Dividing factor SCR2 SCR1 SCR0

1000

2001

4010

8011 16 1 0 0 32 1 0 1 64 1 1 0

128 1 1 1

clock division ranges:

PR Prescaling factor SCP1 SCP0

100 301 410

13 1 1

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ST ST7232A User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

1 INTRODUCTION

2 PIN DESCRIPTION

3 REGISTER & MEMORY MAP

4 FLASH PROGRAM MEMORY

4.1 Introduction

4.2 Main Features

4.3 Structure

4.3.1 Read-out Protection

4.4 ICC Interface

4.5 ICP (In-Circuit Programming)

4.6 IAP (In-Application Programming)

4.7 Related Documentation

4.7.1 Register Description FLASH CONTROL/STATUS REGISTER (FCSR)

5 CENTRAL PROCESSING UNIT

5.1 INTRODUCTION

5.2 MAIN FEATURES

5.3 CPU REGISTERS

6 SUPPLY, RESET AND CLOCK MANAGEMENT

6.1 PHASE LOCKED LOOP

6.2 MULTI-OSCILLATOR (MO)

6.3 RESET SEQUENCE MANAGER (RSM)

6.3.1 Introduction

6.3.3 External Power-On RESET

6.3.4 Internal Watchdog RESET

6.4 SYSTEM INTEGRITY MANAGEMENT

6.4.1 Register Description SYSTEM INTEGRITY (SI) CONTROL/STATUS REGISTER (SICSR)

7 INTERRUPTS

7.1 INTRODUCTION

7.2 MASKING AND PROCESSING FLOW

7.3 INTERRUPTS AND LOW POWER MODES

7.4 CONCURRENT & NESTED MANAGEMENT

7.5 INTERRUPT REGISTER DESCRIPTION

7.6 EXTERNAL INTERRUPTS

7.6.1 I/O Port Interrupt Sensitivity

7.7 EXTERNAL INTERRUPT CONTROL REGISTER (EICR)

8 POWER SAVING MODES

8.1 INTRODUCTION

8.2 SLOW MODE

8.3 WAIT MODE

8.4 ACTIVE-HALT AND HALT MODES

8.4.1 ACTIVE-HALT MODE

8.4.2 HALT MODE

8.4.2.1 Halt Mode Recommendations

9 I/O PORTS

9.1 INTRODUCTION

9.2 FUNCTIONAL DESCRIPTION

9.2.1 Input Modes

9.2.2 Output Modes

9.2.3 Alternate Functions

9.3 I/O PORT IMPLEMENTATION

9.4 LOW POWER MODES

9.5 INTERRUPTS

9.5.1 I/O Port Implementation

10 ON-CHIP PERIPHERALS

10.1 WATCHDOG TIMER (WDG)

10.1.1 Introduction

10.1.2 Main Features

10.1.3 Functional Description

10.1.4 How to Program the Watchdog Timeout

10.1.5 Low Power Modes

10.1.6 Hardware Watchdog Option

10.1.7 Using Halt Mode with the WDG (WDGHALT option)

10.1.8 Interrupts

10.1.9 Register Description CONTROL REGISTER (WDGCR)

MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK AND BEEPER (MCC/RTC)

Programmable CPU Clock Prescaler

Clock-out Capability

Real Time Clock Timer (RTC)

Beeper

Low Power Modes

Interrupts

Register Description

10.3 16-BIT TIMER

10.3.1 Introduction

10.3.2 Main Features

10.3.3 Functional Description