ST ST72324BK2, ST72324BK4, ST72324BK6, ST72324BJ2, ST72324BJ4 User Manual

8-bit MCU for automotive, 3.8 to 5.5V operating range with

LQFP44

10 x 10

LQFP32

7 x 7

8 to 32 Kbyte Flash/ROM, 10-bit ADC, 4 timers, SPI, SCI

Features

Memories

■ 8 to 32 Kbyte dual voltage High Density Flash

(HDFlash) or ROM with readout protection
capability. In-application programming and In­circuit programming for HDFlash devices

■ 384 bytes to 1 Kbyte RAM

■ HDFlash endurance: 100 cycles, data retention

20 years

Clock, reset and supply management

■ Enhanced low voltage supervisor (LVD) with

programmable reset thresholds and auxiliary
voltage detector (AVD) with interrupt capability

■ Clock sources: crystal/ceramic resonator

oscillators, internal RC oscillator and external
clock input

■ PLL for 2x frequency multiplication

■ 4 power saving modes: Slow, Wait, Active Halt,

and Halt

ST72324Bxx-Auto

4 timers

■ Main clock controller with Real-time base,

Beep and Clock-out capabilities

■ Configurable watchdog timer

■ 16-bit Timer A with 1 input capture, 1 output

compare, external clock input, PWM and pulse
generator modes

■ 16-bit Timer B with 2 input captures, 2 output

compares, PWM and pulse generator modes

2 communication interfaces

■ SPI synchronous serial interface

■ SCI asynchronous serial interface

Interrupt management

■ Nested interrupt controller

■ 10 interrupt vectors plus TRAP and RESET

■ 9/6 external interrupt lines (on 4 vectors)

Up to 32 I/O ports

■ 32/24 multifunctional bidirectional I/O lines

■ 22/17 alternate function lines

■ 12/10 high sink outputs

Table 1. Device summary

Device Memory RAM (stack) Voltage range Temp. range Package

ST72324BK2-Auto Flash/ROM 8 Kbytes 384 (256) bytes

ST72324BK4-Auto Flash/ROM 16 Kbytes 512 (256) bytes

ST72324BK6-Auto Flash/ROM 32 Kbytes 1024 (256) bytes

ST72324BJ2-Auto Flash/ROM 8 Kbytes 384 (256) bytes

ST72324BJ4-Auto Flash/ROM 16 Kbytes 512 (256) bytes

ST72324BJ6-Auto Flash/ROM 32 Kbytes 1024 (256) bytes

1 analog peripheral (low current coupling)

■ 10-bit ADC with up to 12 input ports

Instruction set

■ 8-bit data manipulation

■ 63 basic instructions

■ 17 main addressing modes

■ 8 x 8 Unsigned Multiply Instruction

Development tools

■ In-circuit testing capability

3.8 to 5.5V

up to

-40 to 125°C

LQFP32

7x7

LQFP44

10x10

July 2010 Doc ID13466 Rev 4 1/198

www.st.com

1

Contents ST72324B-Auto

Contents

1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3 Register and memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4 Flash program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.3 Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.3.1 Readout protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4.4 ICC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4.5 ICP (in-circuit programming) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.6 IAP (in-application programming) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.7 Related documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.7.1 Flash Control/Status Register (FCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . 25

5 Central processing unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

5.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

5.3 CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

5.3.1 Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

5.3.2 Index registers (X and Y) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

5.3.3 Program counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

5.3.4 Condition Code register (CC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

5.3.5 Stack Pointer register (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

6 Supply, reset and clock management . . . . . . . . . . . . . . . . . . . . . . . . . . 31

6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

6.2 PLL (phase locked loop) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

6.3 Multi-oscillator (MO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

6.3.1 External clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

6.3.2 Crystal/ceramic oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

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6.3.3 Internal RC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

6.4 Reset sequence manager (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

6.4.1 Asynchronous external RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

6.5 System integrity management (SI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

6.5.1 LVD (low voltage detector) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

6.5.2 AVD (auxiliary voltage detector) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

6.5.3 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

6.5.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

6.6 SI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

6.6.1 System integrity (SI) control/status register (SICSR) . . . . . . . . . . . . . . . 39

7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

7.2 Masking and processing flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

7.2.1 Servicing pending interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

7.2.2 Different interrupt vector sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

7.2.3 Non-maskable sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

7.2.4 Maskable sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

7.3 Interrupts and low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

7.4 Concurrent and nested management . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

7.5 Interrupt registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

7.5.1 CPU CC register interrupt bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

7.5.2 Interrupt software priority registers (ISPRx) . . . . . . . . . . . . . . . . . . . . . . 46

7.6 External interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

7.6.1 I/O port interrupt sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

7.6.2 External interrupt control register (EICR) . . . . . . . . . . . . . . . . . . . . . . . . 49

8 Power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

8.2 Slow mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

8.3 Wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

8.4 Active Halt and Halt modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

8.4.1 Active Halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

8.4.2 Halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

9 I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

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Contents ST72324B-Auto

9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

9.2 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

9.2.1 Input modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

9.2.2 Output modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

9.2.3 Alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

9.3 I/O port implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

9.4 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

9.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

9.5.1 I/O port implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

10 On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

10.1 Watchdog timer (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

10.1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

10.1.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

10.1.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

10.1.4 How to program the Watchdog timeout . . . . . . . . . . . . . . . . . . . . . . . . . 66

10.1.5 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

10.1.6 Hardware Watchdog option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

10.1.7 Using Halt mode with the WDG (WDGHALT option) . . . . . . . . . . . . . . . 68

10.1.8 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

10.1.9 Control register (WDGCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

10.2 Main clock controller with real-time clock and beeper (MCC/RTC) . . . . . 69

10.2.1 Programmable CPU clock prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

10.2.2 Clock-out capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

10.2.3 Real-time clock (RTC) timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

10.2.4 Beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

10.2.5 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

10.2.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

10.2.7 MCC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

10.3 16-bit timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

10.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

10.3.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

10.3.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

10.3.4 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

10.3.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

10.3.6 Summary of timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

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10.3.7 16-bit timer registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

10.4 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

10.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

10.4.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

10.4.3 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

10.4.4 Clock phase and clock polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

10.4.5 Error flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

10.4.6 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

10.4.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

10.4.8 SPI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

10.5 Serial communications interface (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . 110

10.5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

10.5.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

10.5.3 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

10.5.4 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

10.5.5 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

10.5.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

10.5.7 SCI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

10.6 10-bit A/D converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

10.6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

10.6.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

10.6.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

10.6.4 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

10.6.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

10.6.6 ADC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

11 Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

11.1 CPU addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

11.1.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

11.1.2 Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

11.1.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

11.1.4 Indexed (no offset, short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

11.1.5 Indirect (short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

11.1.6 Indirect indexed (short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

11.1.7 Relative mode (direct, indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

11.2 Instruction groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

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Contents ST72324B-Auto

12 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

12.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

12.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

12.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

12.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

12.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

12.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

12.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

12.2.1 Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

12.2.2 Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

12.2.3 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

12.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

12.4 LVD/AVD characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

12.4.1 Operating conditions with LVD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

12.4.2 Auxiliary voltage detector (AVD) thresholds . . . . . . . . . . . . . . . . . . . . . 149

12.5 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

12.5.1 ROM current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

12.5.2 Flash current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

12.5.3 Supply and clock managers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

12.5.4 On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

12.6 Clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

12.6.1 General timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

12.6.2 External clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

12.6.3 Crystal and ceramic resonator oscillators . . . . . . . . . . . . . . . . . . . . . . 154

12.6.4 RC oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

12.6.5 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

12.7 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

12.7.1 RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

12.7.2 Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

12.8 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

12.8.1 Functional electromagnetic susceptibility (EMS) . . . . . . . . . . . . . . . . . 158

12.8.2 Electromagnetic interference (EMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

12.8.3 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 160

12.9 I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

12.9.1 General characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

12.9.2 Output driving current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

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12.10 Control pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

12.10.1 Asynchronous RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

12.10.2 ICCSEL/VPP pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

12.11 Timer peripheral characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

12.11.1 16-bit timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

12.12 Communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . 169

12.12.1 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

12.13 10-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

12.13.1 Analog power supply and reference pins . . . . . . . . . . . . . . . . . . . . . . . 173

12.13.2 General PCB design guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

12.13.3 ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

13 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

13.1 LQFP44 package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

13.2 LQFP32 package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

13.3 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

13.4 Ecopack information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

13.5 Packaging for automatic handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

14 Device configuration and ordering information . . . . . . . . . . . . . . . . . 179

14.1 Flash devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

14.1.1 Flash configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

14.1.2 Flash ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

14.2 ROM device ordering information and transfer of customer code . . . . . 183

14.3 Development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

14.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

14.3.2 Evaluation tools and starter kits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

14.3.3 Development and debugging tools . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

14.3.4 Programming tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

14.3.5 Socket and emulator adapter information . . . . . . . . . . . . . . . . . . . . . . 188

14.4 ST7 Application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188

15 Known limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189

15.1 All Flash and ROM devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189

15.1.1 Safe connection of OSC1/OSC2 pins . . . . . . . . . . . . . . . . . . . . . . . . . 189

15.1.2 External interrupt missed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189

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15.1.3 Unexpected reset fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191

15.1.4 Clearing active interrupts outside interrupt routine . . . . . . . . . . . . . . . 191

15.1.5 16-bit timer PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

15.1.6 TIMD set simultaneously with OC interrupt . . . . . . . . . . . . . . . . . . . . . 192

15.1.7 SCI wrong break duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

15.2 8/16 Kbyte Flash devices only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193

15.2.1 39-pulse ICC entry mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193

15.2.2 Negative current injection on pin PB0 . . . . . . . . . . . . . . . . . . . . . . . . . 193

15.3 8/16 Kbyte ROM devices only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193

15.3.1 Readout protection with LVD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193

15.3.2 I/O Port A and F configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193

16 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

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ST72324B-Auto List of tables

List of tables

Table 1. Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. Device pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 3. Hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 4. Sectors available in Flash devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 5. Flash control/status register address and reset value . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 6. Arithmetic management bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 7. Software interrupt bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 8. Interrupt software priority selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 9. ST7 clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 10. Effect of low power modes on SI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 11. AVD interrupt control/wake-up capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 12. SICSR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 13. Reset source flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 14. Interrupt software priority levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 15. CPU CC register interrupt bits description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 16. Interrupt software priority levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 17. ISPRx interrupt vector correspondence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 18. Dedicated interrupt instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 19. EICR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 20. Interrupt sensitivity - ei2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 21. Interrupt sensitivity - ei3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 22. Interrupt sensitivity - ei0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 23. Interrupt sensitivity - ei1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 24. Nested interrupts register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 25. Interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Table 26. MCC/RTC low power mode selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Table 27. DR register value and output pin status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Table 28. I/O port mode options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Table 29. I/O port configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Table 30. Effect of low power modes on I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Table 31. I/O port interrupt control/wake-up capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Table 32. Port configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Table 33. I/O port register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Table 34. Effect of lower power modes on Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Table 35. WDGCR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Table 36. Watchdog timer register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Table 37. Effect of low power modes on MCC/RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Table 38. MCC/RTC interrupt control/wake-up capability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Table 39. MCCSR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Table 40. Time base selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Table 41. MCCBCR register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Table 42. Beep frequency selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Table 43. Main clock controller register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Table 44. Input capture byte distribution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Table 45. Output compare byte distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Table 46. Effect of low power modes on 16-bit timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Table 47. 16-bit timer interrupt control/wake-up capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Table 48. Summary of timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

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List of tables ST72324B-Auto

Table 49. CR1 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Table 50. CR2 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Table 51. CSR register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Table 52. 16-bit timer register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Table 53. Effect of low power modes on SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Table 54. SPI interrupt control/wake-up capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Table 55. SPICR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Table 56. SPI master mode SCK frequency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Table 57. SPICSR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Table 58. SPI register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Table 59. Frame formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Table 60. Effect of low power modes on SCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Table 61. SCI interrupt control/wake-up capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Table 62. SCISR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

Table 63. SCICR1 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

Table 64. SCICR2 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

Table 65. SCIBRR register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

Table 66. SCIERPR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

Table 67. SCIETPR register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

Table 68. Baud rate selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

Table 69. SCI register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

Table 70. Effect of low power modes on ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

Table 71. ADCCSR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

Table 72. ADCDRH register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

Table 73. ADCDRL register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

Table 74. ADC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

Table 75. Addressing mode groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

Table 76. CPU addressing mode overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

Table 77. Inherent instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

Table 78. Immediate instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

Table 79. Instructions supporting direct, indexed, indirect and indirect indexed addressing modes 139

Table 80. Relative direct and indirect instructions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

Table 81. Instruction groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

Table 82. Instruction set overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

Table 83. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

Table 84. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

Table 85. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

Table 86. Operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

Table 87. Operating conditions with LVD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

Table 88. AVD thresholds. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

Table 89. ROM current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

Table 90. Flash current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

Table 91. Oscillators, PLL and LVD current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

Table 92. On-chip peripherals current consumption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

Table 93. General timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

Table 94. External clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

Table 95. Crystal and ceramic resonator oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

Table 96. OSCRANGE selection for typical resonators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

Table 97. RC oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

Table 98. PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

Table 99. RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

Table 100. Dual voltage HDFlash memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

10/198 Doc ID13466 Rev 4

ST72324B-Auto List of tables

Table 101. EMS test results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

Table 102. EMI emissions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

Table 103. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

Table 104. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

Table 105. General characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

Table 106. Output driving current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

Table 107. Asynchronous RESET
Table 108. ICCSEL/V

pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

PP

pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

Table 109. 16-bit timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

Table 110. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

Table 111. 10-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

Table 112. ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

Table 113. 44-pin low profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

Table 114. 32-pin low profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

Table 115. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

Table 116. Flash option bytes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

Table 117. Option byte 0 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

Table 118. Option byte 1 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

Table 119. Package selection (OPT7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

Table 120. STMicroelectronics development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188

Table 121. Suggested list of socket types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188

Table 122. Port A and F configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194

Table 123. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

Doc ID13466 Rev 4 11/198

List of figures ST72324B-Auto

List of figures

Figure 1. Device block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 2. 44-pin LQFP package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 3. 32-pin LQFP package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 4. Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 5. Memory map and sector address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 6. Typical ICC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 7. CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 8. Stack manipulation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 9. PLL block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 10. Clock, reset and supply block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 11. Reset sequence phases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 12. Reset block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 13. RESET sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 14. Low voltage detector vs reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 15. Using the AVD to monitor V

Figure 16. Interrupt processing flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Figure 17. Priority decision process flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Figure 18. Concurrent interrupt management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Figure 19. Nested interrupt management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Figure 20. External interrupt control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Figure 21. Power saving mode transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Figure 22. Slow mode clock transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Figure 23. Wait mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Figure 24. Active Halt timing overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Figure 25. Active Halt mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Figure 26. HALT timing overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Figure 27. Halt mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Figure 28. I/O port general block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Figure 29. Interrupt I/O port state transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Figure 30. Watchdog block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Figure 31. Approximate timeout duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Figure 32. Exact timeout duration (t

Figure 33. Main clock controller (MCC/RTC) block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Figure 34. Timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Figure 35. 16-bit read sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Figure 36. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Figure 37. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Figure 38. Counter timing diagram, internal clock divided by 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Figure 39. Input capture block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Figure 40. Input capture timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Figure 41. Output compare block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Figure 42. Output compare timing diagram, f
Figure 43. Output compare timing diagram, f

Figure 44. One pulse mode cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Figure 45. One Pulse mode timing example(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Figure 46. Pulse width modulation mode timing example with two output compare functions(1)(2) . . 86

Figure 47. Pulse width modulation cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Figure 48. Serial peripheral interface block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

DD

min

and t

). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

max

TIMER
TIMER

= f
= f

/2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

CPU

/4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

CPU

12/198 Doc ID13466 Rev 4

ST72324B-Auto List of figures

Figure 49. Single master/single slave application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Figure 50. Generic SS timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Figure 51. Hardware/software slave select management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Figure 52. Data clock timing diagram(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Figure 53. Clearing the WCOL bit (Write Collision flag) software sequence . . . . . . . . . . . . . . . . . . . 104

Figure 54. Single master/multiple slave configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Figure 55. SCI block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

Figure 56. Word length programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Figure 57. SCI baud rate and extended prescaler block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Figure 58. Bit sampling in Reception mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

Figure 59. ADC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

Figure 60. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

Figure 61. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

Figure 62. f

max versus VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

CPU

Figure 63. Typical application with an external clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

Figure 64. Typical application with a crystal or ceramic resonator (8/16 Kbyte Flash

and ROM devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

Figure 65. Typical application with a crystal or ceramic resonator (32 Kbyte Flash

and ROM devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

Figure 66. Typical f

OSC(RCINT)

vs TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

Figure 67. Integrated PLL jitter vs signal frequency(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

Figure 68. Unused I/O pins configured as input(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

Figure 69. Typical I
Figure 70. Typical V
Figure 71. Typical V
Figure 72. Typical V
Figure 73. Typical V
Figure 74. Typical V
Figure 75. Typical V
Figure 76. RESET
Figure 77. RESET
Figure 78. Two typical applications with ICCSEL/V

vs. VDD with V

PU

at VDD = 5V (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

OL

at V

OL

at VDD = 5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

OH

vs. VDD (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

OL

vs. VDD (high-sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

OL

vs. VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

OH

= 5V (high-sink ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

DD

= VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

IN

pin protection when LVD is enabled(1)(2)(3)(4)(5)(6) . . . . . . . . . . . . . . . . . . . . . 167

pin protection when LVD is disabled(1)(2)(3)(4) . . . . . . . . . . . . . . . . . . . . . . . . . 167

pin(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

PP

Figure 79. SPI slave timing diagram with CPHA = 0(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

Figure 80. SPI slave timing diagram with CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

Figure 81. SPI master timing diagram(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

Figure 82. R
Figure 83. Recommended C

max. vs f

AIN

ADC

with C

and R

AIN

= 0pF(1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

AIN

values(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

AIN

Figure 84. Typical A/D converter application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

Figure 85. Power supply filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

Figure 86. ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

Figure 87. 44-pin low profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

Figure 88. 32-pin low profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

Figure 89. pin 1 orientation in tape and reel conditioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

Figure 90. ST72F324Bxx-Auto Flash commercial product structure . . . . . . . . . . . . . . . . . . . . . . . . . 182

Figure 91. ST72P324Bxx-Auto FastROM commercial product structure. . . . . . . . . . . . . . . . . . . . . . 184

Figure 92. ST72324Bxx-Auto ROM commercial product structure . . . . . . . . . . . . . . . . . . . . . . . . . . 185

Doc ID13466 Rev 4 13/198

Description ST72324B-Auto

8-bit CORE

ALU

ADDRESS AND DATA BUS

OSC1

V

PP

CONTROL

Program

(8 - 32 Kbytes)

V

DD

RESET

PORT F

PF7:6, 4, 2:0

TIMER A

BEEP

PORT A

RAM

(384 - 1024 bytes)

PORT C

10-bit ADC

V

AREF

V

SSA

PORT B

PB4:0

PORT E

PE1:0

(2 bits)

SCI

TIMER B

PA7:3

(5 bits on J devices)

PORT D

PD5:0

SPI

PC7:0

(8 bits)

V

SS

WATCHDOG

OSC

LV D

OSC2

memory

MCC/RTC/BEEP

(4 bits on K devices)

(5 bits on J devices)
(3 bits on K devices)

(6 bits on J devices)

(2 bits on K devices)

(6 bits on J devices)

(5 bits on K devices)

1 Description

The ST72324B-Auto devices are members of the ST7 microcontroller family designed for
mid-range automotive applications running from 3.8 to 5.5V. Different package options offer
up to 32 I/O pins.

All devices are based on a common industry-standard 8-bit core, featuring an enhanced
instruction set and are available with Flash or ROM program memory. The ST7 family
architecture offers both power and flexibility to software developers, enabling the design of
highly efficient and compact application code.

The on-chip peripherals include an A/D converter, two general purpose timers, an SPI
interface and an SCI interface. For power economy, the microcontroller can switch
dynamically into, Slow, Wait, Active Halt or Halt mode when the application is in idle or
stand-by state.

Figure 1. Device block diagram

14/198 Doc ID13466 Rev 4

Typical applications include

● all types of car body applications such as window lift, DC motor control, rain sensors

● safety microcontroller in airbag and engine management applications

● auxiliary functions in car radios

ST72324B-Auto Pin description

MCO/AIN8/PF0

BEEP/(HS) PF1

(HS) PF2

OCMP1_A/AIN10/PF4

ICAP1_A/(HS) PF6

EXTCLK_A/(HS) PF7

V

DD_0

V

SS_0

AIN5/PD5

V

AREF

V

SSA

44 43 42 41 40 39 38 37 36 35 34

33
32
31
30
29
28
27
26
25
24
23

12 13 14 15 16 17 18 19 20 21 22

1
2
3
4
5
6
7
8
9
10
11

ei2

ei3

ei0

ei1

PB3

(HS) PB4
AIN0/PD0
AIN1/PD1
AIN2/PD2
AIN3/PD3
AIN4/PD4

RDI / PE1

PB0
PB1

PB2

PC6/SCK/ICCCLK
PC5/MOSI/AIN14
PC4 / MISO/ICCDATA
PC3 (HS)/ICAP1_B
PC2 (HS)/ICAP2_B
PC1/OCMP1_B/AIN13
PC0/OCMP2_B/AIN12

V

SS_1

V

DD_1

PA3 ( HS)
PC7/SS

/AIN15

V

SS

_

2

RESET

V

PP

/ICCSEL

PA7 ( HS)

PA6 ( HS)

PA5 ( HS)

PA4 ( HS)

PE0/TDO

V

DD

_

2

OSC1

OSC2

eix associated external interrupt vector

(HS) 20mA high sink capability

ICCDATA/MISO/PC4

AIN14/MOSI/PC5

ICCCLK/SCK/PC6

AIN15/SS

/PC7

(HS) PA3

AIN13/OCMP1_B/PC1

ICAP2_B/(HS) PC2

ICAP1_B/(HS) PC3

32 31 30 29 28 27 26 25

24
23
22
21
20
19
18
17

9 10111213141516

1
2
3
4
5
6
7
8

ei1

ei3

ei0

OCMP1_A/AIN10/PF4

ICAP1_A/(HS) PF6

EXTCLK_A/(HS) PF7

AIN12/OCMP2_B/PC0

V

AREF

V

SSA

MCO/AIN8/PF0

BEEP/(HS) PF1

V

PP

/ICCSEL
PA7 ( HS)
PA6 ( HS)
PA4 ( HS)

OSC1
OSC2
V

SS_2

RESET

PB0

PE1/RDI

PE0/TDO

V

DD

_

2

PD1/AIN1

PD0/AIN0

PB4 (HS)

PB3

ei2

eix associated external interrupt vector

(HS) 20mA high sink capability

2 Pin description

Figure 2. 44-pin LQFP package pinout

Figure 3. 32-pin LQFP package pinout

See Section 12: Electrical characteristics on page 145 for external pin connection
guidelines.

Doc ID13466 Rev 4 15/198

Pin description ST72324B-Auto

Refer to Section 9: I/O ports on page 58 for more details on the software configuration of the
I/O ports.

The reset configuration of each pin is shown in bold. This configuration is valid as long as
the device is in reset state.

Table 2. Device pin description

No.

LQFP44

Pin

Name

LQFP32

Level Port

Type

Input

Output

float

Input Output

int

wpu

ana

OD

function

(after

reset)

PP

Main

6 30 PB4 (HS) I/O CTHS X ei3 X X Port B4

7 31 PD0/AIN0 I/O C

8 32 PD1/AIN1 I/O C

9-PD2/AIN2 I/OC

10 - PD3/AIN3 I/O C

11 - PD4/AIN4 I/O C

12 - PD5/AIN5 I/O C

13 1 V

14 2 V

AREF

SSA

(1)

(1)

15 3 PF0/MCO/AIN8 I/O C

16 4 PF1 (HS)/BEEP I/O C

17 - PF2 (HS) I/O C

18 5

PF4/OCMP1_A
/AIN10

T

T

T

T

T

T

S Analog reference voltage for ADC

S Analog ground voltage

T

T

T

I/O C

T

X X X X X Port D0 ADC analog input 0

X X X X X Port D1 ADC analog input 1

X X X X X Port D2 ADC analog input 2

X X X X X Port D3 ADC analog input 3

X X X X X Port D4 ADC analog input 4

X X X X X Port D5 ADC analog input 5

X ei1 X X X Port F0

HS X ei1 X X Port F1 Beep signal output

HS X ei1 X X Port F2

X XXXXPort F4

Alternate function

Main clock
out (f

CPU

Timer A
output
compare 1

ADC analog

)

input 8

ADC analog
Input 10

19 6

20 7

21 - V

22 - V

23 8

24 9

25 10

PF6 
(HS)/ICAP1_A

PF7 
(HS)/EXTCLK_A

(1)

DD_0

(1)

SS_0

PC0/OCMP2_B
/AIN12

PC1/OCMP1_B
/AIN13

PC2 
(HS)/ICAP2_B

I/O C

I/O C

S Digital main supply voltage

S Digital ground voltage

I/O C

I/O C

I/O C

HS X X X X Port F6 Timer A input capture 1

T

HS X XXXPort F7

T

T

T

T

X XXXXPort C0

X XXXXPort C1

HS X X X X Port C2 Timer B input capture 2

16/198 Doc ID13466 Rev 4

Timer A external clock
source

Timer B
output
compare 2

Timer B
output
compare 1

ADC analog
input 12

ADC analog
input 13

ST72324B-Auto Pin description

Table 2. Device pin description (continued)

No.

LQFP44

26 11

27 12

28 13

29 14

Pin

Name

LQFP32

PC3 
(HS)/ICAP1_B

PC4/MISO/ICCD
ATA

PC5/MOSI
/AIN14

PC6/SCK
/ICCCLK

Level Port

Type

Input

Output

I/O C

I/O C

I/O C

I/O C

HS X X X X Port C3 Timer B input capture 1

T

T

T

T

X XXXPort C4

X XXXXPort C5

X XXXPort C6

Input Output

int

wpu

float

ana

OD

function

(after

reset)

PP

Main

SPI master
in/slave out
data

SPI master
out/slave in
data

SPI serial
clock

SPI slave

30 15 PC7/SS

/AIN15 I/O C

T

X XXXXPort C7

select
(active low)

31 16 PA3 (HS) I/O C

32 - V

33 - V

DD_1

SS_1

(1)

(1)

S Digital main supply voltage

S Digital ground voltage

34 17 PA4 (HS) I/O C

35 - PA5 (HS) I/O C

36 18 PA6 (HS) I/O C

37 19 PA7 (HS) I/O CTHS X TPort A7

HS X ei0 X X Port A3

T

HS X XXXPort A4

T

HS X XXXPort A5

T

HS X TPort A6

T

(2)

(2)

Must be tied low. In the Flash
programming mode, this pin acts as

38 20 V

/ICCSEL I

PP

the programming voltage input V
See Section 12.10.2 for more details.
High voltage must not be applied to
ROM devices.

39 21 RESET

40 22 V

SS_2

41 23 OSC2

42 24 OSC1

43 25 V

DD_2

(1)

(3)

(3)

(1)

I/O C

S Digital ground voltage

O Resonator oscillator inverter output

I

S Digital main supply voltage

44 26 PE0/TDO I/O C

127PE1/RDI I/OC

T

T

T

X X X X Port E0 SCI transmit data out

X X X X Port E1 SCI receive data in

Top priority non-maskable interrupt

External clock input or resonator
oscillator inverter input

Alternate function

ICC data
input

ADC analog
input 14

ICC clock
output

ADC analog
input 15

PP

.

Doc ID13466 Rev 4 17/198

Pin description ST72324B-Auto

Table 2. Device pin description (continued)

No.

LQFP44

Pin

Name

LQFP32

Level Port

Type

Input

Output

float

Input Output

int

wpu

ana

OD

function

(after

reset)

PP

Main

Alternate function

Caution: Negative

current injection not

228PB0 I/OC

3-PB1 I/OC

4-PB2 I/OC

529PB3 I/OC

1. It is mandatory to connect all available VDD and V

2. On the chip, each I/O port has eight pads. Pads that are not bonded to external pins are in input pull-up configuration after
reset. The configuration of these pads must be kept at reset state to avoid added current consumption..

3. OSC1 and OSC2 pins connect a crystal/ceramic resonator, or an external source to the on-chip oscillator; see Section 1:

Description and Section 12.6: Clock and timing characteristics or more details.

4. For details refer to Section 12.9.1 on page 162

T

T

T

T

X ei2 X X Port B0

X ei2 X X Port B1

X ei2 X X Port B2

X ei2 X X Port B3

pins to the supply voltage and all VSS and V

REF

allowed on this pin on
8/16 Kbyte Flash
devices.

(4)

pins to ground.

SSA

Legend / Abbreviations for Tabl e 2:

Type:I = input, O = output, S = supply
Input level: A = Dedicated analog input
In/Output level: C = CMOS 0.3V

DD

/0.7

DD

CT = CMOS 0.3VDD/0.7DD with input trigger
Output level: HS = 20mA high sink (on N-buffer only)
Port and control configuration:

Input:float = floating, wpu = weak pull-up, int = interrupt
Output:OD = open drain

(b)

, PP = push-pull

(a)

, ana = analog ports

a. In the interrupt input column, “eiX” defines the associated external interrupt vector. If the weak pull-up column

(wpu) is merged with the interrupt column (int), then the I/O configuration is pull-up interrupt input, else the
configuration is floating interrupt input.

b. In the open drain output column, ‘T’ defines a true open drain I/O (P-Buffer and protection diode to V

implemented). See Section 9: I/O ports and Section 12.9: I/O port pin characteristics for more details.

18/198 Doc ID13466 Rev 4

are not

DD

ST72324B-Auto Register and memory map

0000h

RAM

Program memory

(32, 16 or 8 Kbytes)

Interrupt and reset vectors

HW registers

0080h

007Fh

7FFFh

(see Tabl e 3)

8000h

FFDFh
FFE0h

FFFFh

(see Table 25)

0480h

Reserved

047Fh

Short addressing
RAM (zero page)

256 bytes stack

16-bit addressing

RAM

0100h

01FFh

027Fh

0080h

0200h

00FFh

32 Kbytes

8000h

FFFFh

or 047Fh

16 Kbytes

C000h

(1024, 512 or 384 bytes)

8 Kbytes

E000h

3 Register and memory map

As shown in Figure 4 the MCU is capable of addressing 64 Kbytes of memories and I/O
registers.

The available memory locations consist of 128 bytes of register locations, up to 1024 bytes
of RAM and up to 32 Kbytes of user program memory. The RAM space includes up to 256
bytes for the stack from 0100h to 01FFh.

The highest address bytes contain the user reset and interrupt vectors.

Caution: Never access memory locations marked as ‘Reserved’. Accessing a reserved area can

have unpredictable effects on the device.

Figure 4. Memory map

Table 3. Hardware register map

Address Block Register label Register name

0000h
0001h
0002h

0003h
0004h
0005h

0006h
0007h
0008h

0009h
000Ah
000Bh

000Ch
000Dh

000Eh

Por t A

Por t B

Por t C

Por t D

Por t E

(2)

(1)

(1)

(1)

PA DR
PADDR
PA OR

PBDR
PBDDR
PBOR

PCDR
PCDDR
PCOR

PDADR
PDDDR
PDOR

PEDR
PEDDR
PEOR

Port A data register
Port A data direction register
Port A option register

Port B data register
Port B data direction register
Port B option register

Port C data register
Port C data direction register
Port C option register

Port D data register
Port D data direction register
Port D option register

Port E data register
Port E data direction register
Port E option register

Reset

status

00h

00h
00h

00h

00h
00h

00h

00h
00h

00h

00h
00h

00h

00h
00h

(3)

(2)

(2)

(2)

(2)

(1)

Remarks

R/W
R/W
R/W

R/W
R/W
R/W

R/W
R/W
R/W

R/W
R/W
R/W

R/W
R/W
R/W

(1)

(1)
(1)

Doc ID13466 Rev 4 19/198

Register and memory map ST72324B-Auto

Table 3. Hardware register map (continued)

Address Block Register label Register name

000Fh
0010h
0011h

0012h to

0020h

0021h
0022h
0023h

0024h
0025h
0026h
0027h

Por t F

SPI

ITC

(1)

PFDR
PFDDR
PFOR

SPIDR
SPICR
SPICSR

ISPR0
ISPR1
ISPR2
ISPR3

Port F data register
Port F data direction register
Port F option register

Reserved area (15 bytes)

SPI data I/O register
SPI control register
SPI control/status register

Interrupt software priority register 0
Interrupt software priority register 1
Interrupt software priority register 2
Interrupt software priority register 3

Reset

status

00h

00h
00h

xxh
0xh
00h

FFh
FFh
FFh
FFh

(1)

(2)

0028h EICR External interrupt control register 00h R/W

0029h Flash FCSR Flash control/status register 00h R/W

002Ah Watchdog WDGCR Watchdog control register 7Fh R/W

002Bh SI SICSR System integrity control/status register 000x 000xb R/W

002Ch
002Dh

002Eh to

0030h

MCC

MCCSR
MCCBCR

Main clock control/status register
Main clock controller: beep control register

Reserved area (3 bytes)

00h
00h

Remarks

R/W
R/W
R/W

R/W
R/W
R/W

R/W
R/W
R/W
R/W

R/W
R/W

(1)

0031h
0032h
0033h
0034h
0035h
0036h
0037h
0038h
0039h
003Ah

003Bh
003Ch
003Dh

003Eh

003Fh

Timer A

TACR2
TACR1



TACS R
TA IC 1 H R
TA IC 1 L R
TAOC 1 H R
TAOC1LR
TACHR
TACL R 
TAACHR
TA AC L R
TA IC 2 H R
TA IC 2 L R
TAOC 2 H R
TAOC2LR

Timer A control register 2
Timer A control register 1
Timer A control/status register
Timer A input capture 1 high register
Timer A input capture 1 low register
Timer A output compare 1 high register
Timer A output compare 1 low register
Timer A counter high register
Timer A counter low register
Timer A alternate counter high register
Timer A alternate counter low register
Timer A input capture 2 high register
Timer A input capture 2 low register
Timer A output compare 2 high register
Timer A output compare 2 low register

0040h Reserved area (1 byte)

00h
00h

xxxx x0xxb

xxh
xxh
80h
00h

FFh
FCh
FFh
FCh

xxh

xxh

80h

00h

R/W
R/W
R/W
Read only
Read only
R/W
R/W
Read only
Read only
Read only
Read only
Read only
Read only
R/W
R/W

20/198 Doc ID13466 Rev 4

ST72324B-Auto Register and memory map

Table 3. Hardware register map (continued)

Address Block Register label Register name

0041h
0042h
0043h
0044h
0045h
0046h
0047h
0048h
0049h
004Ah

004Bh
004Ch
004Dh

004Eh

004Fh

0050h

0051h

0052h

0053h

0054h

0055h

0056h

0057h

Timer B

SCI

TBCR2
TBCR1
TBCSR
TBIC1HR
TBIC1LR
TBOC1HR
TBOC1LR
TBCHR
TBCLR
TBACHR
TBACLR
TBIC2HR
TBIC2LR
TBOC2HR
TBOC2LR

SCISR
SCIDR
SCIBRR
SCICR1
SCICR2
SCIERPR



SCIETPR

Timer B control register 2
Timer B control register 1
Timer B control/status register
Timer B input capture 1 high register
Timer B input capture 1 low register
Timer B output compare 1 high register
Timer B output compare 1 low register
Timer B counter high register
Timer B counter low register
Timer B alternate counter high register
Timer B alternate counter low register
Timer B input capture 2 high register
Timer B input capture 2 low register
Timer B output compare 2 high register
Timer B output compare 2 low register

SCI status register
SCI data register
SCI baud rate register
SCI control register 1
SCI control register 2
SCI extended receive prescaler register
Reserved area
SCI extended transmit prescaler register

Reset

(1)

status

00h
00h

xxxx x0xxb

xxh
xxh
80h

00h
FFh
FCh
FFh
FCh

xxh

xxh

80h

00h

C0h

xxh

00h

x000 0000b

00h

00h

---

00h

Remarks

R/W
R/W
R/W
Read only
Read only
R/W
R/W
Read only
Read only
Read only
Read only
Read only
Read only
R/W
R/W

Read only
R/W
R/W
R/W
R/W
R/W



R/W

(1)

0058h to

006Fh

0070h
0071h
0072h

ADC

ADCCSR
ADCDRH
ADCDRL

Control/status register
Data high register
Data low register

0073h
007Fh

1. Legend: x = undefined, R/W = read/write.

2. The bits associated with unavailable pins must always keep their reset value.

3. The contents of the I/O port DR registers are readable only in output configuration. In input configuration, the values of the
I/O pins are returned instead of the DR register contents.

Reserved area (24 bytes)

Reserved area (13 bytes)

00h
00h
00h

R/W
Read only
Read only

Doc ID13466 Rev 4 21/198

Flash program memory ST72324B-Auto

4 Flash program memory

4.1 Introduction

The ST7 dual voltage High Density Flash (HDFlash) is a non-volatile memory that can be
electrically erased as a single block or by individual sectors and programmed on a byte-by­byte basis using an external V

The HDFlash devices can be programmed and erased off-board (plugged in a programming
tool) or on-board using ICP (in-circuit programming) or IAP (in-application programming).

The array matrix organization allows each sector to be erased and reprogrammed without
affecting other sectors.

4.2 Main features

● 3 Flash programming modes:

– Insertion in a programming tool. In this mode, all sectors including option bytes

can be programmed or erased.

– ICP (in-circuit programming). In this mode, all sectors including option bytes can

be programmed or erased without removing the device from the application board.

– IAP (in-application programming). In this mode, all sectors, except Sector 0, can

be programmed or erased without removing the device from the application board
and while the application is running.

● ICT (in-circuit testing) for downloading and executing user application test patterns in

RAM

● Readout protection

● Register Access Security System (RASS) to prevent accidental programming or

erasing

supply.

PP

4.3 Structure

The Flash memory is organized in sectors and can be used for both code and data storage.

Depending on the overall Flash memory size in the microcontroller device, there are up to
three user sectors (see
unnecessary erasing of the whole Flash memory when only a partial erasing is required.

The first two sectors have a fixed size of 4 Kbytes (see Figure 5). They are mapped in the
upper part of the ST7 addressing space so the reset and interrupt vectors are located in
Sector 0 (F000h-FFFFh).

Table 4. Sectors available in Flash devices

Flash size (bytes) Available sectors

22/198 Doc ID13466 Rev 4

Ta ble 4). Each of these sectors can be erased independently to avoid

4K Sector 0

8K Sectors 0, 1

>8K Sectors 0, 1, 2

ST72324B-Auto Flash program memory

4Kbytes

4Kbytes

Sector 1

Sector 0

Sector 2

8K 16K

32K

Flash

FFFFh

EFFFh

DFFFh

7FFFh

24 Kbytes

memory size

8Kbytes

BFFFh

4.3.1 Readout protection

Readout protection, when selected, provides a protection against program memory content
extraction and against write access to Flash memory. Even if no protection can be
considered as totally unbreakable, the feature provides a very high level of protection for a
general purpose microcontroller.

In Flash devices, this protection is removed by reprogramming the option. In this case, the
entire program memory is first automatically erased.

Readout protection selection depends on the device type:

● In Flash devices it is enabled and removed through the FMP_R bit in the option byte.

● In ROM devices it is enabled by mask option specified in the option list.

Figure 5. Memory map and sector address

4.4 ICC interface

ICC needs a minimum of 4 and up to 6 pins to be connected to the programming tool (see

Figure 6). These pins are:

● RESET: device reset

● V

● ICCCLK: ICC output serial clock pin

● ICCDATA: ICC input/output serial data pin

● ICCSEL/V

● OSC1 (or OSCIN): main clock input for external source (optional)

● V

: device power supply ground

SS

: programming voltage

PP

: application board power supply (optional, see Figure 6, Note 3).

DD

Doc ID13466 Rev 4 23/198

Flash program memory ST72324B-Auto

ICC connector

ICCDATA

ICCCLK

RESET

V

DD

HE10 connector type

Application
power supply

1

246810

975 3

Programming tool

ICC connector

Application board

ICC cable

(See note 3)

10k

V

SS

ICCSEL/VPP

ST7

OSC1

OSC2

Mandatory for

See note 1

See note 2

Application

reset source

Application

I/O

(see note 4)

8/16 Kbyte Flash devices

Figure 6. Typical ICC interface

1. If the ICCCLK or ICCDATA pins are only used as outputs in the application, no signal isolation is
necessary. As soon as the programming tool is plugged to the board, even if an ICC session is not in
progress, the ICCCLK and ICCDATA pins are not available for the application. If they are used as inputs by
the application, isolation such as a serial resistor has to be implemented in case another device forces the
signal. Refer to the Programming Tool documentation for recommended resistor values.

2. During the ICC session, the programming tool must control the RESET
between the programming tool and the application reset circuit if it drives more than 5mA at high level
(PUSH-pull output or pull-up resistor <1K). A schottky diode can be used to isolate the application reset
circuit in this case. When using a classical RC network with R>1K or a reset management IC with open
drain output and pull-up resistor >1K, no additional components are needed. In all cases the user must
ensure that no external reset is generated by the application during the ICC session.

3. The use of Pin 7 of the ICC connector depends on the programming tool architecture. This pin must be
connected when using most ST programming tools (it is used to monitor the application power supply).
Please refer to the programming tool manual.

4. Pin 9 has to be connected to the OSC1 (OSCIN) pin of the ST7 when the clock is not available in the
application or if the selected clock option is not programmed in the option byte. ST7 devices with multi­oscillator capability need to have OSC2 grounded in this case.

pin. This can lead to conflicts

Caution: External clock ICC entry mode is mandatory in ST72F324B 8/16 Kbyte Flash devices. In

this case pin 9 must be connected to the OSC1 (OSCIN) pin of the ST7 and OSC2 must be
grounded. 32 Kbyte Flash devices may use external clock or application clock ICC entry
mode.

4.5 ICP (in-circuit programming)

To perform ICP the microcontroller must be switched to ICC (in-circuit communication) mode
by an external controller or programming tool.

Depending on the ICP code downloaded in RAM, Flash memory programming can be fully

24/198 Doc ID13466 Rev 4

customized (number of bytes to program, program locations, or selection serial
communication interface for downloading).

When using an STMicroelectronics or third-party programming tool that supports ICP and
the specific microcontroller device, the user needs only to implement the ICP hardware
interface on the application board (see
to the device pinout description.

Figure 6). For more details on the pin locations, refer

ST72324B-Auto Flash program memory

4.6 IAP (in-application programming)

This mode uses a BootLoader program previously stored in Sector 0 by the user (in ICP
mode or by plugging the device in a programming tool).

This mode is fully controlled by user software. This allows it to be adapted to the user
application, (such as user-defined strategy for entering programming mode, choice of
communications protocol used to fetch the data to be stored). For example, it is possible to
download code from the SPI, SCI, USB or CAN interface and program it in the Flash. IAP
mode can be used to program any of the Flash sectors except Sector 0, which is write/erase
protected to allow recovery in case errors occur during the programming operation.

4.7 Related documentation

For details on Flash programming and ICC protocol, refer to the ST7 Flash Programming
Reference Manual and to the ST7 ICC Protocol Reference Manual

4.7.1 Flash Control/Status Register (FCSR)

This register is reserved for use by programming tool software. It controls the Flash
programming and erasing operations.

FCSR Reset value:0000 0000 (00h)

76543210

.

00000000

R/W R/W R/W R/W R/W R/W R/W R/W

Table 5. Flash control/status register address and reset value

Address (Hex) Register label 7 6 5 4 3 2 1 0

0029h FCSR reset value 0 0 0 0 0 0 0 0

Doc ID13466 Rev 4 25/198

Central processing unit (CPU) ST72324B-Auto

Accumulator

X index register

Y index register

Stack pointer

Condition code register

Program counter

70

1C1I1HI0NZ

Reset value = reset vector @ FFFEh-FFFFh

70

70

70

0

7

15 8

PCH

PCL

15

87 0

Reset value = stack higher address

Reset value = 1 X11X1XX

Reset value = XXh

Reset value = XXh

Reset value = XXh

X = undefined value

5 Central processing unit (CPU)

5.1 Introduction

This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8­bit data manipulation.

5.2 Main features

● Enable executing 63 basic instructions

● Fast 8-bit by 8-bit multiply

● 17 main addressing modes (with indirect addressing mode)

● Two 8-bit index registers

● 16-bit stack pointer

● Low power Halt and Wait modes

● Priority maskable hardware interrupts

● Non-maskable software/hardware interrupts

5.3 CPU registers

The six CPU registers shown in Figure 7 are not present in the memory mapping and are
accessed by specific instructions.

Figure 7. CPU registers

26/198 Doc ID13466 Rev 4

ST72324B-Auto Central processing unit (CPU)

5.3.1 Accumulator (A)

The Accumulator is an 8-bit general purpose register used to hold operands and the results
of the arithmetic and logic calculations and to manipulate data.

5.3.2 Index registers (X and Y)

These 8-bit registers are used to create effective addresses or as temporary storage areas
for data manipulation. (The Cross-Assembler generates a precede instruction (PRE) to
indicate that the following instruction refers to the Y register.)

The Y register is not affected by the interrupt automatic procedures.

5.3.3 Program counter (PC)

The program counter is a 16-bit register containing the address of the next instruction to be
executed by the CPU. It is made of two 8-bit registers PCL (Program Counter Low which is
the LSB) and PCH (Program Counter High which is the MSB).

5.3.4 Condition Code register (CC)

The 8-bit Condition Code register contains the interrupt masks and four flags representative
of the result of the instruction just executed. This register can also be handled by the PUSH
and POP instructions. These bits can be individually tested and/or controlled by specific
instructions.

CC Reset value: 111x1xxx

76543210

11I1HI0NZC

R/W R/W R/W R/W R/W R/W R/W R/W

Table 6. Arithmetic management bits

BIt Name Function

Half carry

This bit is set by hardware when a carry occurs between bits 3 and 4 of the ALU
during an ADD or ADC instructions. It is reset by hardware during the same

4H

2N

instructions.
0: No half carry has occurred.
1: A half carry has occurred.
This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD
arithmetic subroutines.

Negative

This bit is set and cleared by hardware. It is representative of the result sign of the last
arithmetic, logical or data manipulation. It is a copy of the result 7th bit.
0: The result of the last operation is positive or null.
1: The result of the last operation is negative (that is, the most significant bit is a logic

1.
This bit is accessed by the JRMI and JRPL instructions.

Doc ID13466 Rev 4 27/198

Central processing unit (CPU) ST72324B-Auto

Table 6. Arithmetic management bits (continued)

BIt Name Function

Zero (Arithmetic Management bit)

This bit is set and cleared by hardware. This bit indicates that the result of the last

1Z

0C

Table 7. Software interrupt bits

BIt Name Function

5I1

3I0

arithmetic, logical or data manipulation is zero.
0: The result of the last operation is different from zero.
1: The result of the last operation is zero.
This bit is accessed by the JREQ and JRNE test instructions.

Carry/borrow

This bit is set and cleared by hardware and software. It indicates an overflow or an
underflow has occurred during the last arithmetic operation.
0: No overflow or underflow has occurred.
1: An overflow or underflow has occurred.
This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC
instructions. It is also affected by the ‘bit test and branch’, shift and rotate instructions.

Software Interrupt Priority 1

The combination of the I1 and I0 bits determines the current interrupt software priority
(see Ta b le 8).

Software Interrupt Priority 0

The combination of the I1 and I0 bits determines the current interrupt software priority
(see Ta b le 8).

Table 8. Interrupt software priority selection

Interrupt software priority Level I1 I0

Level 0 (main)

Low

10

Level 1 01

Level 2 00

Level 3 (= interrupt disable) 1 1

High

These two bits are set/cleared by hardware when entering in interrupt. The loaded value is
given by the corresponding bits in the interrupt software priority registers (ISPRx). They can
be also set/cleared by software with the RIM, SIM, IRET, HALT, WFI and PUSH/POP
instructions.

See Section 7: Interrupts on page 41 for more details.

28/198 Doc ID13466 Rev 4

ST72324B-Auto Central processing unit (CPU)

5.3.5 Stack Pointer register (SP)

SP Reset value: 01 FFh

1514131211109876543210

00000001SP7SP6SP5SP4SP3SP2SP1SP0

R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

The Stack Pointer is a 16-bit register which is always pointing to the next free location in the
stack. It is then decremented after data has been pushed onto the stack and incremented
before data is popped from the stack (see

Since the stack is 256 bytes deep, the 8 most significant bits are forced by hardware.
Following an MCU reset, or after a Reset Stack Pointer instruction (RSP), the Stack Pointer
contains its reset value (the SP7 to SP0 bits are set) which is the stack higher address.

The least significant byte of the Stack Pointer (called S) can be directly accessed by an LD
instruction.

Note: When the lower limit is exceeded, the Stack Pointer wraps around to the stack upper limit,

without indicating the stack overflow. The previously stored information is then overwritten
and therefore lost. The stack also wraps in case of an underflow.

Figure 8).

The stack is used to save the return address during a subroutine call and the CPU context
during an interrupt. The user may also directly manipulate the stack by means of the PUSH
and POP instructions. In the case of an interrupt, the PCL is stored at the first location
pointed to by the SP. Then the other registers are stored in the next locations as shown in

Figure 8.

● When an interrupt is received, the SP is decremented and the context is pushed on the

stack.

● On return from interrupt, the SP is incremented and the context is popped from the

stack.

A subroutine call occupies two locations and an interrupt five locations in the stack area.

Doc ID13466 Rev 4 29/198

Central processing unit (CPU) ST72324B-Auto

PCH
PCL

SP

PCH
PCL

SP

PCL

PCH

X

A

CC

PCH
PCL

SP

PCL

PCH

X

A

CC

PCH
PCL

SP

PCL

PCH

X

A

CC

PCH
PCL

SP

SP

Y

Call

subroutine

Interrupt

event

Push Y Pop Y IRET

RET

or RSP

@ 01FFh

@ 0100h

Stack Higher Address = 01FFh
Stack Lower Address =

0100h

Figure 8. Stack manipulation example

30/198 Doc ID13466 Rev 4

ST72324B-Auto Supply, reset and clock management

0

1

PLL option bit

PLL x 2

f

OSC2

/ 2

f

OSC

6 Supply, reset and clock management

6.1 Introduction

The device includes a range of utility features for securing the application in critical
situations (for example in case of a power brown-out), and reducing the number of external
components. An overview is shown in

For more details, refer to dedicated parametric section.

Main features

● Optional Phase Locked Loop (PLL) for multiplying the frequency by 2 (not to be used

with internal RC oscillator in order to respect the max. operating frequency)

● Multi-Oscillator clock management (MO)

– 5 crystal/ceramic resonator oscillators
– 1 Internal RC oscillator

● Reset Sequence Manager (RSM)

● System Integrity management (SI)

– Main supply low voltage detection (LVD)
– Auxiliary voltage detector (AVD) with interrupt capability for monitoring the main

supply

Figure 10.

6.2 PLL (phase locked loop)

If the clock frequency input to the PLL is in the range 2 to 4 MHz, the PLL can be used to
multiply the frequency by two to obtain an f
byte. If the PLL is disabled, then f

OSC2

= f

Caution: The PLL is not recommended for applications where timing accuracy is required.

Furthermore, it must not be used with the internal RC oscillator.

Figure 9. PLL block diagram

of 4 to 8 MHz. The PLL is enabled by option

OSC2

/2.

OSC

Doc ID13466 Rev 4 31/198

Supply, reset and clock management ST72324B-Auto

Low Voltage

Detector

(LVD)

f

OSC2

Auxiliary Voltage

Detector

(AVD)

Multi-

Oscillator

(MO)

OSC1

RESET

V

SS

V

DD

Reset Sequence

Manager

(RSM)

OSC2

Main Clock

AVD Interrupt Request

Controller

PLL

System Integrity Management

Watchdog

SICSR

timer (WDG)

with Real-time

Clock (MCC/RTC)

AVD AVD

LV D

RF

IE

WDG

RF

f

OSC

(option)

0

F

f

CPU

00

0

Figure 10. Clock, reset and supply block diagram

6.3 Multi-oscillator (MO)

The main clock of the ST7 can be generated by three different source types coming from the
multi-oscillator block:

● an external source

● 4 crystal or ceramic resonator oscillators

● an internal high frequency RC oscillator

Each oscillator is optimized for a given frequency range in terms of consumption and is
selectable through the option byte. The associated hardware configurations are shown in

Ta bl e 9. Refer to the electrical characteristics section for more details.

Caution: The OSC1 and/or OSC2 pins must not be left unconnected. For the purposes of Failure

Mode and Effect Analysis, it should be noted that if the OSC1 and/or OSC2 pins are left
unconnected, the ST7 main oscillator may start and, in this configuration, could generate an
f

clock frequency in excess of the allowed maximum (> 16 MHz.), putting the ST7 in an

OSC

6.3.1 External clock source

unsafe/undefined state. The product behavior must therefore be considered undefined when
the OSC pins are left unconnected.

In this external clock mode, a clock signal (square, sinus or triangle) with ~50% duty cycle
has to drive the OSC1 pin while the OSC2 pin is tied to ground.

32/198 Doc ID13466 Rev 4

ST72324B-Auto Supply, reset and clock management

OSC1 OSC2

External

ST7

source

OSC1 OSC2

Load

capacitors

ST7

C

L2

C

L1

OSC1 OSC2

ST7

6.3.2 Crystal/ceramic oscillators

This family of oscillators has the advantage of producing a very accurate rate on the main
clock of the ST7. The selection within a list of four oscillators with different frequency ranges
has to be done by option byte in order to reduce consumption (refer to

Section 14.1 on page

179 for more details on the frequency ranges). In this mode of the multi-oscillator, the

resonator and the load capacitors have to be placed as close as possible to the oscillator
pins in order to minimize output distortion and start-up stabilization time. The loading
capacitance values must be adjusted according to the selected oscillator.

These oscillators are not stopped during the reset phase to avoid losing time in the oscillator
start-up phase.

6.3.3 Internal RC oscillator

This oscillator allows a low cost solution for the main clock of the ST7 using only an internal
resistor and capacitor. Internal RC oscillator mode has the drawback of a lower frequency
accuracy and should not be used in applications that require accurate timing.

In this mode, the two oscillator pins have to be tied to ground.

In order not to exceed the maximum operating frequency, the internal RC oscillator must not
be used with the PLL.

Table 9. ST7 clock sources

Hardware configuration

External clockCrystal/ceramic resonatorsInternal RC oscillator

Doc ID13466 Rev 4 33/198

Supply, reset and clock management ST72324B-Auto

RESET

ACTIVE PHASE

INTERNAL RESET

256 or 4096 CLOCK CYCLES

FETCH

VECTOR

6.4 Reset sequence manager (RSM)

The reset sequence manager includes three reset sources as shown in Figure 12:

● External reset source pulse

● Internal LVD reset

● Internal Watchdog reset

These sources act on the RESET pin and it is always kept low during the delay phase.

The reset service routine vector is fixed at addresses FFFEh-FFFFh in the ST7 memory
map.

The basic reset sequence consists of three phases as shown in Figure 11:

● Active Phase depending on the reset source

● 256 or 4096 CPU clock cycle delay (selected by option byte)

● Reset vector fetch

Caution: When the ST7 is unprogrammed or fully erased, the Flash is blank and the RESET vector is

not programmed. For this reason, it is recommended to keep the RESET pin in low state
until programming mode is entered, in order to avoid unwanted behavior.

The 256 or 4096 CPU clock cycle delay allows the oscillator to stabilize and ensures that
recovery has taken place from the reset state. The shorter or longer clock cycle delay
should be selected by option byte to correspond to the stabilization time of the external
oscillator used in the application.

The reset vector fetch phase duration is two clock cycles.

Figure 11. Reset sequence phases

6.4.1 Asynchronous external RESET pin

The RESET pin is both an input and an open-drain output with integrated RON weak pull-up
resistor. This pull-up has no fixed value but varies in accordance with the input voltage. It
can be pulled low by external circuitry to reset the device. See the Electrical characteristics
section for more details.

A reset signal originating from an external source must have a duration of at least t
in order to be recognized (see
MCU can enter reset state even in Halt mode.

Figure 13). This detection is asynchronous and therefore the

h(RSTL)in

34/198 Doc ID13466 Rev 4

ST72324B-Auto Supply, reset and clock management

RESET

R

ON

V

DD

Watchdog reset

LVD reset

Internal
reset

Pulse

generator

Filter

Figure 12. Reset block diagram

The RESET pin is an asynchronous signal which plays a major role in EMS performance. In
a noisy environment, it is recommended to follow the guidelines mentioned in the electrical
characteristics section.

External power-on reset

If the LVD is disabled by option byte, to start up the microcontroller correctly, the user must
ensure by means of an external reset circuit that the reset signal is held low until V
the minimum level specified for the selected f

frequency.

OSC

A proper reset signal for a slow rising VDD supply can generally be provided by an external
RC network connected to the

RESET pin.

is over

DD

Internal LVD reset

Two different reset sequences caused by the internal LVD circuitry can be distinguished:

● Power-On reset

● Voltage Drop reset

The device RESET pin acts as an output that is pulled low when VDD < V
V

< V

DD

The LVD filters spikes on V

(falling edge) as shown in Figure 13.

IT-

larger than t

DD

to avoid parasitic resets.

g(VDD)

(rising edge) or

IT+

Internal Watchdog reset

The reset sequence generated by a internal Watchdog counter overflow is shown in

Figure 13.

Starting from the Watchdog counter underflow, the device RESET pin acts as an output that
is pulled low during at least t

w(RSTL)out

.

Doc ID13466 Rev 4 35/198

Supply, reset and clock management ST72324B-Auto

V

DD

Run

RESET pin

External

Watchdog

Active phase

V

IT+(LVD)

V

IT-(LVD)

t

h(RSTL)in

Run

Watchdog underflow

t

w(RSTL)out

Run Run

reset

RESET
source

External

reset

LVD

reset

Watchdog

reset

Internal reset (256 or 4096 T

CPU

)

Vector fetch

Active
phase

Active

phase

Figure 13. RESET sequences

6.5 System integrity management (SI)

The system integrity management block contains the LVD and auxiliary voltage detector
(AVD) functions. It is managed by the SICSR register.

6.5.1 LVD (low voltage detector)

The LVD function generates a static reset when the VDD supply voltage is below a V
reference value. This means that it secures the power-up as well as the power-down
keeping the ST7 in reset.

The V
on in order to avoid a parasitic reset when the MCU starts running and sinks current on the
supply (hysteresis).

The LVD reset circuitry generates a reset when VDD is below:

● V

● V

The LVD function is illustrated in Figure 13.

The voltage threshold can be configured by option byte to be low, medium or high.

reference value for a voltage drop is lower than the V

IT-

when VDD is rising

IT+

when VDD is falling

IT-

IT-

reference value for power-

IT+

36/198 Doc ID13466 Rev 4

ST72324B-Auto Supply, reset and clock management

V

DD

V

IT+

RESET

V

IT-

V

hys

Provided the minimum VDD value (guaranteed for the oscillator frequency) is above V
MCU can only be in two modes:

● under full software control

● in static safe reset

In these conditions, secure operation is always ensured for the application without the need
for external reset hardware.

During an LVD reset, the RESET pin is held low, thus permitting the MCU to reset other
devices.

Note: 1 The LVD allows the device to be used without any external reset circuitry.

2 If the medium or low thresholds are selected, the detection may occur outside the specified

operating voltage range. Below 3.8V, device operation is not guaranteed.

3 The LVD is an optional function which can be selected by option byte.

4 It is recommended to make sure that the V

supply voltage rises monotonously when the

DD

device is exiting from reset, to ensure the application functions properly.

Figure 14. Low voltage detector vs reset

IT-

, the

6.5.2 AVD (auxiliary voltage detector)

The AVD is based on an analog comparison between a V
value and the V
V

reference value for rising voltage in order to avoid parasitic detection (hysteresis).

IT+

main supply. The V

DD

reference value for falling voltage is lower than the

IT-

The output of the AVD comparator is directly readable by the application software through a
real-time status bit (AVDF) in the SICSR register. This bit is read only.

Caution: The AVD function is active only if the LVD is enabled through the option byte (see

Section 14.1 on page 179).

Monitoring the VDD main supply

The AVD voltage threshold value is relative to the selected LVD threshold configured by
option byte (see

If the AVD interrupt is enabled, an interrupt is generated when the voltage crosses the
V

IT+(AVD)

or V

In the case of a drop in voltage, the AVD interrupt acts as an early warning, allowing
software to shut down safely before the LVD resets the microcontroller. See

Section 14.1 on page 179).

threshold (AVDF bit toggles).

IT-(AVD)

Doc ID13466 Rev 4 37/198

IT-(AVD)

and V

IT+(AVD)

Figure 15.

reference

Supply, reset and clock management ST72324B-Auto

V

DD

V

IT+(AVD)

V

IT-(AVD)

AVDF bit 0 0Reset value

if AVDIE bit = 1

V

hyst

AVD Interrupt
Request

Interrupt process

Interrupt process

V

IT+(LVD)

V

IT-(LVD)

LVD RESET

Early warning interrupt
(power has dropped, MCU not
not yet in reset)

1

1

t

rv

Voltage rise time

The interrupt on the rising edge is used to inform the application that the VDD warning state
is over.

If the voltage rise time trv is less than 256 or 4096 CPU cycles (depending on the reset delay
selected by option byte), no AVD interrupt will be generated when V

IT+(AVD)

is reached.

If trv is greater than 256 or 4096 cycles then:

● If the AVD interrupt is enabled before the V

IT+(AVD)

threshold is reached, then 2 AVD
interrupts will be received: the first when the AVDIE bit is set, and the second when the
threshold is reached.

● If the AVD interrupt is enabled after the V

IT+(AVD)

threshold is reached then only one

AVD interrupt will occur.

Figure 15. Using the AVD to monitor V

6.5.3 Low power modes

Table 10. Effect of low power modes on SI

DD

Mode Description

Wait No effect on SI. AVD interrupt causes the device to exit from Wait mode.

Halt The CRSR register is frozen.

6.5.4 Interrupts

The AVD interrupt event generates an interrupt if the AVDIE bit is set and the interrupt mask
in the CC register is reset (RIM instruction).

38/198 Doc ID13466 Rev 4

M

Table 11. AVD interrupt control/wake-up capability

Interrupt event Event flag Enable Control bit Exit from WAIT Exit from HALT

AVD event AVDF AVDIE Yes No

ST72324B-Auto Supply, reset and clock management

6.6 SI registers

6.6.1 System integrity (SI) control/status register (SICSR)

SICSR Reset value: 000x 000x (00h)

76543210

Res AVDIE AVDF LVDRF Reserved WDGRF

- R/W RO R/W - R/W

Table 12. SICSR register description

Bit Name Function

7 - Reserved, must be kept cleared

Voltage Detector Interrupt Enable

This bit is set and cleared by software. It enables an interrupt to be generated

6AVDIE

5AVDF

4 LVDRF

3:1 - Reserved, must be kept cleared

0 WDGRF

when the AVDF flag changes (toggles). The pending interrupt information is
automatically cleared when software enters the AVD interrupt routine
0: AVD interrupt disabled
1: AVD interrupt enabled

Voltage Detector Flag

This read-only bit is set and cleared by hardware. If the AVDIE bit is set, an
interrupt request is generated when the AVDF bit changes value. Refer to

Figure 15 and to Section 6.5.2: AVD (auxiliary voltage detector) for additional

details.
0: V
1: V

over V

DD

under V

DD

IT+(AVD)

IT-(AVD)

threshold

threshold

LVD Reset Flag

This bit indicates that the last reset was generated by the LVD block. It is set by
hardware (LVD reset) and cleared by software (writing zero). See WDGRF flag
description for more details. When the LVD is disabled by option byte, the LVDRF
bit value is undefined.

Watchdog Reset Flag

This bit indicates that the last reset was generated by the Watchdog peripheral. It is
set by hardware (watchdog reset) and cleared by software (writing zero) or an LVD
reset (to ensure a stable cleared state of the WDGRF flag when CPU starts).
Combined with the LVDRF information, the flag description is given in Table 13.

Table 13. Reset source flags

Reset sources LVDRF WDGRF

External RESET

Watchdog 0 1

LV D 1 X

Doc ID13466 Rev 4 39/198

pin 0 0

Supply, reset and clock management ST72324B-Auto

Application notes

The LVDRF flag is not cleared when another reset type occurs (external or watchdog); the
LVDRF flag remains set to keep trace of the original failure. In this case, a watchdog reset
can be detected by software while an external reset cannot.

Caution: When the LVD is not activated with the associated option byte, the WDGRF flag can not be

used in the application.

40/198 Doc ID13466 Rev 4

ST72324B-Auto Interrupts

7 Interrupts

7.1 Introduction

The ST7 enhanced interrupt management provides the following features:

● Hardware interrupts

● Software interrupt (TRAP)

● Nested or concurrent interrupt management with flexible interrupt priority and level

management:
– up to 4 software programmable nesting levels
– up to 16 interrupt vectors fixed by hardware
– 2 non-maskable events: reset, TRAP

This interrupt management is based on:

● Bit 5 and bit 3 of the CPU CC register (I1:0)

● Interrupt software priority registers (ISPRx)

● Fixed interrupt vector addresses located at the high addresses of the memory map

(FFE0h to FFFFh) sorted by hardware priority order

This enhanced interrupt controller guarantees full upward compatibility with the standard
(not nested) ST7 interrupt controller.

7.2 Masking and processing flow

The interrupt masking is managed by the I1 and I0 bits of the CC register and the ISPRx
registers which give the interrupt software priority level of each interrupt vector (see

Ta bl e 14). The processing flow is shown in Figure 16.

When an interrupt request has to be serviced:

● Normal processing is suspended at the end of the current instruction execution.

● The PC, X, A and CC registers are saved onto the stack.

● I1 and I0 bits of CC register are set according to the corresponding values in the ISPRx

registers of the serviced interrupt vector.

● The PC is then loaded with the interrupt vector of the interrupt to service and the first

instruction of the interrupt service routine is fetched (refer to Table 25: Interrupt

mapping for vector addresses).

The interrupt service routine should end with the IRET instruction which causes the
contents of the saved registers to be recovered from the stack.

Note: As a consequence of the IRET instruction, the I1 and I0 bits will be restored from the stack

and the program in the previous level will resume.

Doc ID13466 Rev 4 41/198

Interrupts ST72324B-Auto

“IRET”

RESTORE PC, X, A, CC

Stack PC, X, A, CC

load I1:0 from interrupt SW reg.

Fetch next

Reset

TRAP

Pending

Instruction

I1:0

from stack

load PC from interrupt vector

Y

N

Y

N

Y

N

Interrupt has the same or a

lower software priority

The interrupt

stays pending

than current one

Interrupt has a higher

software priority

than current one

Execute

instruction

Interrupt

PENDING

SOFTWARE

Different

INTERRUPTS

Same

HIGHEST HARDWARE
PRIORITY SERVICED

PRIORITY

HIGHEST SOFTWARE
PRIORITY SERVICED

Table 14. Interrupt software priority levels

Interrupt software priority Level I1 I0

Level 0 (main) Low

10

Level 1 0 1

Level 2 0 0

Level 3 (= interrupt disable) 1 1

High

Figure 16. Interrupt processing flowchart

7.2.1 Servicing pending interrupts

As several interrupts can be pending at the same time, the interrupt to be taken into account
is determined by the following two-step process:

● the highest software priority interrupt is serviced,

● if several interrupts have the same software priority then the interrupt with the highest

hardware priority is serviced first.

Figure 17 describes this decision process.

Figure 17. Priority decision process flowchart

42/198 Doc ID13466 Rev 4

ST72324B-Auto Interrupts

When an interrupt request is not serviced immediately, it is latched and then processed
when its software priority combined with the hardware priority becomes the highest one.

Note: 1 The hardware priority is exclusive while the software one is not. This allows the previous

process to succeed with only one interrupt.

2 Reset and TRAP can be considered as having the highest software priority in the decision

process.

7.2.2 Different interrupt vector sources

Two interrupt source types are managed by the ST7 interrupt controller: the non-maskable
type (reset, TRAP) and the maskable type (external or from internal peripherals).

7.2.3 Non-maskable sources

These sources are processed regardless of the state of the I1 and I0 bits of the CC register
(see

Figure 16). After stacking the PC, X, A and CC registers (except for reset), the

corresponding vector is loaded in the PC register and the I1 and I0 bits of the CC are set to
disable interrupts (level 3). These sources allow the processor to exit Halt mode.

TRAP (non-maskable software interrupt)

This software interrupt is serviced when the TRAP instruction is executed. It will be serviced
according to the flowchart in

Figure 16.

Reset

The reset source has the highest priority in the ST7. This means that the first current routine
has the highest software priority (level 3) and the highest hardware priority.

See the reset chapter for more details.

7.2.4 Maskable sources

Maskable interrupt vector sources can be serviced if the corresponding interrupt is enabled
and if its own interrupt software priority (in ISPRx registers) is higher than the one currently
being serviced (I1 and I0 in CC register). If any of these two conditions is false, the interrupt
is latched and thus remains pending.

External interrupts

External interrupts allow the processor to Exit from Halt low power mode. External interrupt
sensitivity is software selectable through the External Interrupt Control register (EICR).

External interrupt triggered on edge will be latched and the interrupt request automatically
cleared upon entering the interrupt service routine.

If several input pins of a group connected to the same interrupt line are selected
simultaneously, these will be logically ORed.

Peripheral interrupts

Usually the peripheral interrupts cause the MCU to Exit from Halt mode except those
mentioned in
is set in the peripheral status registers and if the corresponding enable bit is set in the

Ta ble 25: Interrupt mapping. A peripheral interrupt occurs when a specific flag

Doc ID13466 Rev 4 43/198

Interrupts ST72324B-Auto

Main

IT4

IT2

IT1

TRAP

IT1

Main

IT0

I1

Hardware priority

Software

3

3

3

3

3

3/0

3

11

11

11

11

11

11/10

11

RIM

IT2

IT1

IT4

TRAP

IT3

IT0

IT3

I0

10

priority
level

Used stack = 10 bytes

peripheral control register. The general sequence for clearing an interrupt is based on an
access to the status register followed by a read or write to an associated register.

Note: The clearing sequence resets the internal latch. A pending interrupt (that is, waiting to be

serviced) is therefore lost if the clear sequence is executed.

7.3 Interrupts and low power modes

All interrupts allow the processor to exit the Wait low power mode. On the contrary, only
external and other specified interrupts allow the processor to exit from the Halt modes (see
column Exit from HALT in

Ta bl e 25: Interrupt mapping). When several pending interrupts are

present while exiting Halt mode, the first one serviced can only be an interrupt with Exit from
Halt mode capability and it is selected through the same decision process shown in

Figure 17.

Note: If an interrupt, that is not able to exit from Halt mode, is pending with the highest priority

when exiting Halt mode, this interrupt is serviced after the first one serviced.

7.4 Concurrent and nested management

Figure 18 and Figure 19 show two different interrupt management modes. The first is called

concurrent mode and does not allow an interrupt to be interrupted, unlike the nested mode
in

Figure 19. The interrupt hardware priority is given in order from the lowest to the highest

as follows: MAIN, IT4, IT3, IT2, IT1, IT0. Software priority is given for each interrupt.

Warning: A stack overflow may occur without notifying the software of

the failure.

Figure 18. Concurrent interrupt management

44/198 Doc ID13466 Rev 4

ST72324B-Auto Interrupts

Main

IT2

TRAP

Main

IT0

IT2

IT1

IT4

TRAP

IT3

IT0

Hardware priority

3

2

1

3

3

3/0

3

11

00

01

11

11

11

RIM

IT1

IT4

IT4

IT1

IT2

IT3

I1

I0

11 / 10

10

Software
priority
level

Used stack = 20 bytes

Figure 19. Nested interrupt management

7.5 Interrupt registers

7.5.1 CPU CC register interrupt bits

CPU CC Reset value: 111x 1010(xAh)

76543210

11I1 H I0 NZC

R/ WR/ WR/ WR/ WR/ WR/ WR/ WR/ W

Table 15. CPU CC register interrupt bits description

Bit Name Function

5 I1 Software Interrupt Priority 1

3 I0 Software Interrupt Priority 0

Table 16. Interrupt software priority levels

Interrupt software priority Level I1 I0

Level 0 (main) Low

10

Level 1 0 1

Level 2 0 0

Level 3 (= interrupt disable)

1. TRAP and RESET events can interrupt a level 3 program.

(1)

High

11

These two bits indicate the current interrupt software priority (see Ta ble 16) and are
set/cleared by hardware when entering in interrupt. The loaded value is given by the
corresponding bits in the interrupt software priority registers (ISPRx).

Doc ID13466 Rev 4 45/198

Interrupts ST72324B-Auto

They can be also set/cleared by software with the RIM, SIM, HALT, WFI, IRET and
PUSH/POP instructions (see

Ta bl e 18: Dedicated interrupt instruction set).

7.5.2 Interrupt software priority registers (ISPRx)

ISPRx Reset value: 1111 1111 (FFh)

76543210

ISPR0 I1_3 I0_3 I1_2 I0_2 I1_1 I0_1 I1_0 I0_0

ISPR1 I1_7 I0_7 I1_6 I0_6 I1_5 I0_5 I1_4 I0_4

ISPR2 I1_11 I0_11 I1_10 I0_10 I1_9 I0_9 I1_8 I0_8

R/WR/WR/WR/WR/WR/WR/WR/W

ISPR31111I1_13I0_13I1_12I0_12

RO RO RO RO R/W R/W R/W R/W

These four registers contain the interrupt software priority of each interrupt vector.

● Each interrupt vector (except reset and TRAP) has corresponding bits in these

registers where its own software priority is stored. This correspondence is shown in the
following Tab l e 1 7 .

Table 17. ISPRx interrupt vector correspondence

Vector address ISPRx bits

FFFBh-FFFAh I1_0 and I0_0 bits

FFF9h-FFF8h I1_1 and I0_1 bits

... ...

FFE1h-FFE0h I1_13 and I0_13 bits

● Each I1_x and I0_x bit value in the ISPRx registers has the same meaning as the I1

and I0 bits in the CC register.

● Level 0 cannot be written (I1_x = 1, I0_x = 0). In this case, the previously stored value

is kept (for example, previous value = CFh, write = 64h, result = 44h).

The reset, and TRAP vectors have no software priorities. When one is serviced, the I1 and
I0 bits of the CC register are both set.

Caution: If the I1_x and I0_x bits are modified while the interrupt x is executed the following behavior

has to be considered: If the interrupt x is still pending (new interrupt or flag not cleared) and
the new software priority is higher than the previous one, the interrupt x is re-entered.
Otherwise, the software priority stays unchanged up to the next interrupt request (after the
IRET of the interrupt x).

Table 18. Dedicated interrupt instruction set

Instruction New description Function/example I1 H I0 N Z C

(1)

HALT Entering HALT mode 1 0

46/198 Doc ID13466 Rev 4

ST72324B-Auto Interrupts

Table 18. Dedicated interrupt instruction set

(1)

(continued)

Instruction New description Function/example I1 H I0 N Z C

IRET Interrupt routine return POP CC, A, X, PC I1 H I0 N Z C

JRM Jump if I1:0=11 (level 3) I1:0=11 ?

JRNM Jump if I1:0<>11 I1:0<>11 ?

POP CC POP CC from the Stack Mem => CC I1 H I0 N Z C

RIM Enable interrupt (level 0 set) Load 10 in I1:0 of CC 1 0

SIM Disable interrupt (level 3 set) Load 11 in I1:0 of CC 1 1

TRAP Software TRAP Software NMI 1 1

WFI WAIT for interrupt 1 0

1. During the execution of an interrupt routine, the HALT, POP CC, RIM, SIM and WFI instructions change
the current software priority up to the next IRET instruction or one of the previously mentioned instructions.

Doc ID13466 Rev 4 47/198

Interrupts ST72324B-Auto

IS10 IS11

EICR

PBOR.3

PBDDR.3

IPB BIT

PB3

ei2 interrupt source

Port B [3:0] interrupts

PB3
PB2
PB1
PB0

IS10 IS11

EICR

PBOR.4

PBDDR.4

PB4

ei3 interrupt source

Port B4 interrupt

IS20 IS21

EICR

PAOR.3

PADDR.3

IPA BIT

PA3

ei0 interrupt source

Port A3 interrupt

IS20 IS21

EICR

PFOR.2

PFDDR.2

PF2

ei1 interrupt source

Port F [2:0] interrupts

PF2
PF1
PF0

Sensitivity

control

Sensitivity

control

Sensitivity

Sensitivity

control

control

7.6 External interrupts

7.6.1 I/O port interrupt sensitivity

The external interrupt sensitivity is controlled by the IPA, IPB and ISxx bits of the EICR
register (
sensitivities.

Each external interrupt source can be generated on four (or five) different events on the pin:

● Falling edge

● Rising edge

● Falling and rising edge

● Falling edge and low level

● Rising edge and high level (only for ei0 and ei2)

To guarantee correct functionality, the sensitivity bits in the EICR register can be modified
only when the I1 and I0 bits of the CC register are both set to 1 (level 3). This means that
interrupts must be disabled before changing sensitivity.

The pending interrupts are cleared by writing a different value in the ISx[1:0], IPA or IPB bits
of the EICR.

Figure 20). This control allows up to four fully independent external interrupt source

Figure 20. External interrupt control bits

48/198 Doc ID13466 Rev 4

ST72324B-Auto Interrupts

7.6.2 External interrupt control register (EICR)

EICR Reset value: 0000 0000 (00h)

76543210

IS11 IS10 IPB IS21 IS20 IPA Reserved

R/W R/W R/W R/W R/W R/W -

Table 19. EICR register description

Bit Name Function

ei2 and ei3 sensitivity

The interrupt sensitivity, defined using the IS1[1:0] bits, is applied to the following
external interrupts:

7:6 IS1[1:0]

5IPB

4:3 IS2[1:0]

- ei2 for port B [3:0] (see Tabl e 2 0 )

- ei3 for port B4 (see Table 21
Bits 7 and 6 can only be written when I1 and I0 of the CC register are both set to 1
(level 3).

Interrupt Polarity (for port B)

This bit is used to invert the sensitivity of port B [3:0] external interrupts. It can be
set and cleared by software only when I1 and I0 of the CC register are both set to 1
(level 3).
0: No sensitivity inversion
1: Sensitivity inversion

ei0 and ei1 sensitivity

The interrupt sensitivity, defined using the IS2[1:0] bits, is applied to the following
external interrupts:

- ei0 for port A[3:0] (see Ta ble 22 )

- ei1 for port F[2:0] (see Ta ble 2 3 )
Bits 4 and 3 can only be written when I1 and I0 of the CC register are both set to 1

(level 3).

Interrupt Polarity (for port A)

This bit is used to invert the sensitivity of port A [3:0] external interrupts. It can be

2IPA

set and cleared by software only when I1 and I0 of the CC register are both set to 1
(level 3).
0: No sensitivity inversion.
1: Sensitivity inversion.

1:0 - Reserved, must always be kept cleared

Table 20. Interrupt sensitivity - ei2

External interrupt sensitivity

IS11 IS10

IPB bit = 0 IPB bit = 1

0 0 Falling edge and low level Rising edge and high level

0 1 Rising edge only Falling edge only

1 0 Falling edge only Rising edge only

1 1 Rising and falling edge

Doc ID13466 Rev 4 49/198

Interrupts ST72324B-Auto

Table 21. Interrupt sensitivity - ei3

IS11 IS10 External interrupt sensitivity

0 0 Falling edge and low level

0 1 Rising edge only

1 0 Falling edge only

1 1 Rising and falling edge

Table 22. Interrupt sensitivity - ei0

External interrupt sensitivity

IS21 IS20

IPA bit = 0 IPA bit = 1

0 0 Falling edge and low level Rising edge and high level

0 1 Rising edge only Falling edge only

1 0 Falling edge only Rising edge only

1 1 Rising and falling edge

Table 23. Interrupt sensitivity - ei1

IS21 IS20 External interrupt sensitivity

0 0 Falling edge and low level

0 1 Rising edge only

1 0 Falling edge only

1 1 Rising and falling edge

Table 24. Nested interrupts register map and reset values

Address (Hex.)Register label76543210

ei1 ei0 MCC + SI

0024h

ISPR0
reset value

I1_31I0_31I1_21I0_21I1_11I0_1

111

SPI ei3 ei2

0025h

ISPR1
reset value

I1_71I0_71I1_61I0_61I1_51I0_51I1_41I0_4

1

AVD SCI Timer B Timer A

0026h

0027h

ISPR2

I1_111I0_111I1_101I0_101I1_91I0_91I1_81I0_8

reset value

ISPR3

I1_131I0_131I1_121I0_12

reset value 1111

1

1

0028h

EICR
reset value

IS110IS100IPB0IS210IS200IPA

50/198 Doc ID13466 Rev 4

000

ST72324B-Auto Interrupts

Table 25. Interrupt mapping

No.

Source

block

Reset Reset

Description

Register

label

Priority

order

Exit from

Halt/Active Halt

Address vector

yes FFFEh-FFFFh

N/A

TRAP Software interrupt no FFFCh-FFFDh

0 Not used FFFAh-FFFBh

1 MCC/RTC

Main clock controller time base
interrupt

2 ei0 External interrupt port A3..0

MCCSR

Higher

priority

yes FFF8h-FFF9h

yes FFF6h-FFF7h

3 ei1 External interrupt port F2..0 yes FFF4h-FFF5h

N/A

4 ei2 External interrupt port B3..0 yes FFF2h-FFF3h

5 ei3 External interrupt port B7..4 yes FFF0h-FFF1h

6 Not used FFEEh-FFEFh

7 SPI SPI peripheral interrupts SPICSR yes FFECh-FFEDh

8 Timer A Timer A peripheral interrupts TASR no FFEAh-FFEBh

9 Timer B Timer B peripheral interrupts TBSR no FFE8h-FFE9h

10 SCI SCI peripheral interrupts SCISR

11 AVD Auxiliary voltage detector interrupt SICSR no FFE4h-FFE5h

Lower

priority

no FFE6h-FFE7h

Doc ID13466 Rev 4 51/198

Power saving modes ST72324B-Auto

Power consumption

Wait

Slow

Run

Active Halt

High

Low

Slow Wait

Halt

8 Power saving modes

8.1 Introduction

To give a large measure of flexibility to the application in terms of power consumption, four
main power saving modes are implemented in the ST7 (see
Wait), Active Halt and Halt.

After a reset the normal operating mode is selected by default (Run mode). This mode
drives the device (CPU and embedded peripherals) by means of a master clock which is
based on the main oscillator frequency divided or multiplied by 2 (f

From Run mode, the different power saving modes may be selected by setting the relevant
register bits or by calling the specific ST7 software instruction whose action depends on the
oscillator status.

Figure 21. Power saving mode transitions

Figure 21): Slow, Wait (Slow

).

OSC2

8.2 Slow mode

This mode has two targets:

● To reduce power consumption by decreasing the internal clock in the device,

● To adapt the internal clock frequency (f

Slow mode is controlled by three bits in the MCCSR register: the SMS bit which enables or
disables Slow mode and two CPx bits which select the internal slow frequency (f

In this mode, the master clock frequency (f
and peripherals are clocked at this lower frequency (f

Note: Slow-Wait mode is activated when entering the Wait mode while the device is already in

Slow mode.

52/198 Doc ID13466 Rev 4

) to the available supply voltage.

CPU

) can be divided by 2, 4, 8 or 16. The CPU

OSC2

CPU

).

CPU

).

ST72324B-Auto Power saving modes

00 01

SMS

CP1:0

f

CPU

New Slow

Normal Run mode

MCCSR

frequency

request

request

f

OSC2

f

OSC2

/2 f

OSC2

/4 f

OSC2

WFI instruction

Reset

Interrupt

Y

N

N

Y

CPU

Oscillator
Peripherals

I[1:0] bits

on
on

10

off

Fetch reset vector

or service interrupt

CPU

Oscillator
Peripherals

I[1:0] bits

on
off

10

on

CPU

Oscillator
Peripherals

I[1:0] bits

on
on

XX

(1)

on

256 or 4096 CPU clock

cycle delay

Figure 22. Slow mode clock transitions

8.3 Wait mode

Wait mode places the MCU in a low power consumption mode by stopping the CPU.

This power saving mode is selected by calling the ‘WFI’ instruction.

All peripherals remain active. During Wait mode, the I[1:0] bits of the CC register are forced
to ‘10’, to enable all interrupts. All other registers and memory remain unchanged. The MCU
remains in Wait mode until an interrupt or reset occurs, whereupon the Program Counter
branches to the starting address of the interrupt or reset service routine. The MCU will
remain in Wait mode until a reset or an interrupt occurs, causing it to wake up. Refer to

Figure 23.

Figure 23. Wait mode flowchart

1. Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the CC register are
set to the current software priority level of the interrupt routine and recovered when the CC register is
popped.

Doc ID13466 Rev 4 53/198

Power saving modes ST72324B-Auto

HaltRun Run

256 or 4096 CPU

cycle delay

(1)

Reset

or

interrupt

Halt

instruction

Fetch

vector

Active

[MCCSR.OIE = 1]

8.4 Active Halt and Halt modes

Active Halt and Halt modes are the two lowest power consumption modes of the MCU. They
are both entered by executing the ‘HALT’ instruction. The decision to enter either in Active
Halt or Halt mode is given by the MCC/RTC interrupt enable flag (OIE bit in the MCCSR
register).

Table 26. MCC/RTC low power mode selection

MCCSR OIE bit Power saving mode entered when HALT instruction is executed

0 Halt mode

1 Active Halt mode

8.4.1 Active Halt mode

Active Halt mode is the lowest power consumption mode of the MCU with a real-time clock
available. It is entered by executing the ‘HALT’ instruction when the OIE bit of the Main Clock
Controller Status register (MCCSR) is set (see

time clock and beeper (MCC/RTC) on page 69 for more details on the MCCSR register).

The MCU can exit Active Halt mode on reception of either an MCC/RTC interrupt, a specific
interrupt (see

Ta bl e 25: Interrupt mapping) or a reset. When exiting Active Halt mode by

means of an interrupt, no 256 or 4096 CPU cycle delay occurs. The CPU resumes operation
by servicing the interrupt or by fetching the reset vector which woke it up (see

When entering Active Halt mode, the I[1:0] bits in the CC register are forced to ‘10b’ to
enable interrupts. Therefore, if an interrupt is pending, the MCU wakes up immediately.

Section 10.2: Main clock controller with real-

Figure 25).

In Active Halt mode, only the main oscillator and its associated counter (MCC/RTC) are
running to keep a wake-up time base. All other peripherals are not clocked except those
which get their clock supply from another clock generator (such as external or auxiliary
oscillator).

The safeguard against staying locked in Active Halt mode is provided by the oscillator
interrupt.

Note: As soon as the interrupt capability of one of the oscillators is selected (MCCSR.OIE bit set),

entering Active Halt mode while the Watchdog is active does not generate a reset.



This means that the device cannot spend more than a defined delay in this power saving
mode.

Caution: When exiting Active Halt mode following an interrupt, OIE bit of MCCSR register must not be

cleared before t
on option byte). Otherwise, the ST7 enters Halt mode for the remaining t

after the interrupt occurs (t

DELAY

= 256 or 4096 t

DELAY

delay depending

CPU

DELAY

period.

Figure 24. Active Halt timing overview

1. This delay occurs only if the MCU exits Active Halt mode by means of a reset.

54/198 Doc ID13466 Rev 4

ST72324B-Auto Power saving modes

Halt instruction

Reset

Interrupt

(2)

Y

N

N

Y

CPU

Oscillator
Peripherals

(1)

I[1:0] bits

on
off

10

off

Fetch reset vector

or service interrupt

CPU

Oscillator
Peripherals

I[1:0] bits

on
off

XX

(3)

on

CPU

Oscillator
Peripherals

I[1:0] bits

on
on

XX

(3)

on

256 or 4096 CPU clock

cycle delay

(MCCSR.OIE = 1)

Figure 25. Active Halt mode flowchart

1. Peripheral clocked with an external clock source can still be active.

2. Only the MCC/RTC interrupt and some specific interrupts can exit the MCU from Active Halt mode (such as
external interrupt). Refer to Table 25: Interrupt mapping on page 51 for more details.

3. Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the CC register are
set to the current software priority level of the interrupt routine and restored when the CC register is
popped.

8.4.2 Halt mode

The Halt mode is the lowest power consumption mode of the MCU. It is entered by
executing the ‘HALT’ instruction when the OIE bit of the Main Clock Controller Status
register (MCCSR) is cleared (see

and beeper (MCC/RTC) on page 69for more details on the MCCSR register).

The MCU can exit Halt mode on reception of either a specific interrupt (see Ta ble 25:

Interrupt mapping) or a reset. When exiting Halt mode by means of a reset or an interrupt,

the oscillator is immediately turned on and the 256 or 4096 CPU cycle delay is used to
stabilize the oscillator. After the start up delay, the CPU resumes operation by servicing the
interrupt or by fetching the reset vector which woke it up (see

When entering Halt mode, the I[1:0] bits in the CC register are forced to ‘10b’ to enable
interrupts. Therefore, if an interrupt is pending, the MCU wakes up immediately.

In Halt mode, the main oscillator is turned off causing all internal processing to be stopped,
including the operation of the on-chip peripherals. All peripherals are not clocked except the
ones which get their clock supply from another clock generator (such as an external or
auxiliary oscillator).

The compatibility of Watchdog operation with Halt mode is configured by the “WDGHALT”
option bit of the option byte. The HALT instruction when executed while the Watchdog
system is enabled, can generate a Watchdog reset (see
details.

Section 10.2: Main clock controller with real-time clock

Figure 27).

Section 14.1 on page 179) for more

Doc ID13466 Rev 4 55/198

Power saving modes ST72324B-Auto

HaltRun Run

256 or 4096 CPU

cycle delay

Reset

or

interrupt

Halt

instruction

Fetch

vector

[MCCSR.OIE = 0]

Halt instruction

Reset

Interrupt

(3)

Y

N

N

Y

CPU

Oscillator
Peripherals

(2)

I[1:0] bits

off
off

10

off

Fetch reset vector

or service interrupt

CPU

Oscillator
Peripherals

I[1:0] bits

on
off

XX

(4)

on

CPU

Oscillator
Peripherals

I[1:0] bits

on
on

XX

(4)

on

256 or 4096 CPU clock

delay

Watchdog

Enable

Disable

WDGHALT

(1)

0

Watchdog

reset

1

(MCCSR.OIE = 0)

cycle

Figure 26. HALT timing overview

Figure 27. Halt mode flowchart

1. WDGHALT is an option bit. See Section 14.1 on page 179 for more details.

2. Peripheral clocked with an external clock source can still be active.

3. Only some specific interrupts can exit the MCU from Halt mode (such as external interrupt). Refer to

Table 25: Interrupt mappingfor more details.

4. Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the CC register are
set to the current software priority level of the interrupt routine and recovered when the CC register is
popped.

56/198 Doc ID13466 Rev 4

ST72324B-Auto Power saving modes

Halt mode recommendations

● Make sure that an external event is available to wake up the microcontroller from Halt

mode.

● When using an external interrupt to wake up the microcontroller, reinitialize the

corresponding I/O as “Input Pull-up with Interrupt” before executing the HALT
instruction. The main reason for this is that the I/O may be wrongly configured due to
external interference or by an unforeseen logical condition.

● For the same reason, reinitialize the sensitivity level of each external interrupt as a

precautionary measure.

● The opcode for the HALT instruction is 0x8E. To avoid an unexpected HALT instruction

due to a program counter failure, it is advised to clear all occurrences of the data value
0x8E from memory. For example, avoid defining a constant in ROM with the value
0x8E.

● As the HALT instruction clears the interrupt mask in the CC register to allow interrupts,

the user may choose to clear all pending interrupt bits before executing the HALT
instruction. This avoids entering other peripheral interrupt routines after executing the
external interrupt routine corresponding to the wake-up event (reset or external
interrupt).

Doc ID13466 Rev 4 57/198

I/O ports ST72324B-Auto

9 I/O ports

9.1 Introduction

The I/O ports offer different functional modes:

● transfer of data through digital inputs and outputs,

and for specific pins:

● external interrupt generation,

● alternate signal input/output for the on-chip peripherals.

An I/O port contains up to 8 pins. Each pin can be programmed independently as digital
input (with or without interrupt generation) or digital output.

9.2 Functional description

Each port has two main registers:

● Data Register (DR)

● Data Direction Register (DDR)

and one optional register:

● Option Register (OR)

Each I/O pin may be programmed using the corresponding register bits in the DDR and OR
registers: bit X corresponding to pin X of the port. The same correspondence is used for the
DR register.

The following description takes into account the OR register, (for specific ports which do not
provide this register refer to
I/O block diagram is shown in Figure 28.

Section 9.3: I/O port implementation on page 62). The generic

9.2.1 Input modes

The input configuration is selected by clearing the corresponding DDR register bit.

In this case, reading the DR register returns the digital value applied to the external I/O pin.

Different input modes can be selected by software through the OR register.

Note: 1 Writing the DR register modifies the latch value but does not affect the pin status.

2 When switching from input to output mode, the DR register has to be written first to drive the

correct level on the pin as soon as the port is configured as an output.

3 Do not use read/modify/write instructions (BSET or BRES) to modify the DR register as this

might corrupt the DR content for I/Os configured as input.

58/198 Doc ID13466 Rev 4

ST72324B-Auto I/O ports

External interrupt function

When an I/O is configured as ‘Input with Interrupt’, an event on this I/O can generate an
external interrupt request to the CPU.

Each pin can independently generate an interrupt request. The interrupt sensitivity is
independently programmable using the sensitivity bits in the EICR register.

Each external interrupt vector is linked to a dedicated group of I/O port pins (see pinout
description and interrupt section). If several input pins are selected simultaneously as
interrupt sources, these are first detected according to the sensitivity bits in the EICR
register and then logically ORed.

The external interrupts are hardware interrupts, which means that the request latch (not
accessible directly by the application) is automatically cleared when the corresponding
interrupt vector is fetched. To clear an unwanted pending interrupt by software, the
sensitivity bits in the EICR register must be modified.

9.2.2 Output modes

The output configuration is selected by setting the corresponding DDR register bit. In this
case, writing the DR register applies this digital value to the I/O pin through the latch. Then
reading the DR register returns the previously stored value.

Two different output modes can be selected by software through the OR register: Output
push-pull and open-drain.

Table 27. DR register value and output pin status

DR Push-pull Open-drain

0V

1V

SS

DD

V

SS

Floating

9.2.3 Alternate functions

When an on-chip peripheral is configured to use a pin, the alternate function is automatically
selected. This alternate function takes priority over the standard I/O programming.

When the signal is coming from an on-chip peripheral, the I/O pin is automatically
configured in output mode (push-pull or open drain according to the peripheral).

When the signal is going to an on-chip peripheral, the I/O pin must be configured in input
mode. In this case, the pin state is also digitally readable by addressing the DR register.

Note: Input pull-up configuration can cause unexpected value at the input of the alternate

peripheral input. When an on-chip peripheral use a pin as input and output, this pin has to
be configured in input floating mode.

Doc ID13466 Rev 4 59/198

I/O ports ST72324B-Auto

DR

DDR

OR

Data bus

Pad

V

DD

Alternate
enable

Alternate
output

1

0

OR SEL

DDR SEL

DR SEL

Pull-up
condition

P-buffer
(see table 24 below)

N-buffer

Pull-up
(see table 24 below)

1

0

Analog

input

If implemented

V

DD

Diodes
(see table 24 below)

CMOS

Register
access

External
interrupt

source (ei

x

)

Alternate
input

Schmitt
trigger

Figure 28. I/O port general block diagram

Table 28. I/O port mode options

Configuration mode Pull-up P-buffer

Floating with/without Interrupt Off

Input

Pull-up with/without Interrupt On

Push-pull

1. The diode to VDD is not implemented in the true open drain pads.

2. A local protection between the pad and VSS is implemented to protect the device against positive stress.

3. Off = implemented not activated.

4. On = implemented and activated.

5. NI = not implemented

60/198 Doc ID13466 Rev 4

Output

Open drain (logic level) Off

True open drain NI NI NI

(3)

(4)

Off

Off

On

to V

On

DD

(5)

Diodes

(1)

to V

On

SS

(2)

ST72324B-Auto I/O ports

V

DD

R

PU

W

R

true open drain

Not implemented in

I/O ports

Pad

Pull-up
condition

DR

register

DR register access

Data bus

Alternate input

External interrupt
source (ei

x

)

Interrupt

condition

Analog input

Pad

R

PU

R/W

V

DD

DR register access

DR

register

true open drain

Not implemented in

I/O ports

Data bus

Alternate

output

Alternate

enable

Pad

R

PU

DR

R/W

V

DD

true open drain

Not implemented in

I/O ports

DR register access

register

Data bus

Alternate

enable

Alternate

output

Table 29. I/O port configurations

Hardware configuration

(1)

Input

(2)

Open-drain output

(2)

PUSH-pull output

1. When the I/O port is in input configuration and the associated alternate function is enabled as an output,
reading the DR register will read the alternate function output status.

2. When the I/O port is in output configuration and the associated alternate function is enabled as an input,
the alternate function reads the pin status given by the DR register content.

Caution: The alternate function must not be activated as long as the pin is configured as input with

interrupt, in order to avoid generating spurious interrupts.

Doc ID13466 Rev 4 61/198

I/O ports ST72324B-Auto

01

floating/pull-up

interrupt

Input

00

floating

(reset state)

Input

10

open-drain

Output

11

push-pull

Output

XX

= DDR, OR

Analog alternate function

When the pin is used as an ADC input, the I/O must be configured as floating input. The
analog multiplexer (controlled by the ADC registers) switches the analog voltage present on
the selected pin to the common analog rail which is connected to the ADC input.

It is recommended not to change the voltage level or loading on any port pin while
conversion is in progress. Furthermore it is recommended not to have clocking pins located
close to a selected analog pin.

Warning: The analog input voltage level must be within the limits

stated in the absolute maximum ratings.

9.3 I/O port implementation

The hardware implementation on each I/O port depends on the settings in the DDR and OR
registers and specific feature of the I/O port such as ADC Input or true open drain.

Switching these I/O ports from one state to another should be done in a sequence that
prevents unwanted side effects. Recommended safe transitions are illustrated in
Other transitions are potentially risky and should be avoided, since they are likely to present
unwanted side-effects such as spurious interrupt generation.

Figure 29.

Figure 29. Interrupt I/O port state transitions

9.4 Low power modes

Table 30. Effect of low power modes on I/O ports

Mode Description

Wait No effect on I/O ports. External interrupts cause the device to exit from Wait mode.

Halt No effect on I/O ports. External interrupts cause the device to exit from Halt mode.

9.5 Interrupts

The external interrupt event generates an interrupt if the corresponding configuration is
selected with DDR and OR registers and the interrupt mask in the CC register is not active
(RIM instruction).

62/198 Doc ID13466 Rev 4

ST72324B-Auto I/O ports

Table 31. I/O port interrupt control/wake-up capability

Interrupt event Event flag Enable Control bit Exit from WAIT Exit from HALT

External interrupt on selected
external event

9.5.1 I/O port implementation

The I/O port register configurations are summarized Tab l e 32.

Table 32. Port configuration

Port Pin name

OR = 0 OR = 1 OR = 0 OR = 1

PA7:6 Floating True open-drain (high sink)

Por t A

Por t B

Port C PC7:0 Floating Pull-up Open drain Push-pull

Port D PD5:0 Floating Pull-up Open drain Push-pull

Port E PE1:0 Floating Pull-up Open drain Push-pull

Por t F

PA5:4 Floating Pull-up Open drain Push-pull

PA3 Floating Floating interrupt Open drain Push-pull

PB3 Floating Floating interrupt Open drain Push-pull

PB4, PB2:0 Floating Pull-up Open drain Push-pull

PF7:6, 4 Floating Pull-up Open drain Push-pull

PF2:0 Floating Pull-up Open drain Push-pull

- DDRx, ORx Yes Yes

Input (DDR = 0) Output (DDR = 1)

Table 33. I/O port register map and reset values

Address (Hex.) Register label 7 6 5 43210

Reset value of all I/O port registers00000000

0000h PADR

MSB LSB0001h PADDR

0002h PAOR

0003h PBDR

MSB LSB0004h PBDDR

0005h PBOR

0006h PCDR

MSB LSB0007h PCDDR

0008h PCOR

0009h PDDR

MSB LSB000Ah PDDDR

000Bh PDOR

Doc ID13466 Rev 4 63/198

I/O ports ST72324B-Auto

Table 33. I/O port register map and reset values (continued)

Address (Hex.) Register label 7 6 5 43210

000Ch PEDR

MSB LSB000Dh PEDDR

000Eh PEOR

000Fh PFDR

MSB LSB0010h PFDDR

0011h PFOR

64/198 Doc ID13466 Rev 4

ST72324B-Auto On-chip peripherals

10 On-chip peripherals

10.1 Watchdog timer (WDG)

10.1.1 Introduction

The Watchdog timer is used to detect the occurrence of a software fault, usually generated
by external interference or by unforeseen logical conditions, which causes the application
program to abandon its normal sequence. The Watchdog circuit generates an MCU reset on
expiry of a programmed time period, unless the program refreshes the counter’s contents
before the T6 bit becomes cleared.

10.1.2 Main features

● Programmable free-running downcounter

● Programmable reset

● Reset (if Watchdog activated) when the T6 bit reaches zero

● Optional reset on HALT instruction (configurable by option byte)

● Hardware Watchdog selectable by option byte

10.1.3 Functional description

The counter value stored in the Watchdog Control register (WDGCR bits T[6:0]), is
decremented every 16384 f
be programmed by the user in 64 increments.

If the watchdog is activated (the WDGA bit is set) and when the 7-bit timer (bits T[6:0]) rolls
over from 40h to 3Fh (T6 becomes cleared), it initiates a reset cycle pulling low the reset pin
for typically 30µs.

The application program must write in the WDGCR register at regular intervals during
normal operation to prevent an MCU reset. This downcounter is free-running: it counts down
even if the watchdog is disabled. The value to be stored in the WDGCR register must be
between FFh and C0h:

● The WDGA bit is set (Watchdog enabled)

● The T6 bit is set to prevent generating an immediate reset

● The T[5:0] bits contain the number of increments which represents the time delay

before the Watchdog produces a reset (see Figure 31: Approximate timeout duration).
The timing varies between a minimum and a maximum value due to the unknown
status of the prescaler when writing to the WDGCR register (see Figure 32).

Following a reset, the watchdog is disabled. Once activated it cannot be disabled, except by
a reset.

The T6 bit can be used to generate a software reset (the WDGA bit is set and the T6 bit is
cleared).

cycles (approx.), and the length of the timeout period can

OSC2

If the Watchdog is activated, the HALT instruction generates a reset.

Doc ID13466 Rev 4 65/198

On-chip peripherals ST72324B-Auto

Reset

WDGA

6-bit downcounter (CNT)

f

OSC2

T6

T0

WDG prescaler

Watchdog Control register (WDGCR)

div 4

T1

T2

T3

T4

T5

12-bit MCC

RTC counter

LSB

Div 64

0

5

6

11

MCC/RTC

TB[1:0] bits
(MCCSR
register)

MSB

CNT value (Hex.)

Watchdog timeout (ms) @ 8 MHz. f

OSC2

3F

00

38

128

1.5 65

30

28

20

18

10

08

503418 82 98 114

Figure 30. Watchdog block diagram

10.1.4 How to program the Watchdog timeout

Figure 31 shows the linear relationship between the 6-bit value to be loaded in the

Watchdog Counter (CNT) and the resulting timeout duration in milliseconds. This can be
used for a quick calculation without taking the timing variations into account. If more
precision is needed, use the formulae in

Figure 32.

Caution: When writing to the WDGCR register, always write 1 in the T6 bit to avoid generating an

immediate reset.

Figure 31. Approximate timeout duration

66/198 Doc ID13466 Rev 4

ST72324B-Auto On-chip peripherals

WHERE:

t

min0

= (LSB + 128) x 64 x t

OSC2

t

max0

= 16384 x t

OSC2

t

OSC2

= 125ns if f

OSC2

= 8 MHz

CNT = value of T[5:0] bits in the WDGCR register (6 bits)

MSB and LSB are values from the table below depending on the timebase selected by the TB[1:0] bits in the MCCSR
register

To calculate the minimum Watchdog timeout (t

min

):

IF THEN

ELSE

To calculate the maximum Watchdog timeout (t

max

):

IF THEN

ELSE

NOTE: In the above formulae, division results must be rounded down to the next integer value.

EXAMPLE: With 2ms timeout selected in MCCSR register

TB1 bit

(MCCSR reg.)

TB0 bit

(MCCSR reg.)

Selected MCCSR timebase MSB LSB

0 0 2ms 4 59

0 1 4ms 8 53

1 0 10ms 20 35

1 1 25ms 49 54

Value of T[5:0] bits in WDGCR register

(Hex.)

Min. Watchdog timeout (ms)

t

min

Max. Watchdog timeout (ms)

t

max

00 1.496 2.048

3F 128 128.552

CNT

MSB

4

-------------

<

t

mintmin0

16384 CN T t

osc2

+=

t

mintmin0

16384 CNT

4CNT

MSB

-----------------

–





 192 LSB+64

4CNT

MSB

-----------------

+ t

osc2

+=

CNT

MSB

4

-------------



t

maxtmax0

16384 CN T t

osc2

+=

t

maxtmax0

16384 CNT

4CNT

MSB

-----------------

–





 192 L SB+64

4CNT

MSB

-----------------

+ t

osc2

+=

Figure 32. Exact timeout duration (t

min

and t

max

)

Doc ID13466 Rev 4 67/198

On-chip peripherals ST72324B-Auto

10.1.5 Low power modes

Table 34. Effect of lower power modes on Watchdog

Mode Description

Slow

No effect on Watchdog

Wait

OIE bit in

MCCSR register

00

Halt

0 1 A reset is generated.

1x

WDGHALT bit in

option byte

10.1.6 Hardware Watchdog option

No Watchdog reset is generated. The MCU enters
Halt mode. The Watchdog counter is decremented
once and then stops counting and is no longer able to
generate a watchdog reset until the MCU receives an
external interrupt or a reset.
If an external interrupt is received, the Watchdog
restarts counting after 256 or 4096 CPU clocks. If a
reset is generated, the Watchdog is disabled (reset
state) unless Hardware Watchdog is selected by
option byte. For application recommendations, see

Section 10.1.7 below.

No reset is generated. The MCU enters Active Halt
mode. The Watchdog counter is not decremented. It
stop counting. When the MCU receives an oscillator
interrupt or external interrupt, the Watchdog restarts
counting immediately. When the MCU receives a
reset the Watchdog restarts counting after 256 or
4096 CPU clocks.

If Hardware Watchdog is selected by option byte, the watchdog is always active and the
WDGA bit in the WDGCR is not used. Refer to the option byte description in

Flash devices.

10.1.7 Using Halt mode with the WDG (WDGHALT option)

The following recommendation applies if Halt mode is used when the watchdog is enabled:
Before executing the HALT instruction, refresh the WDG counter to avoid an unexpected
WDG reset immediately after waking up the microcontroller.

10.1.8 Interrupts

None.

68/198 Doc ID13466 Rev 4

Section 14.1:

ST72324B-Auto On-chip peripherals

10.1.9 Control register (WDGCR)

WDGCR Reset value: 0111 1111 (7F h)

76543210

WDGA T[6:0]

R/W R/W

Table 35. WDGCR register description

Bit Name Function

Activation bit

This bit is set by software and only cleared by hardware after a reset. When

7WDGA

6:0 T[6:0]

WDGA = 1, the watchdog can generate a reset.
0: Watchdog disabled
1: Watchdog enabled

Note: This bit is not used if the hardware watchdog option is enabled by option byte.

7-bit counter (MSB to LSB)

These bits contain the value of the Watchdog counter, which is decremented every
16384 f
(T6 is cleared).

cycles (approx.). A reset is produced when it rolls over from 40h to 3Fh

OSC2

10.2

10.2.1

Table 36. Watchdog timer register map and reset values

Address (Hex.)Register label76543210

002Ah

WDGCR
reset value

WDGA0T6

T5

1

1

T4

T3

1

1

T2

T1

1

T0

1

1

Main clock controller with real-time clock and beeper (MCC/RTC)

The main clock controller consists of three different functions:

●

a programmable CPU clock prescaler

●

a clock-out signal to supply external devices

●

a real-time clock timer with interrupt capability

Each function can be used independently and simultaneously.

Programmable CPU clock prescaler

The programmable CPU clock prescaler supplies the clock for the ST7 CPU and its internal
peripherals. It manages Slow power saving mode (see
for more details).

The prescaler selects the f

main clock frequency and is controlled by three bits in the

CPU

MCCSR register: CP[1:0] and SMS.

Section 8.2: Slow mode on page 52

Doc ID13466 Rev 4 69/198

On-chip peripherals ST72324B-Auto

Div 2, 4, 8, 16

MCC/RTC interrupt

SMSCP1 CP0 TB1 TB0 OIE OIF

CPU clock

MCCSR

12-bit MCC RTC

counter

to CPU and
peripherals

f

OSC2

f

CPU

MCO

MCO

BC1 BC0

MCCBCR

Beep

selection

Beep signal

1

0

To

Watchdog

timer

Div 64

10.2.2

Caution:

10.2.3

10.2.4

Clock-out capability

The clock-out capability is an alternate function of an I/O port pin that outputs the f
to drive external devices. It is controlled by the MCO bit in the MCCSR register.

When selected, the clock out pin suspends the clock during Active Halt mode.

CPU

clock

Real-time clock (RTC) timer

The counter of the real-time clock timer allows an interrupt to be generated based on an
accurate real-time clock. Four different time bases depending directly on f

are available.

OSC2

The whole functionality is controlled by four bits of the MCCSR register: TB[1:0], OIE and
OIF.

When the RTC interrupt is enabled (OIE bit set), the ST7 enters Active Halt mode when the
HALT instruction is executed. See

Section 8.4: Active Halt and Halt modes on page 54for

more details.

Beeper

The beep function is controlled by the MCCBCR register. It can output three selectable
frequencies on the Beep pin (I/O port alternate function).

Figure 33.

Main clock controller (MCC/RTC) block diagram

70/198 Doc ID13466 Rev 4

ST72324B-Auto On-chip peripherals

10.2.5

10.2.6

Low power modes

Table 37. Effect of low power modes on MCC/RTC

Mode Description

Wait

Active Halt

Halt

No effect on MCC/RTC peripheral. MCC/RTC interrupt causes the device to exit
from Wait mode.

No effect on MCC/RTC counter (OIE bit is set), the registers are frozen.
MCC/RTC interrupt causes the device to exit from Active Halt mode.

MCC/RTC counter and registers are frozen. MCC/RTC operation resumes when
the MCU is woken up by an interrupt with Exit from Halt capability.

Interrupts

The MCC/RTC interrupt event generates an interrupt if the OIE bit of the MCCSR register is
set and the interrupt mask in the CC register is not active (RIM instruction).

Table 38. MCC/RTC interrupt control/wake-up capability

Interrupt event Event flag Enable control bit Exit from WAIT Exit from HALT

Time base overflow event OIF OIE Yes No

1. The MCC/RTC interrupt wakes up the MCU from Active Halt mode, not from Halt mode.

(1)

10.2.7 MCC registers

MCC control/status register (MCCSR)

)

MCCSR Reset value: 0000 0000 (00h)

76543210

MCO CP[1:0] SMS

R/W R/W R/W R/W R/W R/W

Table 39. MCCSR register description

Bit Name Function

Main Clock Out selection

This bit enables the MCO alternate function on the PF0 I/O port. It is set and
cleared by software.

7MCO

0: MCO alternate function disabled (I/O pin free for general-purpose I/O).
1: MCO alternate function enabled (f

Note: To reduce power consumption, the MCO function is not active in Active Halt
mode.

TB[1:0]

on I/O port).

CPU

OIE OIF

Doc ID13466 Rev 4 71/198

On-chip peripherals ST72324B-Auto

Table 39. MCCSR register description (continued)

Bit Name Function

CPU Clock Prescaler

These bits select the CPU clock prescaler which is applied in different slow modes.
Their action is conditioned by the setting of the SMS bit. These two bits are set and

6:5 CP[1:0]

4SMS

3:2

TB[1:0]

cleared by software:
00: f
01: f
10: f
11: f

in Slow mode = f

CPU

in Slow mode = f

CPU

in Slow mode = f

CPU

in Slow mode = f

CPU

OSC2
OSC2
OSC2
OSC2

/2
/4
/8
/16

Slow Mode Select

This bit is set and cleared by software.
0: Normal mode. f
1: Slow mode. f

= f

CPU

is given by CP1, CP0.

CPU

OSC2

.

See Section 8.2: Slow mode and Section 10.2: Main clock controller with real-time

clock and beeper (MCC/RTC) for more details.

Time Base control

These bits select the programmable divider time base. They are set and cleared by
software (see Tabl e 4 0 ). A modification of the time base is taken into account at the
end of the current period (previously set) to avoid an unwanted time shift. This
allows to use this time base as a real-time clock.

Oscillator interrupt Enable

This bit set and cleared by software.

1OIE

0: Oscillator interrupt disabled
1: Oscillator interrupt enabled
This interrupt can be used to exit from Active Halt mode. When this bit is set, calling
the ST7 software HALT instruction enters the Active Halt power saving mode

Oscillator interrupt Flag

This bit is set by hardware and cleared by software reading the MCCSR register. It
indicates when set that the main oscillator has reached the selected elapsed time

0OIF

(TB1:0).
0: Timeout not reached
1: Timeout reached
Caution: The BRES and BSET instructions must not be used on the MCCSR
register to avoid unintentionally clearing the OIF bit.

.

Table 40. Time base selection

Counter prescaler

16000 4ms 2ms 0 0

32000 8ms 4ms 0 1

80000 20ms 10ms 1 0

200000 50ms 25ms 1 1

= 4 MHz f

f

OSC2

Time base

OSC2

.

TB1 TB0

= 8 MHz

72/198 Doc ID13466 Rev 4

ST72324B-Auto On-chip peripherals

MCC beep control register (MCCBCR)

MCCBCR Reset value: 0000 0000 (00h)

76543210

Reserved BC[1:0]

-R/W

Table 41. MCCBCR register description

Bit Name Function

7:2 - Reserved, must be kept cleared

Beep Control

1:0 BC[1:0]

Table 42. Beep frequency selection

These 2 bits select the PF1 pin beep capability (see Ta ble 4 2 ). The beep output
signal is available in Active Halt mode but has to be disabled to reduce the
consumption.

BC1 BC0 Beep mode with f

OSC2

00 Off

0 1 ~2 kHz

1 0 ~1 kHz

11 ~500 Hz

Table 43. Main clock controller register map and reset values

Address

(Hex.)

002Bh

002Ch

002Dh

Register label7654321 0

SICSR
Reset value 0

MCCSR

MCO0CP10CP00SMS0TB1

Reset value

AVD IE0AVD F0LVDRF

x000

0

MCCBCR
Reset value000000

= 8 MHz

Output

Beep signal

~50% duty cycle

TB00OIE

0

BC1

0

WDGRF

x

OIF

0

BC0

0

Doc ID13466 Rev 4 73/198

On-chip peripherals ST72324B-Auto

10.3 16-bit timer

10.3.1 Introduction

The timer consists of a 16-bit free-running counter driven by a programmable prescaler.

It may be used for a variety of purposes, including pulse length measurement of up to two
input signals (input capture) or generation of up to two output waveforms (output compare
and PWM).

Pulse lengths and waveform periods can be modulated from a few microseconds to several
milliseconds using the timer prescaler and the CPU clock prescaler.

Some ST7 devices have two on-chip 16-bit timers. They are completely independent, and
do not share any resources. They are synchronized after a MCU reset as long as the timer
clock frequencies are not modified.

This description covers one or two 16-bit timers. In ST7 devices with two timers, register
names are prefixed with TA (Timer A) or TB (Timer B).

10.3.2 Main features

● Programmable prescaler: f

● Overflow status flag and maskable interrupt

● External clock input (must be at least four times slower than the CPU clock speed) with

divided by 2, 4 or 8

CPU

the choice of active edge

● 1 or 2 output compare functions each with:

– 2 dedicated 16-bit registers
– 2 dedicated programmable signals
– 2 dedicated status flags
– 1 dedicated maskable interrupt

● 1 or 2 input capture functions each with:

– 2 dedicated 16-bit registers
– 2 dedicated active edge selection signals
– 2 dedicated status flags
– 1 dedicated maskable interrupt

● Pulse width modulation mode (PWM)

● One pulse mode

● Reduced power mode

● 5 alternate functions on I/O ports (ICAP1, ICAP2, OCMP1, OCMP2, EXTCLK)

(c)

The timer block diagram is shown in Figure 34.

c. Some timer pins may not be available (not bonded) in some ST7 devices. Refer to Section 2: Pin description.

When reading an input signal on a non-bonded pin, the value will always be ‘1’.

74/198 Doc ID13466 Rev 4

ST72324B-Auto On-chip peripherals

10.3.3 Functional description

Counter

The main block of the programmable timer is a 16-bit free running upcounter and its
associated 16-bit registers. The 16-bit registers are made up of two 8-bit registers called
high and low.

● Counter Register (CR)

– Counter High Register (CHR) is the most significant byte (MSB)
– Counter Low Register (CLR) is the least significant byte (LSB)

● Alternate Counter Register (ACR)

– Alternate Counter High Register (ACHR) is the most significant byte (MSB)
– Alternate Counter Low Register (ACLR) is the least significant byte (LSB)

These two read-only 16-bit registers contain the same value but with the difference that
reading the ACLR register does not clear the TOF bit (timer overflow flag), located in the
Status register (SR) (see note at the end of paragraph entitled

Writing in the CLR register or ACLR register resets the free running counter to the FFFCh
value. Both counters have a reset value of FFFCh (this is the only value which is reloaded in
the 16-bit timer). The reset value of both counters is also FFFCh in one pulse mode and
PWM mode.

16-bit read sequence).

The timer clock depends on the clock control bits of the CR2 register, as illustrated in

Ta bl e 50. The value in the counter register repeats every 131072, 262144 or 524288 CPU

clock cycles depending on the CC[1:0] bits. The timer frequency can be f
f

/8 or an external frequency.

CPU

CPU

/2, f

CPU

/4,

Doc ID13466 Rev 4 75/198

On-chip peripherals ST72324B-Auto

MCU-peripheral interface

Counter

Alternate

Output

Compare

register

Output Compare

Edge Detect

Overflow

Detect

circuit

1/2
1/4
1/8

8-bit

buffer

ST7 internal bus

Latch 1

OCMP1

ICAP1

EXTCLK

fCPU

Timer interrupt

ICF2ICF1 TIMD 0 0OCF2OCF1 TOF

PWMOC1E

EXEDG

IEDG2CC0CC1

OC2E

OPM

FOLV2ICIE OLVL1IEDG1OLVL2FOLV1OCIE TOIE

ICAP2

Latch 2

OCMP2

8

8

8 low

16

8 high

16 16

16

16

(Control register 1) CR1

(Control register 2) CR2

(Control/Status register) CSR

6

16

8 8 8

88 8

high

low

high

high

high

low

low

low

EXEDG

Timer internal bus

circuit 1

Edge Detect

circuit 2

circuit

1

Output

Compare

register

2

Input

Capture

register

1

Input

Capture

register

2

CC[1:0]

pin

pin

pin

pin

pin

register

(See note 1)

Counter

register

Figure 34. Timer block diagram

1. If IC, OC and TO interrupt requests have separate vectors then the last OR is not present (see Table 25:

Interrupt mapping on page 51).

76/198 Doc ID13466 Rev 4

ST72324B-Auto On-chip peripherals

Read

At t0

Read

Returns the buffered

LSB value at t0

At t0 +t

Other

instructions

Beginning of the sequence

Sequence completed

LSB is buffered

LSB

MSB

16-bit read sequence

The 16-bit read sequence (from either the Counter register or the Alternate Counter
register) is illustrated in the following

Figure 35. 16-bit read sequence

The user must first read the MSB, afterwhich the LSB value is automatically buffered.

This buffered value remains unchanged until the 16-bit read sequence is completed, even if
the user reads the MSB several times.

After a complete reading sequence, if only the CLR register or ACLR register are read, they
return the LSB of the count value at the time of the read.

Figure 35.

Whatever the timer mode used (input capture, output compare, one pulse mode or PWM
mode) an overflow occurs when the counter rolls over from FFFFh to 0000h then:

● The TOF bit of the SR register is set.

● A timer interrupt is generated if:

– TOIE bit of the CR1 register is set and
– I bit of the CC register is cleared.

If one of these conditions is false, the interrupt remains pending to be issued as soon as
they are both true.

Clearing the overflow interrupt request is done in two steps:

1. Reading the SR register while the TOF bit is set.

2. An access (read or write) to the CLR register.

Note: The TOF bit is not cleared by access to the ACLR register. The advantage of accessing the

ACLR register rather than the CLR register is that it allows simultaneous use of the overflow
function and reading the free running counter at random times (for example, to measure
elapsed time) without the risk of clearing the TOF bit erroneously.

The timer is not affected by Wait mode.

In Halt mode, the counter stops counting until the mode is exited. Counting then resumes
from the previous count (MCU awakened by an interrupt) or from the reset count (MCU
awakened by a reset).

Doc ID13466 Rev 4 77/198

On-chip peripherals ST72324B-Auto

CPU clock

FFFD FFFE FFFF 0000 0001 0002 0003

Internal reset

Timer clock

Counter register

Timer Overflow Flag (TOF)

FFFC FFFD 0000 0001

CPU clock

Internal reset

Timer clock

Counter register

Timer Overflow Flag (TOF)

CPU clock

Internal reset

Timer clock

Counter register

Timer Overflow Flag (TOF)

FFFC FFFD

0000

External clock

The external clock (where available) is selected if CC0 = 1 and CC1 = 1 in the CR2 register.

The status of the EXEDG bit in the CR2 register determines the type of level transition on
the external clock pin EXTCLK that will trigger the free running counter.

The counter is synchronized with the falling edge of the internal CPU clock.

A minimum of four falling edges of the CPU clock must occur between two consecutive
active edges of the external clock; thus the external clock frequency must be less than a
quarter of the CPU clock frequency.

Figure 36. Counter timing diagram, internal clock divided by 2

Figure 37. Counter timing diagram, internal clock divided by 4

Figure 38. Counter timing diagram, internal clock divided by 8

Note: The MCU is in reset state when the internal reset signal is high, when it is low the MCU is

running.

78/198 Doc ID13466 Rev 4

ST72324B-Auto On-chip peripherals

Input capture

In this section, the index, i, may be 1 or 2 because there are two input capture functions in
the 16-bit timer.

The two 16-bit input capture registers (IC1R/IC2R) are used to latch the value of the free
running counter after a transition is detected on the ICAPi pin (see Figure

Table 44. Input capture byte distribution

Register MS byte LS byte

ICiR ICiHR ICiLR

The ICiR registers are read-only registers.

The active transition is software programmable through the IEDGi bit of Control Registers
(CRi).

40).

Timing resolution is one count of the free running counter: (f

/CC[1:0]).

CPU

Procedure

To use the input capture function select the following in the CR2 register:

● Select the timer clock (CC[1:0]) (see Tabl e 5 0 ).

● Select the edge of the active transition on the ICAP2 pin with the IEDG2 bit (the ICAP2

pin must be configured as floating input or input with pull-up without interrupt if this
configuration is available).

Select the following in the CR1 register:

● Set the ICIE bit to generate an interrupt after an input capture coming from either the

ICAP1 pin or the ICAP2 pin

● Select the edge of the active transition on the ICAP1 pin with the IEDG1 bit (the

ICAP1pin must be configured as floating input or input with pull-up without interrupt if
this configuration is available).

When an input capture occurs:

● ICFi bit is set.

● The ICiR register contains the value of the free running counter on the active transition

on the ICAPi pin (see Figure 40).

● A timer interrupt is generated if the ICIE bit is set and the I bit is cleared in the CC

register. Otherwise, the interrupt remains pending until both conditions become true.

Clearing the Input Capture interrupt request (that is, clearing the ICFi bit) is done in two
steps:

1. Reading the SR register while the ICFi bit is set

2. An access (read or write) to the ICiLR register

Doc ID13466 Rev 4 79/198

On-chip peripherals ST72324B-Auto

ICIE

CC0CC1

16-bit free running

counter

IEDG1

(Control register 1) CR1

(Control register 2) CR2

ICF2

ICF1 000

(Status register) SR

IEDG2

ICAP1

ICAP2

Edge Detect

circuit 2

16-bit

IC1R register

Edge Detect

circuit 1

pin

pin

IC2R register

FF01

FF02

FF03

FF03

Timer clock

Counter register

ICAPi pin

ICAPi flag

ICAPi register

Note: The rising edge is the active edge.

Note: 1 After reading the ICiHR register, transfer of input capture data is inhibited and ICFi will never

be set until the ICiLR register is also read.

2 The ICiR register contains the free running counter value which corresponds to the most

recent input capture.

3 The two input capture functions can be used together even if the timer also uses the two

output compare functions.

4 In One pulse mode and PWM mode only Input Capture 2 can be used.

5 The alternate inputs (ICAP1 and ICAP2) are always directly connected to the timer. So any

transitions on these pins activates the input capture function.



Moreover if one of the ICAPi pins is configured as an input and the second one as an output,
an interrupt can be generated if the user toggles the output pin and if the ICIE bit is set.



This can be avoided if the input capture function i is disabled by reading the ICiHR (see
note 1).

6 The TOF bit can be used with interrupt generation in order to measure events that go

beyond the timer range (FFFFh).

Figure 39. Input capture block diagram

Figure 40. Input capture timing diagram

80/198 Doc ID13466 Rev 4

ST72324B-Auto On-chip peripherals

 OCiR =

t * f

CPU

PRESC

Output compare

In this section, the index, i, may be 1 or 2 because there are two output compare functions in
the 16-bit timer.

This function can be used to control an output waveform or indicate when a period of time
has elapsed.

When a match is found between the Output Compare register and the free running counter,
the output compare function:

● Assigns pins with a programmable value if the OCiE bit is set

● Sets a flag in the status register

● Generates an interrupt if enabled

Two 16-bit registers Output Compare register 1 (OC1R) and Output Compare register 2
(OC2R) contain the value to be compared to the counter register each timer clock cycle.

Table 45. Output compare byte distribution

Register MS byte LS byte

OCiR OCiHR OCiLR

These registers are readable and witable and are not affected by the timer hardware. A
reset event changes the OC

iR value to 8000h.

Timing resolution is one count of the free running counter: (f

/CC[1:0]).

CPU

Procedure

To use the Output Compare function, select the following in the CR2 register:

● Set the OCiE bit if an output is needed then the OCMPi pin is dedicated to the output

compare i signal.

● Select the timer clock (CC[1:0]) (see Tabl e 5 0 ).

And select the following in the CR1 register:

● Select the OLVLi bit to applied to the OCMPi pins after the match occurs.

● Set the OCIE bit to generate an interrupt if it is needed.

When a match is found between OCRi register and CR register:

● OCFi bit is set

● The OCMPi pin takes OLVLi bit value (OCMPi pin latch is forced low during reset)

● A timer interrupt is generated if the OCIE bit is set in the CR1 register and the I bit is

cleared in the CC register (CC).

The OCiR register value required for a specific timing application can be calculated using
the following formula:

Where:
t = Output compare period (in seconds)

f

= CPU clock frequency (in hertz)

CPU

PRESC = Timer prescaler factor (2, 4 or 8 depending on CC[1:0] bits; see Ta bl e 50)

Doc ID13466 Rev 4 81/198

On-chip peripherals ST72324B-Auto

 OCiR = t * f

EXT

If the timer clock is an external clock, the formula is:

Where:
t = Output compare period (in seconds)

f

= External timer clock frequency (in hertz)

EXT

Clearing the output compare interrupt request (that is, clearing the OCFi bit) is done by:

1. Reading the SR register while the OCFi bit is set.

2. An access (read or write) to the OCiLR register.

The following procedure is recommended to prevent the OCFi bit from being set between
the time it is read and the write to the OC

● Write to the OCiHR register (further compares are inhibited).

● Read the SR register (first step of the clearance of the OCFi bit, which may be already

iR register:

set).

● Write to the OCiLR register (enables the output compare function and clears the OCFi

bit).

Note: 1 After a processor write cycle to the OCiHR register, the output compare function is inhibited

until the OCiLR register is also written.

2 If the OCiE bit is not set, the OCMPi pin is a general I/O port and the OLVLi bit will not

appear when a match is found but an interrupt could be generated if the OCIE bit is set.

3 In both internal and external clock modes, OCFi and OCMPi are set while the counter value

equals the OCiR register value (see Figure 42 on page 83 for an example with f

Figure 43 on page 83 for an example with f

/4). This behavior is the same in OPM or

CPU

CPU

/2 and

PWM mode.

4 The output compare functions can be used both for generating external events on the

OCMPi pins even if the input capture mode is also used.

5 The value in the 16-bit OC

iR register and the OLVi bit should be changed after each

successful comparison in order to control an output waveform or establish a new elapsed
timeout.

Forced output compare capability

When the FOLVi bit is set by software, the OLVLi bit is copied to the OCMPi pin. The OLVi bit
has to be toggled in order to toggle the OCMPi pin when it is enabled (OCiE bit
OCFi bit is then not set by hardware, and thus no interrupt request is generated.

The FOLVLi bits have no effect in both one pulse mode and PWM mode.

82/198 Doc ID13466 Rev 4

= 1). The

ST72324B-Auto On-chip peripherals

Output compare

16-bit

circuit

OC1R register

16-bit free running counter

OC1E CC0CC1OC2E

OLVL1OLVL2OCIE

(Control Register 1) CR1

(Control Register 2) CR2

000OCF2OCF1

(Status register) SR

16-bit

16-bit

OCMP1

OCMP2

Latch

1

Latch

2

OC2R register

Pin

Pin

FOLV2FOLV1

Internal CPU clock

Timer clock

Counter register

Output Compare register i (OCRi)

Output Compare flag i (OCFi)

OCMPi pin (OLVLi =1)

2ED3

2ED0 2ED1 2ED2

2ED3

2ED42ECF

Internal CPU clock

Timer clock

Counter register

Output Compare register i (OCRi)

2ED3

2ED0 2ED1 2ED2

2ED3

2ED42ECF

Output Compare flag i (OCFi)

OCMPi pin (OLVLi =1)

Figure 41. Output compare block diagram

Figure 42. Output compare timing diagram, f

Figure 43. Output compare timing diagram, f

TIMER

TIMER

= f

= f

CPU

CPU

/2

/4

Doc ID13466 Rev 4 83/198

On-chip peripherals ST72324B-Auto

event occurs

counter =

OC1R

OCMP1 = OLVL1

When

When

on ICAP1

OCMP1 = OLVL2

Counter is reset

to FFFCh

ICF1 bit is set

ICR1 = Counter

One Pulse mode

One Pulse mode enables the generation of a pulse when an external event occurs. This
mode is selected via the OPM bit in the CR2 register.

The one pulse mode uses the Input Capture1 function and the Output Compare1 function.

Procedure

To use One Pulse mode:

1. Load the OC1R register with the value corresponding to the length of the pulse (see the

formula below).

2. Select the following in the CR1 register:

– Using the OLVL1 bit, select the level to be applied to the OCMP1 pin after the

pulse.

– Using the OLVL2 bit, select the level to be applied to the OCMP1 pin during the

pulse.

– Select the edge of the active transition on the ICAP1 pin with the IEDG1 bit (the

ICAP1 pin must be configured as floating input).

3. Select the following in the CR2 register:

– Set the OC1E bit, the OCMP1 pin is then dedicated to the Output Compare 1

function.
– Set the OPM bit.
– Select the timer clock CC[1:0] (see Ta b l e 5 0 ).

Figure 44. One pulse mode cycle

Then, on a valid event on the ICAP1 pin, the counter is initialized to FFFCh and OLVL2 bit is
loaded on the OCMP1 pin, the ICF1 bit is set and the value FFFDh is loaded in the IC1R
register.

Because the ICF1 bit is set when an active edge occurs, an interrupt can be generated if the
ICIE bit is set.

Clearing the Input Capture interrupt request (that is, clearing the ICFi bit) is done in two
steps:

1. Reading the SR register while the ICFi bit is set.

2. An access (read or write) to the ICiLR register.

84/198 Doc ID13466 Rev 4

ST72324B-Auto On-chip peripherals

OCiR value =

t

* fCPU
PRESC

- 5

OCiR = t * f

EXT

- 5

Counter

FFFC FFFD FFFE 2ED0 2ED1 2ED2

2ED3

FFFC FFFD

OLVL2

OLVL2OLVL1

ICAP1

OCMP1

Compare1

01F8

01F8

2ED3

IC1R

The OC1R register value required for a specific timing application can be calculated using
the following formula:

Where:
t = Pulse period (in seconds)

f

= CPU clock frequnency (in hertz)

CPU

PRESC = Timer prescaler factor (2, 4 or 8 depending on the CC[1:0] bits; see Ta ble 50)

If the timer clock is an external clock the formula is:

Where:
t = Pulse period (in seconds)

f

EXT

= External timer clock frequency (in hertz)

When the value of the counter is equal to the value of the contents of the OC1R register, the
OLVL1 bit is output on the OCMP1 pin (see

Figure 45).

Note: 1 The OCF1 bit cannot be set by hardware in one pulse mode but the OCF2 bit can generate

an Output Compare interrupt.

2 When the Pulse Width Modulation (PWM) and One Pulse Mode (OPM) bits are both set, the

PWM mode is the only active one.

3 If OLVL1 = OLVL2 a continuous signal will be seen on the OCMP1 pin.

4 The ICAP1 pin can not be used to perform input capture. The ICAP2 pin can be used to

perform input capture (ICF2 can be set and IC2R can be loaded) but the user must take
care that the counter is reset each time a valid edge occurs on the ICAP1 pin and ICF1 can
also generates interrupt if ICIE is set.

5 When one pulse mode is used OC1R is dedicated to this mode. Nevertheless OC2R and

OCF2 can be used to indicate a period of time has been elapsed but cannot generate an
output waveform because the level OLVL2 is dedicated to the one pulse mode.

Figure 45. One Pulse mode timing example

(1)

1. IEDG1 = 1, OC1R = 2ED0h, OLVL1 = 0, OLVL2 = 1

Doc ID13466 Rev 4 85/198

On-chip peripherals ST72324B-Auto

Counter

34E2

34E2 FFFC

OLVL2

OLVL2

OLVL1

OCMP1

compare2 compare1 compare2

FFFC FFFD FFFE

2ED0

2ED1

2ED2

Figure 46. Pulse width modulation mode timing example with two output compare

functions

1. OC1R = 2ED0h, OC2R = 34E2, OLVL1 = 0, OLVL2 = 1

2. On timers with only one Output Compare register, a fixed frequency PWM signal can be generated using
the output compare and the counter overflow to define the pulse length.

(1)(2)

Pulse Width Modulation mode

Pulse Width Modulation (PWM) mode enables the generation of a signal with a frequency
and pulse length determined by the value of the OC1R and OC2R registers.

Pulse Width Modulation mode uses the complete Output Compare 1 function plus the
OC2R register, and so this functionality can not be used when PWM mode is activated.

In PWM mode, double buffering is implemented on the output compare registers. Any new
values written in the OC1R and OC2R registers are taken into account only at the end of the
PWM period (OC2) to avoid spikes on the PWM output pin (OCMP1).

Procedure

To use Pulse Width Modulation mode:

1. Load the OC2R register with the value corresponding to the period of the signal using

the formula below.

2. Load the OC1R register with the value corresponding to the period of the pulse if

(OLVL1

3. Select the following in the CR1 register:

– Using the OLVL1 bit, select the level to be applied to the OCMP1 pin after a

– Using the OLVL2 bit, select the level to be applied to the OCMP1 pin after a

4. Select the following in the CR2 register:

– Set OC1E bit: the OCMP1 pin is then dedicated to the output compare 1 function.
– Set the PWM bit.
– Select the timer clock (CC[1:0]) (see Table 50).

= 0 and OLVL2 = 1) using the formula in the opposite column.

successful comparison with the OC1R register.

successful comparison with the OC2R register.

86/198 Doc ID13466 Rev 4

ST72324B-Auto On-chip peripherals

counter

OCMP1 = OLVL2

counter

= OC2R

OCMP1 = OLVL1

When

When

= OC1R

counter is reset

to FFFCh

ICF1 bit is set

OCiR value =

t

* fCPU

PRESC

- 5

OCiR = t * f

EXT

- 5

Figure 47. Pulse width modulation cycle

If OLVL1 = 1 and OLVL2 = 0, the length of the positive pulse is the difference between the
OC2R and OC1R registers.

If OLVL1 = OLVL2, a continuous signal will be seen on the OCMP1 pin.

The OC1R register value required for a specific timing application can be calculated using
the following formula:

Where:
t = Signal or pulse period (in seconds)

f

= CPU clock frequnency (in hertz)

CPU

PRESC = Timer prescaler factor (2, 4 or 8 depending on the CC[1:0] bits; see Ta ble 50)

If the timer clock is an external clock the formula is:

Where:
t = Signal or pulse period (in seconds)

f

EXT

= External timer clock frequency (in hertz)

The Output Compare 2 event causes the counter to be initialized to FFFCh (see Ta bl e 46).

Note: 1 After a write instruction to the OCiHR register, the output compare function is inhibited until

the OCiLR register is also written.

2 The OCF1 and OCF2 bits cannot be set by hardware in PWM mode therefore the Output

Compare interrupt is inhibited.

3 The ICF1 bit is set by hardware when the counter reaches the OC2R value and can produce

a timer interrupt if the ICIE bit is set and the I bit is cleared.

4 In PWM mode the ICAP1 pin can not be used to perform input capture because it is

disconnected to the timer. The ICAP2 pin can be used to perform input capture (ICF2 can be
set and IC2R can be loaded) but the user must take care that the counter is reset each
period and ICF1 can also generates interrupt if ICIE is set.

5 When the Pulse Width Modulation (PWM) and One Pulse Mode (OPM) bits are both set, the

PWM mode is the only active one.

Doc ID13466 Rev 4 87/198

On-chip peripherals ST72324B-Auto

10.3.4 Low power modes

Table 46. Effect of low power modes on 16-bit timer

Mode Description

Wait

Halt

10.3.5 Interrupts

Table 47. 16-bit timer interrupt control/wake-up capability

Interrupt event Event flag Enable Control bit Exit from WAIT Exit from HALT

Input Capture 1 event/counter
reset in PWM mode

Input Capture 2 event ICF2

Output Compare 1 event 
(not available in PWM mode)

Output Compare 2 event 
(not available in PWM mode)

Timer Overflow event TOF TOIE

No effect on 16-bit timer.
Timer interrupts cause the device to exit from Wait mode.

16-bit timer registers are frozen.
In Halt mode, the counter stops counting until Halt mode is exited. Counting resumes

from the previous count when the MCU is woken up by an interrupt with Exit from Halt
mode capability or from the counter reset value when the MCU is woken up by a reset.

If an input capture event occurs on the ICAPi pin, the input capture detection circuitry is
armed. Consequently, when the MCU is woken up by an interrupt with Exit from Halt
mode capability, the ICFi bit is set, and the counter value present when exiting from Halt
mode is captured into the ICiR register.

(1)

ICF1

ICIE

OCF1

Ye s N o

OCIE

OCF2

1. The 16-bit timer interrupt events are connected to the same interrupt vector (see Section 7: Interrupts).
These events generate an interrupt if the corresponding Enable Control bit is set and the interrupt mask in
the CC register is reset (RIM instruction).

88/198 Doc ID13466 Rev 4

ST72324B-Auto On-chip peripherals

10.3.6 Summary of timer modes

Table 48. Summary of timer modes

Timer resources

Mode

Input

Capture 1

Input

Capture 2

Output

Compare 1

Output

Compare 2

Input Capture
(1 and/or 2)

Ye s Ye s Ye s Ye s

Output Compare
(1 and/or 2)

One Pulse mode

Not recommended

No

PWM mode Not recommended

1. See note 4 in One Pulse mode on page 84.

2. See note 5 in One Pulse mode on page 84.

3. See note 4 in Pulse Width Modulation mode on page 86.

(1)

(3)

No

Partially

(2)

No

10.3.7 16-bit timer registers

Each timer is associated with three control and status registers, and with six pairs of data
registers (16-bit values) relating to the two input captures, the two output compares, the
counter and the alternate counter.

Control Register 1 (CR1)

CR1 Reset value: 0000 0000 (00h)

76543210

ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1

R/W R/W R/W R/W R/W R/W R/W R/W

M

Table 49. CR1 register description

Bit Name Function

Input Capture Interrupt Enable

7ICIE

6OCIE

0: Interrupt is inhibited.
1: A timer interrupt is generated whenever the ICF1 or ICF2 bit of the SR register is
set.

Output Compare Interrupt Enable

0: Interrupt is inhibited.
1: A timer interrupt is generated whenever the OCF1 or OCF2 bit of the SR register
is set.

5TOIE

Timer Overflow Interrupt Enable

0: Interrupt is inhibited.
1: A timer interrupt is enabled whenever the TOF bit of the SR register is set.

Doc ID13466 Rev 4 89/198

On-chip peripherals ST72324B-Auto

Table 49. CR1 register description (continued)

Bit Name Function

Forced Output compare 2

This bit is set and cleared by software.

4FOLV2

3FOLV1

2OLVL2

1IEDG1

0OLVL1

0: No effect on the OCMP2 pin.
1: Forces the OLVL2 bit to be copied to the OCMP2 pin, if the OC2E bit is set and
even if there is no successful comparison.

Forced Output compare 1

This bit is set and cleared by software.
0: No effect on the OCMP1 pin.
1: Forces OLVL1 to be copied to the OCMP1 pin, if the OC1E bit is set and even if
there is no successful comparison.

Output Level 2

This bit is copied to the OCMP2 pin whenever a successful comparison occurs with
the OC2R register and OCxE is set in the CR2 register. This value is copied to the
OCMP1 pin in One Pulse mode and Pulse Width modulation mode.

Input Edge 1

This bit determines which type of level transition on the ICAP1 pin will trigger the
capture.
0: A falling edge triggers the capture.
1: A rising edge triggers the capture.

Output Level 1

The OLVL1 bit is copied to the OCMP1 pin whenever a successful comparison
occurs with the OC1R register and the OC1E bit is set in the CR2 register.

Control Register 2 (CR2)

CR2 Reset value: 0000 0000 (00h)

76543210

OC1E OC2E OPM PWM CC[1:0] IEDG2 EXEDG

R/W R/W R/W R/W R/W R/W R/W

90/198 Doc ID13466 Rev 4

ST72324B-Auto On-chip peripherals

M

Table 50. CR2 register description

Bit Name Function

Output Compare 1 Pin Enable
This bit is used only to output the signal from the timer on the OCMP1 pin (OLV1 in

7OCIE

6OC2E

5OPM

4PWM

3:2 CC[1:0]

Output Compare mode, both OLV1 and OLV2 in PWM and One-Pulse mode).
Whatever the value of the OC1E bit, the Output Compare 1 function of the timer
remains active.
0: OCMP1 pin alternate function disabled (I/O pin free for general-purpose I/O).
1: OCMP1 pin alternate function enabled.

Output Compare 2 Pin Enable
This bit is used only to output the signal from the timer on the OCMP2 pin (OLV2 in

Output Compare mode). Whatever the value of the OC2E bit, the Output Compare 2
function of the timer remains active.
0: OCMP2 pin alternate function disabled (I/O pin free for general-purpose I/O).
1: OCMP2 pin alternate function enabled.

One Pulse Mode

0: One Pulse mode is not active.
1: One Pulse mode is active, the ICAP1 pin can be used to trigger one pulse on the
OCMP1 pin; the active transition is given by the IEDG1 bit. The length of the
generated pulse depends on the contents of the OC1R register.

Pulse Width Modulation

0: PWM mode is not active.
1: PWM mode is active, the OCMP1 pin outputs a programmable cyclic signal; the
length of the pulse depends on the value of OC1R register; the period depends on
the value of OC2R register.

Clock Control

The timer clock mode depends on these bits.
00: Timer clock = f
01: Timer clock = f
10: Timer clock = f

CPU
CPU
CPU

/4
/2
/8

11: Timer clock = external clock (where available)

Note: If the external clock pin is not available, programming the external clock
configuration stops the counter.

1IEDG2

0 EXEDG

Input Edge 2

This bit determines which type of level transition on the ICAP2 pin will trigger the
capture.
0: A falling edge triggers the capture.
1: A rising edge triggers the capture.

External Clock Edge

This bit determines which type of level transition on the external clock pin EXTCLK
will trigger the counter register.
0: A falling edge triggers the counter register.
1: A rising edge triggers the counter register.

Doc ID13466 Rev 4 91/198

On-chip peripherals ST72324B-Auto

Control/Status Register (CSR)

CSR Reset value: xxxx x0xx (xxh)

76543210

ICF1 OCF1 TOF ICF2 OCF2 TIMD Reserved

RO RO RO RO RO R/W -

M

Table 51. CSR register description

Bit Name Function

Input Capture Flag 1

0: No Input Capture (reset value).

7ICF1

6OCF1

1: An Input Capture has occurred on the ICAP1 pin or the counter has reached the
OC2R value in PWM mode. To clear this bit, first read the SR register, then read or
write the low byte of the IC1R (IC1LR) register.

Output Compare Flag 1

0: No match (reset value).
1: The content of the free running counter has matched the content of the OC1R
register. To clear this bit, first read the SR register, then read or write the low byte of
the OC1R (OC1LR) register.

Timer Overflow Flag

0: No timer overflow (reset value).

5TOF

1: The free running counter rolled over from FFFFh to 0000h. To clear this bit, first
read the SR register, then read or write the low byte of the CR (CLR) register.

Note: Reading or writing the ACLR register does not clear TOF.

Input Capture Flag 2

4ICF2

0: No input capture (reset value).
1: An Input Capture has occurred on the ICAP2 pin. To clear this bit, first read the SR
register, then read or write the low byte of the IC2R (IC2LR) register.

Output Compare Flag 2

0: No match (reset value).

3OCF2

1: The content of the free running counter has matched the content of the OC2R
register. To clear this bit, first read the SR register, then read or write the low byte of
the OC2R (OC2LR) register.

Timer Disable

This bit is set and cleared by software. When set, it freezes the timer prescaler and
counter and disabled the output functions (OCMP1 and OCMP2 pins) to reduce

2TIMD

power consumption. Access to the timer registers is still available, allowing the timer
configuration to be changed, or the counter reset, while it is disabled.
0: Timer enabled.
1: Timer prescaler, counter and outputs disabled.

1:0 - Reserved, must be kept cleared.

92/198 Doc ID13466 Rev 4

ST72324B-Auto On-chip peripherals

Input Capture 1 High Register (IC1HR)

This is an 8-bit register that contains the high part of the counter value (transferred by the
input capture 1 event).

IC1HR Reset value: undefined

76543210

MSB LSB

RO RO RO RO RO RO RO RO

Doc ID13466 Rev 4 93/198

On-chip peripherals ST72324B-Auto

Input Capture 1 Low Register (IC1LR)

This is an 8-bit register that contains the low part of the counter value (transferred by the
input capture 1 event).

IC1LR Reset value: undefined

76543210

MSB LSB

RO RO RO RO RO RO RO RO

Output Compare 1 High Register (OC1HR)

This is an 8-bit register that contains the high part of the value to be compared to the CHR
register.

OC1HR Reset value: 1000 0000 (80h)

76543210

MSB LSB

R/W R/W R/W R/W R/W R/W R/W R/W

Output Compare 1 Low Register (OC1LR)

This is an 8-bit register that contains the low part of the value to be compared to the CLR
register.

OC1LR Reset value: 0000 0000 (00h)

76543210

MSB LSB

R/W R/W R/W R/W R/W R/W R/W R/W

Output Compare 2 High Register (OC2HR)

This is an 8-bit register that contains the high part of the value to be compared to the CHR
register.

OC2HR Reset value: 1000 0000 (80h)

76543210

MSB LSB

R/W R/W R/W R/W R/W R/W R/W R/W

94/198 Doc ID13466 Rev 4

ST72324B-Auto On-chip peripherals

Output Compare 2 Low Register (OC2LR)

This is an 8-bit register that contains the low part of the value to be compared to the CLR
register.

OC2LR Reset value: 0000 0000 (00h)

76543210

MSB LSB

R/W R/W R/W R/W R/W R/W R/W R/W

Counter High Register (CHR)

This is an 8-bit register that contains the high part of the counter value.

CHR Reset value: 1111 1111 (FFh)

76543210

MSB LSB

RO RO RO RO RO RO RO RO

Counter Low Register (CLR)

This is an 8-bit register that contains the low part of the counter value. A write to this register
resets the counter. An access to this register after accessing the CSR register clears the
TOF bit.

CLR Reset value: 1111 1100 (FCh)

76543210

MSB LSB

RO RO RO RO RO RO RO RO

Alternate Counter High Register (ACHR)

This is an 8-bit register that contains the high part of the counter value.

ACHR Reset value: 1111 1111 (FFh)

76543210

MSB LSB

RO RO RO RO RO RO RO RO

Doc ID13466 Rev 4 95/198

On-chip peripherals ST72324B-Auto

Alternate Counter Low Register (ACLR)

This is an 8-bit register that contains the low part of the counter value. A write to this register
resets the counter. An access to this register after an access to CSR register does not clear
the TOF bit in the CSR register.

ACLR Reset value: 1111 1100 (FCh)

76543210

MSB LSB

RO RO RO RO RO RO RO RO

Input Capture 2 High Register (IC2HR)

This is an 8-bit register that contains the high part of the counter value (transferred by the
Input Capture 2 event).

1C2HR Reset value: undefined

76543210

MSB LSB

RO RO RO RO RO RO RO RO

Input Capture 2 Low Register (IC2LR)

This is an 8-bit register that contains the low part of the counter value (transferred by the
Input Capture 2 event).

1C2LR Reset value: undefined

76543210

MSB LSB

RO RO RO RO RO RO RO RO

Table 52. 16-bit timer register map and reset values

Address

(Hex.)

Timer A: 32
Timer B: 42

Timer A: 31
Timer B: 41

Timer A: 33
Timer B: 43

Register

label

CR1
Reset value

CR2
Reset value

CSR
Reset value

76543210

ICIE

0

OCIE

0

TOIE0FOLV20FOLV10OLVL20IEDG10OLVL1

OC1E0OC2E0OPM

0

ICF1

x

OCF1

x

TOF

x

PWM

0

ICF2

x

CC1

0

OCF2

x

0

CC00IEDG20EXEDG

0

TIMD

0

-

x

-

x

Timer A: 34
Timer B: 44

IC1HR
Reset value

MSB

xxxxxxx

96/198 Doc ID13466 Rev 4

LSB

x

ST72324B-Auto On-chip peripherals

Table 52. 16-bit timer register map and reset values (continued)

Address

(Hex.)

Timer A: 35
Timer B: 45

Timer A: 36
Timer B: 46

Timer A: 37
Timer B: 47

Timer A: 3E
Timer B: 4E

Timer A: 3F
Timer B: 4F

Timer A: 38
Timer B: 48

Timer A: 39
Timer B: 49

Timer A: 3A
Timer B: 4A

Timer A: 3B
Timer B: 4B

Timer A: 3C
Timer B: 4C

Register

label

IC1LR
Reset value

OC1HR
Reset value

OC1LR
Reset value

OC2HR
Reset value

OC2LR
Reset value

CHR
Reset value

CLR
Reset value

ACHR
Reset value

ACLR
Reset value

IC2HR
Reset value

76543210

MSB

xxxxxxx

MSB

1000000

MSB

0000000

MSB

1000000

MSB

0000000

MSB

1111111

MSB

1111110

MSB

1111111

MSB

1111110

MSB

xxxxxxx

LSB

x

LSB

0

LSB

0

LSB

0

LSB

0

LSB

1

LSB

0

LSB

1

LSB

0

LSB

x

Timer A: 3D
Timer B: 4D

IC2LR
Reset value

MSB

xxxxxxx



10.4 Serial peripheral interface (SPI)

10.4.1 Introduction

The serial peripheral interface (SPI) allows full-duplex, synchronous, serial communication
with external devices. An SPI system may consist of a master and one or more slaves.
However, the SPI interface can not be a master in a multi-master system.

10.4.2 Main features

● Full duplex synchronous transfers (on 3 lines)

● Simplex synchronous transfers (on 2 lines)

● Master or slave operation

● 6 master mode frequencies (f

● f

● SS Management by software or hardware

● Programmable clock polarity and phase

● End of transfer interrupt flag

● Write collision, Master mode fault and Overrun flags

/2 max. slave mode frequency (see note)

CPU

CPU

/4 max.)

LSB

x

Doc ID13466 Rev 4 97/198

On-chip peripherals ST72324B-Auto

SPIDR

Read Buffer

8-bit Shift Register

Write

Read

Data/Address bus

SPI

SPIE SPE MSTR CPHA SPR0SPR1CPOL

Serial clock

generator

MOSI

MISO

SS

SCK

control

state

SPICR

SPICSR

Interrupt

request

Master

control

SPR2

0

7

0

7

SPIF WCOL MODF

0

OVR SS ISSMSOD

SOD

bit

SS

1

0

Note: In slave mode, continuous transmission is not possible at maximum frequency due to the

software overhead for clearing status flags and to initiate the next transmission sequence.

10.4.3 General description

Figure 49 shows the serial peripheral interface (SPI) block diagram. The SPI has three

registers:

● SPI Control Register (SPICR)

● SPI Control/Status Register (SPICSR)

● SPI Data Register (SPIDR)

The SPI is connected to external devices through four pins:

● MISO: Master In / Slave Out data

● MOSI: Master Out / Slave In data

● SCK: Serial Clock out by SPI masters and input by SPI slaves

● SS: Slave select: This input signal acts as a ‘chip select’ to let the SPI master

communicate with slaves individually and to avoid contention on the data lines. Slave
SS

inputs can be driven by standard I/O ports on the master MCU.

Figure 48. Serial peripheral interface block diagram

98/198 Doc ID13466 Rev 4

Functional description

A basic example of interconnections between a single master and a single slave is
illustrated in

Figure 49.

ST72324B-Auto On-chip peripherals

8-bit Shift Register

SPI

clock

generator

8-bit Shift Register

MISO

MOSI

MOSI

MISO

SCK

SCK

Slave

Master

SS

SS

+5V

MSB LSB MSB LSB

Not used if SS is managed

by software

The MOSI pins are connected together and the MISO pins are connected together. In this
way data is transferred serially between master and slave (most significant bit first).

The communication is always initiated by the master. When the master device transmits
data to a slave device via MOSI pin, the slave device responds by sending data to the
master device via the MISO pin. This implies full duplex communication with both data out
and data in synchronized with the same clock signal (which is provided by the master device
via the SCK pin).

To use a single data line, the MISO and MOSI pins must be connected at each node (in this
case only simplex communication is possible).

Four possible data/clock timing relationships may be chosen (see Figure 52) but master and
slave must be programmed with the same timing mode.

Figure 49. Single master/single slave application

Slave Select management

As an alternative to using the SS pin to control the Slave Select signal, the application can
choose to manage the Slave Select signal by software. This is configured by the SSM bit in
the SPICSR register (see

In software management, the external SS pin is free for other application uses and the
internal

SS signal level is driven by writing to the SSI bit in the SPICSR register.

In Master mode:

● SS internal must be held high continuously

Depending on the data/clock timing relationship, there are two cases in Slave mode (see

Figure 50):

If CPHA = 1 (data latched on second clock edge):

● SS internal must be held low during the entire transmission. This implies that in single

slave applications the SS
managing the SS
register)

If CPHA = 0 (data latched on first clock edge):

● SS internal must be held low during byte transmission and pulled high between each

byte to allow the slave to write to the shift register. If SS

Figure 51).

pin either can be tied to VSS, or made free for standard I/O by

function by software (SSM = 1 and SSI = 0 in the in the SPICSR

is not pulled high, a Write

Doc ID13466 Rev 4 99/198

On-chip peripherals ST72324B-Auto

Byte 1 Byte 2

Byte 3

MOSI/MISO

Master SS

Slave SS
(if CPHA=0)

Slave SS
(if CPHA=1)

1

0

SS internal

SSM bit

SSI bi

t

SS external pin

Collision error will occur when the slave writes to the shift register (seeWrite collision

error (WCOL) on page 103).

Figure 50. Generic SS

timing diagram

Figure 51. Hardware/software slave select management

Master mode operation

In master mode, the serial clock is output on the SCK pin. The clock frequency, polarity and
phase are configured by software (refer to the description of the SPICSR register).

Note: The idle state of SCK must correspond to the polarity selected in the SPICSR register (by

pulling up SCK if CPOL

= 1 or pulling down SCK if CPOL = 0).

How to operate the SPI in master mode

To operate the SPI in master mode, perform the following steps in order:

1. Write to the SPICR register:

– Select the clock frequency by configuring the SPR[2:0] bits.
– Select the clock polarity and clock phase by configuring the CPOL and CPHA bits.

Figure 52 shows the four possible configurations.

Note: The slave must have the same CPOL and CPHA settings as the master.

2. Write to the SPICSR register:

– Either set the SSM bit and set the SSI bit or clear the SSM bit and tie the SS pin

high for the complete byte transmit sequence.

3. Write to the SPICR register:

– Set the MSTR and SPE bits.

Note: MSTR and SPE bits remain set only if SS

is high.

Caution: If the SPICSR register is not written first, the SPICR register setting (MSTR bit) might not be

taken into account.

The transmit sequence begins when software writes a byte in the SPIDR register.

100/198 Doc ID13466 Rev 4