ST ST72101, ST72212, ST72213 User Manual

查询ST72101G1供应商
ST72101/ST72212/ST72213
8-BIT MCU WITH 4 TO 8K ROM/OTP/EPROM,
256 BYTES RAM, ADC, WDG, SPI AND 1 OR 2 TIMERS
DATASHEET
User Program Memory (ROM/OTP/EPROM):
4 to8K bytes
Data RAM: 256 bytes, including 64 bytes of
Master Resetand Power-On Reset
Run, Wait, Slow, Halt and RAM Retention
modes
22 multifunctionalbidirectional I/O lines:
– 22 programmable interrupt inputs – 8 high sinkoutputs – 6 analog alternateinputs – 10 to 14 alternate functions – EMI filtering
Programmable watchdog (WDG)
One or two 16-bit Timers, each featuring:
– 2 Input Captures – 2 Output Compares – External Clock input (on Timer A only) – PWM and Pulse Generator modes
Synchronous Serial Peripheral Interface (SPI)
8-bit Analog-to-Digital converter (6 channels)
(ST72212 and ST72213 only)
8-bit Data Manipulation
63 Basic Instructions
17 mainAddressing Modes
8 x8 Unsigned Multiply Instruction
True BitManipulation
Complete Development Support on PC/DOS-
(See ordering information at the end of datasheet)
WINDOWSTMReal-Time Emulator
Full Software Package on DOS/WINDOWS
TM
(C-Compiler, Cross-Assembler, Debugger)
Device Summary
Features ST72101G1 ST72101G2 ST72213G1 ST72212G2
Program Memory- bytes 4K 8K 4K 8K RAM (stack) - bytes 256 (64) 16-bit Timers one one one two ADC no no yes yes Other Peripherals Watchdog, SPI Operating Supply 3 to 5.5 V CPU Frequency 8MHz max (16MHz oscillator) - 4MHz max over 85°C Temperature Range - 40°C to + 125°C Package SO28 - SDIP32
September 1999 1/84
PSDIP32
CSDIP32W
SO28
Rev. 1.7
1
Table of Contents
1 GENERAL DESCRIPTION . . . . . . ................................................ 4
1.1 INTRODUCTION . . . . . . . . . . . . ............................................. 4
1.2 PIN DESCRIPTION . . ..................................................... 5
1.3 EXTERNAL CONNECTIONS . .. . . . . . . . . . . . . . . . . . . .. . . . . . . .. . . . . . . . . ......... 9
1.4 MEMORY MAP . . . . . .. . . . ............................................... 10
2 CENTRAL PROCESSING UNIT . . ............................................... 13
2.1 INTRODUCTION . . . . . . . . . . . . ............................................13
2.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . .............................. 13
2.3 CPU REGISTERS . . . .................................................... 13
3 CLOCKS, RESET, INTERRUPTS & POWER SAVING MODES . . . . . .. . . . . . . ...........16
3.1 CLOCK SYSTEM . . . . . .. . . . . . ............................................16
3.1.1 General Description . . . .. . ...........................................16
3.2 RESET . . . . . . . . . . . . .. . . . . . . .. . . . . . . . . . . . . .............................. 17
3.2.1 Introduction . . . .................................................... 17
3.2.2 External Reset . . . . . . ...............................................17
3.2.3 Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . ........................... 17
3.2.4 Power-on Reset .................................................... 17
3.3 INTERRUPTS . . . .. . . . . . .. . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . .. . . . . . . .. . . . . . . 18
3.4 POWER SAVING MODES . .. . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . .. . . . . . . ........ 21
3.4.1 Introduction . . . .................................................... 21
3.4.2 Slow Mode . . .. . . . . . . . . . . . . . . . . . . . ................................. 21
3.4.3 Wait Mode . . . . . . . . . . . . . . .. ........................................ 21
3.4.4 Halt Mode . . . . . .................................................... 22
3.5 MISCELLANEOUS REGISTER . . . . .. . . . . . .................................. 23
4 ON-CHIP PERIPHERALS . . . . . . . . . . . ...........................................24
4.1 I/O PORTS . . . . . . . . .. . . . . . . . . ...........................................24
4.1.1 Introduction . . . .................................................... 24
4.1.2 Functional Description . . . . ...........................................24
4.1.3 I/O Port Implementation . . . . . . . . . . . . . . . . . . . ........................... 25
4.1.4 Register Description . . . . . . ...........................................28
4.2 WATCHDOG TIMER (WDG) . . . . . . .. . . . . . . .. . . .. . . .. . . . . . . . . . . . . . . . .. . . . . . . 30
4.2.1 Introduction . . . .................................................... 30
4.2.2 Main Features . .. . . . ...............................................30
4.2.3 Functional Description . . . . ...........................................31
4.2.4 Low Power Modes . . . ............................................... 31
4.2.5 Interrupts . . . . . .. . . . . . . . . . .. . . . . . . ................................. 31
4.2.6 Register Description . . . . . . ...........................................31
4.3 16-BIT TIMER . . . . . . . . . . . . . . . . . . ........................................32
4.3.1 Introduction . . . .................................................... 32
4.3.2 Main Features . .. . . . ...............................................32
4.3.3 Functional Description . . . . ...........................................32
4.3.4 Low Power Modes . . ............................................... 43
4.3.5 Interrupts . . .. . .................................................... 43
4.3.6 Register Description . . . . . . ...........................................44
95
2/84
2
Table of Contents
4.4 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . .. . . . . . . . . ...........49
4.4.1 Introduction . . . .................................................... 49
4.4.2 Main Features . .. . . . ...............................................49
4.4.3 General description . . . . . .. . . . . . . . .. . . .. . . . . . . . . . .. . . . . . . . . . . . . . . . . . . 49
4.4.4 Functional Description . . . . ...........................................51
4.4.5 Low Power Modes . . . ............................................... 58
4.4.6 Interrupts . . .. . .................................................... 58
4.4.7 Register Description . . . . . . ...........................................59
4.5 8-BIT A/D CONVERTER (ADC) . . . . . .. . . . . . . . . . . . ........................... 62
4.5.1 Introduction . . . .................................................... 62
4.5.2 Main Features . .. . . . ...............................................62
4.5.3 Functional Description . . . . ...........................................63
4.5.4 Low Power Modes . . . ............................................... 63
4.5.5 Interrupts . . . . . .. . . . . . . . . . .. . . . . . . ................................. 63
4.5.6 Register Description . . . . . . ...........................................64
5 INSTRUCTION SET . . . . . . . . . . . . . . . . . . ........................................ 65
5.1 ST7 ADDRESSING MODES . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . 65
5.1.1 Inherent . . . . . . . . . . . ...............................................66
5.1.2 Immediate . .. . . . . . . . . . . . . . . . . . . .. . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
5.1.3 Direct . ........................................................... 66
5.1.4 Indexed (No Offset, Short, Long) . . . . . . . . . . . . ........................... 66
5.1.5 Indirect (Short, Long) . . . . .. . . . . . . . . . .. . . . . . . . . . . . .. . . .. . . . . . . . . . . . . . . 66
5.1.6 Indirect Indexed (Short,Long) . ........................................67
5.1.7 Relative mode (Direct,Indirect) . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . .. . . . . . . . 67
5.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . ................................. 68
6 ELECTRICALCHARACTERISTICS . . . . . . . . . . . . . . . . .............................. 71
6.1 ABSOLUTE MAXIMUM RATINGS . . . ........................................71
6.2 RECOMMENDED OPERATING CONDITIONS . . ............................... 72
6.3 DC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . .. . . . . . . . . . . . . ...........73
6.4 RESET CHARACTERISTICS . . . . . . . . . ..................................... 74
6.5 OSCILLATOR CHARACTERISTICS . . . .. . . . . . . .............................. 74
6.6 A/D CONVERTERCHARACTERISTICS (ST72212 AND ST72213ONLY) . . . ........ 75
6.7 SPI CHARACTERISTICS . . ...............................................77
7 GENERAL INFORMATION . . . . . . . . . . ........................................... 80
7.1 EPROM ERASURE . . .. . . . . . . . . . . . . .. . . . . . ............................... 80
7.2 PACKAGE MECHANICALDATA . . . . . . . . . . . . .. . . . ........................... 80
7.3 ORDERING INFORMATION . . . . . .. . . . . . . .................................. 82
7.3.1 Transfer Of CustomerCode . . . . . . . . . . . .. . . .. . . . . . . . . . . . ............... 82
8 SUMMARY OF CHANGES . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
3/84
3
ST72101/ST72212/ST72213
1 GENERAL DESCRIPTION
1.1 INTRODUCTION
The ST72101, ST72213 and ST72212 HCMOS Microcontroller Units are members of the ST7 family. These devices are based on an industry­standard 8-bit core and feature an enhanced instruction set. They normally operate ata 16MHz oscillator frequency. Under software control, the ST72101, ST72213 and ST72212 may be placed in either WAIT, SLOW or HALT modes, thus reducing power consumption. The enhanced instruction set and addressing modes afford real programming potential. In addition to standard 8-bit data management, the ST72101, ST72213
unsigned multiplication and indirect addressing modes on the whole memory. The devices include an on-chip oscillator, CPU, program memory (ROM/OTP/EPROM versions), RAM, 22 I/O lines and the following on-chip peripherals: Analog-to­Digital Converter (ADC) with 6 multiplexed analog inputs (ST72212 and ST72213 only), industry standard synchronous SPI serial interface, digital Watchdog, one or two independent 16-bit Timers, one featuring an External Clock Input, and both featuring Pulse Generator capabilities, 2 Input Captures and 2 Output Compares.
and ST72212 feature true bit manipulation, 8x8
Figure 1. ST72101, ST72213 and ST72212 Block Diagram
Internal
OSCIN
OSCOUT
RESET
OSC
CONTROL
8-BIT CORE
ALU
CLOCK
ADDRESSAND DATA BUS
PORT A
SPI
PORT B
TIMER A
PA0 -> PA7
(8 bits)
PB0 -> PB7
(8 bits)
4/84
4
PROGRAM
MEMORY
(4 - 8K Bytes)
(256 Bytes)
V
DD
V
SS
1) ST72213 and ST72212 only
2) ST72212 only
RAM
POWER
SUPPLY
PORT C
8-BIT ADC
TIMER B
WATCHDOG
PC0 -> PC5
(6 bits)
1)
2)
1.2 PIN DESCRIPTION
ST72101/ST72212/ST72213
Figure 2. ST72212 Pinout (SO28)
RESET
OSCIN
OSCOUT
SS/PB7
SCK/PB6 MISO/PB5 MOSI/PB4
OCMP2_A/PB3
ICAP2_A/PB2
OCMP1_A/PB1
ICAP1_A/PB0
AIN5/EXTCLK_A/PC5
AIN4/OCMP2_B/PC4
AIN3/ICAP2_B/PC3
1) VPPonEPROM/OTP only
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
Figure 3. ST72213 Pinout (SO28)
RESET
OSCIN
OSCOUT
SS/PB7
SCK/PB6 MISO/PB5 MOSI/PB4
OCMP2_A/PB3
ICAP2_A/PB2
OCMP1_A/PB1
ICAP1_A/PB0
AIN5/EXTCLK_A/PC5
AIN4/PC4 AIN3/PC3
1) VPPon EPROM/OTPonly
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
V
DD
V
SS
TEST/V PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PC0/ICAP1_B/AIN0 PC1/OCMP1_B/AIN1 PC2/CLKOUT/AIN2
1)
PP
V
DD
V
SS
TEST/V PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PC0/AIN0 PC1/AIN1 PC2/CLKOUT/AIN2
1)
PP
Figure 5. ST72212 Pinout (SDIP32)
V
RESET
OSCIN
OSCOUT
SS/PB7
SCK/PB6 MISO/PB5 MOSI/PB4
NC NC
OCMP2_A/PB3
ICAP2_A/PB2
OCMP1_A/PB1
ICAP1_A/PB0
AIN5/EXTCLK_A/PC5
AIN4/OCMP2_B/PC4
AIN3/ICAP2_B/PC3
1) VPPon EPROM/OTP only
1 2 3 4 5 6 7 8
9 10 11 12 13 14 15 16
32 31 30
29 28 27 26 25 24 23 22 21 20 19 18 17
V TEST/V PA0 PA1 PA2 PA3 NC NC PA4 PA5 PA6 PA7 PC0/ICAP1_B/AIN0 PC1/OCMP1_B/AIN1 PC2/CLKOUT/AIN2
Figure 6. ST72213 Pinout (SDIP32)
V
RESET
OSCIN
OSCOUT
SS/PB7
SCK/PB6 MISO/PB5 MOSI/PB4
NC NC
OCMP2_A/PB3
ICAP2_A/PB2
OCMP1_A/PB1
ICAP1_A/PB0
AIN5/EXTCLK_A/PC5
AIN4/PC4 AIN3/PC3
1) VPPonEPROM/OTP only
1 2 3 4 5 6 7 8
9 10 11 12 13 14
15
32 31
TEST/V
30 29
PA0 PA1
28
PA2
27 26
PA3
25
NC
24
NC
23
PA4
22
PA5
21
PA6
20
PA7
19
PC0/AIN0
18
PC1/AIN1
1716
PC2/CLKOUT/AIN2
V
DD SS
1)
PP
DD
SS
1)
PP
Figure 4. ST72101 Pinout (SO28)
RESET
OSCIN
OSCOUT
SS/PB7
SCK/PB6 MISO/PB5 MOSI/PB4
OCMP2_A/PB3
ICAP2_A/PB2
OCMP1_A/PB1
ICAP1_A/PB0
EXTCLK_A/PC5
PC4 PC3
1) VPPon EPROM/OTP only
1 2 3 4 5 6 7 8 9 10 11 12 13
14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
V
DD
V
SS
TEST/V PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PC0 PC1 PC2/CLKOUT
1)
PP
Figure 7. ST72101 Pinout (SDIP32)
32
RESET
OSCIN
OSCOUT
SS/PB7
SCK/PB6 MISO/PB5 MOSI/PB4
NC NC
OCMP2_A/PB3
ICAP2_A/PB2
OCMP1_A/PB1
ICAP1_A/PB0
EXTCLK_A/PC5
PC4 PC3
1) VPPon EPROM/OTPonly
1 2 3 4 5 6 7 8
9 10 11 12 13 14
15
31 30
29 28 27 26 25 24 23 22 21 20 19 18 1716
V V TEST/V PA0 PA1 PA2 PA3
NC NC PA4 PA5 PA6 PA7 PC0 PC1 PC2/CLKOUT
DD SS
1)
PP
5/84
5
ST72101/ST72212/ST72213
Table 1. ST72212 Pin Configuration
Pin n°
SDIP32
Pin n °
SO28
Pin Name Type Description Remarks
1 1 RESET I/O Bidirectional. Active low. Top priority non maskable interrupt. 22OSCIN I 3 3 OSCOUT O
Input/Output Oscillator pin. These pins connect a parallel-resonant crystal, or an external source to the on-chip oscillator.
4 4 PB7/SS I/O Port B7 or SPI Slave Select (active low) External Interrupt: EI1 5 5 PB6/SCK I/O Port B6 or SPI Serial Clock External Interrupt: EI1 6 6 PB5/MISO I/O Port B5 or SPI Master In/ Slave Out Data External Interrupt: EI1 7 7 PB4/MOSI I/O Port B4 or SPI Master Out / Slave In Data External Interrupt: EI1 8 NC Not Connected
9 NC Not Connected 10 8 PB3/OCMP2_A I/O Port B3 or TimerA Output Compare 2 External Interrupt: EI1 11 9 PB2/ICAP2_A I/O Port B2 or TimerA Input Capture 2 External Interrupt: EI1 12 10 PB1/OCMP1_A I/O Port B1 or TimerA Output Compare 1 External Interrupt: EI1 13 11 PB0/ICAP1_A I/O Port B0 or TimerA Input Capture 1 External Interrupt: EI1 14 12 PC5/EXTCLK_A/AIN5 I/O PortC5orTimerA InputClockorADCAnalog Input5 External Interrupt: EI1
15 13 PC4/OCMP2_B/AIN4 I/O 16 14 PC3 /IC A P2 _ B /AIN 3 I/O
PortC4orTimerB OutputCompare2orADCAnalog Input 4
Port C3 orTimerB InputCapture 2 orADC Analog Input 3
External Interrupt: EI1 External Interrupt: EI1
Port C2or InternalClockFrequency Outputor ADC
17 15 PC2/CLKOUT/AIN2 I/O
Analog Input 2. Clockout is driven by Bit 5 of the
External Interrupt: EI1
miscellaneous register.
18 16 PC1/OCMP1_B/AIN1 I/O 19 17 PC0 /IC A P1 _ B /AIN 0 I/O
PortC1orTimerB OutputCompare1orADCAnalog Input 1
Port C0 orTimerB InputCapture 1 orADC Analog Input 0
External Interrupt: EI1 External Interrupt: EI1
20 18 PA7 I/O Port A7, High Sink External Interrupt: EI0 21 19 PA6 I/O Port A6, High Sink External Interrupt: EI0 22 20 PA5 I/O Port A5, High Sink External Interrupt: EI0 23 21 PA4 I/O Port A4, High Sink External Interrupt: EI0 24 NC Not Connected 25 NC Not Connected 26 22 PA3 I/O Port A3, High Sink External Interrupt: EI0 27 23 PA2 I/O Port A2, High Sink External Interrupt: EI0 28 24 PA1 I/O Port A1, High Sink External Interrupt: EI0 29 25 PA0 I/O Port A0, High Sink External Interrupt: EI0
30 26 TEST/V 31 27 V
32 28 V
Note 1:VPPon EPROM/OTP only
SS DD
PP
(1)
Test mode pin (should be tied low in user mode). In the EPROM program-
I/S
ming mode, this pin acts as the programming voltage input V
S Ground S Main power supply
PP.
6/84
6
Table 2. ST72213 Pin Configuration
ST72101/ST72212/ST72213
Pin n°
SDIP32
Pin n°
SO28
Pin Name Type Description Remarks
1 1 RESET I/O
2 2 OSCIN I
3 3 OSCOUT O
Bidirectional. Active low. Top priority non maskable interrupt.
Input/Output Oscillator pin. These pins connect a parallel-resonant crystal, oran external source to the on-chip oscillator.
4 4 PB7/SS I/O Port B7 orSPI Slave Select (active low) External Interrupt: EI1
5 5 PB6/SCK I/O Port B6 orSPI Serial Clock External Interrupt: EI1
6 6 PB5/MISO I/O Port B5 orSPI Master In/ Slave Out Data External Interrupt: EI1
7 7 PB4/MOSI I/O Port B4 orSPI Master Out / Slave In Data External Interrupt: EI1
8 NC Not Connected
9 NC Not Connected 10 8 PB3/OCMP2_A I/O Port B3 or TimerA Output Compare 2 External Interrupt: EI1 11 9 PB2/ICAP2_A I/O Port B2 orTimerA Input Capture 2 External Interrupt: EI1 12 10 PB1/OCMP1_A I/O Port B1 or TimerA Output Compare 1 External Interrupt: EI1 13 11 PB0/ICAP1_A I/O Port B0 orTimerA Input Capture 1 External Interrupt: EI1
14 12 PC5/EXTCLK_A/AIN5 I/O
Port C5 orTimerA Input Clock or ADC Analog Input 5
External Interrupt: EI1
15 13 PC4/AIN4 I/O Port C4 or ADC Analog Input 4 External Interrupt: EI1 16 14 PC3/AIN3 I/O Port C3 or ADC Analog Input 3 External Interrupt: EI1
Port C2 orInternal Clock Frequency Output or
17 15 PC2/CLKOUT/AIN2 I/O
ADC Analog Input 2. Clockout is driven by Bit 5
External Interrupt: EI1
of the miscellaneous register.
18 16 PC1/AIN1 I/O Port C1 or ADC Analog Input 1 External Interrupt: EI1 19 17 PC0/AIN0 I/O Port C0 or ADC Analog Input 0 External Interrupt: EI1 20 18 PA7 I/O Port A7, High Sink External Interrupt: EI0 21 19 PA6 I/O Port A6, High Sink External Interrupt: EI0 22 20 PA5 I/O Port A5, High Sink External Interrupt: EI0 23 21 PA4 I/O Port A4, High Sink External Interrupt: EI0 24 NC Not Connected 25 NC Not Connected 26 22 PA3 I/O Port A3, High Sink External Interrupt: EI0 27 23 PA2 I/O Port A2, High Sink External Interrupt: EI0 28 24 PA1 I/O Port A1, High Sink External Interrupt: EI0 29 25 PA0 I/O Port A0, High Sink External Interrupt: EI0
30 26 TEST/V 31 27 V
32 28 V
Note 1:VPPon EPROM/OTP only
SS DD
PP
(1)
Test mode pin (should be tied low in user mode). In the EPROM pro-
I/S
gramming mode, this pin acts asthe programming voltage input V
S Ground S Main power supply
PP.
7/84
7
ST72101/ST72212/ST72213
Table 3. ST72101 Pin Configuration
Pin n°
SDIP32
Pinn°
SO28
Pin Name Type Description Remarks
1 1 RESET I/O Bidirectional. Active low. Top priority non maskable interrupt.
2 2 OSCIN I
3 3 OSCOUT O
Input/Output Oscillator pin. These pins connect a parallel-resonant crystal, or an external source to the on-chip oscillator.
4 4 PB7/SS I/O Port B7 orSPI Slave Select (active low) External Interrupt: EI1
5 5 PB6/SCK I/O Port B6 orSPI Serial Clock External Interrupt: EI1
6 6 PB5/MISO I/O Port B5 orSPI Master In/ Slave Out Data External Interrupt: EI1
7 7 PB4/MOSI I/O Port B4 orSPI Master Out / Slave In Data External Interrupt: EI1
8 NC Not Connected
9 NC Not Connected 10 8 PB3/OCMP2_A I/O Port B3 orTimerA Output Compare 2 External Interrupt: EI1 11 9 PB2/ICAP2_A I/O Port B2 orTimerA Input Capture 2 External Interrupt: EI1 12 10 PB1/OCMP1_A I/O Port B1 orTimerA Output Compare 1 External Interrupt: EI1 13 11 PB0/ICAP1_A I/O Port B0 orTimerA Input Capture 1 External Interrupt: EI1 14 12 PC5/EXTCLK_A I/O Port C5 or TimerA Input Clock External Interrupt: EI1 15 13 PC4 I/O Port C4 External Interrupt: EI1 16 14 PC3 I/O Port C3 External Interrupt: EI1
17 15 PC2/CLKOUT I/O
Port C2 or Internal Clock Frequency Output.Clockout is driven by MCO bit of the miscellaneous register.
External Interrupt: EI1
18 16 PC1 I/O Port C1 External Interrupt: EI1 19 17 PC0 I/O Port C0 External Interrupt: EI1 20 18 PA7 I/O Port A7, High Sink External Interrupt: EI0 21 19 PA6 I/O Port A6, High Sink External Interrupt: EI0 22 20 PA5 I/O Port A5, High Sink External Interrupt: EI0 23 21 PA4 I/O Port A4, High Sink External Interrupt: EI0 24 NC Not Connected 25 NC Not Connected 26 22 PA3 I/O Port A3, High Sink External Interrupt: EI0 27 23 PA2 I/O Port A2, High Sink External Interrupt: EI0 28 24 PA1 I/O Port A1, High Sink External Interrupt: EI0 29 25 PA0 I/O Port A0, High Sink External Interrupt: EI0
30 26 TEST/V 31 27 V
32 28 V
Note 1:V
on EPROM/OTP only.
PP
SS DD
PP
(1)
Test mode pin (should be tied low in user mode). In the EPROM programming
I/S
mode, this pin acts as the programming voltage input V
PP.
S Ground S Main power supply
8/84
8
1.3 EXTERNAL CONNECTIONS
ST72101/ST72212/ST72213
The following figure shows the recommended ex­ternal connections for the device.
The VPPpin is only used for programming OTP and EPROM devices and must betied to ground in user mode.
The 10 nF and 0.1 µF decoupling capacitors on the power supply lines are a suggested EMC per­formance/cost tradeoff.
Figure 8. Recommended External Connections
V
DD
EXTERNAL RESET CIRCUIT
10nF
+
V
DD
0.1µF
0.1µF
The external reset network is intended to protect the device against parasitic resets, especially in noisy environments.
Unused I/Os should be tied high to avoid any un­necessary power consumption on floating lines. An alternative solution is to program the unused ports as inputs with pull-up.
V
PP
V
4.7K
DD
V
SS
RESET
0.1µF
See Clocks Section
Or configure unused I/O ports by software as input with pull-up
V
10K
DD
OSCIN
OSCOUT
Unused I/O
9/84
9
ST72101/ST72212/ST72213
1.4 MEMORY MAP Figure 9. Memory Map
0000h
007Fh 0080h
017Fh
0180h
DFFFh
E000h
F000h
FFDFh
FFE0h
FFFFh
HW Registers
(see Table 5)
256 Bytes RAM
Reserved
8K Bytes
Program Memory
4K Bytes
Program Memory
Interrupt & Reset Vectors
(see Table 4)
0080h
Short Addressing RAM (zero page)
00FFh 0100h
16-bit Addressing
013Fh 0140h
64 Bytes Stack or
16-bit Addressing RAM
017Fh
RAM
Table 4. Interrupt Vector Map
Vector Address Description Remarks
FFE0-FFE1h FFE2-FFE3h FFE4-FFE5h FFE6-FFE7h FFE8-FFE9h
FFEA-FFEBh
FFEC-FFEDh
FFEE-FFEFh
FFF0-FFF1h FFF2-FFF3h FFF4-FFF5h FFF6-FFF7h FFF8-FFF9h FFFA-FFFBh
FFFC-FFFDh
FFFE-FFFFh
TIMER B Interrupt Vector (ST72212 only)
TIMER A Interrupt Vector
External Interrupt Vector EI1 External Interrupt Vector EI0
TRAP (software) Interrupt Vector
Not Used Not Used Not Used Not Used Not Used Not Used Not Used
Not Used
SPI Interrupt Vector
Not Used
RESET Vector
10/84
10
Internal Interrupt
Internal Interrupt Internal Interrupt
External Interrupt External Interrupt
CPU Interrupt
Table 5. Hardware Register Memory Map
Address
Block Name
Register
Label
ST72101/ST72212/ST72213
Register name Reset Status Remarks
0000h 0001h 0002h
0003h Reserved Area (1 Byte) 0004h
0005h 0006h
0007h Reserved Area (1 Byte) 0008h
0009h 000Ah
000Bh to 001Fh
0020h MISCR Miscellaneous Register 00h R/W 0021h
0022h 0023h
0024h WDG WDGCR Watchdog Control register 7Fh R/W 0025h to
0030h 0031h
0032h 0033h 0034h-0035h
0036h-0037h
0038h-0039h
003Ah-003Bh
003Ch-003Dh
003Eh-003Fh
Port C
Port B
Port A
SPI
Timer A
PCDR PCDDR PCOR
PBDR PBDDR PBOR
PADR PADDR PAOR
SPIDR SPICR SPISR
TACR2 TACR1 TASR TAIC1HR TAIC1LR TAOC1HR TAOC1LR TACHR TACLR TAACHR TAACLR TAIC2HR TAIC2LR TAOC2HR TAOC2LR
Data Register Data Direction Register Option Register
Data Register Data Direction Register Option Register
Data Register Data Direction Register Option Register
Reserved Area (21 Bytes)
Data I/O Register Control Register Status Register
Reserved Area (12 Bytes)
Control Register2 Control Register1 Status Register Input Capture1 High Register Input Capture1 Low Register Output Compare1 High Register Output Compare1 Low Register Counter High Register Counter Low Register Alternate Counter High Register Alternate Counter Low Register Input Capture2 High Register Input Capture2 Low Register Output Compare2 High Register Output Compare2 Low Register
00h 00h 00h
00h 00h 00h
00h 00h 00h
xxh 0xh 00h
00h 00h 00h xxh xxh 80h
00h FFh FCh FFh FCh
xxh
xxh
80h
00h
R/W R/W R/W
R/W R/W R/W
R/W R/W R/W
R/W R/W
Read Only
R/W
R/W Read Only Read Only Read Only
R/W
R/W Read Only Read Only Read Only Read Only Read Only Read Only
R/W
R/W
0040h Reserved Area (1 Byte)
11/84
11
ST72101/ST72212/ST72213
Address
0041h 0042h 0043h 0044h-0045h
0046h-0047h
0048h-0049h
004Ah-004Bh
004Ch-004Dh
004Eh-004Fh
0050h to 006Fh
0070h 0071h
0072h to 007Fh
Block Name
Timer B
2)
ADC
1)
Register
Label
TBCR2 TBCR1 TBSR TBIC1HR TBIC1LR TBOC1HR TBOC1LR TBCHR TBCLR TBACHR TBACLR TBIC2HR TBIC2LR TBOC2HR TBOC2LR
ADCDR ADCCSR
Register name Reset Status Remarks
Control Register2 Control Register1 Status Register Input Capture1 High Register Input Capture1 Low Register Output Compare1 High Register Output Compare1 Low Register Counter High Register Counter Low Register Alternate Counter High Register Alternate Counter Low Register Input Capture2 High Register Input Capture2 Low Register Output Compare2 High Register Output Compare2 Low Register
Reserved Area (32 Bytes)
Data Register Control/Status Register
Reserved Area (14 Bytes)
00h 00h 00h xxh xxh 80h
00h FFh FCh FFh FCh
xxh
xxh
80h
00h
00h
00h
R/W
R/W Read Only Read Only Read Only
R/W
R/W Read Only Read Only Read Only Read Only Read Only Read Only
R/W
R/W
Read Only
R/W
Notes:
1. ST72212 only, reserved area for other devices.
2. ST72212 and ST72213 only, reserved otherwise.
12/84
12
2 CENTRAL PROCESSING UNIT
ST72101/ST72212/ST72213
2.1 INTRODUCTION
This CPU hasa full 8-bit architecture andcontains six internal registers allowing efficient 8-bit data manipulation.
2.2 MAIN FEATURES
63 basicinstructions
Fast 8-bit by 8-bit multiply
17 main addressing modes (with indirect
addressing mode)
Two 8-bit index registers
16-bit stackpointer
8 MHzCPU internal frequency
Low power modes
Maskable hardware interrupts
Non-maskable software interrupt
2.3 CPU REGISTERS
The 6 CPU registers shown in Figure 10 are not present in thememory mapping and are accessed by specificinstructions.
Figure 10. CPU Registers
70
RESET VALUE = XXh
70
RESET VALUE= XXh
70
RESET VALUE = XXh
Accumulator (A)
The Accumulator is an 8-bit general purpose reg­ister used to hold operands and the results of the arithmetic and logic calculations andto manipulate data.
Index Registers (Xand Y)
In indexedaddressingmodes, these 8-bit registers are used to create either effective addresses or temporary storage areas for data manipulation. (The Cross-Assembler generates a precede in­struction (PRE) to indicate that the following in­struction refers to the Y register.)
The Y register is notaffected by theinterrupt auto­matic procedures (notpushed toand popped from the stack).
Program Counter (PC)
The program counteris a16-bit register containing the address of the next instruction to be executed by the CPU. It is made of two 8-bit registers PCL (Program CounterLow whichis the LSB) and PCH (Program Counter High which is the MSB).
ACCUMULATOR
X INDEX REGISTER
Y INDEX REGISTER
15 8
RESET VALUE= RESET VECTOR @ FFFEh-FFFFh
15
RESET VALUE = STACKHIGHER ADDRESS
PCH
RESET VALUE =
7
70
1C11HINZ
1X11X1XX
87 0
PCL
0
PROGRAM COUNTER
CONDITION CODE REGISTER
STACK POINTER
X = Undefined Value
13/84
13
ST72101/ST72212/ST72213
CENTRAL PROCESSING UNIT (Cont’d) CONDITION CODE REGISTER (CC)
Read/Write Reset Value: 111x1xxx
70
ter it and resetby the IRET instruction at theend of the interrupt routine. If the I bit is cleared by soft­ware inthe interrupt routine, pending interruptsare serviced regardless of the priority levelof the cur­rent interrupt routine.
111HINZC
The 8-bit Condition Code register contains the in­terrupt mask and four flags representative of the result of the instructionjust executed. This register can also be handled by the PUSH and POP in­structions.
These bits can be individually tested and/or con­trolled by specific instructions.
Bit 4 = H
Half carry
.
This bit isset byhardware when a carry occurs be­tween bits 3 and 4 of the ALU during an ADD or ADC instruction.Itis reset by hardware during the same instructions. 0: No half carry has occurred. 1: A half carry has occurred.
This bit is tested using the JRH or JRNH instruc­tion. The H bit is useful in BCD arithmetic subrou­tines.
Bit 3 = I
Interrupt mask
.
This bit is set by hardware when entering in inter­rupt or by software to disable all interrupts except the TRAP software interrupt. This bit is cleared by software. 0: Interrupts are enabled. 1: Interrupts are disabled.
This bit is controlled by the RIM, SIM and IRET in­structions andis tested bythe JRM and JRNM in­structions.
Note: Interrupts requested while I is set are latched and can be processed when I is cleared. By default an interrupt routine is not interruptable because the I bit is set by hardware when you en-
Bit 2 = N
Negative
.
This bit is set and cleared by hardware.It is repre­sentative of the result sign of the last arithmetic, logical or data manipulation. It is a copy of the 7 bit of the result. 0:Theresult of the last operation is positiveor null. 1: The result of the last operation is negative
(i.e. the most significant bit is a logic 1).
This bit isaccessed by the JRMIand JRPL instruc­tions.
Bit 1 = Z
Zero
.
This bit is set and clearedby hardware. Thisbit in­dicates that the result of the last arithmetic, logical or data manipulation is zero. 0: The result of the last operation is different from
zero.
1: The result of the last operation is zero. This bit is accessed by the JREQ and JRNE test
instructions.
Bit 0 = C
Carry/borrow.
This bit is set and cleared by hardware and soft­ware. It indicates an overflow or anunderflow has occurred during the last arithmetic operation. 0: No overflowor underflow has occurred. 1: An overflow or underflow has occurred.
This bit is driven by the SCFand RCF instructions and tested by theJRC andJRNC instructions.It is also affected by the“bit test and branch”, shift and rotate instructions.
th
14/84
14
ST72101/ST72212/ST72213
CENTRAL PROCESSING UNIT (Cont’d) Stack Pointer (SP)
Read/Write Reset Value: 01 7Fh
15 8
00000001
70
0 1 SP5 SP4 SP3 SP2 SP1 SP0
The Stack Pointer is a 16-bit register which is al­ways pointingto the next free location in the stack. It isthen decremented after datahas been pushed onto the stack and incremented before data is popped from the stack (see Figure 11).
Since the stack is 64 bytes deep, the 10 most sig­nificant bits are forced by hardware. Following an MCU Reset, or after a Reset Stack Pointer instruc­tion (RSP), the Stack Pointer contains its reset val­ue (the SP5 to SP0 bits are set) which is the stack higher address.
The least significant byte of the Stack Pointer (called S) can be directly accessed by a LD in­struction.
Note: When the lower limit is exceeded, the Stack Pointer wraps around tothe stackupper limit, with­out indicating the stack overflow. The previously stored information is then overwritten and there­fore lost.The stackalso wrapsin caseof anunder­flow.
The stack is used to save the return address dur­ing a subroutine call and the CPU context during an interrupt.Theuser may also directly manipulate the stack by means of the PUSH and POP instruc­tions. In the case ofan interrupt, the PCLis stored at the first location pointed to by the SP. Then the other registers are stored in the next locations as shown in Figure 11.
– Whenan interrupt isreceived, the SP is decre-
mented and the context is pushed on the stack.
– Onreturn from interrupt, the SP is incremented
and thecontext is popped from the stack.
A subroutine call occupies twolocations and anin­terrupt five locations in the stack area.
Figure 11. Stack Manipulation Example
@ 0140h
SP
@ 017Fh
CALL
Subroutine
SP
PCH
PCL
Stack Lower Address = 0140h Stack Higher Address =
Interrupt
Event
SP
CC
A
X PCH PCL PCH PCL
017Fh
PUSH Y POP Y IRET
SP
Y
CC
A X
PCH
PCL
PCH
PCL
CC
A
X PCH PCL PCH
PCL
SP
PCH
PCL
RET
or RSP
SP
15/84
15
ST72101/ST72212/ST72213
3 CLOCKS, RESET, INTERRUPTS & POWER SAVING MODES
3.1 CLOCK SYSTEM
3.1.1 General Description
The MCU accepts either a Crystal or Ceramicres­onator, or an external clock signal to drive the in­ternal oscillator. The internal clock (f
rived fromthe external oscillator frequency (f
CPU
) is de-
OSC).
The external Oscillator clock is first divided by 2, and division factor of 32 can be applied if Slow Mode is selected by settingthe SMS bit in the Mis­cellaneous Register. This reduces the frequency of the f
; the clock signal is also routed to the
CPU
on-chip peripherals. The internal oscillator is designed to operate with
an AT-cut parallel resonant quartz crystal resona­tor in the frequency range specified for f
osc
.The
circuit shown in Figure 13 is recommended when using a crystal, and Table 6 lists the recommend­ed capacitance and feedback resistance values. The crystal and associated componentsshould be mounted as close as possible to the input pins in order to minimize output distortion and start-up stabilisation time.
Use of an external CMOS oscillator is recom­mended when crystals outside the specified fre­quency ranges are to be used.
Figure 12. External Clock Source Connections
OSCIN OSCOUT
NC
EXTERNAL
CLOCK
Figure 13. Crystal/CeramicResonator
OSCIN OSCOUT
Table 6. Recommended Values for 16 MHz
Crystal Resonator (C0<7pF)
R
SMAX
C
OSCIN
C
OSCOUT
40 60 150
56pF 47pF 22pF 56pF 47pF 22pF
C0: parasitic shunt capacitance of the quartz crys­tal.
R
er limit, see crystal specification).
C
OSCIN and OSCOUT, including the external ca-
: equivalent serialresistor of the crystal (up-
SMAX
OSCOUT,COSCIN
: maximum total capacitance on
pacitance plus the parasitic capacitance of the board and the device.
C
OSCIN
C
OSCOUT
Figure 14. Clock Prescaler Block Diagram
C
OSCIN
OSCIN
OSCOUT
C
OSCOUT
%2 % 16
f
CPU
to CPU and Peripherals
16/84
16
3.2 RESET
ST72101/ST72212/ST72213
3.2.1 Introduction
There are three sources of Reset: – RESET pin (externalsource) – Power-On Reset (Internal source) – WATCHDOG (Internal Source) The Reset Service Routine vectoris located at ad-
dress FFFEh-FFFFh.
3.2.2 External Reset
The RESET pin is both an input and an open-drain output with integrated pull-up resistor. When one of the internal Reset sources is active, the Reset pin is driven low , for a duration of t the whole application.
RESET,
to reset
3.2.3 Reset Operation
The duration of the Reset state is a minimum of 4096 internal CPU Clock cycles. During the Reset state, all I/Os take their reset value.
A Reset signal originating from an externalsource must have a duration of at least t
PULSE
in order to be recognised. This detection is asynchronous and therefore the MCU can enter Reset state even in Halt mode.
At the end of the Reset cycle, the MCU may be held in the Reset state by an External Reset sig­nal. The RESET pin may thus be used to ensure VDDhas risen to a point where theMCU can oper­ate correctly before the user program is run. Fol-
lowing a Reset event, or after exiting Halt mode, a 4096 CPU Clock cycle delay period is initiated in order to allow the oscillator to stabilise and to en­sure that recovery hastaken place from the Reset state.
In the high state, the RESET pin is connected in­ternally to a pull-up resistor (RON). This resistor can be pulled low by external circuitry to reset the device.
The RESET pin is an asynchronous signal which plays a majorrole in EMS performance. In a noisy environment, it is recommended to use the exter­nal connections shown in Figure8.
3.2.4 Power-on Reset
This circuit detects the ramping up of VDD, and generates a pulse that is used to reset the applica­tion (at approximately VDD= 2V).
Power-On Reset is designed exclusively to cope with power-up conditions, and should not be used in order to attempt to detect a drop in the power supply voltage.
Caution:
to re-initialize the Power-On Reset, the power supply must fall below approximately 0.8V (Vtn), prior to rising above 2V. If this condition is not respected, on subsequent power-upthe Reset pulse may not be generated. An external Reset pulse may be required to correctly reactivate the circuit.
Figure 15. Reset Block Diagram
OSCILLATOR
SIGNAL
RESET
V
DD
R
ON
TO ST7
RESET
INTERNAL RESET
COUNTER
POWER-ON RESET
WATCHDOG RESET
17/84
17
ST72101/ST72212/ST72213
3.3 INTERRUPTS
The ST7 coremaybe interruptedby one of two dif­ferent methods: maskable hardware interrupts as listed in the Interrupt Mapping Table and a non­maskable software interrupt (TRAP). The Interrupt processing flowchartis shown in Figure16. The maskable interrupts mustbe enabled clearing the I bitin order to be serviced. However, disabled interrupts may be latched and processed when they are enabled (see external interrupts subsec­tion).
When an interrupt has to be serviced: – Normal processing is suspended at the end of
the current instruction execution.
– The PC, X, A and CC registersare saved onto
the stack.
– The I bit of the CC register is set to prevent addi-
tional interrupts.
– ThePC is thenloaded with theinterrupt vector of
the interrupt to service and the first instructionof the interrupt serviceroutine is fetched(refer to the Interrupt Mapping Table for vector address­es).
The interrupt service routine should finish with the IRET instruction which causes the contents of the saved registersto be recovered from thestack.
Note: As a consequence of the IRET instruction, the I bit will be cleared and the main program will resume.
Priority management
By default, a servicing interrupt can not be inter­rupted because the I bit is set by hardware enter­ing in interrupt routine.
In the case several interrupts are simultaneously pending, an hardware priority defines which one will be serviced first (seethe Interrupt Mapping Ta­ble).
Non Maskable Software Interrupts
This interrupt is entered when the TRAP instruc­tion is executed regardless of the state of theI bit. It will be serviced according to the flowchart on Figure 16.
Interrupts and Low power mode
All interrupts allowthe processorto leave the Wait low power mode. Only external and specific men­tioned interrupts allow the processor to leave the
Halt low power mode(referto the “Exit from HALT“ column in the Interrupt Mapping Table).
External Interrupts
External interrupt vectorscan be loaded in the PC register if the corresponding external interrupt oc­curred and if the I bit is cleared. These interrupts allow the processor to leave the Halt low power mode.
The external interrupt polarity is selected through the miscellaneous register or interrupt register (if available).
External interrupt triggered on edge will be latched and the interrupt request automatically cleared upon entering the interrupt service routine.
If several input pins, connected to the same inter­rupt vector, are configured as interrupts, their sig­nals are logically ANDed before entering theedge/ level detection block.
Warning: The type of sensitivity defined in the Miscellaneous or Interrupt register (if available) applies to the EI source. In case of an ANDed source (as described on the I/O ports section), a low level on an I/O pin configured as input with in­terrupt, masks the interrupt request even in case of rising-edge sensitivity.
Peripheral Interrupts
Different peripheral interrupt flags in the status register are able to cause an interrupt when they are active if both:
– TheI bit of the CC register is cleared. – Thecorresponding enablebit is set in thecontrol
register.
If any of these two conditions is false, theinterrupt is latched and thus remains pending.
Clearing an interrupt request is done by: – writing “0” to the corresponding bit in the status
register or
– anaccess to the status register while the flag is
set followed bya read or write of anassociated register.
Note: the clearing sequence resets the internal latch. A pending interrupt (i.e. waiting for being en­abled) will therefore be lost ifthe clear sequence is executed.
18/84
18
INTERRUPTS (Cont’d) Figure 16. Interrupt Processing Flowchart
FROM RESET
ST72101/ST72212/ST72213
EXECUTE INSTRUCTION
RESTORE PC, X, A,CC FROM STACK
BIT I SET
Y
FETCH NEXT INSTRUCTION
N
THIS CLEARS I BIT BY DEFAULT
IRET
Y
N
N
BIT I SET
Y
STACK PC, X, A, CC
SET I BIT
LOAD PC FROM INTERRUPT VECTOR
19/84
19
ST72101/ST72212/ST72213
Table 7. Interrupt Mapping
Source
Block
RESET Reset N/A N/A yes FFFEh-FFFFh
TRAP Software N/A N/A no FFFCh-FFFDh
EI0 External Interrupt PA0:PA7 N/A N/A yes FFFAh-FFFBh EI1 External Interrupt PB0:PB7, PC0:PC5 N/A N/A yes FFF8h-FFF9h
SPI
TIMER A
TIMER B
1)
Description
Not Used FFF6h-FFF7h
Transfer Complete
Mode Fault MODF
Input Capture 1
Output Compare 1 OCF1_A
Input Capture 2 ICF2_A
Output Compare 2 OCF2_A
Timer Overflow TOF_A
Not Used FFF0h-FFF1h
Input Capture 1
Output Compare 1 OCF1_B
Input Capture 2 ICF2_B
Output Compare 2 OCF2_B
Timer Overflow TOF_B
Not Used
Register
Label
SPISR
TASR
TBSR
Flag
SPIF
ICF1_A
ICF1_B
Exit
from
HALT
no FFF4h-FFF5h
no FFF2h-FFF3h
no FFEEh-FFEFh
Vector
Address
FFECh-FFEDh
FFEAh-FFEBh
FFE8h-FFE9h FFE6h-FFE7h FFE4h-FFE5h FFE2h-FFE3h
FFE0h-FFE1h
Priority
Order
Highest
Priority
Lowest Priority
Note 1: Timer B is available on ST72212 only.
20/84
20
3.4 POWER SAVING MODES
3.4.1 Introduction
There are threePower Saving modes. SlowMode is selected by setting the relevant bits in the Mis­cellaneous register. Wait and Halt modes may be entered usingthe WFI and HALT instructions.
ST72101/ST72212/ST72213
Figure 17. WAIT Flow Chart
WFI INSTRUCTION
3.4.2 Slow Mode
In Slow mode, the oscillator frequency can be di­vided by a value defined in the Miscellaneous Register. The CPU and peripherals are clocked at this lower frequency. Slow mode isused to reduce power consumption, andenables the user to adapt clock frequencyto available supply voltage.
3.4.3 Wait Mode
Wait mode places the MCU in a low power con­sumption mode by stoppingthe CPU. Allperipher­als remain active. During Wait mode, the I bit (CC Register) is cleared, so as to enable all interrupts. All otherregisters and memory remain unchanged. The MCU will remain in Wait mode until an Inter­rupt or Reset occurs, whereupon the Program Counter branches to the starting address of the In­terrupt orReset Service Routine. The MCU will remain in Wait mode until a Reset or an Interrupt occurs, causing it to wake up.
Refer to Figure 17 below.
N
INTERRUPT
Y
OSCILLATOR PERIPH. CLOCK CPU CLOCK
I-BIT
N
RESET
OSCILLATOR PERIPH. CLOCK CPU CLOCK
I-BIT
4096 CPU CLOCK
CYCLES DELAY
ON
ON
OFF CLEARED
Y
ON
ON
ON SET
OSCILLATOR PERIPH. CLOCK CPU CLOCK
I-BIT
FETCH RESET VECTOR
OR SERVICE INTERRUPT
Note: Before servicing an interrupt, the CC register is pushed on the stack. The I-Bit is set during the inter­rupt routine and cleared when the CC register is popped.
ON
ON
ON SET
21/84
21
ST72101/ST72212/ST72213
POWER SAVINGMODES (Cont’d)
3.4.4 Halt Mode
The Halt mode is the MCU lowest power con­sumption mode. The Halt mode is entered byexe­cuting theHALT instruction. The internal oscillator is then turnedoff, causing allinternal processing to be stopped, including the operation of the on-chip peripherals. The Halt mode cannot be used when the watchdog isenabled, ifthe HALT instruction is executed while the watchdog system is enabled,a watchdog reset is generatedthus resetting the en­tire MCU.
When entering Halt mode, the Ibit in the CC Reg­ister is clearedso as toenable ExternalInterrupts. If an interrupt occurs, the CPU becomes active.
The MCU canexit theHalt mode upon reception of an interrupt or a reset. Refer to the Interrupt Map­ping Table. The oscillator is then turned on and a stabilization time is provided beforereleasing CPU operation. Thestabilization timeis 4096 CPU clock cycles.
After the start up delay, the CPU continuesoper­ation byservicingthe interrupt whichwakes it up or by fetching the reset vector if a reset wakes it up.
Figure 18. HALT Flow Chart
HALT INSTRUCTION
WATCHDOG
RESET
N
EXTERNAL
INTERRUPT
Y
OSCILLATOR PERIPH. CLOCK CPU CLOCK I-BIT
N
1)
WDG
ENABLED?
N
OFF
OFF
OFF CLEARED
RESET
Y
Y
1) or some specific interrupts
2) if reset PERIPH. CLOCK = ON ;if interrupt PERIPH. CLOCK = OFF
Note: Before servicing an interrupt, the CC register is pushed on the stack. The I-Bit is set during the inter­rupt routine and cleared when the CC register is popped.
OSCILLATOR PERIPH. CLOCK CPU CLOCK I-BIT
4096 CPU CLOCK
CYCLES DELAY
OSCILLATOR PERIPH. CLOCK
CPU CLOCK I-BIT
FETCH RESET VECTOR
OR SERVICE INTERRUPT
ON
2)
OFF
ON SET
ON
ON
ON SET
22/84
22
3.5 MISCELLANEOUS REGISTER
ST72101/ST72212/ST72213
The Miscellaneous register allows to select the SLOW operatingmode, the polarity of external in­terrupt requestsand to output the internal clock.
Register Address:0020h — Read/Write Reset Value: 0000 0000 (00h)
70
PEI3 PEI2 MCO PEI1 PEI0 - - SMS
Bit 7:6 = PEI[3:2]
Option
.
External Interrupt EI1 Polarity
These bits are set and cleared by software. They
Bit 4:3 = PEI[1:0]
Option
.
External Interrupt EI0 Polarity
These bits are set and cleared by software. They determine which event on EI0 causes the exter­nal interrupt according to Table 9.
Table 9. EI0 External Interrupt Polarity Options
MODE PEI1 PEI0
Falling edge and low level
(Reset state)
Falling edge only 1 0
Rising edge only 0 1
Rising and falling edge 1 1
determine which event on EI1 causes the exter­nal interrupt according to Table 8.
Note: Any modification of oneof these two bits re-
Table 8. EI1 External Interrupt Polarity Options
MODE PEI3 PEI2
Falling edge and low level
(Reset state)
Falling edge only 1 0
Rising edge only 0 1
Rising and falling edge 1 1
00
Note: Any modification of one of these twobits re­sets the interrupt request related to this interrupt vector.
Bit 5 = MCO
Main Clock Out
sets the interrupt request related to this interrupt vector.
Bit 1:2 = Unused, always read at 0.
Warning:
Software must write 1 to these bits for
compatibility with future products.
Bit 0 = SMS
Slow Mode Select
This bit is set andcleared by software. 0- Normal mode - f
= Oscillator frequency / 2
CPU
(Reset state)
1- Slow mode - f
= Oscillatorfrequency /32
CPU
This bit isset andcleared by software. When set, it enables the output of the Internal Clock on the PC2 I/Oport. 0 -PC2 is a general purpose I/O port. 1 -MCO alternate function (f
is output on PC2
CPU
pin).
00
23/84
23
ST72101/ST72212/ST72213
4 ON-CHIP PERIPHERALS
4.1 I/O PORTS
4.1.1 Introduction
The I/O ports offer different functional modes: – transferof data through digital inputsand outputs and forspecific pins: – analog signal input (ADC) – alternate signal input/output for the on-chip pe-
ripherals. – external interrupt generation An I/O port is composed of up to 8 pins. Each pin
can be programmedindependently as digital input (with or without interrupt generation) or digital out­put.
4.1.2 Functional Description
Each portis associated to 2 main registers: – Data Register (DR) – Data Direction Register (DDR) and someof them to an optional register: – Option Register (OR) Each I/Opin may beprogrammed using thecorre-
sponding register bits inDDR and ORregisters: bit X corresponding to pin Xof the port.The same cor­respondence is used for the DR register.
The following description takes into account the OR register, for specific ports whichdo not provide this register refer to the I/O Port Implementation Section 4.1.3. The generic I/O block diagram is shown onFigure 20.
4.1.2.1 Input Modes
The input configuration isselected by clearing the corresponding DDRregister bit.
In this case, reading the DR register returns the digital value applied to the external I/O pin.
Different input modes can beselected by software through theOR register.
Notes:
1. All the inputs are triggered by a Schmitt trigger.
2. When switching from input mode to output mode, the DR register should be written first to output the correct value as soon as the port is con­figured as an output.
Interrupt function
When an I/O is configured in Input with Interrupt, an event on this I/O can generate an external In­terrupt request to the CPU. Theinterrupt polarity is given independently according to the description mentioned in the Miscellaneous register or in the interrupt register (where available).
Each pin can independently generate an Interrupt request.
Each external interrupt vector is linked to a dedi­cated group of I/O port pins (see Interrupts sec­tion). If several input pins are configured as inputs to the same interrupt vector, their signals are logi­cally ANDed before entering the edge/level detec­tion block. For this reason if one of the interrupt pins is tied low, it masks the other ones.
4.1.2.2 Output Mode
The pin is configured in output mode bysetting the corresponding DDR registerbit.
In this mode, writing “0” or “1” to the DR register applies this digital value to the I/O pin through the latch. Then reading the DR register returns the previously stored value.
Note: In this mode, the interrupt function is disa­bled.
4.1.2.3 Digital Alternate Function
When an on-chipperipheral is configured to use a pin, the alternate function is automatically select­ed. This alternate function takes priority over standard I/O programming. When the signal is coming from an on-chip peripheral, the I/O pin is automatically configuredin output mode (push-pull or open drain according to theperipheral).
When the signal is going to an on-chip peripheral, the I/O pin has to be configured ininput mode. In this case, the pin’s state is also digitally readable by addressing the DR register.
Notes:
1. Input pull-up configuration can cause an unex­pected value atthe input of the alternate peripher­al input.
2. When the on-chip peripheral uses apin asinput and output, this pin must be configured as an input (DDR = 0).
Warning
vated as long as the pin isconfigured as inputwith interrupt, in order to avoid generating spurious in­terrupts.
: The alternate function must not be acti-
24/84
24
I/O PORTS (Cont’d)
4.1.2.4 Analog Alternate Function
When the pin isused asan ADC input theI/O must be configured as input, floating. The analog multi­plexer (controlled by the ADC registers) switches the analog voltage present on the selected pin to the common analog rail which is connected to the ADC input.
It isrecommended not to change the voltage level or loading on any port pin while conversion is in progress. Furthermore it is recommended not to have clocking pins located close to a selected an­alog pin.
Warning
: The analog input voltage level must be
4.1.3 I/O Port Implementation
The hardware implementation oneach I/O port de­pends on the settingsin theDDR andOR registers and specific feature ofthe I/O portsuch as ADCIn­put (see Figure 20) or true open drain. Switching these I/O ports from one state to another should be done in a sequence that prevents unwanted side effects. Recommended safetransitions areil­lustrated in Figure 19. Other transitions are poten­tially risky and should be avoided, since they are likely to present unwanted side-effects such as spurious interrupt generation.
within the limits stated in the Absolute Maximum Ratings.
Figure 19. Recommended I/O State Transition Diagram
ST72101/ST72212/ST72213
INPUT
with interrupt
INPUT
no interrupt
OUTPUT
OUTPUT push-pullopen-drain
25
25/84
ST72101/ST72212/ST72213
I/O PORTS (Cont’d) Figure 20. I/O BlockDiagram
ALTERNATE OUTPUT
ALTERNATE ENABLE
1
M U
X
0
V
DD
P-BUFFER
(S
EE TABLE BELOW)
DATA BUS
EE TABLE BELOW)
(S
COMMON ANALOG RAIL
DR SEL
ALTERNATE INPUT
DR
LATCH
DDR LATCH
OR
LATCH
ORSEL
DDR SEL
ALTERNATE ENABLE
PULL-UP CONDITION
PULL-UP
V
DD
DIODE
(SEE TABLEBELOW)
PAD
ANALOG ENABLE
(ADC)
ANALOG
GND
SWITCH
(S
EE NOTE BELOW)
N-BUFFER
ALTERNATE
1 M U
X
0
ENABLE
GND
CMOS
SCHMITT TRIGGER
EXTERNAL INTERRUPT
POLARITY
SEL
FROM OTHER BITS
SOURCE (EIx)
Table 10. Port Mode Configuration
Configuration Mode Pull-up P-buffer V
Floating 0 0 1 Pull-up 1 0 1 Push-pull 0 1 1
True Open Drain not present not present Open Drain (logic level) 0 0 1
Legend: 0 - present, not activated 1 - present and activated
Notes:
– No OR Register on some ports (see register map). – ADC Switch on ports with analog alternate functions.
26/84
DD
not present in OTP
and EPROM devices
26
Diode
Loading...
+ 58 hidden pages