ST ST7036 User Manual

r

查询ST7036供应商

ST

Sitronix ST7036

Preliminary Dot Matrix LCD Controller/Driver

 Features

z 5 x 8 dot matrix possible
z Low power operation support:

-- 2.7 to 5.5V

z Range of LCD driver power

-- 2.7 to 7.0V

z 4-bit, 8-bit, serial or 400kbits/s fast I

MPU interface enabled

z 80 x 8-bit display RAM (80 characters max.)
z 10,240-bit character generator ROM for a

total of 256 character fonts(max)

z 64 x 8-bit character generator RAM(max)
z Support two display mode:

16-com x 100-seg and 80 ICON
24-com x 80-seg and 80 ICON

z 16 x 5 –bit ICON RAM(max)

2

C-bus

z Wide range of instruction functions:

Display clear, cursor home, display on/off,
cursor on/off, display character blink, cursor
shift, display shift, double height font

z Automatic reset circuit that initializes the

controller/driver after power on and external
reset pin

z Internal oscillator(Frequency=540kHz) and

external clock

z Built-in voltage booster and follower circuit

(low power consumption )

z COM/SEG direction selectable
z Multi-selectable for CGRAM/CGROM size
z Instruction compatible to ST7066U and

KS0066U and HD44780

z Available in COG type

 Description

The ST7036 dot-matrix liquid crystal display controller and

driver LSI displays alphanumeric, Japanese kana
characters, and symbols. It can be configured to drive a
dot-matrix liquid crystal display under the control of a 4-/
8-bit, serial or fast I
the functions such as display RAM, character generator,
and liquid crystal driver, required for driving a dot-matrix
liquid crystal display are internally provided on one chip, a
minimal system can be interfaced with this
controller/driver.

The ST7036 character generator ROM is extended to
generate 256 5x8dot character fonts for a total of 256
different character fonts. The low power supply (2.7V to

product Name

ST7036-0A 256 1 1 English / Japan/Europe

ST7036

2

C interface microprocessor. Since all

Character generato

ROM Size

- - - - -

6800-4bit / 8bit interface
(without IIC interface)

5.5V) of the ST7036 is suitable for any portable
battery-driven product requiring low power dissipation.

The ST7036 LCD driver consists of 17 common signal
drivers and 100 segment signal drivers. And the second
mode is consists of 25 common signal and 80 segment
signal drivers. The maximum display RAM size can be
either 80 characters in 1-line display or 40 characters in
2-line display or 16 characters in 3-line. A single ST7036
can display up to one 20-character line or two 20-character
lines or three 16-character lines.
No extra drivers can be cascaded.

OPR1 OPR2 Support Character

ST7036i

V1.1 2003/12/24

IIC interface

1/72

ST7036

Version Date Description

0.1a 2003/04/28 1st Edition

0.1b 2003/06/03

0.2a 2003/09/01 1. Include ST7036i

1.0 2003/10/24

1.1 2003/12/24

ST7036 Serial Specification Revision History

PAD Dimension:
IC L mark location modified
Chip Size X/Y modified

1. Add application circuit for 3 line display.

2. 4 bit interface program example modified.

1. Remove the instruction of frequency adjust.

2. Add the detail of CGRAM/CGROM arrangement.

V1.1 2003/12/24

2/72

ST7036

 Pad Dimensions

¾ Chip Size: 5190.0X910.0 µm

¾ Bump Pitch : 55 µm ( min )

¾ Bump Height : 17 µm ( typ. )

¾ Bump Size :

z Pad No.1~52 : 56 x 72 µm
z Pad No.53~170 : 35 x 101 µm

V1.1 2003/12/24

3/72

ST7036

 Pad Location Coordinates(N3=0 1 line/2 line)

Pad No. Function X Y Pad No. Function X Y

1 XRESET 1859 393 41 CLS -1181 393

2 OSC 1783 393 42 CAP1N -1257 393

3 VDD 1707 393 43 CAP1N -1333 393

4 RS 1631 393 44 VOUT -1409 393

5 CSB 1555 393 45 VOUT -1485 393

6 RW 1479 393 46 V0 -1561 393

7 E 1403 393 47 V0 -1637 393

8 DB0 1327 393 48 V1 -1713 393

9 DB1 1251 393 49 V2 -1789 393

10 DB2 1175 393 50 V3 -1865 393

11 DB3 1099 393 51 V4 -1941 393

12 DB4 1023 393 52 NC -2017 393

13 DB5 947 393 53 COM[8] -2125 378

14 DB6 871 393 54 COM[7] -2180 378

15 DB7 795 393 55 COM[6] -2235 378

16 VSS 719 393 56 COM[5] -2290 378

17 VSS 643 393 57 COM[4] -2518 365

18 VSS 567 393 58 COM[3] -2518 310

19 OPF1 491 393 59 COM[2] -2518 255

20 OPF2 415 393 60 COM[1] -2518 200

21 OPR1 339 393 61 COMI1 -2518 145

22 OPR2 263 393 62 SEG[1] -2518 90

23 SHLC 187 393 63 SEG[2] -2518 35

24 SHLS 111 393 64 SEG[3] -2518 -20

25 N3 35 393 65 SEG[4] -2518 -75

26 TEST1 -41 393 66 SEG[5] -2518 -130

27 VDD -117 393 67 SEG[6] -2518 -185

28 VDD -193 393 68 SEG[7] -2518 -240

29 VDD -269 393 69 SEG[8] -2518 -295

30 VIN -345 393 70 SEG[9] -2518 -350

31 VIN -421 393 71 SEG[10] -2253 -378

32 VOUT -497 393 72 SEG[11] -2198 -378

33 VOUT -573 393 73 SEG[12] -2143 -378

34 PSB -649 393 74 SEG[13] -2088 -378

35 VSS -725 393 75 SEG[14] -2033 -378

36 PSI2B -801 393 76 SEG[15] -1978 -378

37 CAP1P -877 393 77 SEG[16] -1923 -378

38 CAP1P -953 393 78 SEG[17] -1868 -378

39 EXT -1029 393 79 SEG[18] -1813 -378

40 VSS -1105 393 80 SEG[19] -1758 -378

V1.1 2003/12/24

4/72

ST7036

Pad No. Function X Y Pad No. Function X Y

81 SEG[20] -1703 -378 121 SEG[60] 497 -378

82 SEG[21] -1648 -378 122 SEG[61] 552 -378

83 SEG[22] -1593 -378 123 SEG[62] 607 -378

84 SEG[23] -1538 -378 124 SEG[63] 662 -378

85 SEG[24] -1483 -378 125 SEG[64] 717 -378

86 SEG[25] -1428 -378 126 SEG[65] 772 -378

87 SEG[26] -1373 -378 127 SEG[66] 827 -378

88 SEG[27] -1318 -378 128 SEG[67] 882 -378

89 SEG[28] -1263 -378 129 SEG[68] 937 -378

90 SEG[29] -1208 -378 130 SEG[69] 992 -378

91 SEG[30] -1153 -378 131 SEG[70] 1047 -378

92 SEG[31] -1098 -378 132 SEG[71] 1102 -378

93 SEG[32] -1043 -378 133 SEG[72] 1157 -378

94 SEG[33] -988 -378 134 SEG[73] 1212 -378

95 SEG[34] -933 -378 135 SEG[74] 1267 -378

96 SEG[35] -878 -378 136 SEG[75] 1322 -378

97 SEG[36] -823 -378 137 SEG[76] 1377 -378

98 SEG[37] -768 -378 138 SEG[77] 1432 -378

99 SEG[38] -713 -378 139 SEG[78] 1487 -378

100 SEG[39] -658 -378 140 SEG[79] 1542 -378

101 SEG[40] -603 -378 141 SEG[80] 1597 -378

102 SEG[41] -548 -378 142 SEG[81] 1652 -378

103 SEG[42] -493 -378 143 SEG[82] 1707 -378

104 SEG[43] -438 -378 144 SEG[83] 1762 -378

105 SEG[44] -383 -378 145 SEG[84] 1817 -378

106 SEG[45] -328 -378 146 SEG[85] 1872 -378

107 SEG[46] -273 -378 147 SEG[86] 1927 -378

108 SEG[47] -218 -378 148 SEG[87] 1982 -378

109 SEG[48] -163 -378 149 SEG[88] 2037 -378

110 SEG[49] -108 -378 150 SEG[89] 2092 -378

111 SEG[50] -53 -378 151 SEG[90] 2147 -378

112 SEG[51] 2 -378 152 SEG[91] 2202 -378

113 SEG[52] 57 -378 153 SEG[92] 2518 -350

114 SEG[53] 112 -378 154 SEG[93] 2518 -295

115 SEG[54] 167 -378 155 SEG[94] 2518 -240

116 SEG[55] 222 -378 156 SEG[95] 2518 -185

117 SEG[56] 277 -378 157 SEG[96] 2518 -130

118 SEG[57] 332 -378 158 SEG[97] 2518 -75

119 SEG[58] 387 -378 159 SEG[98] 2518 -20

120 SEG[59] 442 -378 160 SEG[99] 2518 35

V1.1 2003/12/24

5/72

ST7036

Pad No. Function X Y Pad No. Function X Y

161 SEG[100] 2518 90

162 COM[9] 2518 145

163 COM[10] 2518 200

164 COM[11] 2518 255

165 COM[12] 2518 310

166 COM[13] 2518 365

167 COM[14] 2290 378

168 COM[15] 2235 378

169 COM[16] 2180 378

170 COMI2 2125 378

V1.1 2003/12/24

6/72

ST7036

 Pad Location Coordinates(N3=1 3 line)

Pad No. Function X Y Pad No. Function X Y

1 XRESET 1859 393 41 CLS -1181 393

2 OSC 1783 393 42 CAP1N -1257 393

3 VDD 1707 393 43 CAP1N -1333 393

4 RS 1631 393 44 VOUT -1409 393

5 CSB 1555 393 45 VOUT -1485 393

6 RW 1479 393 46 V0 -1561 393

7 E 1403 393 47 V0 -1637 393

8 DB0 1327 393 48 V1 -1713 393

9 DB1 1251 393 49 V2 -1789 393

10 DB2 1175 393 50 V3 -1865 393

11 DB3 1099 393 51 V4 -1941 393

12 DB4 1023 393 52 NC -2017 393

13 DB5 947 393 53 COM[12] -2125 378

14 DB6 871 393 54 COM[11] -2180 378

15 DB7 795 393 55 COM[10] -2235 378

16 VSS 719 393 56 COM[9] -2290 378

17 VSS 643 393 57 COM[8] -2518 365

18 VSS 567 393 58 COM[7] -2518 310

19 OPF1 491 393 59 COM[6] -2518 255

20 OPF2 415 393 60 COM[5] -2518 200

21 OPR1 339 393 61 NC -2518 145

22 OPR2 263 393 62 COM[4] -2518 90

23 SHLC 187 393 63 COM[3] -2518 35

24 SHLS 111 393 64 COM[2] -2518 -20

25 N3 35 393 65 COM[1] -2518 -75

26 TEST1 -41 393 66 COMI1 -2518 -130

27 VDD -117 393 67 NC -2518 -185

28 VDD -193 393 68 NC -2518 -240

29 VDD -269 393 69 NC -2518 -295

30 VIN -345 393 70 NC -2518 -350

31 VIN -421 393 71 NC -2253 -378

32 VOUT -497 393 72 SEG[1] -2198 -378

33 VOUT -573 393 73 SEG[2] -2143 -378

34 PSB -649 393 74 SEG[3] -2088 -378

35 VSS -725 393 75 SEG[4] -2033 -378

36 PSI2B -801 393 76 SEG[5] -1978 -378

37 CAP1P -877 393 77 SEG[6] -1923 -378

38 CAP1P -953 393 78 SEG[7] -1868 -378

39 EXT -1029 393 79 SEG[8] -1813 -378

40 VSS -1105 393 80 SEG[9] -1758 -378

V1.1 2003/12/24

7/72

ST7036

Pad No. Function X Y Pad No. Function X Y

81 SEG[10] -1703 -378 121 SEG[50] 497 -378

82 SEG[11] -1648 -378 122 SEG[51] 552 -378

83 SEG[12] -1593 -378 123 SEG[52] 607 -378

84 SEG[13] -1538 -378 124 SEG[53] 662 -378

85 SEG[14] -1483 -378 125 SEG[54] 717 -378

86 SEG[15] -1428 -378 126 SEG[55] 772 -378

87 SEG[16] -1373 -378 127 SEG[56] 827 -378

88 SEG[17] -1318 -378 128 SEG[57] 882 -378

89 SEG[18] -1263 -378 129 SEG[58] 937 -378

90 SEG[19] -1208 -378 130 SEG[59] 992 -378

91 SEG[20] -1153 -378 131 SEG[60] 1047 -378

92 SEG[21] -1098 -378 132 SEG[61] 1102 -378

93 SEG[22] -1043 -378 133 SEG[62] 1157 -378

94 SEG[23] -988 -378 134 SEG[63] 1212 -378

95 SEG[24] -933 -378 135 SEG[64] 1267 -378

96 SEG[25] -878 -378 136 SEG[65] 1322 -378

97 SEG[26] -823 -378 137 SEG[66] 1377 -378

98 SEG[27] -768 -378 138 SEG[67] 1432 -378

99 SEG[28] -713 -378 139 SEG[68] 1487 -378

100 SEG[29] -658 -378 140 SEG[69] 1542 -378

101 SEG[30] -603 -378 141 SEG[70] 1597 -378

102 SEG[31] -548 -378 142 SEG[71] 1652 -378

103 SEG[32] -493 -378 143 SEG[72] 1707 -378

104 SEG[33] -438 -378 144 SEG[73] 1762 -378

105 SEG[34] -383 -378 145 SEG[74] 1817 -378

106 SEG[35] -328 -378 146 SEG[75] 1872 -378

107 SEG[36] -273 -378 147 SEG[76] 1927 -378

108 SEG[37] -218 -378 148 SEG[77] 1982 -378

109 SEG[38] -163 -378 149 SEG[78] 2037 -378

110 SEG[39] -108 -378 150 SEG[79] 2092 -378

111 SEG[40] -53 -378 151 SEG[80] 2147 -378

112 SEG[41] 2 -378 152 NC 2202 -378

113 SEG[42] 57 -378 153 NC 2518 -350

114 SEG[43] 112 -378 154 NC 2518 -295

115 SEG[44] 167 -378 155 NC 2518 -240

116 SEG[45] 222 -378 156 NC 2518 -185

117 SEG[46] 277 -378 157 NC 2518 -130

118 SEG[47] 332 -378 158 COM[13] 2518 -75

119 SEG[48] 387 -378 159 COM[14] 2518 -20

120 SEG[49] 442 -378 160 COM[15] 2518 35

V1.1 2003/12/24

8/72

ST7036

Pad No. Function X Y Pad No. Function X Y

161 COM[16] 2518 90

162 COM[17] 2518 145

163 COM[18] 2518 200

164 COM[19] 2518 255

165 COM[20] 2518 310

166 COM[21] 2518 365

167 COM[22] 2290 378

168 COM[23] 2235 378

169 COM[24] 2180 378

170 COMI2 2125 378

V1.1 2003/12/24

9/72

ST7036

 Block Diagram

OSC

XRESET

CLS

RS

RW

E

CSB

PSB

PSI2B

DB4 to
DB7

Reset
circuit

MPU

interface

Instruction

register(IR)

Instruction

decoder

Address

counter

Data

register

(DR)

CPG

(AC)

Display data

RAM

(DDRAM)

80x8 bits

Timing

generator

100-bit

shift

register

24-bit

shift

register

100-bit

latch

circuit

Common

signal
driver

Segment

signal
driver

COM1 to
COM16
(OR 24)

COMI

SEG1 to
SEG100

V0~V4

DB0 to
DB3

SHLC
SHLS

EXT

N3

OPR1,2
OPF1,2

VSS

VDD

Input/

output

buffer

Busy

flag

Character

generator RAM

(CGRAM)

64 bytes

ICON RAM

80 bits

Character

generator ROM

(CGROM)

10.240 bits

Parallel/serial converter

and

attribute circuit

controller

Cursor

and

blink

LCD drive

voltage

follower

Voltage
booster

circuit

VOUT

VIN

CAP1P
CAP1N

V1.1 2003/12/24

10/72

ST7036

 Pin Function

Name Number I/O Interfaced with Function

External reset pin. Only if the power on reset be used, the

XRESET 1 I MPU

RS 1 I MPU

R/W 1 I MPU

E 1 I MPU

CSB 1 I MPU

XRESET pin could be fixed to VDD.

Low active.

Select registers.
0: Instruction register (for write)

Busy flag & address counter (for read)
1: Data register (for write and read)

Select read or write(In parallel mode).
0: Write
1: Read

Starts data read/write. (“E” must connect to “VDD” when
serial mode is selected.)

Chip select in parallel mode and serial interface(Low
active). When the CSB in falling edge state ( in serial
interface ), the shift register and the counter are reset.

DB0~DB3 are four low order bi-directional data bus pins.
DB0~DB3 are used for data transfer and receive between
the MPU and the ST7036.
These pins are not used during 4-bit operation and must
connect to VDD.

DB0 to DB7 8 I/O MPU

Ext 1 I ITO option

PSB 1 I MPU

PSI2B 1 I ITO option

DB4~DB7 are four high order bi-directional data bus pins.
DB4~DB7 are used for data transfer and receive between
the MPU and the ST7036. DB7 can be used as a busy flag.
In serial interface mode DB7 is SI(input data),DB6 is
SCL(serial clock).

2

C interface DB7 is slave address A1, DB6 is slave

In I
address A0, DB5 DB4 DB3 are SDA –out, DB2 DB1 are
SDA-in and D0 is SCL.
SDA and SCL must connect to I2C bus ( I2C bus means that
connecting a resister between SDA/SCL and the power of
I2C bus ).

Extension instruction select:
0:enable extension instruction(add contrast/ICON/double
height font/ extension instruction)
1:disable extension instruction(compatible to ST7066U, but
without 5x11dot font)

Interface selection
0:serial mode
(“E” must connect to “VDD” when serial mode is selected.)
1:parallel mode(4/8 bit)
In I2C interface PSB must connect to VDD

PSB PSI2B Interface

0 0 No use

0 1 SI4

1 0 SI2 ( I2C )

1 1 Parallel 68

V1.1 2003/12/24

11/72

ST7036

Name Number I/O Interfaced with Function

Character generator select:

OPR1 OPR2 CGROM CGRAM

OPR1,OPR2 2 I ITO option

SHLC 1 I ITO option

SHLS 1 I ITO option

COM1 to

COM16

COMI2
COMI1

Seg1~Seg10

Seg91~Seg100

N3 1 I ITO option

SEG11 to

SEG90

OPF1,OPF2 2 I ITO option

CAP1P 2 - Power supply

CAP1N 2 - Power supply

VIN 2 - Power supply Input the voltage to booster

VOUT 4 - Power supply

V0 to V4 6 - Power supply

VDD,VSS 4,5 - Power supply VDD : 2.7V to 5.5V, VSS: 0V

CLS 1 I ITO option

OSC 1 I Oscillation

TEST1 1 I/O Test pin TEST1 must connect to VDD.

16 O LCD

1 O LCD

21 O LCD

80 O LCD Segment signals

0 0 240 8

0 1 250 6

1 0 248 8

1 1 256 0

Common signals direction select:
0:Com1~24←Row address 23~0(Invert)
1:Com1~24←Row address 0~23(Normal)

Segment signals direction select:
0:Seg1~100←Column address 99~0(Invert)
1:Seg1~100←Column address 0~99(Normal)

Common signals that are not used are changed
to non-selection waveform. COM9 to COM16
are non-selection waveforms at 1/8 or 1/9 duty factor

ICON common signals

Select “N3” pin for common or segment waveform output
(follow up table 2 defined)

1 line/2 line or 3 line select :
0:1 line/2 line SEG0~SEG100:normal
1:3 line COMI1,SEG1~SEG5,SEG97~SEG100 re-defined

The built-in voltage follower circuit selection

OPF1 OPF2 Bias select

0 0 Built-in voltage follower(only use at EXT=0)

0 1 Built-in bias resistor(3.3KΩ)

1 0 Built-in bias resistor(9.6KΩ)

1 1 External bias resistor select

For voltage booster circuit(V
External capacitor about 0.1u~4.7uf

DC/DC voltage converter. Connect a capacitor between this
terminal and VIN when the built-in booster is used.

Power supply for LCD drive
V0-Vss = 7V (Max)
Built-in/external Voltage follower circuit

Internal/External oscillation select
0:external clock
1:internal oscillation

When the pin input is an external clock, it must be input to
OSC.
When the on-chip oscillator is used, it must be connected
to VDD.

DD-VSS)

V1.1 2003/12/24

12/72

ST7036

 EXT option pin difference table

Mode

Difference

Booster Always OFF ON/OFF controlled by instruction

Can’t use the follower circuit

Bias (V0~V4)

Contrast adjust Control by external VR

ICON RAM Can’t be use RAM size has 80 bit width(S1~S80).

Only use external resistor or internal resistor(1/5
bias)

Normal mode (EXT=1)

( Instruction compatible to ST7066U )

Extension mode (EXT=0)

Follower or internal/external resistor selectable

1. Controlled by instruction with follower

2. Controlled by external VR with
internal/external resistor

Instruction Control normal instruction similar to ST7066U.

Double height font Only 5x8 font Can set 5x8 or 5x16 font

Control extension instruction for low power
consumption.

V1.1 2003/12/24

13/72

ST7036

 Function Description

z System Interface

This chip has all four kinds of interface type with MPU: 4-bit bus, 8-bit bus, serial and fast I
or 8-bit bus is selected by DL bit in the instruction register.

During read or write operation, two 8-bit registers are used. One is data register (DR), the other is instruction
register(IR).

The data register(DR) is used as temporary data storage place for being written into or read from
DDRAM/CGRAM/ICON RAM, target RAM is selected by RAM address setting instruction. Each internal
operation, reading from or writing into RAM, is done automatically. So to speak, after MPU reads DR data, the
data in the next DDRAM/CGRAM/ICON RAM address is transferred into DR automatically. Also after MPU writes
data to DR, the data in DR is transferred into DDRAM/CGRAM/ICON RAM automatically.

The Instruction register(IR) is used only to store instruction code transferred from MPU. MPU cannot use it to
read instruction data.

To select register, use RS input pin in 4-bit/8-bit bus mode.

RS R/W Operation

L L Instruction Write operation (MPU writes Instruction code into IR)

L H Read Busy Flag(DB7) and address counter (DB0 ~ DB6)
H L Data Write operation (MPU writes data into DR)
H H Data Read operation (MPU reads data from DR)

Table 1. Various kinds of operations according to RS and R/W bits.

2

C interface

I

It just only could write Data or Instruction to ST7036 by the IIC Interface.
It could not read Data or Instruction from ST7036 (except Acknowledge signal).

SCL: serial clock input
SDA_IN: serial data input
SDA_OUT: acknowledge response output

Slaver address could set from “0111100” to “0111111”.

2

The I

C interface send RAM data and executes the commands sent via the I2C Interface. It could send data in to the RAM.

2

The I

C Interface is two-line communication between different ICs or modules. The two lines are a Serial Data line (SDA)
and a Serial Clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor. Data transfer may be
initiated only when the bus is not busy.

B

IT TRANSFER

One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of
the clock pulse because changes in the data line at this time will be interpreted as a control signal. Bit transfer is illustrated
in Fig.1.

S

TART AND STOP CONDITIONS

Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the clock
is HIGH is defined as the START condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined
as the STOP condition (P). The START and STOP conditions are illustrated in Fig.2.

S

YSTEM CONFIGURATION

The system configuration is illustrated in Fig.3.

· Transmitter: the device, which sends the data to the bus

· Master: the device, which initiates a transfer, generates clock signals and terminates a transfer

· Slave: the device addressed by a master

· Multi-Master: more than one master can attempt to control the bus at the same time without corrupting the message

2

C interface. 4-bit bus

V1.1 2003/12/24

14/72

ST7036

· Arbitration: procedure to ensure that, if more than one master simultaneously tries to control the bus, only one is allowed to

do so and the message is not corrupted

· Synchronization: procedure to synchronize the clock signals of two or more devices.

A

CKNOWLEDGE

Acknowledge signal (ACK) is not BF signal in parallel interface.

Each byte of eight bits is followed by an acknowledge bit. The acknowledge bit is a HIGH signal put on the bus by the
transmitter during which time the master generates an extra acknowledge related clock pulse. A slave receiver which is
addressed must generate an acknowledge after the reception of each byte. A master receiver must also generate an
acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that
acknowledges must pull-down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during
the HIGH period of the acknowledge related clock pulse (set-up and hold times must be taken into consideration). A master
receiver must signal an end-of-data to the transmitter by not generating an acknowledge on the last byte that has been
clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master to generate a STOP
condition. Acknowledgement on the I

SDA
SCL

SDA

SCL

SDA

SCL

START condition STOP condition

MASTER

TRANSMITTER/

RECEIVER

2

C Interface is illustrated in Fig.4.

data line

stable;

data valid

Fig .1 Bit transfer

change

of data

allowed

SP

Fig .2 Definition of START and STOP conditions

SLAVE

RECEIVER (1)

0111100

Fig .3 System configuration

SLAVE

RECEIVER (2)

0111101

SLAVE

RECEIVER (3)

0111110

RECEIVER (4)

SLAVE

0111111

V1.1 2003/12/24

15/72

ST7036

I2C Interface protocol
The ST7036 supports command, data write addressed slaves on the bus.
Before any data is transmitted on the I
addresses (0111100 to 0111111) are reserved for the ST7036. The R/W is assigned to 0 for Write only.

2

C Interface protocol is illustrated in Fig.5.

The I

The sequence is initiated with a START condition (S) from the I2C Interface master, which is followed by the slave address.
All slaves with the corresponding address acknowledge in parallel, all the others will ignore the I
acknowledgement, one or more command words follow which define the status of the addressed slaves.
A command word consists of a control byte, which defines Co and RS, plus a data byte.
The last control byte is tagged with a cleared most significant bit (i.e. the continuation bit Co). After a control byte with a
cleared Co bit, only data bytes will follow. The state of the RS bit defines whether the data byte is interpreted as a command
or as RAM data. All addressed slaves on the bus also acknowledge the control and data bytes. After the last control byte,
depending on the RS bit setting; either a series of display data bytes or command data bytes may follow. If the RS bit is set
to logic 1, these display bytes are stored in the display RAM at the address specified by the data pointer. The data pointer is
automatically updated and the data is directed to the intended ST7036i device. If the RS bit of the last control byte is set to
logic 0, these command bytes will be decoded and the setting of the device will be changed according to the received
commands. Only the addressed slave makes the acknowledgement after each byte. At the end of the transmission the I
INTERFACE-bus master issues a STOP condition (P).

DATA OUTPUT

BY TRANSMITTER

DATA OUTPUT

BY RECEIVER

SCL FROM

MASTER

Fig .4 Acknowledgement on the IIC Interface

not acknowledge

acknowledge

1

S

START

condition

2

C Interface, the device, which should respond, is addressed first. Four 7-bit slave

2

89

clock pulse for

acknowledgement

2

C Interface transfer. After

2

C

V1.1 2003/12/24

16/72

ST7036

During write operation, two 8-bit registers are used. One is data register (DR), the other is instruction
register(IR).

The data register(DR) is used as temporary data storage place for being written into DDRAM/CGRAM/ICON
RAM, target RAM is selected by RAM address setting instruction. Each internal operation, writing into RAM, is
done automatically. So to speak, after MPU writes data to DR, the data in DR is transferred into
DDRAM/CGRAM/ICON RAM automatically.

The Instruction register(IR) is used only to store instruction code transferred from MPU. MPU cannot use it to
read instruction data.

To select register, use RS bit input in IIC interface.

z Busy Flag (BF)

When BF = "High”, it indicates that the internal operation is being processed. So during this time the next
instruction cannot be accepted. BF can be read, when RS = Low and R/W = High (Read Instruction Operation),
through DB7 port. Before executing the next instruction, be sure that BF is not High.

z Address Counter (AC)

Address Counter(AC) stores DDRAM/CGRAM/ICON RAM address, transferred from IR.
After writing into (reading from) DDRAM/CGRAM/ICON RAM, AC is automatically increased (decreased) by 1.
When RS = "Low" and R/W = "High", AC can be read through DB0 ~ DB6 ports.

Write mode

acknowledgement

from ST7036i

S 01111 1

slave address

0 A

1

0

R/W

slave address

Co

R
S

1 0

control byte

R

001111

W

acknowledgement

from ST7036i

2n>=0 bytes

command word

/

A

data byte

C

R

000000

S

o

control byte

acknowledgement

from ST7036i

R

0

A

S

Co

acknowledgement

from ST7036i

control byte

1 byte

D

D6D5D4D3D2D1D

7

data byte

A

n>=0 bytes

MSB.......................LSB

0

data byte

Fig .5 IIC Interface protocol

Last control byte to be sent. Only a stream of data bytes is allowed to follow.

0

Co

This stream may only be terminated by a STOP condition.

1 Another control byte will follow the data byte unless a STOP condition is received.

RS R/W Operation

L L Instruction Write operation (MPU writes Instruction code into IR)

H L Data Write operation (MPU writes data into DR)

Table 2. Various kinds of operations according to RS and R/W bits.

acknowledgement

from ST7036i

A P

V1.1 2003/12/24

17/72

ST7036

z Display Data RAM (DDRAM)

Display data RAM (DDRAM) stores display data represented in 8-bit character codes. Its extended capacity is 80
x 8 bits, or 80 characters. The area in display data RAM (DDRAM) that is not used for display can be used as
general data RAM. See Figure 6 for the relationships between DDRAM addresses and positions on the liquid
crystal display.

The DDRAM address (A

¾ 1-line display (N3=0,N = 0) (Figure 7)

When there are fewer than 80 display characters, the display begins at the head position. For
example, if using only the ST7036, 20 characters are displayed. See Figure 7.
When the display shift operation is performed, the DDRAM address shifts. See Figure 8.

DD ) is set in the address counter (AC) as hexadecimal.

High order bits Low order bits

AC6 AC5 AC4 AC3 AC2 AC1 AC0

Fig. 6 DDRAM Address

Display Position (digit)

123456 787980

DDRAM Address

Display Position

DDRAM Address

00 01 02 03 04 05 ........ 4D 4E 4F

Fig. 7 1-Line Display

1234 20

00 01 02 03 .... 13

Example : DDRAM Address 4F

1 0 0 1 1 1 1

For Shift Left

For Shift Right

Fig. 8 1-Line by 20-Character Display Example

V1.1 2003/12/24

00 01 02 .... 124F

18/72

1401 02 03 04 ....

ST7036

¾ 2-line display (N3=0,N = 1) (Figure 9)

Case 1: When the number of display characters is less than 40 x 2 lines, the two lines are displayed from the
head. Note that the first line end address and the second line start address are not consecutive. For example,
when just the ST7036 is used, 20 characters x 2 lines are displayed. See Figure 9.
When display shift operation is performed, the DDRAM address shifts. See Figure 10.

Display Position

123456 383940

Display
Position

DDRAM
Address

DDRAM
Address
(hexadecimal)

12345678 17181920

00 01 02 03 04 05 06 07

40 41 42 43 44 45 46 47

00 01 02 03 04 05 ........ 25 26 27

40 41 42 43 44 45 ........ 65 66 67

Fig. 9 2-Line Display

……………

……………

10 11 12 13

50 51 52 53

For Shift
Left

For Shift
Right

0801 02 03 04 05 06 07

4841 42 43 44 45 46 47

00 01 02 03 04 05 0627

40 41 42 43 44 45 4667

Fig. 10 2-Line by 20-Character Display Example

……………

……………

……………

……………

11 12 13 14

5451 52 53

0F 10 11 12

4F 50 51 52

V1.1 2003/12/24

19/72

ST7036

¾ 3-line display (N3=1,N =1) (Figure 11)

Case 1: When the number of display characters is less than 16 x 3 lines, the tree lines are displayed from the
head. For example, when just the ST7036 is used, 16 characters x 3 lines are displayed. See Figure 11.
When display shift operation is performed, the DDRAM address shifts. See Figure 12.

Display Position

123456 141516

DDRAM
Address
(hexadecimal)

Display Position

DDRAM
Address
(hexadecimal)

00 01 02 03 04 05 ........ 0D 0E 0F

10 11 12 13 14 15 ........ 1D 1E 1F

20 21 22 23 24 25 ........ 2D 2E 2F

Fig. 11 3-Line Display

123456 141516

00 01 02 03 04 05 ........ 0D 0E 0F

10 11 12 13 14 15 ........ 1D 1E 1F

20 21 22 23 24 25 ........ 2D 2E 2F

123456 141516

01 02 03 04 05 06 ........ 0E 0F 00

For Shift Left

11 12 13 14 15 16 ........ 1E 1F 10

21 22 23 24 25 26 ........ 2E 2F 20

123456 141516

0F 00 01 02 03 04 ........ 0C 0D 0E

For Shift Right

1F 10 11 12 13 14 ........ 1C 1D 1E

2F 20 21 22 23 24 ........ 2C 2D 2E

Fig. 12 3-Line Display

V1.1 2003/12/24

20/72

ST7036

z Character Generator ROM (CGROM)

The character generator ROM generates 5 x 8 dot character patterns from 8-bit character codes. It can generate
240/250/248/256 5 x 8 dot character patterns(select by OPR1/2 ITO pin). User-defined character patterns are
also available by mask-programmed ROM.

z Character Generator RAM (CGRAM)

In the character generator RAM, the user can rewrite character patterns by program. For 5 x 8 dots, eight
character patterns can be written.

Write into DDRAM the character codes at the addresses shown as the left column of Table 5 to show the
character patterns stored in CGRAM.

See Table 5 for the relationship between CGRAM addresses and data and display patterns. Areas that are not
used for display can be used as general data RAM.

z ICON RAM
In the ICON RAM, the user can rewrite icon pattern by program.
There are totally 80 dots for icon can be written.
See Table 6 for the relationship between ICON RAM address and data and the display patterns.

z Timing Generation Circuit

The timing generation circuit generates timing signals for the operation of internal circuits such as
DDRAM, CGROM and CGRAM. RAM read timing for display and internal operation timing by MPU
access are generated separately to avoid interfering with each other. Therefore, when writing data to
DDRAM, for example, there will be no undesirable interference, such as flickering, in areas other than
the display area.

z LCD Driver Circuit(N3=0)

LCD Driver circuit has 17 common and 100 segment signals for LCD driving. Data from CGRAM/CGROM/ICON
is transferred to 100 bit segment latch serially, and then it is stored to 100 bit shift latch. When each common is
selected by 17 bit common register, segment data also output through segment driver from 100 bit segment
latch. In case of 1-line display mode, COM1 ~ COM8(with COMI) have 1/9 duty, and in 2-line mode, COM1 ~
COM16(with COMI) have 1/17 duty ratio.

z LCD Driver Circuit(N3=1)

LCD Driver circuit has 25 common and 80 segment signals for LCD driving. Data from CGRAM/CGROM/ICON
is transferred to 80 bit segment latch serially, and then it is stored to 80 bit shift latch. When each common is
selected by 25 bit common register, segment data also output through segment driver from 80 bit segment latch.
In case of 3-line display mode, COM1 ~ COM24(with COMI) have 1/25 duty.

COM/SEG Output pins

N3 COMI1

VSS COMI1

VDD NC

COM

[1:8]

COM

[1:8]

COM

[5:12]

z Cursor/Blink Control Circuit

It can generate the cursor or blink in the cursor/blink control circuit. The cursor or the blink appears in the digit at
the display data RAM address set in the address counter.

SEG
[1:5]
SEG
[1:5]

COM[4:1]

+ COMI1

SEG

[6:10]

SEG

[6:10]

NC

SEG

[11:90]

SEG

[11:90]

SEG

[1:80]

Table 3. COM/SEG output define

SEG

[91:96]

SEG

[91:96]

NC

SEG

[97:100]

SEG

[97:100]

COM

[13:16]

COM

[9:16]

COM

[9:16]

COM

[17:24]

COMI2

COMI2

COMI2

V1.1 2003/12/24

21/72

ST7036

Table 4 Correspondence between Character Codes and Character Patterns

V1.1 2003/12/24

22/72

ST7036

CGRAM/CGROM arrangement with (OPR1, OPR2)=

V1.1 2003/12/24

23/72

ST7036

Character Code

(DDRAM Data)

b7 b6 b5 b4 b3 b2 b1 b0 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0

0 0 0 0 0 0 1 1 1 1 1
0 0 0 0 0 1 0 0 1 0 0
0 0 0 0 1 0 0 0 1 0 0

0 0 0 0 -

0 0 0 0 -

Table 5 Relationship between CGRAM Addresses, Character Codes (DDRAM) and Character

Notes:

1. Character code bits 0 to 2 correspond to CGRAM address bits 3 to 5 (3 bits: 8 types).

2. CGRAM address bits 0 to 2 designate the character pattern line position. The 8th line is the cursor position

and its display is formed by a logical OR with the cursor. Maintain the 8th line data, corresponding to the

cursor display position, at 0 as the cursor display. If the 8th line data is 1, 1 bits will light up the 8th line

regardless of the cursor presence.

3. Character pattern row positions correspond to CGRAM data bits 0 to 4 (bit 4 being at the left).

4. As shown Table 5, CGRAM character patterns are selected when character code bits 4 to 7 are all 0.

However, since character code bit 3 has no effect, the R display example above can be selected by either

character code 00H or 08H.

5. “1” for CGRAM data corresponds to display selection and “0” to non-selection,“-“ Indicates no effect.

6. Different OPR1/2 ITO option can select different CGRAM size.

0 0 0 0 1 1 0 0 1 0 0
0 0 0 1 0 0 0 0 1 0 0
0 0 0 1 0 1 0 0 1 0 0
0 0 0 1 1 0 0 0 1 0 0
0 0 0
0 0 1 0 0 0 1 1 1 1 0
0 0 1 0 0 1 1 0 0 0 1
0 0 1 0 1 0 1 0 0 0 1
0 0 1 0 1 1 1 1 1 1 0
0 0 1 1 0 0 10 1 0 0
0 0 1 1 0 1 10 0 1 0
0 0 1 1 1 0 1 0 0 0 1
0 0 1

CGRAM

Address

000

111

001

111

patterns (CGRAM Data)

Character Patterns

(CGRAM Data)

---

0 0 0 0 0

---

0 0 0 0 0

V1.1 2003/12/24

24/72

ST7036

When SHLS=1, ICON RAM map refer below table

ICON address

D7 D6 D5 D4 D3 D2 D1 D0

00H - - - S1 S2 S3 S4 S5

01H - - - S6 S7 S8 S9 S10

02H - - - S11 S12 S13 S14 S15

03H - - - S16 S17 S18 S19 S20

04H - - - S21 S22 S23 S24 S25

05H - - - S26 S27 S28 S29 S30

06H - - - S31 S32 S33 S34 S35

07H - - - S36 S37 S38 S39 S40

08H - - - S41 S42 S43 S44 S45

09H - - - S46 S47 S48 S49 S50

0AH - - - S51 S52 S53 S54 S55

0BH - - - S56 S57 S58 S59 S60

0CH - - - S61 S62 S63 S64 S65

0DH - - - S66 S67 S68 S69 S70

0EH - - - S71 S72 S73 S74 S75

0FH - - - S76 S77 S78 S79 S80

When SHLS=0, ICON RAM map refer below table

ICON address

D7 D6 D5 D4 D3 D2 D1 D0

ICON RAM bits

ICON RAM bits

00H - - - S80 S79 S78 S77 S76

01H - - - S75 S74 S73 S72 S71

02H - - - S70 S69 S68 S67 S66

03H - - - S65 S64 S63 S62 S61

04H - - - S60 S59 S58 S57 S56

05H - - - S55 S54 S53 S52 S51

06H - - - S50 S49 S48 S47 S46

07H - - - S45 S44 S43 S42 S41

08H - - - S40 S39 S38 S37 S36

09H - - - S35 S34 S33 S32 S31

0AH - - - S30 S29 S28 S27 S26

0BH - - - S25 S24 S23 S22 S21

0CH - - - S20 S19 S18 S17 S16

0DH - - - S15 S14 S13 S12 S11

0EH - - - S10 S9 S8 S7 S6

0FH - - - S5 S4 S3 S2 S1

Table 6 ICON RAM map

When ICON RAM data is filled the corresponding position displayed is described as the following table.

V1.1 2003/12/24

25/72

ST7036

 Instructions

There are four categories of instructions that:

z Designate ST7036 functions, such as display format, data length, etc.
z

Set internal RAM addresses

z

Perform data transfer with internal RAM

z

Others

instruction table at “Normal mode”

¾

(when “EXT” option pin connect to V

Instruction Code

Instruction

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Clear
Display

Return
Home

Entry Mode
Set

Display
ON/OFF

Cursor or
Display Shift

0 0 0 0 0 0 0 0 0 1

0 0 0 0 0 0 0 0 1 X

0 0 0 0 0 0 0 1 I/D S

0 0 0 0 0 0 1 D C B

0 0 0 0 0 1 S/C R/L X X

DD, the instruction set follow below table)

Description

Write "20H" to DDRAM. and set
DDRAM address to "00H" from AC

Set DDRAM address to "00H" from
AC and return cursor to its original
position if shifted. The contents of
DDRAM are not changed.

Sets cursor move direction and
specifies display shift. These
operations are performed during
data write and read.

D=1:entire display on
C=1:cursor on
B=1:cursor position on

S/C and R/L:
Set cursor moving and display shift
control bit, and the direction, without
changing DDRAM data.

Instruction

Execution Time

OSC=
380kHz

26.3 µs 18.5 µs 14.3 µs

26.3 µs 18.5 µs 14.3 µs

26.3 µs 18.5 µs 14.3 µs

1.08
ms

1.08
ms

OSC=
540kHz

0.76
ms

0.76
ms

OSC=
700kHz

0.59
ms

0.59
ms

Function Set 0 0 0 0 1 DL N X X X

Set CGRAM 0 0 0 1 AC5 AC4 AC3 AC2 AC1 AC0

Set DDRAM
Address

0 0 1 AC6 AC5 AC4 AC3 AC2 AC1 AC0

Read Busy
Flag and

0 1 BF AC6 AC5 AC4 AC3 AC2 AC1 AC0

Address

Write Data
to RAM

Read Data
from RAM

1 0 D7 D6 D5 D4 D3 D2 D1 D0

1 1 D7 D6 D5 D4 D3 D2 D1 D0

DL: interface data is 8/4 bits
N: number of line is 2/1

Set CGRAM address in address
counter

Set DDRAM address in address
counter

Whether during internal operation or
not can be known by reading BF.
The contents of address counter
can also be read.

Write data into internal RAM
(DDRAM/CGRAM)

Read data from internal RAM
(DDRAM/CGRAM)

26.3 µs 18.5 µs 14.3 µs

26.3 µs 18.5 µs 14.3 µs

26.3 µs 18.5 µs 14.3 µs

0 0 0

26.3 µs 18.5 µs 14.3 µs

26.3 µs 18.5 µs 14.3 µs

Note:
Be sure the ST7036 is not in the busy state (BF = 0) before sending an instruction from the MPU to the ST7036.
If an instruction is sent without checking the busy flag, the time between the first instruction and next instruction
will take much longer than the instruction time itself. Refer to Instruction Table for the list of each instruction
execution time.

V1.1 2003/12/24

26/72

ST7036

¾ instruction table at “Extension mode”

(when “EXT” option pin connect to VSS, the instruction set follow below table)

Instruction Code

Instruction

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Clear
Display

Return
Home

Entry Mode
Set

Display
ON/OFF

0 0 0 0 0 0 0 0 0 1

0 0 0 0 0 0 0 0 1 x

0 0 0 0 0 0 0 1 I/D S

0 0 0 0 0 0 1 D C B

Function Set 0 0 0 0 1 DL N DH IS2 IS1

Write "20H" to DDRAM. and set
DDRAM address to "00H" from AC

Set DDRAM address to "00H" from
AC and return cursor to its original
position if shifted. The contents of
DDRAM are not changed.

Sets cursor move direction and
specifies display shift. These
operations are performed during
data write and read.

D=1:entire display on
C=1:cursor on
B=1:cursor position on

DL: interface data is 8/4 bits
N: number of line is 2/1
DH: double height font
IS[2:1]: instruction table select

Description

Instruction

Execution Time

OSC=
380kHz

26.3 µs 18.5 µs 14.3 µs

26.3 µs 18.5 µs 14.3 µs

26.3 µs 18.5 µs 14.3 µs

1.08
ms

1.08
ms

OSC=
540kHz

0.76
ms

0.76
ms

OSC=
700kHz

0.59
ms

0.59
ms

Set DDRAM
Address

Read Busy
Flag and
Address

Write Data
to RAM

Read Data
from RAM

0 0 1 AC6 AC5 AC4 AC3 AC2 AC1 AC0

0 1 BF AC6 AC5 AC4 AC3 AC2 AC1 AC0

1 0 D7 D6 D5 D4 D3 D2 D1 D0

1 1 D7 D6 D5 D4 D3 D2 D1 D0

Set DDRAM address in address
counter

Whether during internal operation or
not can be known by reading BF.
The contents of address counter
can also be read.

Write data into internal RAM
(DDRAM/CGRAM/ICONRAM)

Read data from internal RAM
(DDRAM/CGRAM/ICONRAM)

26.3 µs 18.5 µs 14.3 µs

0 0 0

26.3 µs 18.5 µs 14.3 µs

26.3 µs 18.5 µs 14.3 µs

V1.1 2003/12/24

27/72

ST7036

Instruction table 0(IS[2:1]=[0,0])

Cursor or
Display Shift

Set CGRAM 0 0 0 1 AC5 AC4 AC3 AC2 AC1 AC0

Bias Set

Set ICON
Address

Power/ICON
Control/
Contrast Set

Follower
Control

Contrast Set

0 0 0 0 0 1 S/C R/L X X

Instruction table 1(IS[2:1]=[0,1])

0 0

0 0

0 0 0 1 0 1 Ion Bon C5 C4

0 0

0 0

0 0 0 1 BS 1 0 FX

0 1 0 0 AC3 AC2 AC1 AC0

0 1 1 0 Fon

0 1 1 1 C3 C2 C1 C0

Rab2Rab1Rab

0

S/C and R/L:
Set cursor moving and display shift
control bit, and the direction, without
changing DDRAM data.

Set CGRAM address in address
counter

BS=1:1/4 bias
BS=0:1/5 bias
FX: fixed on high in 3-line
application and fixed on low in other
applications.

Set ICON address in address
counter.

Ion: ICON display on/off
Bon: set booster circuit on/off
C5,C4: Contrast set for internal
follower mode.

Fon: set follower circuit on/off
Rab2~0:
select follower amplified ratio.

Contrast set for internal follower
mode.

26.3 µs 18.5 µs 14.3 µs

26.3 µs 18.5 µs 14.3 µs

26.3 µs 18.5 µs 14.3 µs

26.3 µs 18.5 µs 14.3 µs

26.3 µs 18.5 µs 14.3 µs

26.3 µs 18.5 µs 14.3 µs

26.3 µs 18.5 µs 14.3 µs

Instruction table 2(IS[2:1]=[1,0])

Double
Height
Position

0 0 0 0 0 1 UD X x x UD: Double height position select

Select

Reserved 0 0 0 1 X X X X X X Do not use (reserved for test)

Instruction table 3(IS[2:1]=[1,1]):Do not use (reserved for test)

26.3 µs 18.5 µs 14.3 µs

26.3 µs 18.5 µs 14.3 µs

V1.1 2003/12/24

28/72

ST7036

 Instruction Description

z Clear Display

R/WRS DB6DB7 DB4DB5 DB2DB3 DB0DB1

00 00 00 00 10

Clear all the display data by writing "20H" (space code) to all DDRAM address, and set DDRAM address to

"00H" into AC (address counter). Return cursor to the original status, namely, bring the cursor to the left edge

on first line of the display. Make entry mode increment (I/D = "1").

z Return Home

R/WRS DB6DB7 DB4DB5 DB2DB3 DB0DB1

00 00 00 00 X1

Return Home is cursor return home instruction. Set DDRAM address to "00H" into the address counter.

Return cursor to its original site and return display to its original status, if shifted. Contents of DDRAM does

not change.

z Entry Mode Set

R/WRS DB6DB7 DB4DB5 DB2DB3 DB0DB1

00 00 00 10 SI/D

Set the moving direction of cursor and display.

¾

I/D : Increment / decrement of DDRAM address (cursor or blink)

When I/D = "High", cursor/blink moves to right and DDRAM address is increased by 1.

When I/D = "Low", cursor/blink moves to left and DDRAM address is decreased by 1.

* CGRAM operates the same as DDRAM, when read from or write to CGRAM.

¾ S: Shift of entire display

When DDRAM read (CGRAM read/write) operation or S = "Low", shift of entire display is not performed. If

S = "High" and DDRAM write operation, shift of entire display is performed according to I/D value (I/D =

"1" : shift left, I/D = "0" : shift right).

S I/D Description

H H Shift the display to the left

H L Shift the display to the right

V1.1 2003/12/24

29/72

ST7036

z Display ON/OFF

R/WRS DB6DB7 DB4DB5 DB2DB3 DB0DB1

00 00 00 D1 BC

Control display/cursor/blink ON/OFF 1 bit register.

¾ D : Display ON/OFF control bit

When D = "High", entire display is turned on.

When D = "Low", display is turned off, but display data is remained in DDRAM.

¾ C : Cursor ON/OFF control bit

When C = "High", cursor is turned on.

When C = "Low", cursor is disappeared in current display, but I/D register remains its data.

¾ B : Cursor Blink ON/OFF control bit

When B = "High", cursor blink is on, that performs alternate between all the high data and display

character at the cursor position.

When B = "Low", blink is off.

Alternating

display

Every

64 frames

Cursor

z Cursor or Display Shift

R/WRS DB6DB7 DB4DB5 DB2DB3 DB0DB1

00 00 10 R/LS/C XX

S/C: Screen/Cursor select bit

¾

When S/C=”High”, Screen is controlled by R/L bit.

When S/C=”Low”, Cursor is controlled by R/L bit.

¾ R/L: Right/Left

When R/L=”High”, set direction to right.

When R/L=”Low”, set direction to left.

Without writing or reading of display data, shift right/left cursor position or display. This instruction is used to

correct or search display data. During 2-line mode display, cursor moves to the 2nd line after 40th digit of 1st

line. Note that display shift is performed simultaneously in all the line. When displayed data is shifted

repeatedly, each line shifted individually. When display shift is performed, the contents of address counter are

not changed.

S/C R/L Description AC Value

L L Shift cursor to the left AC=AC-1

L H Shift cursor to the right AC=AC+1

H L Shift display to the left. Cursor follows the display shift AC=AC

H H Shift display to the right. Cursor follows the display shift AC=AC

V1.1 2003/12/24

30/72

ST7036

z Function Set

R/WRS DB6DB7 DB4DB5 DB2DB3 DB0DB1

00 00 DL1 DHN IS1IS2

DL : Interface data length control bit

¾

When DL = "High", it means 8-bit bus mode with MPU.

When DL = "Low", it means 4-bit bus mode with MPU. So to speak, DL is a signal to select

8-bit or 4-bit bus mode.

When 4-bit bus mode, it needs to transfer 4-bit data by two times.

¾ N : Display line number control bit

When N = "High", 2-line display mode is set.

When N = "Low", it means 1-line display mode.

When “N3” option pin connect to VDD, N must set “N=1”.

¾ DH : Double height font type control bit

When DH = " High " and N= “Low”, display font is selected to double height mode(5x16 dot),RAM address

can only use 00H~27H.

When DH= “High” and N= “High”, it is forbidden.

When DH = " Low ", display font is normal (5x8 dot).

EXT option pin connect to

N DH

high

Display Lines

L L 1 5x8 1 5x8
L H 1 5x8 1 5x16
H L 2 5x8 2 5x8
H H 2 5x8 Forbidden

Character

Font

EXT option pin connect to

low

Display Lines

Character

Font

2 line mode normal display (DH=0/N=1)

1 line mode with double height font (DH=1/N=0)

V1.1 2003/12/24

31/72

ST7036

¾ IS[2:1]: instruction table select

When IS[2:1]=(0,0): normal instruction be selected(refer instruction table 0)

When IS[2:1]=(0,1):extension instruction be selected(refer instruction table 1 )

When IS[2:1]=(1,0):extension instruction be selected(refer instruction table 2 )

When IS[2:1]=(1,1):Do not use (reserved for test)

z Double height position set: IS[2:1]=(1,0)

R/WRS DB6DB7 DB4DB5 DB2DB3 DB0DB1

00 00 10 XUD XX

¾ UD: Select double height font display position of screen.(N3=VDD)

When UD = "High", double height font is show on Com1~Com16.

R/WRS DB6DB7 DB4DB5 DB2DB3 DB0DB1

00 10 00 AC2AC3 AC0AC1

When UD = "Low", double height font is show on Com9~Com24.

DH UD 2 LINES(N3=VSS) 3 LINES(N3=VDD)

H H Com1~Com16 Double Height

H L Com1~Com16 Double Height

Com1~Com16 Double Height
Com17~Com24 Normal Display
Com1~Com8 Normal Display
Com9~Com24 Double Height

L X Normal Display Normal Display

V1.1 2003/12/24

32/72

ST7036

3 Line mode normal display (DH = 0 / N = 1 / UD = don`t care )

COM1 ..8 is normal , COM9 .. 24 is a double height font (DH = 1 / N = 1 / UD = 0 )

COM17 ..24 is normal , COM1 .. 16 is a double height font (DH = 1 / N = 1 / UD = 1 )

V1.1 2003/12/24

33/72

ST7036

z Set CGRAM Address

R/WRS DB6DB7 DB4DB5 DB2DB3 DB0DB1

00 10 AC4AC5 AC2AC3 AC0AC1

Set CGRAM address to AC.

This instruction makes CGRAM data available from MPU.

z Set DDRAM Address

R/WRS DB6DB7 DB4DB5 DB2DB3 DB0DB1

00 AC61 AC4AC5 AC2AC3 AC0AC1

Set DDRAM address to AC.

This instruction makes DDRAM data available from MPU.

When 1-line display mode (N = 0), DDRAM address is from "00H" to "4FH".

In 2-line display mode (N = 1), DDRAM address in the 1st line is from "00H" to "27H", and

DDRAM address in the 2nd line is from "40H" to "67H".

In 3-line display mode (N3=1, N=1), DDRAM address in the 1st line is from “00H” to “OFH”, DDRAM in the

2nd line is from “10H” to “1FH”, and DDRAM in the 3rd line is from “20H” to “2FH”.

z Read Busy Flag and Address

R/WRS DB6DB7 DB4DB5 DB2DB3 DB0DB1

10 AC6BF AC4AC5 AC2AC3 AC0AC1

When BF = “High”, indicates that the internal operation is being processed. So during this time the next

instruction cannot be accepted.

The address Counter (AC) stores DDRAM/CGRAM addresses, transferred from IR.

After writing into (reading from) DDRAM/CGRAM, AC is automatically increased (decreased) by 1.

V1.1 2003/12/24

34/72

ST7036

z Write Data to CGRAM,DDRAM or ICON RAM

R/WRS DB6DB7 DB4DB5 DB2DB3 DB0DB1

01 D6D7 D4D5 D2D3 D0D1

Write binary 8-bit data to CGRAM,DDRAM or ICON RAM

The selection of RAM from DDRAM, CGRAM or ICON RAM, is set by the previous address set instruction

: DDRAM address set, CGRAM address set, ICON RAM address set. RAM set instruction can also determine

the AC

direction to RAM.

After write operation, the address is automatically increased/decreased by 1, according to

the entry mode.

z Read Data from CGRAM,DDRAM or ICON RAM

R/WRS DB6DB7 DB4DB5 DB2DB3 DB0DB1

11 D6D7 D4D5 D2D3 D0D1

Read binary 8-bit data from DDRAM/CGRAM./ICON RAM

The selection of RAM is set by the previous address set instruction. If address set instruction of RAM is not

performed before this instruction, the data that read first is invalid, because the direction of AC is not

determined. If you read RAM data several times without RAM address set instruction before read operation,

you can get correct RAM data from the second, but the first data would be incorrect, because there is no time

margin to transfer RAM data.

V1.1 2003/12/24

35/72

ST7036

z Bias Set

BS: bias selection

¾

When BS=”High”, the bias will be 1/4

When BS=”Low”, the bias will be 1/5

BS will be invalid when external bias resistors are used(OPF1=1,OPF2=1)

¾ FX: must be fixed on high in 3-line application and fixed on low in other applications.

z Set ICON RAM address

Set ICON RAM address to AC.

This instruction makes ICON data available from MPU.

When IS=1 at Extension mode,

The ICON RAM address is from "00H" to "0FH".

z Power/ICON control/Contrast set(high byte)

R/WRS DB6DB7 DB4DB5 DB2DB3 DB0DB1

00 10 10 B

Ion: set ICON display on/off

¾

When Ion = "High", ICON display on.

When Ion = "Low", ICON display off.

¾ Bon: switch booster circuit

Bon can only be set when internal follower is used (OPF1=0,OPF2=0).

When Bon = "High", booster circuit is turn on.

When Bon = "Low", booster circuit is turn off.

¾ C5,C4 : Contrast set(high byte)

C5,C4,C3,C2,C1,C0 can only be set when internal follower is used (OPF1=0,OPF2=0).They can more
precisely adjust the input reference voltage of V0 generator. The details please refer to the supply voltage
for LCD driver.

I

ON

ON

C4C5

V1.1 2003/12/24

36/72

ST7036

z Follower control

R/WRS DB6DB7 DB4DB5 DB2DB3 DB0DB1

00 10 01

Fon: switch follower circuit

¾

Fon can only be set when internal follower is used (OPF1=0,OPF2=0).

When Fon = "High", internal follower circuit is turn on.

When Fon = "Low", internal follower circuit is turn off.

Note that Fon must be set to “Low” if (OPF1, OPF2) is not (0,0).

¾ Rab2,Rab1,Rab0 : V0 generator amplified ratio

Rab2,Rab1,Rab0 can only be set when internal follower is used (OPF1=0,OPF2=0).They can adjust the

amplified ratio of V0 generator. The details please refer to the supply voltage for LCD driver.

z Contrast set(low byte)

Rab

F

ON

2

R/WRS DB6DB7 DB4DB5 DB2DB3 DB0DB1

Rab

1

Rab

0

00 10 11 C2C3 C0C1

C3,C2,C1,C0:Contrast set(low byte)

¾

C5,C4,C3,C2,C1,C0 can only be set when internal follower is used (OPF1=0,OPF2=0).They can more
precisely adjust the input reference voltage of V0 generator. The details please refer to the supply voltage
for LCD driver.

V1.1 2003/12/24

37/72

ST7036

 Reset Function

Initializing by Internal Reset Circuit

An internal reset circuit automatically initializes the ST7036 when the power is turned on. The

following instructions are executed during the initialization. The busy flag (BF) is kept in the busy state (BF = 1)

until the initialization ends. The busy state lasts for 40 ms after VDD rises to stable.

1. Display clear

2. Function set:

DL = 1; 8-bit interface data

N = 0; 1-line display

DH=0; normal 5x8 font

IS[2:1]=(0,0); use instruction table 0

3. Display on/off control:

D = 0; Display off

C = 0; Cursor off

B = 0; Blinking off

4. Entry mode set:

I/D = 1; Increment by 1

S = 0; No shift

5. 3 line: FX=1

1/2 line: FX=0

6. ICON control

Ion=0; ICON off

7. Power control

BS=0; 1/5bias

Bon=0; booster off

Fon=0; follower off

(C5,C4,C3,C2,C1,C0)=(1,0,0,0,0,0)

(Rab2,Rab1,Rab0)=(0,1,0)

8. Double Height Position Select

UD=0, double height font is show on Com9~Com24.

Note:
If the electrical characteristics conditions listed under the table Power Supply Conditions Using
Internal Reset Circuit are not met, the internal reset circuit will not operate normally and will fail
to initialize the ST7036.
When internal Reset Circuit not operate,ST7036 can be reset by XRESET pin from MPU control signal.

V1.1 2003/12/24

38/72

ST7036

 Initializing by Instruction

z 8-bit Interface (fosc=380kHz)
z

POW ER ON or external reset

W a it tim e >40 m S
After V D D sta ble

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 0 0 1 1 N DH IS 2 IS 1

W a it tim e >26 .3 μ S

Function set

Function set

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 0 0 1 1 N DH IS 2 IS 1

W a it tim e >26 .3 μ S

Intern al O S C frequen cy

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 0 0 0 1 BS F2 F1 F0

W a it tim e >26 .3 μ S

Contrast set

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 0 1 1 1 C3

W a it tim e >26 .3 μ S

C2 C1 C0

BF cannot be
checked before
this in struc tio n.

BF cannot be
checked before
this in struc tio n.

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 0 1 0 1 Ion

W a it tim e >26 .3 μ S

Bon C5 C4

Fo llow er co ntrol

Power/ICON/Contrast control

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 0 1 1 0 Fon

W a it tim e >26 .3 μ S

Rab2 Rab1 Rab0

D isp la y O N /O F F c o n tro l

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 0 0 0 0 1 D C B

W a it tim e >26 .3 μ S

Initia lizatio n en d

V1.1 2003/12/24

39/72

ST7036

Initial Program Code Example For 8051 MPU(8 Bit Interface):

¾

;--------------------------------------------------------------------------------­INITIAL_START:

CALL DELAY40mS
MOV A,#38H ;FUNCTION SET
CALL WRINS_NOCHK ;8 bit, N=1,5*7dot
CALL DELAY30uS
MOV A,#38H ;FUNCTION SET
CALL WRINS_NOCHK ;8 bit, N=1,5*7dot
CALL DELAY30uS
MOV A,#14H ;set bias
CALL WRINS_CHK
CALL DELAY30uS
MOV A,#78H ;Contrast set adjustment
CALL WRINS_CHK
CALL DELAY30uS
MOV A,#5EH ;Power/ICON/Contrast control
CALL WRINS_CHK
CALL DELAY30uS
MOV A,#6AH ;Follower control
CALL WRINS_CHK
CALL DELAY30uS
MOV A,#0CH ;DISPLAY ON
CALL WRINS_CHK
CALL DELAY30uS
MOV A,#01H ;CLEAR DISPLAY
CALL WRINS_CHK
CALL DELAY2mS
MOV A,#06H ;ENTRY MODE SET
CALL WRINS_CHK ;CURSOR MOVES TO RIGHT

CALL DELAY30uS
;--------------------------------------------------------------------------------­MAIN_START:

XXXX
XXXX
XXXX

XXXX
;---------------------------------------------------------------------------------
WRINS_CHK:

CALL CHK_BUSY
WRINS_NOCHK:

CLR RS ;EX: Port 3.0

CLR RW ;EX: Port 3.1

SETB E ;EX:Port 3.2

MOV P1,A ;EX:Port 1=Data Bus

CLR E

MOV P1,#FFH ;For Check Busy Flag

RET
;---------------------------------------------------------------------------------
CHK_BUSY: ;Check Busy Flag

CLR RS

SETB RW

SETB E

JB P1.7,$

CLR E

RET

V1.1 2003/12/24

40/72

ST7036

z 4-bit Interface (fosc=380kHz)

V1.1 2003/12/24

41/72

ST7036

Initial Program Code Example For 8051 MPU(4 Bit Interface):

¾

;------------------------------------------------------------------­INITIAL_START:

CALL DELAY40mS
MOV A,#30H ; FUNCTION SET
CALL WRINS_ONCE ; 8 bit, DL = 1
CALL DELAY2mS

MOV A,#30H ; FUNCTION SET
CALL WRINS_ONCE ; 8 bit, DL = 1
CALL DELAY30uS

MOV A,#30H ; FUNCTION SET
CALL WRINS_ONCE ; 8 bit, DL = 1
CALL DELAY30uS

CALL CHK_BUSY
MOV A,#20H ; FUNCTION SET
CALL WRINS_ONCE ; 4 bit, DL = 0
CALL DELAY30uS

MOV A,#29H ; FUNCTION SET
CALL WRINS_CHK ;
CALL DELAY30uS ; IS2 = 0, IS1 = 1

MOV A,#14H ;bias
CALL WRINS_CHK
CALL DELAY30uS

MOV A,#78H ;Contrast set
CALL WRINS_CHK
CALL DELAY30uS

MOV A,#5EH ;
CALL WRINS_CHK
CALL DELAY30uS

MOV A,#6AH ;Follower control
CALL WRINS_CHK
CALL DELAY30uS

MOV A,#0CH ;DISPLAY ON
CALL WRINS_CHK
CALL DELAY30uS

MOV A,#01H ;CLEAR DISPLAY
CALL WRINS_CHK
CALL DELAY2mS

MOV A,#06H ;ENTRY MODE SET
CALL WRINS_CHK

CALL DELAY30uS
;------------------------------------------------------------------­MAIN_START:

XXXX
XXXX
XXXX

4 bit, DL = 0, N = 1,

Power/ICON/Contrast

;-------------------------------------------------------------------
WRINS_CHK:

WRINS_NOCHK:

WRINS_ONCE:

;-------------------------------------------------------------------
CHK_BUSY: ;Check Busy Flag

$1

XXXX

CALL CHK_BUSY

PUSH A
ANL A,#F0H
CLR RS ;EX: Port 3.0
CLR RW ;EX: Port 3.1
SETB E ;EX: Port 3.2
MOV P1,A ;EX:Port1=Data Bus
CLR E
POP A
SWAP A

ANL A,#F0H
CLR RS
CLR RW
SETB E
MOV P1,A
CLR E
MOV P1,#FFH ;For Check Bus Flag
RET

PUSH A
MOV P1,#FFH

CLR RS
SETB RW
SETB E
MOV A,P1
CLR E
MOV P1,#FFH
CLR RS
SETB RW
SETB E
NOP
CLR E
JB A.7,$1
POP A

RET

V1.1 2003/12/24

42/72

ST7036

z Serial interface & IIC interface ( fosc = 380kHz )

POWER ON and external reset

Wait time >40mS
After VDD stable

Function set

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 0 0 1 1 N DH IS2 IS1

Wait time >26.3μS

Function set

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 0 0 1 1 N DH IS2 IS1

Wait time >26.3μS

Internal OSC frequency

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 0 0 0 1 BS F2 F1 F0

Wait time >26.3μS

Contrast set

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 0 1 1 1 C3 C2 C1 C0

Wait time >26.3μS

Power/ICON/Contrast control

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 0 1 0 1 Ion

Wait time >26.3μS

Bon C5 C4

Follower control

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 0 1 1 0 Fon

Wait time >200mS
(for power stable)

Rab2 Rab1 Rab0

Display ON/OFF control

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 0 0 0 0 1 D C B

Wait time >26.3μS

Initialization end

V1.1 2003/12/24

43/72

ST7036

¾ Initial Program Code Example For 8051 MPU ( Serial Interface ) :

;--------------------------------------------------------------------------------­INITIAL_START:

CALL HARDWARE_RESET

CALL DELAY40mS

MOV A,#38H ;FUNCTION SET

CALL WRINS_NOCHK ;8 bit, N=1,5*7dot

CALL DELAY30uS

MOV A,#39H ;FUNCTION SET

CALL WRINS_NOCHK ;8 bit, N=1,5*7dot,IS=1

CALL DELAY30uS

MOV A,#14H ;bias

CALL WRINS_NOCHK

CALL DELAY30uS

MOV A,#78H ;Contrast set

CALL WRINS_NOCHK

CALL DELAY30uS

MOV A,#5EH ;Power/ICON/Contrast control

CALL WRINS_NOCHK

CALL DELAY30uS

MOV A,#6AH ;Follower control

CALL WRINS_NOCHK

CALL DELAY200mS ;for power stable

MOV A,#0CH ;DISPLAY ON

CALL WRINS_NOCHK

CALL DELAY30uS

MOV A,#01H ;CLEAR DISPLAY

CALL WRINS_NOCHK

CALL DELAY2mS

MOV A,#06H ;ENTRY MODE SET

CALL WRINS_NOCHK ;CURSOR MOVES TO RIGHT

CALL DELAY30uS
;--------------------------------------------------------------------------------­MAIN_START:

XXXX
XXXX
XXXX
XXXX
.
.
.

;---------------------------------------------------------------------------------
WRINS_NOCHK:

PUSH 1
MOV R1,#8
CLR RS

$1

RLC A
MOV SI,C
SETB SCL
NOP
CLR SCL
DJNZ R1,$1
POP 1

CALL DLY1.5mS
RET

V1.1 2003/12/24

44/72

ST7036

 Interfacing to the MPU

The ST7036 can send data in two 4-bit operations/one 8-bit operation, serial 1 bit operation or fast

thus allowing interfacing with 4-bit, 8-bit or

I2C MPU.

I2C operation,

z For 4-bit interface data, only four bus lines (DB4 to DB7) are used for transfer. Bus lines DB0 to DB3

are disabled. The data transfer between the ST7036 and the MPU is completed after the 4-bit data has been

transferred twice. As for the order of data transfer, the four high order bits (for 8-bit operation, DB4 to DB7)

are transferred before the four low order bits (for 8-bit operation, DB0 to DB3). The busy flag must be

checked (one instruction) after the 4-bit data has been transferred twice. Two more 4-bit operations then

transfer the busy flag and address counter data.

¾ Example of busy flag check timing sequence

CSB

RS

R/W

E

Internal

operation

DB7

Intel 8051 interface(4 Bit)

¾

P1.0 to P1.3

Intel 8051 Serial ST7036

Functioning

IR7 IR3 AC3

Busy flag check Busy flag check Instruction writeInstruction write

4

P3.0
P3.1
P3.2

P3.3 CSB

Not

Busy

COM16/24

DB4 to DB7

RS
R/W
E

SEG100/80

AC3 IR3IR7

COM1 to

SEG1 to

16/24

100/80

V1.1 2003/12/24

45/72

ST7036

z For 8-bit interface data, all eight bus lines (DB0 to DB7) are used.

Example of busy flag check timing sequence

¾

CSB

RS

R/W

E

Internal

operation

DB7

¾ Intel 8051 interface(8 Bit)

P1.0 to P1.7

Intel 8051 Serial ST7036

Data

Instruction

write

P3.0
P3.1
P3.2

Functioning

Busy flag

check

8

BusyBusy Data

Busy flag

check

DB0 to DB7

RS
R/W
E
CSBP3.3

COM16/24

SEG100/80

Not

Busy

Busy flag

check

COM1 to

SEG1 to

16/24

100/80

Instruction

write

V1.1 2003/12/24

46/72

ST7036

For serial interface data, only two bus lines (DB6 to DB7) are used.

z

Example of timing sequence

¾

CSB

SI

D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2

SCL

1 2 3 4 5 6 7 8 9 10 11 12 13 14

RS

Intel 8051 interface ( Serial 4-line )

¾

P1.6 to P1.7

Intel 8051 Serial ST7036

P3.0
P3.3

COM1 to

2

SI , SCL

RS
CSB

COM16/24

SEG1 to

SEG100/80

16/24

100/80

V1.1 2003/12/24

47/72

ST7036

z For I

Example of timing sequence

¾

SDA

2

C interface data, all eight bus lines (DB0 to DB7) are used.

D7 D6 D5 D4 D3 D2 D1 D0

ACK

. . . . . . .

D0

ACK

SCL

Intel 8051 interface ( I

¾

123456789

2

C interface )

. . . . . .

V1.1 2003/12/24

48/72

ST7036

 Supply Voltage for LCD Drive

When external bias resistors are used

z

(OPF1=1,OPF2=1)

VCC (2.7~ 5.5V)

OPF1 OPF2

VOUT

VIN

CAP1P

CAP1N

VDD

V0

V1

V2

Vext

VR

R

R

V3

R

V4

R

VSS

1/4 bias

GND

z When built-in bias resistors(9.6KΩ) are used

(OPF1=1,OPF2=0)

VLCD

VCC(2.7~5.5V)

VCC (2.7~ 5.5V)

OPF1 OPF2

VOUT

VIN

CAP1P

CAP1N

1/5 bias

Vext

VDD

V0

V1

V2

V3

V4

VSS

Vext

VR

R

R

VLCD

R

R

GND

OPF1

VOUT

VIN

CAP1P

CAP1N

VDD

V0

V1

V2

V3

VR

VLCD

V4

OPF2

VSS

GND

V1.1 2003/12/24

49/72

ST7036

When built-in bias resistors(3.3KΩ) are used

z

(OPF1=0,OPF2=1)

OPF2
VOUT

VIN

CAP1P

CAP1N

VCC (2.7~ 5.5V)

VDD

V0

V1

V2

Vext

V3

V4

OPF1

VSS

GND

When built-in voltage followers with external Vout are used

z

(OPF1=0,OPF2=0 and instruction setting Bon=0,Fon=1)

VR

VLCD

Vext ≧ V0

VCC (2.7~ 5.5V)

VOUT

VIN

CAP1P

CAP1N

OPF1 OPF2

VDD

V0

V1

V2

V3

V4

VSS

Don't need to connect stable capacitor when
use internal follower circuit

VLCD

GND

V1.1 2003/12/24

50/72

ST7036

When built-in booster and voltage followers are used(OPF1=0,OPF2=0)

z

VIN

VOUT

CAP1P

CAP1N

VCC (2.7~ 3.5V)

VDD

V0

V1

V2

V3

V4

Don't need to connect stable capacitor when
use internal follower circuit

VOUT≦2xVDD

VDD=2.7~3.5V

VLCD

2 x step-up voltage relationships

VSS=0V

OPF1 OPF2

VSS

GND

Note:
Ensure V0 level stable, that must let |Vout-V0| over 0.5V(if panel size over 4.5”,the |Vout-V0| propose over 0.8V).

|Vout-V0|>0.5V(minimum)

Vout

V

V

CC

GND

DD

V

SS

(System side) (ST7036Side)

V

0

V1.1 2003/12/24

51/72

ST7036

¾ V0 voltage follower value calculation

Vout(≧V

DD)VDD

Vref

V0

V0=(1+

While Vref=V

Ra

V

SS

Rb

Rb
Ra

x

) Vref

α+36

x

DD (

100

C5 C4 C3 C2 C1 C0 α Rab2 Rab1 Rab0 1+Rb/Ra

0 0 0 0 0 0 0

0 0 0 0 0 1 1

0 0 0 0 1 0 2

:
:

1 1 1 1 0 1 61

1 1 1 1 1 0 62

1 1 1 1 1 1 63

:
:

0 0 0 1

0 0 1 1.25

0 1 0 1.5

0 1 1 1.8

1 0 0 2

1 0 1 2.5

1 1 0 3

1 1 1 3.75

8

)

7

6

5

4

3

2

1

0

1 3 5 7 9 111315171921232527293133353739414345474951535557596163

V0 level (Condition:Booster on, Follower on, VIN=3.5V, VDD=3.0V,Display off)

The recommended curve: follower = 04H

Notes:

1. Vout

≧V0 ≧V1 ≧V2 ≧V3 ≧V4 ≧Vss must be maintained.

2. If the calculation value of V0 is higher than Vout, the real V0 value will saturate to Vout.

3. internal built-in booster can only be used when OPF1=0,OPF2=0.

V1.1 2003/12/24

52/72

ST7036

8

7

6

5

4

3

2

1

0

0 2 4 6 8 10 12 14 1618 20 2224 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62

V0 level

The recommended curve: followe=01H

(Condition: VDD=5.0V, external Vout=7.0V)

Notes:

1. Vout ≧V0 ≧V1 ≧V2 ≧V3 ≧V4 ≧Vss must be maintained.

2. If the calculation value of V0 is higher than Vout, the real V0 value will saturate to Vout.

3. internal built-in booster can only be used when OPF1=0,OPF2=0.

V1.1 2003/12/24

53/72

ST7036

 AC Characteristics

z 68 Interface

RS

R/W

tAW6 tAH6

CSB

tCYC6

tEWH

tEWL

E

tDS6 tDH6

D0 to D7

(Write)

tACC6 tOH6

D0 to D7

(Read)

(Ta =25°C )

Item Signal Symbol Condition

VDD=2.7 to 4.5V

Rating

Min. Max. Min. Max.

VDD=4.5 to 5.5V

Rating

Units

Address hold time RS tAH6

Address setup time RS tAW6

System cycle time RS tCYC6 —

Data setup time D0 to D7 tDS6

Data hold time D0 to D7 tDH6

Access time D0 to D7 tACC6

Output disable time D0 to D7 tOH6

Enable H pulse time E tEWH

Enable L pulse time E tEWL

Note: All timing is specified using 20% and 80% of V

V1.1 2003/12/24

DD as the reference.

—

—

CL = 100 pF

— 200 - 120 -

— 150 - 130 -

54/72

20 - 20 -

20 - 20 -

400 - 280 -

100 - 80 -

40 - 20 -

- 500 - 400

300 - 150 -

ns

ns

ns

ns

ns

ns

ST7036

z Serial Interface

CSB

RS

tCSS tCSH

tSAS tSAH

tSCYC

tSLW

SCL

tSDS tSDH

SI

VDD=2.7 to 4.5V

Item Signal Symbol Condition

Min. Max. Min. Max.

Serial Clock Period

SCL “H” pulse width

SCL “L” pulse width

Address setup time

Address hold time

Data setup time

Data hold time

CS-SCL time CS

SCL

RS

SI

tSCYC

tSHW

tSLW
tSAS
tSAH
tSDS
tSDH
tCSS

—

—

—

—

tCSH

*1 All timing is specified using 20% and 80% of VDD as the standard.

200 - 100 -

20 - 20 -

160 - 120 -

10 - 10 -

250 - 150 -

10 - 10 -

10 - 20 -

20 - 20 -

350 - 200 -

Rating

tSHW

VDD=4.5 to 5.5V

Rating

(Ta = 25°C )

Units

ns

ns

ns

ns

V1.1 2003/12/24

55/72

ST7036

t

z I2C interface

SDA

SCL

SDA

tBUF

tLOW

tDH;STA

tr

tHD;DAT

tSU;STA

Item Signal Symbol Condition

tHIGH

tSU;DAT

tf

SU;STO

VDD=2.7 to 4.5V

Rating

Min. Max. Min. Max.

VDD=4.5 to 5.5V

Rating

( Ta = 25°C )

Units

SCL clock frequency f
SCL clock low period t
SCL clock high period
Data set-up time t

Data hold time

SCL,SDA rise time tr 20+0.1Cb300 20+0.1Cb 300

SCL,SDA fall time
Capacitive load represent by each bus

line
Setup time for a repeated START
condition

Start condition hold time

Setup time for STOP condition t

Bus free time between a Stop and
START condition

SCL

SDA

SCL,

SDA

C

SDA

SCL t

DC 300K DC 400 kHz

SCLK

2.5

LOW

t

HIGH

SU;DAT

t

HD:DAT

tf

— — 400 — 400 pf

b

t

— 0.6 — 0.6 — µs

SU;STA

t

— 1.8 — 1.0 — µs

HD;STA

— 0.6 — 0.6 — µs

SU;STO

— 1.3 — 1.3 — µs

BUF

—

—

—

0.6 — 0.6 —

1800 — 700 —

0 0.5 0 0.5 µs

20+0.1Cb300 20+0.1Cb 300

—

1.3

—

µs

ns

ns

V1.1 2003/12/24

56/72

ST7036

z Internal Power Supply Reset

z Hardware reset(XRESET)

2.7V/4.5V

0.2V 0.2V 0.2V

rcc

t

Notes:
 t

OFF compensates for the power oscillation period caused by momentary power supply

oscillations.

 Specified at 4.5V for 5V operation, and at 2.7V for 3V operation.
 For if 2.7V/4.5V is not reached during 3V/5V operation, internal reset circuit will not

operate normally.

tOFF

tOFF≧1mS0.1mS≦trcc≦10mS

2.7V/4.5V

0.2V

≦

tr 100nS

tL>100uS

V1.1 2003/12/24

57/72

ST7036

 Absolute Maximum Ratings

Characteristics Symbol Value

Power Supply Voltage VDD -0.3 to +7.0

LCD Driver Voltage V

Input Voltage VIN -0.3 to VDD+0.3

Operating Temperature TA -40oC to + 90oC

7.0- Vss to -0.3+Vss

LCD

Storage Temperature T

 DC Characteristics

( TA = 25℃ , VDD = 2.7 V)

Symbol Characteristics Test Condition Min. Typ. Max. Unit

VDD Operating Voltage - 2.7 - 4.5 V

V

LCD Voltage V0-Vss 2.7 - 7.0 V

LCD

VIN Power Supply - - - 3.5 V

ICC Power Supply Current

V

IH1

V

IL1

V

IH2

V

IL2

Input High Voltage

(Except OSC1)

Input Low Voltage

(Except OSC1)

Input High Voltage

(OSC1)

Input Low Voltage

(OSC1)

-55oC to + 125oC

STO

VDD=3.0V

(Use internal

booster/follower circuit)

-

- - 0.3 - 0.8 V

-

- - -

- 160 230 uA

0.7

VDD

0.7

VDD

- VDD V

- VDD V

0.2

VDD

V

VOH

VOL

R

COM

R

SEG

I

LEAK

I

PUP

Output High Voltage

(DB0 - DB7)

Output Low Voltage

(DB0 - DB7)

Common Resistance V

Segment Resistance V

Input Leakage

Current

IOH = -1.0mA

I

= 1.0mA - - 0.8 V

OL

= 4V, Id = 0.05mA - 2 20 KΩ

LCD

= 4V, Id = 0.05mA - 2 30 KΩ

LCD

VIN = 0V to VDD -1 - 1 µA

Pull Up MOS Current VDD = 3V 20 30 40 µA

0.7

VDD

- - V

fOSC Oscillation frequency VDD = 3V,1/17duty 350 540 1100 kHz

V1.1 2003/12/24

58/72

ST7036

 DC Characteristics

( TA = 25℃, VDD = 4.5 V)

Symbol Characteristics Test Condition Min. Typ. Max. Unit

VDD Operating Voltage - 4.5 - 5.5 V

V

LCD Voltage V0-Vss 2.7 - 7.0 V

LCD

VIN Power Supply - - - 3.5 V

ICC Power Supply Current

VDD=5.0V

(Use internal

booster/follower circuit)

- 240 340 µA

V

V

V

V

VOH

VOL

R

COM

R

SEG

I

LEAK

I

PUP

IH1

IL1

IH2

IL2

Input High Voltage

(Except OSC1)

Input Low Voltage

(Except OSC1)

Input High Voltage

(OSC1)

Input Low Voltage

(OSC1)

Output High Voltage

(DB0 - DB7)

Output Low Voltage

(DB0 - DB7)

Common Resistance V

Segment Resistance V

Input Leakage

Current

LCD

LCD

VIN = 0V to VDD -1 - 1 µA

-

- -0.3 - 0.8 V

-

- - - 1.0 V

IOH = -1.0mA

I

= 1.0mA - - 0.8 V

OL

= 4V, Id = 0.05mA - 2 20 KΩ

= 4V, Id = 0.05mA - 2 30 KΩ

Pull Up MOS Current VDD = 5V 65 95 125 µA

0.7

VDD

0.7

VDD

0.8

VDD

- VDD V

- VDD V

- VDD V

fOSC Oscillation frequency VDD = 5V,1/17duty 350 540 1100 kHz

V1.1 2003/12/24

59/72

ST7036

 LCD Frame Frequency

z 1/16 Duty(ST7066U normal mode); Assume the oscillation frequency is 540KHZ, 1 clock cycle time

= 1.85us, 1/16 duty; 1/5 bias,1 frame =1.85us x 200 x 16 = 5.92ms=168.9Hz(SHLC and SHLS connect

to High)

200 clocks

1 2 3 4 16 1 2 3 4 16 1 2 3 4 16

V0
V1
V2

COM1

COM2

V3
V4
Vss

V0
V1
V2

V3
V4
Vss

COM16

SEGx off

SEGx on

V0
V1
V2

V3
V4
Vss

V0
V1
V2

V3
V4
Vss

V0
V1
V2

V3
V4
Vss

1 frame

V1.1 2003/12/24

60/72

ST7036

z 1/17 Duty(Extension mode); Assume the oscillation frequency is 540KHZ, 1 clock cycle time =

1.85us, 1/17 duty; 1/5 bias,1 frame =1.85us x 200 x 17 = 6.29ms=159Hz(SHLC and SHLS connect to

High)

200 clocks

1 2 3 4 17 1 2 3 4 17 1 2 3 4 17

V0
V1
V2

COM1

COM2

V3
V4
Vss

V0
V1
V2

V3
V4
Vss

COM17

SEGx off

SEGx on

V0
V1
V2

V3
V4
Vss

V0
V1
V2

V3
V4
Vss

V0
V1
V2

V3
V4
Vss

1 frame

V1.1 2003/12/24

61/72

ST7036

z 1/8 Duty(ST7066U normal mode); Assume the oscillation frequency is 540KHZ, 1 clock cycle time =

1.85us, 1/8 duty; 1/4 bias,1 frame = 1.85us x 400 x 8 = 5.92ms=168.9Hz(SHLC and SHLS connect to
High)

400 clocks

1 2 3 4 8 1 2 3 4 8 1 2 3 4 8

V0
V1

COM1

COM2

COM8

V2
V3

V4
Vss

V0
V1

V2
V3

V4
Vss

V0
V1

V2
V3

V4
Vss

V0
V1

SEGx off

SEGx on

V1.1 2003/12/24

V2
V3

V4
Vss

V0
V1

V2
V3

V4
Vss

1 frame

62/72

ST7036

z 1/9 Duty(Extension mode); Assume the oscillation frequency is 540KHZ, 1 clock cycle time =

1.85us, 1/9 duty; 1/4 bias,1 frame = 1.85us x 400 x 9 = 6.66ms=150Hz(SHLC and SHLS connect to
High)

400 clocks

1 2 3 4 9 1 2 3 4 9 1 2 3 4 9

V0
V1

COM1

COM2

COM9

V2
V3

V4
Vss

V0
V1

V2
V3

V4
Vss

V0
V1

V2
V3

V4
Vss

V0
V1

SEGx off

SEGx on

V1.1 2003/12/24

V2
V3

V4
Vss

V0
V1

V2
V3

V4
Vss

1 frame

63/72

ST7036

1/25 Duty( Extension mode and 3-line ); Assume the oscillation frequency is 540KHZ, 1 clock cycle

z

time = 1.85us, 1/25 duty; 1/4 bias,1 frame = 1.85us x 160 x 25 = 7.40ms=135.1Hz(SHLC and SHLS
connect to High)

z

V0
V1

160 clocks

1 2 3 4 25 1 2 3 4 25 1 2 3 4 25

COM1

COM2

COM25

V2
V3

V4
Vss

V0
V1

V2
V3

V4
Vss

V0
V1

V2
V3

V4
Vss

V0
V1

SEGx off

SEGx on

V1.1 2003/12/24

V2
V3

V4
Vss

V0
V1

V2
V3

V4
Vss

1 frame

64/72

ST7036

 I/O Pad Configuration

Input PAD (No Pull up):
RS, R/W, XRESET, CSB,
PSB, OPFx, OPRx, SHLx,
CLS, EXT

VDD

PMOS

NMOS

VDD

VDD

PSB

PMOS

NMOS

PSB=1==>E(Floating)
PSB=0==>E(Pull up)

PMOS

VDD

VDD

PMOS

NMOS

VDD

Enable

PMOS

Data

NMOS

I/O PAD (Pull up):
DB0-DB5

V1.1 2003/12/24

65/72

ST7036

 LCD and ST7036 Connection

SHLC/SHLS ITO option pin can select at different direction for LCD panel

Com normal direction/Seg normal direction

z

3 line x 16 characters, SHLC=1 SHLS=1

Com normal direction/Seg reverse direction

z

3 line x 16 characters, SHLC=1, SHLS=0

Com reverse direction/Seg normal direction

z

3 line x 16 characters, SHLC=0, SHLS=1

Com reverse direction/Seg reverse direction

z

3 line x 16 characters, SHLC=0, SHLS=0

V1.1 2003/12/24

66/72

ST7036

 Application Circuit ( Normal mode )

¾ Use internal resistor(9.6K ohm) and contrast adjust with external VR.
¾ Booster always off.
¾ Has 240 character of CGROM.
¾ Internal oscillator.

Dot Matrix LCD Panel

Vext

VDD

VOUT
VIN

CAP1N
CAP1P

V0
V1
V2
V3
V4

Seg 1-80Com 1-24

ST7036

RS,R/W,E,CSB,DB0-DB7,XRESET

To MPU

VDD

CLS

SHLC

SHLS

N3

EXT
OPF1
OPF2

OPR1
OPR2

V1.1 2003/12/24

67/72

ST7036

 Application Circuit(Extension mode)

¾ Use internal follower circuit.
¾ Booster has 2 times pump.
¾ Has 240 character of CGROM.
¾ Internal oscillator.

Dot Matrix LCD Panel

Vext

VOUT
VIN

Seg 1-80Com 1-24

CLS

SHLC

SHLS

CAP1N
CAP1P

V0
V1
V2
V3
V4

ST7036

RS,R/W,E,CSB,DB0-DB7,XRESET

EXT
OPF1
OPF2

OPR1
OPR2

To MPU

z When the heavy load is applied, the dotted line part could be added.

VDD

N3

V1.1 2003/12/24

68/72

ST7036

 Application Circuit ( for glass layout )

z ST7036 over Glass,6800 serial 8bit interface, with booster and follower circuit on

V1.1 2003/12/24

69/72

ST7036

z ST7036 over Glass,6800 serial 4bit interface, with booster and follower circuit on

V1.1 2003/12/24

70/72

ST7036

z ST7036 over Glass, serial interface, with booster and follower circuit on

V1.1 2003/12/24

71/72

ST7036

z ST7036 over Glass, I2C interface, with booster and follower circuit on

V1.1 2003/12/24

72/72