ST ST7036 User Manual

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Sitronix ST7036

Preliminary Dot Matrix LCD Controller/Driver

 Features

z 5 x 8 dot matrix possible z Low power operation support:

-- 2.7 to 5.5V

z Range of LCD driver power

-- 2.7 to 7.0V

z 4-bit, 8-bit, serial or 400kbits/s fast I

MPU interface enabled

z 80 x 8-bit display RAM (80 characters max.) z 10,240-bit character generator ROM for a

total of 256 character fonts(max)

z 64 x 8-bit character generator RAM(max) z Support two display mode:

16-com x 100-seg and 80 ICON 24-com x 80-seg and 80 ICON

z 16 x 5 –bit ICON RAM(max)

C-bus

z Wide range of instruction functions:

Display clear, cursor home, display on/off, cursor on/off, display character blink, cursor shift, display shift, double height font

z Automatic reset circuit that initializes the

controller/driver after power on and external reset pin

z Internal oscillator(Frequency=540kHz) and

external clock

z Built-in voltage booster and follower circuit

(low power consumption )

z COM/SEG direction selectable z Multi-selectable for CGRAM/CGROM size z Instruction compatible to ST7066U and

KS0066U and HD44780

z Available in COG type

 Description

The ST7036 dot-matrix liquid crystal display controller and

driver LSI displays alphanumeric, Japanese kana characters, and symbols. It can be configured to drive a dot-matrix liquid crystal display under the control of a 4-/ 8-bit, serial or fast I the functions such as display RAM, character generator, and liquid crystal driver, required for driving a dot-matrix liquid crystal display are internally provided on one chip, a minimal system can be interfaced with this controller/driver.

The ST7036 character generator ROM is extended to generate 256 5x8dot character fonts for a total of 256 different character fonts. The low power supply (2.7V to

product Name

ST7036-0A 256 1 1 English / Japan/Europe

ST7036

C interface microprocessor. Since all

Character generato

ROM Size

- - - - -

6800-4bit / 8bit interface (without IIC interface)

5.5V) of the ST7036 is suitable for any portable battery-driven product requiring low power dissipation.

The ST7036 LCD driver consists of 17 common signal drivers and 100 segment signal drivers. And the second mode is consists of 25 common signal and 80 segment signal drivers. The maximum display RAM size can be either 80 characters in 1-line display or 40 characters in 2-line display or 16 characters in 3-line. A single ST7036 can display up to one 20-character line or two 20-character lines or three 16-character lines. No extra drivers can be cascaded.

OPR1 OPR2 Support Character

ST7036i

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Version Date Description

0.1a 2003/04/28 1st Edition

0.1b 2003/06/03

0.2a 2003/09/01 1. Include ST7036i

1.0 2003/10/24

1.1 2003/12/24

ST7036 Serial Specification Revision History

PAD Dimension: IC L mark location modified Chip Size X/Y modified

1. Add application circuit for 3 line display.

2. 4 bit interface program example modified.

1. Remove the instruction of frequency adjust.

2. Add the detail of CGRAM/CGROM arrangement.

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 Pad Dimensions

¾ Chip Size: 5190.0X910.0 µm

¾ Bump Pitch : 55 µm ( min )

¾ Bump Height : 17 µm ( typ. )

¾ Bump Size :

z Pad No.1~52 : 56 x 72 µm z Pad No.53~170 : 35 x 101 µm

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 Pad Location Coordinates(N3=0 1 line/2 line)

Pad No. Function X Y Pad No. Function X Y

1 XRESET 1859 393 41 CLS -1181 393

2 OSC 1783 393 42 CAP1N -1257 393

3 VDD 1707 393 43 CAP1N -1333 393

4 RS 1631 393 44 VOUT -1409 393

5 CSB 1555 393 45 VOUT -1485 393

6 RW 1479 393 46 V0 -1561 393

7 E 1403 393 47 V0 -1637 393

8 DB0 1327 393 48 V1 -1713 393

9 DB1 1251 393 49 V2 -1789 393

10 DB2 1175 393 50 V3 -1865 393

11 DB3 1099 393 51 V4 -1941 393

12 DB4 1023 393 52 NC -2017 393

13 DB5 947 393 53 COM[8] -2125 378

14 DB6 871 393 54 COM[7] -2180 378

15 DB7 795 393 55 COM[6] -2235 378

16 VSS 719 393 56 COM[5] -2290 378

17 VSS 643 393 57 COM[4] -2518 365

18 VSS 567 393 58 COM[3] -2518 310

19 OPF1 491 393 59 COM[2] -2518 255

20 OPF2 415 393 60 COM[1] -2518 200

21 OPR1 339 393 61 COMI1 -2518 145

22 OPR2 263 393 62 SEG[1] -2518 90

23 SHLC 187 393 63 SEG[2] -2518 35

24 SHLS 111 393 64 SEG[3] -2518 -20

25 N3 35 393 65 SEG[4] -2518 -75

26 TEST1 -41 393 66 SEG[5] -2518 -130

27 VDD -117 393 67 SEG[6] -2518 -185

28 VDD -193 393 68 SEG[7] -2518 -240

29 VDD -269 393 69 SEG[8] -2518 -295

30 VIN -345 393 70 SEG[9] -2518 -350

31 VIN -421 393 71 SEG[10] -2253 -378

32 VOUT -497 393 72 SEG[11] -2198 -378

33 VOUT -573 393 73 SEG[12] -2143 -378

34 PSB -649 393 74 SEG[13] -2088 -378

35 VSS -725 393 75 SEG[14] -2033 -378

36 PSI2B -801 393 76 SEG[15] -1978 -378

37 CAP1P -877 393 77 SEG[16] -1923 -378

38 CAP1P -953 393 78 SEG[17] -1868 -378

39 EXT -1029 393 79 SEG[18] -1813 -378

40 VSS -1105 393 80 SEG[19] -1758 -378

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Pad No. Function X Y Pad No. Function X Y

81 SEG[20] -1703 -378 121 SEG[60] 497 -378

82 SEG[21] -1648 -378 122 SEG[61] 552 -378

83 SEG[22] -1593 -378 123 SEG[62] 607 -378

84 SEG[23] -1538 -378 124 SEG[63] 662 -378

85 SEG[24] -1483 -378 125 SEG[64] 717 -378

86 SEG[25] -1428 -378 126 SEG[65] 772 -378

87 SEG[26] -1373 -378 127 SEG[66] 827 -378

88 SEG[27] -1318 -378 128 SEG[67] 882 -378

89 SEG[28] -1263 -378 129 SEG[68] 937 -378

90 SEG[29] -1208 -378 130 SEG[69] 992 -378

91 SEG[30] -1153 -378 131 SEG[70] 1047 -378

92 SEG[31] -1098 -378 132 SEG[71] 1102 -378

93 SEG[32] -1043 -378 133 SEG[72] 1157 -378

94 SEG[33] -988 -378 134 SEG[73] 1212 -378

95 SEG[34] -933 -378 135 SEG[74] 1267 -378

96 SEG[35] -878 -378 136 SEG[75] 1322 -378

97 SEG[36] -823 -378 137 SEG[76] 1377 -378

98 SEG[37] -768 -378 138 SEG[77] 1432 -378

99 SEG[38] -713 -378 139 SEG[78] 1487 -378

100 SEG[39] -658 -378 140 SEG[79] 1542 -378

101 SEG[40] -603 -378 141 SEG[80] 1597 -378

102 SEG[41] -548 -378 142 SEG[81] 1652 -378

103 SEG[42] -493 -378 143 SEG[82] 1707 -378

104 SEG[43] -438 -378 144 SEG[83] 1762 -378

105 SEG[44] -383 -378 145 SEG[84] 1817 -378

106 SEG[45] -328 -378 146 SEG[85] 1872 -378

107 SEG[46] -273 -378 147 SEG[86] 1927 -378

108 SEG[47] -218 -378 148 SEG[87] 1982 -378

109 SEG[48] -163 -378 149 SEG[88] 2037 -378

110 SEG[49] -108 -378 150 SEG[89] 2092 -378

111 SEG[50] -53 -378 151 SEG[90] 2147 -378

112 SEG[51] 2 -378 152 SEG[91] 2202 -378

113 SEG[52] 57 -378 153 SEG[92] 2518 -350

114 SEG[53] 112 -378 154 SEG[93] 2518 -295

115 SEG[54] 167 -378 155 SEG[94] 2518 -240

116 SEG[55] 222 -378 156 SEG[95] 2518 -185

117 SEG[56] 277 -378 157 SEG[96] 2518 -130

118 SEG[57] 332 -378 158 SEG[97] 2518 -75

119 SEG[58] 387 -378 159 SEG[98] 2518 -20

120 SEG[59] 442 -378 160 SEG[99] 2518 35

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Pad No. Function X Y Pad No. Function X Y

161 SEG[100] 2518 90

162 COM[9] 2518 145

163 COM[10] 2518 200

164 COM[11] 2518 255

165 COM[12] 2518 310

166 COM[13] 2518 365

167 COM[14] 2290 378

168 COM[15] 2235 378

169 COM[16] 2180 378

170 COMI2 2125 378

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 Pad Location Coordinates(N3=1 3 line)

Pad No. Function X Y Pad No. Function X Y

1 XRESET 1859 393 41 CLS -1181 393

2 OSC 1783 393 42 CAP1N -1257 393

3 VDD 1707 393 43 CAP1N -1333 393

4 RS 1631 393 44 VOUT -1409 393

5 CSB 1555 393 45 VOUT -1485 393

6 RW 1479 393 46 V0 -1561 393

7 E 1403 393 47 V0 -1637 393

8 DB0 1327 393 48 V1 -1713 393

9 DB1 1251 393 49 V2 -1789 393

10 DB2 1175 393 50 V3 -1865 393

11 DB3 1099 393 51 V4 -1941 393

12 DB4 1023 393 52 NC -2017 393

13 DB5 947 393 53 COM[12] -2125 378

14 DB6 871 393 54 COM[11] -2180 378

15 DB7 795 393 55 COM[10] -2235 378

16 VSS 719 393 56 COM[9] -2290 378

17 VSS 643 393 57 COM[8] -2518 365

18 VSS 567 393 58 COM[7] -2518 310

19 OPF1 491 393 59 COM[6] -2518 255

20 OPF2 415 393 60 COM[5] -2518 200

21 OPR1 339 393 61 NC -2518 145

22 OPR2 263 393 62 COM[4] -2518 90

23 SHLC 187 393 63 COM[3] -2518 35

24 SHLS 111 393 64 COM[2] -2518 -20

25 N3 35 393 65 COM[1] -2518 -75

26 TEST1 -41 393 66 COMI1 -2518 -130

27 VDD -117 393 67 NC -2518 -185

28 VDD -193 393 68 NC -2518 -240

29 VDD -269 393 69 NC -2518 -295

30 VIN -345 393 70 NC -2518 -350

31 VIN -421 393 71 NC -2253 -378

32 VOUT -497 393 72 SEG[1] -2198 -378

33 VOUT -573 393 73 SEG[2] -2143 -378

34 PSB -649 393 74 SEG[3] -2088 -378

35 VSS -725 393 75 SEG[4] -2033 -378

36 PSI2B -801 393 76 SEG[5] -1978 -378

37 CAP1P -877 393 77 SEG[6] -1923 -378

38 CAP1P -953 393 78 SEG[7] -1868 -378

39 EXT -1029 393 79 SEG[8] -1813 -378

40 VSS -1105 393 80 SEG[9] -1758 -378

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Pad No. Function X Y Pad No. Function X Y

81 SEG[10] -1703 -378 121 SEG[50] 497 -378

82 SEG[11] -1648 -378 122 SEG[51] 552 -378

83 SEG[12] -1593 -378 123 SEG[52] 607 -378

84 SEG[13] -1538 -378 124 SEG[53] 662 -378

85 SEG[14] -1483 -378 125 SEG[54] 717 -378

86 SEG[15] -1428 -378 126 SEG[55] 772 -378

87 SEG[16] -1373 -378 127 SEG[56] 827 -378

88 SEG[17] -1318 -378 128 SEG[57] 882 -378

89 SEG[18] -1263 -378 129 SEG[58] 937 -378

90 SEG[19] -1208 -378 130 SEG[59] 992 -378

91 SEG[20] -1153 -378 131 SEG[60] 1047 -378

92 SEG[21] -1098 -378 132 SEG[61] 1102 -378

93 SEG[22] -1043 -378 133 SEG[62] 1157 -378

94 SEG[23] -988 -378 134 SEG[63] 1212 -378

95 SEG[24] -933 -378 135 SEG[64] 1267 -378

96 SEG[25] -878 -378 136 SEG[65] 1322 -378

97 SEG[26] -823 -378 137 SEG[66] 1377 -378

98 SEG[27] -768 -378 138 SEG[67] 1432 -378

99 SEG[28] -713 -378 139 SEG[68] 1487 -378

100 SEG[29] -658 -378 140 SEG[69] 1542 -378

101 SEG[30] -603 -378 141 SEG[70] 1597 -378

102 SEG[31] -548 -378 142 SEG[71] 1652 -378

103 SEG[32] -493 -378 143 SEG[72] 1707 -378

104 SEG[33] -438 -378 144 SEG[73] 1762 -378

105 SEG[34] -383 -378 145 SEG[74] 1817 -378

106 SEG[35] -328 -378 146 SEG[75] 1872 -378

107 SEG[36] -273 -378 147 SEG[76] 1927 -378

108 SEG[37] -218 -378 148 SEG[77] 1982 -378

109 SEG[38] -163 -378 149 SEG[78] 2037 -378

110 SEG[39] -108 -378 150 SEG[79] 2092 -378

111 SEG[40] -53 -378 151 SEG[80] 2147 -378

112 SEG[41] 2 -378 152 NC 2202 -378

113 SEG[42] 57 -378 153 NC 2518 -350

114 SEG[43] 112 -378 154 NC 2518 -295

115 SEG[44] 167 -378 155 NC 2518 -240

116 SEG[45] 222 -378 156 NC 2518 -185

117 SEG[46] 277 -378 157 NC 2518 -130

118 SEG[47] 332 -378 158 COM[13] 2518 -75

119 SEG[48] 387 -378 159 COM[14] 2518 -20

120 SEG[49] 442 -378 160 COM[15] 2518 35

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Pad No. Function X Y Pad No. Function X Y

161 COM[16] 2518 90

162 COM[17] 2518 145

163 COM[18] 2518 200

164 COM[19] 2518 255

165 COM[20] 2518 310

166 COM[21] 2518 365

167 COM[22] 2290 378

168 COM[23] 2235 378

169 COM[24] 2180 378

170 COMI2 2125 378

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 Block Diagram

OSC

XRESET

CLS

CSB

PSB

PSI2B

DB4 to DB7

Reset circuit

MPU

interface

Instruction

decoder

Address

counter

Data

(DR)

CPG

(AC)

Display data

RAM

(DDRAM)

80x8 bits

Timing

generator

100-bit

shift

24-bit

shift

100-bit

latch

circuit

Common

signal driver

Segment

signal driver

COM1 to COM16 (OR 24)

COMI

SEG1 to SEG100

V0~V4

DB0 to DB3

SHLC SHLS

EXT

OPR1,2 OPF1,2

VSS

VDD

Input/

output

buffer

Busy

flag

Character

generator RAM

(CGRAM)

64 bytes

ICON RAM

80 bits

Character

generator ROM

(CGROM)

10.240 bits

Parallel/serial converter

and

attribute circuit

controller

Cursor

and

blink

LCD drive

voltage

follower

Voltage booster

circuit

VOUT

VIN

CAP1P CAP1N

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 Pin Function

Name Number I/O Interfaced with Function

External reset pin. Only if the power on reset be used, the

XRESET 1 I MPU

RS 1 I MPU

R/W 1 I MPU

E 1 I MPU

CSB 1 I MPU

XRESET pin could be fixed to VDD.

Low active.

Select registers. 0: Instruction register (for write)

Busy flag & address counter (for read) 1: Data register (for write and read)

Select read or write(In parallel mode). 0: Write 1: Read

Starts data read/write. (“E” must connect to “VDD” when serial mode is selected.)

Chip select in parallel mode and serial interface(Low active). When the CSB in falling edge state ( in serial interface ), the shift register and the counter are reset.

DB0~DB3 are four low order bi-directional data bus pins. DB0~DB3 are used for data transfer and receive between the MPU and the ST7036. These pins are not used during 4-bit operation and must connect to VDD.

DB0 to DB7 8 I/O MPU

Ext 1 I ITO option

PSB 1 I MPU

PSI2B 1 I ITO option

DB4~DB7 are four high order bi-directional data bus pins. DB4~DB7 are used for data transfer and receive between the MPU and the ST7036. DB7 can be used as a busy flag. In serial interface mode DB7 is SI(input data),DB6 is SCL(serial clock).

C interface DB7 is slave address A1, DB6 is slave

In I address A0, DB5 DB4 DB3 are SDA –out, DB2 DB1 are SDA-in and D0 is SCL. SDA and SCL must connect to I2C bus ( I2C bus means that connecting a resister between SDA/SCL and the power of I2C bus ).

Extension instruction select: 0:enable extension instruction(add contrast/ICON/double height font/ extension instruction) 1:disable extension instruction(compatible to ST7066U, but without 5x11dot font)

Interface selection 0:serial mode (“E” must connect to “VDD” when serial mode is selected.) 1:parallel mode(4/8 bit) In I2C interface PSB must connect to VDD

PSB PSI2B Interface

0 0 No use

0 1 SI4

1 0 SI2 ( I2C )

1 1 Parallel 68

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Name Number I/O Interfaced with Function

Character generator select:

OPR1 OPR2 CGROM CGRAM

OPR1,OPR2 2 I ITO option

SHLC 1 I ITO option

SHLS 1 I ITO option

COM1 to

COM16

COMI2 COMI1

Seg1~Seg10

Seg91~Seg100

N3 1 I ITO option

SEG11 to

SEG90

OPF1,OPF2 2 I ITO option

CAP1P 2 - Power supply

CAP1N 2 - Power supply

VIN 2 - Power supply Input the voltage to booster

VOUT 4 - Power supply

V0 to V4 6 - Power supply

VDD,VSS 4,5 - Power supply VDD : 2.7V to 5.5V, VSS: 0V

CLS 1 I ITO option

OSC 1 I Oscillation

TEST1 1 I/O Test pin TEST1 must connect to VDD.

16 O LCD

1 O LCD

21 O LCD

80 O LCD Segment signals

0 0 240 8

0 1 250 6

1 0 248 8

1 1 256 0

Common signals direction select: 0:Com1~24←Row address 23~0(Invert) 1:Com1~24←Row address 0~23(Normal)

Segment signals direction select: 0:Seg1~100←Column address 99~0(Invert) 1:Seg1~100←Column address 0~99(Normal)

Common signals that are not used are changed to non-selection waveform. COM9 to COM16 are non-selection waveforms at 1/8 or 1/9 duty factor

ICON common signals

Select “N3” pin for common or segment waveform output (follow up table 2 defined)

1 line/2 line or 3 line select : 0:1 line/2 line SEG0~SEG100:normal 1:3 line COMI1,SEG1~SEG5,SEG97~SEG100 re-defined

The built-in voltage follower circuit selection

OPF1 OPF2 Bias select

0 0 Built-in voltage follower(only use at EXT=0)

0 1 Built-in bias resistor(3.3KΩ)

1 0 Built-in bias resistor(9.6KΩ)

1 1 External bias resistor select

For voltage booster circuit(V External capacitor about 0.1u~4.7uf

DC/DC voltage converter. Connect a capacitor between this terminal and VIN when the built-in booster is used.

Power supply for LCD drive V0-Vss = 7V (Max) Built-in/external Voltage follower circuit

Internal/External oscillation select 0:external clock 1:internal oscillation

When the pin input is an external clock, it must be input to OSC. When the on-chip oscillator is used, it must be connected to VDD.

DD-VSS)

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 EXT option pin difference table

Mode

Difference

Booster Always OFF ON/OFF controlled by instruction

Can’t use the follower circuit

Bias (V0~V4)

Contrast adjust Control by external VR

ICON RAM Can’t be use RAM size has 80 bit width(S1~S80).

Only use external resistor or internal resistor(1/5 bias)

Normal mode (EXT=1)

( Instruction compatible to ST7066U )

Extension mode (EXT=0)

Follower or internal/external resistor selectable

1. Controlled by instruction with follower

2. Controlled by external VR with internal/external resistor

Instruction Control normal instruction similar to ST7066U.

Double height font Only 5x8 font Can set 5x8 or 5x16 font

Control extension instruction for low power consumption.

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 Function Description

z System Interface

This chip has all four kinds of interface type with MPU: 4-bit bus, 8-bit bus, serial and fast I or 8-bit bus is selected by DL bit in the instruction register.

During read or write operation, two 8-bit registers are used. One is data register (DR), the other is instruction register(IR).

The data register(DR) is used as temporary data storage place for being written into or read from DDRAM/CGRAM/ICON RAM, target RAM is selected by RAM address setting instruction. Each internal operation, reading from or writing into RAM, is done automatically. So to speak, after MPU reads DR data, the data in the next DDRAM/CGRAM/ICON RAM address is transferred into DR automatically. Also after MPU writes data to DR, the data in DR is transferred into DDRAM/CGRAM/ICON RAM automatically.

The Instruction register(IR) is used only to store instruction code transferred from MPU. MPU cannot use it to read instruction data.

To select register, use RS input pin in 4-bit/8-bit bus mode.

RS R/W Operation

L L Instruction Write operation (MPU writes Instruction code into IR)

L H Read Busy Flag(DB7) and address counter (DB0 ~ DB6) H L Data Write operation (MPU writes data into DR) H H Data Read operation (MPU reads data from DR)

Table 1. Various kinds of operations according to RS and R/W bits.

C interface

It just only could write Data or Instruction to ST7036 by the IIC Interface. It could not read Data or Instruction from ST7036 (except Acknowledge signal).

SCL: serial clock input SDA_IN: serial data input SDA_OUT: acknowledge response output

Slaver address could set from “0111100” to “0111111”.

The I

C interface send RAM data and executes the commands sent via the I2C Interface. It could send data in to the RAM.

The I

C Interface is two-line communication between different ICs or modules. The two lines are a Serial Data line (SDA) and a Serial Clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor. Data transfer may be initiated only when the bus is not busy.

IT TRANSFER

One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse because changes in the data line at this time will be interpreted as a control signal. Bit transfer is illustrated in Fig.1.

TART AND STOP CONDITIONS

Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the clock is HIGH is defined as the START condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP condition (P). The START and STOP conditions are illustrated in Fig.2.

YSTEM CONFIGURATION

The system configuration is illustrated in Fig.3.

· Transmitter: the device, which sends the data to the bus

· Master: the device, which initiates a transfer, generates clock signals and terminates a transfer

· Slave: the device addressed by a master

· Multi-Master: more than one master can attempt to control the bus at the same time without corrupting the message

C interface. 4-bit bus

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· Arbitration: procedure to ensure that, if more than one master simultaneously tries to control the bus, only one is allowed to

do so and the message is not corrupted

· Synchronization: procedure to synchronize the clock signals of two or more devices.

CKNOWLEDGE

Acknowledge signal (ACK) is not BF signal in parallel interface.

Each byte of eight bits is followed by an acknowledge bit. The acknowledge bit is a HIGH signal put on the bus by the transmitter during which time the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. A master receiver must also generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges must pull-down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse (set-up and hold times must be taken into consideration). A master receiver must signal an end-of-data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master to generate a STOP condition. Acknowledgement on the I

SDA SCL

SDA

SCL

SDA

SCL

START condition STOP condition

MASTER

TRANSMITTER/

RECEIVER

C Interface is illustrated in Fig.4.

data line

stable;

data valid

Fig .1 Bit transfer

change

of data

allowed

Fig .2 Definition of START and STOP conditions

SLAVE

RECEIVER (1)

0111100

Fig .3 System configuration

SLAVE

RECEIVER (2)

0111101

SLAVE

RECEIVER (3)

0111110

RECEIVER (4)

SLAVE

0111111

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I2C Interface protocol The ST7036 supports command, data write addressed slaves on the bus. Before any data is transmitted on the I addresses (0111100 to 0111111) are reserved for the ST7036. The R/W is assigned to 0 for Write only.

C Interface protocol is illustrated in Fig.5.

The I

The sequence is initiated with a START condition (S) from the I2C Interface master, which is followed by the slave address. All slaves with the corresponding address acknowledge in parallel, all the others will ignore the I acknowledgement, one or more command words follow which define the status of the addressed slaves. A command word consists of a control byte, which defines Co and RS, plus a data byte. The last control byte is tagged with a cleared most significant bit (i.e. the continuation bit Co). After a control byte with a cleared Co bit, only data bytes will follow. The state of the RS bit defines whether the data byte is interpreted as a command or as RAM data. All addressed slaves on the bus also acknowledge the control and data bytes. After the last control byte, depending on the RS bit setting; either a series of display data bytes or command data bytes may follow. If the RS bit is set to logic 1, these display bytes are stored in the display RAM at the address specified by the data pointer. The data pointer is automatically updated and the data is directed to the intended ST7036i device. If the RS bit of the last control byte is set to logic 0, these command bytes will be decoded and the setting of the device will be changed according to the received commands. Only the addressed slave makes the acknowledgement after each byte. At the end of the transmission the I INTERFACE-bus master issues a STOP condition (P).

DATA OUTPUT

BY TRANSMITTER

DATA OUTPUT

BY RECEIVER

SCL FROM

MASTER

Fig .4 Acknowledgement on the IIC Interface

not acknowledge

acknowledge

START

condition

C Interface, the device, which should respond, is addressed first. Four 7-bit slave

clock pulse for

acknowledgement

C Interface transfer. After

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During write operation, two 8-bit registers are used. One is data register (DR), the other is instruction register(IR).

The data register(DR) is used as temporary data storage place for being written into DDRAM/CGRAM/ICON RAM, target RAM is selected by RAM address setting instruction. Each internal operation, writing into RAM, is done automatically. So to speak, after MPU writes data to DR, the data in DR is transferred into DDRAM/CGRAM/ICON RAM automatically.

The Instruction register(IR) is used only to store instruction code transferred from MPU. MPU cannot use it to read instruction data.

To select register, use RS bit input in IIC interface.

z Busy Flag (BF)

When BF = "High”, it indicates that the internal operation is being processed. So during this time the next instruction cannot be accepted. BF can be read, when RS = Low and R/W = High (Read Instruction Operation), through DB7 port. Before executing the next instruction, be sure that BF is not High.

z Address Counter (AC)

Address Counter(AC) stores DDRAM/CGRAM/ICON RAM address, transferred from IR. After writing into (reading from) DDRAM/CGRAM/ICON RAM, AC is automatically increased (decreased) by 1. When RS = "Low" and R/W = "High", AC can be read through DB0 ~ DB6 ports.

Write mode

acknowledgement

from ST7036i

S 01111 1

slave address

0 A

R/W

slave address

R S

1 0

control byte

001111

acknowledgement

from ST7036i

2n>=0 bytes

command word

data byte

000000

control byte

acknowledgement

from ST7036i

acknowledgement

from ST7036i

control byte

1 byte

D6D5D4D3D2D1D

data byte

n>=0 bytes

MSB.......................LSB

data byte

Fig .5 IIC Interface protocol

Last control byte to be sent. Only a stream of data bytes is allowed to follow.

This stream may only be terminated by a STOP condition.

1 Another control byte will follow the data byte unless a STOP condition is received.

RS R/W Operation

L L Instruction Write operation (MPU writes Instruction code into IR)

H L Data Write operation (MPU writes data into DR)

Table 2. Various kinds of operations according to RS and R/W bits.

acknowledgement

from ST7036i

A P

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z Display Data RAM (DDRAM)

Display data RAM (DDRAM) stores display data represented in 8-bit character codes. Its extended capacity is 80 x 8 bits, or 80 characters. The area in display data RAM (DDRAM) that is not used for display can be used as general data RAM. See Figure 6 for the relationships between DDRAM addresses and positions on the liquid crystal display.

The DDRAM address (A

¾ 1-line display (N3=0,N = 0) (Figure 7)

When there are fewer than 80 display characters, the display begins at the head position. For example, if using only the ST7036, 20 characters are displayed. See Figure 7. When the display shift operation is performed, the DDRAM address shifts. See Figure 8.

DD ) is set in the address counter (AC) as hexadecimal.

High order bits Low order bits

AC6 AC5 AC4 AC3 AC2 AC1 AC0

Fig. 6 DDRAM Address

Display Position (digit)

123456 787980

DDRAM Address

Display Position

DDRAM Address

00 01 02 03 04 05 ........ 4D 4E 4F

Fig. 7 1-Line Display

1234 20

00 01 02 03 .... 13

Example : DDRAM Address 4F

1 0 0 1 1 1 1

For Shift Left

For Shift Right

Fig. 8 1-Line by 20-Character Display Example

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1401 02 03 04 ....

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¾ 2-line display (N3=0,N = 1) (Figure 9)

Case 1: When the number of display characters is less than 40 x 2 lines, the two lines are displayed from the head. Note that the first line end address and the second line start address are not consecutive. For example, when just the ST7036 is used, 20 characters x 2 lines are displayed. See Figure 9. When display shift operation is performed, the DDRAM address shifts. See Figure 10.

Display Position

123456 383940

Display Position

DDRAM Address

DDRAM Address (hexadecimal)

12345678 17181920

00 01 02 03 04 05 06 07

40 41 42 43 44 45 46 47

00 01 02 03 04 05 ........ 25 26 27

40 41 42 43 44 45 ........ 65 66 67

Fig. 9 2-Line Display

……………

10 11 12 13

50 51 52 53

For Shift Left

For Shift Right

0801 02 03 04 05 06 07

4841 42 43 44 45 46 47

00 01 02 03 04 05 0627

40 41 42 43 44 45 4667

Fig. 10 2-Line by 20-Character Display Example

……………

11 12 13 14

5451 52 53

0F 10 11 12

4F 50 51 52

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¾ 3-line display (N3=1,N =1) (Figure 11)

Case 1: When the number of display characters is less than 16 x 3 lines, the tree lines are displayed from the head. For example, when just the ST7036 is used, 16 characters x 3 lines are displayed. See Figure 11. When display shift operation is performed, the DDRAM address shifts. See Figure 12.

Display Position

123456 141516

DDRAM Address (hexadecimal)

Display Position

DDRAM Address (hexadecimal)

00 01 02 03 04 05 ........ 0D 0E 0F

10 11 12 13 14 15 ........ 1D 1E 1F

20 21 22 23 24 25 ........ 2D 2E 2F

Fig. 11 3-Line Display

123456 141516

00 01 02 03 04 05 ........ 0D 0E 0F

10 11 12 13 14 15 ........ 1D 1E 1F

20 21 22 23 24 25 ........ 2D 2E 2F

123456 141516

01 02 03 04 05 06 ........ 0E 0F 00

For Shift Left

11 12 13 14 15 16 ........ 1E 1F 10

21 22 23 24 25 26 ........ 2E 2F 20

123456 141516

0F 00 01 02 03 04 ........ 0C 0D 0E

For Shift Right

1F 10 11 12 13 14 ........ 1C 1D 1E

2F 20 21 22 23 24 ........ 2C 2D 2E

Fig. 12 3-Line Display

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z Character Generator ROM (CGROM)

The character generator ROM generates 5 x 8 dot character patterns from 8-bit character codes. It can generate 240/250/248/256 5 x 8 dot character patterns(select by OPR1/2 ITO pin). User-defined character patterns are also available by mask-programmed ROM.

z Character Generator RAM (CGRAM)

In the character generator RAM, the user can rewrite character patterns by program. For 5 x 8 dots, eight character patterns can be written.

Write into DDRAM the character codes at the addresses shown as the left column of Table 5 to show the character patterns stored in CGRAM.

See Table 5 for the relationship between CGRAM addresses and data and display patterns. Areas that are not used for display can be used as general data RAM.

z ICON RAM In the ICON RAM, the user can rewrite icon pattern by program. There are totally 80 dots for icon can be written. See Table 6 for the relationship between ICON RAM address and data and the display patterns.

z Timing Generation Circuit

The timing generation circuit generates timing signals for the operation of internal circuits such as DDRAM, CGROM and CGRAM. RAM read timing for display and internal operation timing by MPU access are generated separately to avoid interfering with each other. Therefore, when writing data to DDRAM, for example, there will be no undesirable interference, such as flickering, in areas other than the display area.

z LCD Driver Circuit(N3=0)

LCD Driver circuit has 17 common and 100 segment signals for LCD driving. Data from CGRAM/CGROM/ICON is transferred to 100 bit segment latch serially, and then it is stored to 100 bit shift latch. When each common is selected by 17 bit common register, segment data also output through segment driver from 100 bit segment latch. In case of 1-line display mode, COM1 ~ COM8(with COMI) have 1/9 duty, and in 2-line mode, COM1 ~ COM16(with COMI) have 1/17 duty ratio.

z LCD Driver Circuit(N3=1)

LCD Driver circuit has 25 common and 80 segment signals for LCD driving. Data from CGRAM/CGROM/ICON is transferred to 80 bit segment latch serially, and then it is stored to 80 bit shift latch. When each common is selected by 25 bit common register, segment data also output through segment driver from 80 bit segment latch. In case of 3-line display mode, COM1 ~ COM24(with COMI) have 1/25 duty.

COM/SEG Output pins

N3 COMI1

VSS COMI1

VDD NC

COM

[1:8]

COM

[1:8]

COM

[5:12]

z Cursor/Blink Control Circuit

It can generate the cursor or blink in the cursor/blink control circuit. The cursor or the blink appears in the digit at the display data RAM address set in the address counter.

SEG [1:5] SEG [1:5]

COM[4:1]

+ COMI1

SEG

[6:10]

SEG

[6:10]

SEG

[11:90]

SEG

[11:90]

SEG

[1:80]

Table 3. COM/SEG output define

SEG

[91:96]

SEG

[91:96]

SEG

[97:100]

SEG

[97:100]

COM

[13:16]

COM

[9:16]

COM

[9:16]

COM

[17:24]

COMI2

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Table 4 Correspondence between Character Codes and Character Patterns

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