ST ST70134, ST70134A User Manual

查询ST70134A 供应商

■ FULLY INTEGRATED AFE FOR CPE ADSL

■ OVERALL 12 BIT RESOLUTION, 1.1MHz

SIGNAL BANDWIDTH IN Rx

■ 8.8MS/s ADC

■ 8.8MS/s DAC

ST70134 - ST70134A

ASCOTTM INTEGRATED ADSL CMOS

ANALOG FRONT-END CIRCUIT

■ THD: -60dB @FULL SCALE

■ 4-BIT DIGI TAL INT ER FACE TO/FROM THE

DMT MODEM

■ 1V FULL SCALE INPUT

■ DIFFERENTIAL ANALOG I/O

■ ACCURA TE CONTINUOUS-TIME CHANNEL

FIL TER ING

■ 3rd & 4th ORDER TUNABLE CONTINUOUS

TIME LP FILTERS

■ 0.5 WATT AT 3.3V

■ 0.5mm HCMOS5 LA TECHNOLOGY

■ 64 PIN TQFP PACKAGE

DESCRIPTION

ST70134 is the Analog Front End of the STMicroelectronics ASCOT coupled with ST70135A or ST70235 (DMT modem) allows to g et a T1.413 Issue 2 or G .dmt compliant solution.

ADSL chipset and when

TQFP64

ORDERING NUMBER:

ST70134 (TQFP64)

ST70134A (TQFP64)

The ST70134 analog front end handles 2 transmission channels on a balanced 2 wire interconnection; a 16 to 640Kbit/s upstream transmit channel and a 1.536Mbit/s to 8.192Mbit/s downstream receive channel.

This asymmetrical data transmission system uses high resolution, high speed analog to digital and digital to analog conversion and high order analog filtering to reduce the echo and noise in both receivers and transmitters.

External low noise driver and input stage used with ST70134 guarantee low noise performances.

The filters, with a program m able cuto ff frequency, use automatic C ontinuous Time Tuning to avoid time varying phase characteristic which can be of dramatic consequence for DMT modem.

It requires few ex ternal compon ents, uses a 3.3V supply. It is packaged in a 64-pin TQFP in order to reduce PCB area.

1/22January 2001

ST70134A

Figure 1 : Block Diagram

TXP TXN

RXP(0:1) RXN(0:1)

G = -15...0dB

step = 1dB

AGCtx

G = 0...31dB

step = 1dB

AGCrx

1.1MHz

HC2

R-MOS-C

TUNING

I/V-REF

1.1MHz

HC1

The Receiver (RX) Part

The DMT signal coming from the line to the ST70134 is first filtered by two external filters, Pots HP and channel filters.

An analog multiplexer allows the selection between two input ports which can be used to select an attenuated (0, 10dB for ex.) version of the signal in case of short loop or large echo.

The signal is am plified by a low nois e gain stage (0-31dB) then low-pass filtered to avoid aliasing and to ease further digital processing by removing unwanted high frequency out-of-band noise.A 13-bit A/D converter samples the data at

8.832MS/s (or 4.416MS/s in alternative mode), transforms the signal into a digital representation and sends it to the DMT signal processor via the digital interface.

The Transmitter (TX) part

The 12-bit data words at 8.832MS/ s (or 4.41 6MS/ s) coming from the DMT signal processor through the digital interface are transformed by D/A converter into a analog signal.

This signal is then filtered to dec rease DMT sidelobes level and meet the ANSI transmitter spectral response but also to reduce the out-of-band noise (which can be echoed to the RX path) to an acceptable level. The pre-driver buffers the signa l

XTAL-DRIVER

VCXO DAC

ADC

13 Bits

DIGITAL

138kHz

SC2

DAC

12 Bits

for the external line driver and in case of short loop provide attenuation (-15...0dB).

The VCXO Part

The VCXO is divided in a XTAL driver and a auxiliary 8 bits DAC for timing recovery.The XTAL driver is able to operate at 35.328MHz.

The DAC which is driven by the CTRLIN pin provides a current output with 8-bit resolution and can be used to tune the XTAL frequency with the help of external components.

A time constant between DAC input and VCXO output can be introduced (via the CTLIN interface) and programmed with the help of an external capacitor (on VCOC pin).See chapte r ’VCXO’ for the external circuit related to the VCXO.

The Digital Interface Part

The digital part of the ST70134 can be divided in 2 sections:

– The data interface converts the multiplexed data

from/to the DMT signal processor into valid representation for the TX DAC and RX ADC.

– The control interface allows the board processor

to configure the STL70134 paths (RX/TX gains, filter band, ...) or settings (OSR, vcodac enable, digital / analog loopback,...).

Rx (0:3)

Tx (0:3)

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ST70134A

DMT Signal (Done by the DMT companion chip)

A DMT signal is basically the sum of N independently QAM m odulated signals, each c arried over a distinct carrier. The frequency separation of each carrier is 4.3125kHz with a total number of 256 carriers (ANSI). For N large, the signal can be modelled by a gaussian process with a certain amplitude probability density function. Since the maximum amplitude is expected to arise very rarely, we decide to clip the signal and to trade-off the resulting SNR loss against AD/DA dynamic. A clipping factor (Vpeak/Vrms = "crest factor") of 5.3 will be used resulting in a maximum SNR of 75dB.

ADSL DMT signals are no minally sent at an average of -38dBmHz (-1.65dBm /carrier) with a maximal power of 15.7mW for the transmitter (upstream for ADSL over Pots, DMT carriers are

Table 1 : Target Signal Levels (on the line)

ATU - R ATU - C (for reference)

Parameter

RX TX RX TX

from 7 to 31, for ADSL over ISDN DMT carriers are from 31 to 64).

Maximum / Minimum Sign al Levels

The following table gives the transmitted and received signal levels for CPE (ATU-R) and, for reference, at ATU-C. All the levels are referred to the line voltages (i.e. after hybrid and trans formers in TX direction, before hybrid and transformer in RX direction).

Note that signal amplitudes shown below are for illustration purpose and depending on the transmit power and line i mpedance signal amplitudes can differ from these values.

The reference line imped ance for all power calculations is 100Ω.

Package

The ST70134 is packaged in a 64-pin TQFP package (body size 10x10mm, pitch 0.5mm).

Max level 3.95 Vpdif * 6.8 Vpdif 1.66 mVpdif 15.8 Vpdif * Max RMS level 791 mVrms 671 mVrms 168 mVrms 3.16 Vrms Min level 42 mVpdif 839 mVpdif 54 mVpdif 3.95 Vpdif Min RMS level 8 mVrms 168 mVrms 11 mVrms 791 mVrms

* Power cut back software co facility.

3/22

ST70134A

Figure 2 : Pin Connection

TX2

TX3

DVSS2

AVSS1

XTALO

XTALI

AVDD1

RES

VCXO

IVCO

AVDD2

IREF

AVSS2

AVSS6

RXIP1

RXIN1

58 57 56 55 54 53 52 51 50 4964 63 62 61 60 59

TX1

TX0

NU3

NU2

NU1

NU0

CTRLIN

DVSS1

CLKM

CLNIB

CLWD

RX3

RX2

RX1

RX0

ST7013 4

RXIP0

RXIN0

GC1

GC0

VCOC

GP2

AVDD6

AVDD5 RES

RES

AGND

RES

AVSS5

AVSS4

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DVDD1

DVDD2

GP1

23 24 25 26 27 28 29 30 31 3217 18 19 20 21 22

GP0

RES

PDOWN

RES

RESETN

AVSS3

VRAP

VREF

VRAN

AVDD3

NC0

AVDD4

NC1

TXP

TXN

ST70134A

Table 2 : Pin Functions

Numbers Name Function PCB connection Supply

ANALOG INTERFACE

24 VRAP Positive Voltage Reference ADC Decoupling network AVDD3 25 VREF Ground Reference ADC Decoupling network AVDD3 26 VRAN Negative Voltage Refer ence ADC Decoupling networ k AVDD3 31 TXP Pre Driver Output Line driver input AVDD4 32 TXN Pre Driver Output Line driver input AVDD4 38 AGND Virtual Analog Ground (AVDD/2 = 1.65V) Decoupling network AVDD5 44 VCOC VCODAC Time Constant Capacitor VCODAC cap. AVDD5 45 GC0 External Gain Control Output LSB - AVDD5 46 GC1 External Gain Control Output MSB - AVDD5 47 RXN0 Analog Receive Negative Input Gain 0 Echo filter output AVDD5 48 RXP0 Analog Receive Positive Input Gain 0 Echo filter output AVDD5 49 RXN1 Analog Receive Negative Input Gain 1

50 RXP1 Analog Receive Positive Input Gain 1

53 IREF Current Reference TX DAC/DACE Decoupling network AVDD2 55 IVCO Current Reference VCO DAC VCO bias network AVDD1 56 VCXO VXCO Control Current VCXO filter AVDD1 59 XTALI XTAL Oscillator Input Pin Crystal + varicap AVDD1 60 XTALO XTAL Oscillator Output Pin Crystal + varicap AVDD1

DIGITAL INTERFACE

1 TX1 Digital Transmit Input, Parallel Data - DVDD2 2 TX0 Digital Transmit Input, Parallel Data - DVDD2 7 CTRLIN Serial Data Input (Settings) Async Interface DVDD2 9 CLKM Master Clock Output, f = 35.328MHz Load = CL<30pF DVDD2

10 CLNIB Nibble Clock Output, f = 17.664MHz

11 CLWD Word Clock Output, f = 8.832/4.416MHz Load = CL<30pF DVDD2 12 RX3 Digital Receive Output, Parallel Data Load = CL<30pF DVDD2 13 RX2 Digital Receive Output, Parallel Data Load = CL<30pF DVDD2 14 RX1 Digital Receive Output, Parallel Data Load = CL<30pF DVDD2 15 RX0 Digital Receive Output, Parallel Data Load = CL<30pF DVDD2 18 PDOWN Power Down Select, "1" = Power Down Power Down Input DVDD2 20 RESETN Reset Pin (Active Low) RC- Reset DVDD2 22 GP0 General Purpose Output 0 (on AVDD 1) Echo filter output AVDD 33 GP1 General Purpose Output 1 (on AVDD 1) Echo filter output AVDD 43 GP2 General Purpose Output 2 (on AVDD 1) Echo filter output AVDD 63 TX3 Digital Transmit Input, Parallel Data Load = CL<30pF DVDD2 64 TX2 Digital Transmit Input, Parallel Data Load = CL<30pF DVDD2

19, 21 RES RESERVED Must Be Connected to DVSS (Input) -

36, 37, 39,

40, 57

RES RESERVED Must Be Connected to AVSS (Input) -

(Most Sensitive Input)

(OSR = 2) or ground (OSR = 4)

Echo filter output AVDD5

Load = CL<30pF DVDD2

5/22

ST70134A

Numbers Name Function PCB connection Supply

SUPPLY VOLTAGES

8 DVSS1 - DVSS 16 DVDD1 Digital I/O Supply Voltage DVDD 17 DVDD2 Digital Internal Supply Voltage DVDD 23 AVSS3 - AVSS 27 AVDD3 ADC Supply Voltage AVDD 28 AVDD4 TX Pre - Drivers Supply AVDD 34 AVSS4 - AVSS 35 AVSS5 - AVSS 41 AVDD5 CT Filter Supply AVDD 42 AVDD6 LNA Supply AVDD 51 AVSS6 - AVSS 52 AVSS2 - AVSS 54 AVDD2 DAC and Support Circuit AVDD 58 AVDD1 XTAL Oscillator Supply Voltage AVDD 61 AVSS1 - AVSS 62 DVSS2 - DVSS -

SPARES

3 NU3 Not Used Inputs DVSS -

4 NU2 Not Used Inputs DVSS -

5 NU1 Not Used Inputs DVSS -

6 NU0 Not Used Inputs DVSS 29 NC0 - - 30 NC1 - - -

Figure 3 : Grounding and Decoupling Networks

10µF

VRAP Pin VRAN Pin

10µF 100nF 10µF 100nF

VREF Pin IREF Pin

10µF 100nF 10µF

6/22

100nF

Analog

VDD

4.7 L1

F 100nF 100nF

100nF 10µF10µF

AVDD

(Each pin

must have its

own capacitor)

AGND PinVCOC Pin

ST70134A

BLOCK DIAGRAM

Application principle is described in Figure 4. A LP filter may be used on the TX path to reduce

DMT sidelobes and out of band noise influence on the receiver. On the RX path, a HP filter must be used in order to reduce the echo signal le vel and to avoid saturation of the input stage of the receiver. The POTS filter i s used in both directions to reduce crosstalk between ADSL signals and POTS speech an d signalling. Low p ass POTS filter can be very simple for Lite - ADSL applic ation (see Figure 4).

RX Path Speech Filter

An external bi-directional LC filter for up and downstream POTS service splits the speech s ignal from the ADSL signal to the POTS circuits. The ADSL analog front end integrated circuit does not contain any circuitry for the POTS service but it guarantees that bandwidth is not disturbed by spurious signals from the ADSL-spectrum.

Figure 4 : Block Diagram

Line Zo = 100

Ω

POTS

LP POTSFILTER

Channel Filters

The external analog circuits provide partial echo cancellation by an analo g filtering of the transmit upstream signal. This is feasible because the upstream and the downstream data are modulated on separate carriers (FDM) (see Figure 4).

Signal to Noi s e P erf ormance

RX- PATH SENSITIVITY AT MAXIMUM GAIN

The RX path sensitivity at the maximal RX-AGC of the receiver is defined at -140dB m/Hz (for 100Ω ref) on the line. This figure corresponds to the equivalent input noise o f 31nVHz

-1/2

seen on the

line. The maximum noise density within the pass band

can exceed the average value as follows: RX path (max AGC setting): <100nVHz <31nVHz

-1/2

@ 138kHz

-1/2

for 250kHz < f

HP POTSFILTER

50k

Ω

2R2R

DRIVER

1.1

Ω

GTX

LINE

GRX

LPF

HPF + Attenuator

RXP(0:1)

RXN(0:1)

TXP

TXN

VCXOUT

VCODAC

LNA

-15.0dB

* For ADSL over ISDN, in st ead of SC2, HC2 1.1MHz L P f i l ter is programm ed.

35.328MHz

60 59

XTAL DRIVER

LP 1.1MHz

HC1

LP 138KHz

SC2 *

13 Bits A/D

Converter

12 Bits D/A

Converter

Master Clock

35.328MHz Nibbles

17.664MHz Word

8.832/4.416MHz

13 14 15

RXn

CTRLIN

RESETN

TXn

To ST70135

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