ST ST70134, ST70134A User Manual

ST70134A

ST70134 - ST70134A

ASCOTTM INTEGRATED ADSL CMOS

ANALOG FRONT-END CIRCUIT

■FULLY INTEGRATED AFE FOR CPE ADSL

■OVERALL 12 BIT RESOLUTION, 1.1MHz SIGNAL BANDWIDTH IN Rx

■8.8MS/s ADC

■8.8MS/s DAC

■THD: -60dB @FULL SCALE

■4-BIT DIGITAL INTERFACE TO/FROM THE DMT MODEM

■1V FULL SCALE INPUT

■DIFFERENTIAL ANALOG I/O

■ACCURATE CONTINUOUS-TIME CHANNEL FILTERING

■3rd & 4th ORDER TUNABLE CONTINUOUS TIME LP FILTERS

■0.5 WATT AT 3.3V

■0.5mm HCMOS5 LA TECHNOLOGY

■64 PIN TQFP PACKAGE

DESCRIPTION

ST70134 is the Analog Front End of the STMicroelectronics ASCOTTM ADSL chipset and when coupled with ST70135A or ST70235 (DMT modem) allows to get a T1.413 Issue 2 or G.dmt compliant solution.

TQFP64

ORDERING NUMBER:

ST70134 (TQFP64)

ST70134A (TQFP64)

The ST70134 analog front end handles 2 transmission channels on a balanced 2 wire interconnection; a 16 to 640Kbit/s upstream transmit channel and a 1.536Mbit/s to 8.192Mbit/s downstream receive channel.

This asymmetrical data transmission system uses high resolution, high speed analog to digital and digital to analog conversion and high order analog filtering to reduce the echo and noise in both receivers and transmitters.

External low noise driver and input stage used with ST70134 guarantee low noise performances.

The filters, with a programmable cutoff frequency, use automatic Continuous Time Tuning to avoid time varying phase characteristic which can be of dramatic consequence for DMT modem.

It requires few external components, uses a 3.3V supply. It is packaged in a 64-pin TQFP in order to reduce PCB area.

January 2001

1/22

ST70134A

Figure 1 : Block Diagram

R-MOS-C	I/V-REF	XTAL-DRIVER
TUNING		VCXO DAC
G = -15...0dB		ADC	Rx (0:3)
step = 1dB
TXP		13 Bits
TXN
			DIGITAL
AGCtx			IF
1.1MHz	1.1MHz	138kHz
HC2	HC1	SC2
G = 0...31dB
step = 1dB		DAC	Tx (0:3)
RXP(0:1)		12 Bits
RXN(0:1)
AGCrx

The Receiver (RX) Part

The DMT signal coming from the line to the ST70134 is first filtered by two external filters, Pots HP and channel filters.

An analog multiplexer allows the selection between two input ports which can be used to select an attenuated (0, 10dB for ex.) version of the signal in case of short loop or large echo.

The signal is amplified by a low noise gain stage (0-31dB) then low-pass filtered to avoid aliasing and to ease further digital processing by removing unwanted high frequency out-of-band noise.A 13-bit A/D converter samples the data at 8.832MS/s (or 4.416MS/s in alternative mode), transforms the signal into a digital representation and sends it to the DMT signal processor via the digital interface.

The Transmitter (TX) part

The 12-bit data words at 8.832MS/s (or 4.416MS/ s) coming from the DMT signal processor through the digital interface are transformed by D/A converter into a analog signal.

This signal is then filtered to decrease DMT sidelobes level and meet the ANSI transmitter spectral response but also to reduce the out-of-band noise (which can be echoed to the RX path) to an acceptable level. The pre-driver buffers the signal

for the external line driver and in case of short loop provide attenuation (-15...0dB).

The VCXO Part

The VCXO is divided in a XTAL driver and a auxiliary 8 bits DAC for timing recovery.The XTAL driver is able to operate at 35.328MHz.

The DAC which is driven by the CTRLIN pin provides a current output with 8-bit resolution and can be used to tune the XTAL frequency with the help of external components.

A time constant between DAC input and VCXO output can be introduced (via the CTLIN interface) and programmed with the help of an external capacitor (on VCOC pin).See chapter ’VCXO’ for the external circuit related to the VCXO.

The Digital Interface Part

The digital part of the ST70134 can be divided in 2 sections:

–The data interface converts the multiplexed data from/to the DMT signal processor into valid representation for the TX DAC and RX ADC.

–The control interface allows the board processor to configure the STL70134 paths (RX/TX gains, filter band, ...) or settings (OSR, vcodac enable, digital / analog loopback,...).

2/22

ST70134A

DMT Signal (Done by the DMT companion chip)

A DMT signal is basically the sum of N independently QAM modulated signals, each carried over a distinct carrier. The frequency separation of each carrier is 4.3125kHz with a total number of 256 carriers (ANSI). For N large, the signal can be modelled by a gaussian process with a certain amplitude probability density function. Since the maximum amplitude is expected to arise very rarely, we decide to clip the signal and to trade-off the resulting SNR loss against AD/DA dynamic. A clipping factor (Vpeak/Vrms = "crest factor") of 5.3 will be used resulting in a maximum SNR of 75dB.

ADSL DMT signals are nominally sent at an average of -38dBmHz (-1.65dBm/carrier) with a maximal power of 15.7mW for the transmitter (upstream for ADSL over Pots, DMT carriers are

Table 1 : Target Signal Levels (on the line)

from 7 to 31, for ADSL over ISDN DMT carriers are from 31 to 64).

Maximum / Minimum Signal Levels

The following table gives the transmitted and received signal levels for CPE (ATU-R) and, for reference, at ATU-C. All the levels are referred to the line voltages (i.e. after hybrid and transformers in TX direction, before hybrid and transformer in RX direction).

Note that signal amplitudes shown below are for illustration purpose and depending on the transmit power and line impedance signal amplitudes can differ from these values.

The reference line impedance for all power calculations is 100Ω.

Package

The ST70134 is packaged in a 64-pin TQFP package (body size 10x10mm, pitch 0.5mm).

		ATU - R		ATU - C (for reference)
Parameter
	RX		TX	RX	TX
Max level	3.95 Vpdif *		6.8 Vpdif	1.66 mVpdif	15.8 Vpdif *
Max RMS level	791 mVrms		671 mVrms	168 mVrms	3.16 Vrms
Min level	42 mVpdif		839 mVpdif	54 mVpdif	3.95 Vpdif
Min RMS level	8 mVrms		168 mVrms	11 mVrms	791 mVrms

* Power cut back software co facility.

3/22

ST70134A

Figure 2 : Pin Connection

	TX2	TX3	DVSS2	AVSS1	XTALO	XTALI	AVDD1	RES	VCXO	IVCO	AVDD2	IREF	AVSS2	AVSS6	RXIP1	RXIN1
	64	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49
TX1	1															48
TX0	2															47
NU3	3															46
NU2	4															45
NU1	5															44
NU0	6															43
CTRLIN	7															42
DVSS1	8						ST70134									41
CLKM	9															40
CLNIB	10															39
CLWD	11															38
RX3	12															37
RX2	13															36
RX1	14															35
RX0	15															34
DVDD1	16															33
	17	18	19	20	21	22	23	24	25	26	27	28	29	30	31	32
	DVDD2	PDOWN	RES	RESETN	RES	GP0	AVSS3	VRAP	VREF	VRAN	AVDD3	AVDD4	NC0	NC1	TXP	TXN

RXIP0

RXIN0

GC1

GC0

VCOC

GP2

AVDD6

AVDD5

RES

RES

AGND

RES

RES

AVSS5

AVSS4

GP1

4/22

				ST70134A
Table 2 : Pin Functions
Numbers	Name		Function	PCB connection	Supply
ANALOG INTERFACE
24	VRAP		Positive Voltage Reference ADC	Decoupling network	AVDD3
25	VREF		Ground Reference ADC	Decoupling network	AVDD3
26	VRAN		Negative Voltage Reference ADC	Decoupling network	AVDD3
31	TXP		Pre Driver Output	Line driver input	AVDD4
32	TXN		Pre Driver Output	Line driver input	AVDD4
38	AGND		Virtual Analog Ground (AVDD/2 = 1.65V)	Decoupling network	AVDD5
44	VCOC		VCODAC Time Constant Capacitor	VCODAC cap.	AVDD5
45	GC0		External Gain Control Output LSB	-	AVDD5
46	GC1		External Gain Control Output MSB	-	AVDD5
47	RXN0		Analog Receive Negative Input Gain 0	Echo filter output	AVDD5
48	RXP0		Analog Receive Positive Input Gain 0	Echo filter output	AVDD5
49	RXN1		Analog Receive Negative Input Gain 1	Echo filter output	AVDD5
			(Most Sensitive Input)
50	RXP1		Analog Receive Positive Input Gain 1	Echo filter output	AVDD5
			(Most Sensitive Input)
53	IREF		Current Reference TX DAC/DACE	Decoupling network	AVDD2
55	IVCO		Current Reference VCO DAC	VCO bias network	AVDD1
56	VCXO		VXCO Control Current	VCXO filter	AVDD1
59	XTALI		XTAL Oscillator Input Pin	Crystal + varicap	AVDD1
60	XTALO		XTAL Oscillator Output Pin	Crystal + varicap	AVDD1
DIGITAL INTERFACE
1	TX1		Digital Transmit Input, Parallel Data	-	DVDD2
2	TX0		Digital Transmit Input, Parallel Data	-	DVDD2
7	CTRLIN		Serial Data Input (Settings)	Async Interface	DVDD2
9	CLKM		Master Clock Output, f = 35.328MHz	Load = CL<30pF	DVDD2
10	CLNIB		Nibble Clock Output, f = 17.664MHz	Load = CL<30pF	DVDD2
			(OSR = 2) or ground (OSR = 4)
11	CLWD		Word Clock Output, f = 8.832/4.416MHz	Load = CL<30pF	DVDD2
12	RX3		Digital Receive Output, Parallel Data	Load = CL<30pF	DVDD2
13	RX2		Digital Receive Output, Parallel Data	Load = CL<30pF	DVDD2
14	RX1		Digital Receive Output, Parallel Data	Load = CL<30pF	DVDD2
15	RX0		Digital Receive Output, Parallel Data	Load = CL<30pF	DVDD2
18	PDOWN		Power Down Select, "1" = Power Down	Power Down Input	DVDD2
20	RESETN		Reset Pin (Active Low)	RCReset	DVDD2
22	GP0		General Purpose Output 0 (on AVDD 1)	Echo filter output	AVDD
33	GP1		General Purpose Output 1 (on AVDD 1)	Echo filter output	AVDD
43	GP2		General Purpose Output 2 (on AVDD 1)	Echo filter output	AVDD
63	TX3		Digital Transmit Input, Parallel Data	Load = CL<30pF	DVDD2
64	TX2		Digital Transmit Input, Parallel Data	Load = CL<30pF	DVDD2
19, 21	RES		RESERVED	Must Be Connected to DVSS (Input)	-
36, 37, 39,	RES		RESERVED	Must Be Connected to AVSS (Input)	-
40, 57
					5/22

ST70134A

Numbers						Name							Function							PCB connection										Supply
SUPPLY VOLTAGES
8					DVSS1				-								DVSS													-
16					DVDD1				Digital I/O Supply Voltage								DVDD													-
17					DVDD2				Digital Internal Supply Voltage								DVDD													-
23					AVSS3				-								AVSS													-
27					AVDD3				ADC Supply Voltage								AVDD													-
28					AVDD4				TX Pre - Drivers Supply								AVDD													-
34					AVSS4				-								AVSS													-
35					AVSS5				-								AVSS													-
41					AVDD5				CT Filter Supply								AVDD													-
42					AVDD6				LNA Supply								AVDD													-
51					AVSS6				-								AVSS													-
52					AVSS2				-								AVSS													-
54					AVDD2				DAC and Support Circuit								AVDD													-
58					AVDD1				XTAL Oscillator Supply Voltage								AVDD													-
61					AVSS1				-								AVSS													-
62					DVSS2				-								DVSS													-
SPARES
3						NU3			Not Used Inputs								DVSS													-
4						NU2			Not Used Inputs								DVSS													-
5						NU1			Not Used Inputs								DVSS													-
6						NU0			Not Used Inputs								DVSS													-
29						NC0			-								-													-
30						NC1			-								-													-
Figure 3 : Grounding and Decoupling Networks
									μ									μ											AVDD
								10 F										4.7 H											(Each pin
VRAP Pin														VRAN Pin				L1
															Analog														must have its
															VDD			10μF											own capacitor)
10μF								100nF		10μF				100nF											100nF			100nF

VREF Pin

IREF Pin

VCOC Pin

AGND Pin

10μF

100nF

10μF

100nF

10μF

100nF

10μF

6/22

ST70134A

BLOCK DIAGRAM

Application principle is described in Figure 4.

A LP filter may be used on the TX path to reduce DMT sidelobes and out of band noise influence on the receiver. On the RX path, a HP filter must be used in order to reduce the echo signal level and to avoid saturation of the input stage of the receiver. The POTS filter is used in both directions to reduce crosstalk between ADSL signals and POTS speech and signalling. Low pass POTS filter can be very simple for Lite - ADSL application (see Figure 4).

RX Path Speech Filter

An external bi-directional LC filter for up and downstream POTS service splits the speech signal from the ADSL signal to the POTS circuits. The ADSL analog front end integrated circuit does not contain any circuitry for the POTS service but it guarantees that bandwidth is not disturbed by spurious signals from the ADSL-spectrum.

Channel Filters

The external analog circuits provide partial echo cancellation by an analog filtering of the transmit upstream signal. This is feasible because the upstream and the downstream data are modulated on separate carriers (FDM) (see Figure 4).

Signal to Noise Performance

RXPATH SENSITIVITY AT MAXIMUM GAIN

The RX path sensitivity at the maximal RX-AGC of the receiver is defined at -140dBm/Hz (for 100Ω ref) on the line. This figure corresponds to the equivalent input noise of 31nVHz-1/2 seen on the line.

The maximum noise density within the pass band can exceed the average value as follows:

RX path (max AGC setting): <100nVHz-1/2 @ 138kHz <31nVHz-1/2 for 250kHz < f

Figure 4 : Block Diagram

		POTS
Line
Zo = 100Ω
		LP POTSFILTER
	1.1			VCXOUT	35.328MHz
HP POTSFILTER				56	60	59
										Master Clock
									9
										35.328MHz
				VCODAC	XTAL DRIVER				10	Nibbles
										17.664MHz
R	R			RXP(0:1)
			Attenuator	48					11	Word
										8.832/4.416MHz
50kΩ	50kΩ			50			13 Bits A/D	4	12
		GRX		LNA	LP 1.1MHz				13
							Converter
			HPF +	47	HC1					RXn
									14
										ST70135To
				49					15
2R	2R			RXN(0:1)
									7	CTRLIN
									20	RESETN
	GTX			-15.0dB
	LINE
	DRIVER			TXP					1
				31	LP 138KHz		12 Bits D/A
										TXn
			LPF	PD
					SC2 *		Converter
				32					2
				TXN

* For ADSL over ISDN, instead of SC2, HC2 1.1MHz LP filter is programmed.

7/22