ST ST6G3244ME User Manual

Level translator for SD, SDIO, mini SD, and micro SD Cards

with internal I/O supply and ±15 kV ESD protection

Features

■ Supports 60 MHz clock rate

■ Supports DDR mode for SD Card™

■ Compliant with

– SD Specification Part 1 Physical Layer

Specification 3.00 (SDR12, SDR25,
DDR50)

– SD Specification Part 1 Physical Layer

Specification 2.00

■ Bi-directional with direction control pin

■ Balanced propagation delays: t

LDO power-down support. When the LDO is

■

powered down, V
the 130 Ω

resistor. When V

is pulled to GND via

CCB

CCB

no additional leakage seen on V

■ EMI filtering and signal conditioning

■ Supports both 1.8 V and 2.9 V data translation

on card side

■ Integrated LDO to supply 1.8 V or 2.9 V power

for B-side I/Os (pin-selectable); can be used
also externally

■ Integrated pull-up and pull-down resistors on

B-side

■ Operating voltage range

–V
–V

■ Latch-up performance exceeds 100 mA

= 1.62 V to 1.98 V

CCA

= 3.0 V to 5.0 V

BAT

(JEDEC Standard 78)

■ ESD protection for card side (B-port, CD and

WP pins)
– ±8 kV contact discharge (IEC61000-4-2)
– ±15 kV air-gap discharge (IEC61000-4-2)

■ ESD protection for host side (A-side)

– ±2 kV HBM (JEDEC 22-A114)
– ±200 V MM (JEDEC 22-A115)

≈ t

PLH

PHL

= 0 V, there is

.

CCA

ST6G3244ME

Flip Chip 25

■ Operating temperature range –40 °C to +85 °C

■ Space-saving Flip Chip 25 package

(2 x 2 x 0.605 mm, 0.4 mm bump pitch)

■ RoHS compliant, lead-free soldering capable

Applications

■ Mobile phones, smartphones

■ PDAs

■ Cameras

■ SD Card readers

■ Any device with SD memory card

Table 1. Device summary

Order code Package Packing

Flip Chip 25

and reel

parts per

ST6G3244MEBJR

2 x 2 x

0.605 mm,

0.4 mm

bump pitch

Tape

(5000

reel)

Package
topmark

VKH,

VKV

November 2011 Doc ID 022157 Rev 2 1/27

www.st.com

1

Contents ST6G3244ME

Contents

1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

3 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

4 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

5 Passive integration and low-pass EMI filter . . . . . . . . . . . . . . . . . . . . . 12

6 Data transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

6.1 Test circuit from host to SD Card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

6.2 Test circuit from SD Card to host . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

6.3 Measurement of t

6.4 Measurement of t

(SD Card to host) from rising edge CLK.h . . . . . 17

SKEW

SKEW.f

(read mode) from rising edge CLK.h . . . . . . . . . 18

7 Low drop-out voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

8 SD Card specification compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

9 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

10 Tape and reel information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

2/27 Doc ID 022157 Rev 2

ST6G3244ME List of tables

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Table 3. Direction control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 4. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 5. Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 6. Current levels under recommended operating conditions (T

Table 7. Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 8. EMI filter attenuation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 9. DC voltage levels on host CPU side (T
Table 10. DC voltage levels on SD Card side (T

= –40 °C to 85 °C) . . . . . . . . . . . . . . . . . . . . . . . 14

A

= –40 °C to 85 °C) . . . . . . . . . . . . . . . . . . . . . . . . 14

A

Table 11. Leakage and short-circuit currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 12. AC characteristics (T
Table 13. V

selection (B-side power supply voltage), EN pin control . . . . . . . . . . . . . . . . . . . . . . 19

CCB

Table 14. LDO static parameters (V
Table 15. LDO dynamic parameters (V

= –40 °C to 85 °C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

A

EN

= V

EN

unless otherwise specified). . . . . . . . . . . . . . . . . . . . 20

CCA

= V

unless otherwise specified) . . . . . . . . . . . . . . . . . 20

CCA

Table 16. Package mechanical data for Flip Chip 25 (2 mm x 2 mm x 0.605 mm,

0.4 mm pitch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 17. Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

= –40 °C to 85 °C) . . . . . . . 11

A

Doc ID 022157 Rev 2 3/27

List of figures ST6G3244ME

List of figures

Figure 1. Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 2. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 3. Typical application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 4. Circuit diagram of ST6G3244ME (without LDO). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 5. Symbol definitions of t

Figure 6. Test circuit from host to SD Card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 7. Test circuit from SD Card to host . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 8. Example of measurement of t
Figure 9. Example of measurement of t

Figure 10. Low drop-out voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 11. Package outline for Flip Chip 25 (2 mm x 2 mm x 0.605 mm, 0.4 mm pitch) . . . . . . . . . . . 23

Figure 12. Footprint recommendation for Flip Chip 25 (2 mm x 2 mm x 0.605 mm,

0.4 mm pitch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 13. Pin 1 orientation in tape . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

PLH

, t

, tr and tf for AC characteristics . . . . . . . . . . . . . . . . . . . . . 15

PHL

(SD Card to host) from rising edge CLK.h . . . . . . . . . 17

SKEW

for read mode from rising edge CLK.h . . . . . . . . . . . . 18

SKEW

4/27 Doc ID 022157 Rev 2

ST6G3244ME Description

1 Description

The ST6G3244ME is a dual supply, low voltage 6-bit bi-directional CMOS level translator for
SD, mini SD and micro SD Cards. Designed for use as an interface between baseband and
memory cards, it achieves high speed operation while maintaining CMOS low-power
dissipation.

The A-port is designed to track V

. The internal LDO is powered by V

CCA

and provides

BAT

a power supply of either 1.8 V or 2.9 V to the B-side I/Os (programmed by the SEL pin).
The B-port is designed to track V
V

= 0 V, there is no additional leakage seen on V

CCB

CCB

. The V

voltage can be also used externally. When

CCB

. All outputs are push-pull type.

CCA

This device is intended for two-way asynchronous communication between data buses.
The direction of data transmission is determined by CMD.dir, DAT0.dir and DAT123.dir
inputs.

All inputs are equipped with protection circuits against electrostatic discharge, giving them
±2 kV (on A-side) and ±15 kV (on B-side, CD and WP) ESD and transient excess voltage
immunity.

Doc ID 022157 Rev 2 5/27

Functional description ST6G3244ME

2 Functional description

Figure 1. Pin connections

5

DAT2B

DAT3B

CLKB

DAT0B

DAT1B

543 2

V

DAT2B

DAT3B

CLKB

DAT0B

DAT1B

V

CMDB

BAT

CCB_OUT

GND

WP

DAT0.di r

V

GND

DAT123.dir

E

123 4

DAT2.h

DAT3.h

CLK.h

DAT1.h

CMD.dir

CMD.hDAT0.h

CLK-f

DAT0.dir

SEL SEL

EN

V

CCA

GND

DAT123.di r

V

BAT

V

CCB_OUT

GND

CMDB

WP

Top through view Bump side view

Table 2. Signal names

Pin name Bump Type Side Description

(1)

CMD.dir

CCA

CMD.h DAT0.h

CLK-f

EN

1

DAT2.h

DAT3.h

CLK.h

DAT1.h

E

AM04955v1

V

CCA

V

CCB_OUT

V

BAT

GND C4 Ground - Ground

GND C3 Ground - Ground

EN C2 Input A Enable, active-high

SEL B2 Input A V

CMD.dir A2 Input A Command direction control

CMD.h D2 I/O A Host side command

CLK.h C1 Input A Host side clock input

CLK-f E2 Output A Clock feedback to host

DAT0.dir A3 Input A DAT0 direction control

DAT0.h D1 I/O A Host side data input/output

DAT123.dir E3 Input A DAT1, DAT2, DAT3 direction control

DAT1.h E1 I/O A Host side data input/output

6/27 Doc ID 022157 Rev 2

B3 Input A Host side positive power supply (1.8 V)

B4 Output B Internal supply voltage decoupling, V

A4 Input A Battery power supply (3.0 - 5.0 V)

selection (B-side supply voltage, 1.8 V/2.9 V)

CCB

LDO output

CCB

ST6G3244ME Functional description

Table 2. Signal names (continued)

(1)

Pin name Bump Type Side Description

DAT2.h A1 I/O A Host side data input/output

DAT3.h B1 I/O A Host side data input/output

WP E4 Input to CPU A Write protect

CD D3 Input to CPU A Card detect

CMDB D4 I/O B Card side command

CLKB C5 Output B Card side clock output

DAT0B D5 I/O B Card side data input/output

DAT1B E5 I/O B Card side data input/output

DAT2B A5 I/O B Card side data input/output

DAT3B B5 I/O B Card side data input/output

1. Collective names are used for groups of pins in the datasheet:

*.dir = CMD.dir, DAT0.dir, DAT123.dir

*.h = CMD.h, CLK.h, DAT0.h, DAT1.h, DAT2.h, DAT3.h

*B = CMDB, CLKB, DAT0B, DAT1B, DAT2B, DAT3B

= all A-side input pins.

V

IA

Table 3. Direction control

Command signals Direction of A-side signals

(1)

Direction of B-side signals

(1)

EN

CMD.dir

DAT0.dir

DAT123.dir

CMD.h

CLK-f

CLK.h

DAT0.h

DAT1.h

DAT2.h

DAT3.h

CMDB

CLKB

DAT0B

DAT1.B

DAT2.B

H H X X IN IN OUT X X OUT OUT X X

HL X X OUTINOUTX X INOUTX X

H X H X X IN OUT IN X X OUT OUT X

H X L X X IN OUT OUT X X OUT IN X

H X X H X IN OUT X IN X OUT X OUT

H X X L X IN OUT X OUT X OUT X IN

LX X X X XZX X

1. When the direction of the A-side signal is INPUT, the host CPU WRITES to the SD Card (i.e. the direction of the B-side
signal is OUTPUT).
When the direction of the A-side signal is OUTPUT, the host CPU READS the SD Card (i.e. the direction of the B-side
signal is INPUT).

2. Level of the B-side signals when EN = L is defined by the internal resistors as listed in Table 7.

(2)

Z

(2) (2)

Note: During application design it has to be considered that the level shifter device needs some

time to change the direction after a change of the .dir signal level. Valid data on the input of
the corresponding channel can then start after a turn-around time, see the t

specification

TA

in Ta bl e 1 2.

DAT3.B

Doc ID 022157 Rev 2 7/27

Functional description ST6G3244ME

Figure 2. Block diagram

V

CCA

V

CCA

2 kV

V

BAT

2 kV

LDO

R9

R10

R11

R12

TSD

UVLO

V

CCB

V

CCB

V

CCB

V

CCB

A

R, C

15 kΩ

70 kΩ

70 kΩ

70 kΩ

R

130 Ω

EMI

filters

PD

V

CCB

15 kV

15 kV

15 kV

15 kV

15 kV

15 kV

SEL

EN

2 kV

500 kΩ

2 kV

500 kΩ

R

SEL

REF

R

EN

V

CCA

V

CCB

Level translator

CMD.dir

CMD.h

CLK.h

CLK-f

DAT0.dir

DAT0.h

DAT123.dir

DAT1.h

DAT2.h DAT2B

2 kV

2 kV

2 kV

2 kV

2 kV

2 kV

2 kV

2 kV

2 kV

V

CCB OUT

CMDB

CLKB

DAT0B

DAT1B

DAT3.h DAT3B

WP

2 kV

V

CCA

R14

100 kΩ

15 kV 15 kV

GND

8/27 Doc ID 022157 Rev 2

R7

470 kΩ

R13

V

15 kV

CCA

100 kΩ

CD

AM04956v2

ST6G3244ME Functional description

Figure 3. Typical application diagram

V

V

CCA

(3.0 – 5.0 V)

BAT

Host

CPU

SEL

EN

CLK.h

CLK-f

CMD.dir

CMD.h

DAT0.dir

DAT0.h

DAT123.dir

DAT1.h

DAT2.h

DAT3.h

WP

SEL

ESD
2kV

ST6G3244ME

C

VCCA

GND

voltage regulator

CLKB

CMDB

DAT0B

DAT1B

DAT2B

DAT3B

Low drop-out

LDO

V

CCB

ESD 15 kV

and EMI

ESD 15 kV

C

BAT

ESD 15 kV

V

CCB_OUT

(2.9/1.8 V)

C

VCCB

CLKB

CMDB

DAT0B

DAT1B

DAT2B

DAT3B

WP

CDCD

GND

(1)

SD

Card

1. Can be used externally, however, note that it follows V

value that is switched between 2.9 and 1.8 V by the SEL pin.

CCB

AM04957v4

Doc ID 022157 Rev 2 9/27