ST ST6G3244ME User Manual

ST6G3244ME

Level translator for SD, SDIO, mini SD, and micro SD Cards with internal I/O supply and ±15 kV ESD protection

Features

■Supports 60 MHz clock rate

■Supports DDR mode for SD Card™

■Compliant with

–SD Specification Part 1 Physical Layer Specification 3.00 (SDR12, SDR25, DDR50)

–SD Specification Part 1 Physical Layer Specification 2.00

■Bi-directional with direction control pin

■Balanced propagation delays: tPLH ≈ tPHL

■LDO power-down support. When the LDO is

powered down, VCCB is pulled to GND via the 130 Ω resistor. When VCCB = 0 V, there is no additional leakage seen on VCCA.

■EMI filtering and signal conditioning

■Supports both 1.8 V and 2.9 V data translation on card side

■Integrated LDO to supply 1.8 V or 2.9 V power for B-side I/Os (pin-selectable); can be used also externally

■Integrated pull-up and pull-down resistors on B-side

■Operating voltage range

–VCCA = 1.62 V to 1.98 V

–VBAT = 3.0 V to 5.0 V

■Latch-up performance exceeds 100 mA (JEDEC Standard 78)

■ESD protection for card side (B-port, CD and WP pins)

–±8 kV contact discharge (IEC61000-4-2)

–±15 kV air-gap discharge (IEC61000-4-2)

■ESD protection for host side (A-side)

–±2 kV HBM (JEDEC 22-A114)

–±200 V MM (JEDEC 22-A115)

Flip Chip 25

■Operating temperature range –40 °C to +85 °C

■Space-saving Flip Chip 25 package

(2 x 2 x 0.605 mm, 0.4 mm bump pitch)

■RoHS compliant, lead-free soldering capable

Applications

■Mobile phones, smartphones

■PDAs

■Cameras

■SD Card readers

■Any device with SD memory card

	Table 1.	Device summary
	Order code		Package	Packing	Package
					topmark
			Flip Chip 25	Tape
			2 x 2 x	and reel	VKH,
	ST6G3244MEBJR		0.605 mm,	(5000
					VKV
			0.4 mm	parts per
			bump pitch	reel)

November 2011

Doc ID 022157 Rev 2

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www.st.com

Contents	ST6G3244ME

Contents

1	Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. 5
2	Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		6
3	Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		10
4	DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		11
5	Passive integration and low-pass EMI filter . . . . . . . . . . . . . . . . . . . . .		12
6	Data transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		14
	6.1	Test circuit from host to SD Card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	16
	6.2	Test circuit from SD Card to host . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	16

6.3Measurement of tSKEW (SD Card to host) from rising edge CLK.h . . . . . 17

6.4 Measurement of tSKEW.f (read mode) from rising edge CLK.h . . . . . . . . . 18

7	Low drop-out voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	19
8	SD Card specification compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . .	21
9	Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	22
10	Tape and reel information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	25
11	Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	26

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ST6G3244ME	List of tables

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Table 2. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Table 3. Direction control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 4. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 5. Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 6. Current levels under recommended operating conditions (TA = –40 °C to 85 °C) . . . . . . . 11 Table 7. Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 8. EMI filter attenuation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 9. DC voltage levels on host CPU side (TA = –40 °C to 85 °C) . . . . . . . . . . . . . . . . . . . . . . . 14 Table 10. DC voltage levels on SD Card side (TA = –40 °C to 85 °C) . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 11. Leakage and short-circuit currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 12. AC characteristics (TA = –40 °C to 85 °C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 13. VCCB selection (B-side power supply voltage), EN pin control . . . . . . . . . . . . . . . . . . . . . . 19 Table 14. LDO static parameters (VEN = VCCA unless otherwise specified). . . . . . . . . . . . . . . . . . . . 20 Table 15. LDO dynamic parameters (VEN = VCCA unless otherwise specified) . . . . . . . . . . . . . . . . . 20 Table 16. Package mechanical data for Flip Chip 25 (2 mm x 2 mm x 0.605 mm,

0.4 mm pitch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 17. Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

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List of figures	ST6G3244ME

List of figures

Figure 1. Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 2. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 3. Typical application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 4. Circuit diagram of ST6G3244ME (without LDO). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 5. Symbol definitions of tPLH, tPHL, tr and tf for AC characteristics . . . . . . . . . . . . . . . . . . . . . 15 Figure 6. Test circuit from host to SD Card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 7. Test circuit from SD Card to host . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 8. Example of measurement of tSKEW (SD Card to host) from rising edge CLK.h . . . . . . . . . 17 Figure 9. Example of measurement of tSKEW for read mode from rising edge CLK.h . . . . . . . . . . . . 18 Figure 10. Low drop-out voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 11. Package outline for Flip Chip 25 (2 mm x 2 mm x 0.605 mm, 0.4 mm pitch) . . . . . . . . . . . 23 Figure 12. Footprint recommendation for Flip Chip 25 (2 mm x 2 mm x 0.605 mm,

0.4 mm pitch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 13. Pin 1 orientation in tape . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

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ST6G3244ME	Description

1 Description

The ST6G3244ME is a dual supply, low voltage 6-bit bi-directional CMOS level translator for SD, mini SD and micro SD Cards. Designed for use as an interface between baseband and memory cards, it achieves high speed operation while maintaining CMOS low-power dissipation.

The A-port is designed to track VCCA. The internal LDO is powered by VBAT and provides a power supply of either 1.8 V or 2.9 V to the B-side I/Os (programmed by the SEL pin).

The B-port is designed to track VCCB. The VCCB voltage can be also used externally. When VCCB = 0 V, there is no additional leakage seen on VCCA. All outputs are push-pull type.

This device is intended for two-way asynchronous communication between data buses. The direction of data transmission is determined by CMD.dir, DAT0.dir and DAT123.dir inputs.

All inputs are equipped with protection circuits against electrostatic discharge, giving them ±2 kV (on A-side) and ±15 kV (on B-side, CD and WP) ESD and transient excess voltage immunity.

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Functional description	ST6G3244ME

2 Functional description

Figure 1.

Pin connections

1

2

3

4

5

5

4

3

2

1

A

A

DAT2.h

CMD.dir DAT0.dir

VBAT

DAT2B

DAT2B

VBAT

DAT0.di r CMD.dir DAT2.h

B

DAT3.h

SEL

VCCA

VCCB_OUT

DAT3B

DAT3B VCCB_OUT

VCCA

SEL

DAT3.h

B

C

CLK.h

EN

GND

GND

CLKB

CLKB

GND

GND

EN

CLK.h

C

D

DAT0.h

CMD.h

CD

CMDB

DAT0B

DAT0B

CMDB

CD

CMD.h

DAT0.h

D

E

DAT1.h

CLK-f DAT123.di r WP

DAT1B

DAT1B

WP DAT123.dir CLK-f

DAT1.h

E

Top through view

Bump side view

AM04955v1

Table 2.

Signal names (1)

Pin name

Bump

Type

Side

Description

VCCA

B3

Input

A

Host side positive power supply (1.8 V)

VCCB_OUT

B4

Output

B

Internal supply voltage decoupling, VCCB LDO output

VBAT

A4

Input

A

Battery power supply (3.0 - 5.0 V)

GND

C4

Ground

-

Ground

GND

C3

Ground

-

Ground

EN

C2

Input

A

Enable, active-high

SEL

B2

Input

A

VCCB selection (B-side supply voltage, 1.8 V/2.9 V)

CMD.dir

A2

Input

A

Command direction control

CMD.h

D2

I/O

A

Host side command

CLK.h

C1

Input

A

Host side clock input

CLK-f

E2

Output

A

Clock feedback to host

DAT0.dir

A3

Input

A

DAT0 direction control

DAT0.h

D1

I/O

A

Host side data input/output

DAT123.dir

E3

Input

A

DAT1, DAT2, DAT3 direction control

DAT1.h

E1

I/O

A

Host side data input/output

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Doc ID 022157 Rev 2

ST6G3244ME						Functional description
Table 2.	Signal names (continued)(1)
Pin name		Bump	Type		Side	Description
DAT2.h		A1	I/O		A	Host side data input/output
DAT3.h		B1	I/O		A	Host side data input/output
WP		E4	Input to CPU		A	Write protect
CD		D3	Input to CPU		A	Card detect
CMDB		D4	I/O		B	Card side command
CLKB		C5	Output		B	Card side clock output
DAT0B		D5	I/O		B	Card side data input/output
DAT1B		E5	I/O		B	Card side data input/output
DAT2B		A5	I/O		B	Card side data input/output
DAT3B		B5	I/O		B	Card side data input/output

1.Collective names are used for groups of pins in the datasheet: *.dir = CMD.dir, DAT0.dir, DAT123.dir

*.h = CMD.h, CLK.h, DAT0.h, DAT1.h, DAT2.h, DAT3.h *B = CMDB, CLKB, DAT0B, DAT1B, DAT2B, DAT3B VIA = all A-side input pins.

Table 3.

Direction control

Command signals

Direction of A-side signals(1)

Direction of B-side signals(1)

EN

CMD.dir

DAT0.dir

DAT123.dir

CMD.h

CLK.h

CLK-f

DAT0.h

DAT1.h

DAT2.h

DAT3.h

CMDB

CLKB

DAT0B

DAT1.B

DAT2.B

DAT3.B

H

H

X

X

IN

IN

OUT

X

X

OUT

OUT

X

X

H

L

X

X

OUT

IN

OUT

X

X

IN

OUT

X

X

H

X

H

X

X

IN

OUT

IN

X

X

OUT

OUT

X

H

X

L

X

X

IN

OUT

OUT

X

X

OUT

IN

X

H

X

X

H

X

IN

OUT

X

IN

X

OUT

X

OUT

H

X

X

L

X

IN

OUT

X

OUT

X

OUT

X

IN

L

X

X

X

X

X

Z

X

X

(2)

Z

(2)

(2)

1.When the direction of the A-side signal is INPUT, the host CPU WRITES to the SD Card (i.e. the direction of the B-side signal is OUTPUT).

When the direction of the A-side signal is OUTPUT, the host CPU READS the SD Card (i.e. the direction of the B-side signal is INPUT).

2.Level of the B-side signals when EN = L is defined by the internal resistors as listed in Table 7.

Note:	During application design it has to be considered that the level shifter device needs some
	time to change the direction after a change of the .dir signal level. Valid data on the input of
	the corresponding channel can then start after a turn-around time, see the tTA specification
	in Table 12.

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Functional description	ST6G3244ME
Figure 2. Block diagram
VCCA	VBAT

	VCCA				2 kV
		2 kV	LDO
SEL	2 kV		A
	500 kΩ	RSEL			VCCB
			R, C		VCCB OUT
EN			TSD	RPD	15 kV
				130 Ω
	2 kV		REF
			UVLO
	500 kΩ	REN	VCCB
		VCCA

Level translator	VCCB
CMD.dir
2 kV	R9	15 kΩ
CMD.h			CMDB
2 kV			15 kV
CLK.h			CLKB
2 kV			15 kV
CLK-f
2 kV			EMI
	VCCB
DAT0.dir			filters
2 kV	R10	70 kΩ
DAT0.h			DAT0B
2 kV			15 kV
DAT123.dir	VCCB
2 kV	R11	70 kΩ
DAT1.h			DAT1B
2 kV	VCCB		15 kV
	R12	70 kΩ
DAT2.h			DAT2B
2 kV			15 kV
DAT3.h			DAT3B
2 kV	R7		15 kV
		470 kΩ
VCCA			VCCA
R14 100 kΩ			R13 100 kΩ
WP			CD
15 kV			15 kV

GND

AM04956v2

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ST6G3244ME	Functional description

Figure 3. Typical application diagram

			VCCA	V BAT (3.0 – 5.0 V)
			CVCCA		C BAT
	SEL		SEL	Low drop-out
	EN		voltage regulator			VCCB_OUT
				LDO
	CLK.h					(2.9/1.8 V) (1)
	CLK-f			VCCB	ESD 15 kV	CVCCB
	CMD.dir
	CMD.h	ESD	CLKB			CLKB
	DAT0.dir
		2 kV	CMDB			CMDB
	DAT0.h
Host			DAT0B			DAT0B	SD
	DAT123.dir			ESD 15 kV
CPU			DAT1B	and EMI		DAT1B	Card
	DAT1.h
	DAT2.h		DAT2B			DAT2B
	DAT3.h		DAT3B			DAT3B
	WP					WP
	CD			ESD 15 kV		CD
		ST6G3244ME
			GND			GND
							AM04957v4

1. Can be used externally, however, note that it follows VCCB value that is switched between 2.9 and 1.8 V by the SEL pin.

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