ST ST40RA User Manual

JTAG

UDI

JTAG

Debug

SCIF

SCIF

Integer & FP

execution units

Registers

MMU

I Cache

ST40RA

32-bit Embedded SuperH Device

Mailbox

24 data

MMU

D Cache

PIO

interface

Timer (TMU)

Real-time clock

Interrupt ctrl

Clock ctrl

PLLs

Cbus Bridge/

SuperHyway I/F

SuperHyway

PCI I/F 66MHz

32 data 64 data

PCI Peripherals SDRAM

Overview

The ST40RA is the first member of the ST40 family. Based
on the SH-4, SuperH CPU core from SuperH Inc, the
ST40RA is designed to work as a standalone device, or as
part of a two chip solution for application specific systems.

Example applications the ST40RA is designed for include
digital consumer, embedded communications, industrial
and automotive. The high connectivity of the ST40 through
its PCI bus and its dual memory uses makes it a versatile
device, ideal for data-intensive and high performance
applications.

System features

■ 32-bit SuperH CPU

● 64-bit hardware FPU (1.16 GFLOPS)

● 128-bit vector unit for matrix manipulations

● up to 200MHz, 360 MIPS (DMIPS 1.1)

● Up to 664 Mbytes/s CPU bandwidth

● Direct mapped, on-chip, ICache (8 Kbytes) and DCache

(16 Kbytes)

■ High-performance 5-channel DMA engine,
supporting 1D or 2D block moves and linked lists

■ SuperHyway internal interconnect

● High throughput, low latency, split transaction packet

router

2 channel

control

32 data

MPX

Coprocessor

Flash

Peripherals

ST40 Local Memory I/F

5 channel

DMA

controller

EMI

■ Memory protection and VM system support

● 64-entry unified TLB, 4-entry instruction TLB

● 4 Gbytes address space

■ Standard ST40 peripherals

● 2 synchronous serial ports with FIFO (SCIF)

● Timers and a real-time clock

IO devices

● Mailbox register for interprocessor communication

● Additional PIO

Bus interfaces

■ Local memory interface SDRAM & DDR SDRAM

● Up to 100 MHz (1.6 Gbytes/s peak throughput)

■ PCI interface - 32-bit, 66/33 MHz, 3.3 V

■ Enhanced memory interface (EMI)

● 32-bit bus, up to 83 MHz, for attaching peripherals

● High-speed, sync mode, burst flash ROM support

● SDRAM support

● MPX initiator and target interface

● Programmable MPX bus arbiter

May 2005 1/92

ST40RA

Contents

Appendix A Interconnect architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

A.1 Arbitration schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

A.1.1 PCI arbiter: (CPU, GPDMA, PCI, EMPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

A.1.2 EMI arbiter: (CPU buffer, GPDMA, PCI, EMPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

A.1.3 LMI 1 arbiter: (CPU, GPDMA, PCI, EMPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

A.1.4 PER arbiter: (CPU, GPDMA, PCI, EMPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

A.1.5 LMI2 arbiter: (CPU, GPDMA, PCI, EMPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

A.1.6 Return arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

A.2 Interconnect registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

A.2.1 LMI1 arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

A.2.2 LMI2 arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

A.2.3 EMI arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

A.2.4 PCI arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

A.2.5 Peripheral arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Appendix B Implementation restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

B.1 ST40 CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

B.1.1 tas.b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

B.1.2 Store queue power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

B.1.3 UBC power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

B.1.4 System standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

B.2 PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

B.2.1 Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

B.2.2 Type 2 configuration accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

B.2.3 Software visible changes between STB1HC7 and ST40RAH8D . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

B.2.4 Error behavior. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

B.2.5 Master abort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

B.3 EMI/EMPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

B.3.1 EMPI burst mode operation: ST40RA MPX target . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

B.3.2 SDRAM initialization during boot from flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

B.3.3 MPX boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

B.4 Mailbox. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

B.4.1 Test and set functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

B.5 Power down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

B.5.1 Module power-down sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

B.5.2 Accesses to modules in power-down state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

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B.6 PIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

B.6.1 PIO default functionality following reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

B.6.2 PCI/PIO alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

B.7 Interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

B.7.1 Memory bridge functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

B.7.2 Clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

B.7.3 Pad drive control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

B.8 GPDMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

B.8.1 Linked list support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

B.8.2 2-D transfers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

B.8.3 Protocol signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Chapter 1 Scope of this document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Chapter 2 ST40 documentation suite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

CPU documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

System documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Chapter 3 ST40RA devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Chapter 4 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

4.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4.2 ST40 system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4.2.1 SuperH ST40 SH-4 core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4.2.2 SuperHyway internal interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4.2.3 Standard ST40 peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4.3 Bus interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.3.1 Local memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.3.2 PCI interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4.3.3 EMI/MPX interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4.4 I/O devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4.4.1 Mailbox . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4.5 Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4.5.1 Development systems and software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4.5.2 Software compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Chapter 5 System configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

5.1 System addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

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5.1.1 System address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

5.2 System identifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

5.3 Interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

5.3.1 ST40 core interrupt allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

5.3.2 ST40 standard system interrupt allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

5.3.3 ST40RA I/O device interrupt allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

5.4 GPDMA channel mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

5.5 EMI DACK mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

5.6 EMI address pin mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

5.7 EMI pin to function relationship . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

5.8 Memory bridge control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

5.8.1 Memory bridge control signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

5.8.2 Memory bridge status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

5.8.3 Changing control of a memory bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

5.9 System configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

5.9.1 EMI.GENCFG EMI general configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

5.9.2 LMI.COC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

5.9.3 LMI.CIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

5.9.4 SYSCONF registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

5.9.5 SYSCONF.SYS_CON2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

5.9.6 PIO alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

5.9.7 PCI.PERF register definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Chapter 6 Clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

6.1 Clock domains and sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

6.2 Recommended operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

6.3 Clocks and registers at start up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

6.3.1 CLOCKGENA_2x PCI (PCI_DIV_BYPASS = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

6.3.2 Division ratios on CLOCKGENA_2x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

6.4 Setting clock frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

6.4.1 Programming the PLL output frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

6.4.2 Changing clock frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

6.4.3 Changing the core PLL frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

6.4.4 Changing the frequency division ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

6.5 Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

6.5.1 CPU low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

6.5.2 Module low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

6.6 Clock generation registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

6.6.1 CLOCKGENB.CLK_SELCR register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

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6.6.2 CPG.STBCR register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

6.6.3 CLOCKGENA.STBREQCR and CLOCKGENB.STBREQCR registers . . . . . . . . . . . . . . . . . . . . . . 54

6.6.4 CLOCKGENA.STBREQCR_SET and CLOCKGENB.STBREQCR_SET registers . . . . . . . . . . . . . 54

6.6.5 CLOCKGENA.STBREQCR_CLR and CLOCKGENB.STBREQCR_CLR register . . . . . . . . . . . . 54

6.6.6 CLOCKGENA.STBACKCR and CLOCKGENB.STBACKCR register . . . . . . . . . . . . . . . . . . . . . . 55

Chapter 7 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56

7.1 DC absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

7.1.1 Fmax clock domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

7.1.2 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

7.1.3 Pad specific output AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

7.2 Rise and fall times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

7.3 PCI interface AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

7.4 LMI interface (SDRAM) AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

7.5 LMI interface (DDR-SDRAM) AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

7.6 DDR bus termination (SSTL_2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

7.7 General purpose peripheral bus (EMI) AC specifications . . . . . . . . . . . . . . . . . . . . . . . 67

7.8 PIO AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

7.9 System CLKIN AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

7.10 Low power CLKIN AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

7.11 UDI and IEEE 1149.1 TAP AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Chapter 8 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72

8.1 Function pin use selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

8.2 Mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

8.3 PBGA 27 x 27 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

8.4 Pin states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Chapter 9 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91

5/92

ST40RA A Interconnect architecture

A Interconnect architecture

This detail is included for information only. It is not recommended to write to any of these registers,
without prior consultation from ST, as it could cause the device to malfunction.

ST only guarantees correct operation of the device with the default register values. The register
reset default values have been programmed to balance the system and give optimum system
performance, so there is no need to modify them.

For details of other registers see the ST40 System Architecture Manual.

The internal architecture of the block is shown in Figure 1.

Figure 1: ST40RA interconnect architecture

ST40 core

PCI

(t)

GPDMA

T3

32

PCI

100 MHz

SH4 subsystem

f_conv

CPU subsystem

100 MHz

Node 1

64-bit

full

cross bar

conn_2 x 2

64/32

T3/T3

T3

64

32/64

T3/T3

LMI

CPU P LPUG

Cpu_plug

T3

64

Node 2

T3

T3

32

32

32-bit

EMI

subsystem

T3

T3

32

32/32

32

PI

32

1

T1

T3/T1

PER
sub

T1

32

T3

32

T3

32

Full cross bar

conn_4 x 4

EMPI

T3

SH_PER

PER

32

Programming

Programming

port

port

6/92

A Interconnect architecture ST40RA

A.1 Arbitration schemes

A.1.1 PCI arbiter: (CPU, GPDMA, PCI, EMPI)

The default configuration (after reset) for fixed priority mode has to be in the following priority order:

● CPU buffer,

● EMPI,

● GPDMA,

● PCI (PCI master request, although not expected, get served to avoid deadlock).

The priority orders have to be programmable and the latency checking algorithm can be enabled for
GPDMA, PCI, EMPI.

A.1.2 EMI arbiter: (CPU buffer, GPDMA, PCI, EMPI)

The default configuration (after reset) for fixed priority mode has to be in the following priority order:

● CPU buffer,

● PCI,

● EMPI,

● GPDMA.

The priority order have to be programmable and the latency checking algorithm can be enabled for
GPDMA, PCI, EMPI.

A.1.3 LMI 1 arbiter: (CPU, GPDMA, PCI, EMPI)

The default configuration (after reset) as to be to work fixed priority mode in the following priority
order:

● CPU,

● GPDMA and PCI buffer.

The priority orders have to be programmable and the latency checking algorithm can be enabled for
GPDMA, PCI, EMPI.

A.1.4 PER arbiter: (CPU, GPDMA, PCI, EMPI)

The default configuration (after reset) as to be to work fixed priority mode in the following priority
order:

● CPU buffer,

● PCI,

● EMPI,

● GPDMA.

The priority order have to be programmable and the latency checking algorithm can be enabled for
GPDMA, PCI, EMPI.

7/92

ST40RA A Interconnect architecture

A.1.5 LMI2 arbiter: (CPU, GPDMA, PCI, EMPI)

The default configuration (after reset) as to be to work fixed priority mode in the following priority
order:

● PCI,

● EMPI,

● GPDMA,

● CPU buffer (although the CPU requests are not supposed to go in that node to be send in the

LMI, it has to be managed in order to avoid deadlock).

The priority order have to be programmable and the latency checking algorithm can be enabled for
GPDMA, PCI, EMPI.

A.1.6 Return arbitration

The possibilities of the return arbitration are simpler than for the request arbitration. The arbiter is
not programmable but a specific arbitration can be chosen when implementing it.

The arbitration mode chosen is the fixed priority. For each arbiter (one per initiator), the order is the
following: LMI then other targets for the arbiters in node 1 and LMI, EMI, PCI, peripheral subsystem
for the arbiters of node 2.

A.2 Interconnect registers

A summary of registers is given in Ta bl e 1 . Addresses in the table are offset from the interconnect
base address at 0x1B05 0000.

Address
offset

0x010 LATENCY_LMI1_ENABLE Enables or disables initiators latency counters, see LMI1 arbiter on page 9

0x018 LMI1_CPU_PRI Defines priority for the CPU in the LMI1 arbiter, see LMI1 arbiter on page 9

0x020 LATENCY_LMI1_VALUE Defines priority and latency value for the node 2 in the LMI1 arbiter, see

0x110 LATENCY_LMI2_ENABLE Enables or disables initiators latency counters, see LMI2 arbiter on page 10

0x118 LMI2_CPU_PRI Defines priority for the CPU in the LMI2 arbiter, see LMI2 arbiter on page 10

0x120 LMI2_LATENCY_PCI Defines priority and latency value for PCI initiator in the PCI arbiter, see

0x128 LMI2_LATENCY_EMPI Defines priority and latency value for EMPI initiator in the PCI arbiter, see

0x130 LMI2_LATENCY_GPDMA Defines priority and latency value for GPDMA initiator in the PCI arbiter, see

Name Function

Table 1: Interconnect register summary

LMI1 arbiter on page 9

LMI2 arbiter on page 10

LMI2 arbiter on page 10

LMI2 arbiter on page 10

0x210 LATENCY_EMI_ENABLE Enables or disables initiators latency counters, see EMI arbiter on page 11

0x218 EMI_CPU_PRI Defines priority for the CPU in the EMI arbiter, see EMI arbiter on page 11

0x220 EMI_LATENCY_PCI Defines priority and latency value for PCI initiator in the EMI arbiter, see

EMI arbiter on page 11

0x228 EMI_LATENCY_EMPI Defines priority and latency value for EMPI initiator in the EMI arbiter, see

EMI arbiter on page 11

8/92

A Interconnect architecture ST40RA

Table 1: Interconnect register summary

Address
offset

0x230 EMI_LATENCY_GPDMA Defines priority and latency value for GPDMA initiator in the EMI arbiter,

0x310 LATENCY_PCI_ENABLE Enables or disables initiators latency counters, see PCI arbiter on page 12

0x318 PCI_CPU_PRI Defines priority for the CPU in the PCI arbiter, see PCI arbiter on page 12

0x320 PCI_LATENCY_PCI Defines priority and latency value for PCI initiator in the PCI arbiter, see PCI

0x328 PCI_LATENCY_EMPI Defines priority and latency value for EMPI initiator in the PCI arbiter, see

0x330 PCI_LATENCY_GPDMA Defines priority and latency value for GPDMA initiator in the PCI arbiter, see

0x410 LATENCY_PER_ENABLE Enables or disables initiators latency counters, see Peripheral arbiter on

0x418 PER_CPU_PRI Defines priority for the CPU in the peripheral arbiter, see Peripheral arbiter

0x420 PER_LATENCY_PCI Defines priority and latency value for PCI initiator in the peripheral arbiter,

0x428 PER_LATENCY_EMPI Defines priority and latency value for EMPI initiator in the peripheral arbiter,

Name Function

see EMI arbiter on page 11

arbiter on page 12

PCI arbiter on page 12

PCI arbiter on page 12

page 13

on page 13

see Peripheral arbiter on page 13

see Peripheral arbiter on page 13

0x430 PER_LATENCY_GPDMA Defines priority and latency value for GPDMA initiator in the peripheral

A.2.1 LMI1 arbiter

LATENCY_LMI1_ENABLE LMI1 arbiter: enable latency counters

0 Reserved Reset: Always 0

1 ENABLE_1 Enable latency check for node 2

[31:2] Reserved Reset: Always 0

LMI1_CPU_PRI

[3:0] CPU_PRIORITY Defines priority for CPU

[31:4] Reserved

arbiter, see Peripheral arbiter on page 13

Reset: 0

LMI1 arbiter: CPU priority

Reset: 0x1

0x010

RW

0x018

RW

LATENCY_LMI1_VALUE

[3:0] NODE2_PRIORITY Defines priority for node 2 initiators

[15:4] Reserved

LMI1 arbiter: node 2 intitiator priority and latency

Reset: 0x0

9/92

0x020

RW

ST40RA A Interconnect architecture

LATENCY_LMI1_VALUE

[23:16] NODE2_LATENCY Defines maximum accepted latency for node 2 initiators

[31:24] Reserved

A.2.2 LMI2 arbiter

LATENCY_LMI2_ENABLE

0 Reserved Reset: Always 0

1 ENABLE_PCI Enable latency check for PCI

2 ENABLE_EMPI Enable latency check for EMPI

3 ENABLE_GPDMA Enable latency check for GPDMA

[31:4] Reserved Reset: Always 0

LMI1 arbiter: node 2 intitiator priority and latency

Reset: 0x00

LMI2 arbiter: enable latency counters

Reset: 0

Reset: 0

Reset: 0

0x020

RW

0x110

RW

RW

RW

LMI2_CPU_PRI

[3:0] CPU_PRIORITY Defines priority for CPU

[31:4] Reserved

LMI2_LATENCY_PCI

[3:0] PCI_PRIORITY Defines priority for PCI

[15:4] Reserved

[23:16] PCI_LATENCY Defines maximum accepted latency for PCI

[31:24] Reserved

LMI2_LATENCY_EMPI

[3:0] EMPI_PRIORITY Defines priority for EMPI

LMI2 arbiter: CPU priority

Reset: 0x0

LMI2 arbiter: PCI intitiator priority and latency

Reset: 0x3

Reset: 0x00

LMI2 arbiter: EMPI intitiator priority and latency

Reset: 0x2

0x118

RW

0x120

RW

RW

0x128

RW

[15:4] Reserved

[23:16] EMPI_LATENCY Defines maximum accepted latency for EMPI

Reset: 0x00

[31:24] Reserved

10/92

RW

A Interconnect architecture ST40RA

LMI2_LATENCY_GPDMA

[3:0] GPDMA_PRIORITY Defines priority for GPDMA

[15:4] Reserved

[23:16] GPDMA_LATENCY Defines maximum accepted latency for GPDMA

[31:24] Reserved

A.2.3 EMI arbiter

LATENCY_EMI_ENABLE

0 Reserved Reset: Always 0

1 ENABLE_PCI Enable latency check for PCI

2 ENABLE_EMPI Enable latency check for EMPI

3 ENABLE_GPDMA Enable latency check for GPDMA

LMI2 arbiter: GPDMA intitiator priority and latency

Reset: 0x1

Reset: 0x00

EMI arbiter: enable latency counters

Reset: 0

Reset: 0

Reset: 0

0x130

RW

RW

0x210

RW

RW

RW

[31:4] Reserved Reset: Always 0

EMI_CPU_PRI

[3:0] CPU_PRIORITY Defines priority for CPU

[31:4] Reserved

EMI_LATENCY_PCI

[3:0] PCI_PRIORITY Defines priority for PCI

[15:4] Reserved

[23:16] PCI_LATENCY Defines maximum accepted latency for PCI

[31:24] Reserved

EMI arbiter: CPU priority

Reset: 0x3

EMI arbiter: PCI intitiator priority and latency

Reset: 0x2

Reset: 0x00

0x218

RW

0x220

RW

RW

EMI_LATENCY_EMPI

[3:0] EMPI_PRIORITY Defines priority for EMPI

[15:4] Reserved

EMI arbiter: EMPI intitiator priority and latency

Reset: 0x1

11/92

0x228

RW

ST40RA A Interconnect architecture

EMI_LATENCY_EMPI

[23:16] EMPI_LATENCY Defines maximum accepted latency for EMPI

[31:24] Reserved

EMI_LATENCY_GPDMA

[3:0] GPDMA_PRIORITY Defines priority for GPDMA

[15:4] Reserved

[23:16] GPDMA_LATENCY Defines maximum accepted latency for GPDMA

[31:24] Reserved

A.2.4 PCI arbiter

LATENCY_PCI_ENABLE

EMI arbiter: EMPI intitiator priority and latency

Reset: 0x00

EMI arbiter: GPDMA intitiator priority and latency

Reset: 0x0

Reset: 0x00

PCI arbiter: enable latency counters

0x228

RW

0x230

RW

RW

0x310

0 Reserved

1 ENABLE_PCI Enable latency check for PCI

Reset: 0

2 ENABLE_EMPI Enable latency check for EMPI

Reset: 0

3 ENABLE_GPDMA Enable latency check for GPDMA

Reset: 0

[31:4] Reserved Reset: Always 0

PCI_CPU_PRI

[3:0] CPU_PRIORITY Defines priority for CPU

[31:4] Reserved

PCI_LATENCY_PCI

[3:0] PCI_PRIORITY Defines priority for PCI

PCI arbiter: CPU priority

Reset: 0x3

PCI arbiter: PCI intitiator priority and latency

Reset: 0x0

RW

RW

RW

0x318

RW

0x320

RW

[15:4] Reserved

[23:16] PCI_LATENCY Defines maximum accepted latency for PCI

Reset: 0x00

[31:24] Reserved

12/92

RW

A Interconnect architecture ST40RA

PCI_LATENCY_EMPI

[3:0] EMPI_PRIORITY Defines priority for EMPI

[15:4] Reserved

[23:16] EMPI_LATENCY Defines maximum accepted latency for EMPI

[31:24] Reserved

PCI_LATENCY_GPDMA

[3:0] GPDMA_PRIORITY Defines priority for GPDMA

[15:4] Reserved

[23:16] GPDMA_LATENCY Defines maximum accepted latency for GPDMA

[31:24] Reserved

PCI arbiter: EMPI intitiator priority and latency

Reset: 0x2

Reset: 0x00

PCI arbiter: GPDMA intitiator priority and latency

Reset: 0x1

Reset: 0x00

0x328

RW

RW

0x330

RW

RW

A.2.5 Peripheral arbiter

LATENCY_PER_ENABLE Peripheral arbiter: enable latency counters

0 Reserved Reset: Always 0

1 ENABLE_PCI Enable latency check for PCI

2 ENABLE_EMPI Enable latency check for EMPI

3 ENABLE_GPDMA Enable latency check for GPDMA

[31:4] Reserved Reset: Always 0

PER_CPU_PRI Peripheral arbiter: CPU priority

[3:0] CPU_PRIORITY Defines priority for CPU

[31:4] Reserved

Reset: 0

Reset: 0

Reset: 0

Reset: 0x3

0x410

RW

RW

RW

0x418

RW

PER_LATENCY_PCI

[3:0] PCI_PRIORITY Defines priority for PCI

[15:4] Reserved

Peripheral arbiter: PCI intitiator priority and latency

Reset: 0x2

13/92

0x420

RW

ST40RA A Interconnect architecture

PER_LATENCY_PCI

[23:16] PCI_LATENCY Defines maximum accepted latency for PCI

[31:24] Reserved

PER_LATENCY_EMPI

[3:0] EMPI_PRIORITY Defines priority for EMPI

[15:4] Reserved

[23:16] EMPI_LATENCY Defines maximum accepted latency for EMPI

[31:24] Reserved

PER_LATENCY_GPDMA

Peripheral arbiter: PCI intitiator priority and latency

Reset: 0x00

Peripheral arbiter: EMPI intitiator priority and
latency

Reset: 0x1

Reset: 0x00

Peripheral arbiter: GPDMA intitiator priority and
latency

0x420

RW

0x428

RW

RW

0x430

[3:0] GPDMA_PRIORITY Defines priority for GPDMA

Reset: 0x0

[15:4] Reserved

[23:16] GPDMA_LATENCY Defines maximum accepted latency for GPDMA

Reset: 0x00

[31:24] Reserved

RW

RW

14/92

B Implementation restrictions ST40RA

B Implementation restrictions

B.1 ST40 CPU

B.1.1 tas.b

The atomicity of the tas.b instruction is only guaranteed for processes executing on the ST40 CPU
core and should not be used to implement intermodule or interchip semaphores. Either use the
mailbox functionality or an appropriate software algorithm for such semaphores.

B.1.2 Store queue power-down

The store queue is considered part of the general CPU and independent power-down of this block
is not implemented.

B.1.3 UBC power-down

The UBC is considered part of the general CPU and independent power-down of this block is not
implemented.

B.1.4 System standby

To enter and leave standby it is necessary for the CPU to power down the system including memory
devices and then to enter standby by executing a sleep instruction. On leaving sleep and standby, it
may be necessary for the CPU to power itself up and subsequently power up the system and its
memory devices.

During the power-down and power-up sequences the main memory devices are not available. The
CPU therefore preloads the appropriate code into the cache as part of the power sequencing.

B.2 PCI

B.2.1 Clocking

PCI internal clock loop back is not implemented. To use the internal PCI clock, the pads
PCICLOCKOUT and PCICLOCKIN are connected to rollback the clock generator. Alternatively an
external clock source may be used.

B.2.2 Type 2 configuration accesses

Configuration space accesses to devices across a PCI bridge are implemented as type 2
operations on the PCI bus. In this implementation such accesses must be broken into a sequence of
byte operations. For example, access to a 32-bit register is through four single byte operations.

B.2.3 Software visible changes between STB1HC7 and ST40RAH8D

PCI PLL reprogramming required for H7 parts is no longer required for H8.

The PCI PLL register is renamed from PLLPCICR to CLKGENA.PLL2CR.

The register implementation for PCI MBAR mappings has changed between the STB1HC7 and
ST40RAH8D implementations and software device drivers should reflect this.

B.2.4 Error behavior

The implementation of local (PCI register) error handling is not fully implemented.

15/92

ST40RA B Implementation restrictions

B.2.5 Master abort

When operating as a bus master, the PCI module is not guaranteed to have the value 0xFFFF FFFF
following a master abort of a read cycle. The master abort may be detected using either the PCI
module status and interrupt information supplied by the module.

B.3 EMI/EMPI

B.3.1 EMPI burst mode operation: ST40RA MPX target

MPX operations using the ST40RA as the target which lead to burst requests to memory (Read
ahead, 8-, 16- and 32-byte read operations) have limited support.

MPX operations from the ST40RA as an initiator includes full support for all transfer sizes.

B.3.2 SDRAM initialization during boot from flash

During the SDRAM initialization sequence only internal EMI registers are accessible, it is therefore
necessary to ensure the program required to execute the initialization sequence is placed in an
alternate memory location such as the LMI or preloaded into the cache.

B.3.3 MPX boot

BOOTFROMMPX is not supported on this part.

B.4 Mailbox

B.4.1 Test and set functionality

This is not supported.

B.5 Power down

B.5.1 Module power-down sequencing

Whilst powering down using the associated registers for the ST40RA module, in general, software is
responsible for ensuring the module is in a safe state before requesting module shutdown. For
details refer to the appropriate documentation.

B.5.2 Accesses to modules in power-down state

Once a module is in power-down state, attempts to access that module may lead the system to
hang.

16/92

B Implementation restrictions ST40RA

B.6 PIO

B.6.1 PIO default functionality following reset

In the ST40 family device, the operational modes for these registers differ from the standard
architecture definition and are shown in Tab le 2 .

Table 2: PIO alternate function registers

PIO bit configuration PIO output state PIO.PC2 PIO.PC1 PIO.PC0

NonPIO function

PIO bidirectional Open drain 0 0 1

PIO output Push-pull 0 1 0

PIO bidirectional Open drain 0 1 1

PIO input High impedance 1 0 0

PIO input High impedance 1 0 1

Reserved - 1 1 0

Reserved - 1 1 1

a

a. State following reset

B.6.2 PCI/PIO alternate functions

The following PIO signals cannot be used when PCI is enabled even if the PCI implementation does
not require the primary pin function.

BPN

Pin name

Row Col Default Alternate Type Dir

Architecture

signal name

-000

Table 3: PCI/PIO alternate functions

Pin function Pin

NOTPREQ0 E 18 NOTPCI_REQ0 PCI external request for bus PIO16 P8 I/O I/O

NOTPREQ1 E 17 NOTPCI_REQ1 PCI external request for bus PIO18 P8 I I/O

NOTPREQ2 F 16 NOTPCI_REQ2 PCI external request for bus PIO20 P8 I I/O

NOTPREQ3 G 16 NOTPCI_REQ3 PCI external request for bus PIO22

If PCI is disabled, the alternate functions may be used.

17/92

EMPIDREQ1

P8 I I/O

O

ST40RA B Implementation restrictions

B.7 Interconnect

B.7.1 Memory bridge functionality

Ensure there is no traffic passing though the memory bridge when changing frequency.

Semisynchronous modes of operation are not supported.

B.7.2 Clock selection

The alternate CLOCKGENB clock is not supported for the LMI.

B.7.3 Pad drive control

Programmable drive strength control is not supported for DDR operation.

B.8 GPDMA

B.8.1 Linked list support

Decrementing transfers are not supported as part of link list transfer sequences

B.8.2 2-D transfers

2-D transfers fail if the following conditions are met.

1 Source or destination length is greater than 64 bytes.

2 Real transfer unit is less then 32 bytes.

3 The expression length = n * 64 + tu is true, where:

➢ length is either SLENGTH or DLENGTH,

➢ tu the real transfer unit of the first access of the second line,

➢ n > 0.

B.8.3 Protocol signals

DACK and DRACK protocol signals have limited support.

18/92

1 Scope of this document ST40RA

1 Scope of this document

This document describes only those areas of the ST40RA that are device specific, for example the
system address map. Information that is generic to the ST40 family of devices is contained in the
ST40 documentation suite.

2 ST40 documentation suite

This document references a number of other generic ST40 documents that combined together form
a complete datasheet.

CPU documentation

The SH-4 CPU core and its instruction set are documented in the SH-4 CPU Core Architecture
Manual.

System documentation

Devices listed in the system address map, Figure 5 on page 26 are documented in the ST40
System Architecture Manual:

● Volume 1: System, details the ST40 CPU and standard peripherals,

● Volume 2: Bus Interfaces, details the standard PCI, LMI and EMI bus interfaces.

3 ST40RA devices

Table 4: ST40RA device types

Device

ST40RA150XHA 150 MHz
ST40RA166XH1 166 MHz
ST40RA166XH6 166 MHz

ST40RA200XH6 200 MHz

19/92

CPU

clock frequency

Temperature range

Minimum Maximum

-40 oC+85

o

C+70

0

o

-40

C+85

o

-40

C+85

o

C

o

C

o

C

o

C

VDD Core

1.65V to 1.95V

1.80V to 1.95V

ST40RA 4 Architecture

4 Architecture

4.1 Overview

The ST40RA combines an SH-4, 32-bit microprocessor with a wide range of interfaces to external
peripherals. This section briefly describes each of the features of the ST40RA.

4.2 ST40 system

4.2.1 SuperH ST40 SH-4 core

Figure 2 illustrates the system architecture of the ST40 SH-4 core. The following section briefly

describes the features and performance of the core.

Figure 2: ST40 SH-4 core architecture

CPU

32-bit data (load)

32-bit add (instruction)

ICache 8 Kbytes ITLB UTLB

32-bit address (data)

32-bit data (instruction)

32-it data (store)

UBC

Lower 32-bit data

Lower 32-bit data

Cache and TLB
controller

29bit add

32bit data

32bit data

FPU

DCache 16 Kbytes

64-bit data (store)

Upper 32-bit data

Central processing unit

The central processing unit is built around a 32-bit RISC, two-way superscalar architecture.
Operating at 166 MHz it runs with high code density using fixed length 16-bit instructions. It has a
load/store architecture, delayed branch instruction capability and an on-chip multiplier. It uses a five­stage pipeline.

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4 Architecture ST40RA

Floating point unit/multiply and accumulate

The on-chip, floating point coprocessor executes single precision (32-bit) and double precision

(64-bit) operations. It has a five-stage pipeline and supports IEEE754-compliant data types and

exceptions. It has rounding modes: (round-to-nearest) and (round-to-zero), and handles
denormalized numbers (truncation-to-zero) or interrupt generation for compliance with IEEE754.
The floating point unit performs the following functions:

● fmac (multiply-and-accumulate), fdiv (divide),

● fsqrt (square root) instructions,

● 3-D graphics instructions (single-precision):

➢ 4-dimensional vector conversion and matrix operations (ftrv): 4 cycles (pitch), 7 cycles

(latency),

➢ 4-dimensional vector (fipr) inner product: 1 cycle (pitch), 4 cycles (latency).

MMU configuration

There is 4 Gbytes virtual address space with 256 address space identifiers (8-bit ASIDs),
supporting single virtual and multiple virtual memory modes. Page sizes are 1 Kbyte, 4 Kbytes, 64
Kbytes or 1 Mbyte. The MMU supports four-entry, fully associative ITLB for instructions and
64-entry fully associative UTLB for instructions and operands. Software-controlled replacement and
random-counter replacement algorithms are also supported. The physical address space is 512
Mbytes (29-bit), see Figure 3: System address organization on page 25.

Cache

8 Kbytes of direct-mapped instruction cache are organized as 256 32-byte lines, and 16 Kbytes of
direct-mapped operand cache are organized as 512 32-byte lines. RAM mode (8-Kbyte cache plus
8-Kbyte RAM) with selectable write method (copy back or write through) is supported. A single
stage buffer for copy-back and a single stage buffer for write-through are available. The cache
contents can be address mapped and there is a 32-byte two-entry store queue.

4.2.2 SuperHyway internal interconnect

The ST40RA uses the SuperHyway memory mapped packet router for on-chip intermodule
communication. The interconnect supports a split transaction system allowing a nonblocking high
throughput, low latency system to be built. There are separate request and response packet routers.

The ST40RA SuperHyway implementation is show in Section 5.8: Memory bridge control on

page 34. The interconnect allows simultaneous requests between multiple modules and is able to

ensure a very high data throughput with in many cases zero routing, arbitration and decode
latencies.

4.2.3 Standard ST40 peripherals

Synchronous serial channel

There are two ST40 compatible full duplex communication channels (SCIF1, SCIF2). Asynchronous
mode is supported. A separate 16-byte FIFO is provided for the transmitter and receiver.

Interrupt controller

The interrupt controller supports all of the on-chip peripheral module interrupts, and five external
interrupts (NMI and IRL0 to IRL3). The priority can be set for each on-chip peripheral module
interrupt. IRL0 to IRL3 are configured as four independent interrupts or encoded to provide 15
external interrupt levels.

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ST40RA 4 Architecture

Debug controller

Debugging is performed by break interrupts. There are two break channels. The address, data
value, access type, and data size can all be set as break conditions. Sequential break functions are
supported.

The user debug interface (UDI) contains a five-pin serial interface conforming to JTAG, IEEE
Standard TAP and boundary scan architecture. The interface provides host access to the 1 Kbyte
ASERAM for emulator firmware (accessible only in ASE mode).

Timers

The three-channel, auto-reload, 32-bit timer has an input capture function and a choice of seven
counter input clocks.

Real-time clock

The built-in 32-kHz crystal oscillator has a maximum 1/256 second resolution. It has dynamically
programmable operating frequencies and on-chip clock and calendar functions. It has two sleep
modes and one standby mode.

Watchdog timer

The ST40RA has an 8-bit watchdog timer (WDT) with programmable clock ratio. The WDT is able to
generate a power-on reset or a manual reset.

Programmable PLLs

The ST40RA has three programmable PLLs. The PLLs are configured by MODE pins at reset and
then reconfigured by software to optimize system performance or reduce system power
consumption.

General-purpose DMA controller

The five-channel physical address GPDMA controller has four general-purpose channels for
memory-to-memory or memory-to-peripheral transfers, and one buffered multiplexed channel. Both
2-D block moves and linked lists are supported. Two sets of DMA handshake pins are available for
use by external devices to support efficient transfer interdevice transfers via external interfaces such
as the EMI MPX.

Parallel I/O module

24 bits of parallel I/O are provided from the ST40 compatible PIO. Each bit is programmable as an
output or an input. “Input compare” generates an interrupt on any change of any input bit.

4.3 Bus interfaces

4.3.1 Local memory interface

The LMI supports 16-, 32- and 64-bit wide bus SDRAM and DDR SDRAM, at up to 100 MHz with a
maximum address space of 112 Mbytes. Devices supported include two and four bank 16-, 64-,
128- and 256-Mbit technologies in x4, x8, x16 and x32 packages. The LMI pads are dual mode
pads electrically compatible with LVTTL (for standard SDRAM) and SSTL_2 (for DDR SDRAM). For
full detail of the configuration options of the LMI please see ST40 System Architecture Manual,
Volume 2: Bus Interfaces.

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4 Architecture ST40RA

4.3.2 PCI interface

The PCI interface complies to the PCI v2.1 and Power Management Interface V1.0 specifications. It
is 32 bits wide and operates at 33 or 66 MHz. Master and target mode are supported. A PCI arbiter
and clock generator is provided inside the ST40RA. For details on the configuration options for the
PCI interface please see ST40 System Architecture Manual, Volume 2: Bus Interfaces.

4.3.3 EMI/MPX interface

The EMI/MPX interface contains the following blocks. For full details of the configuration options of
the EMI please see the ST40 System Architecture Manual, Volume 2: Bus Interfaces.

EMI memory interface initiator

The EMI provides access to ROMs, SDRAM, memory mapped asynchronous external peripherals
and synchronous MPX bus peripherals. The EMI supports burst mode flash ROM and MPX for
memory-mapped device coupling. The ST40RA GPDMA unit accesses external devices and two
sets of DMA channels control signals are provided for this purpose.

EMPI memory interface target

The EMPI is a synchronous MPX target that allows for an external MPX initiator to access the
ST40RA internal memory space. The EMPI contains a general purpose control channel and four
high performance channels each of which implements a write buffer and a pair of 32-byte read­ahead buffers able to optimize external device burst access to and from the ST40RA internal
memory. These buffers can be associated with memory regions within the ST40RA and external
DMA channels. Four sets of DMA handshake signals are provided to the EMPI to optimize long
burst transfers between the ST40RA and external initiators like the STi5514.

MPX bus arbiter

The ST40RA has an internal programmable bus arbiter to optimize utilization of the MPX bus. The
ST40RA MPX arbiter supports one external initiator and has programmable bus priority (ST40RA or
external device), bus parking (ST40RA, external, idle or last user) and latency timers. The internal
arbiter can be bypassed if an external arbiter supporting more initiators is required.

4.4 I/O devices

4.4.1 Mailbox

The ST40 and the external microprocessor communicate with each other and synchronize their
activities using the memory-mapped mailbox. Processes generate interrupts to either CPU, and
send and receive messages between the two CPUs. There are buffers for message queueing in
both directions and interrupt bits can be set in each direction. Access to the mailbox from external
devices is through the ST40RA EMPI or the PCI target interface.

4.5 Software

4.5.1 Development systems and software

The ST40RA supports application development, with a full range of debug features and an
emulation mode (ASE). The ASE mode has a dedicated 1-Kbyte buffer for emulator firmware,
supporting performance counters and branch trace. The ST40RA, with its memory management
unit, supports standard operating systems including WindowsCE and Linux. The ST40 has a wide
range of development support from ST and third parties, and efficiently runs applications written in
C, C++ and Java.

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ST40RA 5 System configuration

ST’s own tools include:

● C/C++ compilers,

● debugger,

● proprietary OS.

Third parties include:

● Microsoft: WindowsCE,

● Sun: JavaOS for consumers,

● WindRiver: VxWorks, Tornado tools,

● Linux,

● Insignia JVM,

● ANT browser.

4.5.2 Software compatibility

SH-4 core software

The ST40RA SH-4 core is binary code compatible with the Hitachi SH775x family.

Standard peripheral driver

The ST40 standard SCIF, timer, real-time clock and PIO are compatible with the ST40 SOC range of
devices and the Hitachi SH775x family.

Bus interface driver

The PCI, LMI, and EMI interfaces are register compatible with the ST40 SOC range of devices.

The ST40RA contains an EMPI and MPX arbiter and MPX clock control unit which are additional to
the bus interface components of the ST40 SOC range of devices.

I/O device driver

The Mailbox is a module with no ST legacy software.

5 System configuration

The ST40RA system address map has been designed to maintain compatibility with existing ST40
family devices and other STMicroelectronics devices.

The SH-4 core and core peripherals maintain compatibility with the ST40 SOC range of devices and
Hitachi SH7750 wherever possible.

Devices listed in Table 5: ST40RA system address map on page 26, are documented in the ST40
System Architecture Manual as described in Chapter 2: ST40 documentation suite on page 19.

Coherency between the cache and external memory is assured by software. The ST40 CPU has
cache control instructions which enable software to do this. Details of these instructions are given in
the ST40 CPU Core Architecture Manual.

The ST40RA is run in little endian mode.

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5 System configuration ST40RA

The ST40RA power on configuration is controlled by the MODE pins as defined in Table 37: Mode

selection pins for ST40RA on page 72.

Subsystem configuration registers are usually found with the module register space. Other system
level functions and the software register locations are shown in Table 14: System configuration

registers on page 36.

5.1 System addresses

The ST40 family system address organization is shown in Figure 3.

Figure 3: System address organization

0x1800 0000

Reserved

0x0000 0000
(standard ST40
physical boot
address)

EMI

0x1B00 0000

0x07F0 0000

0x0800 0000

0x0F00 0000

0x1000 0000

0x1700 0000

0x1800 0000

0x1C00 0000

0x1FFF FFFF

EMI control registers

System

peripherals

LMI

LMI control registers

Reserved

PCI

PCI control registers

Reserved

Area 7

peripherals

Memory address space

Device control register address space

Reserved address space

Core

0x1BFF FFFF

0x1C00 0000

0x1F00 0000

0x1FFF FFFF

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ST40RA 5 System configuration

5.1.1 System address map

Table 5: ST40RA system address map

Address

Module

a

Reference

Base Top

Standard bus interfaces ST40 System Architecture Manual Volume 2: Bus

Interfaces

EMI (FMI) 0x0000 0000 0x07EF FFFF

EMI control and buffer
registers

LMI 0x0800 0000 0x0EFF FFFF

LMI control registers 0x0F00 0000 0x0FFF FFFF

PCI 0x1000 0000 0x16FF FFFF

PCI control registers 0x1700 0000 0x17FF FFFF

Reserved 0x1800 0000 0x1AFF FFFF

ST40 core peripherals ST40 System Architecture Manual Volume 1: System

DMAC 0x1B00 0000 0x1B00 FFFF

PIO1 0x1B01 0000 0x1B01 FFFF

PIO2 0x1B02 0000 0x1B02 FFFF

0x07F0 0000 0x07FF FFFF

PIO3 0x1B03 0000 0x1B03 FFFF

CLOCKGEN 0x1B04 0000 0x1B04 FFFF

Interconnect 0x1B05 0000 0x1B05 FFFF

Reserved 0x1B06 0000 0x1B0F FFFF

CLOCKGENB 0x1B10 0000 0x1B10 FFFF

Reserved 0x1B11 0000 0x1B12 FFFF

EMPI 0x1B13 0000 0x1B13 7FFF ST40 System Architecture Manual Volume 2: Bus

Interfaces

MPXARB 0x1B13 8000 0x1B13 FFFF ST40 System Architecture Manual Volume 2: Bus

Interfaces

ST40RA additional peripherals ST40 System Architecture Manual Volume 4: I/O

Devices

MailBox 0x1B15 0000 0x1B15 FFFF

SYSCONF 0x1B19 0000 0x1B19 FFFF

Reserved 0x1B1A 0000 0x1B1F FFFF

Reserved for additional peripherals

Reserved 0x1B20 0000 0x1B3F FFFF

ST40 core peripherals ST40 System Architecture Manual Volume 1: System

INTC2 0x1E08 0000 0x1E0F FFFF

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5 System configuration ST40RA

Table 5: ST40RA system address map

Address

Module

a

Reference

Base Top

Reserved: CPU only
registers

CPG 0x1FC0 0000 0x1FC7 9999

RTC 0x1FC8 0000 0x1FCF FFFF

INTC 0x1FD0 0000 0x1FD7 9999

TMU 0x1FD8 0000 0x1FDF FFFF

SCIF1 0x1FE0 0000 0x1FE7 9999

SCIF2 0x1FE8 0000 0x1FEF FFFF

EMU 0x1FF0 0000 0x1FF7 9999

Reserved 0x1FF8 0000 0X1FFF FFFF

0x1E10 0000 0x1FBF FFFF

a. For information about which address region to access for each module, see SH-4 32-bit CPU Core

Architecture, sections 2.5 and 3.4

.

When operating in privilege mode, these registers should be accessed via the P2 region by adding
an offset of 0xA000 0000, when operating in user mode, access should be via the U0 address.

5.2 System identifiers

● SH-4 core processor identity: 0x0100.

● SH-4 core processor version: 0x0541D.

● ST40RA-HC8 TAP identity: 05141041.

● ST40RA-HC8 PCI identity:

➢ Vendor: 104A,

➢ Device: 4000,

➢ Revision ID: 0x01,

➢ Class: 0x4 0000,

➢ Subsystem ID: 0x0000.

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ST40RA 5 System configuration

5.3 Interrupt mapping

For full details on the interrupt controller see ST40 System Architecture Manual Volume 1:System.

The mapping of the CPU interrupts is described in Section 5.3.1, Section 5.3.2 and Section 5.3.3.

Note: Some INTEVT codes are shown as reserved in Ta bl e 6 and therefore cannot be generated by this

device.

5.3.1 ST40 core interrupt allocation

The allocation of core interrupts is as shown in Tab le 6 .

Table 6: ST40 core interrupt allocation (page 1 of 2)

Interrupt source

NMI 0x1C0 16 - - -

IRL

level
encoding

IRL3–IRL0 = F 0x200 15 - - -

IRL3–IRL0 = E 0x220 14 - - -

IRL3–IRL0 = D 0x240 13 - - -

IRL3–IRL0 = C 0x260 12 - - -

IRL3–IRL0 = B 0x280 11 - - -

IRL3–IRL0 = A 0x2A0 10 - - -

IRL3–IRL0 = 90x2C0 9 - - -

IRL3–IRL0 = 80x2E0 8 - - -

IRL3–IRL0 = 70x300 7 - - -

IRL3–IRL0 = 60x320 6 - - -

IRL3–IRL0 = 50x340 5 - - -

IRL3–IRL0 = 40x360 4 - - -

INTEVT

code

Interrupt priority

IPR

bit numbers

Priority

within IPR

setting unitValue Initial value

IRL3–IRL0 = 30x380 3 - - -

IRL3–IRL0 = 20x3A0 2 - - -

IRL3–IRL0 = 10x3C0 1 - - -

IRL

independent

encoding

H-UDI H-UDI 0x600 15 to 0 0 IPRC[3:0] -

TMU0 TUNI0 0x400 15 to 0 0 IPRA[15:12] -

TMU1 TUNI1 0x420 0 to 15 0 IPRA[11:8] -

TMU2 TUNI2 0x440

IRL0 0x240 15 to 0 13 IPRD[15:12] -

IRL1 0x2A0 15 to 0 10 IPRD[11:8] -

IRL2 0x300 15 to 0 7 IPRD[7:4] -

IRL3 0x360 15 to 0 4 IPRD[3:0] -

High

0 to 15 0 IPRA[7:4]

TICPI2 0x460 Low

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