ST ST3DV520E User Manual

Features

ST3DV520E

MUX/DEMUX for 4 differential channel LVDS and DDC

■ Low R

■ V

CC

■ Enhanced ESD protection: > 8 kV (contact) and

: 4.0 Ω typical

ON

operating range: 3.0 to 3.6 V

15 kV (HBM)

■ Channel on capacitance: 9.5 pF typical

■ Switching time speed: 9 ns

■ Near to zero propagation delay: 250 ps

■ Very low crosstalk: -45 dB at 250 MHz

■ Bit-to-bit skew: 200 ps

■ > 600 MHz -3 dB typical bandwidth (or data

frequency)

■ Support up to 4 differential LVDS channel

■ Support 2 channel for DDC

■ Independent SEL control for LVDS and DDC

channels

■ Package: QFN56

Applications

■ Audio/video switching

■ High bandwidth physical layer signals routing

QFN56

Description

The ST3DV520E is a 4 differential channel LVDS
multiplexer/demultiplexer low R
switch used to switch between multiple LVDS
sources. It is designed for very low crosstalk, low
bit-to-bit skew and low I/O capacitance, to
maintain high signal integrity.

bidirectional

ON

The differential signal from the LVDS transceiver
is multiplexed into one of two selected outputs
while the unselected switch goes to Hi-Z status.

The device integrates 2 SPDT (single pole dual
throw) switches, for DDC channel.

SEL for LVDS and DDC channel is controlled
independently.

Table 1. Device summary

Order code Package Packing

ST3DV520EQTR QFN56 Tape and reel

December 2010 Doc ID 18318 Rev 1 1/19

www.st.com

19

Contents ST3DV520E

Contents

1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.1 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

4 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

5 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2/19 Doc ID 18318 Rev 1

ST3DV520E Pin description

1 Pin description

Figure 1. Pin connection (top through view)

SEL1

6$$

DDC1

DDC2

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6$$

'.$$#

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NC

6$$"!

'.$

'.$

DDC1_0

DDC2_0

'.$

DDC1_1

DDC2_1

6$$

'.$

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&

('(

'

'.$

%

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6$$

$#$

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Table 2. Pin description

Pin Symbol Name and function

2, 3, 7, 8, 11, 12, 14, 15 A, B, C, D, E, F, G, H 8-bit bus

48, 47, 43, 42, 37, 36, 32, 31 A0, B0, C0, D0, E0, F0, G0, H0 8-bit multiplexed to bus 0

46, 45, 41, 40, 35, 34, 30, 29 A1, B1, C1, D1, E1, F1, G1, H1 8-bit multiplexed to bus 1

17 SEL1 LVDS channel selection

54 SEL2 DDC channel selection

6$$

'.$

SEL2

'.$

NC

NC

6$$

'.$

!

19, 20 DDC1, DDC2 DDC switch input

22, 23, 25, 26

DDC1_0, DDC2_0, DDC1_1,

4, 10, 18, 27, 38, 50, 56 V

1, 6, 9, 13, 16, 21, 24, 28, 33,

39, 44, 49, 53, 55

5, 51, 52 NC No internal connection

Doc ID 18318 Rev 1 3/19

DDC2_1

DD

DDC switch output

Supply voltage

GND Ground

Pin description ST3DV520E

Figure 2. Input equivalent circuit

SEL

A

B

A0

B0

A1

B1

C

D

C0

D0

C1

D1

E

F

E0

F0

E1

C

F1

G

H

G0

H0

G1

H1

DDC1

DDC2

SEL2

Table 3. LVDS switch function table

SEL1 Function

L 8-bit bus to 8-bit multiplexed bus 0

H 8-bit bus to 8-bit multiplexed bus 1

Table 4. DDC switch function table

SEL2 Function

L DDC switch input connected to DDC switch output X_0

H DDC switch input connected to DDC switch output X_1

DDC1_0

DDC1_1

DDC2_0

DDC2_1

AM08682V1

4/19 Doc ID 18318 Rev 1

ST3DV520E Maximum rating

2 Maximum rating

Stressing the device above the rating listed in the “absolute maximum ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.

Table 5. Absolute maximum ratings

Symbol Parameter Value Unit

V

CC

V

V

I

O

P

T

stg

T

1. If VIO x IO does not exceed the maximum limit of PD.

Supply voltage to ground -0.5 to 4.6 V

DC input output voltage -0.5 to 4.6 V

IO

DC control input voltage -0.5 to 4.6 V

IC

DC output current

Power dissipation 0.5 W

D

(1)

Storage temperature -65 to 150 °C

Lead temperature (10 sec) 300 °C

L

2.1 Recommended operating conditions

Table 6. Recommended operating conditions

Symbol Parameter

V

V

V

T

Supply voltage to ground 3 - 3.6 V

CC

DC control input voltage (SEL1, 2) 0 - V

IC

DC input/output voltage 0 - V

IO

Operating temperature -40 - 85 ° C

A

120 mA

Val ue

Min Typ Max

CC

CC

Unit

V

V

Doc ID 18318 Rev 1 5/19

Electrical characteristics ST3DV520E

3 Electrical characteristics

Table 7. DC electrical characteristics

Symbol Parameter Test condition

Voltage input high (SEL1,

2)

Voltage input low
(SEL1, 2)

Clamp diode voltage
(SEL1, 2)

Input high current
(SEL1, 2)

Input low current
(SEL1, 2)

Leakage current through
the switch common

(1)

terminals (A to H)
(DDC1 to DDC2)

High level guaranteed 2.4 - - V

Low level guaranteed -0.5 - 0.8 V

VCC = 3.6 V

= -18 mA

I

IN

VCC = 3.6 V

= V

V

IN

CC

V

= 3.6 V

CC

= GND

V

IN

= 3.6 V

V

CC

A to H = V

CC

DDC1 to DDC2 = V
A0 to H0 = 0 V
A1 to H1 = floating
DDCx_0=0V

IOFF

V

V

V

I

I

IH

IL

IK

IH

IL

(SW)

DDCx1 = floating

IOFF

(SEL1)

SEL1 pin leakage current

SEL1 = V

V

CC

SEL1, 2 = 0 to 3.6 V

= 0 V

, SEL2 = V

CC

VCC = 3.0 V

R

ON

Switch ON resistance

(2)

= 1.5 to V

V

IN

IIN = -40 mA

VCC = 3.0 V

R

ΔR

FLAT

ON

ON resistance flatness

(3)

ON resistance match
between channel

ΔR

= R

ON

(2)(4)

ONMAX-RONMIN

(2)

at 1.5 and VCC

V

IN

= -40 mA

I

IN

VCC = 3.0 V
VIN = 1.5 to V
IIN = -40 mA

CC

CC

CC

CC

Val ue

Min Typ Max

- -0.8 -1.2 V

--±5µA

--±5µA

--±1µA

--±1

-4.06.5Ω

-0.5-Ω

-0.41Ω

Unit-40 to 85 °C

µA

1. Refer to Figure 4: Test circuit for leakage current (IOFF) on page 9

2. Measured by voltage drop between channels at indicated current through the switch. ON resistance is determined by the
lower of the voltages.

3. Flatness is defined as the difference between the R

ΔR

4.

measured at same VCC, temperature and voltage level.

ON

ONMAX

and R

of ON resistance over the specified range.

ONMIN

6/19 Doc ID 18318 Rev 1