ST ST24E64, ST25E64 User Manual

ST24E64EB1TR

ST24E64

ST25E64

SERIAL EXTENDED ADDRESSING COMPATIBLE WITH I2C BUS 64K (8K x 8) EEPROM

COMPATIBLE with I2C EXTENDED ADDRESSING

TWO WIRE SERIAL INTERFACE, SUPPORTS 400kHz PROTOCOL

1 MILLION ERASE/WRITE CYCLES, OVER the FULL SUPPLY VOLTAGE RANGE

40 YEARS DATA RETENTION

SINGLE SUPPLY VOLTAGE

±4.5V to 5.5V for ST24E64 version

±2.5V to 5.5V for ST25E64 version WRITE CONTROL FEATURE

BYTE and PAGE WRITE (up to 32 BYTES)

BYTE, RANDOM and SEQUENTIAL READ MODES

SELF TIMED PROGRAMING CYCLE AUTOMATIC ADDRESS INCREMENTING

ENHANCED ESD/LATCH UP PERFORMANCES

PRELIMINARY DATA

8	8
1	1
PSDIP8 (B)	SO8 (M)
0.25mm Frame	200mil Width

Figure 1. Logic Diagram

VCC

DESCRIPTION

The ST24/25E64 are 64K bit electrically erasable programmable memories (EEPROM), organized as 8 blocks of 1024 x 8 bits. The ST25E64 operates with a power supply value as low as 2.5V. Both Plastic Dual-in-Line and Plastic Small Outline packages are available.

Table 1. Signal Names

E0 - E2	Chip Enable Inputs
SDA	Serial Data Address Input/Output
SCL	Serial Clock
WC	Write Control
VCC	Supply Voltage
VSS	Ground

3

E0-E2

SDA

ST24E64

SCL ST25E64

WC

VSS

AI01204B

November 1996

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This is preliminary information on a new product now in development or undergoing evaluatio n.Details are subject to change without notice.

ST24E64, ST25E64

Figure 2A. DIP Pin Connections

Figure 2B. SO Pin Connections

	ST24E64				ST24E64
	ST25E64				ST25E64
E0	1	8	VCC	E0	1	8	VCC
E1	2	7	WC	E1	2	7	WC
E2	3	6	SCL	E2	3	6	SCL
VSS	4	5	SDA	VSS	4	5	SDA
		AI01205B				AI01206C

Table 2. Absolute Maximum Ratings (1)

Symbol		Parameter		Value	Unit
TA	Ambient Operating Temperature			±40 to 125	°C
TSTG	Storage Temperature			±65 to 150	°C
TLEAD	Lead Temperature, Soldering	(SO8)	40 sec	215	°C
		(PSDIP8)	10 sec	260
VIO	Input or Output Voltages			±0.6 to 6.5	V
VCC	Supply Voltage			±0.3 to 6.5	V
VESD	Electrostatic Discharge Voltage (Human Body model) (2)			4000	V
	Electrostatic Discharge Voltage (Machine model) (3)
				500	V

Notes: 1. Except for the rating ºOperating Temperature Rangeº, stresses above those listed in the Table ºAbsolute Maximum Ratingsº may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the SGS-THOMSON SURE Program and other relevant quality documents.

2.100pF through 1500Ω; MIL-STD-883C, 3015.7

3.200pF through 0Ω; EIAJ IC-121 (condition C)

DESCRIPTION (cont'd)

Each memory is compatible with the I2C extended addressing standard, two wire serial interface which uses a bi-directional data bus and serial clock. The ST24/25E64carry a built-in 4 bit, unique device identification code (1010) corresponding to the I2C bus definition. The ST24/25E64 behave as

slave devices in the I2C protocol with all memory operations synchronized by the serial clock. Read and write operations are initiated by a START conditiongenerated by the bus master. The START condition is followed by a stream of 4 bits (identification code 1010), 3 bit Chip Enable input to form a 7 bit Device Select, plus one read/write bit and terminated by an acknowledge bit.

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ST24E64, ST25E64

Table 3. Device Select Code

		Device Code				Chip Enable		RW
Bit	b7	b6	b5	b4	b3	b2	b1	b0
Device Select	1	0	1	0	E2	E1	E0	RW

Note: The MSB b7 is sent first.

Table 4. Operating Modes

Mode	RW bit	Bytes	Initial Sequence
Current Address Read	'1'	1	START, Device Select, RW = '1'
Random Address Read	'0'	1	START, Device Select, RW = '0', Address,
	'1'		reSTART, Device Select, RW = '1'
Sequential Read	'1'	1 to 8192	As CURRENT or RANDOM Mode
Byte Write	'0'	1	START, Device Select, RW = '0'
Page Write	'0'	32	START, Device Select, RW = '0'

When writing data to the memory it responds to the 8 bits received by asserting an acknowledge bit during the 9th bit time. When data is read by the bus master, it acknowledges the receipt of the data bytes in the same way.

Data transfers are terminated with a STOP condition. In this way, up to 8 ST24/25E64 may be connected to the same I2C bus and selected individually, allowing a total addressing field of 512 Kbit.

Power On Reset: VCC lock out write protect. In order to prevent data corruption and inadvertent write operations during power up, a Power On Reset (POR) circuit is implemented. Untill the VCC voltage has reached the POR threshold value, the internal reset is active: all operations are disabled and the device will not respond to any command. In the same way, when VCC drops down from the operating voltage to below the POR threshold value, all operations are disabled and the device will not respond to any command. A stable VCC must be applied before applying any logic signal.

SIGNALS DESCRIPTION

Serial Clock (SCL). The SCL input pin is used to synchronize all data in and out of the memory. A

resistor can be connected from the SCL line to VCC to act as a pull up (see Figure 3)

Serial Data (SDA). The SDA pin is bi-directional and is used to transfer data in or out of the memory. It is an open drain output that may be wire-OR'ed with other open drain or open collector signals on the bus. Aresistor must be connectedfrom the SDA bus line to VCC to act as pull up (see Figure 3).

Chip Enable (E0 - E2). These chip enable inputs are used to set the 3 least significant bits of the 7 bit device select code. They may be driven dynamically or tied to VCC or VSS to establish the device select code. Note that the VIL and VIH levels for the inputs are CMOS, not TTL compatible.

Write Control (WC). The Write Control feature WC is useful to protect the contents of the memory from any erroneous erase/write cycle. The Write Control signal is used to enable (WC at VIH) or disable (WC at VIL) the internal write protection. When pin WC is unconnected, the WC input is internally read as VIL (see Table 5).

When WC = '1', Device Select and Address bytes are acknowledged; Data bytes are not acknowledged.

Refer to the AN404 Application Note for more detailed information about Write Control feature.

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ST24E64, ST25E64

Figure 3. Maximum RL Value versus Bus Capacitance (CBUS) for an I2C Bus, fC = 400kHz

RL max (kΩ)

20
			VCC
16
				RL	RL
12				SDA
			MASTER	SCL	CBUS
8
					CBUS
4
VCC = 5V
0
25	50	75	100
	CBUS (pF)				AI01115

DEVICE OPERATION

I2C Bus Background

The ST24/25E64support the extended addressing I2C protocol. This protocol defines any device that sends data onto the bus as a transmitter and any device that reads the data as a receiver. The device that controls the data transfer is known as the master and the other as the slave. The master will always initiate a data transfer and will provide the serial clock for synchronisation. The ST24/25E64 are always slave devices in all communications.

Start Condition. START is identified by a high to low transition of the SDA line while the clock SCL is stable in the high state. A START condition must precede any command for data transfer. Except during a programming cycle, the ST24/25E64 continuously monitor the SDA and SCL signals for a START condition and will not respond unless one is given.

Stop Condition. STOPis identified by a low to high transition of the SDA line while the clock SCL is stable in the high state. A STOP condition terminates communication between the ST24/25E64 and the bus master. A STOP condition at the end of a Read command forces the standby state. A

STOP condition at the end of a Write command triggers the internal EEPROM write cycle.

Acknowledge Bit (ACK). An acknowledge signal is used to indicate a successful data transfer. The bus transmitter, either master or slave, will release the SDA bus after sending 8 bits of data. During the 9th clock pulse the receiver pulls the SDA bus low to acknowledge the receipt of the 8 bits of data.

Data Input. During data input the ST24/25E64 sample the SDA bus signal on the rising edge of the clock SCL. For correct device operation the SDA signal must be stable during the clock low to high transition and the data must change ONLY when the SCL line is low.

Device Selection. To start communication between the bus master and the slave ST24/25E64, the master must initiate a START condition. The 8 bits sent after a START condition are made up of a device select of 4 bits that identifies the device type, 3 Chip Enable bits and one bit for a READ (RW = 1) or WRITE (RW = 0) operation. There are two modes both for read and write. These are summarised in Table 4 and described hereafter. A communication between the master and the slave is ended with a STOP condition.

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ST24E64, ST25E64

Table 5. Input Parameters (1)	(TA = 25 °C, f = 400 kHz )
Symbol	Parameter	Test Condition	Min	Max	Unit

CIN

CIN

ZWCL

ZWCH

tLP

Input Capacitance (SDA)			8	pF
Input Capacitance (other pins)			6	pF
WC Input Impedance	VIN ≤ 0.3 VCC	5	20	kΩ
WC Input Impedance	VIN ≥ 0.7 VCC	500		kΩ
Low-pass filter input time constant			100	ns
(SDA and SCL)

Note: 1. Sampled only, not 100% tested.

Table 6. DC Characteristics

(TA = ±40 to 85 °C or 0 to 70 °C; VCC = 4.5V to 5.5V or 2.5V to 5.5V)

Symbol

ILI

ILO

ICC

ICC1

ICC2

VIL

VIH

VIL

VIH

VOL

Parameter

Input Leakage Current

(SCL, SDA, E0-E2)

Output Leakage Current

Supply Current (ST24 series) Supply Current (ST25 series)

Supply Current (Standby) (ST24 series)

Supply Current (Standby) (ST25 series)

Input Low Voltage (SCL, SDA)

Input High Voltage (SCL, SDA)

Input Low Voltage (E0-E2, WC)

Input High Voltage (E0-E2, WC)

Output Low Voltage

Output Low Voltage (ST25 series)

Test Condition	Min	Max	Unit
0V ≤ VIN ≤ VCC		±2	μA
0V ≤ VOUT ≤ VCC		±2	μA
SDA in Hi-Z
fC = 400kHz		2	mA
(Rise/Fall time < 30ns)		1	mA
VIN = VSS or VCC,		100	μA
VCC = 5V
VIN = VSS or VCC,		300	μA
VCC = 5V, fC = 400kHz
VIN = VSS or VCC,		5	μA
VCC = 2.5V
VIN = VSS or VCC,		50	μA
VCC = 2.5V, fC = 400kHz
	±0.3	0.3 VCC	V
	0.7 VCC	VCC + 1	V
	±0.3	0.5	V
	VCC ± 0.5	VCC + 1	V
IOL = 3mA, VCC = 5V		0.4	V
IOL = 2.1mA, VCC = 2.5V		0.4	V

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