ST ST24LC21B User Manual

ST24LC21B, ST24LW21 ST24FC21, ST24FC21B, ST24FW21

1 Kbit (x8) Dual Mode Serial EEPROM for VESA PLUG & PLAY

1 MILLION ERASE/WRITE CYCLES

40 YEARS DATA RETENTION

3.6V to 5.5V or 2.5V to 5.5V SINGLE SUPPLY VOLTAGE

HARDWARE WRITE CONTROL (ST24LW21 and ST24FW21)

TTL SCHMITT-TRIGGER on VCLK INPUT

100k / 400k Hz COMPATIBILITY with the I2C BUS BIT TRANSFER RANGE

TWO WIRE SERIAL INTERFACE I2C BUS COMPATIBLE

I2C PAGE WRITE (up to 8 Bytes)

I2C BYTE, RANDOM and SEQUENTIAL READ MODES

SELF TIMED PROGRAMMING CYCLE

AUTOMATIC ADDRESS INCREMENTING

ENHANCED ESD/LATCH UP PERFORMANCES

ERROR RECOVERY MECHANISM

(ST24FC21 and ST24FW21) VESA 2 COMPATIBLE

DESCRIPTION

The ST24LC21B, ST24LW21, ST24FC21, ST24FC21B and ST24FW21 are 1K bit electrically erasable programmable memory (EEPROM), organized in 128x8 bits. In the text, products are referred as ST24xy21, where "x" is either "L" for VESA 1 or "F" for VESA 2 compatible memories and where "y" indicates the Write Control pin connection: "C" means WC on pin 7 and "W" means WC on pin 3.

Table 1. Signal Names

SDA	Serial Data Address Input/Output

SCL	Serial Clock (I2C mode)
VCC	Supply Voltage

VSS	Ground

VCLK	Clock Transmit only mode

WC	Write Control

8	8
1	1
PSDIP8 (B)	SO8 (M)
0.25mm Frame	150mil Width

Figure 1. Logic Diagram

VCC

SCL	SDA

VCLK ST24xy21

VSS

AI01741

Note: WC signal is only available for ST24LW21 and ST24FW21 products.

June 2002

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ST24LC21B, ST24LW21, ST24FC21, ST24FC21B, ST24FW21

Figure 2A. DIP Pin Connections

	ST24LC21B
NC	1		8	VCC


NC	2		7	VCLK
NC	3		6	SCL

VSS		4	5	SDA


			AI01742

Warning: NC = Not Connected.

Figure 2C. DIP Pin Connections

ST24FC21

ST24FC21B

NC	1	8	VCC
NC	2	7	VCLK
DU	3	6	SCL
VSS	4	5	SDA
		AI01744

Figure 2B. SO Pin Connections

	ST24LC21B

NC		1	8	VCC
NC		2	7	VCLK
NC		3	6	SCL
VSS		4	5	SDA
			AI01743

Warning: NC = Not Connected.

Figure 2D. SO Pin Connections

ST24FC21

ST24FC21B

NC	1	8	VCC
NC	2	7	VCLK
DU	3	6	SCL
VSS	4	5	SDA
		AI01745

Warning: NC = Not Connected. DU = Don’t Use, must be left open or connected to VCC or VSS.

Figure 2E. DIP Pin Connections				Figure 2F. SO Pin Connections
	ST24FW21				ST24FW21
	ST24LW21				ST24LW21
		8
NC	1	8	VCC	NC	1	8	VCC
NC	2	7	VCLK	NC	2	7	VCLK
WC	3	6	SCL	WC	3	6	SCL
VSS	4	5	SDA	VSS	4	5	SDA
		AI01746				AI01747

Warning: NC = Not Connected.				Warning: NC = Not Connected.

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ST24LC21B, ST24LW21, ST24FC21, ST24FC21B, ST24FW21

Table 2. Absolute Maximum Ratings (1)

Symbol		Parameter		Value	Unit

TA	Ambient Operating Temperature			–40 to 85	°C

TSTG	Storage Temperature			–65 to 150	°C

TLEAD	Lead Temperature, Soldering	(SO8 package)	40 sec	215	°C
		(PSDIP8 package)	10 sec	260	°C
		(PSDIP8 package)	10 sec	260

VIO	Input or Output Voltages			–0.3 to 6.5	V

VCC	Supply Voltage			–0.3 to 6.5	V

VESD	Electrostatic Discharge Voltage (Human Body model) (2)			4000	V
VESD	Electrostatic Discharge Voltage (Machine model) (3)			500	V
	Electrostatic Discharge Voltage (Machine model) (3)			500	V

Notes: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and operation of thedevice at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum

Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.

2.MIL-STD-883C, 3015.7 (100pF, 1500 Ω ).

3.EIAJ IC-121 (Condition C) (200pF, 0 Ω ).

Table 3A. Device Select Code (ST24LC21B, ST24LW21, ST24FC21 and ST24FW21)

Device Code

Chip Enable

Bit

Device Select

Note: The MSB b7 is sent first.

X = 0 or 1.

Table 3B. Device Select Code (ST24FC21B)


		Device Code				Chip Enable			RW

Bit	b7	b6	b5	b4	b3		b2	b1	b0

Device Select	1	0	1	0	0		0	0
Device Select	1	0	1	0	0		0	0	RW

Note: The MSB b7 is sent first.

X = 0 or 1.

DESCRIPTION (cont’d)

The ST24xy21 can operate in two modes: Trans- mit-Only mode and I2C bidirectional mode. When powered, the device is in Transmit-Only mode with EEPROM data clocked out from the rising edge of the signal applied on VCLK.

The device will switch to the I2C bidirectional mode upon the falling edge of the signal applied on SCL pin. When in I2C mode, the ST24LC21B (or the ST24LW21) cannot switch back to the Transmit Only mode (except when the power supply is removed). For the ST24FC21, ST24FC21B (or the ST24FW21), after the falling edge of SCL, the memory enter in a transition state which allowed to

switch back to the Transmit-Only mode if no valid I2C activity is observed. Both Plastic Dual-in-Line and Plastic Small Outline packages are available.

Transmit Only Mode

After a Power-up, the ST24xy21 is in the Transmit Only mode. A proper initialization sequence (see Figure 3) must supply nine clock pulses on the VCLK pin (in order to internally synchronize the device). During this initialization sequence, the SDA pin is in high impedance. On the rising edge of the tenth pulse applied on VCLK pin, the device will output the first bit of byte located at address 00h (most significant bit first).

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ST24LC21B, ST24LW21, ST24FC21, ST24FC21B, ST24FW21

Figure 3. Transmit Only Mode Waveforms

VCC
SCL
SDA						Bit 7		Bit 6
	tVPU
VCLK	1	2		8	9	10	11
VCC
SCL
SDA	Bit 6	Bit 5	Bit 4		Bit 0		Bit 7	Bit 6
VCLK	12		13	17	18	19		20
								AI01501
Table 4. I2C Operating Modes

ST24LC21B

ST24LW21

Mode

ST24FC21

ST24FW21

Bytes

Initial Sequence

bit

ST24FC21B

VCLK

Current Address

’1’

START, Device Select, RW = ’1’

Read

’0’

Random Address

START, Device Select, RW

= ’0’, Address,

Read

’1’

reSTART, Device Select, RW = ’1’

Sequential Read

’1’

1 to 128

Similar to Current or Random Mode

Byte Write

’0’

VIH

START, Device Select, RW

= ’0’

Page Write

’0’

VIH

START, Device Select, RW

= ’0’

Note: X = VIH or VIL

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ST24LC21B, ST24LW21, ST24FC21, ST24FC21B, ST24FW21

Figure 4. Transition from Transmit Only (DDC1) to Bi-directional (DDC2B) Mode Waveforms

Transmit Only Mode	- Temporary Bi-Directional Mode			- Locked Bi-Directional
	(ST24FC21 and ST24FW21)			Mode (ST24FC21
	- Locked Bi-Directional Mode			and ST24FW21)
	(ST24LC21B and ST24LW21)
SCL	1	2	8	9
SDA	MSB			ACK

VCLK

START

CONDITION

AI01892

A byte is clocked out (on SDA pin) with nine clock pulses on VCLK: 8 clock pulses for the data byte and one extra clock pulse for a Don’t Care bit.

As long as the SCL pin is held high, each byte of the memory array is transmitted serially on the SDA pin with an automatic address increment.

When the last byte is transmitted, the address counter will roll-over to location 00h.

I2C Bidirectional Mode

The ST24xy21 can be switched from Transmit Only mode to I2C Bidirectional mode by applying a valid high to low transition on the SCL pin (see Figure 4).

–When the ST24LC21B (or the ST24FC21 or the ST24FC21B) is in the I2C Bidirectional mode, the VCLK input (pin 7) enables (or inhibits) the execution of any write instruction: if VCLK = 1, write instructions are executed; if VCLK = 0, write instructions are not executed.

–When the ST24LW21 (or the ST24FW21) is in the I2C Bidirectional mode, the Write Control (WC on pin 3) input enables (or inhibits) the execution of any write instruction: if WC = 1, write instructions are executed;if WC = 0, write instructions are not executed.

The ST24xy21 is compatible with the I2C standard, two wire serial interface which uses a bidirectional data bus and serial clock. The ST24xy21 carries a built-in 4 bit, unique device identification code (1010) named Device Select code corresponding to the I2C bus definition. The ST24LC21B carries a unique device identification code (1010.0000 RW)

named Device Select code corresponding to the I2C bus definition.

The ST24xy21 behaves as a slave device in the I2C protocol with all memory operations synchronized by the serial clock SCL. Read and write operations are initiated by a START condition generated by the bus master. TheSTART condition is followed by a stream of 7 bits, plus one read/write bit and terminated by an acknowledge bit.

When data is written into the memory, the ST24xy21 responds to the 8 bits received by asserting an acknowledge bit during the 9th bit time. When data is read by the bus master, it must acknowledge the receipt of the data bytes in the same way. Data transfers are terminated with a STOP condition (see READ and WRITE descriptions in the following pages).

Power On Reset: VCC lock out write protect

In order to prevent data corruption and inadvertent write operations during power up, a Power On Reset (POR) circuit is implemented. Until the VCC voltage has reached the POR threshold value, the internal reset is active, all operations are disabled and the device will not respond to any command. In the same way, when VCC drops down from the operating voltage to below the POR threshold value, all operations are disabled and the device will not respond to any command. A stable VCC must be applied before applying any logic signal.

Error Recovery Modes available in the ST24FC21, ST24FC21B and the ST24FW21

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ST24LC21B, ST24LW21, ST24FC21, ST24FC21B, ST24FW21

Figure 5. Error Recovery Mechanism Flowchart for the ST24FC21, ST24FC21B and ST24FW21 products

Memory Power On

Internal Address Pointer = 0

VCLK YES

NO SCL

YES

SDA Hi-Z

VCLK Internal Counter = 0

Start Internal 2 sec Timer

			Transmit-Only Mode
	Send Data bit (MSB first) pointed		Transmit-Only Mode
	Send Data bit (MSB first) pointed		(DDC1)
	by the Address Pointer and		(DDC1)
	by the Address Pointer and
	auto-increment pointed bit/byte

		SCL	YES
		NO		Reset VCLK Internal Counter
		NO		and Reset Internal Timer
				and Reset Internal Timer
		Valid
		I2C access		YES
	(START + Device Select)			YES
	(START + Device Select)
Transition		?
Transition
State
(VESA 2)				I2C communication idle
				I2C communication idle
	NO	VCLK		waiting for a Device Select byte
	NO	VCLK
		YES		Reset Counter and Timer	I2C Mode
	Increment VCLK Counter				(DDC2B)
	Increment VCLK Counter
				Send Acknowledge
NO	Counter = 128			Respond to the Incoming
	or Timer > 2 sec			I2C Command
		YES
	Switch Back to
	Transmit-Only Mode
				AI01748

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ST24LC21B, ST24LW21, ST24FC21, ST24FC21B, ST24FW21

Figure 6. Maximum RL Value versus Bus Capacitance (CBUS) for an I2C Bus

Maximum RP value (kΩ )

VCC

SDA

CBUS

MASTER

SCL

fc = 100kHz

fc = 400kHz

CBUS

100

1000

CBUS (pF)

AI01665

When the ST24FC21 (or the ST24FC21B or the ST24FW21) first switches to the I2C mode (VESA DDC2B mode), it enters a transition state which is functionally identical to I2C operation. But, if the ST24FC21 (or the ST24FC21B or the ST24FW21) does not receive a valid I2C sequence, that is a START condition followed by a valid Device Select code (1010XXX RW for ST24FC21 and ST24FW21; 1010000 RW for ST24FC21B), within either 128 VCLK periods or a period of time of tRECOVERY (approximately 2 seconds), the ST24FC21 (or the ST24FC21B or the ST24FW21) will revert to the Transmit-Only mode (VESA DDC1 mode).

If the ST24FC21 (or the ST24FC21B or the ST24FW21) decodes a valid I2C Device Select code, it will lock into I2C mode. Under this condition, signals applied on the VCLK input will not disturb READ access from the ST24FC21 (or the ST24FC21B or the ST24FW21). For WRITE access, refer to the Signal Description paragraph.

When in the transition state, the count of VCLK pulses and the internal 2 seconds timer are reset by any activity on the SCL line. This means that, after each high to low transition on SCL, the memory will re-initialise its transition state and will switch back to Transmit-Only mode only after 128 more VCLK pulses or after a new tRECOVERY delay.

SIGNAL DESCRIPTIONS

I2C Serial Clock (SCL). The SCL input pin is used to synchronize all data in and out of the memory. A resistor can be connected from the SCL line to VCC to act as a pull up (see Figure 6).

Serial Data (SDA). The SDA pin is bi-directional and is used to transfer data in or out of the memory. It is an open drain output that may be wire-OR’ed with other open drain or open collector signals on the bus. A resistor must be connected from the SDA bus line to VCC to act as pull up (see Figure 6).

Transmit Only Clock (VCLK). The VCLK input pin is used to synchronize data out when the ST24xy21 is in Transmit Only mode.

For the ST24LC21B and the ST24FC21 or ST24FC21B Only, the VCLK offers also a Write Enable (active high) function when the ST24LC21B and the ST24FC21 or ST24FC21B are in I2C bidirectional mode.

Write Control (WC). An hardware Write Control feature (WC) is offered only on ST24LW21 and ST24FW21 on pin 3. This feature is usefull to protect the contents of the memory from any erroneous erase/write cycle. The Write Control signal is used to enable (WC = VIL) or disable (WC = VIH) the internal write protection. When unconnected, the WC input is internally tied to VSS by a 100k ohm pull-down resistor and the memory is write protected.

DEVICE OPERATION

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