ST ST24C08, ST25C08, ST24W08, ST25W08 User Manual

ST24C08

ST24C08, ST25C08

ST24W08, ST25W08

8 Kbit Serial I2C Bus EEPROM with User-Defined Block Write Protection

1 MILLION ERASE/WRITE CYCLES with 40 YEARS DATA RETENTION

SINGLE SUPPLY VOLTAGE:

–3V to 5.5V for ST24x08 versions

–2.5V to 5.5V for ST25x08 versions

HARDWARE WRITE CONTROL VERSIONS: ST24W08 and ST25W08

PROGRAMMABLE WRITE PROTECTION

TWO WIRE SERIAL INTERFACE, FULLY I2C BUS COMPATIBLE

BYTE and MULTIBYTE WRITE (up to 8 BYTES)

PAGE WRITE (up to 16 BYTES)

BYTE, RANDOM and SEQUENTIAL READ MODES

SELF TIMED PROGRAMMING CYCLE

AUTOMATIC ADDRESS INCREMENTING

ENHANCED ESD/LATCH UP PERFORMANCES

DESCRIPTION

This specification covers a range of 8 Kbits I2C bus EEPROM products, the ST24/25C08 and the ST24/25W08. In the text, products are referred to as ST24/25x08, where "x" is: "C" for Standard version and "W" for Hardware Write Control version.

Table 1. Signal Names

	PRE		Write Protect Enable
	E		Chip Enable Input
	SDA		Serial Data Address Input/Output
	SCL		Serial Clock
	MODE		Multibyte/Page Write Mode
			(C version)
			Write Control (W version)
	WC
	VCC		Supply Voltage
	VSS		Ground

8	8
1	1
PSDIP8 (B)	SO8 (M)
0.25mm Frame	150mil Width

Figure 1. Logic Diagram

VCC

	E								SDA
PRE					ST24x08
SCL					ST25x08
MODE/WC*

VSS

AI00860E

Note: WC signal is only available for ST24/25W08 products.

February 1999

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ST24/25C08, ST24/25W08

Figure 2A. DIP Pin Connections

Figure 2B. SO Pin Connections

ST24x08

ST24x08

ST25x08

ST25x08

8

PRE

1

VCC

PRE

1

8

VCC

NC

2

7

MODE/WC

NC

2

7

MODE/WC

E

3

6

SCL

E

3

6

SCL

VSS

4

5

SDA

VSS

4

5

SDA

AI00861E

AI01073E

Warning: NC = Not Connected.

Warning: NC = Not Connected.

Table 2. Absolute Maximum Ratings (1)

Symbol

Parameter

Value

Unit

TA

Ambient Operating Temperature

–40 to 125

°C

TSTG

Storage Temperature

–65 to 150

°C

TLEAD

Lead Temperature, Soldering

(SO8 package)

40 sec

215

°C

(PSDIP8 package)

10 sec

260

VIO

Input or Output Voltages

–0.6 to 6.5

V

VCC

Supply Voltage

–0.3 to 6.5

V

VESD

Electrostatic Discharge Voltage (Human Body model) (2)

4000

V

Electrostatic Discharge Voltage (Machine model) (3)

500

V

Notes: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum

Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.

2.MIL-STD-883C, 3015.7 (100pF, 1500 Ω).

3.EIAJ IC-121 (Condition C) (200pF, 0 Ω).

DESCRIPTION (cont’d)

The ST24/25x08 are 8 Kbit electrically erasable programmable memories (EEPROM), organized as 4 blocks of 256 x8 bits. They are manufactured in STMicroelectronics’s Hi-Endurance Advanced CMOS technology which guarantees an endurance of one million erase/write cycles with a data retention of 40 years.

Both Plastic Dual-in-Line and Plastic Small Outline packages are available.

The memories are compatible with the I2C standard, two wire serial interface which uses a bi-direc-

tional data bus and serial clock. The memories carry a built-in 4 bit, unique device identification code (1010) corresponding to the I2C bus definition. This is used together with 1 chip enable input

(E) so that up to 2 x 8K devices may be attached to the I2C bus and selected individually. The memories behave as a slave device in the I2C protocol with all memory operations synchronized by the serial clock. Read and write operations are initiated by a START condition generated by the bus master. The START condition is followed by a stream of 7 bits (identification code 1010), plus one read/write bit and terminated by an acknowledge bit.

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ST24/25C08, ST24/25W08

Table 3. Device Select Code

					Chip		Block
		Device Code							RW
					Enable		Select
Bit	b7	b6	b5	b4	b3	b2		b1	b0
Device Select	1	0	1	0	E	A9		A8
									RW

Note: The MSB b7 is sent first.

Table 4. Operating Modes (1)

Mode	RW bit			MODE	Bytes	Initial Sequence
Current Address Read		’1’		X	1
						START, Device Select, RW			= ’1’
		’0’
Random Address Read				X	1	START, Device Select, RW			= ’0’, Address,
		’1’
						reSTART, Device Select, RW				= ’1’
Sequential Read		’1’		X	1 to 1024	Similar to Current or Random Mode
Byte Write		’0’		X	1
						START, Device Select, RW			= ’0’
Multibyte Write (2)		’0’		VIH	8
						START, Device Select, RW			= ’0’
Page Write		’0’		VIL	16
						START, Device Select, RW			= ’0’

Notes: 1. X = VIH or VIL

2. Multibyte Write not available in ST24/25W08 versions.

When writing data to the memory it responds to the 8 bits received by asserting an acknowledge bit during the 9th bit time. When data is read by the bus master, it acknowledges the receipt of the data bytes in the same way. Data transfers are terminated with a STOP condition.

Power On Reset: VCC lock out write protect. In order to prevent data corruption and inadvertent write operations during power up, a Power On Reset (POR) circuit is implemented. Until the VCC voltage has reached the POR threshold value, the internal reset is active, all operations are disabled and the device will not respond to any command. In the same way, when VCC drops down from the operating voltage to below the POR threshold value, all operations are disabled and the device will not respond to any command. A stable VCC must be applied before applying any logic signal.

SIGNAL DESCRIPTIONS

Serial Clock (SCL). The SCL input pin is used to synchronize all data in and out of the memory. A resistor can be connected from the SCL line to VCC to act as a pull up (see Figure 3).

Serial Data (SDA). The SDA pin is bi-directional and is used to transfer data in or out of the memory. It is an open drain output that may be wire-OR’ed

with other open drain or open collector signals on the bus. A resistor must be connected from the SDA bus line to VCC to act as pull up (see Figure 3).

Chip Enable (E). This chip enable input is used to set one least significant bit (b3) of the device select byte code. This input may be driven dynamically or tied to VCC or VSS to establish the device select code.

Protect Enable (PRE). The PRE input pin, in addition to the status of the Block Address Pointer bit (b2, location 3FFh as in Figure 7), sets the PRE write protection active.

Mode (MODE). The MODE input is available on pin 7 (see also WC feature) and may be driven dynamically. It must be at VIL or VIH for the Byte Write mode, VIH for Multibyte Write mode or VIL for Page Write mode. When unconnected, the MODE input is internally read as a VIH (Multibyte Write mode).

Write Control (WC). An hardware Write Control (WC) feature is offered only for ST24W08 and ST25W08 versions on pin 7. This feature is usefull to protect the contents of the memory from any erroneous erase/write cycle. The Write Control sig- nal is used to enable (WC = VIH) or disable (WC = VIL) the internal write protection. When unconnected, the WC input is internally read as VIL and the memory area is not write protected.

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ST24/25C08, ST24/25W08

SIGNAL DESCRIPTIONS (cont’d)

The devices with this Write Control feature no longer support the Multibyte Write mode of operation, however all other write modes are fully supported.

Refer to the AN404 Application Note for more detailed information about Write Control feature.

DEVICE OPERATION

I2C Bus Background

The ST24/25x08 support the I2C protocol. This protocol defines any device that sends data onto the bus as a transmitter and any device that reads the data as a receiver. The device that controls the data transfer is known as the master and the other as the slave. The master will always initiate a data transfer and will provide the serial clock for synchronisation. The ST24/25x08 are always slave devices in all communications.

Start Condition. START is identified by a high to low transition of the SDA line while the clock SCL is stable in the high state. A START condition must precede any command for data transfer. Except during a programming cycle, the ST24/25x08 continuously monitor the SDA and SCL signals for a START condition and will not respond unless one is given.

Stop Condition. STOP is identified by a low to high transition of the SDA line while the clock SCL is stable in the high state. A STOP condition terminates communication between the ST24/25x08 and the bus master. A STOP condition at the end of a Read command, after and only after a No Acknowledge, forces the standby state. A STOP condition at the end of a Write command triggers the internal EEPROM write cycle.

Acknowledge Bit (ACK). An acknowledge signal is used to indicate a successfull data transfer. The bus transmitter, either master or slave, will release the SDA bus after sending 8 bits of data. During the 9th clock pulse period the receiver pulls the SDA bus low to acknowledge the receipt of the 8 bits of data.

Data Input. During data input the ST24/25x08 sample the SDA bus signal on the rising edge of the clock SCL. Note that for correct device operation the SDA signal must be stable during the clock low to high transition and the data must change ONLY when the SCL line is low.

Memory Addressing. To start communication between the bus master and the slave ST24/25x08, the master must initiate a START condition. Following this, the master sends onto the SDA bus line 8 bits (MSB first) corresponding to the device select code (7 bits) and a READ or WRITE bit.

Figure 3. Maximum RL Value versus Bus Capacitance (CBUS) for an I2C Bus

RL max (kΩ)

20

VCC

16

									RL					RL
12						SDA									CBUS
					MASTER
8						SCL
4											CBUS
VCC = 5V
0
100		200	300	400
		CBUS (pF)													AI01100

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ST24/25C08, ST24/25W08

Table 5. Input Parameters (1) (TA = 25 °C, f = 100 kHz )

Symbol			Parameter	Test Condition	Min	Max	Unit
CIN		Input Capacitance (SDA)				8	pF
CIN		Input Capacitance (other pins)				6	pF
ZWCL				VIN £ 0.3 VCC	5	20	kW
		WC	Input Impedance (ST24/25W08)
ZWCH				VIN ³ 0.7 VCC	500		kW
		WC	Input Impedance (ST24/25W08)
tLP		Low-pass filter input time constant				100	ns
		(SDA and SCL)

Note: 1. Sampled only, not 100% tested.

Table 6. DC Characteristics

(TA = 0 to 70°C, –20 to 85°C or –40 to 85°C; VCC = 3V to 5.5V or 2.5V to 5.5V)

Symbol	Parameter			Test Condition	Min	Max	Unit
ILI	Input Leakage Current			0V £ VIN £ VCC		±2	mA
ILO	Output Leakage Current			0V £ VOUT £ VCC		±2	mA
				SDA in Hi-Z
	Supply Current (ST24 series)			VCC = 5V, fC = 100kHz		2	mA
ICC				(Rise/Fall time < 10ns)
	Supply Current (ST25 series)			VCC = 2.5V, fC = 100kHz		1	mA
				VIN = VSS or VCC,		100	mA
	Supply Current (Standby)			VCC = 5V
ICC1
	(ST24 series)			VIN = VSS or VCC,		300	mA
				VCC = 5V, fC = 100kHz
				VIN = VSS or VCC,		5	mA
ICC2	Supply Current (Standby)			VCC = 2.5V
	(ST25 series)			VIN = VSS or VCC,		50	mA
				VCC = 2.5V, fC = 100kHz
VIL	Input Low Voltage (SCL, SDA)				–0.3	0.3 VCC	V
VIH	Input High Voltage (SCL, SDA)				0.7 VCC	VCC + 1	V
VIL	Input Low Voltage				–0.3	0.5	V
	(E, PRE, MODE, WC)
VIH	Input High Voltage				VCC – 0.5	VCC + 1	V
	(E, PRE, MODE, WC)
VOL	Output Low Voltage (ST24 series)			IOL = 3mA, VCC = 5V		0.4	V
	Output Low Voltage (ST25 series)			IOL = 2.1mA, VCC = 2.5V		0.4	V

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