ST ST23YS02 User Manual
with enhanced security and 2 Kbytes high-density EEPROM
Features
ST23YS02 major applications include:
■ Banking targeting the EMVCo certificate
Hardware features
ST23YS02
Smartcard MCU
Data Brief
■ Enhanced 8/16-bit CPU core with 16 Mbytes
linear addressable memory
■ 36 Kbytes User ROM
■ 2 Kbytes User RAM
■ 2 Kbytes User EEPROM including 64 Bytes
User OTP area:
– Highly reliable CMOS EEPROM submicron
technology
– 10-year data retention
– 500,000 Erase/Write cycles endurance
typical at 25° C
– 1 to 32 Bytes Erase or Program in 1.5 ms
■ Two 8-bit timers with watchdog and interrupt
capability
■ 3V and 5V supply voltage ranges
■ External clock frequency from 1 up to 5 MHz
■ High performance provided by:
– CPU clock frequency up to 29 MHz
■ Power-saving Standby state
■ Contact assignment compatible ISO 7816-3
■ Asynchronous Receiver Transmitter (IART) for
high speed serial data support (ISO 7816-3
and EMV™ compliant)
■ ISO 3309 CRC calculation block
■ ESD protection greater than 5 kV (HBM)
259a.ai
Micromodule Wafer
Security features
■ Active shield
■ Monitoring of environmental parameters
■ Protection mechanisms against faults
■ Hardware Security Enhanced DES accelerator
■ AIS-31 class P2 compliant True Random
Number Generator (TRNG)
■ Unique serial number on each die
Development environment
Software development and firmware generation
are supported by a comprehensive set of
development tools dedicated to software design
and validation:
■ C Compiler
■ Simulator
■ Emulator
September 2007 Rev 1 1/4
For further information contact your local STMicroelectronics sales office.
www.st.com
1
Description ST23YS02
1 Description
The ST23YS02 product is a serial access microcontroller specially designed for secure
smartcard applications.
It is based on an enhanced STMicroelectronics 8/16-bit CPU core offering 16 Mbytes linear
addressing space. It is manufactured using an advanced highly reliable ST CMOS EEPROM
technology.
Figure 1. ST23YS02 block diagram
RAM
CRC
Module
EEPROM
Clock
Gene-
rator
Module
CLK
2 x
8-bit
timers
User ROM
Internal Bus
Security
Monitor-
ing and
Control
RESET
ST ROM
(Boot software)
ST ROM Firewall
True
Random
Number
Gene-
rator
Vcc
8/16-bit
CPU
Core
GND
EDES
Accelerator
IART
I/O
Ai12551
2/4
Loading...