ST ST21Y144 User Manual
with 144 Kbytes High Density EEPROM
Feature summary
ST21Y144 major applications include:
■ Mobile communications (GSM and CDMA)
■ Java applications
ST21Y144
Smartcard MCU
Data Brief
Hardware features
■ Enhanced 8/16-bit CPU core with 16 MBytes
linear addressable memory
■ 400 Kbytes User ROM
■ 8 Kbytes User RAM
■ 144 Kbytes User EEPROM including 64 Bytes
User OTP area:
– Highly reliable CMOS EEPROM submicron
technology
– 10-year data retention
– 500,000 Erase/Write cycles endurance
typical at 25°C
– 1 to 64 Bytes Erase or Program in 1.5 ms
■ Asynchronous Receiver Transmi tter
supporting ISO 7816-3 T=0 and T=1 protocols
■ Two 8-bit timers with interrupt capability
■ 1.8V, 3V and 5V supply voltage ranges
■ External clock frequency from 1 up to 7.5 MHz
■ High performance provided by:
– CPU clock frequency up to 22 MHz
– External clock multiplier (2x, 3x, and 4x)
■ Current consumption complies with GSM
specifications
■ Power-saving Standby mode
■ Contact assignment compatible ISO 7816-2
■ ESD protection greater than 4 kV (HBM)
259a.ai
Micromodule Wafer
Security features
■ Monitoring of environmental paramete rs
■ Protection against faults
■ ISO 3309 CRC calculation block
■ Cryptographic performances
(1)
:
– Triple DES (with keys loaded): 9.3 µs
– Single DES (with keys loaded): 3.1 µs
■ True Random Number Generator
■ Unique serial number on each die
■ Hardware DES accelerator
Development environment
Software development and firmware generation
are supported by a comprehensive set of
development tools dedicated to software design
and validation.
1. Typical values at 22 MHz
March 2007 Rev 2 1/4
For further information contact your local STMicroelectronics sales office .
www.st.com
1
Description ST21Y144
1 Description
The ST21Y144 product is a serial access microcontroller specially designed for costeffective secure mobile applications.
It is based on an enhanced STMicroelectronics 8/16-bit CPU core off ering 16 MBytes
linear addressing space.
It is manufactured using an advanced highly reliable ST CM OS EEPROM technology.
The device includes a DES accelerator.
A serial interface fully compatible with the ISO 7816-3 standard (T = 0 and T = 1) for
Smartcard applications is available.
A CRC calculation block is also available and is directly accessible by the User.
The product architecture is optimized for low power consumption applications. A flexible
clock generator module provides increased perf ormance for specific current requirements.
Figure 1. Block diagram
CRC
Module
RAM
Clock
Gene-
rator
Module
CLK
EEPROM
2 x
8-bit
timers
Internal Bus
Security
Adminis-
trator
RESET
ROM
True
Random
Number
Gene-
rator
Vcc
DES
Accelerator
8/16-bit
CPU
Core
GND
IART
I/O
579
2/4
Loading...