The ST1S40 is an internally compensated 850
kHz fixed-frequency PWM synchronous stepdown regulator. ST1S40 operates from 4.0 V to
18 V input, while it regulates an output voltage as
low as 0.8 V and up to V
The ST1S40 integrates a 95 mΩ high side switch
and 69 mΩ synchronous rectifier allowing very
high efficiency with very low output voltages.
The peak current mode control with internal
compensation delivers a very compact solution
with a minimum component count.
The ST1S40 is available in VFQFPN 4 mm x 4
mm 8 lead package, HSOP-8 and standard SO-8.
Enable input. With EN higher than 1.2 V the device in ON and with EN lower than
0.4 V the device is OFF (ST1S40Ixx).
Feedback input. Connecting the output voltage directly to this pin the output
voltage is regulated at 0.8 V. To have higher regulated voltages an external
resistor divider is required from Vout to the FB pin.
Table 1.Pin description
VFQFPN
and HSOP8
13
24EN
35FB
46AGND Ground
5-NCIt can be connected to ground
VINA
EN
FB
GND
1
2
9
3
4
PGND
8
SW
7
VINSW
6
NC
5
1
SWVINSW
PGND
VINA
EN
45
HSOP8SO8-BW
8
GND
AGND
FB
68VINSW Power input voltage
71SWRegulator output switching pin
82PGND Power ground
-7Ground
9-ePadExposed pad mandatory connected to ground
Doc ID 17928 Rev 43/30
Maximum ratingsST1S40
2 Maximum ratings
Table 2.Absolute maximum ratings
SymbolParameterValueUnit
V
V
V
V
V
P
T
T
Power input voltage-0.3 to 20
INSW
Input voltage-0.3 to 20
INA
Enable voltage-0.3 to V
EN
Output switching voltage-1 to V
SW
Feedback voltage-0.3 to 2.5
FB
I
FB current-1 to +1mA
FB
Power dissipation at TA < 60 °C
TOT
Operating junction temperature range-40 to 150°C
OP
Storage temperature range-55 to 150°C
stg
3 Thermal data
Table 3.Thermal data
SymbolParameterValueUnit
R
Maximum thermal resistance junction-ambient
thJA
2.25 (HSOP8/DFN4x4);
VFQFPN40
(1)
SO8-BW55
INA
IN
1.6 SO8-BW
V
W
°C/WHSOP840
1. Package mounted on demonstration board.
4/30Doc ID 17928 Rev 4
ST1S40Electrical characteristics
4 Electrical characteristics
TJ=25 °C, VCC=12 V, unless otherwise specified.
Table 4.Electrical characteristics
Val ues
SymbolParameterTest condition
Min.Typ.Max.
Unit
Operating input voltage
IN
range
Tur n-o n VCC threshold
Threshold hysteresis
High side switch ON
-P
resistance
Low side switch ON
-N
resistance
Maximum limiting current
V
R
R
V
V
INON
INHYS
DSON
DSON
I
LIM
Oscillator
D
F
SW
MAX
Switching frequency0.70.851MHz
Maximum duty cycle
Dynamic characteristics
%V
ΔI
%V
V
ΔV
FB
OUT
OUT
OUT
Feedback voltage
/
Reference load regulation Isw=10 mA to I
/
Reference line regulation VIN= 4.0 V to 18 V
IN
DC characteristics
(1)
(1)
(1)
ISW=750 mA
418
2.9
V
0.250
95
mΩ
ISW=750 mA69mΩ
(2)
(2)
4.06.0A
100%
0.7840.80.816
(1)
LIM
0.7760.80.824
(2)
(2)
0.5%
0.4%
V
I
Q
I
QST-BY
Quiescent current
Total standby quiescent
current
Duty cycle=0, no load
=1.2 V
V
FB
OFF215μA
IFBFB bias current50
Enable
Device ON level1.2
V
EN
I
EN
EN threshold voltage
Device OFF level0.4
EN current2μA
Doc ID 17928 Rev 45/30
1.52.5mA
V
Electrical characteristicsST1S40
Table 4.Electrical characteristics (continued)
Val ues
SymbolParameterTest condition
Min.Typ.Max.
Soft start
Unit
T
SS
Soft-start duration1ms
Protection
Thermal shutdown150
T
SHDN
1. Specification referred to TJ from -40 to +125 °C. Specifications in the -40 to +125 °C temperature range are
assured by design, characterization and statistical correlation.
2. Guaranteed by design.
Hysteresis 15
°C
6/30Doc ID 17928 Rev 4
ST1S40Functional description
OSC
E/A
DRIVER
DRIVER
DMD
OTP
MOSFET
CONTROL
LOGIC
REGULATOR
SHUT-DOWN
I_SENSE
COMP
COMP
OCP
REF
0.8V
SOFTSTART
Vsum
Vc
OCP
UVLO
Vdrv_p
Vdrv_n
I2V
R
SENSE
VINAVINSW
SW
GNDPGNDAENFB
5 Functional description
The ST1S40 is based on a “peak current mode”, constant frequency control. The output
voltage V
providing an error signal that, compared to the output of the current sense amplifier, controls
the ON and OFF time of the power switch.
The main internal blocks are shown in the block diagram in Figure 3. They are:
●A fully integrated oscillator that provides the internal clock and the ramp for the slope
compensation avoiding sub-harmonic instability
●The soft-start circuitry to limit inrush current during the startup phase
●The transconductance error amplifier with integrated compensation network
●The pulse width modulator and the relative logic circuitry necessary to drive the internal
power switches
●The drivers for embedded P-channel and N-channel Power MOSFET switches
●The high side current sensing block
●The low side current sense to implement diode emulation
●A voltage monitor circuitry (UVLO) that checks the input and internal voltages
●A thermal shutdown block, to prevent thermal run-away.
is sensed by the feedback pin (FB) compared to an internal reference (0.8 V)
OUT
Figure 3.Block diagram
5.1 Internal soft-start
The soft-start is essential to assure correct and safe startup of the step-down converter. It
avoids inrush current surge and causes the output voltage to increase monothonically.
Doc ID 17928 Rev 47/30
Functional descriptionST1S40
L
Cout
Cur rent s ense
Logic
And
Driver
Slope
Com pensati on
PW M comparator
Error Amp
Rc
Cc
R1
R2
0.8 V
Hi gh side
Swi tch
Low s i de
Swi tch
GCO(s)
G
DIV
(s)
G
EA
(s)
VIN
V
C
V
OUT
V
FB
The soft-start is performed by ramping the non-inverting input (V
from 0 V to 0.8 V in around 1 ms.
5.2 Error amplifier and control loop stability
The error amplifier compares the FB pin voltage with the internal 0.8 V reference and it
provides the error signal to be compared with the output of the current sense circuitry, that is
the high side Power MOSFET current. Comparing the output of the error amplifier and the
peak inductor current implements the peak current mode control loop.
The error amplifier is a transconductance amplifier (OTA). The uncompensated
characteristics are listed inTable 5.
Table 5.Error amplifier characteristics
DC Gain95 dB
Gm251 µA/V
Ro240 MΩ
The ST1S40 embeds the compensation network that assures the stability of the loop in the
whole operating range. All the tools needed to check the loop stability are shown below.
Figure 4. shows the simple small signal model for the peak current mode control loop.
Figure 4.Block diagram of the loop for the small signal analysis