ST ST1S10 User Manual

3 A, 900 kHz, monolithic synchronous step-down regulator IC

Features

■ Step-down current mode PWM regulator

■ Output voltage adjustable from 0.8 V

■ Input voltage from 2.5 V up to 18 V

■ 2% DC output voltage tolerance

■ Synchronous rectification

■ Inhibit function

■ Synchronizable switching frequency from 400

kHz up to 1.2 MHz

■ Internal soft start

■ Dynamic short circuit protection

■ Typical efficiency: 90%

■ 3 A output current capability

■ Stand-by supply current: max 6 µA over

temperature range

■ Operative junction temp: from - 40 °C to 125 °C

Applications

■ Consumer

– STB, DV D, DV D r e c o r d e rs, TV, V C R , c a r

audio, LCD monitors

■ Networking

– XDSL, modems, DC-DC modules

■ Computer

– Optical storage, HD drivers, printers,

audio/graphic cards

■ Industrial and security

– Battery chargers, DC-DC converters, PLD,

PLA, FPGA, LED drivers

ST1S10

Datasheet − production data

DFN8 (4 x 4 mm)

Description

The ST1S10 is a high efficiency step-down PWM
current mode switching regulator capable of
providing up to 3 A of output current. The device
operates with an input supply range from 2.5 V to
18 V and provides an adjustable output voltage
from 0.8 V (V
V

*(1+R1/R2)]. It operates either at a 900 kHz

FB

fixed frequency or can be synchronized to an
external clock (from 400 kHz to 1.2 MHz). The
high switching frequency allows the use of tiny
SMD external components, while the integrated
synchronous rectifier eliminates the need for a
Schottky diode. The ST1S10 provides excellent
transient response, and is fully protected against
thermal overheating, switching over-current and
output short circuit.

The ST1S10 is the ideal choice for point-of-load
regulators or LDO pre-regulation.

) to 0.85*V

FB

IN_SW

PowerSO-8

[V

=

OUT

Table 1. Device summary

Order codes

Part number

DFN8 (4 x 4 mm) PowerSO-8

ST1S10 ST1S10PUR ST1S10PHR

June 2012 Doc ID 13844 Rev 5 1/29

This is information on a product in full production.

www.st.com

29

Contents ST1S10

Contents

1 Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

3 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

5 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

5.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

5.2 External components selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

5.2.1 Input capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

5.3 Output capacitor (V

5.4 Output capacitor (0.8 V < V

> 2.5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

OUT

< 2.5 V) . . . . . . . . . . . . . . . . . . . . . . . . . 12

OUT

5.5 Output voltage selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

5.6 Inductor (V

5.7 Inductor (0.8 V < V

> 2.5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

OUT

< 2.5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

OUT

5.8 Function operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

5.8.1 Sync operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

5.8.2 Inhibit function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5.8.3 OCP (overcurrent protection) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5.8.4 SCP (short circuit protection) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5.8.5 SCP and OCP operation with high capacitive load . . . . . . . . . . . . . . . . 14

6 Layout considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

6.1 Thermal considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

7 Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

8 Typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

9 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

2/29 Doc ID 13844 Rev 5

ST1S10 List of tables

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Table 3. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 4. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 5. Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Table 6. Power SO-8 (exposed pad) mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 7. Power SO-8 (exposed pad) tape and reel mechanical data . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 8. DFN8 (4X4) mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 9. DFN8 (4x4)tape and reel mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 10. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Doc ID 13844 Rev 5 3/29

List of figures ST1S10

List of figures

Figure 1. Typical application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 2. Pin connections (top view for PowerSO-8, bottom view for DFN8) . . . . . . . . . . . . . . . . . . . 6

Figure 3. Application schematic for heavy capacitive load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 4. Application schematic for low output voltage (V
Figure 5. Application schematic for low output voltage (V

Figure 6. PCB layout suggestion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 7. PCB layout suggestion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 8. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 9. Voltage feedback vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 10. Oscillator frequency vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 11. Max duty cycle vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 12. Inhibit threshold vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 13. Reference line regulation vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 14. Reference load regulation vs. temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 15. ON mode quiescent current vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 16. Shutdown mode quiescent current vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 17. PMOS ON resistance vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 18. NMOS ON resistance vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 19. Efficiency vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 20. Efficiency vs. output current@V
Figure 21. Efficiency vs. output current@V
Figure 22. Efficiency vs. output current@V

= 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

out

= 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

out

= 12 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

out

Figure 23. Power SO-8 (exposed pad) dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 24. Power SO-8 (exposed pad) recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 25. Power SO-8 (exposed pad) tape and reel dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 26. DFN8 (4x4) dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 27. DFN8 (4x4)tape and reel dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

< 2.5 V) and 2.5 V < VIN < 8 V . . . . . 15

OUT

< 2.5 V) and 8 V < V

OUT

< 16 V . . . . . . 15

IN

4/29 Doc ID 13844 Rev 5

ST1S10 Application circuit

1 Application circuit

Figure 1. Typical application circuit

L1

L1

3.3µH

3.3µH

12V

12V

C1

C1

4.7µF

4.7µF

C3

C3

0.1µF

0.1µF

VIN_SW

VIN_SW

EN

EN

VIN_A

VIN_A

ST1S10

ST1S10

SYNC

SYNC

AGND

AGND

PGND

PGND

SW

SW

FB

FB

R1

R1

R2

R2

C2

C2

22µF

22µF

5V – 3A

5V – 3A5V – 3A

Doc ID 13844 Rev 5 5/29

Pin configuration ST1S10

2 Pin configuration

Figure 2. Pin connections (top view for PowerSO-8, bottom view for DFN8)

DFN8 (4x4)

Table 2. Pin description

Pin n° Symbol Name and function

1V

IN_A

2 INH (EN) Inhibit pin active low. Connect to V

3V

FB

4 AGND Analog ground

5 SYNC

6V

IN_SW

7 SW Switching node to be connected to the inductor

8 PGND Power ground

epad epad Exposed pad to be connected to ground

Analog input supply voltage to be tied to VIN supply source

if not used

IN_A

Feedback voltage for connection to external voltage divider to set the V
from 0.8V up to 0.85*V

. (see output voltage selection paragraph 5.5)

IN_SW

Synchronization and frequency select. Connect SYNC to GND for 900 kHz
operation, or to an external clock from 400 kHz to 1.2 MHz. (see Sync
operation paragraph 5.8.1)

Power input supply voltage to be tied to VIN power supply source

PowerSO-8

OUT

6/29 Doc ID 13844 Rev 5

ST1S10 Maximum ratings

3 Maximum ratings

Table 3. Absolute maximum ratings

Symbol Parameter Value Unit

V

IN_SW

V

IN_A

V

V

V

I

INH

SW

FB

FB

Positive power supply voltage -0.3 to 20 V

Positive supply voltage -0.3 to 20 V

Inhibit voltage -0.3 to V

IN_A

V

Output switch voltage -0.3 to 20 V

Feedback voltage -0.3 to 2.5 V

FB current -1 to +1 mA

Sync Synchronization -0.3 to 6 V

T

T

STG

OP

Storage temperature range -40 to 150 °C

Operating junction temperature range -40 to 125 °C

Note: Absolute maximum ratings are the values beyond which damage to the device may occur.

Functional operation under these conditions is not implied.

Table 4. Thermal data

Symbol Parameter PowerSO-8 DFN8 Unit

R

thJA

R

thJC

Thermal resistance junction-ambient 40 40 °C/W

Thermal resistance junction-case 12 4 °C/W

Doc ID 13844 Rev 5 7/29

Electrical characteristics ST1S10

4 Electrical characteristics

V

= V

IN

+0.1 µF, C
the typical application circuit. Typical values assume T

Table 5. Electrical characteristics

Symbol Parameter Test conditions Min. Typ. Max. Unit

V

FB

I

FB

I

Q

I

OUT

Feedback voltage

VFB pin bias current 600 nA

Quiescent current

Output current

IN_SW

OUT

= V

IN_A

= V

= 12 V, V

INH

SYNC

= GND, V

OUT

= 5 V, I

= 10 mA, CIN = 4.7 µF

OUT

= 22 µF, L1 = 3.3 µH, TJ = -40 to 125°C (Unless otherwise specified, refer to

= 25°C).

J

T

= 25°C 784 800 816 mV

J

T

= -25°C to 125°C 776 800 824 mV

J

V

> 1.2 V, not switching 1.5 2.5 mA

INH

V

< 0.4 V 2 6 µA

INH

(1)

VIN = 2.5 V to 18 V V

0.8 V to 13.6 V

(2)

OUT

=

3.0 A

%V

OUT

%V

∆I

V

I

INH

INH

OUT

OUT

Inhibit threshold

Inhibit pin current 2 µA

/∆VINReference line regulation 2.5 V < V

/

Reference load regulation 10 mA < I

PWM fs PWM switching frequency

(2)

R

R

D

MAX

DSon

DSon

I

SWL

Maximum duty cycle

-N NMOS switch on resistance ISW = 750 mA 0.10 Ω

-P PMOS switch on resistance ISW = 750 mA 0.12 Ω

Switch current limitation 5.0 A

ν Efficiency

V

T

T

OUT

SHDN

HYS

/∆I

Thermal shut down 150 °C

Thermal shut down hysteresis 15 °C

Output transient response

OUT

Device ON 1.2 V

Device OFF 0.4 V

< 18 V 0.4

IN

< 3 A 0.5

OUT

= 0.7 V, Sync = GND TJ

V

FB

= 25°C

0.7 0.9 1.1 MHz

%V

∆V

%V

∆I

85 90 %

I

= 100 mA to 300 mA 85 %

OUT

= 300 mA to 3 A 90 %

I

OUT

100 mA < I
≥ 500 ns

< 1 A, tR = t

OUT

F

±5%V

OUT

IN

OUT

OUT

/

/

O

V

/∆I

OUT

@IO=short

F

SYNC

SYNC

V

IL_SYNC

Short circuit removal response

OUT

(overshot)

SYNC frequency capture range

SYNC pulse width V

WD

SYNC input threshold low V

10 mA < I

= 2.5 V to 18 V, V

V

IN

< short ±10 %V

OUT

0 to 5 V

= 2.5 V to 18 V 250 ns

IN

= 2.5 V to 18 V 0.4 V

IN

8/29 Doc ID 13844 Rev 5

SYNC

=

0.4 1.2 MHz

O

ST1S10 Electrical characteristics

Table 5. Electrical characteristics (continued)

Symbol Parameter Test conditions Min. Typ. Max. Unit

V

IH_SYNC

I

IL, IIH

SYNC input threshold high V

SYNC input current

UVLO Under voltage lock-out threshold

= 2.5 V to 18 V 1.6 V

IN

V

= 2.5 V to 18 V, V

IN

0 or 5 V

V

rising 2.3 V

IN

Hysteresis 200 mV

1. Guaranteed by design, but not tested in production.

2. See output voltage selection paragraph 5.5 for maximum duty cycle conditions.

SYNC

=

-10 +10 µA

Doc ID 13844 Rev 5 9/29

Application information ST1S10

5 Application information

5.1 Description

The ST1S10 is a high efficiency synchronous step-down DC-DC converter with inhibit
function. It provides up to 3 A over an input voltage range of 2.5 V to 18 V, and the output
voltage can be adjusted from 0.8 V up to 85% of the input voltage level. The synchronous
rectification removes the need for an external Schottky diode and allows higher efficiency
even at very low output voltages.

A high internal switching frequency (0.9 MHz) allows the use of tiny surface-mount
components, as well as a resistor divider to set the output voltage value. In typical
application conditions, only an inductor and 3 capacitors are required for proper operation.

The device can operate in PWM mode with a fixed frequency or synchronized to an external
frequency through the SYNC pin. The current mode PWM architecture and stable operation
with low ESR SMD ceramic capacitors results in low, predictable output ripple. No external
compensation is needed.

To maximize power conversion efficiency, the ST1S10 works in pulse skipping mode at light
load conditions and automatically switches to PWM mode when the output current
increases.

The ST1S10 is equipped with thermal shut down protection activated at 150 °C (typ.).

Cycle-by-cycle short circuit protection provides protection against shorted outputs for the
application and the regulator. An internal soft start for start-up current limiting and power ON
delay of 275 µs (typ.) helps to reduce inrush current during start-up.

5.2 External components selection

5.2.1 Input capacitor

The ST1S10 features two VIN pins: V
switching peak current is drawn, and V
drivers.

The V
and reduces switching noise in the IC. A high power supply source impedance requires
larger input capacitance.

For the V
higher than the RMS input current. The maximum RMS input current can be calculated
using the following equation:

Equation 1

input capacitor reduces the current peaks drawn from the input power supply

IN_SW

input capacitor the RMS current rating is a critical parameter that must be

IN_SW

=

=

for the power supply input voltage where the

IN_SW

to supply the ST1S10 internal circuitry and

IN_A

⋅

⋅

ORMS

ORMS

22

⋅

⋅

D2

D2

-DII

-DII

η

η

22

D

D

+

+

η

η

where η is the expected system efficiency, D is the duty cycle and I
current. The duty cycle can be derived using the equation:

10/29 Doc ID 13844 Rev 5

is the output DC

O

ST1S10 Application information

Equation 2

D = (V

where V

+ VF) / (VIN-VSW)

OUT

is the voltage drop across the internal NMOS, and VSW represents the voltage

F

drop across the internal PDMOS. The minimum duty cycle (at V
duty cycle (at V

) should be considered in order to determine the max I

IN_min

through the input capacitor.

A minimum value of 4.7 µF for the V
suitable in most application conditions. A 10 µF or higher ceramic capacitor for the V
and a 1 µF or higher for the V
impedance or where long wires are needed between the power supply source and the V
pins. The above higher input capacitor values are also recommended in cases where an
output capacitive load is present (47 µF < C
switching peak current drawn from the input capacitor during the start-up transient.

In cases of very high output capacitive loads (C
values shall be modified as described in the OCP and SCP operation section 5.8.5 of this
document.

The input ceramic capacitors should have a voltage rating in the range of 1.5 times the
maximum input voltage and be located as close as possible to V

5.3 Output capacitor (V

The most important parameters for the output capacitor are the capacitance, the ESR and
the voltage rating. The capacitance and the ESR affect the control loop stability, the output
ripple voltage and transient response of the regulator.

) and the maximum

IN_max

and a 0.1 µF ceramic capacitor for the V

IN_SW

are recommended in cases of higher power supply source

IN_A

< 100 µF), which could impact the

LOAD

> 100 µF), all input/output capacitor

LOAD

pins.

IN

> 2.5 V)

OUT

RMS

flowing

IN_A

IN_SW

are

IN

The ripple due to the capacitance can be calculated with the following equation:

Equation 3

V

RIPPLE(C)

where F

= (0.125 x ∆ISW) / (FS x C

is the PWM switching frequency and ∆ISW is the inductor peak-to-peak switching

S

OUT

)

current, which can be calculated as:

Equation 4

∆I

= [(VIN - V

SW

) / (FS x L)] x D

OUT

where D is the duty cycle.

The ripple due to the ESR is given by:

Equation 5

V

(ESR) = ∆ISW x ESR

RIPPLE

The equations above can be used to define the capacitor selection range, but final values
should be verified by testing an evaluation circuit.

Lower ESR ceramic capacitors are usually recommended to reduce the output ripple
voltage. Capacitors with higher voltage ratings have lower ESR values, resulting in lower
output ripple voltage.

Doc ID 13844 Rev 5 11/29

Application information ST1S10

Also, the capacitor ESL value impacts the output ripple voltage, but ceramic capacitors
usually have very low ESL, making ripple voltages due to the ESL negligible. In order to
reduce ripple voltages due to the parasitic inductive effect, the output capacitor connection
paths should be kept as short as possible.

The ST1S10 has been designed to perform best with ceramic capacitors. Under typical
application conditions a minimum ceramic capacitor value of 22 µF is recommended on the
output, but higher values are suitable considering that the control loop has been designed to
work properly with a natural output LC frequency provided by a 3.3 µH inductor and 22 µF
output capacitor. If the high capacitive load application circuit shown in Figure 3 is used, a
47 µF (or 2 x 22 µF capacitors in parallel) could be needed as described in the OCP and
SCP operation Section 5.8.5: SCP and OCP operation with high capacitive load. of this
document.

The use of ceramic capacitors with voltage ratings in the range of 1.5 times the maximum
output voltage is recommended.

5.4 Output capacitor (0.8 V < V

OUT

For applications with lower output voltage levels (V
inductor values should be selected in a way that improves the DC-DC control loop behavior.
In this output condition two cases must be considered: V

For V

< 8 V the use of 2 x 22 µF capacitors in parallel to the output is recommended, as

IN

shown in Figure 4.

For V

> 8 V, a 100 µF electrolytic capacitor with ESR < 0.1 Ω should be added in parallel to

IN

the 2 x 22 µF output capacitors as shown in Figure 5.

5.5 Output voltage selection

The output voltage can be adjusted from 0.8 V up to 85% of the input voltage level by
connecting a resistor divider (see R1 and R2 in the typical application circuit) between the
output and the V
compromise in terms of current consumption. Once the R2 value is selected, R1 can be
calculated using the following equation:

Equation 6

R1 = R2 x (V

where V

= 0.8 V (typ.).

FB

Lower values are suitable as well, but will increase current consumption. Be aware that duty
cycle must be kept below 85% at all application conditions, so that:

pin. A resistor divider with R2 in the range of 20 kΩ is a suitable

FB

- VFB) / V

OUT

FB

< 2.5 V)

< 2.5 V) the output capacitance and

out

> 8 V and VIN < 8 V.

IN

Equation 7

D = (V

where V

+ VF) / (VIN-VSW) < 0.85

OUT

is the voltage drop across the internal NMOS, and VSW represents the voltage

F

drop across the internal PDMOS.

Note that once the output current is fixed, higher V
of the device leading to an increase in the operating junction temperature. It is

12/29 Doc ID 13844 Rev 5

levels increase the power dissipation

OUT

ST1S10 Application information

recommended to select a V
thermal shut-down protection threshold (150°C typ.) at the rated output current. The
following equation can be used to calculate the junction temperature (T

Equation 8

T

= {[V

J

where R
current and T

x I

OUT

OUT

is the junction-to-ambient thermal resistance, η is the efficiency at the rated I

thJA

AMB

To ensure safe operating conditions the application should be designed to keep T

5.6 Inductor (V

The inductor value fixes the ripple current flowing through output capacitor and switching
peak current. The ripple current should be kept in the range of 20-40% of I
example it is 0.6 - 1.2 A at I
the following equation:

Equation 9

L = [(V

where T

T

ON

The inductor should be selected with saturation current (I
inductor peak current, which can be calculated with the following equation:

IN

ON

= D/F

- V

OUT

is the ON time of the internal switch, given by:

S

level which maintains the junction temperature below the

OUT

x R

x (1-η)] / η} +T

thJA

AMB

is the ambient temperature.

> 2.5 V)

OUT

= 3 A). The approximate inductor value can be obtained with

OUT

) / ∆ISW] x T

ON

):

J

OUT_MAX

) equal to or higher than the

SAT

< 140°C.

J

(for

OUT

Equation 10

I

= IO + (∆ISW/2), I

PK

SAT

≥ I

PK

The inductor peak current must be designed so that it does not exceed the switching current
limit.

5.7 Inductor (0.8 V < V

For applications with lower output voltage levels (V
section is still valid but it is recommended to keep the inductor values in a range from 1µH to

2.2 µH in order to improve the DC-DC control loop behavior, and increase the output
capacitance depending on the V
application conditions a 2.2 µH inductor is the best compromise between DC-DC control
loop behavior and output voltage ripple.

5.8 Function operation

5.8.1 Sync operation

The ST1S10 operates at a fixed frequency or can be synchronized to an external frequency
with the SYNC pin. The ST1S10 switches at a frequency of 900 kHz when the SYNC pin is
connected to ground, and can synchronize the switching frequency between 400 kHz to 1.2

< 2.5 V)

OUT

< 2.5 V) the description in the previous

out

level as shown in the Figure 4 and Figure 5. In most

IN

Doc ID 13844 Rev 5 13/29

Application information ST1S10

MHz from an external clock applied to the SYNC pin. When the SYNC feature is not used,
this pin must be connected to ground with a path as short as possible to avoid any possible
noise injected in the SYNC internal circuitry.

5.8.2 Inhibit function

The inhibit pin can be used to turn OFF the regulator when pulled down, thus drastically
reducing the current consumption down to less than 6 µA. When the inhibit feature is not
used, this pin must be tied to V

to keep the regulator output ON at all times. To ensure

IN

proper operation, the signal source used to drive the inhibit pin must be able to swing above
and below the specified thresholds listed in the electrical characteristics section under V

INH

Any slew rate can be used to drive the inhibit pin.

5.8.3 OCP (overcurrent protection)

The ST1S10 DC-DC converter is equipped with a switch overcurrent protection. In order to
provide protection for the application and the internal power switches and bonding wires, the
device goes into a shutdown state if the switch current limit is reached and is kept in this
condition for the T
(T

ON(OCP)

= 22 µs typ.) under typical application conditions. This operation is repeated cycle

by cycle. Normal operation is resumed when no over-current is detected.

period (T

OFF

OFF(OCP)

= 135 µs typ.) and turns on again for the TON period

.

5.8.4 SCP (short circuit protection)

In order to protect the entire application and reduce the total power dissipation during an
overload or an output short circuit condition, the device is equipped with dynamic short
circuit protection which works by internally monitoring the V

In the event of an overload or output short circuit, if the V
feedback voltage (V
T

time (T

OFF

OFF(SCP)

) to drop below 0.3 V (typ.), the device goes into shutdown for the

FB

= 288 µs typ.) and turns on again for the TON period (T

(feedback voltage).

FB

voltage is reduced causing the

OUT

µs typ.). This operation is repeated cycle by cycle, and normal operation is resumed when
no overload is detected (V

> 0.3 V typ.) for the full TON period.

FB

This dynamic operation can greatly reduce the power dissipation in overload conditions,
while still ensuring excellent power-on startup in most conditions.

5.8.5 SCP and OCP operation with high capacitive load

Thanks to the OCP and SCP circuit, ST1S10 is strongly protected against damage from
short circuit and overload.

However, a highly capacitive load on the output may cause difficulties during start-up. This
can be resolved by using the modified application circuit shown in Figure 3, in which a
minimum of 10 µF for C1 and a 4.7 µF ceramic capacitor for C3 are used. Moreover, for
C
divider resistor (R1) as shown in Figure 3. The recommended value for C4 is 4.7 nF.

Note that C4 may impact the control loop response and should be added only when a
capacitive load higher than 100 µF is continuously present. If the high capacitive load is
variable or not present at all times, in addition to C4 an increase in the output ceramic
capacitor C2 from 22 µF to 47 µF (or 2 x 22 µF capacitors in parallel) is recommended. Also
in this case it is suggested to further increase the input capacitors to a minimum of 10 µF for
C1 and a 4.7 µF ceramic capacitor for C3 as shown in Figure 3.

> 100 µF, it is necessary to add the C4 capacitor in parallel to the upper voltage

LOAD

ON(SCP)

= 130

14/29 Doc ID 13844 Rev 5

ST1S10 Application information

Figure 3. Application schematic for heavy capacitive load

L1

L1

3.3µH

12V

12V

C1

C1

10µF

10µF

C3

C3

4.7µF

4.7µF

VIN_SW

VIN_SW

EN

EN

VIN_A

VIN_A

ST1S10

ST1S10

SYNC

SYNC

AGN D

AGN D

(*) see OCP and SCP descriptions for C2 and C4 selection.

PGND

PGND

SW

SW

FB

FB

3.3µH

R1

R1

R2

R2

C4 (*)

C4 (*)

4.7nF

4.7nF

C2(*)

C2(*)

22µF

22µF

5V – 3A

5V – 3A5V – 3A

LOAD

LOAD

C

C

LOAD

LOADCLOAD

Output Load

Output Load

Figure 4. Application schematic for low output voltage (V

VIN<8V

VIN<8V

C1

C1

10µF

10µF

Figure 5. Application schematic for low output voltage (V

C3

C3

0.1µF

0.1µF

VIN_SW

VIN_SW

EN

EN

VIN_A

VIN_A

ST1S10

ST1S10

SYNC

SYNC

AGND

AGND

PGND

PGND

8V<VIN<16V

8V<VIN<16V

C1

C1

10µF

10µF

C3

C3

4.7µF

4.7µF

VIN_SW

VIN_SW

EN

EN

VIN_A

VIN_A

ST1S10

ST1S10

SW

SW

FB

FB

< 2.5 V) and 2.5 V < VIN < 8 V

OUT

L1

L1

2.2µH

2.2µH

0.8V<VOUT<2.5V

0.8V<VOUT<2.5V

SW

SW

R1

R1

C2

C2

2x22µF

FB

FB

R2

R2

< 2.5 V) and 8 V < V

OUT

L1

L1

2.2µH

2.2µH

R1

R1

2x22µF

2x22µF

R2

R2

2x22µF

0.8V<VOUT<2.5 V

0.8V<VOUT<2.5 V

C2

C2

+

+

C5

C5

100µF

100µF
Electrolyti c

Electrolyti c
ESR<0.1Ohm

ESR<0.1Ohm

< 16 V

IN

SYNC

SYNC

AGND

AGND

PGND

PGND

Doc ID 13844 Rev 5 15/29

Layout considerations ST1S10

6 Layout considerations

Layout is an important step in design for all switching power supplies.

High-speed operation (900 kHz) of the ST1S10 device demands careful attention to PCB
layout. Care must be taken in board layout to get device performance, otherwise the
regulator could show poor line and load regulation, stability issues as well as EMI problems.
It is critical to provide a low inductance, impedance ground path. Therefore, use wide and
short traces for the main current paths.

The input capacitor must be placed as close as possible to the IC pins as well as the
inductor and output capacitor. Use a common ground node for power ground and a different
one for control ground (AGND) to minimize the effects of ground noise. Connect these
ground nodes together underneath the device and make sure that small signal components
returning to the AGND pin and do not share the high current path of C

The feedback voltage sense line (V
routed away from noisy components and traces (e.g., SW line). Its trace should be
minimized and shielded by a guard-ring connected to the ground.

Figure 6. PCB layout suggestion

) should be connected right to the output capacitor and

FB

and C

IN

OUT

.

39mm

39mm

VFBguard-ring

VFBguard-ring

47mm

47mm

CN1=Input power supply

CN1=Input power supply
CN2=Enable/Disable

CN2=Enable/Disable
CN3=Input sync.

CN3=Input sync.
CN4=V

CN4=V

Input capacitor C1 must be placed

Input capacitor C1 must be placed
as close as possible to the IC

as close as possible to the IC
pins as well as the inductor L1

pins as well as the inductor L1
and output capacitor C2

and output capacitor C2

OUT

OUT

Vias from thermal pad

Vias from thermal pad
to bottom layer

to bottom layer

16/29 Doc ID 13844 Rev 5

ST1S10 Layout considerations

Figure 7. PCB layout suggestion

Common ground node

Common ground node

Common ground node
for power ground

for power ground

for power ground

Power Ground

Power Ground

I

I

IN

IN

I

I

OUT

OUT

6.1 Thermal considerations

The lead frame die pad, of ST1S10, is exposed at the bottom of the package and must be
soldered directly to a properly designed thermal pad on the PCB, the addition of thermal
vias from the thermal pad to an internal ground plane will help increase power dissipation.

Doc ID 13844 Rev 5 17/29

Diagram ST1S10

7 Diagram

Figure 8. Block diagram

18/29 Doc ID 13844 Rev 5

ST1S10 Typical performance characteristics

8 Typical performance characteristics

Unless otherwise specified, refer to the typical application circuit under the following
conditions: T
10 mA, C

= 25°C, VIN = V

J

= 4.7 µF + 0.1 µF, C

IN

Figure 9. Voltage feedback vs. temperature Figure 10. Oscillator frequency vs.

830

830

830

820

820

820

810

810

810

800

800

800

[mV]

[mV]

[mV]

790

790

790

FB

FB

FB

V

V

V

780

780

780

770

770

770

760

760

760

-50 -25 0 25 50 75 100 125

-50 -25 0 25 50 75 100 125

-50 -25 0 25 50 75 100 125

VIN=V

=12V, V

VIN=V

=12V, V

INH

INH

TEMPERATURE [°C]

TEMPERATURE [°C]

TEMPERATURE [°C]

OUT

OUT

=0.8V, I

=0.8V, I

OUT

OUT

=10mA

=10mA

= V

IN-SW

= 22 µF, L1 = 3.3 µH

OUT

IN-A

= V

1.2

1.2

1.1

1.1

0.9

0.9

0.8

0.8

Frequency [MHz]

Frequency [MHz]

0.7

0.7

0.6

0.6

= 12 V, V

INH

SYNC

= GND, V

OUT

= 5 V, I

OUT

temperature

1

1

V

V

IN-A=VIN-SW=VINH

IN-A=VIN-SW=VINH

-50 -25 0 25 50 75 100 125

-50 -25 0 25 50 75 100 125

TEMPERATURE [°C]

TEMPERATURE [°C]

=12V, VFB=0V

=12V, VFB=0V

=

Figure 11. Max duty cycle vs. temperature Figure 12. Inhibit threshold vs. temperature

1.4

92

92

90

90

88

88

86

86

84

84

Duty Cycle [%]

Duty Cycle [%]

82

82

80

80

-50 -25 0 25 50 75 100 125

-50 -25 0 25 50 75 100 125

V

V

IN-A=VIN-SW=VINH

IN-A=VIN-SW=VINH

TEMPERATURE [°C]

TEMPERATURE [°C]

=12V, VFB=0V

=12V, VFB=0V

1.4

1.2

1.2

1

1

(V)

(V)

0.8

0.8

INH

INH

0.6

0.6

V

V

0.4

0.4

0.2

0.2

0

0

-50 -25 0 25 50 75 100 125

-50 -25 0 25 50 75 100 125

V

=2.5V, V

V

=2.5V, V

IN-A=VIN-SW

IN-A=VIN-SW

TEMPERATURE [°C]

TEMPERATURE [°C]

OUT

OUT

=0.8V, I

=0.8V, I

OUT

OUT

=10mA

=10mA

Doc ID 13844 Rev 5 19/29

Typical performance characteristics ST1S10

Figure 13. Reference line regulation vs.

0.2

0.2

)]

)]

IN

IN

0.1

0.1

/V

/V

OUT

OUT

0

0

-0.1

-0.1

Line [%(V

Line [%(V

-0.2

-0.2

-50 -25 0 25 50 75 100 125

-50 -25 0 25 50 75 100 125

temperature

V

V

IN-A=VIN-SW=VINH

IN-A=VIN-SW=VINH

from 2.5 to 20V, V

from 2.5 to 20V, V

TEMPERATURE [°C]

TEMPERATURE [°C]

OUT

OUT

=0.8V, I

=0.8V, I

OUT

OUT

=10mA

=10mA

Figure 15. ON mode quiescent current vs.

1.8

1.8

1.6

1.6

1.4

1.4

1.2

1.2
1

1

(mA)

(mA)

0.8

0.8

Q

Q

I

I

0.6

0.6

0.4

0.4

0.2

0.2

0

0

-50 -25 0 25 50 75 100 125

-50 -25 0 25 50 75 100 125

temperature

V

=12V, V

V

=12V, V

IN-A=VIN-SW

IN-A=VIN-SW

TEMPERATURE [°C]

TEMPERATURE [°C]

=1.2V, V

=1.2V, V

INH

INH

=0.8V

=0.8V

OUT

OUT

Figure 14. Reference load regulation vs.

temperature

1.3

1.3

]

]

1

1

OUT

OUT

/I

/I

0.7

0.7

OUT

OUT

0.4

0.4

0.1

0.1

Load [%V

Load [%V

-0.2

-0.2

-0.5

-0.5

-25 0 25 50 75 100 125

-25 0 25 50 75 100 125

V

V

IN-A=VIN-SW=VINH

IN-A=VIN-SW=VINH

=12V, I

from 10mA to 3A

=12V, I

from 10mA to 3A

OUT

OUT

TEMPERATURE [°C]

TEMPERATURE [°C]

Figure 16. Shutdown mode quiescent current

vs. temperature

7

7

6

6

5

5

4

4

(µA)

(µA)

3

3

Q

Q

I

I

2

2

1

1

0

0

-50 -25 0 25 50 75 100 125

-50 -25 0 25 50 75 100 125

V

V

IN-A=VIN-SW

IN-A=VIN-SW

=12V, V

=GND, V

=12V, V

=GND, V

INH

OUT

INH

OUT

TEMPERATURE [°C]

TEMPERATURE [°C]

=0.8V

=0.8V

Figure 17. PMOS ON resistance vs.

320

320

270

270

220

220

170

170

-P[mΩ]

-P[mΩ]

120

120

DSON

DSON

R

R

70

70

20

20

-50 -25 0 25 50 75 100 125

-50 -25 0 25 50 75 100 125

temperature

VIN=12V, ISW=750mA

VIN=12V, ISW=750mA

TEMPERATURE [°C]

TEMPERATURE [°C]

Figure 18. NMOS ON resistance vs.

120

120

110

110

100

100

90

90

-N[mΩ]

-N[mΩ]

80

80

70

70

DSON

DSON

R

R

60

60

50

50

-50 -25 0 25 50 75 100 125

-50 -25 0 25 50 75 100 125

20/29 Doc ID 13844 Rev 5

temperature

VIN=12V, ISW=750mA

VIN=12V, ISW=750mA

TEMPERATURE [°C]

TEMPERATURE [°C]

ST1S10 Typical performance characteristics

Figure 19. Efficiency vs. temperature Figure 20. Efficiency vs. output

100

100

90

90

80

80

70

70

EFFICIENCY [%]

EFFICIENCY [%]

60

60

50

50

-50 -25 0 25 50 75 100 125

-50 -25 0 25 50 75 100 125

V

V

IN-A=VIN-SW=VINH

IN-A=VIN-SW=VINH

=12V, V

=12V, V

TEMPERATURE [°C]

TEMPERATURE [°C]

=5V, I

=3A

=5V, I

=3A

OUT

OUT

OUT

OUT

current@V

100

100

90

90

80

80

70

70

EFFICIENCY [%]

EFFICIENCY [%]

60

60

50

50

00.511.522.53

00.511.522.53

V

V

IN-A=VIN-SW=VINH

IN-A=VIN-SW=VINH

OUTPUT CURRENT [A]

OUTPUT CURRENT [A]

out

= 5 V

=12V, V

=12V, V

=5V, TJ=25°C

=5V, TJ=25°C

OUT

OUT

Figure 21. Efficiency vs. output

100

100

90

90

80

80

70

70

EFFICIENCY [%]

EFFICIENCY [%]

60

60

50

50

current@V

V

V

IN-A=VIN-SW=VINH

IN-A=VIN-SW=VINH

0 0.5 1 1.5 2 2.5 3

0 0.5 1 1.5 2 2.5 3

OUTPUT CURRENT [A]

OUTPUT CURRENT [A]

out

=5V, V

=5V, V

= 3.3 V

=3.3V, TJ=25°C

=3.3V, TJ=25°C

OUT

OUT

Figure 22. Efficiency vs. output

current@V

100

100

90

90

80

80

70

70

EFFICIENCY [%]

EFFICIENCY [%]

60

60

50

50

00.511.522.53

00.511.522.53

V

V

IN-A=VIN-SW=VINH

IN-A=VIN-SW=VINH

OUTPUT CURRENT [A]

OUTPUT CURRENT [A]

out

= 12 V

=16V, V

=16V, V

=12V, TJ=25°C

=12V, TJ=25°C

OUT

OUT

Doc ID 13844 Rev 5 21/29

Package mechanical data ST1S10

9 Package mechanical data

In order to meet environmental requirements, ST offers these devices in different grades of

®

ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK

packages, depending on their level of environmental compliance. ECOPACK®

®

is an ST trademark.

Table 6. Power SO-8 (exposed pad) mechanical data

mm

Dim.

Min. Typ. Max.

A 1.70

A1 0.00 0.15

A2 1.25

b0.31 0.51

c0.17 0.25

D4.804.905.00

D1 ACCORDING TO PAD SIZE

E5.806.006.20

E1 3.80 3.90 4.00

E2 ACCORDING TO PAD SIZE

e1.27

h0.25 0.50

L0.40 1.27

K0 8

ccc 0.10

Note: Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash,

protrusions or gate burrs shall not exceed 0.15mm in total (both side).

Dimension "E1" does not include interlead flash or protrusions.

Interlead flash or protrusions shall not exceed 0.25mm per side.

The size of exposed pad is variable depending of leadframe design pad size.

End user should verify "D1" and "E2" dimensions for each device application

22/29 Doc ID 13844 Rev 5

ST1S10 Package mechanical data

Figure 23. Power SO-8 (exposed pad) dimensions

7195016_D

Doc ID 13844 Rev 5 23/29

Package mechanical data ST1S10

Figure 24. Power SO-8 (exposed pad) recommended footprint

24/29 Doc ID 13844 Rev 5

ST1S10 Package mechanical data

Table 7. Power SO-8 (exposed pad) tape and reel mechanical data

mm

Dim.

Min. Typ. Max.

A 330

C 12.8 13.2

D20.2

N60

T 22.4

Ao 8.1 8.5

Bo 5.5 5.9

Ko 2.1 2.3

Po 3.9 4.1

P7.9 8.1

Figure 25. Power SO-8 (exposed pad) tape and reel dimensions

Doc ID 13844 Rev 5 25/29

Package mechanical data ST1S10

Table 8. DFN8 (4X4) mechanical data

Dim.

Min. Typ. Max.

A 0.80 0.90 1.00

A1 0 0.02 0.05

A3 0.20

b 0.23 0.30 0.38

D 3.90 4.00 4.10

D2 2.82 3.00 3.23

E 3.90 4.00 4.10

E2 2.05 2.20 2.30

e0.80

L 0.40 0.50 0.60

Figure 26. DFN8 (4x4) dimensions

mm.

26/29 Doc ID 13844 Rev 5

7869653B

ST1S10 Package mechanical data

Table 9. DFN8 (4x4)tape and reel mechanical data

mm

Dim.

Min. Typ. Max.

A 330

C 12.8 13.2

D20.2

N99 101

T 14.4

Ao 4.35

Bo 4.35

Ko 1.1

Po 4

P8

Figure 27. DFN8 (4x4)tape and reel dimensions

Doc ID 13844 Rev 5 27/29

Revision history ST1S10

10 Revision history

Table 10. Document revision history

Date Revision Changes

28-Aug-2007 1 Initial release.

24-Sep-2007 2 Add R

25-Oct-2007 3 Added new paragraph 6: Layout considerations.

16-Mar-2010 4 Updated PowerSO-8 package mechanical data.

Updated SO-8 (epad)and DFN8 (4x4) mechanical data.

31-May-2012 5

Changed temperature min from 25

Section 4.

on Ta b l e 4.

thJC

°C to 40 °C in Table 4, and in

28/29 Doc ID 13844 Rev 5

ST1S10

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Doc ID 13844 Rev 5 29/29