ST ST1L05, ST1L05A, ST1L05B, ST1L05C, ST1L05D User Manual

ST1L05 - ST1L05A ST1L05B - ST1L05C - ST1L05D

Very low quiescent BiCMOS voltage regulator

Features

■Fixed output voltage: 1.8 V, 2.5 V, 3.3 V and ADJ

■Output voltage tolerance: ± 2 % at 25 °C

■Output current capability: 1.3 A

■Very low quiescent current: max 650 µA Over temperature range

■Typ. dropout 0.3 V (@ IO =1.3 A)

■Enable function for the B, C and D versions

■Power Good function for the B and D versions

■Stable with low ESR ceramic capacitors

■Thermal shutdown protection with hysteresis

■Overcurrent protection

■Operating junction temperature range: from 0 to 125 °C

Description

The ST1L05 family is a low drop linear voltage regulator capable of supplying up to 1.3 A output current.

The output voltage is fixed at 1.8 V, 2.5 V, 3.3 V and Adjustable. It is available in three different versions with different pin outs.

Thanks to BiCMOS technology, the quiescent current is controlled and maintained below 650 µA over the entire allowed junction temperature

DFN6 (3 x 3 mm)

DFN8 (4 x 4 mm)

range. The ST1L05 is stable with low ESR output ceramic capacitors.

Internal protection circuitry includes thermal protection with hysteresis and overcurrent limiting.

The ST1L05 is especially suitable for data storage applications such as HDDs, where it can be used to supply the 3.3 V required by read channel and memory chips.

The regulator is available in the small and thin DFN6 (3 x 3) and DFN8 (4 x 4) packages.

Table 1.	Device summary
Order codes			Packages	Output voltages
ST1L05PU25R			DFN6D (3 x 3 mm)	2.5 V
ST1L05APU33R			DFN6D (3 x 3 mm)	3.3 V
ST1L05BPUR			DFN6D (3 x 3 mm)	ADJ
ST1L05CPU33R			DFN6D (3 x 3 mm)	3.3 V
ST1L05DPUR			DFN8 (4 x 4 mm)	ADJ
September 2009			Doc ID 14492 Rev 2	1/24

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Contents	ST1L05, ST1L05A, ST1L05B, ST1L05C, ST1L05D

Contents

1	Schematic diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. 3
2	Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		5
3	Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		6
4	Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		7
5	Typical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		11
6	Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		14
	6.1	Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	16
	6.2	Enable function (ST1L05B, ST1L05C and ST1L05D only) . . . . . . . . . . .	16
	6.3	Power Good function (ST1L05B and ST1L05D only) . . . . . . . . . . . . . . . .	16
7	Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		17
8	Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		23

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ST1L05, ST1L05A, ST1L05B, ST1L05C, ST1L05D	Schematic diagrams

1 Schematic diagrams

Figure 1. Schematic diagram for ST1L05

VI

VI

BandGap reference

	OpAmp	Current
		limit

Thermal	VO
protection	VO_SENSE
	R1
	R2

GND

Figure 2. Schematic diagram for ST1L05A

VI

VI

BandGap reference

	OpAmp	Current
		limit

VO

Thermal protection

R1

R2

GND

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Schematic diagrams		ST1L05, ST1L05A, ST1L05B, ST1L05C, ST1L05D
Figure 3. Schematic diagram for ST1L05B and ST1L05D
VI		Power-good PG
		signal
		VI
	BandGap
	reference	Current
	OpAmp
		limit
		VO
		Thermal
		protection
	VI	ADJ

RP

EN

Internal enable

GND

Figure 4. Schematic diagram for ST1L05C

VI		Power-good	PG
		signal
			VI
	BandGap
	reference	Current
	OpAmp
		limit
		Thermal	VO
		protection

VI

ADJ

RP

EN

Internal enable

GND

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ST1L05, ST1L05A, ST1L05B, ST1L05C, ST1L05D	Pin configuration

2 Pin configuration

Figure 5. Pin connections (top through view)

	ST1L05	ST1L05A	ST1L05B
	ST1L05C		ST1L05D
Table 2.	Pin description

	Symbol			Pin n°			Function
		ST1L05	ST1L05A	ST1L05B	ST1L05C	ST1L05D
	VI	6	3	6	6	8	Supply voltage input pin. Bypass with a 4.7
							µF capacitor to GND
	VO	4	2	4	4	6	Output voltage pin. Bypass with a 4.7 µF
							capacitor to GND
	GND	2	6	2	2	2	Ground pin
	ADJ	-	-	5	-	7	Adjust pin
	VO_SENSE	5	-	-	5	-	VO sense
	PG	-	-	3	-	3	Power Good pin
	EN	-	-	1	1	1	Enable pin. Internal pull-up to VI
	NC	1,3	1,4,5	-	3	4, 5	Not connected
	GND			EXP			Exposed pad must be connected to GND

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Maximum ratings				ST1L05, ST1L05A, ST1L05B, ST1L05C, ST1L05D
3	Maximum ratings
Table 3.	Absolute maximum ratings
Symbol			Parameter			Value		Unit
VI			DC supply voltage			-0.3 to 7		V
VO			DC output voltage			-0.3 to 7		V
PG			Power Good pin			-0.3 to 7		V
EN			Enable pin			-0.3 to 7		V
ADJ/VOUT_SENSE			Adjust pin or VO sense			4		V
PD			Power dissipation			internally limited		W
IO			Output current			internally limited		A
TOP			Operating junction temperature range			0 to 150		°C
T			Storage temperature range (1)			-65 to 150		°C
STG
TLEAD			Lead temperature (soldering) 10 Sec.			260		°C
1. Storage temperature > 125 °C are acceptable only if the regulator is soldered to a PCBA.
Note:	Absolute maximum ratings are those values beyond which damage to the device may occur.
	Functional operation under these condition is not implied.
Table 4.	Thermal data
Symbol			Parameter	DFN6		DFN8		Unit
RthJC		Thermal resistance junction-case		10		4		°C/W
RthJA		Thermal resistance junction-ambient		55		40		°C/W
Table 5.	ESD data
Symbol			Parameter			Value		Unit
HBM			Human body model			2		kV
MM			Machine model			150		V

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ST1L05, ST1L05A, ST1L05B, ST1L05C, ST1L05D	Electrical characteristics

4 Electrical characteristics

Refer to the typical application schematic, VI = 3.3 V to 4.5 V, IO = 5 mA to 1.3 A,

CI = CO = 4.7 µF, TJ = 0 to 125 °C, unless otherwise specified. Typical values are intended at TJ = 25 °C unless otherwise specified.

Table 6.

Electrical characteristics for the ST1L05PU25

Symbol

Parameter

Test condition

Min.

Typ.

Max.

Unit

VO

Output voltage

VI =3.3V to 5.25V, T=25°C

2.45

2.5

2.55

V

VO

Output voltage

VI = 3.3V to 5.25V

2.4375

2.5

2.5625

V

VO

Line regulation

VI = 4.75V to 5.25V

15

mV

VO

Load regulation

VI = 4.75V, IO = 10mA to 1.3A

15

30

mV

IS

Output current limit

VI = 5.5V

1.3

A

IOMIN

Minimum output current for

0

mA

regulation

IO = 0.8A

0.2

0.4

V

Vd

Dropout voltage

IO = 1A

0.25

0.45

V

IO = 1.3A

0.3

0.5

V

IQ

Quiescent current

VI = 5V, IO = 2mA to 1.3A, T=25°C

350

500

µA

VI = 5.5V, IO = 2mA to 1.3A

350

650

SVR

Supply voltage rejection (1)

V

I

= 5±0.5V, I = 5mA, f=120Hz

50

68

dB

O

eN

RMS output noise (1)

B = 10Hz to 10kHz, VI = 5V,

0.003

%V

IO=5mA

O

V

/

I

O

Load transient (rising) (1)(2)

VI =5V, any 200mA step from

5

%V

O

100mA to 1.3A, tR ≥ 1µs

O

V

/

I

O

Load transient (falling) (1)(2)

V

I

=5V, I

O

= 1.3A to 10mA, t

F

≥ 1µs

2.75

V

O

V

/

V

I

Start-up transient (1)(2)

VI =0V to 5V, IO = 10mA to 1.3A,

2.75

V

O

tR ≥ 1µs

V

/

I

O

Short circuit removal response

V

I

=5V, I

O

= short to 10mA

2.75

V

O

(1)(2)

TSH

Thermal shutdown trip point (1)

VI =5V

165

°C

1.Guaranteed by design. Not tested in production

2.CI =10µF, CO =10µF, all X7R ceramic capacitors.

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Electrical characteristics	ST1L05, ST1L05A, ST1L05B, ST1L05C, ST1L05D

Refer to the typical application schematic, VI = 4.5 V to 5.5 V, IO = 5 mA to 1.3 A,

CI = CO = 4.7 µF, TJ = 0 to 125 °C, unless otherwise specified). Typical values are intended at TJ = 25 °C unless otherwise specified.

Table 7.

Electrical characteristics for ST1L05APU33

Symbol

Parameter

Test condition

Min.

Typ.

Max.

Unit

VO

Output voltage

VI = 4.75V to 5.25V, T=25°C

3.234

3.3

3.366

V

VO

Output voltage

VI = 4.75V to 5.25V

3.2175

3.3

3.3825

V

VO

Line regulation

VI = 4.75V to 5.25V

15

mV

VO

Load regulation

VI = 4.75V, IO = 10mA to 1.3A

15

30

mV

IS

Output current limit

VI = 5.5V

1.3

A

IOMIN

Minimum output current for

0

mA

regulation

IO = 0.8A

0.2

0.4

V

Vd

Dropout voltage

IO = 1A

0.25

0.45

V

IO = 1.3A

0.3

0.5

V

IQ

Quiescent current

VI = 5V, IO = 2mA to 1.3A, T=25°C

350

500

µA

VI = 5.5V, IO = 2mA to 1.3A

350

650

SVR

Supply voltage rejection (1)

V

I

= 5±0.5V, I = 5mA, f=120Hz

50

65

dB

O

eN

RMS output noise (1)

B = 10Hz to 10kHz, V

I

= 5V, I

=5mA

0.003

%V

O

O

V

/

I

O

Load transient (rising) (1)(2)

VI =5V, any 200mA step from 100mA

5

%V

O

to 1.3A, tR ≥ 1µs

O

V

/

I

O

Load transient (falling) (1)(2)

V

I

=5V, I

O

= 1.3A to 10mA, t

F

≥ 1µs

3.6

V

O

V

/

V

I

Start-up transient (1)(2)

VI =0V to 5V, IO = 10mA to 1.3A,

3.5

V

O

tR ≥ 1µs

V

/

I

O

Short circuit removal response

V

I

=5V, I

O

= short to 10mA

3.5

V

O

(1)(2)

TSH

Thermal shutdown trip point( 1)

VI =5V

165

°C

1.Guaranteed by design. Not tested in production.

2.CI =10µF, CO =10µF, all X7R ceramic capacitors.

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