ST ST10F296E User Manual

16-bit MCU with MAC unit, 832 Kbyte Flash memory

www.BDTIC.com/ST

Features

■ High performance 16-bit CPU with DSP

functions
– 31.25 ns instruction cycle time at 64 MHz

max CPU clock

– Multiply/accumulate unit (MAC) 16 x 16-bit

multiplication, 40-bit accumulator

– Enhanced boolean bit manipulation

facilities

– Single-cycle context switching support

■ Memory organization

– 512 Kbyte Flash memory (32-bit fetch)
– 320 Kbyte extension Flash memory

(16-bit fetch)
– 100 k erasing/programming cycles
– Up to 16 Mbyte linear address space for

code and data (5 Mbytes with CAN or I
– 2 Kbyte on-chip internal RAM (IRAM)
– 66 Kbyte on-chip extension RAM (XRAM)
– Programmable external bus characteristics

for different address ranges
– Five programmable chip-select signals
– Hold-acknowledge bus arbitration support

■ Interrupt

– 8-channel peripheral event controller for

single cycle interrupt driven data transfer
– 16-priority-level interrupt system with 56

sources, sampling rate down to 15.6 ns

■ Timers

– Two multi-functional general purpose timer

units with 5 timers

■ Two 16-channel capture/compare units

■ Analog-to-digital converter (ADC)

– 32-channel 10-bit
–3 µs minimum conversion time
– TImer for ADC channel injection

■ 4-channel PWM unit and 4-channel XPWM

ST10F296E

and 68 Kbyte RAM

PBGA 208

(23 x 23 x 1.96 mm)

■ Serial channels

– Two synchronous/asynch. serial channels
– Two high-speed synchronous channels

2

C standard interface

–I

■ Two CAN 2.0B interfaces operating on one or

two CAN busses (64 or 2 x 32 message
objects, C-CAN version)

2

C)

■ Fail-safe protection

– Programmable watchdog timer
– Oscillator watchdog

■ On-chip bootstrap loader

■ Clock generation

– On-chip PLL and 4-12 MHz oscillator
– Direct or prescaled clock input

■ Real-time clock

■ Up to 143 general purpose I/O lines

– Individually programmable as input, output

or special function

– Programmable threshold (hysteresis)

■ Idle, power-down and stand-by modes

■ single voltage supply: 5 V ±10% (embedded

regulator for 1.8 V core supply).

Table 1. Device summary

Order codes

ST10F296

ST10F296TR

Temp. range

(°C)

-40 to 125 1 to 64

CPU freq. range

(MHz)

October 2008 Rev 2 1/346

www.st.com

1

Contents ST10F296E

www.BDTIC.com/ST

Contents

1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2 Ball data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

4 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

4.1 IFlash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

4.2 XFlash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

4.3 Internal RAM (IRAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

4.4 Extension RAM (XRAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

4.5 Special function register (SFR) areas . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

4.6 CAN1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

4.7 CAN2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

4.8 Real-time clock (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

4.9 Pulse-width modulation 1 (PWM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

4.10 ASC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

4.11 SSC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

4.12 I

4.13 XTimer/XMiscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

4.14 XPort 9/XPort 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

4.15 Visibility of XBus peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

4.16 XPeripheral configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

2

C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

5 Internal Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

5.1 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

5.1.1 Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

5.1.2 Module structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

5.1.3 Low power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

2/346

5.2 Write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

5.2.1 Power supply drop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

5.3 Internal Flash memory registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

ST10F296E Contents

www.BDTIC.com/ST

5.4 Protection strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

5.4.1 Protection registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

5.4.2 Access protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

5.4.3 Write protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

5.4.4 Temporary unprotection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

5.5 Write operation examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

5.5.1 Word program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

5.5.2 Double word program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

5.5.3 Sector erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

5.5.4 Suspend and resume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

5.5.5 Erase suspend, program and resume . . . . . . . . . . . . . . . . . . . . . . . . . . 63

5.5.6 Set protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

5.6 Write operation summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

6 The bootstrap loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

6.1 Selection among user-code, standard or alternate bootstrap . . . . . . . . . 66

6.2 Standard bootstrap loader (BSL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

6.2.1 Entering the standard bootstrap loader . . . . . . . . . . . . . . . . . . . . . . . . . 67

6.2.2 ST10 configuration in BSL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

6.2.3 Booting steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

6.2.4 Hardware to activate BSL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

6.2.5 Memory configuration in bootstrap loader mode . . . . . . . . . . . . . . . . . . 71

6.2.6 Loading the startup code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

6.2.7 Exiting bootstrap loader mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

6.2.8 Hardware requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

6.3 Standard bootstrap with UART (RS232 or K-line) . . . . . . . . . . . . . . . . . . 73

6.3.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

6.3.2 Entering bootstrap via UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

6.3.3 ST10 configuration in UART BSL (RS232 or K-line) . . . . . . . . . . . . . . . 75

6.3.4 Loading the startup code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

6.3.5 Choosing the baud rate for the BSL via UART . . . . . . . . . . . . . . . . . . . 76

6.4 Standard bootstrap with CAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

6.4.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

6.4.2 Entering the CAN bootstrap loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

6.4.3 ST10 configuration in CAN BSL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

6.4.4 Loading the startup code via CAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

3/346

Contents ST10F296E

www.BDTIC.com/ST

6.4.5 Choosing the baud rate for the BSL via CAN . . . . . . . . . . . . . . . . . . . . 82

6.4.6 How to compute the baud rate error . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

6.4.7 Bootstrap via CAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

6.5 Comparing the old and the new bootstrap loader . . . . . . . . . . . . . . . . . . 85

6.5.1 Software aspects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

6.5.2 Hardware aspects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

6.6 Alternate boot mode (ABM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

6.6.1 Activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

6.6.2 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

6.6.3 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

6.6.4 ST10 configuration in alternate boot mode . . . . . . . . . . . . . . . . . . . . . . 87

6.6.5 Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

6.6.6 Exiting alternate boot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

6.6.7 Alternate boot user software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

6.6.8 User/alternate boot mode signature check . . . . . . . . . . . . . . . . . . . . . . 88

6.6.9 Alternate boot user software aspects . . . . . . . . . . . . . . . . . . . . . . . . . . 89

6.6.10 Internal decoding of test modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

6.6.11 Example of alternate boot mode operation . . . . . . . . . . . . . . . . . . . . . . 89

6.7 Selective boot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

7 Central processing unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

7.1 Multiplier-accumulator unit (MAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

7.2 Instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

7.3 MAC coprocessor specific instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

8 External bus controller (EBC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

8.1 Programmable chip select timing control . . . . . . . . . . . . . . . . . . . . . . . . . 98

8.2 READY

8.3 EA

programmable polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

9 Interrupt system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

9.1 XPeripheral interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

10 Capture/compare (CAPCOM) units . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

4/346

9.2 Exception and error traps list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

ST10F296E Contents

www.BDTIC.com/ST

11 General purpose timer unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

11.1 GPT1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

11.2 GPT2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

12 Pulse-width modulation (PWM) modules . . . . . . . . . . . . . . . . . . . . . . 114

12.1 XPWM output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

12.2 XPWM registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

12.2.1 Software control of the XPWM outputs . . . . . . . . . . . . . . . . . . . . . . . . 116

13 Parallel ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

13.1 I/O special features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

13.1.1 Open-drain mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

13.1.2 Input threshold control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

13.1.3 I/0 port registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

13.1.4 Alternate port functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

13.2 Port 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

13.2.1 Port 0 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

13.2.2 Alternate functions of Port 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

13.3 Port 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

13.3.1 Port 1 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

13.3.2 Alternate functions of Port 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

13.4 Port 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

13.4.1 Port 2 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

13.4.2 Alternate functions of Port 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

13.4.3 Port 2 and external interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

13.5 Port 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

13.5.1 Port 3 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

13.5.2 Alternate functions of Port 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

13.6 Port 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

13.6.1 Port 4 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

13.6.2 Alternate functions of Port 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

13.7 Port 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

13.7.1 Port 5 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

13.7.2 Alternate functions of port 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

13.7.3 Port 5 analog inputs disturb protection . . . . . . . . . . . . . . . . . . . . . . . . 152

13.8 Port 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

5/346

Contents ST10F296E

www.BDTIC.com/ST

13.8.1 Port 6 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

13.8.2 Alternate functions of Port 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

13.9 Port 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

13.9.1 Port 7 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

13.9.2 Alternate functions of Port 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

13.10 Port 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

13.10.1 Port 8 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

13.10.2 Alternate functions of Port 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

13.11 XPort 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

13.11.1 XPort 9 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

13.12 XPort 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

13.12.1 XPort 10 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

13.12.2 Alternate functions of XPort 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

13.12.3 XPort 10 analog inputs disturb protection . . . . . . . . . . . . . . . . . . . . . . 174

14 Analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

14.1 Mode selection and operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

14.2 Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

14.3 XTimer module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

14.3.1 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

15 Serial channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

15.1 Asynchronous/synchronous serial interface (ASC0) . . . . . . . . . . . . . . . 183

15.1.1 ASC0 in asynchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

15.1.2 Asynchronous mode baud rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

15.1.3 ASC0 in synchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186

15.1.4 Synchronous mode baud rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186

15.2 Asynchronous/synchronous serial interface (ASC1) . . . . . . . . . . . . . . . 188

15.3 High speed synchronous serial interface (SSC0) . . . . . . . . . . . . . . . . . . 188

15.3.1 Baud rate generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189

15.4 High speed synchronous serial interface (SSC1) . . . . . . . . . . . . . . . . . . 190

16 I2C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191

17 CAN modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

6/346

16.1 I2C bus speed selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191

ST10F296E Contents

www.BDTIC.com/ST

17.1 CAN module memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

17.1.1 CAN1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

17.1.2 CAN2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

17.2 Configuration support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193

17.3 Clock prescaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193

17.4 CAN bus configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194

17.4.1 Single CAN bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194

17.4.2 Multiple CAN bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

17.4.3 Parallel mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

17.5 System clock tolerance range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

17.6 Configuration of the CAN controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199

17.7 Calculation of the bit timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . 200

17.7.1 Example of bit timing at high baud rate . . . . . . . . . . . . . . . . . . . . . . . . 201

17.7.2 Example of bit timing at low baud rate . . . . . . . . . . . . . . . . . . . . . . . . . 202

18 Real-time clock (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203

18.1 RTC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205

18.2 Programming the RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209

19 Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211

20 System reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214

20.1 Input filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214

20.2 Asynchronous reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215

20.2.1 Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215

20.2.2 Hardware reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218

20.2.3 Exit from asynchronous reset state . . . . . . . . . . . . . . . . . . . . . . . . . . . 219

20.3 Synchronous reset (warm reset) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220

20.3.1 Short and long synchronous reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221

20.3.2 Exit from synchronous reset state . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222

20.3.3 Synchronous reset and the RPD pin . . . . . . . . . . . . . . . . . . . . . . . . . . 222

20.4 Software reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226

20.5 Watchdog timer reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227

20.6 Bidirectional reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229

20.6.1 WDTCON flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230

20.7 Reset circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233

7/346

Contents ST10F296E

www.BDTIC.com/ST

20.8 Reset application examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235

20.9 Reset summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237

21 Power reduction modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240

21.1 Idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240

21.2 Power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240

21.2.1 Protected power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241

21.2.2 Interruptible power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241

21.3 Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244

21.3.1 Entering standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244

21.3.2 Exiting standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245

21.4 Power reduction modes summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246

22 Programmable output clock divider . . . . . . . . . . . . . . . . . . . . . . . . . . 247

23 Register set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248

23.1 Register description format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248

23.2 General purpose registers (GPRs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249

23.3 SFRs ordered by name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251

23.4 SFRs ordered by address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258

23.5 X registers ordered by name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265

23.6 X registers ordered by address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270

23.7 Flash registers ordered by name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276

23.8 Flash registers ordered by address . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277

23.9 Identification registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278

23.10 System configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280

23.10.1 XPEREMU register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290

23.11 Emulation dedicated registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291

24 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292

24.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292

8/346

24.2 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 293

24.3 Power considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293

24.4 Parameter interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294

24.5 DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295

ST10F296E Contents

www.BDTIC.com/ST

24.6 Flash characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300

24.7 ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302

24.7.1 Conversion timing control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303

24.7.2 ADC conversion accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304

24.7.3 Analog reference pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306

24.7.4 Analog input pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306

24.7.5 Example of external network sizing . . . . . . . . . . . . . . . . . . . . . . . . . . . 310

24.8 AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311

24.8.1 Test waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311

24.8.2 Definition of internal timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312

24.8.3 Clock generation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313

24.8.4 Prescaler operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314

24.8.5 Direct drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314

24.8.6 Oscillator watchdog (OWD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315

24.8.7 Phase-locked loop (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315

24.8.8 Voltage controlled oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316

24.8.9 PLL jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317

24.8.10 Jitter in the input clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317

24.8.11 Noise in the PLL loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317

24.8.12 PLL lock/unlock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319

24.8.13 Main oscillator specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319

24.8.14 External clock drive XTAL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320

24.8.15 Memory cycle variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321

24.8.16 External memory bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322

24.8.17 READY

24.8.18 External bus arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336

24.8.19 High-speed synchronous serial interface (SSC) timing modes . . . . . . 338

and CLKOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334

25 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342

26 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344

27 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345

9/346

List of tables ST10F296E

www.BDTIC.com/ST

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. Ball description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 3. Address ranges for IFlash. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 4. Address ranges for IFlash. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 5. XPERCON register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 6. Segment 8 address range mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Table 7. Flash module absolute mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 8. Sectorization of the Flash modules (read operations) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 9. Sectorization of the Flash modules (write operations or with ROMS1 = 1) . . . . . . . . . . . . 44

Table 10. Control register interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 11. FCR0L register decription. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 12. FCR0H register decription . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Table 13. FCR1L register description (SMOD = 0, XFlash selected) . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 14. FCR1L register description (SMOD = 1, IFlash selected). . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 15. FCR1H register description (SMOD = 0, XFlash selected). . . . . . . . . . . . . . . . . . . . . . . . . 51

Table 16. FCR1H register description (SMOD = 1, IFlash selected) . . . . . . . . . . . . . . . . . . . . . . . . . 52

Table 17. Banks (BxS) and sectors (BxFy) status bits meaning. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Table 18. FDR0L register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Table 19. FDR0H register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Table 20. FDR1L register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Table 21. FDR1H register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Table 22. FARL register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Table 23. FARH register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Table 24. FER register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Table 25. XFICR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Table 26. FNVWPXRL register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Table 27. FNVWPXRH register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Table 28. FNVWPIRL register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Table 29. FNVWPIRH register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Table 30. FNVAPR0 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Table 31. FNVAPR1L register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Table 32. FNVAPR1H register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Table 33. Summary of access protection levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Table 34. Flash write operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Table 35. ST10F296E boot mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Table 36. ST10 configuration in BSL mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Table 37. ST10 configuration in UART BSL mode (RS232 or K-line). . . . . . . . . . . . . . . . . . . . . . . . . 75

Table 38. ST10 configuration in CAN BSL mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Table 39. Timer content ranges of BRP value in Equation 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Table 40. Software topics summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Table 41. Hardware topics summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Table 42. ST10 configuration in alternate boot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Table 43. EMUCON register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Table 44. Selective boot mode configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Table 45. Instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Table 46. MAC instruction set summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Table 47. Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Table 48. XInterrupt detailed mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

10/346

ST10F296E List of tables

www.BDTIC.com/ST

Table 49. Trap priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Table 50. Compare modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Table 51. CAPCOM timer input frequencies, resolution, and periods at 40 MHz . . . . . . . . . . . . . . . 109

Table 52. CAPCOM timer input frequencies, resolution, and periods at 64 MHz . . . . . . . . . . . . . . . 109

Table 53. GPT1 timer input frequencies, resolution, and periods at 40 MHz . . . . . . . . . . . . . . . . . . 111

Table 54. GPT1 timer input frequencies, resolution, and periods at 64 MHz . . . . . . . . . . . . . . . . . . 111

Table 55. GPT2 timer input frequencies, resolution, and period at 40 MHz . . . . . . . . . . . . . . . . . . . 112

Table 56. GPT2 timer input frequencies, resolution, and period at 64 MHz . . . . . . . . . . . . . . . . . . . 112

Table 57. PWM unit frequencies and resolution at 40 MHz CPU clock . . . . . . . . . . . . . . . . . . . . . . 114

Table 58. PWM unit frequencies and resolution at 64 MHz CPU clock . . . . . . . . . . . . . . . . . . . . . . 115

Table 59. XPOLAR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Table 60. XPWMPORT register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Table 61. PICON register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Table 62. XPICON register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Table 63. XPICON9 register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

Table 64. XPICON9SET register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

Table 65. XPICON9CLR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

Table 66. XPICON10 register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

Table 67. P0L and P0H register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

Table 68. DP0L and DP0H register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

Table 69. P1L and P1H register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

Table 70. DP1L and DP1H register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

Table 71. P2 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

Table 72. DP2 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

Table 73. ODP2 register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

Table 74. Alternate functions of Port 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

Table 75. EXISEL register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

Table 76. External interrupt selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

Table 77. P3 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

Table 78. DP3 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

Table 79. ODP3 register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

Table 80. Port 3 alternative functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

Table 81. P4 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

Table 82. DP4 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

Table 83. ODP4 register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

Table 84. Port 4 alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

Table 85. P5 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

Table 86. Port 5 alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

Table 87. P5DIDIS register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

Table 88. P6 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

Table 89. DP6 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

Table 90. ODP6 register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

Table 91. ODP6 register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

Table 92. Port 6 alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

Table 93. P7 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

Table 94. DP7 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

Table 95. ODP7 register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

Table 96. Port 7 alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

Table 97. P8 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

Table 98. DP8 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

Table 99. ODP8 register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

Table 100. XS1PORT register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

11/346

List of tables ST10F296E

www.BDTIC.com/ST

Table 101. Port 8 alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

Table 102. XP9 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

Table 103. XP9SET register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

Table 104. XP9CLR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

Table 105. XDP9 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

Table 106. XDP9SET register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

Table 107. XDP9CLR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

Table 108. XODP9 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

Table 109. XODP9SET register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

Table 110. XODP9CLR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

Table 111. XP10 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

Table 112. XPort 10 alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

Table 113. XP10DIDIS register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

Table 114. XP10DIDISSET register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

Table 115. XP10DIDISCLR register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

Table 116. ADC programming at f

= 64 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

CPU

Table 117. Different counting modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

Table 118. Commonly used baud rates by reload value and deviation error

= 40 MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

(f

CPU

Table 119. Commonly used baud rates by reload value and deviation error

= 64 MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

(f

CPU

Table 120. Commonly used baud rates by reload value and deviation error

= 40 MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

(f

CPU

Table 121. Commonly used baud rates by reload value and deviation errors

= 64 MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

(f

Table 122. Synchronous baud rate and reload values (f

CPU

Table 123. Synchronous baud rate and reload values (f

= 40 MHz) . . . . . . . . . . . . . . . . . . . . . . 189

CPU

= 64 MHz) . . . . . . . . . . . . . . . . . . . . . . 190

CPU

Table 124. RTCCON register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205

Table 125. EXISEL register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209

Table 126. Interrupt sources associated with the RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210

Table 127. WDTCON register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212

Table 128. WDTCON bit values on different resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212

Table 129. WDTREL reload value (f
Table 130. WDTREL reload value (f

= 40 MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213

CPU

= 64 MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213

CPU

Table 131. Reset event definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214

Table 132. Reset events summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237

Table 133. Latched configurations of Port 0 for the different reset events . . . . . . . . . . . . . . . . . . . . . 238

Table 134. EXICON register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241

Table 135. Power reduction modes summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246

Table 136. XCLKOUTDIV register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247

Table 137. Word register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248

Table 138. General purpose registers (GPRs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249

Table 139. General purpose registers (GPRs) bit wise addressing . . . . . . . . . . . . . . . . . . . . . . . . . . 250

Table 140. SFRs ordered by name. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251

Table 141. SFRs ordered by address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258

Table 142. X registers ordered by name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265

Table 143. X registers ordered by address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270

Table 144. Flash registers ordered by name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276

Table 145. Flash registers ordered by address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277

Table 146. IDMANUF register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278

Table 147. IDCHIP register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278

Table 148. IDMEM register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279

12/346

ST10F296E List of tables

www.BDTIC.com/ST

Table 149. IDPROG register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279

Table 150. SYSCON register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280

Table 151. BUSCONx register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283

Table 152. RP0H register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284

Table 153. EXICON register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285

Table 154. EXISEL register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286

Table 155. External interrupt selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286

Table 156. xxIC register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287

Table 157. XPERCON register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288

Table 158. Segment 8 address range mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290

Table 159. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292

Table 160. Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293

Table 161. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294

Table 162. Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294

Table 163. DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295

Table 164. Flash characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300

Table 165. Data retention characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301

Table 166. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302

Table 167. ADC programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304

Table 168. On-chip clock generator selections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313

Table 169. Internal PLL divider mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316

Table 170. PLL lock/unlock timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319

Table 171. Main oscillator specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319

Table 172. Negative resistance (absolute min value @125 °C/V

Table 173. External clock drive timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321

Table 174. Memory cycle variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321

Table 175. Multiplexed bus timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322

Table 176. Demultiplexed bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328

Table 177. READY

Table 178. External bus arbitration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336

Table 179. Master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338

Table 180. Slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340

Table 181. PBGA 208 (23 x 23 x 1.96 mm) mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343

Table 182. Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344

Table 183. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345

and CLKOUT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334

= 4.5 V) . . . . . . . . . . . . . . . . . . . 320

DD

13/346

List of figures ST10F296E

www.BDTIC.com/ST

List of figures

Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 2. Pin configuration (bottom view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 3. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 4. ST10F296E on-chip memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Figure 5. Flash modules structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Figure 6. ST10F296E new standard bootstrap loader program flow . . . . . . . . . . . . . . . . . . . . . . . . . 69

Figure 7. Booting steps for the ST10F296E. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Figure 8. Hardware provisions to activate the BSL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Figure 9. Memory configuration after reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Figure 10. UART bootstrap loader sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Figure 11. Baud rate deviation between the host and ST10F296E . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Figure 12. CAN bootstrap loader sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Figure 13. Bit rate measurement over a predefined zero-frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Figure 14. Reference signature computation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Figure 15. Reset boot sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Figure 16. CPU block diagram (MAC unit not included) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Figure 17. MAC unit architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Figure 18. Chip select delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Figure 19. EA

Figure 20. XInterrupt basic structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Figure 21. CAPCOM unit block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Figure 22. Block diagram of CAPCOM timers T0 and T7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Figure 23. Block diagram of CAPCOM timers T1 and T8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Figure 24. Block diagram of GPT1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Figure 25. Block diagram of GPT2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Figure 26. Block diagram of PWM module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

Figure 27. XPWM output signal generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Figure 28. SFRs and pins associated with the parallel ports (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Figure 29. SFRs and pins associated with the parallel ports (B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

Figure 30. Output drivers in push-pull mode and in open-drain mode . . . . . . . . . . . . . . . . . . . . . . . . 124

Figure 31. Hysteresis concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

Figure 32. Port 0 I/O and alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

Figure 33. Block diagram of a Port 0 pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

Figure 34. Port 1 I/O and alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

Figure 35. Block diagram of a Port 1 pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

Figure 36. Port 2 I/O and alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

Figure 37. Block diagram of a Port 2 pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

Figure 38. Port 3 I/O and alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

Figure 39. Block diagram of a Port 3 pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

Figure 40. Block diagram of pins P3.15 (CLKOUT) and P3.12 (BHE

Figure 41. Port 4 I/O and alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

Figure 42. Block diagram of Port 4 pins 3 to 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

Figure 43. Block diagram of pin P4.4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

Figure 44. Block diagram of pin P4.5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

Figure 45. Block diagram of pin P4.6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

Figure 46. Block diagram of pin P4.7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

Figure 47. Port 5 I/O and alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

Figure 48. Block diagram of a Port 5 pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

/V

external circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

STBY

/WRH) . . . . . . . . . . . . . . . . . . . 142

14/346

ST10F296E List of figures

www.BDTIC.com/ST

Figure 49. Port 6 I/O and alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

Figure 50. Block diagram of Port 6 pins 7, 6, 1, 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

Figure 51. Block diagram of pin P6.5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

Figure 52. Block diagram of pins P6.2, P6.3, and P6.4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

Figure 53. Port 7 I/O and alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

Figure 54. Block diagram of Port 7 pins 3 to 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

Figure 55. Block diagram of Port 7 pins 7 to 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

Figure 56. Port 8 I/O and alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

Figure 57. Block diagram of P8 pins 5 to 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

Figure 58. Block diagram of pin P8.6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

Figure 59. Block diagram of pin P8.7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

Figure 60. XPort 10 I/O and alternate functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

Figure 61. Block diagram of an XPort 10 pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

Figure 62. ADC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

Figure 63. XTimer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

Figure 64. Asynchronous mode of serial channel ASC0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

Figure 65. Synchronous mode of serial channel ASC0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186

Figure 66. Synchronous serial channel SSC0 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188

Figure 67. Connection to a single CAN bus via separate CAN transceivers . . . . . . . . . . . . . . . . . . . 194

Figure 68. Connection to a single CAN bus via common CAN transceivers . . . . . . . . . . . . . . . . . . . 194

Figure 69. Connection to two different CAN buses (example for gateway application) . . . . . . . . . . . 195

Figure 70. Connection to one CAN bus with internal parallel mode enabled. . . . . . . . . . . . . . . . . . . 195

Figure 71. ESFRs and port pins associated with the RTC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204

Figure 72. RTC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204

Figure 73. Prescaler registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206

Figure 74. Divider counter registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207

Figure 75. Asynchronous power-on reset (EA
Figure 76. Asynchronous power-on reset (EA
Figure 77. Asynchronous hardware reset (EA
Figure 78. Asynchronous hardware reset (EA
Figure 79. Synchronous short/long hardware reset (EA
Figure 80. Synchronous short/long hardware reset (EA
Figure 81. Synchronous long hardware reset (EA
Figure 82. Synchronous long hardware reset (EA
Figure 83. Software/watchdog timer unidirectional reset (EA
Figure 84. Software/watchdog timer unidirectional reset (EA
Figure 85. Software/watchdog timer bidirectional reset (EA
Figure 86. Software/watchdog timer bidirectional reset (EA
Figure 87. Software/watchdog timer bidirectional reset (EA

Figure 88. Minimum external reset circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234

Figure 89. System reset circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234

Figure 90. Example of software or watchdog bidirectional reset (EA
Figure 91. Example of software or watchdog bidirectional reset (EA

Figure 92. Port 0 bits latched into the different registers after reset . . . . . . . . . . . . . . . . . . . . . . . . . 239

Figure 93. External RC circuit on the RPD

Figure 94. Simplified power-down exit circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243

Figure 95. Power-down exit sequence when using an external interrupt (PLL x 2). . . . . . . . . . . . . . 243

Figure 96. Port 2 test mode structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298

Figure 97. Supply current versus the operating frequency (run and idle modes) . . . . . . . . . . . . . . . 299

Figure 98. AD conversion characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305

Figure 99. ADC input pins scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306

Figure 100. Charge sharing timing diagram during sampling phase . . . . . . . . . . . . . . . . . . . . . . . . . . 307

= 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217

= 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218

= 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219

= 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220

= 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223

= 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224

= 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225

= 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226

= 1). . . . . . . . . . . . . . . . . . . . . . . . . . . 227

= 0). . . . . . . . . . . . . . . . . . . . . . . . . . . 228

= 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . 230

= 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . 231

= 0) followed by a hardware reset . . . . 232

= 1) . . . . . . . . . . . . . . . . . . . . . 235

= 0) . . . . . . . . . . . . . . . . . . . . . 236

pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242

15/346

List of figures ST10F296E

www.BDTIC.com/ST

Figure 101. Anti-aliasing filter and conversion rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309

Figure 102. Input/output waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311

Figure 103. Float waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312

Figure 104. Generation mechanisms for the CPU clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313

Figure 105. ST10F296E PLL jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318

Figure 106. ST10F296ECrystal oscillator and resonator connection diagram. . . . . . . . . . . . . . . . . . . 320

Figure 107. External clock drive XTAL1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321

Figure 108. Multiplexed bus with/without R/W delay and normal ALE. . . . . . . . . . . . . . . . . . . . . . . . . 324

Figure 109. Multiplexed bus with/without R/W delay and extended ALE . . . . . . . . . . . . . . . . . . . . . . 325

Figure 110. Multiplexed bus with/without R/W delay, normal ALE, R/W CS
Figure 111. Multiplexed bus with/without R/ W delay, extended ALE, R/W CS

Figure 112. Demultiplexed bus with/without read/write delay and normal ALE . . . . . . . . . . . . . . . . . . 330

Figure 113. Demultiplexed bus with/without R/W delay and extended ALE . . . . . . . . . . . . . . . . . . . . 331

Figure 114. Demultiplexed bus with ALE and R/W CS
Figure 115. Demultiplexed bus no R/W delay, extended ALE, R/W CS
Figure 116. READY

Figure 117. External bus arbitration (releasing the bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336

Figure 118. External bus arbitration (regaining the bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337

Figure 119. SSC master timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339

Figure 120. SSC slave timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341

Figure 121. PBGA 208 (23 x 23 x 1.96 mm) outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342

and CLKOUT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332

. . . . . . . . . . . . . . . . . . . . 326

. . . . . . . . . . . . . . . . . 327

. . . . . . . . . . . . . . . . . . . . . . . 333

16/346

ST10F296E Description

www.BDTIC.com/ST

1 Description

The ST10F296E is a derivative of the STMicroelectronics ST10 family of 16-bit single-chip
CMOS microcontrollers. It combines high CPU performance (up to 32 million instructions
per second) with high peripheral functionality and enhanced I/O-capabilities. It also provides
on-chip high-speed single voltage Flash memory, on-chip high-speed RAM, and clock
generation via the phase-locked loop (PLL).

ST10F296E is processed in 0.18 µm CMOS technology. The MCU core and the logic is
supplied with a 5 V to 1.8 V on-chip voltage regulator. The part is supplied with a single 5 V
supply and I/Os work at 5 V.

The device is upwardly compatible with the ST10F280 device, with the following differences:

● The Flash control interface is now based on STMicroelectronics third generation of

standalone Flash memories (M29F400 series), with an embedded program/erase
controller. This completely frees up the CPU during programming or erasing of the
Flash.

● Pins DC1 and DC2 of ST10F280, are renamed as V

5.0 V external supply. Instead, these pin should be connected to a decoupling capacitor
(ceramic type, typical value 10 nF, maximum value 100 nF).

● The AC and DC parameters are modified due to a difference in the maximum CPU

frequency.

● The EA pin has assumed a new, alternate functionality: It is also used to provide a

dedicated power supply (see V

) to maintain a portion of the XRAM (16 Kbytes)

STBY

biased when the main power supply of the device (V
generated V

) is turned off for low power mode, thereby allowing data retention. V

18

voltage is in the range 4.5-5.5 V, and a dedicated embedded low power voltage
regulator provides the 1.8 V for the RAM. The upper limit of up to 6 V may be exceeded
for a very short period of time during the global life of the device. The lower limit of 4 V
may also be exceeded.

● A second SSC, mapped on the XBus, has been added (SSC of ST10F280 becomes

SSC0, while the new SSC is referred to as XSSC or SSC1). There are some
restrictions and functional differences due to peculiarities present in the XBus between
the classic SSC and the new XSSC.

● A second ASC, mapped on the XBus, has been added (ASC0 of ST10F280 remains

ASC0, while the new one is referred to as XASC or ASC1). Some restrictions and
functional differences due to peculiarities present in the XBus between the classic
ASC, and the new XASC.

● The second PWM (XPWM), mapped on the XBus, has been improved adding set/clear

command for safe management of the control register. Memory mapping is thus slightly
different.

● An I

● The CLKOUT function can output either the CPU clock (as in ST10F280) or a software

2

C interface on the XBus has been added (see X-I2C or simply I2C interface).

programmable prescaled value of the CPU clock.

● the embedded memory size has been significantly increased (both Flash and RAM).

● PLL multiplication factors have been adapted to new frequency range.

. Do not connect these pins to

18

and consequently the internally

DD

STBY

17/346

Description ST10F296E

www.BDTIC.com/ST

● The ADC is not fully compatible with the ST10F280 (timing and programming model).

The formula for the convertion time is still valid, while the sampling phase programming
model is different.

● The external memory bus potential limitations on maximum speed and maximum

capacitance load are under evaluation and may be introduced: ST10F296E will
probably not be able to address an external memory at 64 MHz with 0 wait states.

● The XPERCON register bit mapping has been modified according to new peripheral

implementation (which is not fully compatible with ST10F280).

● The bondout chip for emulation (ST10R201) cannot achieve more than 50 MHz at room

temperature (so, no real-time emulation is possible at maximum speed).

● Input section characteristics are different. The threshold programmability is extended to

all port pins (additional XPICON register); it is possible to select standard TTL (with up
to 400 mV of hysteresis) and standard CMOS (with up to 750 mV of hysteresis).

● Output transition is not programmable.

● An RTC module has been added.

● The CAN module has been enhanced: ST10F296E implements two C-CAN modules,

so the programming model is slightly different. The possibility to map both CAN
modules simultaneously has been added (on P4.5/P4.6).

● The on-chip main oscillator input frequency range has been reshaped, reducing it from

1-25 MHz to 4-12 MHz. This is a high performance oscillator amplifier, that provides a
very high negative resistance and wide oscillation amplitude. When this on-chip
amplifier is used as a reference for the RTC module, the power-down consumption is
dominated by the consumption of the oscillator amplifier itself. A metal option is added
to offer a low power oscillator amplifier working in the range 4-8 MHz which allows a
power consumption reduction when the RTC is running in power-down mode using the
on-chip main oscillator clock as a reference.

● The possibility to reprogram the internal XBus chip select window characteristics

(XRAM2 and XFlash address window) has been added.

18/346

ST10F296E Description

www.BDTIC.com/ST

Figure 1. Logic diagram

V

V

DDVSS

18

XTAL1
XTAL2

RSTIN

RSTOUT

V

AREF

V

AGND

NMI

EA/V

STBY

READY

ALE

RD

WR/WRL

Port 5

16-bit

XPort 10

16-bit

XADCINJ

RPD

ST10F296E

Port 0
16-bit

Port 1
16-bit

Port 2
16-bit

Port 3
15-bit

Port 4
8-bit

Port 6
8-bit

Port 7
8-bit

Port 8
8-bit

XPort 9
16-bit

XPOUT
3-bit

19/346

Ball data ST10F296E

www.BDTIC.com/ST

2 Ball data

The ST10F296E package is a PBGA measuring 23 x 23 x 1.96 mm. Ball pitch is 1.27 mm.
Pin configuration is shown in Figure 2 while the signal assignment of the balls is given in

Ta bl e 2 . This package has 25 additional thermal balls.

Figure 2. Pin configuration (bottom view)

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

U1

U

XP10.15U2V

T1

T

XP10.14T2P5.0T3P5.2T4P5.4T5P5.8T6P5.12T7P2.0T8P2.3T9P2.4

R1

R

XP10.13R2XP10.12R3P5.1R4P5.3R5P5.7R6P5.11R7P5.15R8P2.2R9P2.6

P1

P

XP10.11P2XP10.10P3XP10.9P4XP10.8P5P5.6P6P5.10P7P5.14P8P2.1P9P2.5

N1

N

XP10.7N2XP10.6N3XP10.5N4XP10.4

M1

M

XP10.3M2XP10.2M3XP10.1M4XP10.0

L1

L

V

SS

K1

K

V

DD

J1

J

P7.3J2P7.2J3P7.1J4P7.0

H1

H

V

SS

G1

G

V

18

F1

F

V

SS

E1

E

V

DD

D1

D

P6.7D2P6.4D3P6.1D4XPOUT0D5V

C1

C

P6.3C2XPOUT3C3XPOUT1C4NMIC5P1H.6C6P1H.7C7P1H.4C8P1H.0C9P1L.7

B1

B

P6.2B2XPOUT2B3V

A1

A

V

SS

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

U3

V

AREF

L2

P7.7L3XADCINJL4V

K2

P7.4K3P7.5K4P7.6

H2

P8.7H3P8.6H4P8.5

G2

P8.4G3P8.3G4V

F2

P8.2F3P8.1F4P6.6

E2

P8.0E3P6.5E4P6.0

A2

V

RSTINA4V

DD

U4

P5.5U5P5.9U6P5.13U7V

AGND

B4

RSTOUTB5V

SS

A3

SS

SS

D6

V

SS

B6

V

SS

A5

XTAL1A6XTAL2A7P1H.2A8V

SS

SS

L7

V

SS

K7

V

SS

J7

V

SS

H7

V

SS

G7

V

SS

D7

P1H.5D8P1H.1D9P1L.6

SS

B7

P1H.3B8V

SS

U8

U9

U10

U11

U12

U13

U14

U15

U16

U17

V

P2.7

V

V

P2.13

V

V

V

DD

L8

V

SS

K8

V

SS

J8

V

SS

H8

V

SS

G8

V

SS

SS

SS

SS

18

T10

T11

P2.8

P2.11

R10

R11

P2.9

P2.12

P10

P11

P2.10

P2.14

L9

L10
V

SS

K10
V

SS

J10
V

SS

H10
V

SS

G10
V

SS

D10

P1L.2

C10

P1L.3

B10

P1L.4

A10

P1L.5

L11
V

SS

K11
V

SS

J11
V

SS

H11
V

SS

G11
V

SS

D11

XP9.14

C11

P1L.0

B11

P1L.1

A11
V

SS

XP9.11

XP9.13

XP9.15

V

SS

K9

V

SS

J9

V

SS

H9

V

SS

G9

V

SS

B9

V

SS

A9

V

DD

T12

P2.15

R12
P3.0

P12
P3.2

D12

C12

B12

A12
V

DD

SS

T13
P3.1

R13
P3.3

P13
P3.5

D13

XP9.5

C13

XP9.10

B13

XP9.12

A13
V

SS

SS

T14
P3.4

R14
P3.6

P14
P3.7

N14

P3.10

M14

P3.13

L14
P4.2

K14
P4.6

J14RDJ15WRJ16

H14

P0L.2

G14

P0L.5

F14

P0H.2

E14

P0H.7

D14

XP9.2

C14

XP9.6

B14

XP9.9

A14
V

DD

DD

T15
V

SS

R15

P3.8

P15

P3.11

N15
V

SS

M15
P4.1

L15

P4.4

K15

P4.7

H15

P0L.1

G15

P0L.4

F15

P0H.0

E15

P0H.4

D15

XP9.0

C15

XP9.3

B15

XP9.7

A15

XP9.8

V

SS

T16
V

SS

R16
P3.9

P16

P3.12

N16
P4.0

M16
P4.3

L16
P4.5

K16
V

SS

READY17ALE

H16

P0L.0

G16

P0L.3

F16

P0L.6

E16

P0H.1

D16

P0H.5

C16

XP9.1

B16

XP9.4

A16
V

SS

V

SS

T17

P3.15

R17
V

SS

P17
V

DD

N17
V

SS

M17

RPD

L17
V

DD

K17
V

SS

H17

EA

G17

V

DD

F17
V

SS

E17

P0L.7

D17

P0H.3

C17

P0H.6

B17
V

SS

A17
V

SS

U

T

R

P

N

M

L

K

J

H

G

F

E

D

C

B

A

20/346

ST10F296E Ball data

www.BDTIC.com/ST

Table 2. Ball description

Symbol

P6.0 to P6.7

Ball

Type Function (including port, pin and alternate function where applicable)

no.

E4 O

D3 O P6.1 CS1

O

B1

I/O SCLK1

8-bit bidirectional I/O port,
bit-wise programmable for

O

input or output via direction

C1

D2

E3 I P6.5 HOLD

F4 O P6.6 HLDA

bit. Programming an I/O pin
as input forces the

I/O MTSR1

corresponding output driver
to high impedance state.
Port 6 outputs can be

O

configured as push-pull or
open-drain drivers. The

I/O MRST1

input threshold of Port 6 is
selectable (TTL or CMOS).

P6.0 CS0

CS2

P6.2

CS3 Chip select 3 output

P6.3

CS4 Chip select 4 output

P6.4

Chip select 0 output

Chip select 1 output

Chip select 2 output

SSC1: Master clock
output/slave clock input

SSC1: Master­transmitter/slave-receiver
O/I

SSC1: Master­receiver/slave-transmitter
I/O

External master hold
request input

Hold acknowledge output

P8.0 to P8.7

D1 O P6.7 BREQ

E2 I/O

F3 I/O P8.1 CC17IO

F2 I/O P8.2 CC18IO

8-bit bidirectional I/O port,

G3 I/O P8.3 CC19IO

G2 I/O P8.4 CC20IO

H4 I/O P8.5 CC21IO

H3 I/O P8.6

H2

bit-wise programmable for
input or output via direction
bit. Programming an I/O pin
as input forces the
corresponding output driver
to high impedance state.
Port 8 outputs can be
configured as push-pull or
open-drain drivers. The
input threshold of Port 8 is
selectable (TTL or CMOS).

I/O

O TxD1

P8.0 CC16IO

CC22IO

RxD1

CC23IO

P8.7

Bus request output

CAPCOM2: CC16 capture
input/compare output

CAPCOM2: CC17 capture
input/compare output

CAPCOM2: CC18 capture
input/compare output

CAPCOM2: CC19 capture
input/compare output

CAPCOM2: CC20 capture
input/compare output

CAPCOM2: CC21 capture
input/compare output

CAPCOM2: CC22 capture
input/compare output

ASC1: Data input
(asynchronous) or I/O
(synchronous)

CAPCOM2: CC23 capture
input/compare output

ASC1: Clock/data output
(asynchronous/synchronous)

21/346

Ball data ST10F296E

www.BDTIC.com/ST

Table 2. Ball description (continued)

Symbol

P7.0 to P7.7

XP10.0 to

XP10.15

Ball

Type Function (including port, pin and alternate function where applicable)

no.

J4 O

J3 O P7.1 POUT1 PWM0: Channel 1 output

J2 O P7.2 POUT2 PWM0: Channel 2 output

J1 O P7.3 POUT3 PWM0: Channel 3 output

K2 I/O P7.4 CC28IO

K3 I/O P7.5 CC29IO

K4 I/O P7.6 CC30IO

L2 I/O P7.7 CC31IO

M4 I

M3 I XP10.1

M2 I XP10.2

M1 I XP10.3

N4 I XP10.4

N3 I XP10.5

N2 I XP10.6

N1 I XP10.7

P4 I XP10.8

P3 I XP10.9

P2 I XP10.10

P1 I XP10.11

R2 XP10.12

R1 XP10.13

8-bit bidirectional I/O port,
bit-wise programmable for
input or output via direction
bit. Programming an I/O pin
as input forces the
corresponding output driver
to high impedance state.
Port 7 outputs can be
configured as push-pull or
open-drain drivers. The
input threshold of Port 7 is
selectable (TTL or CMOS).

16-bit input-only port with
Schmitt-Trigger
characteristics. The pins of
XPort 10 can be the analog
input channels (up to 16) for
the ADC, where XP10.x
equals ANy (analog input
channel y, where y = x +

16). The input threshold of
XPort 10 is selectable (TTL
or CMOS).

P7.0 POUT0 PWM0: Channel 0 output

CAPCOM2: CC28 capture
input/compare output

CAPCOM2: CC29 capture
input/compare output

CAPCOM2: CC30 capture
input/compare output

CAPCOM2: CC31 capture
input/compare output

XP10.0

22/346

T1 XP10.14

U1 XP10.15

ST10F296E Ball data

www.BDTIC.com/ST

Table 2. Ball description (continued)

Symbol

P5.0 to

P5.15

Ball

Type Function (including port, pin and alternate function where applicable)

no.

T2 I

R3 I P5.1

T3 I P5.2

R4 I P5.3

T4 I P5.4

U4 I P5.5

P5 I P5.6

R5 I P5.7

T5 I P5.8

U5 I P5.9

P6 I P5.10 T6EUD

R6 I P5.11 T5EUD

T6 I P5.12 T6IN GPT2: Timer T6 count input

U6 I P5.13 T5IN GPT2: Timer T5 count input

P7 I P5.14 T4EUD

R7 I P5.15 T2EUD

16-bit input-only port with
Schmitt-Trigger
characteristics. The pins of
Port 5 can be the analog
input channels (up to 16) for
the ADC, where P5.x equals
ANx (analog input channel
x), or they are timer inputs.
The input threshold of Port 5
is selectable (TTL or
CMOS).

P5.0

GPT2: Timer T6 external
up/down control input

GPT2: Timer T5 external
up/down control input

GPT1: Timer T4 external
up/down control input

GPT1: Timer T2 external
up/down control input

P2.0 to

P2.15

T7 I/O

P8 I/O P2.1 CC1IO

R8 I/O P2.2 CC2IO

T8 I/O P2.3 CC3IO

T9 I/O P2.4 CC4IO

P9 I/O P2.5 CC5IO

R9 I/O P2.6 CC6IO

U9 I/O P2.7 CC7IO

16-bit bidirectional I/O port,
bit-wise programmable for
input or output via direction
bit. Programming an I/O pin
as input forces the
corresponding output driver
to high impedance state.
Port 2 outputs can be
configured as push-pull or
open-drain drivers. The
input threshold of Port 2 is
selectable (TTL or CMOS).

P2.0 CC0IO

23/346

CAPCOM1: CC0 capture
input/compare output

CAPCOM1: CC1 capture
input/compare output

CAPCOM1: CC2 capture
input/compare output

CAPCOM1: CC3 capture
input/compare output

CAPCOM1: CC4 capture
input/compare output

CAPCOM1: CC5 capture
input/compare output

CAPCOM1: CC6 capture
input/compare output

CAPCOM1: CC7 capture
input/compare output

Ball data ST10F296E

www.BDTIC.com/ST

Table 2. Ball description (continued)

Symbol

P2.0 to

P2.15 cont’d

Ball

Type Function (including port, pin and alternate function where applicable)

no.

CAPCOM1: CC8 capture
input/compare output

Fast external interrupt 0
input

CAPCOM1: CC9 capture
input/compare output

Fast external interrupt 1
input

CAPCOM1: CC10 capture
input/compare output

Fast external interrupt 2
input

CAPCOM1: CC11 capture
input/compare output

Fast external interrupt 3
input

CAPCOM1: CC12 capture
input/compare output

Fast external interrupt 4
input

CAPCOM1: CC13 capture
input/compare output

Fast external interrupt 5
input

CAPCOM1: CC14 capture
input/compare output

Fast external interrupt 6
input

CAPCOM1: CC15 capture
input/compare output

Fast external interrupt 7
input

T10

R10

P10

T11

R11

U12

P11

T12

I/O

P2.8

I EX0IN

I/O

P2.9

I EX1IN

I/O

P2.10

I EX2IN

16-bit bidirectional I/O port,

I/O

bit-wise programmable for
input or output via direction

I

bit. Programming an I/O pin
as input forces the
corresponding output driver

I/O

to high impedance state.
Port 2 outputs can be
configured as push-pull or

I EX4IN

open-drain drivers. The
input threshold of Port 2 is

I/O

selectable (TTL or CMOS).

I EX5IN

I/O

I EX6IN

I/O

I EX7IN

P2.11

P2.12

P2.13

P2.14

P2.15

CC8IO

CC9IO

CC10IO

CC11IO

EX3IN

CC12IO

CC13IO

CC14IO

CC15IO

24/346

IT7IN

CAPCOM2: Timer T7 count
input

ST10F296E Ball data

www.BDTIC.com/ST

Table 2. Ball description (continued)

Symbol

P3.0 to

P3.13, P3.15

Ball

Type Function (including port, pin and alternate function where applicable)

no.

R12 I

T13 O P3.1 T6OUT

P12 I P3.2 CAPIN

R13 O P3.3 T3OUT

T14 I P3.4 T3EUD

P13 I P3.5 T4IN

15-bit (P3.14 is missing)

R14 I P3.6 T3IN

P14 I P3.7 T2IN

R15 I/O P3.8 MRST0

R16 I/O P3.9 MTSR0

N14 I/O P3.10 TxD0

P15 O P3.11 RxD0

P16 O P3.12

bidirectional I/O port, bit­wise programmable for input
or output via direction bit.
Programming an I/O pin as
input forces the
corresponding output driver
to high impedance state.
Port 3 outputs can be
configured as push-pull or
open-drain drivers. The
input threshold of Port 3 is
selectable (TTL or CMOS).

P3.0 T0IN

BHE

WRH

CAPCOM1: Timer T0 count
input

GPT2: Timer T6 toggle latch
output

GPT2: Register caprel
capture input

GPT1: Timer T3 toggle latch
output

GPT1: Timer T3 external
up/down control input

GPT1: Timer T4 input for
count/gate/reload/capture

GPT1: Timer T3 count/gate
input

GPT1: Timer T2 input for
count/gate/reload/capture

SSC0: Master receive/slave
transmit I/O

SSC0: Master
transmit/slave receive O/I

ASC0: Clock/data output
(asynchronous/synchronous)

ASC0: Data input
(asynchronous) or I/O
(synchronous)

External memory high byte
enable signal

External memory high byte
write strobe

M14 I/O P3.13 SCLK0

T17 O P3.15 CLKOUT

25/346

SSC0: Master clock
output/slave clock input

Clock output
(programmable divider on
CPU clock)

Ball data ST10F296E

www.BDTIC.com/ST

Table 2. Ball description (continued)

Symbol

P4.0 to P4.7

RD J14 O

Ball

Type Function (including port, pin and alternate function where applicable)

no.

N16 O

P4.0 A16

Least significant segment
address line

M15 O P4.1 A17 Segment address line

L14 O P4.2 A18 Segment address line

M16 O P4.3 A19 Segment address line

L15

L16

K14

K15

8-bit bidirectional I/O port. It
is bit-wise programmable for
input or output via direction

O

bit. Programming an I/O pin

I CAN2_RxD CAN2: Receive data input

as input forces the
corresponding output driver

I/O

to high impedance state.

O

The input threshold is
selectable (TTL or CMOS).

I CAN1_RxD CAN1: Receive data input

Port 4.4, 4.5, 4.6 and 4.7

I CAN2_RxD CAN2: Receive Data Input

outputs can be configured
as push-pull or open-drain

O

drivers. In case of an

O

external bus configuration,
Port 4 can be used to output

O

the segment address lines.

P4.4

P4.5

P4.6

O

O CAN2_TxD CAN2: Transmit data output

P4.7

I/O SDA I

External memory read strobe: RD

is activated for every external instruction or data

A20 Segment address line

SCL I2C interface: Serial clock

A21 Segment address line

A22 Segment address line

CAN1_TxD CAN1: Transmit data output

CAN2_TxD CAN2: Transmit data output

A23

Most significant segment
address line

2

C interface: Serial data

read access.

External memory write strobe: In WR

WR

and

WRL

J15 O

write access. In WRL mode this pin is activated for low byte data write access on a 16­bit bus, and, for every data write access on an 8-bit bus. See WRCFG in register
SYSCON for mode selection.

Ready input: The active level is programmable. When the Ready function is enabled,

READY and

READY

J16 I

the selected inactive level at this pin during an external memory access forces the
insertion of memory cycle time waitstates until the pin returns to the selected active
level.

ALE J17 O

Address latch enable output: Can be used for latching the address into external
memory or an address latch in the multiplexed bus modes.

External access enable pin: A low level applied to this pin during and after reset forces
the ST10F296E to start the program from the external memory space. A high level
forces ST10F296E to start in the internal memory space. This pin is also used (when
standby mode is entered: ST10F296E under reset and main V

EA

V

and

STBY

H17 I

a reference voltage for the low-power embedded voltage regulator which generates
the internal 1.8 V supply to retain data inside the standby portion of the XRAM (16
Kbyte).

It can range from 4.5 to 5.5 V (6 V for a reduced amount of time during the device life).
In running mode, this pin can be tied low during reset without affecting XRAM
activities, since the presence of a stable V
module.

26/346

mode this pin is activated for every external data

turned off) to provide

DD

guarantees the proper biasing of this

DD

ST10F296E Ball data

www.BDTIC.com/ST

Table 2. Ball description (continued)

Symbol

POL.0 to

POL.7 and

POH.0 to

POH.7

Ball

Type Function (including port, pin and alternate function where applicable)

no.

H16 I/O Two 8-bit bidirectional I/O

H15 I/O P0L.1

H14 I/O P0L.2

G16 I/O P0L.3

G15 I/O P0L.4

G14 I/O P0L.5

F16 I/O P0L.6

E17 I/O P0L.7

F15 I/O P0H.0

E16 I/O P0H.1

F14 I/O P0H.2

D17 I/O P0H.3

E15 I/O P0H.4

D16 I/O P0H.5

C17 I/O P0H.6

E14 I/O P0H.7

ports P0L and P0H, bit-wise
programmable for input or
output via direction bit.
Programming an I/O pin as
input forces the
corresponding output driver
to high impedance state.
The input threshold of Port 0
is selectable (TTL or
CMOS).

In case of an external bus
configuration, Port 0 serves
as the address (A) and as
the address/data (AD) bus
in multiplexed bus modes
and as the data (D) bus in
demultiplexed bus modes.

Demultiplexed bus modes

P0L.0-P0L.7: D0-D7 (8-bit),
D0-D7 (16-bit).
P0H.0-P0H.7: I/O (8-bit),
D8-D15 (16-bit).

Multiplexed bus modes

P0L.0-P0L.7: AD0-AD7 (8­bit), AD0-AD7 (16-bit).
P0H.0-P0H.7: A8-A15 (8­bit), AD8-AD15 (16-bit).

P0L.0

27/346

Ball data ST10F296E

www.BDTIC.com/ST

Table 2. Ball description (continued)

Symbol

P1L.0 to

P1L.7 and

P1H.0 to

P1H.7

Ball

Type Function (including port, pin and alternate function where applicable)

no.

C11 I/O

B11 I/O P1L.1

D10 I/O P1L.2

C10 I/O P1L.3

B10 I/O P1L.4

A10 I/O P1L.5

D9 I/O P1L.6

C9 I/O P1L.7

C8 I/O P1H.0

D8 I/O P1H.1

A7 I/O P1H.2

B7 I/O P1H.3

C7 I P1H.4 CC24I

D7 I P1H.5 CC25I

C5 I P1H.6 CC26I

C6 I P1H.7 CC27I

Port 1 output pins: Two 8-bit
bidirectional I/O ports P1L
and P1H, bit-wise
programmable for input or
output via direction bit.
Programming an I/O pin as
input forces the
corresponding output driver
to high impedance state.
Port 1 is used as the 16-bit
address bus (A) in
demultiplexed bus modes: if
at least BUSCONx is
configured so that the
demultiplexed mode is
selected, the pis of Port 1
are not available for general
purpose I/O function. The
input threshold of Port 1 is
selectable (TTL or CMOS).

P1L.0

CAPCOM2: CC24 capture
input

CAPCOM2: CC25 capture
input

CAPCOM2: CC26 capture
input

CAPCOM2: CC27 capture
input

28/346

ST10F296E Ball data

www.BDTIC.com/ST

Table 2. Ball description (continued)

Symbol

XPORT9.0

to

XPORT9.15

XTAL1 A5 I XTAL1: Input to the oscillator amplifier and/or external clock input.

Ball

Type Function (including port, pin and alternate function where applicable)

no.

D15 I/O

C16 I/O XPORT9.1

D14 I/O XPORT9.2

C15 I/O XPORT9.3

B16 I/O XPORT9.4

D13 I/O XPORT9.5

C14 I/O XPORT9.6

B15 I/O XPORT9.7

A15 I/O XPORT9.8

B14 I/O XPORT9.9

C13 I/O XPORT9.10

D12 I/O XPORT9.11

B13 I/O XPORT9.12

C12 I/O XPORT9.13

D11 I/O XPORT9.14

B12 I/O XPORT9.15

16-bit bidirectional I/O port.
It is bit-wise programmable
for input or output via
direction bits. For a pin
configured as input, the
output driver is put into high­impedance state. XPort 9
outputs can be configured
as push-pull or open-drain
drivers.The input threshold
of XPort 9 is selectable (TTL
or CMOS).

XPORT9.0

XTAL2: Output of the oscillator amplifier circuit. To clock the device from an external

XTAL2 A6 O

RSTIN

RSTOUT

NMI

XPOUT.0 D4 O XPWM: Channel 0 output

XPOUT.1 C3 O XPWM: Channel 1 output

XPOUT.2 B2 O XPWM: Channel 2 output

XPOUT.3 C2 O XPWM: Channel 3 output

XADCINJ L3 O Output trigger for ADC channel injection

A3 I

B4 O

C4 I

source, drive XTAL1 while leaving XTAL2 unconnected. Minimum and maximum
high/low and rise/fall times specified in the AC characteristics must be observed

Reset input with CMOS Schmitt-Trigger characteristics: A low level at this pin for a
specified duration while the oscillator is running resets ST10F296E. An internal pull-up
resistor permits power-on reset using only a capacitor connected to VSS. In
bidirectional reset mode (enabled by setting bit BDRSTEN in SYSCON register), the

line is pulled low for the duration of the internal reset sequence.

RSTIN

Internal reset indication output: This pin is driven to a low level during hardware,
software or watchdog timer reset.
initialization) instruction is executed.

Non maskable interrupt input: A high to low transition at this pin causes the CPU to
vector to the NMI trap routine. If bit PWDCFG = 0 in the SYSCON register, when the
PWRDN (power-down) instruction is executed, the NMI
force the ST10F296E to go into power-down mode. If NMI is high and PWDCFG = 0,
when PWRDN is executed, the part will continue to run in normal mode.
If not being used, pin NMI

should be pulled high externally.

RSTOUT

remains low until the EINIT (end of

pin must be low in order to

29/346

Ball data ST10F296E

www.BDTIC.com/ST

Table 2. Ball description (continued)

Symbol

V

AREF

V

AGND

RPD M17 I/O

V

18

V

DD

Ball

Type Function (including port, pin and alternate function where applicable)

no.

U2 - ADC reference voltage and analog supply

U3 - ADC reference and analog ground

G1,

U11

A2

A9
A12
A14

E1

K1

U8
U15
P17

L17

G17

O

Timing pin for the return from power-down circuit and synchronous/
asynchronous reset selection.

1.8 V decoupling pin: A decoupling capacitor (typical value of 10 nF, max 100 nF) must
be connected between this pin and nearest VSS pin.

Digital supply voltage: 5 V during normal operation, idle and power-down modes. It

­can be turned off when standby RAM mode is selected.

30/346