ST ST10F276Z5 User Manual

832 Kbyte Flash memory and 68 Kbyte RAM

Features

■ Highly performance 16-bit CPU with DSP

functions – 31.25 ns instruction cycle time at 64 MHz

max CPU clock

– Multiply/accumulate unit (MAC) 16 x 16-bit

multiplication, 40-bit accumulator – Enhanced boolean bit manipulations – Single-cycle context switching support

■ On-chip memories

– 512 Kbyte Flash memory (32-bit fetch) – 320 Kbyte extension Flash memory (16-bit

fetch) – Single voltage Flash memories with

erase/program controller and 100 K

erasing/programming cycles. – Up to 16 Mbyte linear address space for

code and data (5 Mbytes with CAN or I – 2 Kbyte internal RAM (IRAM) – 66 Kbyte extension RAM (XRAM)

■ External bus

– Programmable external bus configuration &

characteristics for different address ranges – Five programmable chip-select signals – Hold-acknowledge bus arbitration support

■ Interrupt

– 8-channel peripheral event controller for

single cycle interrupt driven data transfer – 16-priority-level interrupt system with 56

sources, sampling rate down to 15.6ns

■ Timers

– Two multi-functional general purpose timer

units with 5 timers

■ Two 16-channel capture / compare units

Table 1. Device summary

ST10F276Z5

16-bit MCU with MAC unit,

7G_3D

PQFP144 28 x 28 x 3.4mm LQFP144 20 x 20 x 1.4mm

■ 4-channel PWM unit + 4-channel XPWM

■ A/D converter

– 24-channel 10-bit – 3 µs minimum conversion time

■ Serial channels

– Two synchronous/asynchronous serial

channels

– Two high-speed synchronous channels

–One I

■ 2 CAN 2.0B interfaces operating on 1 or 2 CAN

busses (64 or 2x32 message, C-CAN version)

■ Fail-safe protection

– Programmable watchdog timer – Oscillator watchdog

■ On-chip bootstrap loader

■ Clock generation

– On-chip PLL with 4 to 12 MHz oscillator – Direct or prescaled clock input

■ Real-time clock and 32 kHz on-chip oscillator

■ Up to 111 general purpose I/O lines

– Individually programmable as input, output

– Programmable threshold (hysteresis)

■ Idle, Power-down and Standby modes

■ Single voltage supply: 5 V ±10% (embedded

regulator for 1.8 V core supply)

C standard interface

or special function

Order code Package

ST10F276Z5Q3 PQFP144 64 MHz 512 Kbytes

ST10F276Z5T3 LQFP144 40 MHz 512 Kbytes 68KB -40/+125

December 2007 Rev 2 1/239

Max CPU

frequency

Iflash Xflash RAM

68KB -40/+125

320 Kbytes

Temperature range

(°C)

www.st.com

Contents ST10F276Z5

Contents

1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2 Pin data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4 Internal Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.2 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.2.1 Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.2.2 Modules structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

4.2.3 Low power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

4.3 Write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

4.3.1 Power supply drop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

4.4 Registers description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

4.4.1 Flash control register 0 low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

4.4.2 Flash control register 0 high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

4.4.3 Flash control register 1 low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

4.4.4 Flash control register 1 high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

4.4.5 Flash data register 0 low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

4.4.6 Flash data register 0 high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

4.4.7 Flash data register 1 low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

4.4.8 Flash data register 1 high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

4.4.9 Flash address register low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

4.4.10 Flash address register high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

4.4.11 Flash error register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

4.4.12 XFlash interface control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

4.5 Protection strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

4.5.1 Protection registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

4.5.2 Flash non volatile write protection X register low . . . . . . . . . . . . . . . . . . 38

4.5.3 Flash non volatile write protection X register high . . . . . . . . . . . . . . . . . 39

4.5.4 Flash non volatile write protection I register low . . . . . . . . . . . . . . . . . . 39

4.5.5 Flash non volatile write protection I register high . . . . . . . . . . . . . . . . . . 39

4.5.6 Flash non volatile access protection register 0 . . . . . . . . . . . . . . . . . . . 40

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4.5.7 Flash non volatile access protection register 1 low . . . . . . . . . . . . . . . . 40

4.5.8 Flash non volatile access protection register 1 high . . . . . . . . . . . . . . . 41

4.5.9 Access protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

4.5.10 Write protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

4.5.11 Temporary unprotection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

4.6 Write operation examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

4.7 Write operation summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

5 Bootstrap loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

5.1 Selection among user-code, standard or alternate bootstrap . . . . . . . . . 47

5.2 Standard bootstrap loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

5.2.1 Entering the standard bootstrap loader . . . . . . . . . . . . . . . . . . . . . . . . . 48

5.2.2 ST10 configuration in BSL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

5.2.3 Booting steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

5.2.4 Hardware to activate BSL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

5.2.5 Memory configuration in bootstrap loader mode . . . . . . . . . . . . . . . . . . 52

5.2.6 Loading the start-up code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

5.2.7 Exiting bootstrap loader mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

5.2.8 Hardware requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

5.3 Standard bootstrap with UART (RS232 or K-Line) . . . . . . . . . . . . . . . . . . 54

5.3.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

5.3.2 Entering bootstrap via UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

5.3.3 ST10 Configuration in UART BSL (RS232 or K-Line) . . . . . . . . . . . . . . 56

5.3.4 Loading the start-up code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

5.3.5 Choosing the baud rate for the BSL via UART . . . . . . . . . . . . . . . . . . . 57

5.4 Standard bootstrap with CAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

5.4.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

5.4.2 Entering the CAN bootstrap loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

5.4.3 ST10 configuration in CAN BSL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

5.4.4 Loading the start-up code via CAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

5.4.5 Choosing the baud rate for the BSL via CAN . . . . . . . . . . . . . . . . . . . . 61

5.4.6 Computing the baud rate error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

5.4.7 Bootstrap via CAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

5.5 Comparing the old and the new bootstrap loader . . . . . . . . . . . . . . . . . . 65

5.5.1 Software aspects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

5.5.2 Hardware aspects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

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5.6 Alternate boot mode (ABM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

5.6.1 Activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

5.6.2 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

5.6.3 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

5.6.4 ST10 configuration in alternate boot mode . . . . . . . . . . . . . . . . . . . . . . 67

5.6.5 Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

5.6.6 Exiting alternate boot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

5.6.7 Alternate boot user software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

5.6.8 User/alternate mode signature integrity check . . . . . . . . . . . . . . . . . . . 68

5.6.9 Alternate boot user software aspects . . . . . . . . . . . . . . . . . . . . . . . . . . 68

5.6.10 EMUCON register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

5.6.11 Internal decoding of test modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

5.6.12 Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

5.7 Selective boot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

6 Central processing unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

6.1 Multiplier-accumulator unit (MAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

6.2 Instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

6.3 MAC coprocessor specific instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

7 External bus controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

8 Interrupt system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

8.1 X-Peripheral interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

8.2 Exception and error traps list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

9 Capture / compare (CAPCOM) units . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

10 General purpose timer unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

10.1 GPT1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

10.2 GPT2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

11 PWM modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

12 Parallel ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

12.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

12.2 I/Os special features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

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12.2.1 Open drain mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

12.2.2 Input threshold control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

12.3 Alternate port functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

13 A/D converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

14 Serial channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

14.1 Asynchronous / synchronous serial interfaces . . . . . . . . . . . . . . . . . . . . . 96

14.2 ASCx in asynchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

14.3 ASCx in synchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

14.4 High speed synchronous serial interfaces . . . . . . . . . . . . . . . . . . . . . . . . 98

15 I2C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

16 CAN modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

16.1 Configuration support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

16.2 CAN bus configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

17 Real-time clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

18 Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

19 System reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

19.1 Input filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

19.2 Asynchronous reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

19.3 Synchronous reset (warm reset) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

19.4 Software reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

19.5 Watchdog timer reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

19.6 Bidirectional reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

19.7 Reset circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

19.8 Reset application examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

19.9 Reset summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

20 Power reduction modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

20.1 Idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

20.2 Power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

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20.2.1 Protected Power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

20.2.2 Interruptible Power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

20.3 Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

20.3.1 Entering Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

20.3.2 Exiting Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

20.3.3 Real-time clock and Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

20.3.4 Power reduction modes summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

21 Programmable output clock divider . . . . . . . . . . . . . . . . . . . . . . . . . . 137

22 Register set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

22.1 Register description format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

22.2 General purpose registers (GPRs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

22.3 Special function registers ordered by name . . . . . . . . . . . . . . . . . . . . . 141

22.4 Special function registers ordered by address . . . . . . . . . . . . . . . . . . . . 148

22.5 X-registers sorted by name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

22.6 X-registers ordered by address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

22.7 Flash registers ordered by name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

22.8 Flash registers ordered by address . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

22.9 Identification registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

22.10 System configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

22.10.1 XPERCON and XPEREMU registers . . . . . . . . . . . . . . . . . . . . . . . . . 176

22.11 Emulation dedicated registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

23 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

23.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

23.2 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

23.3 Power considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

23.4 Parameter interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

23.5 DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

23.6 Flash characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

23.7 A/D converter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

23.7.1 Conversion timing control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188

23.7.2 A/D conversion accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189

23.7.3 Total unadjusted error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190

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23.7.4 Analog reference pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191

23.7.5 Analog input pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191

23.7.6 Example of external network sizing . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

23.8 AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

23.8.1 Test waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

23.8.2 Definition of internal timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197

23.8.3 Clock generation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198

23.8.4 Prescaler operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198

23.8.5 Direct drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198

23.8.6 Oscillator watchdog (OWD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199

23.8.7 Phase locked loop (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199

23.8.8 Voltage controlled oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200

23.8.9 PLL Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201

23.8.10 Jitter in the input clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201

23.8.11 Noise in the PLL loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201

23.8.12 PLL lock/unlock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203

23.8.13 Main oscillator specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203

23.8.14 32 kHz Oscillator specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204

23.8.15 External clock drive XTAL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205

23.8.16 Memory cycle variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206

23.8.17 External memory bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207

23.8.18 Multiplexed bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208

23.8.19 Demultiplexed bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214

23.8.20 CLKOUT and READY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220

23.8.21 External bus arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222

23.8.22 High-speed synchronous serial interface (SSC) timing modes . . . . . . 224

24 Known limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228

24.1 Functional limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228

24.1.1 Injected conversion stalling the A/D converter . . . . . . . . . . . . . . . . . . . 228

24.1.2 Concurrent transmission requests in DAR-mode (C-CAN module) . . . 231

24.1.3 Disabling the transmission requests (C-CAN module) . . . . . . . . . . . . . 231

24.1.4 Spurious BREQ 232

pulse in slave mode during external bus arbitration phase

24.1.5 Executing PWRDN instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232

24.1.6 Behavior of CAPCOM outputs in COMPARE mode 3 . . . . . . . . . . . . . 233

24.2 Electrical limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234

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Contents ST10F276Z5

25 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235

26 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238

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List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 3. Flash modules absolute mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 4. Flash modules sectorization (read operations) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 5. Flash modules sectorization (write operations or with roms1=’1’) . . . . . . . . . . . . . . . . . . . 27

Table 6. Control register interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 7. Flash control register 0 low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 8. Flash control register 0 high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 9. Flash control register 1 low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 10. Flash control register 1 high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 11. Banks (BxS) and sectors (BxFy) status bits meaning. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 12. Flash data register 0 low. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 13. Flash data register 0 high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 14. Flash data register 1 low. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 15. Flash data register 1 high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 16. Flash address register low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 17. Flash address register high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 18. Flash error register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 19. XFlash interface control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 20. Flash non volatile write protection X register low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 21. Flash non volatile write protection X register high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 22. Flash non volatile write protection I register low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 23. Flash non volatile write protection I register high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 24. Flash non volatile access protection register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 25. Flash non volatile access protection register 1 low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 26. Flash non volatile access protection register 1 high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Table 27. Summary of access protection level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Table 28. Flash write operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 29. ST10F276Z5 boot mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Table 30. ST10 configuration in BSL mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 31. ST10 configuration in UART BSL mode (RS232 or K-line). . . . . . . . . . . . . . . . . . . . . . . . . 56

Table 32. ST10 configuration in CAN BSL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Table 33. BRP and PT0 values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Table 34. Software topics summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Table 35. Hardware topics summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Table 36. ST10 configuration in alternate boot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Table 37. ABM bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Table 38. Selective boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Table 39. Standard instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Table 40. MAC instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Table 41. Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Table 42. X-Interrupt detailed mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Table 43. Trap priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Table 44. Compare modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Table 45. CAPCOM timer input frequencies, resolutions and periods at 40 MHz . . . . . . . . . . . . . . . 84

Table 46. CAPCOM timer input frequencies, resolutions and periods at 64 MHz . . . . . . . . . . . . . . . 84

Table 47. GPT1 timer input frequencies, resolutions and periods at 40 MHz. . . . . . . . . . . . . . . . . . . 85

Table 48. GPT1 timer input frequencies, resolutions and periods at 64 MHz. . . . . . . . . . . . . . . . . . . 86

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Table 49. GPT2 timer input frequencies, resolutions and periods at 40 MHz. . . . . . . . . . . . . . . . . . . 87

Table 50. GPT2 timer input frequencies, resolutions and periods at 64 MHz. . . . . . . . . . . . . . . . . . . 87

Table 51. PWM unit frequencies and resolutions at 40 MHz CPU clock . . . . . . . . . . . . . . . . . . . . . . 89

Table 52. PWM unit frequencies and resolutions at 64 MHz CPU clock . . . . . . . . . . . . . . . . . . . . . . 90

Table 53. ASC asynchronous baud rates by reload value and deviation errors (fCPU = 40 MHz) . . 96 Table 54. ASC asynchronous baud rates by reload value and deviation errors (fCPU = 64 MHz) . . 97 Table 55. ASC synchronous baud rates by reload value and deviation errors (fCPU = 40 MHz) . . . 97 Table 56. ASC synchronous baud rates by reload value and deviation errors (fCPU = 64 MHz) . . . 98

Table 57. Synchronous baud rate and reload values (fCPU = 40 MHz). . . . . . . . . . . . . . . . . . . . . . . 99

Table 58. Synchronous baud rate and reload values (fCPU = 64 MHz). . . . . . . . . . . . . . . . . . . . . . . 99

Table 59. WDTREL reload value (fCPU = 40 MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Table 60. WDTREL reload value (fCPU = 64 MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Table 61. Reset event definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Table 62. Reset event. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

Table 63. PORT0 latched configuration for the different reset events . . . . . . . . . . . . . . . . . . . . . . . 130

Table 64. Power reduction modes summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

Table 65. Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

Table 66. General purpose registers (GPRs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

Table 67. General purpose registers (GPRs) bytewise addressing. . . . . . . . . . . . . . . . . . . . . . . . . 139

Table 68. Special function registers ordered by address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

Table 69. Special function registers ordered by address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

Table 70. X-Registers ordered by name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

Table 71. X-registers ordered by address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

Table 72. Flash registers ordered by name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

Table 73. FLASH registers ordered by address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

Table 74. MANUF description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

Table 75. IDCHIP description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

Table 76. IDMEM description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

Table 77. IDPROG description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

Table 78. Identification register settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

Table 79. SYSCON description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

Table 80. BUSCON4 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

Table 81. RPOH description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

Table 82. EXIxES bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

Table 83. EXISEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

Table 84. EXIxSS and port 2 pin configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

Table 85. SFR area description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

Table 86. ESFR description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

Table 87. Segment 8 address range mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

Table 88. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

Table 89. Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

Table 90. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

Table 91. Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

Table 92. DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

Table 93. Flash characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

Table 94. Data retention characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186

Table 96. A/D Converter programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188

Table 97. On-chip clock generator selections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198

Table 98. Internal PLL divider mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200

Table 99. PLL lock/unlock timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203

Table 100. Main oscillator specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203

Table 101. Negative resistance (absolute min. value @125oC / VDD = 4.5 V) . . . . . . . . . . . . . . . . . 204

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Table 102. 32 kHz Oscillator specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204

Table 103. Minimum values of negative resistance (module). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205

Table 104. External clock drive timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206

Table 105. Memory cycle variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206

Table 106. Multiplexed bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208

Table 107. Demultiplexed bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214

Table 108. CLKOUT and READY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220

Table 109. External bus arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222

Table 110. Master mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224

Table 111. Slave mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226

Table 112. PQFP144 - 144-pin Plastic Quad Flatpack 28 x 28 mm, 0.65 mm pitch,

package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236

Table 113. LQFP144 - 144 pin low profile quad flat package 20x20mm, 0.5 mm pitch,

package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237

Table 114. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238

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List of figures

Figure 1. Logic symbol. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 2. Pin configuration (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 3. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 4. Flash modules structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 5. ST10F276Z5 new standard bootstrap loader program flow . . . . . . . . . . . . . . . . . . . . . . . . 50

Figure 6. Booting steps for ST10F276Z5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Figure 7. Hardware provisions to activate the BSL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Figure 8. Memory configuration after reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Figure 9. UART bootstrap loader sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Figure 10. Baud rate deviation between host and ST10F276Z5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Figure 11. CAN bootstrap loader sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Figure 12. Bit rate measurement over a predefined zero-frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Figure 13. Reset boot sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Figure 14. CPU Block Diagram (MAC Unit not included). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Figure 15. MAC unit architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Figure 16. X-Interrupt basic structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Figure 17. Block diagram of GPT1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Figure 18. Block diagram of GPT2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Figure 19. Block diagram of PWM module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Figure 20. Connection to single CAN bus via separate CAN transceivers . . . . . . . . . . . . . . . . . . . . 102

Figure 21. Connection to single CAN bus via common CAN transceivers. . . . . . . . . . . . . . . . . . . . . 102

Figure 22. Connection to two different CAN buses (e.g. for gateway application). . . . . . . . . . . . . . . 103

Figure 23. Connection to one CAN bus with internal Parallel mode enabled . . . . . . . . . . . . . . . . . . 103

Figure 24. Asynchronous power-on RESET (EA = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Figure 25. Asynchronous power-on RESET (EA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

Figure 26. Asynchronous hardware RESET (EA = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Figure 27. Asynchronous hardware RESET (EA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

Figure 28. Synchronous short / long hardware RESET (EA = 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Figure 29. Synchronous short / long hardware RESET (EA = 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Figure 30. Synchronous long hardware RESET (EA = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Figure 31. Synchronous long hardware RESET (EA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

Figure 32. SW / WDT unidirectional RESET (EA = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

Figure 33. SW / WDT unidirectional RESET (EA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

Figure 34. SW / WDT bidirectional RESET (EA=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Figure 35. SW / WDT bidirectional RESET (EA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

Figure 36. SW / WDT bidirectional RESET (EA=0) followed by a HW RESET . . . . . . . . . . . . . . . . . 124

Figure 37. Minimum external reset circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

Figure 38. System reset circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

Figure 39. Internal (simplified) reset circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

Figure 40. Example of software or watchdog bidirectional reset (EA = 1) . . . . . . . . . . . . . . . . . . . . . 127

Figure 41. Example of software or watchdog bidirectional reset (EA = 0) . . . . . . . . . . . . . . . . . . . . . 128

Figure 42. PORT0 bits latched into the different registers after reset . . . . . . . . . . . . . . . . . . . . . . . . 131

Figure 43. External RC circuitry on RPD pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

Figure 44. Port2 test mode structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

Figure 45. Supply current versus the operating frequency (RUN and IDLE modes) . . . . . . . . . . . . . 184

Figure 46. A/D conversion characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190

Figure 47. A/D converter input pins scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191

Figure 48. Charge sharing timing diagram during sampling phase . . . . . . . . . . . . . . . . . . . . . . . . . . 192

12/239

ST10F276Z5 List of figures

Figure 49. Anti-aliasing filter and conversion rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194

Figure 50. Input/output waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

Figure 51. Float waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

Figure 52. Generation mechanisms for the CPU clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197

Figure 53. ST10F276Z5 PLL jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202

Figure 54. Crystal oscillator and resonator connection diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204

Figure 55. 32 kHz crystal oscillator connection diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205

Figure 56. External clock drive XTAL1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206

Figure 57. Multiplexed bus with/without R/W delay and normal ALE. . . . . . . . . . . . . . . . . . . . . . . . . 210

Figure 58. Multiplexed bus with/without R/W delay and extended ALE . . . . . . . . . . . . . . . . . . . . . . . 211

Figure 59. Multiplexed bus, with/without R/W delay, normal ALE, R/W CS. . . . . . . . . . . . . . . . . . . . 212

Figure 60. Multiplexed bus, with/without R/ W delay, extended ALE, R/W CS . . . . . . . . . . . . . . . . . 213

Figure 61. Demultiplexed bus, with/without read/write delay and normal ALE . . . . . . . . . . . . . . . . . 216

Figure 62. Demultiplexed bus with/without R/W delay and extended ALE . . . . . . . . . . . . . . . . . . . . 217

Figure 63. Demultiplexed bus with ALE and R/W CS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218

Figure 64. Demultiplexed bus, no R/W delay, extended ALE, R/W CS . . . . . . . . . . . . . . . . . . . . . . . 219

Figure 65. CLKOUT and READY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221

Figure 66. External bus arbitration (releasing the bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222

Figure 67. External bus arbitration (regaining the bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223

Figure 68. SSC master timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225

Figure 69. SSC slave timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227

Figure 70. ADC injection theoretical operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230

Figure 71. ADC injection actual operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230

Figure 72. Connecting an ST10 in slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232

Figure 73. PQFP144 - 144-pin plastic Quad Flatpack 28 x 28 mm, 0.65 mm pitch,

package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236

Figure 74. LQFP144 - 144 pin low profile quad flat package 20x20 mm, 0.5 mm pitch,

package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237

13/239

Description ST10F276Z5

1 Description

The ST10F276Z5 is a derivative of the STMicroelectronics ST10 family of 16-bit single-chip CMOS microcontrollers. It combines high CPU performance (up to 32 million instructions per second) with high peripheral functionality and enhanced I/O-capabilities. It also provides on-chip high-speed single voltage Flash memory, on-chip high-speed RAM, and clock generation via PLL.

The ST10F276Z5 is processed in 0.18 µm CMOS technology. The MCU core and the logic is supplied with a 5 to 1.8 V on-chip voltage regulator. The part is supplied with a single 5 V supply and I/Os work at 5 V.

The device is upward compatible with the ST10F269 device, with the following set of differences:

● Flash control interface is now based on STMicroelectronics third generation of stand-

alone Flash memories (M29F400 series), with an embedded Program/Erase Controller. This completely frees up the CPU during programming or erasing the Flash.

● Only one supply pin (ex DC1 in ST10F269, renamed into V

is used for decoupling the internally generated 1.8 V core logic supply. Do not connect this pin to 5.0 V external supply. Instead, this pin should be connected to a decoupling capacitor (ceramic type, typical value 10 nF, maximum value 100 nF).

● The AC and DC parameters are modified due to a difference in the maximum CPU

frequency.

● A new V

● EA pin assumes a new alternate functionality: it is also used to provide a dedicated

power supply (see V the main Power Supply of the device (V V

) is turned off for low power mode, allowing data retention. V

pin replaces DC2 of ST10F269.

) to maintain biased a portion of the XRAM (16Kbytes) when

STBY

and consequently the internally generated

the range 4.5-5.5 V, and a dedicated embedded low power voltage regulator is in charge to provide the 1.8 V for the RAM, the low-voltage section of the 32 kHz oscillator and the real-time clock module when not disabled. It is allowed to exceed the upper limit up to 6 V for a very short period of time during the global life of the device, and exceed the lower limit down to 4 V when RTC and 32 kHz on-chip oscillator are not used.

● A second SSC mapped on the XBUS is added (SSC of ST10F269 becomes here

SSC0, while the new one is referred as XSSC or simply SSC1). Note that some restrictions and functional differences due to the XBUS peculiarities are present between the classic SSC, and the new XSSC.

● A second ASC mapped on the XBUS is added (ASC0 of ST10F269 remains ASC0,

while the new one is referred as XASC or simply as ASC1). Note that some restrictions and functional differences due to the XBUS peculiarities are present between the classic ASC, and the new XASC.

● A second PWM mapped on the XBUS is added (PWM of ST10F269 becomes here

PWM0, while the new one is referred as XPWM or simply as PWM1). Note that some

) on the QFP144 package

voltage shall be in

STBY

14/239

ST10F276Z5 Description

restrictions and functional differences due to the XBUS peculiarities are present between the classic PWM, and the new XPWM.

● An I

● CLKOUT function can output either the CPU clock (like in ST10F269) or a software

C interface on the XBUS is added (see X-I2C or simply I2C interface).

programmable prescaled value of the CPU clock.

● Embedded memory size has been significantly increased (both Flash and RAM).

● PLL multiplication factors have been adapted to new frequency range.

● A/D Converter is not fully compatible versus ST10F269 (timing and programming

model). Formula for the conversion time is still valid, while the sampling phase programming model is different. Besides, additional 8 channels are available on P1L pins as alternate function: the accuracy reachable with these extra channels is reduced with respect to the standard Port5 channels.

● External Memory bus potential limitations on maximum speed and maximum

capacitance load could be introduced (under evaluation): ST10F276Z5 will probably not be able to address an external memory at 64 MHz with 0 wait states (under evaluation).

● XPERCON register bit mapping modified according to new peripherals implementation

(not fully compatible with ST10F269).

● Bond-out chip for emulation (ST10R201) cannot achieve more than 50 MHz at room

temperature (so no real-time emulation possible at maximum speed).

● Input section characteristics are different. The threshold programmability is extended to

all port pins (additional XPICON register); it is possible to select standard TTL (with up to 500 mV of hysteresis) and standard CMOS (with up to 800 mV of hysteresis).

● Output transition is not programmable.

● CAN module is enhanced: the ST10F276Z5 implements two C-CAN modules, so the

programming model is slightly different. Besides, the possibility to map in parallel the two CAN modules is added (on P4.5/P4.6).

● On-chip main oscillator input frequency range has been reshaped, reducing it from 1-

25 MHz down to 4-12 MHz. This is a high performance oscillator amplifier, providing a very high negative resistance and wide oscillation amplitude: when this on-chip amplifier is used as reference for real-time clock module, the power-down consumption is dominated by the consumption of the oscillator amplifier itself. A metal option is added to offer a low power oscillator amplifier working in the range of 4-8 MHz: this will allow a power consumption reduction when real-time clock is running in Power-down mode using as reference the on-chip main oscillator clock.

● A second on-chip oscillator amplifier circuit (32 kHz) is implemented for low power

modes: it can be used to provide the reference to the real-time clock counter (either in Power-down or Standby mode). Pin XTAL3 and XTAL4 replace a couple of V

DD/VSS

pins of ST10F269.

● Possibility to re-program internal XBUS chip select window characteristics (XRAM2 and

XFLASH address window) is added.

15/239

Description ST10F276Z5

Figure 1. Logic symbol

DDVSS

XTAL1 XTAL2 XTAL3 XTAL4

RSTIN

RSTOUT

AREF

AGND

NMI

EA / V

STBY

READY

ALE

WR / WRL

Port 5

16-bit

ST10F276Z5

Port 0 16-bit

Port 1 16-bit

Port 2 16-bit

Port 3 15-bit

Port 4 8-bit

Port 6 8-bit

Port 7 8-bit

Port 8 8-bit

RPD

16/239

ST10F276Z5 Pin data

2 Pin data

Figure 2. Pin configuration (top view)

(*)

RSTOUT

RSTIN

VSS

XTAL1

XTAL2

VDD

P1H.7 / A15 / CC27I

P1H.6 / A14 / CC26I

P1H.5 / A13 / CC25I

P1H.4 / A12 / CC24I

P1H.3 / A11

P1H.2 / A10

P1H.1 / A9

P1H.0 / A8

VSS

VDD

P1L.7 / A7 / AN23

P1L.6 / A6 / AN22

P1L.5 / A5 / AN21

P1L.4 / A4 / AN20

P1L.3 / A3 / AN19

P1L.2 / A2 / AN18

P1L.1 / A1 / AN17

P1L.0 / A0 / AN16

P0H.7 / AD15

P0H.6 / AD14

P0H.5 / AD13

P0H.4 / AD12

P0H.3 / AD11

P0H.2 / AD10

P0H.1 / AD9

VSS

P6.0 / CS0 P6.1 / CS1 P6.2 / CS2 P6.3 / CS3 P6.4 / CS4

P6.5 / HOLD / SCLK1

/ MTSR1

P6.6 / HLDA

P6.7 / BREQ P8.0 / XPOUT0 / CC16IO P8.1 / XPOUT1 / CC17IO P8.2 / XPOUT2 / CC18IO P8.3 / XPOUT3 / CC19IO

/ MRST1

P8.4 / CC20IO P8.5 / CC21IO

P8.6 / RxD1 / CC22IO

P8.7 / TxD1 / CC23IO

VDD

VSS P7.0 / POUT0 P7.1 / POUT1 P7.2 / POUT2 P7.3 / POUT3

P7.4 / CC28IO P7.5 / CC29IO P7.6 / CC30IO P7.7 / CC31IO

P5.0 / AN0 P5.1 / AN1 P5.2 / AN2 P5.3 / AN3 P5.4 / AN4 P5.5 / AN5 P5.6 / AN6 P5.7 / AN7 P5.8 / AN8 P5.9 / AN9

XTAL4

XTAL3

NMI

144

143

142

141

140

139

138

137

136

135

134

133

132

131

130

129

128

127

126

125

124

123

122

121

120

119

118

117

116

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

3738394041424344454647484950515253545556575859606162636465666768697071

ST10F276Z5

115

114

113

112

VDD

111

110

109 108

P0H.0 / AD8

107

P0L.7 / AD7

106

P0L.6 / AD6

105

P0L.5 / AD5

104

P0L.4 / AD4

103

P0L.3 / AD3

102

P0L.2 / AD2

101

P0L.1 / AD1

100

P0L.0 / AD0

/ VSTBY

ALE

READY

WR/WRL

VSS

VDD

P4.7 / A23 / CAN2_TxD / SDA

P4.6 / A22 / CAN1_TxD / CAN2_TxD

P4.5 / A21 / CAN1_RxD / CAN2_RxD

P4.4 / A20 / CAN2_RxD / SCL

P4.3 / A19

P4.2 / A18

P4.1 / A17

P4.0 / A16

RPD

VSS

VDD

P3.15 / CLKOUT

P3.13 / SCLK0

P3.12 / BHE

P3.11 / RxD0

P3.10 / TxD0

P3.9 / MTSR0

P3.8 / MRST0

P3.7 / T2IN

P3.6 / T3IN

/ WRH

VSS

P5.12 / AN12 / T6IN

P5.13 / AN13 / T5IN

P5.14 / AN14 / T4EUD

VDD

P2.0 / CC0IO

P2.1 / CC1IO

P2.2 / CC2IO

P2.3 / CC3IO

P5.15 / AN15 / T2EUD

VAREF

VAGND

P5.10 / AN10 / T6EUD

P5.11 / AN11 / T5EUD

V18

VSS

P2.11 / CC11IO / EX3IN

P2.12 / CC12IO / EX4IN

P2.13 / CC13IO / EX5IN

P3.0 / T0IN

P2.14 / CC14IO / EX6IN

P2.15 / CC15IO / EX7IN / T7IN

P2.4 / CC4IO

P2.5 / CC5IO

P2.6 / CC6IO

P2.7 / CC7IO

P2.8 / CC8IO / EX0IN

P2.9 / CC9IO / EX1IN

P2.10 / CC10IO / EX2IN

VSS

VDD

P3.5 / T4IN

P3.2 / CAPIN

P3.1 / T6OUT

P3.3 / T3OUT

P3.4 / T3EUD

17/239

Pin data ST10F276Z5

Table 2. Pin description

Symbol Pin Type Function

8-bit bidirectional I/O port, bit-wise programmable for input or output via direction bit. Programming an I/O pin as input forces the corresponding output driver to

1 - 8 I/O

1OP6.0CS0

... ... ... ... ...

high impedance state. Port 6 outputs can be configured as push-pull or open drain drivers. The input threshold of Port 6 is selectable (TTL or CMOS). The following Port 6 pins have alternate functions:

Chip select 0 output

P6.0 - P6.7

P8.0 - P8.7

5OP6.4CS4 Chip select 4 output

9-16 I/O

... ... ... ... ...

13 I/O P8.4 CC20IO CAPCOM2: CC20 capture input / compare output

14 I/O P8.5 CC21IO CAPCOM2: CC21 capture input / compare output

IP6.5HOLD

I/O SCLK1 SSC1: master clock output / slave clock input

O P6.6 HLDA Hold acknowledge output

I/O MTSR1 SSC1: master-transmitter / slave-receiver O/I

OP6.7 BREQ Bus request output

I/O MRST1 SSC1: master-receiver / slave-transmitter I/O

8-bit bidirectional I/O port, bit-wise programmable for input or output via direction bit. Programming an I/O pin as input forces the corresponding output driver to high impedance state. Port 8 outputs can be configured as push-pull or open drain drivers. The input threshold of Port 8 is selectable (TTL or CMOS). The following Port 8 pins have alternate functions:

I/O P8.0 CC16IO CAPCOM2: CC16 capture input / compare output

O XPWM0 PWM1: channel 0 output

I/O P8.3 CC19IO CAPCOM2: CC19 capture input / compare output

O XPWM0 PWM1: channel 3 output

I/O P8.6 CC22IO CAPCOM2: CC22 capture input / compare output

I/O RxD1 ASC1: Data input (Asynchronous) or I/O (Synchronous)

I/O P8.7 CC23IO CAPCOM2: CC23 capture input / compare output

O TxD1 ASC1: Clock / Data output (Asynchronous/Synchronous)

External master hold request input

18/239

ST10F276Z5 Pin data

Table 2. Pin description (continued)

Symbol Pin Type Function

8-bit bidirectional I/O port, bit-wise programmable for input or output via direction bit. Programming an I/O pin as input forces the corresponding output driver to

P7.0 - P7.7

P5.0 - P5.9

P5.10 - P5.15

19-26 I/O

19 O P7.0 POUT0 PWM0: channel 0 output

... ... ... ... ...

22 O P7.3 POUT3 PWM0: channel 3 output

23 I/O P7.4 CC28IO CAPCOM2: CC28 capture input / compare output

... ... ... ... ...

26 I/O P7.7 CC31IO CAPCOM2: CC31 capture input / compare output

27-36 39-44

39 I P5.10 T6EUD GPT2: timer T6 external up/down control input

40 I P5.11 T5EUD GPT2: timer T5 external up/down control input

41 I P5.12 T6IN GPT2: timer T6 count input

42 I P5.13 T5IN GPT2: timer T5 count input

43 I P5.14 T4EUD GPT1: timer T4 external up/down control input

high impedance state. Port 7 outputs can be configured as push-pull or open drain drivers. The input threshold of Port 7 is selectable (TTL or CMOS). The following Port 7 pins have alternate functions:

16-bit input-only port with Schmitt-Trigger characteristics. The pins of Port 5 can be the analog input channels (up to 16) for the A/D converter, where P5.x equals

ANx (Analog input channel x), or they are timer inputs. The input threshold of

Port 5 is selectable (TTL or CMOS). The following Port 5 pins have alternate functions:

P2.0 - P2.7

P2.8 - P2.15

44 I P5.15 T2EUD GPT1: timer T2 external up/down control input

16-bit bidirectional I/O port, bit-wise programmable for input or output via

47-54 57-64

47 I/O P2.0 CC0IO CAPCOM: CC0 capture input/compare output

... ... ... ... ...

54 I/O P2.7 CC7IO CAPCOM: CC7 capture input/compare output

57 I/O P2.8 CC8IO CAPCOM: CC8 capture input/compare output

... ... ... ... ...

64 I/O P2.15 CC15IO CAPCOM: CC15 capture input/compare output

direction bit. Programming an I/O pin as input forces the corresponding output

I/O

driver to high impedance state. Port 2 outputs can be configured as push-pull or open drain drivers. The input threshold of Port 2 is selectable (TTL or CMOS). The following Port 2 pins have alternate functions:

I EX0IN Fast external interrupt 0 input

I EX7IN Fast external interrupt 7 input

I T7IN CAPCOM2: timer T7 count input

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Pin data ST10F276Z5

Table 2. Pin description (continued)

Symbol Pin Type Function

15-bit (P3.14 is missing) bidirectional I/O port, bit-wise programmable for input or 65-70, 73-80,

65 I P3.0 T0IN CAPCOM1: timer T0 count input

66 O P3.1 T6OUT GPT2: timer T6 toggle latch output

67 I P3.2 CAPIN GPT2: register CAPREL capture input

68 O P3.3 T3OUT GPT1: timer T3 toggle latch output

69 I P3.4 T3EUD GPT1: timer T3 external up/down control input

I/O

output via direction bit. Programming an I/O pin as input forces the

I/O

corresponding output driver to high impedance state. Port 3 outputs can be

I/O

configured as push-pull or open drain drivers. The input threshold of Port 3 is

selectable (TTL or CMOS). The following Port 3 pins have alternate functions:

P3.0 - P3.5

P3.6 - P3.13,

P3.15

70 I P3.5 T4IN GPT1; timer T4 input for count/gate/reload/capture

73 I P3.6 T3IN GPT1: timer T3 count/gate input

74 I P3.7 T2IN GPT1: timer T2 input for count/gate/reload / capture

75 I/O P3.8 MRST0 SSC0: master-receiver/slave-transmitter I/O

76 I/O P3.9 MTSR0 SSC0: master-transmitter/slave-receiver O/I

77 O P3.10 TxD0 ASC0: clock / data output (asynchronous/synchronous)

78 I/O P3.11 RxD0 ASC0: data input (asynchronous) or I/O (synchronous)

79 O P3.12 BHE

WRH

80 I/O P3.13 SCLK0 SSC0: master clock output / slave clock input

81 O P3.15 CLKOUT

External memory high byte enable signal

External memory high byte write strobe

System clock output (programmable divider on CPU clock)

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ST10F276Z5 Pin data

Table 2. Pin description (continued)

Symbol Pin Type Function

Port 4 is an 8-bit bidirectional I/O port. It is bit-wise programmable for input or

output via direction bit. Programming an I/O pin as input forces the

corresponding output driver to high impedance state. The input threshold is

85-92 I/O

85 O P4.0 A16 Segment address line

86 O P4.1 A17 Segment address line

87 O P4.2 A18 Segment address line

88 O P4.3 A19 Segment address line

89 O P4.4 A20 Segment address line

P4.0 –P4.7

90 O P4.5 A21 Segment address line

91 O P4.6 A22 Segment address line

selectable (TTL or CMOS). Port 4.4, 4.5, 4.6 and 4.7 outputs can be configured

as push-pull or open drain drivers.

In case of an external bus configuration, Port 4 can be used to output the

segment address lines:

I CAN2_RxD CAN2: receive data input

I/O SCL

I2C Interface: serial clock

I CAN1_RxD CAN1: receive data input

I CAN2_RxD CAN2: receive data input

92 O P4.7 A23 Most significant segment address line

RD 95 O

/WRL 96 O

READY/

READY

97 I

ALE 98 O

O CAN1_TxD CAN1: transmit data output

O CAN2_TxD CAN2: transmit data output

I/O SDA

External memory read strobe. RD

I2C Interface: serial data

is activated for every external instruction or

data read access.

External memory write strobe. In WR

external data write access. In WRL

-mode this pin is activated for every

mode this pin is activated for low byte data write accesses on a 16-bit bus, and for every data write access on an 8-bit bus. See WRCFG in the SYSCON register for mode selection.

Ready input. The active level is programmable. When the ready function is enabled, the selected inactive level at this pin, during an external memory access, will force the insertion of waitstate cycles until the pin returns to the selected active level.

Address latch enable output. In case of use of external addressing or of multiplexed mode, this signal is the latch command of the address lines.

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Pin data ST10F276Z5

Table 2. Pin description (continued)

Symbol Pin Type Function

External access enable pin. A low level applied to this pin during and after Reset forces the ST10F276Z5 to

start the program from the external memory space. A high level forces the ST10F276Z5 to start in the internal memory space. This pin is also used (when

turned

EA / V

STBY

P0L.0 -P0L.7,

P0H.0

P0H.1 - P0H.7

99 I

100-107,

108,

111-117

Standby mode is entered, that is the device under reset and main V off) to bias the 32 kHz oscillator amplifier circuit and to provide a reference voltage for the low-power embedded voltage regulator which generates the internal 1.8 V supply for the RTC module (when not disabled) and to retain data inside the Standby portion of the XRAM (16Kbyte). It can range from 4.5 to 5.5 V (6 V for a reduced amount of time during the device life, 4.0 V when RTC and 32 kHz on-chip oscillator amplifier are turned off). In running mode, this pin can be tied low during reset without affecting 32 kHz oscillator, RTC and XRAM activities, since the presence of a stable V guarantees the proper biasing of all those modules.

Two 8-bit bidirectional I/O ports P0L and P0H, bit-wise programmable for input or output via direction bit. Programming an I/O pin as input forces the corresponding output driver to high impedance state. The input threshold of Port 0 is selectable (TTL or CMOS). In case of an external bus configuration, PORT0 serves as the address (A) and as the address / data (AD) bus in multiplexed bus modes and as the data (D) bus in demultiplexed bus modes.

Demultiplexed bus modes

Data path width 8-bit 16-bi

I/O

P0L.0 – P0L.7: D0 – D7 D0 - D7

P0H.0 – P0H.7: I/O D8 - D15

P1L.0 - P1L.7

P1H.0 - P1H.7

Multiplexed bus modes

Data path width 8-bit 16-bi

P0L.0 – P0L.7: AD0 – AD7 AD0 - AD7

P0H.0 – P0H.7: A8 – A15 AD8 - AD15

Two 8-bit bidirectional I/O ports P1L and P1H, bit-wise programmable for input or output via direction bit. Programming an I/O pin as input forces the corresponding output driver to high impedance state. PORT1 is used as the 16bit address bus (A) in demultiplexed bus modes: if at least BUSCONx is

118-125 128-135

configured such the demultiplexed mode is selected, the pis of PORT1 are not available for general purpose I/O function. The input threshold of Port 1 is

I/O

selectable (TTL or CMOS). The pins of P1L also serve as the additional (up to 8) analog input channels for

the A/D converter, where P1L.x equals ANy (Analog input channel y, where y = x + 16). This additional function have higher priority on demultiplexed bus function. The following PORT1 pins have alternate functions:

132 I P1H.4 CC24IO CAPCOM2: CC24 capture input

133 I P1H.5 CC25IO CAPCOM2: CC25 capture input

134 I P1H.6 CC26IO CAPCOM2: CC26 capture input

135 I P1H.7 CC27IO CAPCOM2: CC27 capture input

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ST10F276Z5 Pin data

Table 2. Pin description (continued)

Symbol Pin Type Function

XTAL1 138 I XTAL1 Main oscillator amplifier circuit and/or external clock input.

XTAL2 137 O XTAL2 Main oscillator amplifier circuit output.

To clock the device from an external source, drive XTAL1 while leaving XTAL2 unconnected. Minimum and maximum high / low and rise / fall times specified in the AC Characteristics must be observed.

XTAL3 143 I XTAL3 32 kHz oscillator amplifier circuit input

XTAL4 144 O XTAL4 32 kHz oscillator amplifier circuit output

When 32 kHz oscillator amplifier is not used, to avoid spurious consumption, XTAL3 shall be tied to ground while XTAL4 shall be left open. Besides, bit OFF32 in RTCCON register shall be set. 32 kHz oscillator can only be driven by an external crystal, and not by a different clock source.

Reset Input with CMOS Schmitt-Trigger characteristics. A low level at this pin for a specified duration while the oscillator is running resets the device. An internal

RSTIN

RSTOUT

NMI

140 I

141 O

142 I

pull-up resistor permits power-on reset using only a capacitor connected to V In bidirectional reset mode (enabled by setting bit BDRSTEN in SYSCON register), the RSTIN

line is pulled low for the duration of the internal reset

sequence.

Internal Reset Indication Output. This pin is driven to a low level during hardware, software or watchdog timer reset.

RSTOUT

remains low until the EINIT

(end of initialization) instruction is executed.

Non-Maskable Interrupt Input. A high to low transition at this pin causes the CPU to vector to the NMI trap routine. If bit PWDCFG = ‘0’ in SYSCON register, when the PWRDN (Power-down) instruction is executed, the NMI pin must be low in order to force the device to go into Power-down mode. If NMI is high and PWDCFG =’0’, when PWRDN is executed, the part will continue to run in normal mode. If not used, pin NMI

should be pulled high externally.

AREF

AGND

37 - A/D converter reference voltage and analog supply

38 - A/D converter reference and analog ground

RPD 84 -

17, 46,

72,82,93, 109, 126,

136

18,45, 55,71,

83,94,

110, 127,

139

56 -

Timing pin for the return from interruptible Power-down mode and synchronous / asynchronous reset selection.

Digital supply voltage = + 5 V during normal operation, idle and Power-down

modes. It can be turned off when Standby RAM mode is selected.

- Digital ground

1.8 V decoupling pin: a decoupling capacitor (typical value of 10 nF, max 100 nF) must be connected between this pin and nearest V

pin.

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Functional description ST10F276Z5

3 Functional description

The ST10F276Z5 architecture combines advantages of both RISC and CISC processors and an advanced peripheral subsystem. The block diagram gives an overview of the different on-chip components and the high bandwidth internal bus structure of the ST10F276Z5.

Figure 3. Block diagram

XFLASH

16 16

IFLASH

XPWM

XCAN2

Controller

External Bus

320K

XRAM

48K

XRAM

16K

(STBY)

XRAM

(PEC)

XI2C

XCAN1

Por t 0Por t 1Port 4

Por t 6

81615 8 8

512K

XRTC

XASC

XSSC

Por t 5

CPU-Core and MAC Unit

Interrupt Controller

10-bit ADC

GPT1 / GPT2

BRG BRG

Port 3 Port 7 Por t 8

ASC0

SSC0

PEC

PWM

CAPCOM2

IRAM

Watchdog

Oscillator

32kHz

Oscillator

PLL

5V-1.8V

Vol tag e

Regulator

CAPCOM1

Por t 2

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ST10F276Z5 Internal Flash memory

4 Internal Flash memory

4.1 Overview

The on-chip Flash is composed by two matrix modules each one containing one array divided in two banks that can be read and modified independently one of the other: one bank can be read while another bank is under modification.

Figure 4. Flash modules structure

IFLASH (Module I)

Bank 1: 128 Kbyte

program memory

Bank 0: 384 Kbyte

program memory

8 Kbyte test-Flash

I-BUS interface

The write operations of the 4 banks are managed by an embedded Flash program/erase controller (FPEC). The high voltages needed for program/erase operations are internally generated.

The data bus is 32-bit wide. Due to ST10 core architecture limitation, only the first 512 Kbytes are accessed at 32-bit (internal Flash bus, see I-BUS), while the remaining 320 Kbytes are accessed at 16-bit (see X-BUS).

4.2 Functional description

Control section

HV and Ref.

generator

Program/erase

controller

XFLASH (Module X)

Bank 3: 128 Kbyte

Bank 2: 192 Kbyte

X-BUS interface

program memory

4.2.1 Structure

The following table shows the address space reserved to the Flash module.

Table 3. Flash modules absolute mapping

IFLASH sectors 0x00 0000 to 0x08 FFFF 512 Kbyte

XFLASH sectors 0x09 0000 to 0x0D FFFF 320 Kbyte

Registers and Flash internal reserved area

Description Addresses Size

0x0E 0000 to 0x0E FFFF 64 Kbyte

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Internal Flash memory ST10F276Z5

4.2.2 Modules structure

The IFLASH module is composed by 2 banks. Bank 0 contains 384 Kbyte of program memory divided in 10 sectors. Bank 0 contains also a reserved sector named test-Flash. Bank 1 contains 128 Kbyte of program memory or parameter divided in 2 sectors (64 Kbyte each).

The XFLASH module is composed by 2 banks as well. Bank 2 contains 192 Kbyte of Program Memory divided in 3 sectors. Bank 3 contains 128 Kbyte of program memory or parameter divided in 2 sectors (64 Kbyte each).

Addresses from 0x0E 0000 to 0x0E FFFF are reserved for the control register interface and other internal service memory space used by the Flash program/erase controller.

The following tables show the memory mapping of the Flash when it is accessed in read mode (Ta bl e 4 ), and when accessed in write or erase mode (Ta bl e 3 ): note that with this second mapping, the first three banks are remapped into code segment 1 (same as obtained when setting bit ROMS1 in SYSCON register).

Table 4. Flash modules sectorization (read operations)

Bank Description Addresses Size

Bank 0 Flash 0 (B0F0) 0x0000 0000 - 0x0000 1FFF 8 KB

Bank 0 Flash 1 (B0F1) 0x0000 2000 - 0x0000 3FFF 8 KB

Bank 0 Flash 2 (B0F2) 0x0000 4000 - 0x0000 5FFF 8 KB

Bank 0 Flash 3 (B0F3) 0x0000 6000 - 0x0000 7FFF 8 KB

Bank 0 Flash 4 (B0F4) 0x0001 8000 - 0x0001 FFFF 32 KB

Bank 0 Flash 5 (B0F5) 0x0002 0000 - 0x0002 FFFF 64 KB

Bank 0 Flash 6 (B0F6) 0x0003 0000 - 0x0003 FFFF 64 KB

Bank 0 Flash 7 (B0F7) 0x0004 0000 - 0x0004 FFFF 64 KB

Bank 0 Flash 8 (B0F8) 0x0005 0000 - 0x0005 FFFF 64 KB

Bank 0 Flash 9 (B0F9) 0x0006 0000 - 0x0006 FFFF 64 KB

Bank 1 Flash 0 (B1F0) 0x0007 0000 - 0x0007 FFFF 64 KB

Bank 1 Flash 1 (B1F1) 0x0008 0000 - 0x0008 FFFF 64 KB

Bank 2 Flash 0 (B2F0) 0x0009 0000 - 0x0009 FFFF 64 KB

Bank 2 Flash 1 (B2F1) 0x000A 0000 - 0x000A FFFF 64 KB

Bank 2 Flash 2 (B2F2) 0x000B 0000 - 0x000B FFFF 64 KB

Bank 3 Flash 0 (B3F0) 0x000C 0000 - 0x000C FFFF 64 KB

Bank 3 Flash 1 (B3F1) 0x000D 0000 - 0x000D FFFF 64 KB

ST10 bus

size

32-bit (I-BUS)

16-bit

(X-BUS)

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ST10F276Z5 Internal Flash memory

Table 5. Flash modules sectorization (write operations or with roms1=’1’)

Bank Description Addresses Size

Bank 0 Test-Flash (B0TF) 0x0000 0000 - 0x0000 1FFF 8 KB

Bank 0 Flash 0 (B0F0) 0x0001 0000 - 0x0001 1FFF 8 KB

Bank 0 Flash 1 (B0F1) 0x0001 2000 - 0x0001 3FFF 8 KB

Bank 0 Flash 2 (B0F2) 0x0001 4000 - 0x0001 5FFF 8 KB

Bank 0 Flash 3 (B0F3) 0x0001 6000 - 0x0001 7FFF 8 KB

Bank 0 Flash 4 (B0F4) 0x0001 8000 - 0x0001 FFFF 32 KB

Bank 0 Flash 5 (B0F5) 0x0002 0000 - 0x0002 FFFF 64 KB

Bank 0 Flash 6 (B0F6) 0x0003 0000 - 0x0003 FFFF 64 KB

Bank 0 Flash 7 (B0F7) 0x0004 0000 - 0x0004 FFFF 64 KB

Bank 0 Flash 8 (B0F8) 0x0005 0000 - 0x0005 FFFF 64 KB

Bank 0 Flash 9 (B0F9) 0x0006 0000 - 0x0006 FFFF 64 KB

Bank 1 Flash 0 (B1F0) 0x0007 0000 - 0x0007 FFFF 64 KB

Bank 1 Flash 1 (B1F1) 0x0008 0000 - 0x0008 FFFF 64 KB

Bank 2 Flash 0 (B2F0) 0x0009 0000 - 0x0009 FFFF 64 KB

Bank 2 Flash 1 (B2F1) 0x000A 0000 - 0x000A FFFF 64 KB

Bank 2 Flash 2 (B2F2) 0x000B 0000 - 0x000B FFFF 64 KB

Bank 3 Flash 0 (B3F0) 0x000C 0000 - 0x000C FFFF 64 KB

Bank 3 Flash 1 (B3F1) 0x000D 0000 - 0x000D FFFF 64 KB

ST10 Bus

size

32-bit (I-BUS)

16-bit

(X-BUS)

The table above refers to the configuration when bit ROMS1 of SYSCON register is set. When Bootstrap mode is entered:

● Test-Flash is seen and available for code fetches (address 00’0000h)

● User IFlash is only available for read and write accesses

● Write accesses must be made with addresses starting in segment 1 from 01'0000h,

whatever ROMS1 bit in SYSCON value

● Read accesses are made in segment 0 or in segment 1 depending of ROMS1 value.

In Bootstrap mode, by default ROMS1 = 0, so the first 32KBytes of IFlash are mapped in segment 0.

Example: In default configuration, to program address 0, user must put the value 01'0000h in the FARL and FARH registers, but to verify the content of the address 0 a read to 00'0000h must be performed.

Table 6 shows the control register interface composition: this set of registers can be addressed by the CPU.

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Internal Flash memory ST10F276Z5

Table 6. Control register interface

Bank Description Addresses Size

FCR1-0 Flash control registers 1-0 0x000E 0000 - 0x000E 0007 8 byte

FDR1-0 Flash data registers 1-0 0x000E 0008 - 0x000E 000F 8 byte

FAR Flash address registers 0x000E 0010 - 0x000E 0013 4 byte

FER Flash error register 0x000E 0014 - 0x000E 0015 2 byte

FNVWPXR

FNVWPIR

FNVAPR0

FNVAPR1

XFICR XFlash interface control register 0x000E E000 - 0x000E E001 2 byte

Flash non volatile protection X register

Flash non volatile protection I register

Flash non volatile access protection register 0

Flash non volatile access protection register 1

0x000E DFB0 - 0x000E DFB3 4 byte

0x000E DFB4 - 0x000E DFB7 4 byte

0x000E DFB8 - 0x000E DFB9 2 byte

0x000E DFBC - 0x000E DFBF 4 byte

ST10

bus size

16-bit

(X-BUS)

4.2.3 Low power mode

The Flash modules are automatically switched off executing PWRDN instruction. The consumption is drastically reduced, but exiting this state can require a long time (t

Note: Recovery time from Power-down mode for the Flash modules is anyway shorter than the

main oscillator start-up time. To avoid any problem in restarting to fetch code from the Flash, it is important to size properly the external circuit on RPD pin.

Power-off Flash mode is entered only at the end of the eventually running Flash write operation.

4.3 Write operation

The Flash modules have one single register interface mapped in the memory space of the XFlash module (0x0E 0000 to 0x0E 0013). All the operations are enabled through four 16-bit control registers: Flash Control Register 1-0 High/Low (FCR1H/L-FCR0H/L). Eight other 16bit registers are used to store Flash Address and Data for Program operations (FARH/L and FDR1H/L-FDR0H/L) and Write Operation Error flags (FERH/L). All registers are accessible with 8 and 16-bit instructions (since mapped on ST10 XBUS).

Note: Before accessing the XFlash module (and consequently also the Flash register to be used

for program/erasing operations), bit XFLASHEN in XPERCON register and bit XPEN in SYSCON register shall be set.

The 4 Banks have their own dedicated sense amplifiers, so that any Bank can be read while any other Bank is written. However simultaneous write operations (“write” means either Program or Erase) on different Banks are forbidden: when there is a write operation on going (Program or Erase) anywhere in the Flash, no other write operation can be performed.

During a Flash write operation any attempt to read the bank under modification will output invalid data (software trap 009Bh). This means that the Flash Bank is not fetchable when a write operation is active: the write operation commands must be executed from another

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ST10F276Z5 Internal Flash memory

Bank, or from the other module or again from another memory (internal RAM or external memory).

Note: During a Write operation, when bit LOCK of FCR0 is set, it is forbidden to write into the

Flash Control Registers.

4.3.1 Power supply drop

If during a write operation the internal low voltage supply drops below a certain internal voltage threshold, any write operation running is suddenly interrupted and the modules are reset to Read mode. At following Power-on, an interrupted Flash write operation must be repeated.

4.4 Registers description

4.4.1 Flash control register 0 low

The Flash control register 0 low (FCR0L) together with the Flash control register 0 high (FCR0H) is used to enable and to monitor all the write operations for both the Flash modules. The user has no access in write mode to the test-Flash (B0TF). Besides, testFlash block is seen by the user in Bootstrap mode only.

FCR0L (0x0E 0000) FCR Reset value: 0000h

1514131211109876543210

reserved BSY1 BSY0 LOCK res. BSY3 BSY2 res.

RRR RR

Table 7. Flash control register 0 low

Bit Function

Bank 3:2 Busy (XFLASH) These bits indicate that a write operation is running on the corresponding Bank of

XFLASH. They are automatically set when bit WMS is set. Setting Protection operation sets bit BSY2 (since protection registers are in the Block B2). When these

BSY(3:2)

bits are set every read access to the corresponding Bank will output invalid data (software trap 009Bh), while every write access to the Bank will be ignored. At the end of the write operation or during a Program or Erase Suspend these bits are automatically reset and the Bank returns to read mode. After a Program or Erase Resume these bits are automatically set again.

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Internal Flash memory ST10F276Z5

Table 7. Flash control register 0 low (continued)

Bit Function

Flash registers access locked When this bit is set, it means that the access to the Flash Control Registers FCR0H/-

FCR1H/L, FDR0H/L-FDR1H/L, FARH/L and FER is locked by the FPEC: any read access to the registers will output invalid data (software trap 009Bh) and any write

LOCK

BSY(1:0)

access will be ineffective. LOCK bit is automatically set when the Flash bit WMS is set. This is the only bit the user can always access to detect the status of the Flash: once it is found low, the rest of FCR0L and all the other Flash registers are accessible by the user as well. Note that FER content can be read when LOCK is low, but its content is updated only when also BSY bits are reset.

Bank 1:0 Busy (IFLASH) These bits indicate that a write operation is running in the corresponding Bank of

IFLASH. They are automatically set when bit WMS is set. When these bits are set every read access to the corresponding Bank will output invalid data (software trap 009Bh), while every write access to the Bank will be ignored. At the end of the write operation or during a Program or Erase Suspend these bits are automatically reset and the Bank returns to read mode. After a Program or Erase Resume these bits are automatically set again.

4.4.2 Flash control register 0 high

The Flash control register 0 high (FCR0H) together with the Flash control register 0 Low (FCR0L) is used to enable and to monitor all the write operations for both the Flash modules. The user has no access in write mode to the Test-Flash (B0TF). Besides, testFlash block is seen by the user in Bootstrap mode only.

FCR0H (0x0E 0002) FCR Reset value: 0000h

1514131211109876543210

WMS SUSP WPG DWPG SER Reserved SPR SMOD Reserved

RW RW RW RW RW RW RW

Table 8. Flash control register 0 high

Bit Function

Select module

SMOD

SPR

If this bit is reset, the Write Operation is performed on XFLASH Module; if this bit is set, the Write Operation is performed on IFLASH Module. SMOD bit is automatically reset at the end of the Write operation.

Set protection This bit must be set to select the Set Protection operation. The Set Protection

operation allows to program 0s in place of 1s in the Flash Non Volatile Protection Registers. The Flash Address in which to program must be written in the FARH/L registers, while the Flash Data to be programmed must be written in the FDR0H/L before starting the execution by setting bit WMS. A sequence error is flagged by bit SEQER of FER if the address written in FARH/L is not in the range 0x0EDFB00x0EDFBF. SPR bit is automatically reset at the end of the Set Protection operation.

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