The ST10F276Z5 is a derivative of the STMicroelectronics ST10 family of 16-bit single-chip
CMOS microcontrollers. It combines high CPU performance (up to 32 million instructions
per second) with high peripheral functionality and enhanced I/O-capabilities. It also provides
on-chip high-speed single voltage Flash memory, on-chip high-speed RAM, and clock
generation via PLL.
The ST10F276Z5 is processed in 0.18 µm CMOS technology. The MCU core and the logic
is supplied with a 5 to 1.8 V on-chip voltage regulator. The part is supplied with a single 5 V
supply and I/Os work at 5 V.
The device is upward compatible with the ST10F269 device, with the following set of
differences:
●Flash control interface is now based on STMicroelectronics third generation of stand-
alone Flash memories (M29F400 series), with an embedded Program/Erase Controller.
This completely frees up the CPU during programming or erasing the Flash.
●Only one supply pin (ex DC1 in ST10F269, renamed into V
is used for decoupling the internally generated 1.8 V core logic supply. Do not connect
this pin to 5.0 V external supply. Instead, this pin should be connected to a decoupling
capacitor (ceramic type, typical value 10 nF, maximum value 100 nF).
●The AC and DC parameters are modified due to a difference in the maximum CPU
frequency.
●A new V
●EA pin assumes a new alternate functionality: it is also used to provide a dedicated
power supply (see V
the main Power Supply of the device (V
V
) is turned off for low power mode, allowing data retention. V
18
pin replaces DC2 of ST10F269.
DD
) to maintain biased a portion of the XRAM (16Kbytes) when
STBY
and consequently the internally generated
DD
the range 4.5-5.5 V, and a dedicated embedded low power voltage regulator is in
charge to provide the 1.8 V for the RAM, the low-voltage section of the 32 kHz oscillator
and the real-time clock module when not disabled. It is allowed to exceed the upper
limit up to 6 V for a very short period of time during the global life of the device, and
exceed the lower limit down to 4 V when RTC and 32 kHz on-chip oscillator are not
used.
●A second SSC mapped on the XBUS is added (SSC of ST10F269 becomes here
SSC0, while the new one is referred as XSSC or simply SSC1). Note that some
restrictions and functional differences due to the XBUS peculiarities are present
between the classic SSC, and the new XSSC.
●A second ASC mapped on the XBUS is added (ASC0 of ST10F269 remains ASC0,
while the new one is referred as XASC or simply as ASC1). Note that some restrictions
and functional differences due to the XBUS peculiarities are present between the
classic ASC, and the new XASC.
●A second PWM mapped on the XBUS is added (PWM of ST10F269 becomes here
PWM0, while the new one is referred as XPWM or simply as PWM1). Note that some
) on the QFP144 package
18
voltage shall be in
STBY
14/239
ST10F276Z5Description
restrictions and functional differences due to the XBUS peculiarities are present
between the classic PWM, and the new XPWM.
●An I
●CLKOUT function can output either the CPU clock (like in ST10F269) or a software
2
C interface on the XBUS is added (see X-I2C or simply I2C interface).
programmable prescaled value of the CPU clock.
●Embedded memory size has been significantly increased (both Flash and RAM).
●PLL multiplication factors have been adapted to new frequency range.
●A/D Converter is not fully compatible versus ST10F269 (timing and programming
model). Formula for the conversion time is still valid, while the sampling phase
programming model is different.
Besides, additional 8 channels are available on P1L pins as alternate function: the
accuracy reachable with these extra channels is reduced with respect to the standard
Port5 channels.
●External Memory bus potential limitations on maximum speed and maximum
capacitance load could be introduced (under evaluation): ST10F276Z5 will probably
not be able to address an external memory at 64 MHz with 0 wait states (under
evaluation).
●XPERCON register bit mapping modified according to new peripherals implementation
(not fully compatible with ST10F269).
●Bond-out chip for emulation (ST10R201) cannot achieve more than 50 MHz at room
temperature (so no real-time emulation possible at maximum speed).
●Input section characteristics are different. The threshold programmability is extended to
all port pins (additional XPICON register); it is possible to select standard TTL (with up
to 500 mV of hysteresis) and standard CMOS (with up to 800 mV of hysteresis).
●Output transition is not programmable.
●CAN module is enhanced: the ST10F276Z5 implements two C-CAN modules, so the
programming model is slightly different. Besides, the possibility to map in parallel the
two CAN modules is added (on P4.5/P4.6).
●On-chip main oscillator input frequency range has been reshaped, reducing it from 1-
25 MHz down to 4-12 MHz. This is a high performance oscillator amplifier, providing a
very high negative resistance and wide oscillation amplitude: when this on-chip
amplifier is used as reference for real-time clock module, the power-down consumption
is dominated by the consumption of the oscillator amplifier itself. A metal option is
added to offer a low power oscillator amplifier working in the range of 4-8 MHz: this will
allow a power consumption reduction when real-time clock is running in Power-down
mode using as reference the on-chip main oscillator clock.
●A second on-chip oscillator amplifier circuit (32 kHz) is implemented for low power
modes: it can be used to provide the reference to the real-time clock counter (either in
Power-down or Standby mode). Pin XTAL3 and XTAL4 replace a couple of V
DD/VSS
pins of ST10F269.
●Possibility to re-program internal XBUS chip select window characteristics (XRAM2 and
8-bit bidirectional I/O port, bit-wise programmable for input or output via direction
bit. Programming an I/O pin as input forces the corresponding output driver to
1 - 8I/O
1OP6.0CS0
...............
high impedance state. Port 6 outputs can be configured as push-pull or open
drain drivers. The input threshold of Port 6 is selectable (TTL or CMOS). The
following Port 6 pins have alternate functions:
8-bit bidirectional I/O port, bit-wise programmable for input or output via direction
bit. Programming an I/O pin as input forces the corresponding output driver to
high impedance state. Port 8 outputs can be configured as push-pull or open
drain drivers. The input threshold of Port 8 is selectable (TTL or CMOS).
The following Port 8 pins have alternate functions:
OTxD1ASC1: Clock / Data output (Asynchronous/Synchronous)
External master hold request input
18/239
ST10F276Z5Pin data
Table 2.Pin description (continued)
SymbolPinTypeFunction
8-bit bidirectional I/O port, bit-wise programmable for input or output via direction
bit. Programming an I/O pin as input forces the corresponding output driver to
39IP5.10T6EUDGPT2: timer T6 external up/down control input
40IP5.11T5EUDGPT2: timer T5 external up/down control input
41IP5.12T6INGPT2: timer T6 count input
42IP5.13T5INGPT2: timer T5 count input
43IP5.14T4EUDGPT1: timer T4 external up/down control input
high impedance state. Port 7 outputs can be configured as push-pull or open
drain drivers. The input threshold of Port 7 is selectable (TTL or CMOS).
The following Port 7 pins have alternate functions:
16-bit input-only port with Schmitt-Trigger characteristics. The pins of Port 5 can
be the analog input channels (up to 16) for the A/D converter, where P5.x equals
I
ANx (Analog input channel x), or they are timer inputs. The input threshold of
I
Port 5 is selectable (TTL or CMOS). The following Port 5 pins have alternate
functions:
P2.0 - P2.7
P2.8 - P2.15
44IP5.15T2EUDGPT1: timer T2 external up/down control input
16-bit bidirectional I/O port, bit-wise programmable for input or output via
direction bit. Programming an I/O pin as input forces the corresponding output
I/O
driver to high impedance state. Port 2 outputs can be configured as push-pull or
open drain drivers. The input threshold of Port 2 is selectable (TTL or CMOS).
The following Port 2 pins have alternate functions:
IEX0INFast external interrupt 0 input
IEX7INFast external interrupt 7 input
IT7INCAPCOM2: timer T7 count input
19/239
Pin dataST10F276Z5
Table 2.Pin description (continued)
SymbolPinTypeFunction
15-bit (P3.14 is missing) bidirectional I/O port, bit-wise programmable for input or
65-70,
73-80,
81
65IP3.0T0INCAPCOM1: timer T0 count input
66OP3.1T6OUTGPT2: timer T6 toggle latch output
67IP3.2CAPINGPT2: register CAPREL capture input
68OP3.3T3OUTGPT1: timer T3 toggle latch output
69IP3.4T3EUDGPT1: timer T3 external up/down control input
I/O
output via direction bit. Programming an I/O pin as input forces the
I/O
corresponding output driver to high impedance state. Port 3 outputs can be
I/O
configured as push-pull or open drain drivers. The input threshold of Port 3 is
selectable (TTL or CMOS). The following Port 3 pins have alternate functions:
P3.0 - P3.5
P3.6 - P3.13,
P3.15
70IP3.5T4INGPT1; timer T4 input for count/gate/reload/capture
73IP3.6T3INGPT1: timer T3 count/gate input
74IP3.7T2INGPT1: timer T2 input for count/gate/reload / capture
System clock output (programmable divider on CPU
clock)
20/239
ST10F276Z5Pin data
Table 2.Pin description (continued)
SymbolPinTypeFunction
Port 4 is an 8-bit bidirectional I/O port. It is bit-wise programmable for input or
output via direction bit. Programming an I/O pin as input forces the
corresponding output driver to high impedance state. The input threshold is
85-92I/O
85OP4.0A16Segment address line
86OP4.1A17Segment address line
87OP4.2A18Segment address line
88OP4.3A19Segment address line
89OP4.4A20Segment address line
P4.0 –P4.7
90OP4.5A21Segment address line
91OP4.6A22Segment address line
selectable (TTL or CMOS). Port 4.4, 4.5, 4.6 and 4.7 outputs can be configured
as push-pull or open drain drivers.
In case of an external bus configuration, Port 4 can be used to output the
segment address lines:
ICAN2_RxD CAN2: receive data input
I/OSCL
I2C Interface: serial clock
ICAN1_RxD CAN1: receive data input
ICAN2_RxD CAN2: receive data input
92OP4.7A23Most significant segment address line
RD95O
/WRL96O
WR
READY/
READY
97I
ALE98O
OCAN1_TxDCAN1: transmit data output
OCAN2_TxDCAN2: transmit data output
OCAN2_TxDCAN2: transmit data output
I/OSDA
External memory read strobe. RD
I2C Interface: serial data
is activated for every external instruction or
data read access.
External memory write strobe. In WR
external data write access. In WRL
-mode this pin is activated for every
mode this pin is activated for low byte data
write accesses on a 16-bit bus, and for every data write access on an 8-bit bus.
See WRCFG in the SYSCON register for mode selection.
Ready input. The active level is programmable. When the ready function is
enabled, the selected inactive level at this pin, during an external memory
access, will force the insertion of waitstate cycles until the pin returns to the
selected active level.
Address latch enable output. In case of use of external addressing or of
multiplexed mode, this signal is the latch command of the address lines.
21/239
Pin dataST10F276Z5
Table 2.Pin description (continued)
SymbolPinTypeFunction
External access enable pin.
A low level applied to this pin during and after Reset forces the ST10F276Z5 to
start the program from the external memory space. A high level forces the
ST10F276Z5 to start in the internal memory space. This pin is also used (when
turned
DD
DD
EA / V
STBY
P0L.0 -P0L.7,
P0H.0
P0H.1 - P0H.7
99I
100-107,
108,
111-117
Standby mode is entered, that is the device under reset and main V
off) to bias the 32 kHz oscillator amplifier circuit and to provide a reference
voltage for the low-power embedded voltage regulator which generates the
internal 1.8 V supply for the RTC module (when not disabled) and to retain data
inside the Standby portion of the XRAM (16Kbyte).
It can range from 4.5 to 5.5 V (6 V for a reduced amount of time during the
device life, 4.0 V when RTC and 32 kHz on-chip oscillator amplifier are turned
off). In running mode, this pin can be tied low during reset without affecting 32
kHz oscillator, RTC and XRAM activities, since the presence of a stable V
guarantees the proper biasing of all those modules.
Two 8-bit bidirectional I/O ports P0L and P0H, bit-wise programmable for input or
output via direction bit. Programming an I/O pin as input forces the
corresponding output driver to high impedance state. The input threshold of
Port 0 is selectable (TTL or CMOS).
In case of an external bus configuration, PORT0 serves as the address (A) and
as the address / data (AD) bus in multiplexed bus modes and as the data (D) bus
in demultiplexed bus modes.
Demultiplexed bus modes
Data path width8-bit16-bi
I/O
P0L.0 – P0L.7:D0 – D7D0 - D7
P0H.0 – P0H.7:I/OD8 - D15
P1L.0 - P1L.7
P1H.0 - P1H.7
Multiplexed bus modes
Data path width8-bit16-bi
P0L.0 – P0L.7:AD0 – AD7AD0 - AD7
P0H.0 – P0H.7:A8 – A15AD8 - AD15
Two 8-bit bidirectional I/O ports P1L and P1H, bit-wise programmable for input or
output via direction bit. Programming an I/O pin as input forces the
corresponding output driver to high impedance state. PORT1 is used as the 16bit address bus (A) in demultiplexed bus modes: if at least BUSCONx is
118-125
128-135
configured such the demultiplexed mode is selected, the pis of PORT1 are not
available for general purpose I/O function. The input threshold of Port 1 is
I/O
selectable (TTL or CMOS).
The pins of P1L also serve as the additional (up to 8) analog input channels for
the A/D converter, where P1L.x equals ANy (Analog input channel y,
where y = x + 16). This additional function have higher priority on demultiplexed
bus function. The following PORT1 pins have alternate functions:
132IP1H.4 CC24IOCAPCOM2: CC24 capture input
133IP1H.5 CC25IOCAPCOM2: CC25 capture input
134IP1H.6 CC26IOCAPCOM2: CC26 capture input
135IP1H.7 CC27IOCAPCOM2: CC27 capture input
22/239
ST10F276Z5Pin data
Table 2.Pin description (continued)
SymbolPinTypeFunction
XTAL1138IXTAL1 Main oscillator amplifier circuit and/or external clock input.
XTAL2137OXTAL2 Main oscillator amplifier circuit output.
To clock the device from an external source, drive XTAL1 while leaving XTAL2
unconnected. Minimum and maximum high / low and rise / fall times specified in
the AC Characteristics must be observed.
When 32 kHz oscillator amplifier is not used, to avoid spurious consumption,
XTAL3 shall be tied to ground while XTAL4 shall be left open. Besides, bit OFF32
in RTCCON register shall be set. 32 kHz oscillator can only be driven by an
external crystal, and not by a different clock source.
Reset Input with CMOS Schmitt-Trigger characteristics. A low level at this pin for
a specified duration while the oscillator is running resets the device. An internal
RSTIN
RSTOUT
NMI
140I
141O
142I
pull-up resistor permits power-on reset using only a capacitor connected to V
In bidirectional reset mode (enabled by setting bit BDRSTEN in SYSCON
register), the RSTIN
line is pulled low for the duration of the internal reset
sequence.
Internal Reset Indication Output. This pin is driven to a low level during
hardware, software or watchdog timer reset.
RSTOUT
remains low until the EINIT
(end of initialization) instruction is executed.
Non-Maskable Interrupt Input. A high to low transition at this pin causes the CPU
to vector to the NMI trap routine. If bit PWDCFG = ‘0’ in SYSCON register, when
the PWRDN (Power-down) instruction is executed, the NMI pin must be low in
order to force the device to go into Power-down mode. If NMI is high and
PWDCFG =’0’, when PWRDN is executed, the part will continue to run in normal
mode.
If not used, pin NMI
should be pulled high externally.
SS
.
V
AREF
V
AGND
37-A/D converter reference voltage and analog supply
38-A/D converter reference and analog ground
RPD84-
17, 46,
V
DD
72,82,93,
109, 126,
136
18,45,
55,71,
V
SS
83,94,
110, 127,
139
V
18
56-
Timing pin for the return from interruptible Power-down mode and synchronous /
asynchronous reset selection.
Digital supply voltage = + 5 V during normal operation, idle and Power-down
-
modes.
It can be turned off when Standby RAM mode is selected.
-Digital ground
1.8 V decoupling pin: a decoupling capacitor (typical value of 10 nF, max 100 nF)
must be connected between this pin and nearest V
SS
pin.
23/239
Functional descriptionST10F276Z5
3 Functional description
The ST10F276Z5 architecture combines advantages of both RISC and CISC processors
and an advanced peripheral subsystem. The block diagram gives an overview of the
different on-chip components and the high bandwidth internal bus structure of the
ST10F276Z5.
Figure 3.Block diagram
XFLASH
16
16
8
16
16
16
16 16
16 16
16 16
16
16
IFLASH
XPWM
XCAN2
Controller
External Bus
320K
XRAM
48K
XRAM
16K
(STBY)
XRAM
2K
(PEC)
XI2C
XCAN1
Por t 0Por t 1Port 4
Por t 6
81615 8 8
512K
XRTC
XASC
XSSC
16
16
Por t 5
32
CPU-Core and MAC Unit
Interrupt Controller
10-bit ADC
GPT1 / GPT2
BRGBRG
Port 3Port 7Por t 8
ASC0
SSC0
PEC
PWM
16
16
CAPCOM2
IRAM
2K
Watchdog
Oscillator
32kHz
Oscillator
PLL
5V-1.8V
Vol tag e
Regulator
CAPCOM1
16
Por t 2
24/239
ST10F276Z5Internal Flash memory
4 Internal Flash memory
4.1 Overview
The on-chip Flash is composed by two matrix modules each one containing one array
divided in two banks that can be read and modified independently one of the other: one
bank can be read while another bank is under modification.
Figure 4.Flash modules structure
IFLASH (Module I)
Bank 1: 128 Kbyte
program memory
Bank 0: 384 Kbyte
program memory
+
8 Kbyte test-Flash
I-BUS interface
The write operations of the 4 banks are managed by an embedded Flash program/erase
controller (FPEC). The high voltages needed for program/erase operations are internally
generated.
The data bus is 32-bit wide. Due to ST10 core architecture limitation, only the first
512 Kbytes are accessed at 32-bit (internal Flash bus, see I-BUS), while the remaining
320 Kbytes are accessed at 16-bit (see X-BUS).
4.2 Functional description
Control section
HV and Ref.
generator
Program/erase
controller
XFLASH (Module X)
Bank 3: 128 Kbyte
Bank 2: 192 Kbyte
X-BUS interface
program memory
program memory
4.2.1 Structure
The following table shows the address space reserved to the Flash module.
Table 3.Flash modules absolute mapping
IFLASH sectors0x00 0000 to 0x08 FFFF512 Kbyte
XFLASH sectors0x09 0000 to 0x0D FFFF320 Kbyte
Registers and Flash internal reserved
area
DescriptionAddressesSize
0x0E 0000 to 0x0E FFFF64 Kbyte
25/239
Internal Flash memoryST10F276Z5
4.2.2 Modules structure
The IFLASH module is composed by 2 banks. Bank 0 contains 384 Kbyte of program
memory divided in 10 sectors. Bank 0 contains also a reserved sector named test-Flash.
Bank 1 contains 128 Kbyte of program memory or parameter divided in 2 sectors (64 Kbyte
each).
The XFLASH module is composed by 2 banks as well. Bank 2 contains 192 Kbyte of
Program Memory divided in 3 sectors. Bank 3 contains 128 Kbyte of program memory or
parameter divided in 2 sectors (64 Kbyte each).
Addresses from 0x0E 0000 to 0x0E FFFF are reserved for the control register interface and
other internal service memory space used by the Flash program/erase controller.
The following tables show the memory mapping of the Flash when it is accessed in read
mode (Ta bl e 4 ), and when accessed in write or erase mode (Ta bl e 3 ): note that with this
second mapping, the first three banks are remapped into code segment 1 (same as
obtained when setting bit ROMS1 in SYSCON register).
Bank 0 Flash 0 (B0F0)0x0000 0000 - 0x0000 1FFF8 KB
Bank 0 Flash 1 (B0F1)0x0000 2000 - 0x0000 3FFF8 KB
Bank 0 Flash 2 (B0F2)0x0000 4000 - 0x0000 5FFF8 KB
Bank 0 Flash 3 (B0F3)0x0000 6000 - 0x0000 7FFF8 KB
B0
B1
B2
B3
Bank 0 Flash 4 (B0F4)0x0001 8000 - 0x0001 FFFF32 KB
Bank 0 Flash 5 (B0F5)0x0002 0000 - 0x0002 FFFF64 KB
Bank 0 Flash 6 (B0F6)0x0003 0000 - 0x0003 FFFF64 KB
Bank 0 Flash 7 (B0F7)0x0004 0000 - 0x0004 FFFF64 KB
Bank 0 Flash 8 (B0F8)0x0005 0000 - 0x0005 FFFF64 KB
Bank 0 Flash 9 (B0F9)0x0006 0000 - 0x0006 FFFF64 KB
Bank 1 Flash 0 (B1F0)0x0007 0000 - 0x0007 FFFF64 KB
Bank 1 Flash 1 (B1F1)0x0008 0000 - 0x0008 FFFF64 KB
Bank 2 Flash 0 (B2F0)0x0009 0000 - 0x0009 FFFF64 KB
Bank 2 Flash 1 (B2F1)0x000A 0000 - 0x000A FFFF64 KB
Bank 2 Flash 2 (B2F2)0x000B 0000 - 0x000B FFFF64 KB
Bank 3 Flash 0 (B3F0)0x000C 0000 - 0x000C FFFF64 KB
Bank 3 Flash 1 (B3F1)0x000D 0000 - 0x000D FFFF64 KB
ST10 bus
size
32-bit (I-BUS)
16-bit
(X-BUS)
26/239
ST10F276Z5Internal Flash memory
Table 5.Flash modules sectorization (write operations or with roms1=’1’)
BankDescriptionAddressesSize
Bank 0 Test-Flash (B0TF)0x0000 0000 - 0x0000 1FFF8 KB
Bank 0 Flash 0 (B0F0)0x0001 0000 - 0x0001 1FFF8 KB
Bank 0 Flash 1 (B0F1)0x0001 2000 - 0x0001 3FFF8 KB
Bank 0 Flash 2 (B0F2)0x0001 4000 - 0x0001 5FFF8 KB
Bank 0 Flash 3 (B0F3)0x0001 6000 - 0x0001 7FFF8 KB
B0
B1
B2
B3
Bank 0 Flash 4 (B0F4)0x0001 8000 - 0x0001 FFFF32 KB
Bank 0 Flash 5 (B0F5)0x0002 0000 - 0x0002 FFFF64 KB
Bank 0 Flash 6 (B0F6)0x0003 0000 - 0x0003 FFFF64 KB
Bank 0 Flash 7 (B0F7)0x0004 0000 - 0x0004 FFFF64 KB
Bank 0 Flash 8 (B0F8)0x0005 0000 - 0x0005 FFFF64 KB
Bank 0 Flash 9 (B0F9)0x0006 0000 - 0x0006 FFFF64 KB
Bank 1 Flash 0 (B1F0)0x0007 0000 - 0x0007 FFFF64 KB
Bank 1 Flash 1 (B1F1)0x0008 0000 - 0x0008 FFFF64 KB
Bank 2 Flash 0 (B2F0)0x0009 0000 - 0x0009 FFFF64 KB
Bank 2 Flash 1 (B2F1)0x000A 0000 - 0x000A FFFF64 KB
Bank 2 Flash 2 (B2F2)0x000B 0000 - 0x000B FFFF64 KB
Bank 3 Flash 0 (B3F0)0x000C 0000 - 0x000C FFFF64 KB
Bank 3 Flash 1 (B3F1)0x000D 0000 - 0x000D FFFF64 KB
ST10 Bus
size
32-bit (I-BUS)
16-bit
(X-BUS)
The table above refers to the configuration when bit ROMS1 of SYSCON register is set.
When Bootstrap mode is entered:
●Test-Flash is seen and available for code fetches (address 00’0000h)
●User IFlash is only available for read and write accesses
●Write accesses must be made with addresses starting in segment 1 from 01'0000h,
whatever ROMS1 bit in SYSCON value
●Read accesses are made in segment 0 or in segment 1 depending of ROMS1 value.
In Bootstrap mode, by default ROMS1 = 0, so the first 32KBytes of IFlash are mapped in
segment 0.
Example: In default configuration, to program address 0, user must put the value 01'0000h
in the FARL and FARH registers, but to verify the content of the address 0 a read to
00'0000h must be performed.
Table 6 shows the control register interface composition: this set of registers can be
addressed by the CPU.
27/239
Internal Flash memoryST10F276Z5
Table 6.Control register interface
BankDescriptionAddressesSize
FCR1-0Flash control registers 1-00x000E 0000 - 0x000E 00078 byte
FDR1-0Flash data registers 1-00x000E 0008 - 0x000E 000F8 byte
XFICRXFlash interface control register0x000E E000 - 0x000E E0012 byte
Flash non volatile protection
X register
Flash non volatile protection
I register
Flash non volatile access
protection register 0
Flash non volatile access
protection register 1
0x000E DFB0 - 0x000E DFB34 byte
0x000E DFB4 - 0x000E DFB74 byte
0x000E DFB8 - 0x000E DFB92 byte
0x000E DFBC - 0x000E DFBF4 byte
ST10
bus size
16-bit
(X-BUS)
4.2.3 Low power mode
The Flash modules are automatically switched off executing PWRDN instruction. The
consumption is drastically reduced, but exiting this state can require a long time (t
Note:Recovery time from Power-down mode for the Flash modules is anyway shorter than the
main oscillator start-up time. To avoid any problem in restarting to fetch code from the Flash,
it is important to size properly the external circuit on RPD pin.
PD
).
Power-off Flash mode is entered only at the end of the eventually running Flash write
operation.
4.3 Write operation
The Flash modules have one single register interface mapped in the memory space of the
XFlash module (0x0E 0000 to 0x0E 0013). All the operations are enabled through four 16-bit
control registers: Flash Control Register 1-0 High/Low (FCR1H/L-FCR0H/L). Eight other 16bit registers are used to store Flash Address and Data for Program operations (FARH/L and
FDR1H/L-FDR0H/L) and Write Operation Error flags (FERH/L). All registers are accessible
with 8 and 16-bit instructions (since mapped on ST10 XBUS).
Note:Before accessing the XFlash module (and consequently also the Flash register to be used
for program/erasing operations), bit XFLASHEN in XPERCON register and bit XPEN in
SYSCON register shall be set.
The 4 Banks have their own dedicated sense amplifiers, so that any Bank can be read while
any other Bank is written. However simultaneous write operations (“write” means either
Program or Erase) on different Banks are forbidden: when there is a write operation on
going (Program or Erase) anywhere in the Flash, no other write operation can be performed.
During a Flash write operation any attempt to read the bank under modification will output
invalid data (software trap 009Bh). This means that the Flash Bank is not fetchable when a
write operation is active: the write operation commands must be executed from another
28/239
ST10F276Z5Internal Flash memory
Bank, or from the other module or again from another memory (internal RAM or external
memory).
Note:During a Write operation, when bit LOCK of FCR0 is set, it is forbidden to write into the
Flash Control Registers.
4.3.1 Power supply drop
If during a write operation the internal low voltage supply drops below a certain internal
voltage threshold, any write operation running is suddenly interrupted and the modules are
reset to Read mode. At following Power-on, an interrupted Flash write operation must be
repeated.
4.4 Registers description
4.4.1 Flash control register 0 low
The Flash control register 0 low (FCR0L) together with the Flash control register 0 high
(FCR0H) is used to enable and to monitor all the write operations for both the Flash
modules. The user has no access in write mode to the test-Flash (B0TF). Besides, testFlash block is seen by the user in Bootstrap mode only.
FCR0L (0x0E 0000)FCRReset value: 0000h
1514131211109876543210
reservedBSY1 BSY0 LOCK res. BSY3 BSY2 res.
RRRRR
Table 7.Flash control register 0 low
BitFunction
Bank 3:2 Busy (XFLASH)
These bits indicate that a write operation is running on the corresponding Bank of
XFLASH. They are automatically set when bit WMS is set. Setting Protection
operation sets bit BSY2 (since protection registers are in the Block B2). When these
BSY(3:2)
bits are set every read access to the corresponding Bank will output invalid data
(software trap 009Bh), while every write access to the Bank will be ignored. At the end
of the write operation or during a Program or Erase Suspend these bits are
automatically reset and the Bank returns to read mode. After a Program or Erase
Resume these bits are automatically set again.
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Internal Flash memoryST10F276Z5
Table 7.Flash control register 0 low (continued)
BitFunction
Flash registers access locked
When this bit is set, it means that the access to the Flash Control Registers FCR0H/-
FCR1H/L, FDR0H/L-FDR1H/L, FARH/L and FER is locked by the FPEC: any read
access to the registers will output invalid data (software trap 009Bh) and any write
LOCK
BSY(1:0)
access will be ineffective. LOCK bit is automatically set when the Flash bit WMS is set.
This is the only bit the user can always access to detect the status of the Flash: once it
is found low, the rest of FCR0L and all the other Flash registers are accessible by the
user as well.
Note that FER content can be read when LOCK is low, but its content is updated only
when also BSY bits are reset.
Bank 1:0 Busy (IFLASH)
These bits indicate that a write operation is running in the corresponding Bank of
IFLASH. They are automatically set when bit WMS is set. When these bits are set
every read access to the corresponding Bank will output invalid data (software trap
009Bh), while every write access to the Bank will be ignored. At the end of the write
operation or during a Program or Erase Suspend these bits are automatically reset
and the Bank returns to read mode. After a Program or Erase Resume these bits are
automatically set again.
4.4.2 Flash control register 0 high
The Flash control register 0 high (FCR0H) together with the Flash control register 0 Low
(FCR0L) is used to enable and to monitor all the write operations for both the Flash
modules. The user has no access in write mode to the Test-Flash (B0TF). Besides, testFlash block is seen by the user in Bootstrap mode only.
FCR0H (0x0E 0002)FCRReset value: 0000h
1514131211109876543210
WMS SUSP WPG DWPG SERReservedSPR SMODReserved
RWRWRWRWRWRWRW
Table 8.Flash control register 0 high
BitFunction
Select module
SMOD
SPR
If this bit is reset, the Write Operation is performed on XFLASH Module; if this bit is
set, the Write Operation is performed on IFLASH Module. SMOD bit is automatically
reset at the end of the Write operation.
Set protection
This bit must be set to select the Set Protection operation. The Set Protection
operation allows to program 0s in place of 1s in the Flash Non Volatile Protection
Registers. The Flash Address in which to program must be written in the FARH/L
registers, while the Flash Data to be programmed must be written in the FDR0H/L
before starting the execution by setting bit WMS. A sequence error is flagged by bit
SEQER of FER if the address written in FARH/L is not in the range 0x0EDFB00x0EDFBF. SPR bit is automatically reset at the end of the Set Protection operation.
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