ST ST10F276E User Manual

832 Kbyte Flash memory and 68 Kbyte RAM

Features

■ Highly performance 16-bit CPU with DSP

functions – 31.25ns instruction cycle time at 64MHz

max CPU clock

– Multiply/accumulate unit (MAC) 16 x 16-bit

multiplication, 40-bit accumulator – Enhanced boolean bit manipulations – Single-cycle context switching support

■ On-chip memories

– 512 Kbyte Flash memory (32-bit fetch) – 320 Kbyte extension Flash memory (16-bit

fetch) – Single voltage Flash memories with

erase/program controller and 100K

erasing/programming cycles – Up to 16 Mbyte linear address space for

code and data (5 Mbytes with CAN or I – 2 Kbyte internal RAM (IRAM) – 66 Kbyte extension RAM (XRAM)

■ External bus

– Programmable external bus configuration &

characteristics for different address ranges – 5 programmable chip-select signals – Hold-acknowledge bus arbitration support

■ Interrupt

– 8-channel peripheral event controller for

single cycle interrupt driven data transfer – 16-priority-level interrupt system with 56

sources, sampling rate down to 15.6ns

■ Timers

– 2 multi-functional general purpose timer

units with 5 timers

■ Two 16-channel capture / compare units

ST10F276E

16-bit MCU with MAC unit,

LQFP144 (20 x 20 x 1.4mm)

PQFP144 (28 x 28 x 3.4mm)

(Plastic quad flat package)

■ 4-channel PWM unit + 4-channel XPWM

■ A/D converter

– 24-channel 10-bit – 3 µs minimum conversion time

■ Serial channels

– 2 synch. / asynch. serial channels – 2 high-speed synchronous channels

–1 I

C standard interface

■ 2 CAN 2.0B interfaces operating on 1 or 2 CAN

busses (64 or 2x32 message, C-CAN version)

■ Fail-safe protection

– Programmable watchdog timer – Oscillator watchdog

■ On-chip bootstrap loader

■ Clock generation

– On-chip PLL with 4 to 12 MHz oscillator – Direct or prescaled clock input

■ Real-time clock and 32 kHz on-chip oscillator

■ Up to 111 general purpose I/O lines

– Individually programmable as input, output

or special function

– Programmable threshold (hysteresis)

■ Idle, power down and stand-by modes

■ Single voltage supply: 5V ±10% (embedded

regulator for 1.8 V core supply)

(Low profile plastic quad

flat package)

August 2008 Rev 2 1/231

www.st.com

Contents ST10F276E

Contents

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2 Pin data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4 Internal Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.2 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.2.1 Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.2.2 Modules structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.2.3 Low power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

4.2.4 Write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

4.2.5 Power supply drop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

4.3 Registers description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

4.3.1 Flash control register 0 low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

4.3.2 Flash control register 0 high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

4.3.3 Flash control register 1 low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

4.3.4 Flash control register 1 high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

4.3.5 Flash data register 0 low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

4.3.6 Flash data register 0 high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

4.3.7 Flash data register 1 low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

4.3.8 Flash data register 1 high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

4.3.9 Flash address register low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

4.3.10 Flash address register high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

4.3.11 Flash error register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

4.3.12 XFlash interface control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

4.4 Protection strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

4.4.1 Protection registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

4.4.2 Flash non-volatile write protection X register low . . . . . . . . . . . . . . . . . . 37

4.4.3 Flash non-volatile write protection X register high . . . . . . . . . . . . . . . . . 38

4.4.4 Flash non-volatile write protection I register low . . . . . . . . . . . . . . . . . . 38

4.4.5 Flash non-volatile write protection I register high . . . . . . . . . . . . . . . . . 38

4.4.6 Flash non-volatile access protection register 0 . . . . . . . . . . . . . . . . . . . 39

2/231

ST10F276E Contents

4.4.7 Flash non-volatile access protection register 1 low . . . . . . . . . . . . . . . . 39

4.4.8 Flash non-volatile access protection register 1 high . . . . . . . . . . . . . . . 40

4.4.9 Access protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

4.4.10 Write protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

4.4.11 Temporary unprotection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

4.5 Write operation examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

4.6 Write operation summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

5 Bootstrap loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

5.1 Selection among user-code, standard or alternate bootstrap . . . . . . . . . 46

5.2 Standard bootstrap loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

5.2.1 Entering the standard bootstrap loader . . . . . . . . . . . . . . . . . . . . . . . . . 47

5.2.2 ST10 configuration in BSL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

5.2.3 Booting steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

5.2.4 Hardware to activate BSL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

5.2.5 Memory configuration in bootstrap loader mode . . . . . . . . . . . . . . . . . . 51

5.2.6 Loading the start-up code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

5.2.7 Exiting bootstrap loader mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

5.2.8 Hardware requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

5.3 Standard bootstrap with UART (RS232 or K-Line) . . . . . . . . . . . . . . . . . . 53

5.3.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

5.3.2 Entering bootstrap via UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

5.3.3 ST10 Configuration in UART BSL (RS232 or K-Line) . . . . . . . . . . . . . . 55

5.3.4 Loading the start-up code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

5.3.5 Choosing the baud rate for the BSL via UART . . . . . . . . . . . . . . . . . . . 56

5.4 Standard bootstrap with CAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

5.4.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

5.4.2 Entering the CAN bootstrap loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

5.4.3 ST10 configuration in CAN BSL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

5.4.4 Loading the start-up code via CAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

5.4.5 Choosing the baud rate for the BSL via CAN . . . . . . . . . . . . . . . . . . . . 61

5.4.6 Computing the baud rate error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

5.4.7 Bootstrap via CAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

5.5 Comparing the old and the new bootstrap loader . . . . . . . . . . . . . . . . . . 65

5.5.1 Software aspects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

5.5.2 Hardware aspects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

3/231

Contents ST10F276E

5.6 Alternate boot mode (ABM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

5.6.1 Activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

5.6.2 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

5.6.3 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

5.6.4 ST10 configuration in alternate boot mode . . . . . . . . . . . . . . . . . . . . . . 66

5.6.5 Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

5.6.6 Exiting alternate boot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

5.6.7 Alternate boot user software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

5.6.8 User/alternate mode signature integrity check . . . . . . . . . . . . . . . . . . . 67

5.6.9 Alternate boot user software aspects . . . . . . . . . . . . . . . . . . . . . . . . . . 68

5.6.10 EMUCON register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

5.6.11 Internal decoding of test modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

5.6.12 Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

5.7 Selective boot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

6 Central processing unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

6.1 Multiplier-accumulator unit (MAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

6.2 Instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

6.3 MAC coprocessor specific instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

7 External bus controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

8 Interrupt system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

8.1 X-Peripheral interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

8.2 Exception and error traps list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

9 Capture / compare (CAPCOM) units . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

10 General purpose timer unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

10.1 GPT1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

10.2 GPT2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

11 PWM modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

12 Parallel ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

12.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

12.2 I/O’s special features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

4/231

ST10F276E Contents

12.2.1 Open drain mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

12.2.2 Input threshold control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

12.3 Alternate port functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

13 A/D converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

14 Serial channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

14.1 Asynchronous / synchronous serial interfaces . . . . . . . . . . . . . . . . . . . . . 94

14.2 ASCx in asynchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

14.3 ASCx in synchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

14.4 High speed synchronous serial interfaces . . . . . . . . . . . . . . . . . . . . . . . . 96

15 I2C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

16 CAN modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

16.1 Configuration support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

16.2 CAN bus configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

17 Real-time clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

18 Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

19 System reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

19.1 Input filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

19.2 Asynchronous reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

19.3 Synchronous reset (warm reset) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

19.4 Software reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

19.5 Watchdog timer reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

19.6 Bidirectional reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

19.7 Reset circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

19.8 Reset application examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

19.9 Reset summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

20 Power reduction modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

20.1 Idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

20.2 Power down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

5/231

Contents ST10F276E

20.2.1 Protected power down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

20.2.2 Interruptible power down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

20.3 Stand-by mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

20.3.1 Entering stand-by mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

20.3.2 Exiting stand-by mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

20.3.3 Real-time clock and stand-by mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

20.3.4 Power reduction modes summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

21 Programmable output clock divider . . . . . . . . . . . . . . . . . . . . . . . . . . 134

22 Register set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

22.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

22.2 Register description format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

22.3 General purpose registers (GPRs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

22.4 Special function registers ordered by name . . . . . . . . . . . . . . . . . . . . . 138

22.5 Special function registers ordered by address . . . . . . . . . . . . . . . . . . . . 145

22.6 X-registers sorted by name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

22.7 X-registers ordered by address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

22.8 Flash registers ordered by name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

22.9 Flash registers ordered by address . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

22.10 Identification registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

22.11 System configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

22.12 XPERCON and XPEREMU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

22.13 Emulation dedicated registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

23 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

23.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

23.2 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

23.3 Power considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

23.4 Parameter interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

23.5 DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

23.6 Flash characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

23.7 A/D converter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

23.7.1 Conversion timing control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

23.7.2 A/D conversion accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186

6/231

ST10F276E Contents

23.7.3 Total unadjusted error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

23.7.4 Analog reference pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188

23.7.5 Analog input pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188

23.7.6 Example of external network sizing . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

23.8 AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193

23.8.1 Test waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193

23.8.2 Definition of internal timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194

23.8.3 Clock generation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

23.8.4 Prescaler operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

23.8.5 Direct drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

23.8.6 Oscillator watchdog (OWD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

23.8.7 Phase locked loop (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

23.8.8 Voltage controlled oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197

23.8.9 PLL Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198

23.8.10 Jitter in the input clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198

23.8.11 Noise in the PLL loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198

23.8.12 PLL lock/unlock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200

23.8.13 Main oscillator specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200

23.8.14 32 kHz oscillator specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201

23.8.15 External clock drive XTAL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202

23.8.16 Memory cycle variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203

23.8.17 External memory bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204

23.8.18 Multiplexed bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204

23.8.19 Demultiplexed bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210

23.8.20 CLKOUT and READY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216

23.8.21 External bus arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218

23.8.22 High-speed synchronous serial interface (SSC) timing modes . . . . . . 220

24 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224

24.1 ECOPACK® . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224

25 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228

26 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229

7/231

List of tables ST10F276E

List of tables

Table 1. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 2. Flash modules absolute mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 3. Flash modules sectorization (read operations). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 4. Flash modules sectorization (write operations or with ROMS1 = ‘1’) . . . . . . . . . . . . . . . . . 26

Table 5. Control register interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 6. Flash control register 0 low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 7. Flash control register 0 high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 8. Flash control register 1 low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 9. Flash control register 1 high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 10. Banks (BxS) and sectors (BxFy) status bits meaning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 11. Flash data register 0 low. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 12. Flash data register 0 high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 13. Flash data register 1 low. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 14. Flash data register 1 high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 15. Flash address register low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 16. Flash address register high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 17. Flash error register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 18. XFlash interface control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 19. Flash non-volatile write protection X register low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 20. Flash non-volatile write protection X register high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 21. Flash non-volatile write protection I register low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 22. Flash non-volatile write protection I register high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 23. Flash non-volatile access protection register 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 24. Flash non-volatile access protection register 1 low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 25. Flash non-volatile access protection register 1 high. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 26. Summary of access protection level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 27. Flash write operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Table 28. ST10F276E boot mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Table 29. ST10 configuration in BSL mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Table 30. ST10 configuration in UART BSL mode (RS232 or K-line). . . . . . . . . . . . . . . . . . . . . . . . . 55

Table 31. ST10 configuration in CAN BSL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Table 32. BRP and PT0 values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Table 33. Software topics summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Table 34. Hardware topics summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Table 35. ST10 configuration in alternate boot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Table 36. ABM bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Table 37. Selective boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Table 38. Standard instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Table 39. MAC instruction set summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Table 40. Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Table 41. X-Interrupt detailed mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Table 42. Trap priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Table 43. Compare modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Table 44. CAPCOM timer input frequencies, resolutions and periods at 40 MHz . . . . . . . . . . . . . . . 83

Table 45. CAPCOM timer input frequencies, resolutions and periods at 64 MHz . . . . . . . . . . . . . . . 83

Table 46. GPT1 timer input frequencies, resolutions and periods at 40 MHz. . . . . . . . . . . . . . . . . . . 84

Table 47. GPT1 timer input frequencies, resolutions and periods at 64 MHz. . . . . . . . . . . . . . . . . . . 85

Table 48. GPT2 timer input frequencies, resolutions and periods at 40 MHz. . . . . . . . . . . . . . . . . . . 86

8/231

ST10F276E List of tables

Table 49. GPT2 timer input frequencies, resolutions and periods at 64 MHz. . . . . . . . . . . . . . . . . . . 86

Table 50. PWM unit frequencies and resolutions at 40 MHz CPU clock . . . . . . . . . . . . . . . . . . . . . . 88

Table 51. PWM unit frequencies and resolutions at 64 MHz CPU clock . . . . . . . . . . . . . . . . . . . . . . 88

Table 52. ASC asynchronous baud rates by reload value and deviation errors (fCPU = 40 MHz) . . 94 Table 53. ASC asynchronous baud rates by reload value and deviation errors (fCPU = 64 MHz) . . 95 Table 54. ASC synchronous baud rates by reload value and deviation errors (fCPU = 40 MHz) . . . 95 Table 55. ASC synchronous baud rates by reload value and deviation errors (fCPU = 64 MHz) . . . 96

Table 56. Synchronous baud rate and reload values (fCPU = 40 MHz). . . . . . . . . . . . . . . . . . . . . . . 97

Table 57. Synchronous baud rate and reload values (fCPU = 64 MHz). . . . . . . . . . . . . . . . . . . . . . . 97

Table 58. WDTREL reload value (fCPU = 40 MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Table 59. WDTREL reload value (fCPU = 64 MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Table 60. Reset event definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Table 61. Reset event. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

Table 62. PORT0 latched configuration for the different reset events . . . . . . . . . . . . . . . . . . . . . . . 127

Table 63. Power reduction modes summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

Table 64. Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

Table 65. General purpose registers (GPRs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

Table 66. General purpose registers (GPRs) bytewise addressing . . . . . . . . . . . . . . . . . . . . . . . . . 136

Table 67. Special function registers ordered by address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

Table 68. Special function registers ordered by address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

Table 69. X-Registers ordered by name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

Table 70. X-registers ordered by address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

Table 71. Flash registers ordered by name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

Table 72. Flash registers ordered by address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

Table 73. MANUF description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

Table 74. IDCHIP description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

Table 75. IDMEM description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

Table 76. IDPROG description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

Table 77. SYSCON description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

Table 78. BUSCON4 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

Table 79. RPOH description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

Table 80. EXIxES bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

Table 81. EXISEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

Table 82. EXIxSS and port 2 pin configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

Table 83. SFR area description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

Table 84. ESFR description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

Table 85. Segment 8 address range mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

Table 86. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

Table 87. Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

Table 88. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

Table 89. Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

Table 90. DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

Table 91. Flash characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

Table 92. Data retention characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

Table 93. A/D converter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

Table 94. A/D converter programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

Table 95. On-chip clock generator selections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

Table 96. Internal PLL divider mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197

Table 97. PLL lock/unlock timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200

Table 98. Main oscillator specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200

Table 99. Negative resistance (absolute min. value @125oC / VDD = 4.5V). . . . . . . . . . . . . . . . . . 201

Table 100. 32 kHz Oscillator specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201

9/231

List of tables ST10F276E

Table 101. Minimum values of negative resistance (module). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202

Table 102. External clock drive timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203

Table 103. Memory cycle variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203

Table 104. Multiplexed bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204

Table 105. Demultiplexed bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210

Table 106. CLKOUT and READY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216

Table 107. External bus arbitration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218

Table 108. Master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220

Table 109. Slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222

Table 110. Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228

Table 111. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229

10/231

ST10F276E List of figures

List of figures

Figure 1. Logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 2. Pin configuration (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 3. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 4. Flash modules structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 5. ST10F276E new standard bootstrap loader program flow . . . . . . . . . . . . . . . . . . . . . . . . . 49

Figure 6. Booting steps for ST10F276E. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Figure 7. Hardware provisions to activate the BSL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Figure 8. Memory configuration after reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Figure 9. UART bootstrap loader sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Figure 10. Baud rate deviation between host and ST10F276E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Figure 11. CAN bootstrap loader sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Figure 12. Bit rate measurement over a predefined zero-frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Figure 13. Reset boot sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Figure 14. CPU Block Diagram (MAC Unit not included). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Figure 15. MAC unit architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Figure 16. X-Interrupt basic structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Figure 17. Block diagram of GPT1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Figure 18. Block diagram of GPT2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Figure 19. Block diagram of PWM module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Figure 20. Connection to single CAN bus via separate CAN transceivers . . . . . . . . . . . . . . . . . . . . 100

Figure 21. Connection to single CAN bus via common CAN transceivers. . . . . . . . . . . . . . . . . . . . . 100

Figure 22. Connection to two different CAN buses (e.g. for gateway application). . . . . . . . . . . . . . . 101

Figure 23. Connection to one CAN bus with internal Parallel Mode enabled . . . . . . . . . . . . . . . . . . 101

Figure 24. Asynchronous power-on RESET (EA = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Figure 25. Asynchronous power-on RESET (EA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Figure 26. Asynchronous hardware RESET (EA = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Figure 27. Asynchronous hardware RESET (EA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

Figure 28. Synchronous short / long hardware RESET (EA = 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

Figure 29. Synchronous short / long hardware RESET (EA = 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Figure 30. Synchronous long hardware RESET (EA = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

Figure 31. Synchronous long hardware RESET (EA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Figure 32. SW / WDT unidirectional RESET (EA = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Figure 33. SW / WDT unidirectional RESET (EA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Figure 34. SW / WDT bidirectional RESET (EA = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Figure 35. SW / WDT bidirectional RESET (EA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

Figure 36. SW / WDT bidirectional RESET (EA = 0) followed by a HW RESET . . . . . . . . . . . . . . . . 121

Figure 37. Minimum external reset circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Figure 38. System reset circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

Figure 39. Internal (simplified) reset circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

Figure 40. Example of software or watchdog bidirectional reset (EA = 1) . . . . . . . . . . . . . . . . . . . . . 124

Figure 41. Example of software or watchdog bidirectional reset (EA = 0) . . . . . . . . . . . . . . . . . . . . . 125

Figure 42. PORT0 bits latched into the different registers after reset . . . . . . . . . . . . . . . . . . . . . . . . 128

Figure 43. External RC circuitry on RPD pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

Figure 44. Port2 test mode structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

Figure 45. Supply current versus the operating frequency (RUN and IDLE modes) . . . . . . . . . . . . . 181

Figure 46. A/D conversion characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

Figure 47. A/D converter input pins scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188

Figure 48. Charge sharing timing diagram during sampling phase . . . . . . . . . . . . . . . . . . . . . . . . . . 189

11/231

List of figures ST10F276E

Figure 49. Anti-aliasing filter and conversion rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191

Figure 50. Input/output waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193

Figure 51. Float waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193

Figure 52. Generation mechanisms for the CPU clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194

Figure 53. ST10F276E PLL jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199

Figure 54. Crystal oscillator and resonator connection diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201

Figure 55. 32 kHz crystal oscillator connection diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202

Figure 56. External clock drive XTAL1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203

Figure 57. Multiplexed bus with/without R/W delay and normal ALE. . . . . . . . . . . . . . . . . . . . . . . . . 206

Figure 58. Multiplexed bus with/without R/W delay and extended ALE . . . . . . . . . . . . . . . . . . . . . . . 207

Figure 59. Multiplexed bus, with/without R/W delay, normal ALE, R/W CS. . . . . . . . . . . . . . . . . . . . 208

Figure 60. Multiplexed bus, with/without R/ W delay, extended ALE, R/W CS . . . . . . . . . . . . . . . . . 209

Figure 61. Demultiplexed bus, with/without read/write delay and normal ALE . . . . . . . . . . . . . . . . . 212

Figure 62. Demultiplexed bus with/without R/W delay and extended ALE . . . . . . . . . . . . . . . . . . . . 213

Figure 63. Demultiplexed bus with ALE and R/W CS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214

Figure 64. Demultiplexed bus, no R/W delay, extended ALE, R/W CS . . . . . . . . . . . . . . . . . . . . . . . 215

Figure 65. CLKOUT and READY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217

Figure 66. External bus arbitration (releasing the bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218

Figure 67. External bus arbitration (regaining the bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219

Figure 68. SSC master timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221

Figure 69. SSC slave timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223

Figure 70. PQFP144 mechanical data and package dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225

Figure 71. LQFP144 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226

Figure 72. LQFP144 package dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227

12/231

ST10F276E Introduction

1 Introduction

The ST10F276E is a derivative of the STMicroelectronics ST10 family of 16-bit single-chip CMOS microcontrollers. It combines high CPU performance (up to 32 million instructions per second) with high peripheral functionality and enhanced I/O-capabilities. It also provides on-chip high-speed single voltage Flash memory, on-chip high-speed RAM, and clock generation via PLL.

ST10F276E is processed in 0.18µm CMOS technology. The MCU core and the logic is supplied with a 5V to 1.8V on-chip voltage regulator. The part is supplied with a single 5V supply and I/Os work at 5V.

The device is upward compatible with the ST10F269 device, with the following set of differences:

● Flash control interface is now based on STMicroelectronics third generation of stand-

alone Flash memories (M29F400 series), with an embedded Program/Erase Controller. This completely frees up the CPU during programming or erasing the Flash.

● Only one supply pin (ex DC1 in ST10F269, renamed into V

is used for decoupling the internally generated 1.8V core logic supply. Do not connect this pin to 5.0V external supply. Instead, this pin should be connected to a decoupling capacitor (ceramic type, typical value 10nF, maximum value 100nF).

● The AC and DC parameters are modified due to a difference in the maximum CPU

frequency.

● A new V

● EA pin assumes a new alternate functionality: it is also used to provide a dedicated

power supply (see V the main Power Supply of the device (V V

) is turned off for low power mode, allowing data retention. V

pin replaces DC2 of ST10F269.

) to maintain biased a portion of the XRAM (16 Kbytes) when

STBY

and consequently the internally generated

the range 4.5-5.5 Volt, and a dedicated embedded low power voltage regulator is in charge to provide the 1.8V for the RAM, the low-voltage section of the 32 kHz oscillator and the Real-Time Clock module when not disabled. It is allowed to exceed the upper limit up to 6V for a very short period of time during the global life of the device, and exceed the lower limit down to 4V when RTC and 32kHz on-chip oscillator are not used.

● A second SSC mapped on the XBUS is added (SSC of ST10F269 becomes here

SSC0, while the new one is referred as XSSC or simply SSC1). Note that some restrictions and functional differences due to the XBUS peculiarities are present between the classic SSC, and the new XSSC.

● A second ASC mapped on the XBUS is added (ASC0 of ST10F269 remains ASC0,

while the new one is referred as XASC or simply as ASC1). Note that some restrictions and functional differences due to the XBUS peculiarities are present between the classic ASC, and the new XASC.

● A second PWM mapped on the XBUS is added (PWM of ST10F269 becomes here

PWM0, while the new one is referred as XPWM or simply as PWM1). Note that some restrictions and functional differences due to the XBUS peculiarities are present between the classic PWM, and the new XPWM.

● An I

● CLKOUT function can output either the CPU clock (like in ST10F269) or a software

C interface on the XBUS is added (see X-I2C or simply I2C interface).

programmable prescaled value of the CPU clock.

) on the QFP144 package

voltage shall be in

STBY

13/231

Introduction ST10F276E

● Embedded memory size has been significantly increased (both Flash and RAM).

● PLL multiplication factors have been adapted to new frequency range.

A/D Converter is not fully compatible versus ST10F269 (timing and programming model). Formula for the conversion time is still valid, while the sampling phase programming model is different.

Besides, additional 8 channels are available on P1L pins as alternate function: the accuracy reachable with these extra channels is reduced with respect to the standard Port5 channels.

● External Memory bus potential limitations on maximum speed and maximum

capacitance load could be introduced (under evaluation): ST10F276E will probably not be able to address an external memory at 64MHz with 0 wait states (under evaluation).

● XPERCON register bit mapping modified according to new peripherals implementation

(not fully compatible with ST10F269).

● Bondout chip for emulation (ST10R201) cannot achieve more than 50MHz at room

temperature (so no real-time emulation possible at maximum speed).

● Input section characteristics are different. The threshold programmability is extended to

all port pins (additional XPICON register); it is possible to select standard TTL (with up to 500mV of hysteresis) and standard CMOS (with up to 800mV of hysteresis).

● Output transition is not programmable.

● CAN module is enhanced: ST10F276E implements two C-CAN modules, so the

programming model is slightly different. Besides, the possibility to map in parallel the two CAN modules is added (on P4.5/P4.6).

● On-chip main oscillator input frequency range has been reshaped, reducing it from 1-

25MHz down to 4-12MHz. This is a high performance oscillator amplifier, providing a very high negative resistance and wide oscillation amplitude: when this on-chip amplifier is used as reference for Real-Time Clock module, the Power-down consumption is dominated by the consumption of the oscillator amplifier itself. A metal option is added to offer a low power oscillator amplifier working in the range of 4-8MHz: this will allow a power consumption reduction when Real-Time Clock is running in Power Down mode using as reference the on-chip main oscillator clock.

● A second on-chip oscillator amplifier circuit (32kHz) is implemented for low power

modes: it can be used to provide the reference to the Real-Time Clock counter (either in Power Down or Stand-by mode). Pin XTAL3 and XTAL4 replace a couple of V

DD/VSS

pins of ST10F269.

● Possibility to re-program internal XBUS chip select window characteristics (XRAM2 and

XFLASH address window) is added.

14/231

ST10F276E Introduction

Figure 1. Logic symbol

DDVSS

XTAL1 XTAL2 XTAL3 XTAL4

RSTIN

RSTOUT

AREF

AGND

NMI

EA / V

STBY

READY

ALE

WR / WRL

Port 5

16-bit

ST10F276E

Port 0 16-bit

Port 1 16-bit

Port 2 16-bit

Port 3 15-bit

Port 4 8-bit

Port 6 8-bit

Port 7 8-bit

Port 8 8-bit

RPD

15/231

Pin data ST10F276E

2 Pin data

Figure 2. Pin configuration (top view)

(*)

RSTOUT

RSTIN

VSS

XTAL1

XTAL2

VDD

P1H.7 / A15 / CC27I

P1H.6 / A14 / CC26I

P1H.5 / A13 / CC25I

P1H.4 / A12 / CC24I

P1H.3 / A11

P1H.2 / A10

P1H.1 / A9

P1H.0 / A8

VSS

VDD

P1L.7 / A7 / AN23

P1L.6 / A6 / AN22

P1L.5 / A5 / AN21

P1L.4 / A4 / AN20

P1L.3 / A3 / AN19

P1L.2 / A2 / AN18

P1L.1 / A1 / AN17

P1L.0 / A0 / AN16

P0H.7 / AD15

P0H.6 / AD14

P0H.5 / AD13

P0H.4 / AD12

P0H.3 / AD11

P0H.2 / AD10

P0H.1 / AD9

VSS

P6.0 / CS0 P6.1 / CS1 P6.2 / CS2 P6.3 / CS3 P6.4 / CS4

P6.5 / HOLD / SCLK1

/ MTSR1

P6.6 / HLDA

P6.7 / BREQ P8.0 / XPOUT0 / CC16IO P8.1 / XPOUT1 / CC17IO P8.2 / XPOUT2 / CC18IO P8.3 / XPOUT3 / CC19IO

/ MRST1

P8.4 / CC20IO P8.5 / CC21IO

P8.6 / RxD1 / CC22IO

P8.7 / TxD1 / CC23IO

VDD

VSS P7.0 / POUT0 P7.1 / POUT1 P7.2 / POUT2 P7.3 / POUT3

P7.4 / CC28IO P7.5 / CC29IO P7.6 / CC30IO P7.7 / CC31IO

P5.0 / AN0 P5.1 / AN1 P5.2 / AN2 P5.3 / AN3 P5.4 / AN4 P5.5 / AN5 P5.6 / AN6 P5.7 / AN7 P5.8 / AN8 P5.9 / AN9

XTAL4

XTAL3

NMI

144

143

142

141

140

139

138

137

136

135

134

133

132

131

130

129

128

127

126

125

124

123

122

121

120

119

118

117

116

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

3738394041424344454647484950515253545556575859606162636465666768697071

ST10F276E

115

114

113

112

VDD

111

110

109 108

P0H.0 / AD8

107

P0L.7 / AD7

106

P0L.6 / AD6

105

P0L.5 / AD5

104

P0L.4 / AD4

103

P0L.3 / AD3

102

P0L.2 / AD2

101

P0L.1 / AD1

100

P0L.0 / AD0

/ VSTBY

ALE

READY

WR/WRL

VSS

VDD

P4.7 / A23 / CAN2_TxD / SDA

P4.6 / A22 / CAN1_TxD / CAN2_TxD

P4.5 / A21 / CAN1_RxD / CAN2_RxD

P4.4 / A20 / CAN2_RxD / SCL

P4.3 / A19

P4.2 / A18

P4.1 / A17

P4.0 / A16

RPD

VSS

VDD

P3.15 / CLKOUT

P3.13 / SCLK0

P3.12 / BHE

P3.11 / RxD0

P3.10 / TxD0

P3.9 / MTSR0

P3.8 / MRST0

P3.7 / T2IN

P3.6 / T3IN

/ WRH

VSS

P5.12 / AN12 / T6IN

P5.13 / AN13 / T5IN

P5.14 / AN14 / T4EUD

VDD

P2.0 / CC0IO

P2.1 / CC1IO

P2.2 / CC2IO

P2.3 / CC3IO

P5.15 / AN15 / T2EUD

VAREF

VAGND

P5.10 / AN10 / T6EUD

P5.11 / AN11 / T5EUD

V18

VSS

P2.11 / CC11IO / EX3IN

P2.12 / CC12IO / EX4IN

P2.13 / CC13IO / EX5IN

P3.0 / T0IN

P2.14 / CC14IO / EX6IN

P2.15 / CC15IO / EX7IN / T7IN

P2.4 / CC4IO

P2.5 / CC5IO

P2.6 / CC6IO

P2.7 / CC7IO

P2.8 / CC8IO / EX0IN

P2.9 / CC9IO / EX1IN

P2.10 / CC10IO / EX2IN

VSS

VDD

P3.5 / T4IN

P3.2 / CAPIN

P3.1 / T6OUT

P3.3 / T3OUT

P3.4 / T3EUD

16/231

ST10F276E Pin data

Table 1. Pin description

Symbol Pin Type Function

8-bit bidirectional I/O port, bit-wise programmable for input or output via direction bit. Programming an I/O pin as input forces the corresponding output driver to

P6.0 - P6.7

1 - 8 I/O

1OP6.0CS0

... ... ... ... ...

5OP6.4CS4 Chip select 4 output

high impedance state. Port 6 outputs can be configured as push-pull or open drain drivers. The input threshold of Port 6 is selectable (TTL or CMOS). The following Port 6 pins have alternate functions:

Chip select 0 output

IP6.5HOLD

External master hold request input

I/O SCLK1 SSC1: master clock output / slave clock input

O P6.6 HLDA

Hold acknowledge output

I/O MTSR1 SSC1: master-transmitter / slave-receiver O/I

P8.0 - P8.7

OP6.7 BREQ Bus request output

I/O MRST1 SSC1: master-receiver / slave-transmitter I/O

8-bit bidirectional I/O port, bit-wise programmable for input or output via direction bit. Programming an I/O pin as input forces the corresponding output driver to

9-16 I/O

high impedance state. Port 8 outputs can be configured as push-pull or open drain drivers. The input threshold of Port 8 is selectable (TTL or CMOS). The following Port 8 pins have alternate functions:

I/O P8.0 CC16IO CAPCOM2: CC16 capture input / compare output

O XPWM0 PWM1: channel 0 output

... ... ... ... ...

I/O P8.3 CC19IO CAPCOM2: CC19 capture input / compare output

O XPWM0 PWM1: channel 3 output

13 I/O P8.4 CC20IO CAPCOM2: CC20 capture input / compare output

14 I/O P8.5 CC21IO CAPCOM2: CC21 capture input / compare output

I/O P8.6 CC22IO CAPCOM2: CC22 capture input / compare output

I/O RxD1 ASC1: Data input (Asynchronous) or I/O (Synchronous)

I/O P8.7 CC23IO CAPCOM2: CC23 capture input / compare output

O TxD1 ASC1: Clock / Data output (Asynchronous/Synchronous)

17/231

Pin data ST10F276E

Table 1. Pin description (continued)

Symbol Pin Type Function

8-bit bidirectional I/O port, bit-wise programmable for input or output via direction bit. Programming an I/O pin as input forces the corresponding output driver to

P7.0 - P7.7

P5.0 - P5.9

P5.10 - P5.15

19-26 I/O

19 O P7.0 POUT0 PWM0: channel 0 output

... ... ... ... ...

22 O P7.3 POUT3 PWM0: channel 3 output

23 I/O P7.4 CC28IO CAPCOM2: CC28 capture input / compare output

... ... ... ... ...

26 I/O P7.7 CC31IO CAPCOM2: CC31 capture input / compare output

27-36 39-44

39 I P5.10 T6EUD GPT2: timer T6 external up/down control input

40 I P5.11 T5EUD GPT2: timer T5 external up/down control input

41 I P5.12 T6IN GPT2: timer T6 count input

42 I P5.13 T5IN GPT2: timer T5 count input

43 I P5.14 T4EUD GPT1: timer T4 external up/down control input

high impedance state. Port 7 outputs can be configured as push-pull or open drain drivers. The input threshold of Port 7 is selectable (TTL or CMOS). The following Port 7 pins have alternate functions:

16-bit input-only port with Schmitt-Trigger characteristics. The pins of Port 5 can be the analog input channels (up to 16) for the A/D converter, where P5.x equals

ANx (Analog input channel x), or they are timer inputs. The input threshold of

Port 5 is selectable (TTL or CMOS). The following Port 5 pins have alternate functions:

P2.0 - P2.7

P2.8 - P2.15

44 I P5.15 T2EUD GPT1: timer T2 external up/down control input

16-bit bidirectional I/O port, bit-wise programmable for input or output via

47-54 57-64

47 I/O P2.0 CC0IO CAPCOM: CC0 capture input/compare output

... ... ... ... ...

54 I/O P2.7 CC7IO CAPCOM: CC7 capture input/compare output

57 I/O P2.8 CC8IO CAPCOM: CC8 capture input/compare output

... ... ... ... ...

64 I/O P2.15 CC15IO CAPCOM: CC15 capture input/compare output

direction bit. Programming an I/O pin as input forces the corresponding output

I/O

driver to high impedance state. Port 2 outputs can be configured as push-pull or open drain drivers. The input threshold of Port 2 is selectable (TTL or CMOS). The following Port 2 pins have alternate functions:

I EX0IN Fast external interrupt 0 input

I EX7IN Fast external interrupt 7 input

I T7IN CAPCOM2: timer T7 count input

18/231

ST10F276E Pin data

Table 1. Pin description (continued)

Symbol Pin Type Function

15-bit (P3.14 is missing) bidirectional I/O port, bit-wise programmable for input or 65-70, 73-80,

65 I P3.0 T0IN CAPCOM1: timer T0 count input

66 O P3.1 T6OUT GPT2: timer T6 toggle latch output

67 I P3.2 CAPIN GPT2: register CAPREL capture input

68 O P3.3 T3OUT GPT1: timer T3 toggle latch output

69 I P3.4 T3EUD GPT1: timer T3 external up/down control input

I/O

output via direction bit. Programming an I/O pin as input forces the

I/O

corresponding output driver to high impedance state. Port 3 outputs can be

I/O

configured as push-pull or open drain drivers. The input threshold of Port 3 is

selectable (TTL or CMOS). The following Port 3 pins have alternate functions:

P3.0 - P3.5

P3.6 - P3.13,

P3.15

70 I P3.5 T4IN GPT1; timer T4 input for count/gate/reload/capture

73 I P3.6 T3IN GPT1: timer T3 count/gate input

74 I P3.7 T2IN GPT1: timer T2 input for count/gate/reload / capture

75 I/O P3.8 MRST0 SSC0: master-receiver/slave-transmitter I/O

76 I/O P3.9 MTSR0 SSC0: master-transmitter/slave-receiver O/I

77 O P3.10 TxD0 ASC0: clock / data output (asynchronous/synchronous)

78 I/O P3.11 RxD0 ASC0: data input (asynchronous) or I/O (synchronous)

79 O P3.12 BHE

WRH

80 I/O P3.13 SCLK0 SSC0: master clock output / slave clock input

81 O P3.15 CLKOUT

External memory high byte enable signal

External memory high byte write strobe

System clock output (programmable divider on CPU clock)

19/231

Pin data ST10F276E

Table 1. Pin description (continued)

Symbol Pin Type Function

Port 4 is an 8-bit bidirectional I/O port. It is bit-wise programmable for input or

output via direction bit. Programming an I/O pin as input forces the

corresponding output driver to high impedance state. The input threshold is

85-92 I/O

85 O P4.0 A16 Segment address line

86 O P4.1 A17 Segment address line

87 O P4.2 A18 Segment address line

88 O P4.3 A19 Segment address line

89 O P4.4 A20 Segment address line

P4.0 –P4.7

90 O P4.5 A21 Segment address line

91 O P4.6 A22 Segment address line

selectable (TTL or CMOS). Port 4.4, 4.5, 4.6 and 4.7 outputs can be configured

as push-pull or open drain drivers.

In case of an external bus configuration, Port 4 can be used to output the

segment address lines:

I CAN2_RxD CAN2: receive data input

I/O SCL

I2C Interface: serial clock

I CAN1_RxD CAN1: receive data input

I CAN2_RxD CAN2: receive data input

92 O P4.7 A23 Most significant segment address line

RD 95 O

/WRL 96 O

READY/

READY

97 I

ALE 98 O

O CAN1_TxD CAN1: transmit data output

O CAN2_TxD CAN2: transmit data output

I/O SDA

External memory read strobe. RD

I2C Interface: serial data

is activated for every external instruction or

data read access.

External memory write strobe. In WR

external data write access. In WRL

-mode this pin is activated for every

mode this pin is activated for low byte data write accesses on a 16-bit bus, and for every data write access on an 8-bit bus. See WRCFG in the SYSCON register for mode selection.

Ready input. The active level is programmable. When the ready function is enabled, the selected inactive level at this pin, during an external memory access, will force the insertion of waitstate cycles until the pin returns to the selected active level.

Address latch enable output. In case of use of external addressing or of multiplexed mode, this signal is the latch command of the address lines.

20/231

ST10F276E Pin data

Table 1. Pin description (continued)

Symbol Pin Type Function

External access enable pin. A low level applied to this pin during and after Reset forces the ST10F276E to

start the program from the external memory space. A high level forces ST10F276E to start in the internal memory space. This pin is also used (when

turned

EA / V

STBY

P0L.0 -P0L.7,

P0H.0

P0H.1 - P0H.7

99 I

100-107,

108,

111-117

Stand-by mode is entered, that is ST10F276E under reset and main V off) to bias the 32 kHz oscillator amplifier circuit and to provide a reference voltage for the low-power embedded voltage regulator which generates the internal 1.8V supply for the RTC module (when not disabled) and to retain data inside the Stand-by portion of the XRAM (16 Kbyte). It can range from 4.5 to 5.5V (6V for a reduced amount of time during the device life, 4.0V when RTC and 32 kHz on-chip oscillator amplifier are turned off). In running mode, this pin can be tied low during reset without affecting 32 kHz oscillator, RTC and XRAM activities, since the presence of a stable V guarantees the proper biasing of all those modules.

Two 8-bit bidirectional I/O ports P0L and P0H, bit-wise programmable for input or output via direction bit. Programming an I/O pin as input forces the corresponding output driver to high impedance state. The input threshold of Port 0 is selectable (TTL or CMOS). In case of an external bus configuration, PORT0 serves as the address (A) and as the address / data (AD) bus in multiplexed bus modes and as the data (D) bus in demultiplexed bus modes.

Demultiplexed bus modes

Data path width 8-bit 16-bi

I/O

P0L.0 – P0L.7: D0 – D7 D0 - D7

P0H.0 – P0H.7: I/O D8 - D15

P1L.0 - P1L.7

P1H.0 - P1H.7

Multiplexed bus modes

Data path width 8-bit 16-bi

P0L.0 – P0L.7: AD0 – AD7 AD0 - AD7

P0H.0 – P0H.7: A8 – A15 AD8 - AD15

Two 8-bit bidirectional I/O ports P1L and P1H, bit-wise programmable for input or output via direction bit. Programming an I/O pin as input forces the corresponding output driver to high impedance state. PORT1 is used as the 16bit address bus (A) in demultiplexed bus modes: if at least BUSCONx is

118-125 128-135

configured such the demultiplexed mode is selected, the pis of PORT1 are not available for general purpose I/O function. The input threshold of Port 1 is

I/O

selectable (TTL or CMOS). The pins of P1L also serve as the additional (up to 8) analog input channels for

the A/D converter, where P1L.x equals ANy (Analog input channel y, where y = x + 16). This additional function have higher priority on demultiplexed bus function. The following PORT1 pins have alternate functions:

132 I P1H.4 CC24IO CAPCOM2: CC24 capture input

133 I P1H.5 CC25IO CAPCOM2: CC25 capture input

134 I P1H.6 CC26IO CAPCOM2: CC26 capture input

135 I P1H.7 CC27IO CAPCOM2: CC27 capture input

21/231

Pin data ST10F276E

Table 1. Pin description (continued)

Symbol Pin Type Function

XTAL1 138 I XTAL1 Main oscillator amplifier circuit and/or external clock input.

XTAL2 137 O XTAL2 Main oscillator amplifier circuit output.

To clock the device from an external source, drive XTAL1 while leaving XTAL2 unconnected. Minimum and maximum high / low and rise / fall times specified in the AC Characteristics must be observed.

XTAL3 143 I XTAL3 32 kHz oscillator amplifier circuit input

XTAL4 144 O XTAL4 32 kHz oscillator amplifier circuit output

When 32 kHz oscillator amplifier is not used, to avoid spurious consumption, XTAL3 shall be tied to ground while XTAL4 shall be left open. Besides, bit OFF32 in RTCCON register shall be set. 32 kHz oscillator can only be driven by an external crystal, and not by a different clock source.

Reset Input with CMOS Schmitt-Trigger characteristics. A low level at this pin for a specified duration while the oscillator is running resets the ST10F276E. An

RSTIN

RSTOUT

NMI

140 I

141 O

142 I

internal pull-up resistor permits power-on reset using only a capacitor connected

. In bidirectional reset mode (enabled by setting bit BDRSTEN in

to V

SYSCON register), the RSTIN

line is pulled low for the duration of the internal

reset sequence.

Internal Reset Indication Output. This pin is driven to a low level during hardware, software or watchdog timer reset.

RSTOUT

remains low until the EINIT

(end of initialization) instruction is executed.

Non-Maskable Interrupt Input. A high to low transition at this pin causes the CPU to vector to the NMI trap routine. If bit PWDCFG = ‘0’ in SYSCON register, when the PWRDN (power down) instruction is executed, the NMI pin must be low in order to force the ST10F276E to go into power down mode. If NMI is high and PWDCFG = ‘0’, when PWRDN is executed, the part will continue to run in normal mode. If not used, pin NMI

should be pulled high externally.

AREF

AGND

RPD 84 -

37 - A/D converter reference voltage and analog supply

38 - A/D converter reference and analog ground

Timing pin for the return from interruptible power down mode and synchronous / asynchronous reset selection.

17, 46, 72,82,93, 109, 126,

136

Digital supply voltage = + 5V during normal operation, idle and power down

modes. It can be turned off when Stand-by RAM mode is selected.

18,45, 55,71,

83,94,

- Digital ground

110, 127,

139

56 -

1.8V decoupling pin: a decoupling capacitor (typical value of 10nF, max 100nF) must be connected between this pin and nearest V

22/231

pin.

ST10F276E Functional description

3 Functional description

The architecture of the ST10F276E combines advantages of both RISC and CISC processors and an advanced peripheral subsystem. The block diagram gives an overview of the different on-chip components and the high bandwidth internal bus structure of the ST10F276E.

Figure 3. Block diagram

XFLASH

16 16

IFLASH 512 KB

XPWM

XCAN2

Controller

External Bus

320 KB

XRAM

48 KB

XRAM

16 KB

(STBY)

XRAM

2 KB

(PEC)

XI2C

XCAN1

Por t 0Por t 1Po rt 4

Por t 6

81615 8 8

XRTC

XASC

XSSC

Por t 5

CPU-Core and MAC Unit

Interrupt Controller

10-bit ADC

GPT1 / GPT2

BRG BRG

Port 3 Port 7 Por t 8

ASC0

SSC0

PEC

PWM

CAPCOM2

IRAM

2 KB

Watchdog

Oscillator

32 kHz

Oscillator

PLL

5V-1.8V

Vol tag e

Regulator

CAPCOM1

Por t 2

23/231

Internal Flash memory ST10F276E

4 Internal Flash memory

4.1 Overview

The on-chip Flash is composed of two matrix modules, each one containing one array divided in two banks that can be read and modified independently of one another: one bank can be read while another bank is under modification.

Figure 4. Flash modules structure

IFLASH (Module I)

Bank 1: 128 Kbyte

program memory

Bank 0: 384 Kbyte

program memory

8 Kbyte test-Flash

I-BUS interface

The write operations of the four banks are managed by an embedded Flash program/erase controller (FPEC). The high voltages needed for program/erase operations are internally generated.

The data bus is 32-bit wide. Due to ST10 core architecture limitation, only the first 512 Kbytes are accessed at 32-bit (internal Flash bus, see I-BUS), while the remaining 320 Kbytes are accessed at 16-bit (see X-BUS).

4.2 Functional description

Control section

HV and Ref.

generator

Program/erase

controller

XFLASH (Module X)

Bank 3: 128 Kbyte

Bank 2: 192 Kbyte

X-BUS interface

program memory

4.2.1 Structure

Ta bl e 2 shows the address space reserved to the Flash module.

Table 2. Flash modules absolute mapping

Description Addresses Size

IFLASH sectors 0x00 0000 to 0x08 FFFF 512 Kbyte

XFLASH sectors 0x09 0000 to 0x0D FFFF 320 Kbyte

Registers and Flash internal reserved area 0x0E 0000 to 0x0E FFFF 64 Kbyte

4.2.2 Modules structure

The IFLASH module is composed of two banks. Bank 0 contains 384 Kbyte of program memory divided in 10 sectors. Bank 0 contains also a reserved sector named test-Flash.

24/231

ST10F276E Internal Flash memory

Bank 1 contains 128 Kbyte of program memory or parameter divided in two sectors (64 Kbyte each).

The XFLASH module is composed of two banks as well. Bank 2 contains 192 Kbyte of program memory divided in three sectors. Bank 3 contains 128 Kbyte of program memory or parameter divided in two sectors (64 Kbyte each).

Addresses from 0x0E 0000 to 0x0E FFFF are reserved for the control register interface and other internal service memory space used by the Flash program/erase controller.

The following tables show the memory mapping of the Flash when it is accessed in read mode (Ta bl e 3 ), and when accessed in write or erase mode (Ta bl e 2 ): note that with this second mapping, the first three banks are remapped into code segment 1 (same as obtained when setting bit ROMS1 in SYSCON register).

Table 3. Flash modules sectorization (read operations)

Bank Description Addresses Size

Bank 0 Flash 0 (B0F0) 0x0000 0000 - 0x0000 1FFF 8 KB

Bank 0 Flash 1 (B0F1) 0x0000 2000 - 0x0000 3FFF 8 KB

Bank 0 Flash 2 (B0F2) 0x0000 4000 - 0x0000 5FFF 8 KB

Bank 0 Flash 3 (B0F3) 0x0000 6000 - 0x0000 7FFF 8 KB

Bank 0 Flash 4 (B0F4) 0x0001 8000 - 0x0001 FFFF 32 KB

Bank 0 Flash 5 (B0F5) 0x0002 0000 - 0x0002 FFFF 64 KB

Bank 0 Flash 6 (B0F6) 0x0003 0000 - 0x0003 FFFF 64 KB

Bank 0 Flash 7 (B0F7) 0x0004 0000 - 0x0004 FFFF 64 KB

Bank 0 Flash 8 (B0F8) 0x0005 0000 - 0x0005 FFFF 64 KB

Bank 0 Flash 9 (B0F9) 0x0006 0000 - 0x0006 FFFF 64 KB

Bank 1 Flash 0 (B1F0) 0x0007 0000 - 0x0007 FFFF 64 KB

Bank 1 Flash 1 (B1F1) 0x0008 0000 - 0x0008 FFFF 64 KB

Bank 2 Flash 0 (B2F0) 0x0009 0000 - 0x0009 FFFF 64 KB

Bank 2 Flash 1 (B2F1) 0x000A 0000 - 0x000A FFFF 64 KB

Bank 2 Flash 2 (B2F2) 0x000B 0000 - 0x000B FFFF 64 KB

Bank 3 Flash 0 (B3F0) 0x000C 0000 - 0x000C FFFF 64 KB

Bank 3 Flash 1 (B3F1) 0x000D 0000 - 0x000D FFFF 64 KB

ST10 bus

size

32-bit (I-BUS)

16-bit

(X-BUS)

25/231

Internal Flash memory ST10F276E

Table 4. Flash modules sectorization (write operations or with ROMS1 = ‘1’)

Bank Description Addresses Size

Bank 0 Test-Flash (B0TF) 0x0000 0000 - 0x0000 1FFF 8 KB

Bank 0 Flash 0 (B0F0) 0x0001 0000 - 0x0001 1FFF 8 KB

Bank 0 Flash 1 (B0F1) 0x0001 2000 - 0x0001 3FFF 8 KB

Bank 0 Flash 2 (B0F2) 0x0001 4000 - 0x0001 5FFF 8 KB

Bank 0 Flash 3 (B0F3) 0x0001 6000 - 0x0001 7FFF 8 KB

Bank 0 Flash 4 (B0F4) 0x0001 8000 - 0x0001 FFFF 32 KB

Bank 0 Flash 5 (B0F5) 0x0002 0000 - 0x0002 FFFF 64 KB

Bank 0 Flash 6 (B0F6) 0x0003 0000 - 0x0003 FFFF 64 KB

Bank 0 Flash 7 (B0F7) 0x0004 0000 - 0x0004 FFFF 64 KB

Bank 0 Flash 8 (B0F8) 0x0005 0000 - 0x0005 FFFF 64 KB

Bank 0 Flash 9 (B0F9) 0x0006 0000 - 0x0006 FFFF 64 KB

Bank 1 Flash 0 (B1F0) 0x0007 0000 - 0x0007 FFFF 64 KB

Bank 1 Flash 1 (B1F1) 0x0008 0000 - 0x0008 FFFF 64 KB

Bank 2 Flash 0 (B2F0) 0x0009 0000 - 0x0009 FFFF 64 KB

Bank 2 Flash 1 (B2F1) 0x000A 0000 - 0x000A FFFF 64 KB

Bank 2 Flash 2 (B2F2) 0x000B 0000 - 0x000B FFFF 64 KB

Bank 3 Flash 0 (B3F0) 0x000C 0000 - 0x000C FFFF 64 KB

Bank 3 Flash 1 (B3F1) 0x000D 0000 - 0x000D FFFF 64 KB

ST10 Bus

size

32-bit (I-BUS)

16-bit

(X-BUS)

Ta bl e 4 above refers to the configuration when bit ROMS1 of SYSCON register is set. When

Bootstrap mode is entered:

● Test-Flash is seen and available for code fetches (address 00’0000h)

● User IFlash is only available for read and write accesses

● Write accesses must be made with addresses starting in segment 1 from 01'0000h,

whatever ROMS1 bit in SYSCON value

● Read accesses are made in segment 0 or in segment 1 depending of ROMS1 value.

In Bootstrap mode, by default ROMS1 = 0, so the first 32 Kbytes of IFlash are mapped in segment 0.

Example: In default configuration, to program address 0, user must put the value 01'0000h in the FARL and FARH registers, but to verify the content of the address 0 a read to 00'0000h must be performed.

Ta bl e 5 shows the control register interface composition: this set of registers can be

addressed by the CPU.

26/231

ST10F276E Internal Flash memory

Table 5. Control register interface

Bank Description Addresses Size

FCR1-0 Flash control registers 1-0 0x000E 0000 - 0x000E 0007 8 byte

FDR1-0 Flash data registers 1-0 0x000E 0008 - 0x000E 000F 8 byte

FAR Flash address registers 0x000E 0010 - 0x000E 0013 4 byte

FER Flash error register 0x000E 0014 - 0x000E 0015 2 byte

FNVWPXR

FNVWPIR

FNVAPR0

FNVAPR1

XFICR XFlash interface control register 0x000E E000 - 0x000E E001 2 byte

Flash non-volatile protection X register

Flash non-volatile protection I register

Flash non-volatile access protection register 0

Flash non-volatile access protection register 1

0x000E DFB0 - 0x000E DFB3 4 byte

0x000E DFB4 - 0x000E DFB7 4 byte

0x000E DFB8 - 0x000E DFB9 2 byte

0x000E DFBC - 0x000E DFBF 4 byte

ST10

bus size

16-bit

(X-BUS)

4.2.3 Low power mode

The Flash modules are automatically switched off executing PWRDN instruction. The consumption is drastically reduced, but exiting this state can require a long time (t

Note: Recovery time from Power Down mode for the Flash modules is anyway shorter than the

main oscillator start-up time. To avoid any problem in restarting to fetch code from the Flash, it is important to size properly the external circuit on RPD pin.

Power-off Flash mode is entered only at the end of the eventually running Flash write operation.

4.2.4 Write operation

The Flash modules have one single register interface mapped in the memory space of the XFlash module (0x0E 0000 to 0x0E 0013). All the operations are enabled through four 16-bit control registers: Flash Control Register 1-0 High/Low (FCR1H/L-FCR0H/L). Eight other 16bit registers are used to store Flash Address and Data for Program operations (FARH/L and FDR1H/L-FDR0H/L) and Write Operation Error flags (FERH/L). All registers are accessible with 8 and 16-bit instructions (since mapped on ST10 XBUS).

Note: Before accessing the XFlash module (and consequently also the Flash register to be used

for program/erasing operations), bit XFLASHEN in XPERCON register and bit XPEN in SYSCON register shall be set.

The four banks have their own dedicated sense amplifiers, so that any bank can be read while any other bank is written. However simultaneous write operations (“write” means either Program or Erase) on different banks are forbidden: when there is a write operation on going (Program or Erase) anywhere in the Flash, no other write operation can be performed.

During a Flash write operation any attempt to read the bank under modification will output invalid data (software trap 009Bh). This means that the Flash bank is not fetchable when a write operation is active: the write operation commands must be executed from another

27/231

Internal Flash memory ST10F276E

bank, or from the other module or again from another memory (internal RAM or external memory).

Note: During a Write operation, when bit LOCK of FCR0 is set, it is forbidden to write into the

Flash Control Registers.

4.2.5 Power supply drop

If during a write operation the internal low voltage supply drops below a certain internal voltage threshold, any write operation running is suddenly interrupted and the modules are reset to Read mode. At following Power-on, an interrupted Flash write operation must be repeated.

4.3 Registers description

4.3.1 Flash control register 0 low

The Flash control register 0 low (FCR0L) together with the Flash control register 0 high (FCR0H) is used to enable and to monitor all the write operations for both the Flash modules. The user has no access in write mode to the test-Flash (B0TF). Besides, testFlash block is seen by the user in Bootstrap mode only.

FCR0L (0x0E 0000) FCR Reset value: 0000h

1514131211109876543210

Reserved BSY1 BSY0 LOCK Res. BSY3 BSY2 Res.

RRR RR

Table 6. Flash control register 0 low

Bit Function

Bank 3:2 Busy (XFLASH) These bits indicate that a write operation is running on the corresponding bank of

XFLASH. They are automatically set when bit WMS is set. Setting Protection operation sets bit BSY2 (since protection registers are in the Block B2). When these

BSY(3:2)

bits are set every read access to the corresponding bank will output invalid data (software trap 009Bh), while every write access to the bank will be ignored. At the end of the write operation or during a Program or Erase Suspend these bits are automatically reset and the bank returns to read mode. After a Program or Erase Resume these bits are automatically set again.

28/231

ST10F276E Internal Flash memory

Table 6. Flash control register 0 low (continued)

Bit Function

Flash registers access locked When this bit is set, it means that the access to the Flash Control Registers FCR0H/-

FCR1H/L, FDR0H/L-FDR1H/L, FARH/L and FER is locked by the FPEC: any read access to the registers will output invalid data (software trap 009Bh) and any write

LOCK

BSY(1:0)

access will be ineffective. LOCK bit is automatically set when the Flash bit WMS is set. This is the only bit the user can always access to detect the status of the Flash: once it is found low, the rest of FCR0L and all the other Flash registers are accessible by the user as well. Note that FER content can be read when LOCK is low, but its content is updated only when also BSY bits are reset.

Bank 1:0 Busy (IFLASH) These bits indicate that a write operation is running in the corresponding bank of

IFLASH. They are automatically set when bit WMS is set. When these bits are set every read access to the corresponding bank will output invalid data (software trap 009Bh), while every write access to the bank will be ignored. At the end of the write operation or during a Program or Erase Suspend these bits are automatically reset and the bank returns to read mode. After a Program or Erase Resume these bits are automatically set again.

4.3.2 Flash control register 0 high

The Flash control register 0 high (FCR0H) together with the Flash control register 0 Low (FCR0L) is used to enable and to monitor all the write operations for both the Flash modules. The user has no access in write mode to the Test-Flash (B0TF). Besides, testFlash block is seen by the user in Bootstrap mode only.

FCR0H (0x0E 0002) FCR Reset value: 0000h

1514131211109876543210

WMS SUSP WPG DWPG SER Reserved SPR SMOD Reserved

RW RW RW RW RW RW RW

Table 7. Flash control register 0 high

Bit Function

Select module

SMOD

SPR

If this bit is reset, the Write Operation is performed on XFLASH Module; if this bit is set, the Write Operation is performed on IFLASH Module. SMOD bit is automatically reset at the end of the Write operation.

Set protection This bit must be set to select the Set Protection operation. The Set Protection

operation allows to program 0s in place of 1s in the Flash Non-volatile Protection Registers. The Flash Address in which to program must be written in the FARH/L registers, while the Flash Data to be programmed must be written in the FDR0H/L before starting the execution by setting bit WMS. A sequence error is flagged by bit SEQER of FER if the address written in FARH/L is not in the range 0x0EDFB00x0EDFBF. SPR bit is automatically reset at the end of the Set Protection operation.

29/231

Internal Flash memory ST10F276E

Table 7. Flash control register 0 high (continued)

Bit Function

Sector erase This bit must be set to select the Sector Erase operation in the Flash modules. The

Sector Erase operation allows to erase all the Flash locations to 0xFF. From 1 to all the

SER

DWPG

WPG

SUSP

WMS

sectors of the same bank (excluded Test-Flash for Bank B0) can be selected to be erased through bits BxFy of FCR1H/L registers before starting the execution by setting bit WMS. It is not necessary to pre-program the sectors to 0x00, because this is done automatically. SER bit is automatically reset at the end of the Sector Erase operation.

Double word program This bit must be set to select the Double Word (64 bits) Program operation in the Flash

modules. The Double Word Program operation allows to program 0s in place of 1s. The Flash Address in which to program (aligned with even words) must be written in the FARH/L registers, while the 2 Flash Data to be programmed must be written in the FDR0H/L registers (even word) and FDR1H/L registers (odd word) before starting the execution by setting bit WMS. DWPG bit is automatically reset at the end of the Double Word Program operation.

Word program This bit must be set to select the Word (32 bits) Program operation in the Flash

modules. The Word Program operation allows to program 0s in place of 1s. The Flash Address to be programmed must be written in the FARH/L registers, while the Flash Data to be programmed must be written in the FDR0H/L registers before starting the execution by setting bit WMS. WPG bit is automatically reset at the end of the Word Program operation.

Suspend This bit must be set to suspend the current Program (Word or Double Word) or Sector

Erase operation in order to read data in one of the sectors of the bank under modification or to program data in another bank. The Suspend operation resets the Flash bank to normal read mode (automatically resetting bits BSYx). When in Program Suspend, the two Flash modules accept only the following operations: Read and Program Resume. When in Erase Suspend the modules accept only the following operations: Read, Erase Resume and Program (Word or Double Word; Program operations cannot be suspended during Erase Suspend). To resume the suspended operation, the WMS bit must be set again, together with the selection bit corresponding to the operation to resume (WPG, DWPG, SER). Note: It is forbidden to start a new Write operation with bit SUSP already set.

Write mode start This bit must be set to start every write operation in the Flash modules. At the end of

the write operation or during a Suspend, this bit is automatically reset. To resume a suspended operation, this bit must be set again. It is forbidden to set this bit if bit ERR of FER is high (the operation is not accepted). It is also forbidden to start a new write (program or erase) operation (by setting WMS high) when bit SUSP of FCR0 is high. Resetting this bit by software has no effect.

30/231

+ 201 hidden pages