ST ST10F276E User Manual

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832 Kbyte Flash memory and 68 Kbyte RAM

Features

■ Highly performance 16-bit CPU with DSP

functions – 31.25ns instruction cycle time at 64MHz

max CPU clock

– Multiply/accumulate unit (MAC) 16 x 16-bit

multiplication, 40-bit accumulator – Enhanced boolean bit manipulations – Single-cycle context switching support

■ On-chip memories

– 512 Kbyte Flash memory (32-bit fetch) – 320 Kbyte extension Flash memory (16-bit

fetch) – Single voltage Flash memories with

erase/program controller and 100K

erasing/programming cycles – Up to 16 Mbyte linear address space for

code and data (5 Mbytes with CAN or I – 2 Kbyte internal RAM (IRAM) – 66 Kbyte extension RAM (XRAM)

■ External bus

– Programmable external bus configuration &

characteristics for different address ranges – 5 programmable chip-select signals – Hold-acknowledge bus arbitration support

■ Interrupt

– 8-channel peripheral event controller for

single cycle interrupt driven data transfer – 16-priority-level interrupt system with 56

sources, sampling rate down to 15.6ns

■ Timers

– 2 multi-functional general purpose timer

units with 5 timers

■ Two 16-channel capture / compare units

ST10F276E

16-bit MCU with MAC unit,

LQFP144 (20 x 20 x 1.4mm)

PQFP144 (28 x 28 x 3.4mm)

(Plastic quad flat package)

■ 4-channel PWM unit + 4-channel XPWM

■ A/D converter

– 24-channel 10-bit – 3 µs minimum conversion time

■ Serial channels

– 2 synch. / asynch. serial channels – 2 high-speed synchronous channels

–1 I

C standard interface

■ 2 CAN 2.0B interfaces operating on 1 or 2 CAN

busses (64 or 2x32 message, C-CAN version)

■ Fail-safe protection

– Programmable watchdog timer – Oscillator watchdog

■ On-chip bootstrap loader

■ Clock generation

– On-chip PLL with 4 to 12 MHz oscillator – Direct or prescaled clock input

■ Real-time clock and 32 kHz on-chip oscillator

■ Up to 111 general purpose I/O lines

– Individually programmable as input, output

or special function

– Programmable threshold (hysteresis)

■ Idle, power down and stand-by modes

■ Single voltage supply: 5V ±10% (embedded

regulator for 1.8 V core supply)

(Low profile plastic quad

flat package)

August 2008 Rev 2 1/231

www.st.com

Contents ST10F276E

Contents

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2 Pin data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4 Internal Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.2 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.2.1 Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.2.2 Modules structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.2.3 Low power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

4.2.4 Write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

4.2.5 Power supply drop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

4.3 Registers description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

4.3.1 Flash control register 0 low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

4.3.2 Flash control register 0 high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

4.3.3 Flash control register 1 low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

4.3.4 Flash control register 1 high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

4.3.5 Flash data register 0 low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

4.3.6 Flash data register 0 high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

4.3.7 Flash data register 1 low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

4.3.8 Flash data register 1 high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

4.3.9 Flash address register low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

4.3.10 Flash address register high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

4.3.11 Flash error register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

4.3.12 XFlash interface control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

4.4 Protection strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

4.4.1 Protection registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

4.4.2 Flash non-volatile write protection X register low . . . . . . . . . . . . . . . . . . 37

4.4.3 Flash non-volatile write protection X register high . . . . . . . . . . . . . . . . . 38

4.4.4 Flash non-volatile write protection I register low . . . . . . . . . . . . . . . . . . 38

4.4.5 Flash non-volatile write protection I register high . . . . . . . . . . . . . . . . . 38

4.4.6 Flash non-volatile access protection register 0 . . . . . . . . . . . . . . . . . . . 39

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4.4.7 Flash non-volatile access protection register 1 low . . . . . . . . . . . . . . . . 39

4.4.8 Flash non-volatile access protection register 1 high . . . . . . . . . . . . . . . 40

4.4.9 Access protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

4.4.10 Write protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

4.4.11 Temporary unprotection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

4.5 Write operation examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

4.6 Write operation summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

5 Bootstrap loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

5.1 Selection among user-code, standard or alternate bootstrap . . . . . . . . . 46

5.2 Standard bootstrap loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

5.2.1 Entering the standard bootstrap loader . . . . . . . . . . . . . . . . . . . . . . . . . 47

5.2.2 ST10 configuration in BSL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

5.2.3 Booting steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

5.2.4 Hardware to activate BSL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

5.2.5 Memory configuration in bootstrap loader mode . . . . . . . . . . . . . . . . . . 51

5.2.6 Loading the start-up code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

5.2.7 Exiting bootstrap loader mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

5.2.8 Hardware requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

5.3 Standard bootstrap with UART (RS232 or K-Line) . . . . . . . . . . . . . . . . . . 53

5.3.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

5.3.2 Entering bootstrap via UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

5.3.3 ST10 Configuration in UART BSL (RS232 or K-Line) . . . . . . . . . . . . . . 55

5.3.4 Loading the start-up code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

5.3.5 Choosing the baud rate for the BSL via UART . . . . . . . . . . . . . . . . . . . 56

5.4 Standard bootstrap with CAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

5.4.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

5.4.2 Entering the CAN bootstrap loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

5.4.3 ST10 configuration in CAN BSL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

5.4.4 Loading the start-up code via CAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

5.4.5 Choosing the baud rate for the BSL via CAN . . . . . . . . . . . . . . . . . . . . 61

5.4.6 Computing the baud rate error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

5.4.7 Bootstrap via CAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

5.5 Comparing the old and the new bootstrap loader . . . . . . . . . . . . . . . . . . 65

5.5.1 Software aspects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

5.5.2 Hardware aspects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

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5.6 Alternate boot mode (ABM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

5.6.1 Activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

5.6.2 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

5.6.3 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

5.6.4 ST10 configuration in alternate boot mode . . . . . . . . . . . . . . . . . . . . . . 66

5.6.5 Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

5.6.6 Exiting alternate boot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

5.6.7 Alternate boot user software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

5.6.8 User/alternate mode signature integrity check . . . . . . . . . . . . . . . . . . . 67

5.6.9 Alternate boot user software aspects . . . . . . . . . . . . . . . . . . . . . . . . . . 68

5.6.10 EMUCON register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

5.6.11 Internal decoding of test modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

5.6.12 Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

5.7 Selective boot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

6 Central processing unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

6.1 Multiplier-accumulator unit (MAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

6.2 Instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

6.3 MAC coprocessor specific instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

7 External bus controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

8 Interrupt system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

8.1 X-Peripheral interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

8.2 Exception and error traps list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

9 Capture / compare (CAPCOM) units . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

10 General purpose timer unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

10.1 GPT1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

10.2 GPT2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

11 PWM modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

12 Parallel ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

12.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

12.2 I/O’s special features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

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12.2.1 Open drain mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

12.2.2 Input threshold control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

12.3 Alternate port functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

13 A/D converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

14 Serial channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

14.1 Asynchronous / synchronous serial interfaces . . . . . . . . . . . . . . . . . . . . . 94

14.2 ASCx in asynchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

14.3 ASCx in synchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

14.4 High speed synchronous serial interfaces . . . . . . . . . . . . . . . . . . . . . . . . 96

15 I2C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

16 CAN modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

16.1 Configuration support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

16.2 CAN bus configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

17 Real-time clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

18 Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

19 System reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

19.1 Input filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

19.2 Asynchronous reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

19.3 Synchronous reset (warm reset) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

19.4 Software reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

19.5 Watchdog timer reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

19.6 Bidirectional reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

19.7 Reset circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

19.8 Reset application examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

19.9 Reset summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

20 Power reduction modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

20.1 Idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

20.2 Power down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

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20.2.1 Protected power down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

20.2.2 Interruptible power down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

20.3 Stand-by mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

20.3.1 Entering stand-by mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

20.3.2 Exiting stand-by mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

20.3.3 Real-time clock and stand-by mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

20.3.4 Power reduction modes summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

21 Programmable output clock divider . . . . . . . . . . . . . . . . . . . . . . . . . . 134

22 Register set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

22.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

22.2 Register description format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

22.3 General purpose registers (GPRs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

22.4 Special function registers ordered by name . . . . . . . . . . . . . . . . . . . . . 138

22.5 Special function registers ordered by address . . . . . . . . . . . . . . . . . . . . 145

22.6 X-registers sorted by name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

22.7 X-registers ordered by address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

22.8 Flash registers ordered by name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

22.9 Flash registers ordered by address . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

22.10 Identification registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

22.11 System configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

22.12 XPERCON and XPEREMU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

22.13 Emulation dedicated registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

23 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

23.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

23.2 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

23.3 Power considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

23.4 Parameter interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

23.5 DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

23.6 Flash characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

23.7 A/D converter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

23.7.1 Conversion timing control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

23.7.2 A/D conversion accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186

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23.7.3 Total unadjusted error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

23.7.4 Analog reference pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188

23.7.5 Analog input pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188

23.7.6 Example of external network sizing . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

23.8 AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193

23.8.1 Test waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193

23.8.2 Definition of internal timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194

23.8.3 Clock generation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

23.8.4 Prescaler operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

23.8.5 Direct drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

23.8.6 Oscillator watchdog (OWD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

23.8.7 Phase locked loop (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

23.8.8 Voltage controlled oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197

23.8.9 PLL Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198

23.8.10 Jitter in the input clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198

23.8.11 Noise in the PLL loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198

23.8.12 PLL lock/unlock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200

23.8.13 Main oscillator specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200

23.8.14 32 kHz oscillator specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201

23.8.15 External clock drive XTAL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202

23.8.16 Memory cycle variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203

23.8.17 External memory bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204

23.8.18 Multiplexed bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204

23.8.19 Demultiplexed bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210

23.8.20 CLKOUT and READY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216

23.8.21 External bus arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218

23.8.22 High-speed synchronous serial interface (SSC) timing modes . . . . . . 220

24 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224

24.1 ECOPACK® . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224

25 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228

26 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229

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List of tables

Table 1. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 2. Flash modules absolute mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 3. Flash modules sectorization (read operations). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 4. Flash modules sectorization (write operations or with ROMS1 = ‘1’) . . . . . . . . . . . . . . . . . 26

Table 5. Control register interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 6. Flash control register 0 low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 7. Flash control register 0 high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 8. Flash control register 1 low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 9. Flash control register 1 high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 10. Banks (BxS) and sectors (BxFy) status bits meaning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 11. Flash data register 0 low. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 12. Flash data register 0 high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 13. Flash data register 1 low. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 14. Flash data register 1 high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 15. Flash address register low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 16. Flash address register high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 17. Flash error register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 18. XFlash interface control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 19. Flash non-volatile write protection X register low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 20. Flash non-volatile write protection X register high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 21. Flash non-volatile write protection I register low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 22. Flash non-volatile write protection I register high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 23. Flash non-volatile access protection register 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 24. Flash non-volatile access protection register 1 low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 25. Flash non-volatile access protection register 1 high. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 26. Summary of access protection level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 27. Flash write operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Table 28. ST10F276E boot mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Table 29. ST10 configuration in BSL mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Table 30. ST10 configuration in UART BSL mode (RS232 or K-line). . . . . . . . . . . . . . . . . . . . . . . . . 55

Table 31. ST10 configuration in CAN BSL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Table 32. BRP and PT0 values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Table 33. Software topics summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Table 34. Hardware topics summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Table 35. ST10 configuration in alternate boot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Table 36. ABM bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Table 37. Selective boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Table 38. Standard instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Table 39. MAC instruction set summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Table 40. Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Table 41. X-Interrupt detailed mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Table 42. Trap priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Table 43. Compare modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Table 44. CAPCOM timer input frequencies, resolutions and periods at 40 MHz . . . . . . . . . . . . . . . 83

Table 45. CAPCOM timer input frequencies, resolutions and periods at 64 MHz . . . . . . . . . . . . . . . 83

Table 46. GPT1 timer input frequencies, resolutions and periods at 40 MHz. . . . . . . . . . . . . . . . . . . 84

Table 47. GPT1 timer input frequencies, resolutions and periods at 64 MHz. . . . . . . . . . . . . . . . . . . 85

Table 48. GPT2 timer input frequencies, resolutions and periods at 40 MHz. . . . . . . . . . . . . . . . . . . 86

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Table 49. GPT2 timer input frequencies, resolutions and periods at 64 MHz. . . . . . . . . . . . . . . . . . . 86

Table 50. PWM unit frequencies and resolutions at 40 MHz CPU clock . . . . . . . . . . . . . . . . . . . . . . 88

Table 51. PWM unit frequencies and resolutions at 64 MHz CPU clock . . . . . . . . . . . . . . . . . . . . . . 88

Table 52. ASC asynchronous baud rates by reload value and deviation errors (fCPU = 40 MHz) . . 94 Table 53. ASC asynchronous baud rates by reload value and deviation errors (fCPU = 64 MHz) . . 95 Table 54. ASC synchronous baud rates by reload value and deviation errors (fCPU = 40 MHz) . . . 95 Table 55. ASC synchronous baud rates by reload value and deviation errors (fCPU = 64 MHz) . . . 96

Table 56. Synchronous baud rate and reload values (fCPU = 40 MHz). . . . . . . . . . . . . . . . . . . . . . . 97

Table 57. Synchronous baud rate and reload values (fCPU = 64 MHz). . . . . . . . . . . . . . . . . . . . . . . 97

Table 58. WDTREL reload value (fCPU = 40 MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Table 59. WDTREL reload value (fCPU = 64 MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Table 60. Reset event definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Table 61. Reset event. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

Table 62. PORT0 latched configuration for the different reset events . . . . . . . . . . . . . . . . . . . . . . . 127

Table 63. Power reduction modes summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

Table 64. Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

Table 65. General purpose registers (GPRs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

Table 66. General purpose registers (GPRs) bytewise addressing . . . . . . . . . . . . . . . . . . . . . . . . . 136

Table 67. Special function registers ordered by address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

Table 68. Special function registers ordered by address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

Table 69. X-Registers ordered by name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

Table 70. X-registers ordered by address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

Table 71. Flash registers ordered by name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

Table 72. Flash registers ordered by address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

Table 73. MANUF description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

Table 74. IDCHIP description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

Table 75. IDMEM description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

Table 76. IDPROG description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

Table 77. SYSCON description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

Table 78. BUSCON4 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

Table 79. RPOH description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

Table 80. EXIxES bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

Table 81. EXISEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

Table 82. EXIxSS and port 2 pin configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

Table 83. SFR area description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

Table 84. ESFR description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

Table 85. Segment 8 address range mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

Table 86. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

Table 87. Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

Table 88. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

Table 89. Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

Table 90. DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

Table 91. Flash characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

Table 92. Data retention characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

Table 93. A/D converter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

Table 94. A/D converter programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

Table 95. On-chip clock generator selections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

Table 96. Internal PLL divider mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197

Table 97. PLL lock/unlock timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200

Table 98. Main oscillator specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200

Table 99. Negative resistance (absolute min. value @125oC / VDD = 4.5V). . . . . . . . . . . . . . . . . . 201

Table 100. 32 kHz Oscillator specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201

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Table 101. Minimum values of negative resistance (module). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202

Table 102. External clock drive timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203

Table 103. Memory cycle variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203

Table 104. Multiplexed bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204

Table 105. Demultiplexed bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210

Table 106. CLKOUT and READY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216

Table 107. External bus arbitration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218

Table 108. Master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220

Table 109. Slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222

Table 110. Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228

Table 111. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229

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ST10F276E List of figures

List of figures

Figure 1. Logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 2. Pin configuration (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 3. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 4. Flash modules structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 5. ST10F276E new standard bootstrap loader program flow . . . . . . . . . . . . . . . . . . . . . . . . . 49

Figure 6. Booting steps for ST10F276E. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Figure 7. Hardware provisions to activate the BSL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Figure 8. Memory configuration after reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Figure 9. UART bootstrap loader sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Figure 10. Baud rate deviation between host and ST10F276E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Figure 11. CAN bootstrap loader sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Figure 12. Bit rate measurement over a predefined zero-frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Figure 13. Reset boot sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Figure 14. CPU Block Diagram (MAC Unit not included). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Figure 15. MAC unit architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Figure 16. X-Interrupt basic structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Figure 17. Block diagram of GPT1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Figure 18. Block diagram of GPT2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Figure 19. Block diagram of PWM module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Figure 20. Connection to single CAN bus via separate CAN transceivers . . . . . . . . . . . . . . . . . . . . 100

Figure 21. Connection to single CAN bus via common CAN transceivers. . . . . . . . . . . . . . . . . . . . . 100

Figure 22. Connection to two different CAN buses (e.g. for gateway application). . . . . . . . . . . . . . . 101

Figure 23. Connection to one CAN bus with internal Parallel Mode enabled . . . . . . . . . . . . . . . . . . 101

Figure 24. Asynchronous power-on RESET (EA = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Figure 25. Asynchronous power-on RESET (EA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Figure 26. Asynchronous hardware RESET (EA = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Figure 27. Asynchronous hardware RESET (EA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

Figure 28. Synchronous short / long hardware RESET (EA = 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

Figure 29. Synchronous short / long hardware RESET (EA = 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Figure 30. Synchronous long hardware RESET (EA = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

Figure 31. Synchronous long hardware RESET (EA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Figure 32. SW / WDT unidirectional RESET (EA = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Figure 33. SW / WDT unidirectional RESET (EA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Figure 34. SW / WDT bidirectional RESET (EA = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Figure 35. SW / WDT bidirectional RESET (EA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

Figure 36. SW / WDT bidirectional RESET (EA = 0) followed by a HW RESET . . . . . . . . . . . . . . . . 121

Figure 37. Minimum external reset circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Figure 38. System reset circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

Figure 39. Internal (simplified) reset circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

Figure 40. Example of software or watchdog bidirectional reset (EA = 1) . . . . . . . . . . . . . . . . . . . . . 124

Figure 41. Example of software or watchdog bidirectional reset (EA = 0) . . . . . . . . . . . . . . . . . . . . . 125

Figure 42. PORT0 bits latched into the different registers after reset . . . . . . . . . . . . . . . . . . . . . . . . 128

Figure 43. External RC circuitry on RPD pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

Figure 44. Port2 test mode structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

Figure 45. Supply current versus the operating frequency (RUN and IDLE modes) . . . . . . . . . . . . . 181

Figure 46. A/D conversion characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

Figure 47. A/D converter input pins scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188

Figure 48. Charge sharing timing diagram during sampling phase . . . . . . . . . . . . . . . . . . . . . . . . . . 189

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List of figures ST10F276E

Figure 49. Anti-aliasing filter and conversion rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191

Figure 50. Input/output waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193

Figure 51. Float waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193

Figure 52. Generation mechanisms for the CPU clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194

Figure 53. ST10F276E PLL jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199

Figure 54. Crystal oscillator and resonator connection diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201

Figure 55. 32 kHz crystal oscillator connection diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202

Figure 56. External clock drive XTAL1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203

Figure 57. Multiplexed bus with/without R/W delay and normal ALE. . . . . . . . . . . . . . . . . . . . . . . . . 206

Figure 58. Multiplexed bus with/without R/W delay and extended ALE . . . . . . . . . . . . . . . . . . . . . . . 207

Figure 59. Multiplexed bus, with/without R/W delay, normal ALE, R/W CS. . . . . . . . . . . . . . . . . . . . 208

Figure 60. Multiplexed bus, with/without R/ W delay, extended ALE, R/W CS . . . . . . . . . . . . . . . . . 209

Figure 61. Demultiplexed bus, with/without read/write delay and normal ALE . . . . . . . . . . . . . . . . . 212

Figure 62. Demultiplexed bus with/without R/W delay and extended ALE . . . . . . . . . . . . . . . . . . . . 213

Figure 63. Demultiplexed bus with ALE and R/W CS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214

Figure 64. Demultiplexed bus, no R/W delay, extended ALE, R/W CS . . . . . . . . . . . . . . . . . . . . . . . 215

Figure 65. CLKOUT and READY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217

Figure 66. External bus arbitration (releasing the bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218

Figure 67. External bus arbitration (regaining the bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219

Figure 68. SSC master timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221

Figure 69. SSC slave timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223

Figure 70. PQFP144 mechanical data and package dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225

Figure 71. LQFP144 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226

Figure 72. LQFP144 package dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227

12/231

ST10F276E Introduction

1 Introduction

The ST10F276E is a derivative of the STMicroelectronics ST10 family of 16-bit single-chip CMOS microcontrollers. It combines high CPU performance (up to 32 million instructions per second) with high peripheral functionality and enhanced I/O-capabilities. It also provides on-chip high-speed single voltage Flash memory, on-chip high-speed RAM, and clock generation via PLL.

ST10F276E is processed in 0.18µm CMOS technology. The MCU core and the logic is supplied with a 5V to 1.8V on-chip voltage regulator. The part is supplied with a single 5V supply and I/Os work at 5V.

The device is upward compatible with the ST10F269 device, with the following set of differences:

● Flash control interface is now based on STMicroelectronics third generation of stand-

alone Flash memories (M29F400 series), with an embedded Program/Erase Controller. This completely frees up the CPU during programming or erasing the Flash.

● Only one supply pin (ex DC1 in ST10F269, renamed into V

is used for decoupling the internally generated 1.8V core logic supply. Do not connect this pin to 5.0V external supply. Instead, this pin should be connected to a decoupling capacitor (ceramic type, typical value 10nF, maximum value 100nF).

● The AC and DC parameters are modified due to a difference in the maximum CPU

frequency.

● A new V

● EA pin assumes a new alternate functionality: it is also used to provide a dedicated

power supply (see V the main Power Supply of the device (V V

) is turned off for low power mode, allowing data retention. V

pin replaces DC2 of ST10F269.

) to maintain biased a portion of the XRAM (16 Kbytes) when

STBY

and consequently the internally generated

the range 4.5-5.5 Volt, and a dedicated embedded low power voltage regulator is in charge to provide the 1.8V for the RAM, the low-voltage section of the 32 kHz oscillator and the Real-Time Clock module when not disabled. It is allowed to exceed the upper limit up to 6V for a very short period of time during the global life of the device, and exceed the lower limit down to 4V when RTC and 32kHz on-chip oscillator are not used.

● A second SSC mapped on the XBUS is added (SSC of ST10F269 becomes here

SSC0, while the new one is referred as XSSC or simply SSC1). Note that some restrictions and functional differences due to the XBUS peculiarities are present between the classic SSC, and the new XSSC.

● A second ASC mapped on the XBUS is added (ASC0 of ST10F269 remains ASC0,

while the new one is referred as XASC or simply as ASC1). Note that some restrictions and functional differences due to the XBUS peculiarities are present between the classic ASC, and the new XASC.

● A second PWM mapped on the XBUS is added (PWM of ST10F269 becomes here

PWM0, while the new one is referred as XPWM or simply as PWM1). Note that some restrictions and functional differences due to the XBUS peculiarities are present between the classic PWM, and the new XPWM.

● An I

● CLKOUT function can output either the CPU clock (like in ST10F269) or a software

C interface on the XBUS is added (see X-I2C or simply I2C interface).

programmable prescaled value of the CPU clock.

) on the QFP144 package

voltage shall be in

STBY

13/231

Introduction ST10F276E

● Embedded memory size has been significantly increased (both Flash and RAM).

● PLL multiplication factors have been adapted to new frequency range.

A/D Converter is not fully compatible versus ST10F269 (timing and programming model). Formula for the conversion time is still valid, while the sampling phase programming model is different.

Besides, additional 8 channels are available on P1L pins as alternate function: the accuracy reachable with these extra channels is reduced with respect to the standard Port5 channels.

● External Memory bus potential limitations on maximum speed and maximum

capacitance load could be introduced (under evaluation): ST10F276E will probably not be able to address an external memory at 64MHz with 0 wait states (under evaluation).

● XPERCON register bit mapping modified according to new peripherals implementation

(not fully compatible with ST10F269).

● Bondout chip for emulation (ST10R201) cannot achieve more than 50MHz at room

temperature (so no real-time emulation possible at maximum speed).

● Input section characteristics are different. The threshold programmability is extended to

all port pins (additional XPICON register); it is possible to select standard TTL (with up to 500mV of hysteresis) and standard CMOS (with up to 800mV of hysteresis).

● Output transition is not programmable.

● CAN module is enhanced: ST10F276E implements two C-CAN modules, so the

programming model is slightly different. Besides, the possibility to map in parallel the two CAN modules is added (on P4.5/P4.6).

● On-chip main oscillator input frequency range has been reshaped, reducing it from 1-

25MHz down to 4-12MHz. This is a high performance oscillator amplifier, providing a very high negative resistance and wide oscillation amplitude: when this on-chip amplifier is used as reference for Real-Time Clock module, the Power-down consumption is dominated by the consumption of the oscillator amplifier itself. A metal option is added to offer a low power oscillator amplifier working in the range of 4-8MHz: this will allow a power consumption reduction when Real-Time Clock is running in Power Down mode using as reference the on-chip main oscillator clock.

● A second on-chip oscillator amplifier circuit (32kHz) is implemented for low power

modes: it can be used to provide the reference to the Real-Time Clock counter (either in Power Down or Stand-by mode). Pin XTAL3 and XTAL4 replace a couple of V

DD/VSS

pins of ST10F269.

● Possibility to re-program internal XBUS chip select window characteristics (XRAM2 and

XFLASH address window) is added.

14/231

ST10F276E Introduction

Figure 1. Logic symbol

DDVSS

XTAL1 XTAL2 XTAL3 XTAL4

RSTIN

RSTOUT

AREF

AGND

NMI

EA / V

STBY

READY

ALE

WR / WRL

Port 5

16-bit

ST10F276E

Port 0 16-bit

Port 1 16-bit

Port 2 16-bit

Port 3 15-bit

Port 4 8-bit

Port 6 8-bit

Port 7 8-bit

Port 8 8-bit

RPD

15/231

Pin data ST10F276E

2 Pin data

Figure 2. Pin configuration (top view)

(*)

RSTOUT

RSTIN

VSS

XTAL1

XTAL2

VDD

P1H.7 / A15 / CC27I

P1H.6 / A14 / CC26I

P1H.5 / A13 / CC25I

P1H.4 / A12 / CC24I

P1H.3 / A11

P1H.2 / A10

P1H.1 / A9

P1H.0 / A8

VSS

VDD

P1L.7 / A7 / AN23

P1L.6 / A6 / AN22

P1L.5 / A5 / AN21

P1L.4 / A4 / AN20

P1L.3 / A3 / AN19

P1L.2 / A2 / AN18

P1L.1 / A1 / AN17

P1L.0 / A0 / AN16

P0H.7 / AD15

P0H.6 / AD14

P0H.5 / AD13

P0H.4 / AD12

P0H.3 / AD11

P0H.2 / AD10

P0H.1 / AD9

VSS

P6.0 / CS0 P6.1 / CS1 P6.2 / CS2 P6.3 / CS3 P6.4 / CS4

P6.5 / HOLD / SCLK1

/ MTSR1

P6.6 / HLDA

P6.7 / BREQ P8.0 / XPOUT0 / CC16IO P8.1 / XPOUT1 / CC17IO P8.2 / XPOUT2 / CC18IO P8.3 / XPOUT3 / CC19IO

/ MRST1

P8.4 / CC20IO P8.5 / CC21IO

P8.6 / RxD1 / CC22IO

P8.7 / TxD1 / CC23IO

VDD

VSS P7.0 / POUT0 P7.1 / POUT1 P7.2 / POUT2 P7.3 / POUT3

P7.4 / CC28IO P7.5 / CC29IO P7.6 / CC30IO P7.7 / CC31IO

P5.0 / AN0 P5.1 / AN1 P5.2 / AN2 P5.3 / AN3 P5.4 / AN4 P5.5 / AN5 P5.6 / AN6 P5.7 / AN7 P5.8 / AN8 P5.9 / AN9

XTAL4

XTAL3

NMI

144

143

142

141

140

139

138

137

136

135

134

133

132

131

130

129

128

127

126

125

124

123

122

121

120

119

118

117

116

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

3738394041424344454647484950515253545556575859606162636465666768697071

ST10F276E

115

114

113

112

VDD

111

110

109 108

P0H.0 / AD8

107

P0L.7 / AD7

106

P0L.6 / AD6

105

P0L.5 / AD5

104

P0L.4 / AD4

103

P0L.3 / AD3

102

P0L.2 / AD2

101

P0L.1 / AD1

100

P0L.0 / AD0

/ VSTBY

ALE

READY

WR/WRL

VSS

VDD

P4.7 / A23 / CAN2_TxD / SDA

P4.6 / A22 / CAN1_TxD / CAN2_TxD

P4.5 / A21 / CAN1_RxD / CAN2_RxD

P4.4 / A20 / CAN2_RxD / SCL

P4.3 / A19

P4.2 / A18

P4.1 / A17

P4.0 / A16

RPD

VSS

VDD

P3.15 / CLKOUT

P3.13 / SCLK0

P3.12 / BHE

P3.11 / RxD0

P3.10 / TxD0

P3.9 / MTSR0

P3.8 / MRST0

P3.7 / T2IN

P3.6 / T3IN

/ WRH

VSS

P5.12 / AN12 / T6IN

P5.13 / AN13 / T5IN

P5.14 / AN14 / T4EUD

VDD

P2.0 / CC0IO

P2.1 / CC1IO

P2.2 / CC2IO

P2.3 / CC3IO

P5.15 / AN15 / T2EUD

VAREF

VAGND

P5.10 / AN10 / T6EUD

P5.11 / AN11 / T5EUD

V18

VSS

P2.11 / CC11IO / EX3IN

P2.12 / CC12IO / EX4IN

P2.13 / CC13IO / EX5IN

P3.0 / T0IN

P2.14 / CC14IO / EX6IN

P2.15 / CC15IO / EX7IN / T7IN

P2.4 / CC4IO

P2.5 / CC5IO

P2.6 / CC6IO

P2.7 / CC7IO

P2.8 / CC8IO / EX0IN

P2.9 / CC9IO / EX1IN

P2.10 / CC10IO / EX2IN

VSS

VDD

P3.5 / T4IN

P3.2 / CAPIN

P3.1 / T6OUT

P3.3 / T3OUT

P3.4 / T3EUD

16/231

ST10F276E Pin data

Table 1. Pin description

Symbol Pin Type Function

8-bit bidirectional I/O port, bit-wise programmable for input or output via direction bit. Programming an I/O pin as input forces the corresponding output driver to

P6.0 - P6.7

1 - 8 I/O

1OP6.0CS0

... ... ... ... ...

5OP6.4CS4 Chip select 4 output

high impedance state. Port 6 outputs can be configured as push-pull or open drain drivers. The input threshold of Port 6 is selectable (TTL or CMOS). The following Port 6 pins have alternate functions:

Chip select 0 output

IP6.5HOLD

External master hold request input

I/O SCLK1 SSC1: master clock output / slave clock input

O P6.6 HLDA

Hold acknowledge output

I/O MTSR1 SSC1: master-transmitter / slave-receiver O/I

P8.0 - P8.7

OP6.7 BREQ Bus request output

I/O MRST1 SSC1: master-receiver / slave-transmitter I/O

8-bit bidirectional I/O port, bit-wise programmable for input or output via direction bit. Programming an I/O pin as input forces the corresponding output driver to

9-16 I/O

high impedance state. Port 8 outputs can be configured as push-pull or open drain drivers. The input threshold of Port 8 is selectable (TTL or CMOS). The following Port 8 pins have alternate functions:

I/O P8.0 CC16IO CAPCOM2: CC16 capture input / compare output

O XPWM0 PWM1: channel 0 output

... ... ... ... ...

I/O P8.3 CC19IO CAPCOM2: CC19 capture input / compare output

O XPWM0 PWM1: channel 3 output

13 I/O P8.4 CC20IO CAPCOM2: CC20 capture input / compare output

14 I/O P8.5 CC21IO CAPCOM2: CC21 capture input / compare output

I/O P8.6 CC22IO CAPCOM2: CC22 capture input / compare output

I/O RxD1 ASC1: Data input (Asynchronous) or I/O (Synchronous)

I/O P8.7 CC23IO CAPCOM2: CC23 capture input / compare output

O TxD1 ASC1: Clock / Data output (Asynchronous/Synchronous)

17/231

Pin data ST10F276E

Table 1. Pin description (continued)

Symbol Pin Type Function

8-bit bidirectional I/O port, bit-wise programmable for input or output via direction bit. Programming an I/O pin as input forces the corresponding output driver to

P7.0 - P7.7

P5.0 - P5.9

P5.10 - P5.15

19-26 I/O

19 O P7.0 POUT0 PWM0: channel 0 output

... ... ... ... ...

22 O P7.3 POUT3 PWM0: channel 3 output

23 I/O P7.4 CC28IO CAPCOM2: CC28 capture input / compare output

... ... ... ... ...

26 I/O P7.7 CC31IO CAPCOM2: CC31 capture input / compare output

27-36 39-44

39 I P5.10 T6EUD GPT2: timer T6 external up/down control input

40 I P5.11 T5EUD GPT2: timer T5 external up/down control input

41 I P5.12 T6IN GPT2: timer T6 count input

42 I P5.13 T5IN GPT2: timer T5 count input

43 I P5.14 T4EUD GPT1: timer T4 external up/down control input

high impedance state. Port 7 outputs can be configured as push-pull or open drain drivers. The input threshold of Port 7 is selectable (TTL or CMOS). The following Port 7 pins have alternate functions:

16-bit input-only port with Schmitt-Trigger characteristics. The pins of Port 5 can be the analog input channels (up to 16) for the A/D converter, where P5.x equals

ANx (Analog input channel x), or they are timer inputs. The input threshold of

Port 5 is selectable (TTL or CMOS). The following Port 5 pins have alternate functions:

P2.0 - P2.7

P2.8 - P2.15

44 I P5.15 T2EUD GPT1: timer T2 external up/down control input

16-bit bidirectional I/O port, bit-wise programmable for input or output via

47-54 57-64

47 I/O P2.0 CC0IO CAPCOM: CC0 capture input/compare output

... ... ... ... ...

54 I/O P2.7 CC7IO CAPCOM: CC7 capture input/compare output

57 I/O P2.8 CC8IO CAPCOM: CC8 capture input/compare output

... ... ... ... ...

64 I/O P2.15 CC15IO CAPCOM: CC15 capture input/compare output

direction bit. Programming an I/O pin as input forces the corresponding output

I/O

driver to high impedance state. Port 2 outputs can be configured as push-pull or open drain drivers. The input threshold of Port 2 is selectable (TTL or CMOS). The following Port 2 pins have alternate functions:

I EX0IN Fast external interrupt 0 input

I EX7IN Fast external interrupt 7 input

I T7IN CAPCOM2: timer T7 count input

18/231

ST10F276E Pin data

Table 1. Pin description (continued)

Symbol Pin Type Function

15-bit (P3.14 is missing) bidirectional I/O port, bit-wise programmable for input or 65-70, 73-80,

65 I P3.0 T0IN CAPCOM1: timer T0 count input

66 O P3.1 T6OUT GPT2: timer T6 toggle latch output

67 I P3.2 CAPIN GPT2: register CAPREL capture input

68 O P3.3 T3OUT GPT1: timer T3 toggle latch output

69 I P3.4 T3EUD GPT1: timer T3 external up/down control input

I/O

output via direction bit. Programming an I/O pin as input forces the

I/O

corresponding output driver to high impedance state. Port 3 outputs can be

I/O

configured as push-pull or open drain drivers. The input threshold of Port 3 is

selectable (TTL or CMOS). The following Port 3 pins have alternate functions:

P3.0 - P3.5

P3.6 - P3.13,

P3.15

70 I P3.5 T4IN GPT1; timer T4 input for count/gate/reload/capture

73 I P3.6 T3IN GPT1: timer T3 count/gate input

74 I P3.7 T2IN GPT1: timer T2 input for count/gate/reload / capture

75 I/O P3.8 MRST0 SSC0: master-receiver/slave-transmitter I/O

76 I/O P3.9 MTSR0 SSC0: master-transmitter/slave-receiver O/I

77 O P3.10 TxD0 ASC0: clock / data output (asynchronous/synchronous)

78 I/O P3.11 RxD0 ASC0: data input (asynchronous) or I/O (synchronous)

79 O P3.12 BHE

WRH

80 I/O P3.13 SCLK0 SSC0: master clock output / slave clock input

81 O P3.15 CLKOUT

External memory high byte enable signal

External memory high byte write strobe

System clock output (programmable divider on CPU clock)

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Pin data ST10F276E

Table 1. Pin description (continued)

Symbol Pin Type Function

Port 4 is an 8-bit bidirectional I/O port. It is bit-wise programmable for input or

output via direction bit. Programming an I/O pin as input forces the

corresponding output driver to high impedance state. The input threshold is

85-92 I/O

85 O P4.0 A16 Segment address line

86 O P4.1 A17 Segment address line

87 O P4.2 A18 Segment address line

88 O P4.3 A19 Segment address line

89 O P4.4 A20 Segment address line

P4.0 –P4.7

90 O P4.5 A21 Segment address line

91 O P4.6 A22 Segment address line

selectable (TTL or CMOS). Port 4.4, 4.5, 4.6 and 4.7 outputs can be configured

as push-pull or open drain drivers.

In case of an external bus configuration, Port 4 can be used to output the

segment address lines:

I CAN2_RxD CAN2: receive data input

I/O SCL

I2C Interface: serial clock

I CAN1_RxD CAN1: receive data input

I CAN2_RxD CAN2: receive data input

92 O P4.7 A23 Most significant segment address line

RD 95 O

/WRL 96 O

READY/

READY

97 I

ALE 98 O

O CAN1_TxD CAN1: transmit data output

O CAN2_TxD CAN2: transmit data output

I/O SDA

External memory read strobe. RD

I2C Interface: serial data

is activated for every external instruction or

data read access.

External memory write strobe. In WR

external data write access. In WRL

-mode this pin is activated for every

mode this pin is activated for low byte data write accesses on a 16-bit bus, and for every data write access on an 8-bit bus. See WRCFG in the SYSCON register for mode selection.

Ready input. The active level is programmable. When the ready function is enabled, the selected inactive level at this pin, during an external memory access, will force the insertion of waitstate cycles until the pin returns to the selected active level.

Address latch enable output. In case of use of external addressing or of multiplexed mode, this signal is the latch command of the address lines.

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ST10F276E Pin data

Table 1. Pin description (continued)

Symbol Pin Type Function

External access enable pin. A low level applied to this pin during and after Reset forces the ST10F276E to

start the program from the external memory space. A high level forces ST10F276E to start in the internal memory space. This pin is also used (when

turned

EA / V

STBY

P0L.0 -P0L.7,

P0H.0

P0H.1 - P0H.7

99 I

100-107,

108,

111-117

Stand-by mode is entered, that is ST10F276E under reset and main V off) to bias the 32 kHz oscillator amplifier circuit and to provide a reference voltage for the low-power embedded voltage regulator which generates the internal 1.8V supply for the RTC module (when not disabled) and to retain data inside the Stand-by portion of the XRAM (16 Kbyte). It can range from 4.5 to 5.5V (6V for a reduced amount of time during the device life, 4.0V when RTC and 32 kHz on-chip oscillator amplifier are turned off). In running mode, this pin can be tied low during reset without affecting 32 kHz oscillator, RTC and XRAM activities, since the presence of a stable V guarantees the proper biasing of all those modules.

Two 8-bit bidirectional I/O ports P0L and P0H, bit-wise programmable for input or output via direction bit. Programming an I/O pin as input forces the corresponding output driver to high impedance state. The input threshold of Port 0 is selectable (TTL or CMOS). In case of an external bus configuration, PORT0 serves as the address (A) and as the address / data (AD) bus in multiplexed bus modes and as the data (D) bus in demultiplexed bus modes.

Demultiplexed bus modes

Data path width 8-bit 16-bi

I/O

P0L.0 – P0L.7: D0 – D7 D0 - D7

P0H.0 – P0H.7: I/O D8 - D15

P1L.0 - P1L.7

P1H.0 - P1H.7

Multiplexed bus modes

Data path width 8-bit 16-bi

P0L.0 – P0L.7: AD0 – AD7 AD0 - AD7

P0H.0 – P0H.7: A8 – A15 AD8 - AD15

Two 8-bit bidirectional I/O ports P1L and P1H, bit-wise programmable for input or output via direction bit. Programming an I/O pin as input forces the corresponding output driver to high impedance state. PORT1 is used as the 16bit address bus (A) in demultiplexed bus modes: if at least BUSCONx is

118-125 128-135

configured such the demultiplexed mode is selected, the pis of PORT1 are not available for general purpose I/O function. The input threshold of Port 1 is

I/O

selectable (TTL or CMOS). The pins of P1L also serve as the additional (up to 8) analog input channels for

the A/D converter, where P1L.x equals ANy (Analog input channel y, where y = x + 16). This additional function have higher priority on demultiplexed bus function. The following PORT1 pins have alternate functions:

132 I P1H.4 CC24IO CAPCOM2: CC24 capture input

133 I P1H.5 CC25IO CAPCOM2: CC25 capture input

134 I P1H.6 CC26IO CAPCOM2: CC26 capture input

135 I P1H.7 CC27IO CAPCOM2: CC27 capture input

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Pin data ST10F276E

Table 1. Pin description (continued)

Symbol Pin Type Function

XTAL1 138 I XTAL1 Main oscillator amplifier circuit and/or external clock input.

XTAL2 137 O XTAL2 Main oscillator amplifier circuit output.

To clock the device from an external source, drive XTAL1 while leaving XTAL2 unconnected. Minimum and maximum high / low and rise / fall times specified in the AC Characteristics must be observed.

XTAL3 143 I XTAL3 32 kHz oscillator amplifier circuit input

XTAL4 144 O XTAL4 32 kHz oscillator amplifier circuit output

When 32 kHz oscillator amplifier is not used, to avoid spurious consumption, XTAL3 shall be tied to ground while XTAL4 shall be left open. Besides, bit OFF32 in RTCCON register shall be set. 32 kHz oscillator can only be driven by an external crystal, and not by a different clock source.

Reset Input with CMOS Schmitt-Trigger characteristics. A low level at this pin for a specified duration while the oscillator is running resets the ST10F276E. An

RSTIN

RSTOUT

NMI

140 I

141 O

142 I

internal pull-up resistor permits power-on reset using only a capacitor connected

. In bidirectional reset mode (enabled by setting bit BDRSTEN in

to V

SYSCON register), the RSTIN

line is pulled low for the duration of the internal

reset sequence.

Internal Reset Indication Output. This pin is driven to a low level during hardware, software or watchdog timer reset.

RSTOUT

remains low until the EINIT

(end of initialization) instruction is executed.

Non-Maskable Interrupt Input. A high to low transition at this pin causes the CPU to vector to the NMI trap routine. If bit PWDCFG = ‘0’ in SYSCON register, when the PWRDN (power down) instruction is executed, the NMI pin must be low in order to force the ST10F276E to go into power down mode. If NMI is high and PWDCFG = ‘0’, when PWRDN is executed, the part will continue to run in normal mode. If not used, pin NMI

should be pulled high externally.

AREF

AGND

RPD 84 -

37 - A/D converter reference voltage and analog supply

38 - A/D converter reference and analog ground

Timing pin for the return from interruptible power down mode and synchronous / asynchronous reset selection.

17, 46, 72,82,93, 109, 126,

136

Digital supply voltage = + 5V during normal operation, idle and power down

modes. It can be turned off when Stand-by RAM mode is selected.

18,45, 55,71,

83,94,

- Digital ground

110, 127,

139

56 -

1.8V decoupling pin: a decoupling capacitor (typical value of 10nF, max 100nF) must be connected between this pin and nearest V

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pin.

ST10F276E Functional description

3 Functional description

The architecture of the ST10F276E combines advantages of both RISC and CISC processors and an advanced peripheral subsystem. The block diagram gives an overview of the different on-chip components and the high bandwidth internal bus structure of the ST10F276E.

Figure 3. Block diagram

XFLASH

16 16

IFLASH 512 KB

XPWM

XCAN2

Controller

External Bus

320 KB

XRAM

48 KB

XRAM

16 KB

(STBY)

XRAM

2 KB

(PEC)

XI2C

XCAN1

Por t 0Por t 1Po rt 4

Por t 6

81615 8 8

XRTC

XASC

XSSC

Por t 5

CPU-Core and MAC Unit

Interrupt Controller

10-bit ADC

GPT1 / GPT2

BRG BRG

Port 3 Port 7 Por t 8

ASC0

SSC0

PEC

PWM

CAPCOM2

IRAM

2 KB

Watchdog

Oscillator

32 kHz

Oscillator

PLL

5V-1.8V

Vol tag e

Regulator

CAPCOM1

Por t 2

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Internal Flash memory ST10F276E

4 Internal Flash memory

4.1 Overview

The on-chip Flash is composed of two matrix modules, each one containing one array divided in two banks that can be read and modified independently of one another: one bank can be read while another bank is under modification.

Figure 4. Flash modules structure

IFLASH (Module I)

Bank 1: 128 Kbyte

program memory

Bank 0: 384 Kbyte

program memory

8 Kbyte test-Flash

I-BUS interface

The write operations of the four banks are managed by an embedded Flash program/erase controller (FPEC). The high voltages needed for program/erase operations are internally generated.

The data bus is 32-bit wide. Due to ST10 core architecture limitation, only the first 512 Kbytes are accessed at 32-bit (internal Flash bus, see I-BUS), while the remaining 320 Kbytes are accessed at 16-bit (see X-BUS).

4.2 Functional description

Control section

HV and Ref.

generator

Program/erase

controller

XFLASH (Module X)

Bank 3: 128 Kbyte

Bank 2: 192 Kbyte

X-BUS interface

program memory

4.2.1 Structure

Ta bl e 2 shows the address space reserved to the Flash module.

Table 2. Flash modules absolute mapping

Description Addresses Size

IFLASH sectors 0x00 0000 to 0x08 FFFF 512 Kbyte

XFLASH sectors 0x09 0000 to 0x0D FFFF 320 Kbyte

Registers and Flash internal reserved area 0x0E 0000 to 0x0E FFFF 64 Kbyte

4.2.2 Modules structure

The IFLASH module is composed of two banks. Bank 0 contains 384 Kbyte of program memory divided in 10 sectors. Bank 0 contains also a reserved sector named test-Flash.

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ST10F276E Internal Flash memory

Bank 1 contains 128 Kbyte of program memory or parameter divided in two sectors (64 Kbyte each).

The XFLASH module is composed of two banks as well. Bank 2 contains 192 Kbyte of program memory divided in three sectors. Bank 3 contains 128 Kbyte of program memory or parameter divided in two sectors (64 Kbyte each).

Addresses from 0x0E 0000 to 0x0E FFFF are reserved for the control register interface and other internal service memory space used by the Flash program/erase controller.

The following tables show the memory mapping of the Flash when it is accessed in read mode (Ta bl e 3 ), and when accessed in write or erase mode (Ta bl e 2 ): note that with this second mapping, the first three banks are remapped into code segment 1 (same as obtained when setting bit ROMS1 in SYSCON register).

Table 3. Flash modules sectorization (read operations)

Bank Description Addresses Size

Bank 0 Flash 0 (B0F0) 0x0000 0000 - 0x0000 1FFF 8 KB

Bank 0 Flash 1 (B0F1) 0x0000 2000 - 0x0000 3FFF 8 KB

Bank 0 Flash 2 (B0F2) 0x0000 4000 - 0x0000 5FFF 8 KB

Bank 0 Flash 3 (B0F3) 0x0000 6000 - 0x0000 7FFF 8 KB

Bank 0 Flash 4 (B0F4) 0x0001 8000 - 0x0001 FFFF 32 KB

Bank 0 Flash 5 (B0F5) 0x0002 0000 - 0x0002 FFFF 64 KB

Bank 0 Flash 6 (B0F6) 0x0003 0000 - 0x0003 FFFF 64 KB

Bank 0 Flash 7 (B0F7) 0x0004 0000 - 0x0004 FFFF 64 KB

Bank 0 Flash 8 (B0F8) 0x0005 0000 - 0x0005 FFFF 64 KB

Bank 0 Flash 9 (B0F9) 0x0006 0000 - 0x0006 FFFF 64 KB

Bank 1 Flash 0 (B1F0) 0x0007 0000 - 0x0007 FFFF 64 KB

Bank 1 Flash 1 (B1F1) 0x0008 0000 - 0x0008 FFFF 64 KB

Bank 2 Flash 0 (B2F0) 0x0009 0000 - 0x0009 FFFF 64 KB

Bank 2 Flash 1 (B2F1) 0x000A 0000 - 0x000A FFFF 64 KB

Bank 2 Flash 2 (B2F2) 0x000B 0000 - 0x000B FFFF 64 KB

Bank 3 Flash 0 (B3F0) 0x000C 0000 - 0x000C FFFF 64 KB

Bank 3 Flash 1 (B3F1) 0x000D 0000 - 0x000D FFFF 64 KB

ST10 bus

size

32-bit (I-BUS)

16-bit

(X-BUS)

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Internal Flash memory ST10F276E

Table 4. Flash modules sectorization (write operations or with ROMS1 = ‘1’)

Bank Description Addresses Size

Bank 0 Test-Flash (B0TF) 0x0000 0000 - 0x0000 1FFF 8 KB

Bank 0 Flash 0 (B0F0) 0x0001 0000 - 0x0001 1FFF 8 KB

Bank 0 Flash 1 (B0F1) 0x0001 2000 - 0x0001 3FFF 8 KB

Bank 0 Flash 2 (B0F2) 0x0001 4000 - 0x0001 5FFF 8 KB

Bank 0 Flash 3 (B0F3) 0x0001 6000 - 0x0001 7FFF 8 KB

Bank 0 Flash 4 (B0F4) 0x0001 8000 - 0x0001 FFFF 32 KB

Bank 0 Flash 5 (B0F5) 0x0002 0000 - 0x0002 FFFF 64 KB

Bank 0 Flash 6 (B0F6) 0x0003 0000 - 0x0003 FFFF 64 KB

Bank 0 Flash 7 (B0F7) 0x0004 0000 - 0x0004 FFFF 64 KB

Bank 0 Flash 8 (B0F8) 0x0005 0000 - 0x0005 FFFF 64 KB

Bank 0 Flash 9 (B0F9) 0x0006 0000 - 0x0006 FFFF 64 KB

Bank 1 Flash 0 (B1F0) 0x0007 0000 - 0x0007 FFFF 64 KB

Bank 1 Flash 1 (B1F1) 0x0008 0000 - 0x0008 FFFF 64 KB

Bank 2 Flash 0 (B2F0) 0x0009 0000 - 0x0009 FFFF 64 KB

Bank 2 Flash 1 (B2F1) 0x000A 0000 - 0x000A FFFF 64 KB

Bank 2 Flash 2 (B2F2) 0x000B 0000 - 0x000B FFFF 64 KB

Bank 3 Flash 0 (B3F0) 0x000C 0000 - 0x000C FFFF 64 KB

Bank 3 Flash 1 (B3F1) 0x000D 0000 - 0x000D FFFF 64 KB

ST10 Bus

size

32-bit (I-BUS)

16-bit

(X-BUS)

Ta bl e 4 above refers to the configuration when bit ROMS1 of SYSCON register is set. When

Bootstrap mode is entered:

● Test-Flash is seen and available for code fetches (address 00’0000h)

● User IFlash is only available for read and write accesses

● Write accesses must be made with addresses starting in segment 1 from 01'0000h,

whatever ROMS1 bit in SYSCON value

● Read accesses are made in segment 0 or in segment 1 depending of ROMS1 value.

In Bootstrap mode, by default ROMS1 = 0, so the first 32 Kbytes of IFlash are mapped in segment 0.

Example: In default configuration, to program address 0, user must put the value 01'0000h in the FARL and FARH registers, but to verify the content of the address 0 a read to 00'0000h must be performed.

Ta bl e 5 shows the control register interface composition: this set of registers can be

addressed by the CPU.

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ST10F276E Internal Flash memory

Table 5. Control register interface

Bank Description Addresses Size

FCR1-0 Flash control registers 1-0 0x000E 0000 - 0x000E 0007 8 byte

FDR1-0 Flash data registers 1-0 0x000E 0008 - 0x000E 000F 8 byte

FAR Flash address registers 0x000E 0010 - 0x000E 0013 4 byte

FER Flash error register 0x000E 0014 - 0x000E 0015 2 byte

FNVWPXR

FNVWPIR

FNVAPR0

FNVAPR1

XFICR XFlash interface control register 0x000E E000 - 0x000E E001 2 byte

Flash non-volatile protection X register

Flash non-volatile protection I register

Flash non-volatile access protection register 0

Flash non-volatile access protection register 1

0x000E DFB0 - 0x000E DFB3 4 byte

0x000E DFB4 - 0x000E DFB7 4 byte

0x000E DFB8 - 0x000E DFB9 2 byte

0x000E DFBC - 0x000E DFBF 4 byte

ST10

bus size

16-bit

(X-BUS)

4.2.3 Low power mode

The Flash modules are automatically switched off executing PWRDN instruction. The consumption is drastically reduced, but exiting this state can require a long time (t

Note: Recovery time from Power Down mode for the Flash modules is anyway shorter than the

main oscillator start-up time. To avoid any problem in restarting to fetch code from the Flash, it is important to size properly the external circuit on RPD pin.

Power-off Flash mode is entered only at the end of the eventually running Flash write operation.

4.2.4 Write operation

The Flash modules have one single register interface mapped in the memory space of the XFlash module (0x0E 0000 to 0x0E 0013). All the operations are enabled through four 16-bit control registers: Flash Control Register 1-0 High/Low (FCR1H/L-FCR0H/L). Eight other 16bit registers are used to store Flash Address and Data for Program operations (FARH/L and FDR1H/L-FDR0H/L) and Write Operation Error flags (FERH/L). All registers are accessible with 8 and 16-bit instructions (since mapped on ST10 XBUS).

Note: Before accessing the XFlash module (and consequently also the Flash register to be used

for program/erasing operations), bit XFLASHEN in XPERCON register and bit XPEN in SYSCON register shall be set.

The four banks have their own dedicated sense amplifiers, so that any bank can be read while any other bank is written. However simultaneous write operations (“write” means either Program or Erase) on different banks are forbidden: when there is a write operation on going (Program or Erase) anywhere in the Flash, no other write operation can be performed.

During a Flash write operation any attempt to read the bank under modification will output invalid data (software trap 009Bh). This means that the Flash bank is not fetchable when a write operation is active: the write operation commands must be executed from another

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Internal Flash memory ST10F276E

bank, or from the other module or again from another memory (internal RAM or external memory).

Note: During a Write operation, when bit LOCK of FCR0 is set, it is forbidden to write into the

Flash Control Registers.

4.2.5 Power supply drop

If during a write operation the internal low voltage supply drops below a certain internal voltage threshold, any write operation running is suddenly interrupted and the modules are reset to Read mode. At following Power-on, an interrupted Flash write operation must be repeated.

4.3 Registers description

4.3.1 Flash control register 0 low

The Flash control register 0 low (FCR0L) together with the Flash control register 0 high (FCR0H) is used to enable and to monitor all the write operations for both the Flash modules. The user has no access in write mode to the test-Flash (B0TF). Besides, testFlash block is seen by the user in Bootstrap mode only.

FCR0L (0x0E 0000) FCR Reset value: 0000h

1514131211109876543210

Reserved BSY1 BSY0 LOCK Res. BSY3 BSY2 Res.

RRR RR

Table 6. Flash control register 0 low

Bit Function

Bank 3:2 Busy (XFLASH) These bits indicate that a write operation is running on the corresponding bank of

XFLASH. They are automatically set when bit WMS is set. Setting Protection operation sets bit BSY2 (since protection registers are in the Block B2). When these

BSY(3:2)

bits are set every read access to the corresponding bank will output invalid data (software trap 009Bh), while every write access to the bank will be ignored. At the end of the write operation or during a Program or Erase Suspend these bits are automatically reset and the bank returns to read mode. After a Program or Erase Resume these bits are automatically set again.

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ST10F276E Internal Flash memory

Table 6. Flash control register 0 low (continued)

Bit Function

Flash registers access locked When this bit is set, it means that the access to the Flash Control Registers FCR0H/-

FCR1H/L, FDR0H/L-FDR1H/L, FARH/L and FER is locked by the FPEC: any read access to the registers will output invalid data (software trap 009Bh) and any write

LOCK

BSY(1:0)

access will be ineffective. LOCK bit is automatically set when the Flash bit WMS is set. This is the only bit the user can always access to detect the status of the Flash: once it is found low, the rest of FCR0L and all the other Flash registers are accessible by the user as well. Note that FER content can be read when LOCK is low, but its content is updated only when also BSY bits are reset.

Bank 1:0 Busy (IFLASH) These bits indicate that a write operation is running in the corresponding bank of

IFLASH. They are automatically set when bit WMS is set. When these bits are set every read access to the corresponding bank will output invalid data (software trap 009Bh), while every write access to the bank will be ignored. At the end of the write operation or during a Program or Erase Suspend these bits are automatically reset and the bank returns to read mode. After a Program or Erase Resume these bits are automatically set again.

4.3.2 Flash control register 0 high

The Flash control register 0 high (FCR0H) together with the Flash control register 0 Low (FCR0L) is used to enable and to monitor all the write operations for both the Flash modules. The user has no access in write mode to the Test-Flash (B0TF). Besides, testFlash block is seen by the user in Bootstrap mode only.

FCR0H (0x0E 0002) FCR Reset value: 0000h

1514131211109876543210

WMS SUSP WPG DWPG SER Reserved SPR SMOD Reserved

RW RW RW RW RW RW RW

Table 7. Flash control register 0 high

Bit Function

Select module

SMOD

SPR

If this bit is reset, the Write Operation is performed on XFLASH Module; if this bit is set, the Write Operation is performed on IFLASH Module. SMOD bit is automatically reset at the end of the Write operation.

Set protection This bit must be set to select the Set Protection operation. The Set Protection

operation allows to program 0s in place of 1s in the Flash Non-volatile Protection Registers. The Flash Address in which to program must be written in the FARH/L registers, while the Flash Data to be programmed must be written in the FDR0H/L before starting the execution by setting bit WMS. A sequence error is flagged by bit SEQER of FER if the address written in FARH/L is not in the range 0x0EDFB00x0EDFBF. SPR bit is automatically reset at the end of the Set Protection operation.

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Internal Flash memory ST10F276E

Table 7. Flash control register 0 high (continued)

Bit Function

Sector erase This bit must be set to select the Sector Erase operation in the Flash modules. The

Sector Erase operation allows to erase all the Flash locations to 0xFF. From 1 to all the

SER

DWPG

WPG

SUSP

WMS

sectors of the same bank (excluded Test-Flash for Bank B0) can be selected to be erased through bits BxFy of FCR1H/L registers before starting the execution by setting bit WMS. It is not necessary to pre-program the sectors to 0x00, because this is done automatically. SER bit is automatically reset at the end of the Sector Erase operation.

Double word program This bit must be set to select the Double Word (64 bits) Program operation in the Flash

modules. The Double Word Program operation allows to program 0s in place of 1s. The Flash Address in which to program (aligned with even words) must be written in the FARH/L registers, while the 2 Flash Data to be programmed must be written in the FDR0H/L registers (even word) and FDR1H/L registers (odd word) before starting the execution by setting bit WMS. DWPG bit is automatically reset at the end of the Double Word Program operation.

Word program This bit must be set to select the Word (32 bits) Program operation in the Flash

modules. The Word Program operation allows to program 0s in place of 1s. The Flash Address to be programmed must be written in the FARH/L registers, while the Flash Data to be programmed must be written in the FDR0H/L registers before starting the execution by setting bit WMS. WPG bit is automatically reset at the end of the Word Program operation.

Suspend This bit must be set to suspend the current Program (Word or Double Word) or Sector

Erase operation in order to read data in one of the sectors of the bank under modification or to program data in another bank. The Suspend operation resets the Flash bank to normal read mode (automatically resetting bits BSYx). When in Program Suspend, the two Flash modules accept only the following operations: Read and Program Resume. When in Erase Suspend the modules accept only the following operations: Read, Erase Resume and Program (Word or Double Word; Program operations cannot be suspended during Erase Suspend). To resume the suspended operation, the WMS bit must be set again, together with the selection bit corresponding to the operation to resume (WPG, DWPG, SER). Note: It is forbidden to start a new Write operation with bit SUSP already set.

Write mode start This bit must be set to start every write operation in the Flash modules. At the end of

the write operation or during a Suspend, this bit is automatically reset. To resume a suspended operation, this bit must be set again. It is forbidden to set this bit if bit ERR of FER is high (the operation is not accepted). It is also forbidden to start a new write (program or erase) operation (by setting WMS high) when bit SUSP of FCR0 is high. Resetting this bit by software has no effect.

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ST10F276E Internal Flash memory

4.3.3 Flash control register 1 low

The Flash control register 1 low (FCR1L), together with Flash control register 1 high (FCR1H), is used to select the sectors to erase, or during any write operation to monitor the status of each sector of the module selected by SMOD bit of FCR0H. First diagram shows FCR1L meaning when SMOD = 0; the second one when SMOD = 1.

FCR1L (0x0E 0004) SMOD = 0 FCR Reset value: 0000h

1514131211109876543210

Reserved B2F2 B2F1 B2F0

RS RS RS

FCR1L (0x0E 0004) SMOD = 1 FCR Reset value: 0000h

1514131211109876543210

Reserved B0F9 B0F8 B0F7 B0F6 B0F5 B0F4 B0F3 B0F2 B0F1 B0F0

RS RS RS RS RS RS RS RS RS RS

Table 8. Flash control register 1 low

Bit Function

SMOD = 0 (XFLASH selected)

Bank 2 XFLASH sector 2:0 status These bits must be set during a Sector Erase operation to select the sectors to erase

B2F(2:0)

in Bank 2. Besides, during any erase operation, these bits are automatically set and give the status of the three sectors of Bank 2 (B2F2-B2F0). The meaning of B2Fy bit for sector y of Bank 2 is given by Ta bl e 10 . These bits are automatically reset at the end of a write operation if no errors are detected.

SMOD = 1 (IFLASH selected)

Bank 0 IFLASH sector 9:0 status These bits must be set during a Sector Erase operation to select the sectors to erase

B0F(9:0)

in Bank 0. Besides, during any erase operation, these bits are automatically set and give the status of the 10 sectors of Bank 0 (B0F9-B0F0). The meaning of B0Fy bit for sector y of Bank 0 is given by Ta bl e 10 . These bits are automatically reset at the end of a Write operation if no errors are detected.

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Internal Flash memory ST10F276E

4.3.4 Flash control register 1 high

The Flash control register 1 high (FCR1H), together with Flash control register 1 low (FCR1L), is used to select the sectors to erase, or during any write operation to monitor the status of each sector and each bank of the module selected by SMOD bit of FCR0H. First diagram shows FCR1H meaning when SMOD = 0; the second one when SMOD = 1.

FCR1H (0x0E 0006) SMOD = 0 FCR Reset value: 0000h

1514131211109876543210

Reserved B3S B2S Reserved B3F1 B3F0

RS RS RS RS

FCR1H (0x0E 0006) SMOD = 1 FCR Reset value: 0000h

1514131211109876543210

Reserved B1S B0S Reserved B1F1 B1F0

- RSRS RSRS

Table 9. Flash control register 1 high

Bit Function

SMOD = 0 (XFLASH selected)

Bank 3 XFLASH sector 1:0 status During any erase operation, these bits are automatically set and give the status of the

B3F(1:0)

two sectors of Bank 3 (B3F1-B3F0). The meaning of B3Fy bit for sector y of Bank 1 is given by Ta bl e 1 0 . These bits are automatically reset at the end of a erase operation if no errors are detected.

Bank 3-2 status (XFLASH) During any erase operation, these bits are automatically modified and give the status

B(3:2)S

of the two banks (B3-B2). The meaning of BxS bit for bank x is given in Tab l e 1 0 . These bits are automatically reset at the end of a erase operation if no errors are detected.

SMOD = 1 (IFLASH selected)

Bank 1 IFLASH sector 1:0 status During any erase operation, these bits are automatically set and give the status of the

B1F(1:0)

two sectors of Bank 1 (B1F1-B1F0). The meaning of B1Fy bit for sector y of Bank 1 is given by Ta bl e 1 0 . These bits are automatically reset at the end of a erase operation if no errors are detected.

Bank 1-0 status (IFLASH) During any erase operation, these bits are automatically modified and give the status

B(1:0)S

of the two banks (B1-B0). The meaning of BxS bit for bank x is given in Tab l e 1 0 . These bits are automatically reset at the end of a erase operation if no errors are detected.

During any erase operation, these bits are automatically set and give the status of the two sectors of Bank 1 (B1F1-B1F0). The meaning of B1Fy bit for sector y of Bank 1 is given by

Ta bl e 1 0. These bits are automatically reset at the end of a erase operation if no errors are

detected.

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Table 10. Banks (BxS) and sectors (BxFy) status bits meaning

ERR SUSP BxS = 1 meaning BxFy = 1 meaning

1 - Erase error in bank x Erase error in sector y of bank x

0 1 Erase suspended in bank x Erase suspended in sector y of bank x

0 0 Don’t care Don’t care

4.3.5 Flash data register 0 low

The Flash address registers (FARH/L) and the Flash data registers (FDR1H/L-FDR0H/L) are used during the program operations to store Flash Address in which to program and data to program.

FDR0L (0x0E 0008) FCR Reset value: FFFFh

1514131211109876543210

DIN15 DIN14 DIN13 DIN12 DIN11 DIN10 DIN9 DIN8 DIN7 DIN6 DIN5 DIN4 DIN3 DIN2 DIN1 DIN0

RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW

Table 11. Flash data register 0 low

Bit Function

Data input 15:0

DIN(15:0)

These bits must be written with the data to program the Flash with the following operations: word program (32-bit), double word program (64-bit) and set protection.

4.3.6 Flash data register 0 high

FDR0H (0x0E 000A) FCR Reset value: FFFFh

1514131211109876543210

DIN31 DIN30 DIN29 DIN28 DIN27 DIN26 DIN25 DIN24 DIN23 DIN22 DIN21 DIN20 DIN19 DIN18 DIN17 DIN16

RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW

Table 12. Flash data register 0 high

Bit Function

Data input 31:16

DIN(31:16)

These bits must be written with the data to program the Flash with the following operations: word program (32-bit), double word program (64-bit) and set protection.

4.3.7 Flash data register 1 low

FDR1L (0x0E 000C) FCR Reset value: FFFFh

1514131211109876543210

DIN15 DIN14 DIN13 DIN12 DIN11 DIN10 DIN9 DIN8 DIN7 DIN6 DIN5 DIN4 DIN3 DIN2 DIN1 DIN0

RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW

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Internal Flash memory ST10F276E

Table 13. Flash data register 1 low

Bit Function

Data Input 15:0

DIN(15:0)

These bits must be written with the Data to program the Flash with the following operations: Word Program (32-bit), Double Word Program (64-bit) and Set Protection.

4.3.8 Flash data register 1 high

FDR1H (0x0E 000E) FCR Reset value: FFFFh

1514131211109876543210

DIN31 DIN30 DIN29 DIN28 DIN27 DIN26 DIN25 DIN24 DIN23 DIN22 DIN21 DIN20 DIN19 DIN18 DIN17 DIN16

RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW

Table 14. Flash data register 1 high

Bit Function

Data input 31:16

DIN(31:16)

These bits must be written with the data to program the Flash with the following operations: word program (32-bit), double word program (64-bit) and set protection.

4.3.9 Flash address register low

FARL (0x0E 0010) FCR Reset value: 0000h

1514131211109876543210

ADD15 ADD14 ADD13 ADD12 ADD11 ADD10 ADD9 ADD8 ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 Reserved

RW RW RW RW RW RW RW RW RW RW RW RW RW RW

Table 15. Flash address register low

Bit Function

Address 15:2

ADD(15:2)

These bits must be written with the address of the Flash location to program in the following operations: word program (32-bit) and double word program (64-bit). In double word program bit ADD2 must be written to ‘0’.

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ST10F276E Internal Flash memory

4.3.10 Flash address register high

FARH (0x0E 0012) FCR Reset value: 0000h

1514131211109876543210

Reserved ADD20 ADD19 ADD18 ADD17 ADD16

RW RW RW RW RW

Table 16. Flash address register high

Bit Function

Address 20:16

ADD(20:16)

These bits must be written with the address of the Flash location to program in the following operations: word program and double word program.

4.3.11 Flash error register

Flash error register, as well as all the other Flash registers, can be properly read only once LOCK bit of register FCR0L is low. Nevertheless, its content is updated when also BSY bits are reset as well; for this reason, it is definitively meaningful reading FER register content only when LOCK bit and all BSY bits are cleared.

FER (0xE 0014h) FCR Reset value: 0000h

1514131211109876543210

Reserved WPF RESERSEQER Reserved 10ER PGER ERER ERR

RC RC RC RC RC RC RC

Table 17. Flash error register

Bit Function

Write error

ERR

This bit is automatically set when an error occurs during a Flash write operation or when a bad write operation setup is done. Once the error has been discovered and understood, ERR bit must be software reset.

Erase error This bit is automatically set when an erase error occurs during a Flash write operation.

ERER

This error is due to a real failure of a Flash cell, that can no more be erased. This kind of error is fatal and the sector where it occurred must be discarded. This bit has to be software reset.

Program error This bit is automatically set when a program error occurs during a Flash write

PGER

operation. This error is due to a real failure of a Flash cell, that can no more be programmed. The word where this error occurred must be discarded. This bit has to be software reset.

1 over 0 error This bit is automatically set when trying to program at 1 bits previously set at 0 (this

10ER

does not happen when programming the protection bits). This error is not due to a failure of the Flash cell, but only flags that the desired data has not been written. This bit has to be software reset.

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Internal Flash memory ST10F276E

Table 17. Flash error register (continued)

Bit Function

Sequence error

SEQER

This bit is automatically set when the control registers (FCR1H/L-FCR0H/L, FARH/L, FDR1H/L-FDR0H/L) are not correctly filled to execute a valid write operation. in this case no write operation is executed. This bit has to be software reset.

Resume error

RESER

This bit is automatically set when a suspended program or erase operation is not resumed correctly due to a protocol error. In this case the suspended operation is aborted. This bit has to be software reset.

Write protection flag This bit is automatically set when trying to program or erase in a sector write

WPF

protected. In case of multiple sector erase, the not protected sectors are erased, while the protected sectors are not erased and bit WPF is set. This bit has to be software reset.

4.3.12 XFlash interface control register

This register is used to configure the XFLASH interface behavior on the XBUS. It allows to set the number of wait states introduced on the XBUS before the internal READY given to the ST10 bus master.

XFICR (0xE E000h) XBUS Reset value: 000Fh

1514131211109876543210

signal is

Reserved WS3 WS2 WS1 WS0

Table 18. XFlash interface control register

Bit Function

Wait state setting These three bits are the binary coding of the number of wait states introduced by the

XFLASH interface through the XBUS internal READY

WS(3:0)

is 1111, that is the up to 15 wait states are set. The following recommendations for the ST10F276E are hereafter reported:

For f For f

> 40MHz1 Wait-StateWS(3:0) = ‘0001’

CPU

≤ 40MHz0 Wait-StateWS(3:0) = ‘0000’

CPU

RW RW RW RW

signal. Default value after reset

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ST10F276E Internal Flash memory

4.4 Protection strategy

The protection bits are stored in non-volatile Flash cells inside XFLASH module, that are read once at reset and stored in 7 Volatile registers. Before they are read from the nonvolatile cells, all the available protections are forced active during reset.

The protections can be programmed using the Set Protection operation (see Flash Control Registers paragraph), that can be executed from all the internal or external memories except from the Flash Bank B2.

Two kind of protections are available: write protections to avoid unwanted writings and access protections to avoid piracy. In next paragraphs all different level of protections are shown, and architecture limitations are highlighted as well.

4.4.1 Protection registers

The seven non-volatile protection registers are one time programmable for the user.

Four registers (FNVWPXRL/H-FNVWPIRL/H) are used to store the Write Protection fuses respectively for each sector of the XFLASH Module (see X) and IFLASH module (see I). The other three Registers (FNVAPR0 and FNVAPR1L/H) are used to store the Access Protection fuses (common to both Flash modules even though with some limitations).

4.4.2 Flash non-volatile write protection X register low

FNVWPXRL (0x0E DFB0) NVR Delivery value: FFFFh

1514131211109876543210

W2PPR

RW RW RW RW

Table 19. Flash non-volatile write protection X register low

Bit Function

Write Protection Bank 2 sectors 2-0 (XFLASH)

W2P(2:0)

W2PPR

These bits, if programmed at 0, disable any write access to the sectors of Bank 2 (XFLASH).

Write Protection Bank 2 non-volatile cells This bit, if programmed at 0, disables any write access to the non-volatile cells of Bank

2. Since these non-volatile cells are dedicated to Protection registers, once W2PPR bit is set, the configuration of protection setting is frozen, and can only be modified executing a Temporary Write Unprotection operation.

Reserved W2P2W2P1W2P0

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Internal Flash memory ST10F276E

4.4.3 Flash non-volatile write protection X register high

FNVWPXRH (0x0E DF B2) NVR Delivery value: FFFFh

1514131211109876543210

Reserved W3P1W3P0

RW RW

Table 20. Flash non-volatile write protection X register high

Bit Function

Write Protection Bank 3 / Sectors 1-0 (XFLASH)

W3P(1:0)

These bits, if programmed at 0, disable any write access to the sectors of Bank 3 (XFLASH).

4.4.4 Flash non-volatile write protection I register low

FNVWPIRL (0x0E DFB4) NVR Delivery value: FFFFh

1514131211109876543210

Reserved W0P9W0P8W0P7W0P6W0P5 W0P4 W0P3 W0P2 W0P1 W0P0

RW RW RW RW RW RW RW RW RW RW

Table 21. Flash non-volatile write protection I register low

Bit Function

Write Protection Bank 0 / Sectors 9-0 (IFLASH)

W0P(9:0)

These bits, if programmed at 0, disable any write access to the sectors of Bank 0 (IFLASH).

4.4.5 Flash non-volatile write protection I register high

FNVWPIRH (0x0E DFB6) NVR Delivery value: FFFFh

1514131211109876543210

Reserved W1P1W1P0

Table 22. Flash non-volatile write protection I register high

Bit Function

Write Protection Bank 1 / Sectors 1-0 (IFLASH)

W1P(1:0)

These bits, if programmed at 0, disable any write access to the sectors of Bank 1 (IFLASH).

RW RW

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ST10F276E Internal Flash memory

4.4.6 Flash non-volatile access protection register 0

Due to ST10 architecture, the XFLASH is seen as external memory: this made impossible to access protect it from real external memory or internal RAM.

FNVAPR0 (0x0E DFB8) NVR Delivery value: ACFFh

1514131211109876543210

DBGP

Reserved

Table 23. Flash non-volatile access protection register 0

Bit Function

Access Protection

ACCP

This bit, if programmed at 0, disables any access (read/write) to data mapped inside IFlash Module address space, unless the current instruction is fetched from one of the two Flash modules.

Debug Protection This bit, if erased at 1, allows to by-pass all the protections using the Debug features

DBGP

through the Test Interface. If programmed at 0, on the contrary, all the debug features, the Test Interface and all the Flash Test Modes are disabled. Even STMicroelectronics will not be able to access the device to run any eventual failure analysis.

ACCP

RW RW

4.4.7 Flash non-volatile access protection register 1 low

FNVAPR1L (0x0E DFBC) NVR Delivery value: FFFFh

1514131211109876543210

PDS15 PDS14 PDS13 PDS12 PDS11 PDS10 PDS9 PDS8 PDS7 PDS6 PDS5 PDS4 PDS3 PDS2 PDS1 PDS0

RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW

Table 24. Flash non-volatile access protection register 1 low

Bit Function

Protections Disable 15-0 If bit PDSx is programmed at 0 and bit PENx is erased at 1, the action of bit ACCP is

PDS(15:0)

disabled. Bit PDS0 can be programmed at 0 only if bits DBGP and ACCP have already been programmed at 0. Bit PDSx can be programmed at 0 only if bit PENx-1 has already been programmed at 0.

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Internal Flash memory ST10F276E

4.4.8 Flash non-volatile access protection register 1 high

FNVAPR1H (0x0E DFBE) NVR Delivery value: FFFFh

1514131211109876543210

PEN15 PEN14 PEN13 PEN12 PEN11 PEN10 PEN9 PEN8 PEN7 PEN6 PEN5 PEN4 PEN3 PEN2 PEN1 PEN0

RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW

Table 25. Flash non-volatile access protection register 1 high

Bit Function

Protections Enable 15-0

PEN15-0

If bit PENx is programmed at 0 and bit PDSx+1 is erased at 1, the action of bit ACCP is enabled again. Bit PENx can be programmed at 0 only if bit PDSx has already been programmed at 0.

4.4.9 Access protection

The Flash modules have one level of access protection (access to data both in Reading and Writing): if bit ACCP of FNVAPR0 is programmed at 0, the IFlash module become access protected: data in the IFlash module can be read/written only if the current execution is from the IFlash module itself.

Protection can be permanently disabled by programming bit PDS0 of FNVAPR1H, in order to analyze rejects. Allowing PDS0 bit programming only when ACCP bit is programmed, guarantees that only an execution from the Flash itself can disable the protections.

Protection can be permanently enabled again by programming bit PEN0 of FNVAPR1L. The action to disable and enable again Access Protections in a permanent way can be executed a maximum of 16 times.

Trying to write into the access protected Flash from internal RAM will be unsuccessful. Trying to read into the access protected Flash from internal RAM will output a dummy data.

When the Flash module is protected in access, also the data access through PEC of a peripheral is forbidden. To read/write data in PEC mode from/to a protected bank, first it is necessary to temporary unprotect the Flash module.

Due to ST10 architecture, the XFLASH is seen as external memory: this makes impossible to access protect it from real external memory or internal RAM. Ta b le 2 6 summarizes all levels of possible Access protection: in particular, supposing to enable all possible access protections, when fetching from a memory as listed in the first column, what is possible and what is not possible to do (see column headers) is shown in the table.

Table 26. Summary of access protection level

Read IFLASH/

Memory fetch source

Fetching from IFLASH Yes / Yes Yes / Yes Yes Yes

Fetching from XFLASH No / Yes Yes / Yes Yes No

Fetching from IRAM No / Yes Yes / Yes Yes No

Jump to

IFLASH

Read XFLASH/

Jump to XFLASH

Read FLASH

Registers

Write FLASH

Registers

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ST10F276E Internal Flash memory

Table 26. Summary of access protection level (continued)

Read IFLASH/

Memory fetch source

Fetching from XRAM No / Yes Yes / Yes Yes No

Fetching from External Memory

4.4.10 Write protection

The Flash modules have one level of Write Protections: each sector of each bank of each Flash Module can be Software Write Protected by programming at 0 the related bit WyPx of FNVWPXRH/L-FNVWPIRH/L registers.

4.4.11 Temporary unprotection

Bits WyPx of FNVWPXRH/L-FNVWPIRH/L can be temporary unprotected by executing the Set Protection operation and writing 1 into these bits.

Bit ACCP can be temporary unprotected by executing the Set Protection operation and writing 1 into these bits, but only if these write instructions are executed from the Flash Modules.

To restore the write and access protection bits it is necessary to reset the microcontroller or to execute a Set Protection operation and write 0 into the desired bits.

Read XFLASH/

Jump to

IFLASH

N o / Ye s Ye s / Ye s Yes N o

Jump to XFLASH

Read FLASH

Registers

Write FLASH

Registers

It is not necessary to temporary unprotect an access protected Flash in order to update the code: it is, in fact, sufficient to execute the updating instructions from another Flash bank.

In reality, when a temporary unprotection operation is executed, the corresponding volatile register is written to 1, while the non-volatile registers bits previously written to 0 (for a protection set operation), will continue to maintain the 0. For this reason, the User software must be in charge to track the current protection status (for instance using a specific RAM area), it is not possible to deduce it by reading the non-volatile register content (a temporary unprotection cannot be detected).

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Internal Flash memory ST10F276E

4.5 Write operation examples

In this section, examples for each kind of Flash write operation are presented.

Word program

Example: 32-bit Word Program of data 0xAAAAAAAA at address 0x0C5554 in XFLASH Module.

FCR0H|= 0x2000; /*Set WPG in FCR0H*/ FARL = 0x5554; /*Load Add in FARL*/ FARH = 0x000C; /*Load Add in FARH*/ FDR0L = 0xAAAA; /*Load Data in FDR0L*/ FDR0H = 0xAAAA; /*Load Data in FDR0H*/ FCR0H|= 0x8000; /*Operation start*/

Double word program

Example: Double Word Program (64-bit) of data 0x55AA55AA at address 0x095558 and data 0xAA55AA55 at address 0x09555C in IFLASH Module.

FCR0H|= 0x1080; /*Set DWPG, SMOD*/ FARL = 0x5558; /*Load Add in FARL*/ FARH = 0x0009; /*Load Add in FARH*/ FDR0L = 0x55AA; /*Load Data in FDR0L*/ FDR0H = 0x55AA; /*Load Data in FDR0H*/ FDR1L = 0xAA55; /*Load Data in FDR1L*/ FDR1H = 0xAA55; /*Load Data in FDR1H*/ FCR0H|= 0x8000; /*Operation start*/

Double Word Program is always performed on the Double Word aligned on a even Word: bit ADD2 of FARL is ignored.

Sector erase

Example: Sector Erase of sectors B3F1 and B3F0 of Bank 3 in XFLASH Module.

FCR0H|= 0x0800; /*Set SER in FCR0H*/ FCR1H|= 0x0003; /*Set B3F1, B3F0*/ FCR0H|= 0x8000; /*Operation start*/

Suspend and resume

Word Program, Double Word Program, and Sector Erase operations can be suspended in the following way:

FCR0H|= 0x4000; /*Set SUSP in FCR0H*/

Then the operation can be resumed in the following way:

FCR0H|= 0x0800; /*Set SER in FCR0H*/ FCR0H|= 0x8000; /*Operation resume*/

Before resuming a suspended Erase, FCR1H/FCR1L must be read to check if the Erase is already completed (FCR1H = FCR1L = 0x0000 if Erase is complete). Original setup of Select Operation bits in FCR0H/L must be restored before the operation resume, otherwise the operation is aborted and bit RESER of FER is set.

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ST10F276E Internal Flash memory

Erase suspend, program and resume

A Sector Erase operation can be suspended in order to program (Word or Double Word) another sector.

Example: Sector Erase of sector B3F1 of Bank 3 in XFLASH Module.

FCR0H|= 0x0800;/*Set SER in FCR0H*/ FCR1H|= 0x0002;/*Set B3F1*/ FCR0H|= 0x8000;/*Operation start*/

Example: Sector Erase Suspend.

FCR0H|= 0x4000;/*Set SUSP in FCR0H*/ do /*Loop to wait for LOCK=0 and WMS=0*/ {tmp1 = FCR0L; tmp2 = FCR0H; } while ((tmp1 && 0x0010) || (tmp2 && 0x8000));

Example: Word Program of data 0x5555AAAA at address 0x0C5554 in XFLASH module.

FCR0H&= 0xBFFF;/*Rst SUSP in FCR0H*/ FCR0H|= 0x2000;/*Set WPG in FCR0H*/ FARL = 0x5554; /*Load Add in FARL*/ FARH = 0x000C; /*Load Add in FARH*/ FDR0L = 0xAAAA; /*Load Data in FDR0L*/ FDR0H = 0x5555; /*Load Data in FDR0H*/ FCR0H|= 0x8000; /*Operation start*/

Once the Program operation is finished, the Erase operation can be resumed in the following way:

FCR0H|= 0x0800;/*Set SER in FCR0H*/ FCR0H|= 0x8000;/*Operation resume*/

Notice that during the Program Operation in Erase suspend, bits SER and SUSP are low. A Word or Double Word Program during Erase Suspend cannot be suspended.

To summarize:

● A Sector Erase can be suspended by setting SUSP bit

● To perform a Word Program operation during Erase Suspend, firstly bits SUSP and

SER must be reset, then bit WPG and WMS can be set

● To resume the Sector Erase operation bit SER must be set again

● In any case it is forbidden to start any write operation with SUSP bit already set

Set protection

Example 1: Enable Write Protection of sectors B0F3-0 of Bank 0 in IFLASH module.

FCR0H|= 0x0100;/*Set SPR in FCR0H*/ FARL = 0xDFB4;/*Load Add of register FNVWPIRL in FARL*/ FARH = 0x000E;/*Load Add of register FNVWPIRL in FARH*/ FDR0L = 0xFFF0;/*Load Data in FDR0L*/ FDR0H = 0xFFFF;/*Load Data in FDR0H*/ FCR0H|= 0x8000;/*Operation start*/

Notice that bit SMOD of FCR0H must not be set, since Write Protection bits of IFLASH Module are stored in Test-Flash (XFLASH Module).

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Internal Flash memory ST10F276E

Example 2: Enable Access and Debug Protection.

FCR0H|= 0x0100;/*Set SPR in FCR0H*/ FARL = 0xDFB8;/*Load Add of register FNVAPR0 in FARL*/ FARH = 0x000E;/*Load Add of register FNVAPR0 in FARH*/ FDR0L = 0xFFFC;/*Load Data in FDR0L*/ FCR0H|= 0x8000;/*Operation start*/

Example 3: Disable in a permanent way Access and Debug Protection.

FCR0H|= 0x0100;/*Set SPR in FCR0H*/ FARL = 0xDFBC;/*Load Add of register FNVAPR1L in FARL*/ FARH = 0x000E;/*Load Add of register FNVAPR1L in FARH*/ FDR0L = 0xFFFE; /*Load Data in FDR0L for clearing PDS0*/ FCR0H|= 0x8000;/*Operation start*/

Example 4: Enable again in a permanent way Access and Debug Protection, after having disabled them.

FCR0H|= 0x0100;/*Set SPR in FCR0H*/ FARL = 0xDFBC;/*Load Add register FNVAPR1H in FARL*/ FARH = 0x000E;/*Load Add register FNVAPR1H in FARH*/ FDR0H = 0xFFFE;/*Load Data in FDR0H for clearing PEN0*/ FCR0H|= 0x8000;/*Operation start*/

Disable and re-enable of Access and Debug Protection in a permanent way (as shown by examples 3 and 4) can be done for a maximum of 16 times.

4.6 Write operation summary

In general, each write operation is started through a sequence of three steps:

1. The first instruction is used to select the desired operation by setting its corresponding selection bit in the Flash Control Register 0. This instruction is also used to select in which Flash Module to apply the Write Operation (by setting/resetting bit SMOD).

2. The second step is the definition of the Address and Data for programming or the Sectors or Banks to erase.

3. The last instruction is used to start the write operation, by setting the start bit WMS in the FCR0.

Once selected, but not yet started, one operation can be canceled by resetting the operation selection bit.

A summary of the available Flash Module Write Operations is shown in Tab le 2 7 .

Table 27. Flash write operations

Operation Select bit Address and data Start bit

Word Program (32-bit) WPG

FARL /FARH

FDR0L/FDR0H

WMS

Double Word Program (64-bit) DWPG

Sector Erase SER FCR1L/FCR1H WMS

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FARL /FARH FDR0L/FDR0H FDR1L/FDR1H

WMS

ST10F276E Internal Flash memory

Table 27. Flash write operations (continued)

Operation Select bit Address and data Start bit

Set Protection SPR FDR0L/FDR0H WMS

Program/Erase Suspend SUSP None None

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Bootstrap loader ST10F276E

5 Bootstrap loader

ST10F276E implements innovative boot capabilities in order to

● support a user defined bootstrap (see Alternate bootstrap loader);

● support bootstrap via UART or bootstrap via CAN for the standard bootstrap.

5.1 Selection among user-code, standard or alternate bootstrap

The selection among user-code, standard bootstrap or alternate bootstrap is made by special combinations on Port0L[5...4] during the time the reset configuration is latched from Por t0.

The alternate boot mode is triggered with a special combination set on Port0L[5...4]. Those signals, as other configuration signals, are latched on the rising edge of RSTIN

The alternate boot function is divided in two functional parts (which are independent from each other):

Part 1: Selection of reset sequence according to the Port0 configuration: User mode and alternate mode signatures

● Decoding of reset configuration (P0L.5 = 1, P0L.4 = 1) selects the normal mode and

the user Flash to be mapped from address 00’0000h.

● Decoding of reset configuration (P0L.5 = 1, P0L.4 = 0) selects ST10 standard bootstrap

mode (Test-Flash is active and overlaps user Flash for code fetches from address 00'0000h; user Flash is active and available for read and program).

● Decoding of reset configuration (P0L.5 = 0, P0L.4 = 1) activates new verifications to

select which bootstrap software to execute:

– if the user mode signature in the user Flash is programmed correctly, then a

software reset sequence is selected and the user code is executed;

– if the user mode signature is not programmed correctly but the alternate mode

signature in the user Flash is programmed correctly, then the alternate boot mode is selected;

– if both the user and the alternate mode signatures are not programmed correctly in

the user Flash, then the user key location is read again. Its value will determine the behavior of the selected bootstrap loader.

pin.

Part 2: Running of user selected reset sequence

● Standard bootstrap loader: Jump to a predefined memory location in Test-Flash

(controlled by ST)

● Alternate boot mode: Jump to address 09’0000h

● Selective bootstrap loader: Jump to a predefined location in Test-Flash (controlled by

ST) and check which communication channel is selected

● User code: Make a software reset and jump to 00’0000h

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ST10F276E Bootstrap loader

Table 28. ST10F276E boot mode selection

P0.5 P0.4 ST10 decoding

1 1 User mode: User Flash mapped at 00’0000h

0 1 Alternate boot mode: Flash mapping depends on signatures integrity check

00Reserved

Standard bootstrap loader: User Flash mapped from 00’0000h; code fetches redirected to Test-Flash at 00’0000h

5.2 Standard bootstrap loader

The built-in bootstrap loader of the ST10F276E provides a mechanism to load the startup program, which is executed after reset, via the serial interface. In this case no external (ROM) memory or an internal ROM is required for the initialization code starting at location 00’0000 transfer data via the serial interface into an external RAM using a second level loader routine. ROM memory (internal or external) is not necessary. However, it may be used to provide lookup tables or may provide “core-code”, that is, a set of general purpose subroutines, such as for I/O operations, number crunching or system initialization.

. The bootstrap loader moves code/data into the IRAM but it is also possible to

The Bootstrap Loader can load

● the complete application software into ROMless systems,

● temporary software into complete systems for testing or calibration,

● a programming routine for Flash devices.

The BSL mechanism may be used for standard system start-up as well as for only special occasions like system maintenance (firmware update) or end-of-line programming or testing.

5.2.1 Entering the standard bootstrap loader

As with the old ST10 bootstrap mode, the ST10F276E enters BSL mode if pin P0L.4 is sampled low at the end of a hardware reset. In this case, the built-in bootstrap loader is activated independently of the selected bus mode. The bootstrap loader code is stored in a special Test-Flash; no part of the standard Flash memory area is required for this.

After entering BSL mode and the respective initialization, the ST10F276E scans the RxD0 line and the CAN1_RxD line to receive either a valid dominant bit from the CAN interface or a start condition from the UART line.

Start condition on UART RxD: The ST10F276E starts the standard bootstrap loader. This bootstrap loader is identical to other ST10 devices (Examples: ST10F269, ST10F168). See

Section 5.3 for details.

Valid dominant bit on CAN1 RxD: The ST10F276E starts bootstrapping via CAN1; the bootstrapping method is new and is described in Section 5.4. Figure 5 shows the program flow of the new bootstrap loader. It clearly illustrates how the new functionalities are implemented:

● UART: UART has priority over CAN after a falling edge on CAN1_RxD until the first

valid rising edge on CAN1_RxD;

● CAN: Pulses on CAN1_RxD shorter than 20*CPU-cycles are filtered.

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Bootstrap loader ST10F276E

5.2.2 ST10 configuration in BSL

When the ST10F276E has entered BSL mode, the configuration shown in Tab l e 29 is automatically set (values that deviate from the normal reset values are marked in bold).

Table 29. ST10 configuration in BSL mode

Function or register Access Notes

Watchdog Timer Disabled

0404H

Context Pointer CP FA00

Stack Pointer SP FA40

acc. to startup config.

(1)

XPEN bit set for Bootstrap via CAN or Alternate Boot Mode

(2)

Initialized only if Bootstrap via UART

P3.10 / TXD0 ‘1’ Initialized only if Bootstrap via UART

DP3.10 ‘1’ Initialized only if Bootstrap via UART

CAN1 Status/Control Register

0000

Initialized only if Bootstrap via CAN

CAN1 Bit Timing Register acc. to ‘0’ frame Initialized only if Bootstrap via CAN

XPERCON 042D

XRAM1-2, XFlash, CAN1 and XMISC enabled. Initialized only if Bootstrap via CAN

P4.6 / CAN1_TxD ‘1’ Initialized only if Bootstrap via CAN

DP4.6 ‘1’ Initialized only if Bootstrap via CAN

1. In Bootstrap modes (standard or alternate) ROMEN, bit 10 of SYSCON, is always set regardless of EA pin level. BYTDIS, bit 9 of SYSCON, is set according to data bus width selection via Port0 configuration.

2. BUSCON0 is initialized with 0000h, external bus disabled, if pin EA is high during reset. If pin EA is low during reset, BUSACT0, bit 10, and ALECTL0, bit 9, are set enabling the external bus with lengthened ALE signal. BTYP field, bit 7 and 6, is set according to Port0 configuration.

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ST10F276E Bootstrap loader

Figure 5. ST10F276E new standard bootstrap loader program flow

START

Falling-edge on

UART0 RxD?

UART BOOT

Start timer T6

UART0 RxD = 1?

Stop timer T6

Initialize UART

Send acknowledge

Address = FA40h

Byte received?

[Address] = S0RBUF

Address = Address + 1

Address = FA60h?

Ye s

Falling-edge on

CAN1 RxD?

Start timer PT0

UART RxD = 0?

CAN1 RxD = 1?

PT0 > 20?

Count = 1

CAN RxD = 0?

CAN1 RxD = 1?

CAN BOOT

Glitch on CAN1 RxD

Stop timer PT0

Clear timer PT0

Message received?

UART BOOT

Count += 1

Count = 5?

Stop timer PT0

Initialize CAN

Address = FA40h

[Address] = MO15_data0

Address = Address + 1

Address = FAC0h?

CAN BOOT

Jump to address FA40h

Other than after a normal reset the watchdog timer is disabled, so the bootstrap loading sequence is not time limited. Depending on the selected serial link (UART0 or CAN1), pin TxD0 or CAN1_TxD is configured as output, so the ST10F276E can return the acknowledge byte. Even if the internal IFLASH is enabled, a code cannot be executed from it.

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Bootstrap loader ST10F276E

5.2.3 Booting steps

As Figure 6 shows, booting ST10F276E with the boot loader code occurs in a minimum of four steps:

1. The ST10F276E is reset with P0L.4 low.

2. The internal new bootstrap code runs on the ST10 and a first level user code is

downloaded from the external device, via the selected serial link (UART0 or CAN1). The bootstrap code is contained in the ST10F276E Test-Flash and is automatically run when ST10F276E is reset with P0L.4 low. After loading a preselected number of bytes, ST10F276E begins executing the downloaded program.

3. The first level user code runs on ST10F276E. Typically, this first level user code is

another loader that downloads the application software into the ST10F276E.

4. The loaded application software is now running.

Figure 6. Booting steps for ST10F276E

Step 1

Entering bootstrap

Loading first level user code

Step 2

Step 3

Loading the application

and exiting BSL

Step 4

5.2.4 Hardware to activate BSL

The hardware that activates the BSL during reset may be a simple pull-down resistor on P0L.4 for systems that use this feature at every hardware reset. For systems that use the bootstrap loader only temporarily, it may be preferable to use a switchable solution (via jumper or an external signal).

External device

Download

First level user code

Download

Application

ST10F276E

Link

Serial

ST10F276E

Link

Serial

Run bootstrap code

from Test-Flash

ST10F276E

Link

Serial

Run first level code

from DPRAM @ FA40h

ST10F276E

Link

Serial

Run application code

Note: CAN alternate function on Port4 lines is not activated if the user has selected eight address

segments (Port4 pins have three functions: I/O port, address segment and CAN). Boot via CAN requires that four or less address segments are selected.

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ST10F276E Bootstrap loader

Figure 7. Hardware provisions to activate the BSL

External signal

Normal boot

P0L.4

8kΩ max.

P0L.4

BSL

P0L.4

8kΩ max.

Circuit 1

5.2.5 Memory configuration in bootstrap loader mode

The configuration (that is, the accessibility) of the ST10F276E’s memory areas after reset in Bootstrap Loader mode differs from the standard case. Pin EA is selected to enable or to not enable the external bus:

● If EA = 1, the external bus is disabled (BUSACT0 = 0 in BUSCON0 register);

● If EA = 0, the external bus is enabled (BUSACT0 = 1 in BUSCON0 register).

Moreover, while in BSL mode, accesses to the internal IFLASH area are partially redirected:

● All code accesses are made from the special Test-Flash seen in the range 00’0000h to

00’01FFFh;

● User IFLASH is only available for read and write accesses (Test-Flash cannot be read

or written);

● Write accesses must be made with addresses starting in segment 1 from 01'0000h,

regardless of the value of ROMS1 bit in SYSCON register;

● Read accesses are made in segment 0 or in segment 1 depending on the ROMS1

value;

● In BSL mode, by default, ROMS1 = 0, so the first 32 Kbytes of IFlash are mapped in

segment 0.

Example:

In default configuration, to program address 0, the user must put the value 01'0000h in the FARL and FARH registers but to verify the content of the address 0 a read to 00'0000h must be performed.

Circuit 2

is evaluated when BSL mode

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Bootstrap loader ST10F276E

Figure 8. Memory configuration after reset

16 Mbytes

int. RAM

255

access to external bus disabled

access to int. Flash enabled

user Flash

Test-Flash

int. RAM

Test-Flash

255

access to external bus enabled

access to int. Flash enabled

user Flash

int. RAM

255

Depends on reset config. (EA, P0)

Depends on reset config.

user Flash

BSL mode active Yes (P0L.4 = ‘0’) Yes (P0L.4 = ‘0’) No (P0L.4 = ‘1’)

pin High Low According to application

Code fetch from internal Flash area

Data fetch from internal Flash area

Test-Flash access Test-Flash access User IFLASH access

User IFLASH access User IFLASH access User IFLASH access

Note: As long as ST10F276E is in BSL, the user’s software should not try to execute code from

the internal IFlash, as the fetches are redirected to the Test-Flash.

5.2.6 Loading the start-up code

After the serial link initialization sequence (see following chapters), the BSL enters a loop to receive 32 bytes (boot via UART) or 128 bytes (boot via CAN).

These bytes are stored sequentially into ST10F276E Dual-Port RAM from location 00’FA40h.

To execute the loaded code, the BSL then jumps to location 00’FA40h. The bootstrap sequence running from the Test-Flash is now terminated; however, the microcontroller remains in BSL mode.

Most probably, the initially loaded routine, being the first level user code, will load additional code and data. This first level user code may use the pre-initialized interface (UART or CAN) to receive data and a second level of code, and store it in arbitrary user-defined locations.

This second level of code may be

● the final application code

● another, more sophisticated, loader routine that adds a transmission protocol to

enhance the integrity of the loaded code or data

● a code sequence to change the system configuration and enable the bus interface to

store the received data into external memory

In all cases, the ST10F276E still runs in BSL mode, that is, with the watchdog timer disabled and limited access to the internal IFLASH area.

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ST10F276E Bootstrap loader

5.2.7 Exiting bootstrap loader mode

To execute a program in normal mode, the BSL mode must first be terminated. The ST10F276E exits BSL mode at a software reset (level on P0L.4 is ignored) or a hardware reset (P0L.4 must be high in this case). After the reset, the ST10F276E starts executing from location 00’0000 programmed via pin EA

of the internal Flash (User Flash) or the external memory, as

Note: If a bidirectional software reset is executed and external memory boot is selected (EA

a degeneration of the software reset event into a hardware reset can occur (refer to

Section 19.3: Synchronous reset (warm reset) for details). This implies that P0L.4 becomes

transparent, so to exit from Bootstrap mode it would be necessary to release pin P0L.4 (it is no longer ignored).

5.2.8 Hardware requirements

Although the new bootstrap loader is designed to be compatible with the old bootstrap loader, there are a few hardware requirements relative to the new bootstrap loader:

– External Bus configuration: Must have four or less segment address lines (keep

CAN I/Os available);

– Usage of CAN pins (P4.5 and P4.6): Even in bootstrap via UART, P4.5

(CAN1_RxD) can be used as Port input but not as output. The pin P4.6 (CAN1_TxD) can be used as input or output.

– Level on UART RxD and CAN1_RxD during the bootstrap phase (see Figure 6 -

Step 2): Must be 1 (external pull-ups recommended).

5.3 Standard bootstrap with UART (RS232 or K-Line)

5.3.1 Features

ST10F276E bootstrap via UART has the same overall behavior as the old ST10 bootstrap via UART:

● Same bootstrapping steps

● Same bootstrap method: Analyze the timing of a predefined byte, send back an

acknowledge byte, load a fixed number of bytes and run

● Same functionalities: Boot with different crystals and PLL ratios

=0),

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Bootstrap loader ST10F276E

Figure 9. UART bootstrap loader sequence

RSTIN

P0L.4

(1)

(2)

RxD0

TxD0

CSP:IP

(6)

Int. Boot ROM / Test-Flash BSL-routine

1. BSL initialization time, > 1ms @ f

2. Zero byte (1 start bit, eight ‘0’ data bits, 1 stop bit), sent by host

3. Acknowledge byte, sent by ST10F276E

4. 32 bytes of code / data, sent by host

5. Caution: TxD0 is only driven a certain time after reception of the zero byte (1.3ms @ f

6. Internal Boot ROM / Test-Flash

= 40 MHz

CPU

5.3.2 Entering bootstrap via UART

The ST10F276E enters BSL mode if pin P0L.4 is sampled low at the end of a hardware reset. In this case, the built-in bootstrap loader is activated independently of the selected bus mode. The bootstrap loader code is stored in a special Test-Flash; no part of the standard mask ROM or Flash memory area is required for this.

(4)

(3)

(5)

32 bytes

user software

= 40 MHz).

CPU

After entering BSL mode and the respective initialization, the ST10F276E scans the RxD0 line to receive a zero byte, that is, 1 start bit, eight ‘0’ data bits and 1 stop bit. From the duration of this zero byte, it calculates the corresponding baud rate factor with respect to the current CPU clock, initializes the serial interface ASC0 accordingly and switches pin TxD0 to output. Using this baud rate, an acknowledge byte is returned to the host that provides the loaded data.

The acknowledge byte is D5h for the ST10F276E.

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ST10F276E Bootstrap loader

5.3.3 ST10 Configuration in UART BSL (RS232 or K-Line)

When the ST10F276E enters BSL mode on UART, the configuration shown in Ta bl e 3 0 is automatically set (values that deviate from the normal reset values are marked in bold).

Table 30. ST10 configuration in UART BSL mode (RS232 or K-line)

Function or register Access Notes

Watchdog timer Disabled

Context Pointer CP FA00

Stack Pointer SP FA40

(1)

(2)

P3.10 / TXD0 ‘1’ Initialized only if Bootstrap via UART

DP3.10 ‘1’ Initialized only if Bootstrap via UART

Other than after a normal reset, the watchdog timer is disabled, so the bootstrap loading sequence is not time limited. Pin TxD0 is configured as output, so the ST10F276E can return the acknowledge byte. Even if the internal IFLASH is enabled, a code cannot be executed from it.

5.3.4 Loading the start-up code

After sending the acknowledge byte, the BSL enters a loop to receive 32 bytes via ASC0. These bytes are stored sequentially into locations 00’FA40 allowing up to 16 instructions to be placed into the RAM area. To execute the loaded code the BSL then jumps to location 00’FA40H, that is, the first loaded instruction. The bootstrap loading sequence is now terminated; however, the ST10F276E remains in BSL mode. The initially loaded routine will most probably load additional code or data, as an average application is likely to require substantially more than 16 instructions. This second receive loop may directly use the pre-initialized interface ASC0 to receive data and store it in arbitrary user-defined locations.

Initialized only if Bootstrap via UART

through 00’FA5FH of the IRAM,

This second level of loaded code may be

● the final application code

● another, more sophisticated, loader routine that adds a transmission protocol to

enhance the integrity of the loaded code or data

● a code sequence to change the system configuration and enable the bus interface to

store the received data into external memory

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Bootstrap loader ST10F276E

This process may go through several iterations or may directly execute the final application. In all cases the ST10F276E still runs in BSL mode, that is, with the watchdog timer disabled and limited access to the internal Flash area. All code fetches from the internal IFLASH area (01’0000

...08’FFFFH) are redirected to the special Test-Flash. Data read operations

access the internal Flash of the ST10F276E.

5.3.5 Choosing the baud rate for the BSL via UART

The calculation of the serial baud rate for ASC0 from the length of the first zero byte that is received allows the operation of the bootstrap loader of the ST10F276E with a wide range of baud rates. However, the upper and lower limits must be kept to ensure proper data transfer.

Equation 1

CPU

ST10F276E

The ST10F276E uses timer T6 to measure the length of the initial zero byte. The quantization uncertainty of this measurement implies the first deviation from the real baud rate; the next deviation is implied by the computation of the S0BRL reload value from the timer contents. The formula below shows the association:

------------------------------------------ -

32 S0BRL 1

+()⋅

Equation 2

For a correct data transfer from the host to the ST10F276E, the maximum deviation between the internal initialized baud rate for ASC0 and the real baud rate of the host should be below 2.5%. The deviation (F baud rate can be calculated using the formula below:

Equation 3

Note: Function (F

the serial communication.

This baud rate deviation is a nonlinear function depending on the CPU clock and the baud rate of the host. The maxima of the function (F the smaller baud rate prescaler factors and the implied higher quantization error (see

Figure 10).

CPU

S0BRL

) does not consider the tolerances of oscillators and other devices supporting

T6 36–

------------------- -=

, in percent) between host baud rate and ST10F276E

ContrBHost

--------------------------------------- -

Contr

–

---------------

⋅=

Host

100⋅=

FB2.5≤

) increases with the host baud rate due to

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ST10F276E Bootstrap loader

Figure 10. Baud rate deviation between host and ST10F276E

2.5%

Low

The minimum baud rate (B of timer T6, when measuring the zero byte, that is, it depends on the CPU clock. Using the maximum T6 count 2

High

in Figure 10) is determined by the maximum count capacity

Low

in the formula the minimum baud rate is calculated. The lowest

standard baud rate in this case would be 1200 baud. Baud rates below B

would cause

Low

HOST

T6 to overflow. In this case, ASC0 cannot be initialized properly.

The maximum baud rate (B still does not exceed the limit, that is, all baud rates between B

in Figure 10) is the highest baud rate where the deviation

High

Low

and B

are below the

High

deviation limit. The maximum standard baud rate that fulfills this requirement is 19200 baud.

Higher baud rates, however, may be used as long as the actual deviation does not exceed the limit. A certain baud rate (marked “I” in Figure 10) may, for example, violate the deviation limit, while an even higher baud rate (marked “II” in Figure 10) stays well below it. This depends on the host interface.

5.4 Standard bootstrap with CAN

5.4.1 Features

The bootstrap via CAN has the same overall behavior as the bootstrap via UART:

● Same bootstrapping steps;

● Same bootstrap method: Analyze the timing of a predefined frame, send back an

acknowledge frame BUT only on request

● Same functionalities: Boot with different crystals and PLL ratios.

, load a fixed number of bytes and run;

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Bootstrap loader ST10F276E

Figure 11. CAN bootstrap loader sequence

RSTIN

P0L.4

CAN1_RxD

CAN1_TxD

CSP:IP

1. BSL initialization time, > 1ms @ f

2. Zero frame (CAN message: standard ID = 0, DLC = 0), sent by host

3. CAN message (standard ID = E6h, DLC = 3, Data0 = D5h, Data1-Data2 = IDCHIP_low-high), sent by ST10F276E on request

4. 128 bytes of code / data, sent by host

5. Caution: CAN1_TxD is only driven a certain time after reception of the zero byte (1.3ms @ f

6. Internal Boot ROM / Test-Flash

(1)

(2)

(3)

(5)

Int. Boot ROM / Test-Flash BSL-routine

(6)

= 40 MHz

CPU

(4)

128 bytes

user software

= 40 MHz).

CPU

The Bootstrap Loader can load

● the complete application software into ROM-less systems,

● temporary software into complete systems for testing or calibration,

● a programming routine for Flash devices.

The BSL mechanism may be used for standard system start-up as well as for only special occasions like system maintenance (firmware update) or end-of-line programming or testing.

5.4.2 Entering the CAN bootstrap loader

After entering BSL mode and the respective initialization, the ST10F276E scans the CAN1_TxD line to receive the following initialization frame:

● Standard identifier = 0h

● DLC = 0h

As all the bits to be transmitted are dominant bits, a succession of 5 dominant bits and 1 stuff bit on the CAN network is used. From the duration of this frame, it calculates the corresponding baud rate factor with respect to the current CPU clock, initializes the CAN1 interface accordingly, switches pin CAN1_TxD to output and enables the CAN1 interface to take part in the network communication. Using this baud rate, a Message Object is

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ST10F276E Bootstrap loader

configured in order to send an acknowledge frame. The ST10F276E will not send this Message Object but the host can request it by sending a remote frame.

The acknowledge frame is the following for the ST10F276E:

– Standard identifier = E6h

– DLC = 3h

– Data0 = D5h, that is, generic acknowledge of the ST10 devices

– Data1 = IDCHIP least significant byte

– Data2 = IDCHIP most significant byte

For the ST10F276E, IDCHIP = 114Xh.

Note: Two behaviors can be distinguished in ST10 acknowledging to the host. If the host is

behaving according to the CAN protocol, as at the beginning the ST10 CAN is not configured, the host is alone on the CAN network and does not receive an acknowledge. It automatically resends the zero frame. As soon as the ST10 CAN is configured, it acknowledges the zero frame. The “acknowledge frame” with identifier 0xE6 is configured, but the Transmit Request is not set. The host can request this frame to be sent and therefore obtains the IDCHIP by sending a remote frame.

Hint: As the IDCHIP is sent in the acknowledge frame, Flash programming software now can immediately identify the exact type of device to be programmed.

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5.4.3 ST10 configuration in CAN BSL

When the ST10F276E enters BSL mode via CAN, the configuration shown in Ta bl e 3 1 is automatically set (values that deviate from the normal reset values are marked in bold).

Table 31. ST10 configuration in CAN BSL

Function or register Access Notes

Watchdog timer Disabled

Context pointer CP FA00

Stack pointer SP FA40

CAN1 Status/Control register 0000

CAN1 Bit timing register acc. to ‘0’ frame Initialized only if Bootstrap via CAN

XPERCON 042D

P4.6 / CAN1_TxD ‘1’ Initialized only if Bootstrap via CAN

(1)

0404H

acc. to startup

(2)

config.

XPEN bit set

Initialized only if Bootstrap via CAN

XRAM1-2, XFlash, CAN1 and XMISC enabled

DP4.6 ‘1’ Initialized only if Bootstrap via CAN

Other than after a normal reset, the watchdog timer is disabled, so the bootstrap loading sequence is not time limited. Pin CAN1_TxD1 is configured as output, so the ST10F276E can return the identification frame. Even if the internal IFLASH is enabled, a code cannot be executed from it.

5.4.4 Loading the start-up code via CAN

After sending the acknowledge byte, the BSL enters a loop to receive 128 bytes via CAN1.

Hint: The number of bytes loaded when booting via the CAN interface has been extended to 128 bytes to allow the reconfiguration of the CAN Bit Timing Register with the best timings (synchronization window, ...). This can be achieved by the following sequence of instructions:

ReconfigureBaud rate:

MOV R1,#041h MOV DPP3:0EF00h,R1; Put CAN in Init, enable Configuration Change MOV R1,#01600h MOV DPP3:0EF06h,R1; 1MBaud at Fcpu = 20 MHz

These 128 bytes are stored sequentially into locations 00’FA40 IRAM, allowing up to 64 instructions to be placed into the RAM area. To execute the loaded code the BSL then jumps to location 00’FA40 bootstrap loading sequence is now terminated; however, the ST10F276E remains in BSL

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through 00’FABFH of the

, that is, the first loaded instruction. The

ST10F276E Bootstrap loader

mode. Most probably the initially loaded routine will load additional code or data, as an average application is likely to require substantially more than 64 instructions. This second receive loop may directly use the pre-initialized CAN interface to receive data and store it in arbitrary user-defined locations.

This second level of loaded code may be

● the final application code

● another, more sophisticated, loader routine that adds a transmission protocol to

enhance the integrity of the loaded code or data

● a code sequence to change the system configuration and enable the bus interface to

store the received data into external memory

...08’FFFFH) are redirected to the special Test-Flash. Data read operations will

access the internal Flash of the ST10F276E.

5.4.5 Choosing the baud rate for the BSL via CAN

The Bootstrap via CAN acts the same way as in the UART bootstrap mode. When the ST10F276E is started in BSL mode, it polls the RxD0 and CAN1_RxD lines. When polling a low level on one of these lines, a timer is launched that is stopped when the line returns to high level.

For CAN communication, the algorithm is made to receive a zero frame, that is, the standard identifier is 0x0, DLC is 0. This frame produces the following levels on the network: 5D, 1R, 5D, 1R, 5D, 1R, 5D, 1R, 5D, 1R, 4D, 1R, 1D, 11R. The algorithm lets the timer run until the detection of the 5 bit times: This minimizes the error introduced by the polling

recessive bit. This way the bit timing is calculated over the duration of 29

Figure 12. Bit rate measurement over a predefined zero-frame

Start Stuff bit Stuff bit Stuff bit Stuff bit

........

Measured time

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Bootstrap loader ST10F276E

Error induced by the polling

The code used for the polling is the following:

WaitCom:

JNB P4.5,CAN_Boot ; if SOF detected on CAN, then go to

CAN

; loader JB P3.11,WaitCom ; Wait for start bit at RxD0 BSET T6R ; Start Timer T6

....

CAN_Boot:

BSET PWMCON0.0 ; Start PWM Timer0

; (resolution is 1 CPU clk cycle) JMPR cc_UC,WaitRecessiveBit

WaitDominantBit:

JB P4.5,WaitDominantBit; wait for end of stuff bit

WaitRecessiveBit:

JNB P4.5,WaitRecessiveBit; wait for 1st dominant bit = Stuff

bit

CMPI1R1,#5 ; Test if 5th stuff bit detected JMPR cc_NE,WaitDominantBit; No, go back to count more BCLR PWMCON.0 ; Stop timer

; here the 5th stuff bit is detected:

; PT0 = 29 Bit_Time (25D and 4R)

Therefore the maximum error at the detection of the communication on CAN pin is:

(1 not taken + 1 taken jumps) + 1 taken jump + 1 bit set: (6) + 6 CPU clock cycles

The error at the detection for the 5

recessive bit is:

(1 taken jump) + 1 not taken jump + 1 compare + 1 bit clear: (4) + 6 CPU cycles

In the worst case, the induced error is 6 CPU clock cycles, so the polling could induce an error of 6 timer ticks.

Error induced by the baud rate calculation

The content of the timer PT0 counter corresponds to 29 bit times, resulting in the following equation:

PT0 = 58 x (BRP + 1) X (1 + Tseg1 + Tseg2)

where BRP, Tseg1 and Tseg2 are the field of the CAN Bit Timing register.

The CAN protocol specification recommends to implement a bit time composed of at least 8 time quanta (tq). This recommendation is applied here. Moreover, the maximum bit time length is 25 tq. To ensure precision, the aim is to have the smallest Bit Rate Prescaler (BRP) and the maximum number of tq in a bit time.

This gives the following ranges for PT0 according to BRP:

8 ≤ 1 + Tseg1 + Tseg2 ≤ 25

464 x (1 + BRP) ≤ PT0 ≤ 1450 x (1 + BRP)

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ST10F276E Bootstrap loader

Table 32. BRP and PT0 values

BRP PT0_min PT0_max Comments

0 464 1450

1 1451 2900

2 2901 4350

3 4351 5800

4 5801 7250

5 7251 8700

.. .. ..

43 20416 63800

44 20880 65250

45 21344 66700 Possible timer overflow

.. .. ..

63 X X

The error coming from the measurement of the 29 bit is:

= 6 / [PT0]

It is maximal for the smallest BRP value and the smallest number of ticks in PT0. Therefore:

= 1.29%

1 Max

To improve precision, the aim is to have the smallest BRP so that the time quantum is the smallest possible. Thus, an error on the calculation of time quanta in a bit time is minimal.

In order to do so, the value of PT0 is divided into ranges of 1450 ticks. In the algorithm, PT0 is divided by 1451 and the result is BRP.

The calculated BRP value is then used to divide PT0 in order to have the value of (1 + Tseg1 + Tseg2). A table is made to set the values for Tseg1 and Tseg2 according to the value of (1 + Tseg1 + Tseg2). These values of Tseg1 and Tseg2 are chosen in order to reach a sample point between 70% and 80% of the bit time.

During the calculation of (1 + Tseg1 + Tseg2), an error e

can be introduced by the division.

This error is of 1 time quantum maximum.

To compensate for any possible error on bit rate, the (Re)Synchronization Jump Width is fixed to 2 time quanta.

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Bootstrap loader ST10F276E

5.4.6 Computing the baud rate error

Considering the following conditions, a computation of the error is given as an example.

● CPU frequency: 20 MHz

● Target Bit Rate: 1 Mbit/s

In these conditions, the content of PT0 timer for 29 bits should be:

PT0[]

29 Fcpu×

-------------------------- BitRate

29 20× 6×

---------------------------- - 580===

110

Therefore:

574 < [PT0] < 586

This gives:

BRP = 0

tq = 100 ns

Computation of 1 + Tseg1 + Tseg2: Considering the equation:

[PT0] = 58 x (1 + BRP) x (1 + Tseg1 + Tseg2)

Thus:

574

--------- -

Tseg1 Tseg2

586

----------10=≤+≤=

In the algorithm, a rounding up to the superior value is made if the remainder of the division is greater than half of the divisor. This would have been the case if the PT0 content was 574. Thus, in this example the result is 1 + Tseg1 + Tseg2 = 10, giving a bit time of exactly 1µs => no error in bit rate.

Note: In most cases (24 MHz, 32 MHz, 40 MHz of CPU frequency and 125, 250, 500 or 1Mb/s of

bit rate), there is no error. Nevertheless, it is better to check for an error with the real application parameters.

The content of the bit timing register is: 0x1640. This gives a sample point at 80%.

Note: The (Re)Synchronization Jump Width is fixed to 2 time quanta.

5.4.7 Bootstrap via CAN

After the bootstrap phase, the ST10F276E CAN module is configured as follows:

● The pin P4.6 is configured as output (the latch value is ‘1’ = recessive) to assume

CAN1_TxD function.

● The MO2 is configured to output the acknowledge of the bootstrap with the standard

identifier E6h, a DLC of 3 and Data0 = D5h, Data1 and 2 = IDCHIP.

● The MO1 is configured to receive messages with the standard identifier 5h. Its

acceptance mask is set to ensure that all bits match. The DLC received is not checked: The ST10 expects only 1 byte of data at a time.

No other message is sent by the ST10F276E after the acknowledge.

Note: The CAN boot waits for 128 bytes of data instead of 32 bytes (see UART boot). This is done

to allow the User to reconfigure the CAN bit rate as soon as possible.

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ST10F276E Bootstrap loader

5.5 Comparing the old and the new bootstrap loader

Ta bl e 3 3 and Ta bl e 3 4 summarize the differences between the old ST10 (boot via UART

only) bootstrap and the new one (boot via UART or CAN).

5.5.1 Software aspects

As the CAN1 is needed, XPERCON register is configured by the bootstrap loader code and bit XPEN of SYSCON is set. However, as long as the EINIT instruction is not executed (and it is not in the bootstrap loader code), the settings can be modified. To do this, perform the following steps:

1. Disable the XPeripherals by clearing XPEN in SYSCON register. Attention: If this part of the code is located in XRAM, it will be disabled.

2. Enable the needed XPeripherals by writing the correct value in XPERCON register.

3. Set XPEN bit in SYSCON.

Table 33. Software topics summary

Former bootstrap loader New bootstrap loader Comments

For compatibility between boot

Uses only 32 bytes in Dual-Port RAM from 00’FA40h

Loads 32 bytes from UART

Uses up to 128 bytes in DualPort RAM from 00’FA40h

Loads 32 bytes from UART (boot via UART mode)

via UART and boot via CAN1, please avoid loading the application software in the 00’FA60h/00’FABFh range.

Same files can be used for boot via UART.

User selected Xperipherals can be enabled during boot (Step 3 or Step 4).

5.5.2 Hardware aspects

Although the new bootstrap loader is designed to be compatible with the old bootstrap loader, there are a few hardware requirements for the new bootstrap loader as summarized in Ta bl e 3 4.

Table 34. Hardware topics summary

Former bootstrap loader New bootstrap loader Comments

P4.5 can be used as output in BSL mode.

Level on CAN1_RxD can change during boot Step 2.

Xperipherals selection is fixed.

P4.5 cannot be used as user output in BSL mode, but only as CAN1_RxD or input or address segments.

Level on CAN1_RxD must be stable at ‘1’ during boot Step 2.

User can change the Xperipherals selections through a specific code.

External pull-up on P4.5 needed.

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Bootstrap loader ST10F276E

5.6 Alternate boot mode (ABM)

5.6.1 Activation

Alternate boot is activated with the combination ‘01’ on Port0L[5..4] at the rising edge of RSTIN

5.6.2 Memory mapping

The ST10F276E has the same memory mapping for standard boot mode and for alternate boot mode:

● Test-Flash: Mapped from 00’0000h. The Standard Bootstrap Loader can be started by

● User Flash: The User Flash is divided in two parts: The IFLASH, visible only for

● All ST10F276E XRAM and Xperipherals modules can be accessed if enabled in

Note: The alternate boot mode can be used to reprogram the whole content of the ST10F276E

User Flash (except Block 0 in Bank 2, where the alternate boot is mapped into).

executing a jump to the address of this routine (JMPS 00’xxxx; address to be defined).

memory reads and memory writes (no code fetch) and the XFLASH, visible for any ST10 access (memory read, memory write and code fetch).

XPERCON register.

5.6.3 Interrupts

The ST10 interrupt vector table is always mapped from address 00’0000h.

As a consequence, interrupts are not allowed in Alternate Boot Mode; all maskable and nonmaskable interrupts must be disabled.

5.6.4 ST10 configuration in alternate boot mode

When the ST10F276E enters BSL mode via CAN, the configuration shown in Ta bl e 3 5 is automatically set (values that deviate from the normal reset values are marked in bold).

Table 35. ST10 configuration in alternate boot mode

Function or register Access Notes

Watchdog timer Disabled

Context pointer CP FA00

Stack pointer SP FA40

XPERCON 002D

1. In Bootstrap modes (standard or alternate) ROMEN, bit 10 of SYSCON, is always set regardless of EA pin

level. BYTDIS, bit 9 of SYSCON, is set according to data bus width selection via Port0 configuration.

2. BUSCON0 is initialized with 0000h, external bus disabled, if pin EA is high during reset. If pin EA is low

during reset, BUSACT0, bit 10, and ALECTL0, bit 9, are set enabling the external bus with lengthened ALE signal. BTYP field, bit 7 and 6, is set according to Port0 configuration.

(1)

acc. to startup config.

XPEN bit set

(2)

XRAM1-2, XFlash, CAN1 enabled

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ST10F276E Bootstrap loader

Even if the internal IFLASH is enabled, a code cannot be executed from it.

As the XFlash is needed, XPERCON register is configured by the ABM loader code and bit XPEN of SYSCON is set. However, as long as the EINIT instruction is not executed (and it is not in the bootstrap loader code), the settings can be modified. To do this, perform the following steps:

1. Copy in DPRAM a function that will

a) disable the XPeripherals by clearing XPEN in SYSCON register,

b) enable the needed XPeripherals by writing the correct value in XPERCON

c) set XPEN bit in SYSCON,

d) return to calling address.

2. Call the function from XFlash

The changing of the XPERCON value cannot be executed from the XFlash because the XFlash is disabled by the clearing of XPEN bit in SYSCON.

5.6.5 Watchdog

As for standard boot, the Watchdog timer remains disabled during Alternate Boot Mode. In case a Watchdog reset occurs, a software reset is generated.

Note: See note from Section 5.2.7 concerning software reset.

5.6.6 Exiting alternate boot mode

Once the ABM mode is entered, it can be exited only with a software or hardware reset.

Note: See note from Section 5.2.7 concerning software reset.

5.6.7 Alternate boot user software

If the rules described previously are respected (that is, mapping of variables, disabling of interrupts, exit conditions, predefined vectors in Block 0 of Bank 2, Watchdog usage), then users can write the software they want to execute in this mode starting from 09’0000h.

5.6.8 User/alternate mode signature integrity check

The behavior of the Alternate Boot Mode is based on the computing of a signature between the content of two memory locations and a comparison with a reference signature. This requires that users who use Alternate Boot have reserved and programmed the Flash memory locations according to:

User mode signature

00'0000h: memory address of operand0 for the signature computing

00’1FFCh: memory address of operand1 for the signature computing

00’1FFEh: memory address for the signature reference

Alternate mode signature

09'0000h: memory address of operand0 for the signature computing

09’1FFCh: memory address of operand1 for the signature computing

09’1FFEh: memory address for the signature reference

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Bootstrap loader ST10F276E

The values for operand0, operand1 and the signature should be such that the sequence shown in the figure below is successfully executed.

MOV Rx, CheckBlock1Addr; 00’0000h for standard reset ADD Rx, CheckBlock2Addr; 00’1FFCh for standard reset CPLB RLx ; 1s complement of the lower

; byte of the sum

CMP Rx, CheckBlock3Addr; 00’1FFEh for standard reset

5.6.9 Alternate boot user software aspects

User defined alternate boot code must start at 09’0000h. A new SFR created on the ST10F276E indicates that the device is running in Alternate Boot Mode: Bit 5 of EMUCON (mapped at 0xFE0Ah) is set when the alternate boot is selected by the reset configuration. All the other bits are ignored when checking the content of this register to read the value of bit 5.

This bit is a read-only bit. It remains set until the next software or hardware reset.

5.6.10 EMUCON register

EMUCON (FE0Ah / 05h) SFR Reset value: - xxh:

1514131211109876543210

- ABM

-R-

Table 36. ABM bit description

Bit Function

ABM Flag (or TMOD3)

ABM

0: Alternate Boot Mode is not selected by reset configuration on P0L[5..4] 1: Alternate Boot Mode is selected by reset configuration on P0L[5..4]: This bit is

set if P0L[5..4] = ‘01’ during hardware reset.

5.6.11 Internal decoding of test modes

The test mode decoding logic is located inside the ST10F276E Bus Controller.

The decoding is as follows:

● Alternate Boot Mode decoding: (P0L.5 & P0L.4)

● Standard Bootstrap decoding: (P0L.5 & P0L.4)

● Normal operation: (P0L.5 & P0L.4)

The other configurations select ST internal test modes.

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ST10F276E Bootstrap loader

5.6.12 Example

In the following example, Alternate Boot Mode works as follows:

– On rising edge of RSTIN

● If Bootstrap Loader mode is not enabled (P0L[5..4] = ‘11’), ST10F276E hardware

pin, the reset configuration is latched.

proceeds with a standard hardware reset procedure.

● If standard Bootstrap Loader is enabled (P0L[5..4] = ‘10’), the standard ST10 Bootstrap

Loader is enabled and a variable is cleared to indicate that ABM is not enabled.

● If Alternate Boot Mode is selected (P0L[5..4] = ‘01’), then, depending on signatures

integrity checks, a predefined reset sequence is activated.

5.7 Selective boot mode

The selective boot is a subcase of the Alternate Boot Mode. When none of the signatures are correct, instead of executing the standard bootstrap loader (triggered by P0L.4 low at reset), an additional check is made.

Address 00’1FFCh is read again with the following behavior:

● If value is 0000h or FFFFh, a jump is performed to the standard bootstrap loader.

● Otherwise:

– High byte is disregarded.

– Low byte bits select which communication channel is enabled.

Table 37. Selective boot

Bit Function

UART selection

2..7

0: UART is not watched for a Start condition. 1: UART is watched for a Start condition.

CAN1 selection 0: CAN1 is not watched for a Start condition. 1: CAN1 is watched for a Start condition.

Reserved For upward compatibility, must be programmed to ‘0’

Therefore a value:

● 0xXX03 configures the Selective Bootstrap Loader to poll for RxD0 and CAN1_RxD.

● 0xXX01 configures the Selective Bootstrap Loader to poll only RxD0 (no boot via CAN).

● 0xXX02 configures the Selective Bootstrap Loader to poll only CAN1_RxD (no boot via

UART).

● Other values allow the ST10F276E to execute an endless loop into the Test-Flash.

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Bootstrap loader ST10F276E

Figure 13. Reset boot sequence

RSTIN 0 to 1

Standard start

Yes (P0L[5..4] = ‘01’)

Boot mode?

Yes (P0L[5..4] = ‘10’)

No (P0L[5..4] = ‘11’)

No (P0L[5..4] = ‘other config.’)

ST test modes

Software checks

user reset vector

(K1 is OK?)

K1 is not OK

Software Checks

alternate reset vector

(K2 is OK?)

K2 is OK

Long jump to

09’0000h

ABM / User Flash

Start at 09’0000h

Selective Bootstrap Loader

K1 is OK

K2 is not OK

Read 00’1FFCh

Jump to Test-Flash

SW RESET

Running from test Flash

Std. Bootstrap Loader

Jump to Test-Flash

User Mode / User Flash

Start at 00’0000h

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ST10F276E Central processing unit (CPU)

6 Central processing unit (CPU)

The CPU includes a 4-stage instruction pipeline, a 16-bit arithmetic and logic unit (ALU) and dedicated SFRs. Additional hardware has been added for a separate multiply and divide unit, a bit-mask generator and a barrel shifter.

Most of the ST10F276E’s instructions can be executed in one instruction cycle which requires 31.25ns at 64 MHz CPU clock. For example, shift and rotate instructions are processed in one instruction cycle independent of the number of bits to be shifted.

Multiple-cycle instructions have been optimized: branches are carried out in 2 cycles, 16 x 16-bit multiplication in 5 cycles and a 32/16-bit division in 10 cycles.

The jump cache reduces the execution time of repeatedly performed jumps in a loop, from 2 cycles to 1 cycle.

The CPU uses a bank of 16 word registers to run the current context. This bank of General Purpose Registers (GPR) is physically stored within the on-chip Internal RAM (IRAM) area. A Context Pointer (CP) register determines the base address of the active register bank to be accessed by the CPU.

The number of register banks is only restricted by the available Internal RAM space. For easy parameter passing, a register bank may overlap others.

A system stack of up to 2048 bytes is provided as a storage for temporary data. The system stack is allocated in the on-chip RAM area, and it is accessed by the CPU via the stack pointer (SP) register.

Two separate SFRs, STKOV and STKUN, are implicitly compared against the stack pointer value upon each stack access for the detection of a stack overflow or underflow.

Figure 14. CPU Block Diagram (MAC Unit not included)

512 Kbyte

Flash

memory

STKOV STKUN

Exec. Unit

Instr. Ptr

4-Stage Pipeline

PSW

SYSCON

BUSCON 0 BUSCON 1

BUSCON 2 BUSCON 3 BUSCON 4

Data Pg. Ptrs

CPU

MDH MDL

Mul./Div.-HW

Bit-Mask Gen.

ALU

16-Bit

Barrel-Shift

ADDRSEL 1 ADDRSEL 2

ADDRSEL 3 ADDRSEL 4

Code Seg. Ptr.

R15

General

Purpose

Registers

2Kbyte Internal

RAM

Bank

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Central processing unit (CPU) ST10F276E

6.1 Multiplier-accumulator unit (MAC)

The MAC coprocessor is a specialized coprocessor added to the ST10 CPU Core in order to improve the performances of the ST10 Family in signal processing algorithms.

The standard ST10 CPU has been modified to include new addressing capabilities which enable the CPU to supply the new coprocessor with up to 2 operands per instruction cycle.

This new coprocessor (so-called MAC) contains a fast multiply-accumulate unit and a repeat unit.

The coprocessor instructions extend the ST10 CPU instruction set with multiply, multiplyaccumulate, 32-bit signed arithmetic operations.

Figure 15. MAC unit architecture

Operand 2Operand 1

16 x 16

Multiplier

Mux

GPR Pointers *

IDX0 Pointer IDX1 Pointer

QR0 GPR Offset Register QR1 GPR Offset Register

QX0 IDX Offset Register QX1 IDX Offset Register

Interrupt

Controller

ST10 CPU

MRW

Repeat Unit

MCW

signed/unsigned

Concatenation

32 32

Mux

Sign Extend

Scaler

0h 0h08000h

40 40

Mux

40-bit Signed Arithmetic Unit

Control Unit

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MSW

Flags MAE

MAH MAL

8-bit Left/Right

Shifter

ST10F276E Central processing unit (CPU)

6.2 Instruction set summary

Ta bl e 3 8 lists the instructions of the ST10F276E. The detailed description of each

instruction can be found in the “ST10 Family Programming Manual”.

Table 38. Standard instruction set summary

Mnemonic Description Bytes

ADD(B) Add word (byte) operands 2 / 4

ADDC(B) Add word (byte) operands with Carry 2 / 4

SUB(B) Subtract word (byte) operands 2 / 4

SUBC(B) Subtract word (byte) operands with Carry 2 / 4

MUL(U) (Un)Signed multiply direct GPR by direct GPR (16-16-bit) 2

DIV(U) (Un)Signed divide register MDL by direct GPR (16-/16-bit) 2

DIVL(U) (Un)Signed long divide reg. MD by direct GPR (32-/16-bit) 2

CPL(B) Complement direct word (byte) GPR 2

NEG(B) Negate direct word (byte) GPR 2

AND(B) Bit-wise AND, (word/byte operands) 2 / 4

OR(B) Bit-wise OR, (word/byte operands) 2 / 4

XOR(B) Bit-wise XOR, (word/byte operands) 2 / 4

BCLR Clear direct bit 2

BSET Set direct bit 2

BMOV(N) Move (negated) direct bit to direct bit 4

BAND, BOR, BXOR AND/OR/XOR direct bit with direct bit 4

BCMP Compare direct bit to direct bit 4

BFLDH/L

CMP(B) Compare word (byte) operands 2 / 4

CMPD1/2 Compare word data to GPR and decrement GPR by 1/2 2 / 4

CMPI1/2 Compare word data to GPR and increment GPR by 1/2 2 / 4

PRIOR

SHL / SHR Shift left/right direct word GPR 2

ROL / ROR Rotate left/right direct word GPR 2

ASHR Arithmetic (sign bit) shift right direct word GPR 2

MOV(B) Move word (byte) data 2 / 4

MOVBS Move byte operand to word operand with sign extension 2 / 4

Bit-wise modify masked high/low byte of bit-addressable direct word memory with immediate data

Determine number of shift cycles to normalize direct word GPR and store result in direct word GPR

MOVBZ Move byte operand to word operand with zero extension 2 / 4

JMPA, JMPI, JMPR Jump absolute/indirect/relative if condition is met 4

JMPS Jump absolute to a code segment 4

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Central processing unit (CPU) ST10F276E

Table 38. Standard instruction set summary (continued)

Mnemonic Description Bytes

J(N)B Jump relative if direct bit is (not) set 4

JBC Jump relative and clear bit if direct bit is set 4

JNBS Jump relative and set bit if direct bit is not set 4

CALLA, CALLI, CALLR

CALLS Call absolute subroutine in any code segment 4

PCALL

TRAP Call interrupt service routine via immediate trap number 2

PUSH, POP Push/pop direct word register onto/from system stack 2

Call absolute/indirect/relative subroutine if condition is met 4

Push direct word register onto system stack and call absolute subroutine

SCXT

RET Return from intra-segment subroutine 2

RETS Return from inter-segment subroutine 2

RETP

RETI Return from interrupt service subroutine 2

SRST Software Reset 4

IDLE Enter Idle Mode 4

PWRDN Enter Power Down Mode (supposes NMI

SRVWDT Service Watchdog Timer 4

DISWDT Disable Watchdog Timer 4

EINIT Signify End-of-Initialization on RSTOUT-pin 4

ATOMIC Begin ATOMIC sequence 2

EXTR Begin EXTended Register sequence 2

EXTP(R) Begin EXTended Page (and Register) sequence 2 / 4

EXTS(R) Begin EXTended Segment (and Register) sequence 2 / 4

NOP Null operation 2

Push direct word register onto system stack and update register with word operand

Return from intra-segment subroutine and pop direct word register from system stack

-pin being low) 4

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ST10F276E Central processing unit (CPU)

6.3 MAC coprocessor specific instructions

Ta bl e 3 9 lists the MAC instructions of the ST10F276E. The detailed description of each

instruction can be found in the “ST10 Family Programming Manual”. Note that all MAC instructions are encoded on 4 bytes.

Table 39. MAC instruction set summary

Mnemonic Description

CoABS Absolute Value of the Accumulator

CoADD(2) Addition

CoASHR(rnd) Accumulator Arithmetic Shift Right & Optional Round

CoCMP Compare Accumulator with Operands

CoLOAD(-,2) Load Accumulator with Operands

CoMAC(R,u,s,-,rnd) (Un)Signed/(Un)Signed Multiply-Accumulate & Optional Round

CoMACM(R)(u,s,-,rnd)

CoMAX / CoMIN Maximum / Minimum of Operands and Accumulator

CoMOV Memory to Memory Move

CoMUL(u,s,-,rnd) (Un)Signed/(Un)Signed multiply & Optional Round

CoNEG(rnd) Negate Accumulator & Optional Round

CoNOP No-Operation

CoRND Round Accumulator

CoSHL / CoSHR Accumulator Logical Shift Left / Right

CoSTORE Store a MAC Unit Register

CoSUB(2,R) Substraction

(Un)Signed/(Un)Signed Multiply-Accumulate with Parallel Data Move & Optional Round

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External bus controller ST10F276E

7 External bus controller

All of the external memory accesses are performed by the on-chip external bus controller.

The EBC can be programmed to single chip mode when no external memory is required, or to one of four different external memory access modes:

● 16- / 18- / 20- / 24-bit addresses and 16-bit data, demultiplexed

● 16- / 18- / 20- / 24-bit addresses and 16-bit data, multiplexed

● 16- / 18- / 20- / 24-bit addresses and 8-bit data, multiplexed

● 16- / 18- / 20- / 24-bit addresses and 8-bit data, demultiplexed

In demultiplexed bus modes addresses are output on PORT1 and data is input / output on PORT0 or P0L, respectively. In the multiplexed bus modes both addresses and data use PORT0 for input / output.

Timing characteristics of the external bus interface (memory cycle time, memory tri-state time, length of ALE and read / write delay) are programmable giving the choice of a wide range of memories and external peripherals.

Up to four independent address windows may be defined (using register pairs ADDRSELx / BUSCONx) to access different resources and bus characteristics.

These address windows are arranged hierarchically where BUSCON4 overrides BUSCON3 and BUSCON2 overrides BUSCON1.

All accesses to locations not covered by these four address windows are controlled by BUSCON0. Up to five external CS

signals (four windows plus default) can be generated in order to save external glue logic. Access to very slow memories is supported by a ‘Ready’ function.

A HOLD

/ HLDA protocol is available for bus arbitration which shares external resources

with other bus masters.

The bus arbitration is enabled by setting bit HLDEN in register PSW. After setting HLDEN once, pins P6.7...P6.5 (BREQ master mode (default after reset) the HLDA slave mode is selected where pin HLDA

, HLDA, HOLD) are automatically controlled by the EBC. In

pin is an output. By setting bit DP6.7 to ‘1’ the

is switched to input. This directly connects the slave

controller to another master controller without glue logic.

For applications which require less external memory space, the address space can be restricted to 1 Mbyte, 256 Kbytes or to 64 Kbytes. Port 4 outputs all eight address lines if an address space of 16M Bytes is used, otherwise four, two or no address lines.

Chip select timing can be made programmable. By default (after reset), the CSx

lines change half a CPU clock cycle after the rising edge of ALE. With the CSCFG bit set in the SYSCON register the CSx

lines change with the rising edge of ALE.

The active level of the READY pin can be set by bit RDYPOL in the BUSCONx registers. When the READY function is enabled for a specific address window, each bus cycle within the window must be terminated with the active level defined by bit RDYPOL in the associated BUSCON register.

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ST10F276E Interrupt system

8 Interrupt system

The interrupt response time for internal program execution is from 78ns to 187.5ns at 64 MHz CPU clock.

The ST10F276E architecture supports several mechanisms for fast and flexible response to service requests that can be generated from various sources (internal or external) to the microcontroller. Any of these interrupt requests can be serviced by the Interrupt Controller or by the Peripheral Event Controller (PEC).

In contrast to a standard interrupt service where the current program execution is suspended and a branch to the interrupt vector table is performed, just one cycle is ‘stolen’ from the current CPU activity to perform a PEC service. A PEC service implies a single Byte or Word data transfer between any two memory locations with an additional increment of either the PEC source or destination pointer. An individual PEC transfer counter is implicitly decremented for each PEC service except when performing in the continuous transfer mode. When this counter reaches zero, a standard interrupt is performed to the corresponding source related vector location. PEC services are very well suited to perform the transmission or the reception of blocks of data. The ST10F276E has 8 PEC channels, each of them offers such fast interrupt-driven data transfer capabilities.

An interrupt control register which contains an interrupt request flag, an interrupt enable flag and an interrupt priority bit-field is dedicated to each existing interrupt source. Thanks to its related register, each source can be programmed to one of sixteen interrupt priority levels. Once starting to be processed by the CPU, an interrupt service can only be interrupted by a higher prioritized service request. For the standard interrupt processing, each of the possible interrupt sources has a dedicated vector location.

Software interrupts are supported by means of the ‘TRAP’ instruction in combination with an individual trap (interrupt) number.

Fast external interrupt inputs are provided to service external interrupts with high precision requirements. These fast interrupt inputs feature programmable edge detection (rising edge, falling edge or both edges).

Fast external interrupts may also have interrupt sources selected from other peripherals; for example the CANx controller receive signals (CANx_RxD) and I

C serial clock signal can be

used to interrupt the system.

Ta bl e 4 0 shows all the available ST10F276E interrupt sources and the corresponding

hardware-related interrupt flags, vectors, vector locations and trap (interrupt) numbers:

Table 40. Interrupt sources

Source of interrupt or

PEC service request

CAPCOM Register 0 CC0IR CC0IE CC0INT 00’0040h 10h

CAPCOM Register 1 CC1IR CC1IE CC1INT 00’0044h 11h

CAPCOM Register 2 CC2IR CC2IE CC2INT 00’0048h 12h

CAPCOM Register 3 CC3IR CC3IE CC3INT 00’004Ch 13h

CAPCOM Register 4 CC4IR CC4IE CC4INT 00’0050h 14h

CAPCOM Register 5 CC5IR CC5IE CC5INT 00’0054h 15h

Request

flag

Enable

flag

Interrupt

vector

Vector

location

Trap

number

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Interrupt system ST10F276E

Table 40. Interrupt sources (continued)

Source of interrupt or

PEC service request

CAPCOM Register 6 CC6IR CC6IE CC6INT 00’0058h 16h

CAPCOM Register 7 CC7IR CC7IE CC7INT 00’005Ch 17h

CAPCOM Register 8 CC8IR CC8IE CC8INT 00’0060h 18h

CAPCOM Register 9 CC9IR CC9IE CC9INT 00’0064h 19h

CAPCOM Register 10 CC10IR CC10IE CC10INT 00’0068h 1Ah

CAPCOM Register 11 CC11IR CC11IE CC11INT 00’006Ch 1Bh

CAPCOM Register 12 CC12IR CC12IE CC12INT 00’0070h 1Ch

CAPCOM Register 13 CC13IR CC13IE CC13INT 00’0074h 1Dh

CAPCOM Register 14 CC14IR CC14IE CC14INT 00’0078h 1Eh

CAPCOM Register 15 CC15IR CC15IE CC15INT 00’007Ch 1Fh

CAPCOM Register 16 CC16IR CC16IE CC16INT 00’00C0h 30h

CAPCOM Register 17 CC17IR CC17IE CC17INT 00’00C4h 31h

CAPCOM Register 18 CC18IR CC18IE CC18INT 00’00C8h 32h

CAPCOM Register 19 CC19IR CC19IE CC19INT 00’00CCh 33h

CAPCOM Register 20 CC20IR CC20IE CC20INT 00’00D0h 34h

CAPCOM Register 21 CC21IR CC21IE CC21INT 00’00D4h 35h

CAPCOM Register 22 CC22IR CC22IE CC22INT 00’00D8h 36h

Request

flag

Enable

flag

Interrupt

vector

Vector

location

Trap

number

CAPCOM Register 23 CC23IR CC23IE CC23INT 00’00DCh 37h

CAPCOM Register 24 CC24IR CC24IE CC24INT 00’00E0h 38h

CAPCOM Register 25 CC25IR CC25IE CC25INT 00’00E4h 39h

CAPCOM Register 26 CC26IR CC26IE CC26INT 00’00E8h 3Ah

CAPCOM Register 27 CC27IR CC27IE CC27INT 00’00ECh 3Bh

CAPCOM Register 28 CC28IR CC28IE CC28INT 00’00F0h 3Ch

CAPCOM Register 29 CC29IR CC29IE CC29INT 00’0110h 44h

CAPCOM Register 30 CC30IR CC30IE CC30INT 00’0114h 45h

CAPCOM Register 31 CC31IR CC31IE CC31INT 00’0118h 46h

CAPCOM Timer 0 T0IR T0IE T0INT 00’0080h 20h

CAPCOM Timer 1 T1IR T1IE T1INT 00’0084h 21h

CAPCOM Timer 7 T7IR T7IE T7INT 00’00F4h 3Dh

CAPCOM Timer 8 T8IR T8IE T8INT 00’00F8h 3Eh

GPT1 Timer 2 T2IR T2IE T2INT 00’0088h 22h

GPT1 Timer 3 T3IR T3IE T3INT 00’008Ch 23h

GPT1 Timer 4 T4IR T4IE T4INT 00’0090h 24h

GPT2 Timer 5 T5IR T5IE T5INT 00’0094h 25h

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ST10F276E Interrupt system

Table 40. Interrupt sources (continued)

Source of interrupt or

PEC service request

GPT2 Timer 6 T6IR T6IE T6INT 00’0098h 26h

GPT2 CAPREL Register CRIR CRIE CRINT 00’009Ch 27h

A/D Conversion Complete ADCIR ADCIE ADCINT 00’00A0h 28h

A/D Overrun Error ADEIR ADEIE ADEINT 00’00A4h 29h

ASC0 Transmit S0TIR S0TIE S0TINT 00’00A8h 2Ah

ASC0 Transmit Buffer S0TBIR S0TBIE S0TBINT 00’011Ch 47h

ASC0 Receive S0RIR S0RIE S0RINT 00’00ACh 2Bh

ASC0 Error S0EIR S0EIE S0EINT 00’00B0h 2Ch

SSC Transmit SCTIR SCTIE SCTINT 00’00B4h 2Dh

SSC Receive SCRIR SCRIE SCRINT 00’00B8h 2Eh

SSC Error SCEIR SCEIE SCEINT 00’00BCh 2Fh

PWM Channel 0...3 PWMIR PWMIE PWMINT 00’00FCh 3Fh

See paragraph 8.1 XP0IR XP0IE XP0INT 00’0100h 40h

See paragraph 8.1 XP1IR XP1IE XP1INT 00’0104h 41h

See paragraph 8.1 XP2IR XP2IE XP2INT 00’0108h 42h

See paragraph 8.1 XP3IR XP3IE XP3INT 00’010Ch 43h

Request

flag

Enable

flag

Interrupt

vector

Vector

location

Trap

number

Hardware traps are exceptions or error conditions that arise during run-time. They cause immediate non-maskable system reaction similar to a standard interrupt service (branching to a dedicated vector table location).

The occurrence of a hardware trap is additionally signified by an individual bit in the trap flag register (TFR). Except when another higher prioritized trap service is in progress, a hardware trap will interrupt any other program execution. Hardware trap services cannot not be interrupted by standard interrupt or by PEC interrupts.

8.1 X-Peripheral interrupt

The limited number of X-Bus interrupt lines of the present ST10 architecture, imposes some constraints on the implementation of the new functionality. In particular, the additional XPeripherals SSC1, ASC1, I and PEC transfer capabilities. For this reason, a multiplexed structure for the interrupt management is proposed. In Figure 16, the principle is explained through a simple diagram, which shows the basic structure replicated for each of the four X-interrupt available vectors (XP0INT, XP1INT, XP2INT and XP3INT).

It is based on a set of 16-bit registers XIRxSEL (x=0,1,2,3), divided in two portions each:

● Byte High XIRxSEL[15:8] Interrupt Enable bits

● Byte Low XIRxSEL[7:0] Interrupt Flag bits

When different sources submit an interrupt request, the enable bits (Byte High of XIRxSEL register) define a mask which controls which sources will be associated with the unique

C, PWM1 and RTC need some resources to implement interrupt

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Interrupt system ST10F276E

available vector. If more than one source is enabled to issue the request, the service routine will have to take care to identify the real event to be serviced. This can easily be done by checking the flag bits (Byte Low of XIRxSEL register). Note that the flag bits can also provide information about events which are not currently serviced by the interrupt controller (since masked through the enable bits), allowing an effective software management also in absence of the possibility to serve the related interrupt request: a periodic polling of the flag bits may be implemented inside the user application.

Figure 16. X-Interrupt basic structure

Flag[7:0]

IT Source 7

IT Source 6

IT Source 5

IT Source 4

IT Source 3

IT Source 2

IT Source 1

IT Source 0

XIRxSEL[7:0] (x = 0, 1, 2, 3)

XPxIC.XPxIR (x = 0, 1, 2, 3)

Enable[7:0]

15 8

XIRxSEL[15:8] (x = 0, 1, 2, 3)

Ta bl e 4 1 summarizes the mapping of the different interrupt sources which share the four X-

interrupt vectors.

Table 41. X-Interrupt detailed mapping

Interrupt source XP0INT XP1INT XP2INT XP3INT

CAN1 Interrupt x x

CAN2 Interrupt x x

I2C Receive x x x

I2C Transmit x x x

I2C Error x

SSC1 Receive x x x

SSC1 Transmit x x x

SSC1 Error x

ASC1 Receive x x x

ASC1 Transmit x x x

ASC1 Transmit Buffer x x x

ASC1 Error x

PLL Unlock / OWD x

PWM1 Channel 3...0 x x

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ST10F276E Interrupt system

8.2 Exception and error traps list

Ta bl e 4 2 shows all of the possible exceptions or error conditions that can arise during run-

time.

Table 42. Trap priorities

(1)

Exception condition

Trap

flag

Trap

vector

Vector

location

Trap

number

Reset Functions: Hardware Reset Software Reset Watchdog Timer Overflow

RESET RESET RESET

00’0000h 00’0000h 00’0000h

00h 00h 00h

Class A Hardware Traps: Non-Maskable Interrupt Stack Overflow Stack Underflow

NMI

STKOF

STKUF

NMITRAP STOTRAP STUTRAP

00’0008h 00’0010h 00’0018h

02h 04h 06h

Class B Hardware Traps: Undefined Opcode MAC Interruption Protected Instruction Fault Illegal word Operand Access Illegal Instruction Access Illegal External Bus Access

UNDOPC MACTRP

PRTFLT

ILLOPA

ILLINA

ILLBUS

BTRAP BTRAP BTRAP BTRAP BTRAP BTRAP

00’0028h 00’0028h 00’0028h 00’0028h 00’0028h 00’0028h

0Ah 0Ah 0Ah 0Ah 0Ah 0Ah

Reserved [002Ch - 003Ch] [0Bh - 0Fh]

Trap

priority

III III III

II II II

I I I I I I

Software Traps TRAP Instruction

1. All the class B traps have the same trap number (and vector) and the same lower priority compare to the

class A traps and to the resets. Each class A trap has a dedicated trap number (and vector). They are prioritized in the second priority level. The resets have the highest priority level and the same trap number. The PSW.ILVL CPU priority is forced to the highest level (15) when these exceptions are serviced.

Any

0000h – 01FCh

in steps of 4h

Any

[00h - 7Fh]

Current

CPU

Priority

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Capture / compare (CAPCOM) units ST10F276E

9 Capture / compare (CAPCOM) units

The ST10F276E has two 16-channel CAPCOM units which support generation and control of timing sequences on up to 32 channels with a maximum resolution of 125ns at 64 MHz CPU clock.

The CAPCOM units are typically used to handle high speed I/O tasks such as pulse and waveform generation, pulse width modulation (PMW), Digital to Analog (D/A) conversion, software timing, or time recording relative to external events.

Four 16-bit timers (T0/T1, T7/T8) with reload registers provide two independent time bases for the capture/compare register array.

The input clock for the timers is programmable to several prescaled values of the internal system clock, or may be derived from an overflow/underflow of timer T6 in module GPT2.

This provides a wide range of variation for the timer period and resolution and allows precise adjustments to application specific requirements. In addition, external count inputs for CAPCOM timers T0 and T7 allow event scheduling for the capture/compare registers relative to external events.

Each of the two capture/compare register arrays contain 16 dual purpose capture/compare registers, each of which may be individually allocated to either CAPCOM timer T0 or T1 (T7 or T8, respectively), and programmed for capture or compare functions. Each of the 32 registers has one associated port pin which serves as an input pin for triggering the capture function, or as an output pin to indicate the occurrence of a compare event.

When a capture/compare register has been selected for capture mode, the current contents of the allocated timer will be latched (captured) into the capture/compare register in response to an external event at the port pin which is associated with this register. In addition, a specific interrupt request for this capture/compare register is generated.

Either a positive, a negative, or both a positive and a negative external signal transition at the pin can be selected as the triggering event. The contents of all registers which have been selected for one of the five compare modes are continuously compared with the contents of the allocated timers.

When a match occurs between the timer value and the value in a capture / compare register, specific actions will be taken based on the selected compare mode.

The input frequencies f

, for the timer input selector Tx, are determined as a function of the

CPU clocks. The timer input frequencies, resolution and periods which result from the selected pre-scaler option in TxI when using a 40 MHz and 64 MHz CPU clock are listed in the Ta bl e 4 4 and Tab le 4 5 respectively.

The numbers for the timer periods are based on a reload value of 0000h. Note that some numbers may be rounded to three significant figures.

Table 43. Compare modes

Compare modes Function

Mode 0 Interrupt-only compare mode; several compare interrupts per timer period are possible

Mode 1 Pin toggles on each compare match; several compare events per timer period are possible

Mode 2 Interrupt-only compare mode; only one compare interrupt per timer period is generated

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ST10F276E Capture / compare (CAPCOM) units

Table 43. Compare modes (continued)

Compare modes Function

Mode 3

Double Register Mode

Table 44. CAPCOM timer input frequencies, resolutions and periods at 40 MHz

Pin set ‘1’ on match; pin reset ‘0’ on compare time overflow; only one compare event per timer period is generated

Two registers operate on one pin; pin toggles on each compare match; several compare events per timer period are possible.

Timer input selection TxI

= 40 MHz

CPU

000b 001b 010b 011b 100b 101b 110b 111b

Prescaler for f

CPU

8 16 32 64 128 256 512 1024

Input frequency 5 MHz 2.5 MHz 1.25 MHz 625 kHz 312.5 kHz 156.25 kHz 78.125 kHz 39.1 kHz

Resolution 200ns 400ns 0.8µs 1.6µs 3.2µs 6.4µs 12.8µs 25.6µs

Period 13.1ms 26.2ms 52.4ms 104.8 ms 209.7ms 419.4ms 838.9ms 1.678s

Table 45. CAPCOM timer input frequencies, resolutions and periods at 64 MHz

Timer input selection TxI

= 64 MHz

CPU

000b 001b 010b 011b 100b 101b 110b 111b

Prescaler for f

CPU

8 16 32 64 128 256 512 1024

Input frequency 8 MHz 4 MHz 2 MHz 1 kHz 500 kHz 250 kHz 128 kHz 64 kHz

Resolution 125ns 250ns 0.5µs 1.0µs 2.0µs 4.0µs 8.0µs 16.0µs

Period 8.2ms 16.4ms 32.8ms 65.5ms 131.1ms 262.1ms 524.3ms 1.049s

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General purpose timer unit ST10F276E

10 General purpose timer unit

The GPT unit is a flexible multifunctional timer/counter structure which is used for time related tasks such as event timing and counting, pulse width and duty cycle measurements, pulse generation, or pulse multiplication. The GPT unit contains five 16-bit timers organized into two separate modules GPT1 and GPT2. Each timer in each module may operate independently in several different modes, or may be concatenated with another timer of the same module.

10.1 GPT1

Each of the three timers T2, T3, T4 of the GPT1 module can be configured individually for one of four basic modes of operation: timer, gated timer, counter mode and incremental interface mode.

In timer mode, the input clock for a timer is derived from the CPU clock, divided by a programmable prescaler.

In counter mode, the timer is clocked in reference to external events.

Pulse width or duty cycle measurement is supported in gated timer mode where the operation of a timer is controlled by the ‘gate’ level on an external input pin. For these purposes, each timer has one associated port pin (TxIN) which serves as gate or clock input.

Ta bl e 4 6 and Ta bl e 4 7 list the timer input frequencies, resolution and periods for each pre-

scaler option at 40 MHz and 64 MHz CPU clock respectively.

In Incremental Interface Mode, the GPT1 timers (T2, T3, T4) can be directly connected to the incremental position sensor signals A and B by their respective inputs TxIN and TxEUD.

Direction and count signals are internally derived from these two input signals so that the contents of the respective timer Tx corresponds to the sensor position. The third position sensor signal TOP0 can be connected to an interrupt input.

Timer T3 has output toggle latches (TxOTL) which changes state on each timer over flow / underflow. The state of this latch may be output on port pins (TxOUT) for time out monitoring of external hardware components, or may be used internally to clock timers T2 and T4 for high resolution of long duration measurements.

In addition to their basic operating modes, timers T2 and T4 may be configured as reload or capture registers for timer T3.

Table 46. GPT1 timer input frequencies, resolutions and periods at 40 MHz

Timer input selection T2I / T3I / T4I

= 40 MHz

CPU

Prescaler factor 8 16 32 64 128 256 512 1024

Input frequency 5 MHz 2.5 MHz 1.25 MHz 625 kHz 312.5 kHz 156.25 kHz 78.125 kHz 39.1 kHz

Resolution 200ns 400ns 0.8µs 1.6µs 3.2µs 6.4µs 12.8µs 25.6µs

000b 001b 010b 011b 100b 101b 110b 111b

Period maximum 13.1ms 26.2ms 52.4ms 104.8 ms 209.7ms 419.4ms 838.9ms 1.678s

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ST10F276E General purpose timer unit

Table 47. GPT1 timer input frequencies, resolutions and periods at 64 MHz

Timer input selection T2I / T3I / T4I

= 64 MHz

CPU

000b 001b 010b 011b 100b 101b 110b 111b

Prescaler factor 8 16 32 64 128 256 512 1024

Input frequency 8 MHz 4 MHz 2 MHz 1 kHz 500 kHz 250 kHz 128 kHz 64 kHz

Resolution 125ns 250ns 0.5µs 1.0µs 2.0µs 4.0µs 8.0µs 16.0µs

Period maximum 8.2ms 16.4ms 32.8ms 65.5ms 131.1ms 262.1ms 524.3ms 1.049s

Figure 17. Block diagram of GPT1

T2EUD

CPU Clock

T2IN

2n n=3...10

T2 Mode Control

Reload Capture

U/D

GPT1 Timer T2

Interrupt Request

CPU Clock

T3IN

T3EUD

T4IN

CPU Clock

T4EUD

2n n=3...10

T3 Mode Control

T4 Mode Control

GPT1 Timer T3

U/D

Capture

Reload

GPT1 Timer T4

U/D

T3OTL

T3OUT

Interrupt Request

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General purpose timer unit ST10F276E

10.2 GPT2

The GPT2 module provides precise event control and time measurement. It includes two timers (T5, T6) and a capture/reload register (CAPREL). Both timers can be clocked with an input clock which is derived from the CPU clock via a programmable prescaler or with external signals. The count direction (up/down) for each timer is programmable by software or may additionally be altered dynamically by an external signal on a port pin (TxEUD). Concatenation of the timers is supported via the output toggle latch (T6OTL) of timer T6 which changes its state on each timer overflow/underflow.

The state of this latch may be used to clock timer T5, or it may be output on a port pin (T6OUT). The overflow / underflow of timer T6 can additionally be used to clock the CAPCOM timers T0 or T1, and to cause a reload from the CAPREL register. The CAPREL register may capture the contents of timer T5 based on an external signal transition on the corresponding port pin (CAPIN), and timer T5 may optionally be cleared after the capture procedure. This allows absolute time differences to be measured or pulse multiplication to be performed without software overhead.

The capture trigger (timer T5 to CAPREL) may also be generated upon transitions of GPT1 timer T3 inputs T3IN and/or T3EUD. This is advantageous when T3 operates in Incremental Interface Mode.

Ta bl e 4 8 and Ta bl e 4 9 list the timer input frequencies, resolution and periods for each pre-

scaler option at 40 MHz and 64 MHz CPU clock respectively.

Table 48. GPT2 timer input frequencies, resolutions and periods at 40 MHz

Timer input selection T5I / T6I

= 40MHz

CPU

Prescaler factor 4 8 16 32 64 128 256 512

Input frequency 10 MHz 5 MHz 2.5 MHz 1.25 MHz 625 kHz 312.5 kHz 156.25 kHz 78.125 kHz

Resolution 100ns 200ns 400ns 0.8µs 1.6µs 3.2µs 6.4µs 12.8µs

Period maximum 6.55ms 13.1ms 26.2ms 52.4ms 104.8ms 209.7ms 419.4ms 838.9ms

Table 49. GPT2 timer input frequencies, resolutions and periods at 64 MHz

= 64MHz

CPU

Prescaler factor 4 8 16 32 64 128 256 512

Input frequency 16 MHz 8 MHz 4 MHz 2 MHz 1 kHz 500 kHz 250 kHz 128 kHz

Resolution 62.5ns 125ns 250ns 0.5µs 1.0µs 2.0µs 4.0µs 8.0µs

Period maximum 4.1ms 8.2ms 16.4ms 32.8ms 65.5ms 131.1ms 262.1ms 524.3ms

000b 001b 010b 011b 100b 101b 110b 111b

Timer input selection T5I / T6I

000b 001b 010b 011b 100b 101b 110b 111b

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ST10F276E General purpose timer unit

Figure 18. Block diagram of GPT2

T5EUD

CPU Clock

T5IN

2n n=2...9

T5 Mode Control

Clear

U/D

GPT2 Timer T5

Interrupt Request

CAPIN

T6IN

CPU Clock

T6EUD

2n n=2...9

T6 Mode Control

Capture

GPT2 CAPREL

Reload

GPT2 Timer T6

U/D

Toggle FF

T60TL

Interrupt Request

T6OUT

to CAPCOM Timers

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PWM modules ST10F276E

11 PWM modules

Two pulse width modulation modules are available on ST10F276E: standard PWM0 and XBUS PWM1. They can generate up to four PWM output signals each, using edge-aligned or centre-aligned PWM. In addition, the PWM modules can generate PWM burst signals and single shot outputs. Tab le 5 0 and Tab le 5 1 show the PWM frequencies for different resolutions. The level of the output signals is selectable and the PWM modules can generate interrupt requests.

Figure 19. Block diagram of PWM module

PPx Period Register

Comparator

Clock 1

Clock 2

1. User readable / writeable register

Table 50. PWM unit frequencies and resolutions at 40 MHz CPU clock

Mode

CPU clock divided by

Input

Control

Run

16-bit Up/Down Counter

PWx Pulse Width Register

Resolution 8-bit 10-bit 12-bit 14-bit 16-bit

PTx

Comparator

Shadow Register

(1)

Match

(1)

Match

(1)

Up/Down/

Clear Control

Output Control

Write Control

1 25ns 156.25 kHz 39.1 kHz 9.77 kHz 2.44 Hz 610 Hz

64 1.6µs 2.44 kHz 610 Hz 152.6 Hz 38.15 Hz 9.54 Hz

1 25ns 78.12 kHz 19.53 kHz 4.88 kHz 1.22 kHz 305.2 Hz

64 1.6µs 1.22 kHz 305.17 Hz 76.29 Hz 19.07 Hz 4.77 Hz

Table 51. PWM unit frequencies and resolutions at 64 MHz CPU clock

Enable

POUTx

Mode

CPU clock divided by

Resolution 8-bit 10-bit 12-bit 14-bit 16-bit

1 15.6ns 250 kHz 62.5 kHz 15.63 kHz 3.91 Hz 977 Hz

64 1.0µs 3.91 kHz 976.6 Hz 244.1Hz 61.01 Hz 15.26 Hz

1 15.6ns 125 kHz 31.25 kHz 7.81 kHz 1.95 kHz 488.3 Hz

64 1.0µs 1.95 kHz 488.28 Hz 122.07 Hz 30.52 Hz 7.63 Hz

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ST10F276E Parallel ports

12 Parallel ports

12.1 Introduction

The ST10F276E MCU provides up to 111 I/O lines with programmable features. These capabilities bring very flexible adaptation of this MCU to wide range of applications.

ST10F276E has nine groups of I/O lines gathered as follows:

● Port 0 is a two time 8-bit port named P0L (Low as less significant byte) and P0H (high

as most significant byte)

● Port 1 is a two time 8-bit port named P1L and P1H

● Port 2 is a 16-bit port

● Port 3 is a 15-bit port (P3.14 line is not implemented)

● Port 4 is a 8-bit port

● Port 5 is a 16-bit port input only

● Port 6, Port 7 and Port 8 are 8-bit ports

These ports may be used as general purpose bidirectional input or output, software controlled with dedicated registers.

For example, the output drivers of six of the ports (2, 3, 4, 6, 7, 8) can be configured (bitwise) for push-pull or open drain operation using ODPx registers.

The input threshold levels are programmable (TTL/CMOS) for all the ports. The logic level of a pin is clocked into the input latch once per state time, regardless whether the port is configured for input or output. The threshold is selected with PICON and XPICON registers control bits.

A write operation to a port pin configured as an input causes the value to be written into the port output latch, while a read operation returns the latched state of the pin itself. A readmodify-write operation reads the value of the pin, modifies it, and writes it back to the output latch.

Writing to a pin configured as an output (DPx.y=‘1’) causes the output latch and the pin to have the written value, since the output buffer is enabled. Reading this pin returns the value of the output latch. A read-modify-write operation reads the value of the output latch, modifies it, and writes it back to the output latch, thus also modifying the level at the pin.

I/O lines support an alternate function which is detailed in the following description of each port.

12.2 I/O’s special features

12.2.1 Open drain mode

Some of the I/O ports of ST10F276E support the open drain capability. This programmable feature may be used with an external pull-up resistor, in order to get an AND wired logical function.

This feature is implemented for ports P2, P3, P4, P6, P7 and P8 (see respective sections), and is controlled through the respective Open Drain Control Registers ODPx.

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Parallel ports ST10F276E

12.2.2 Input threshold control

The standard inputs of the ST10F276E determine the status of input signals according to TTL levels. In order to accept and recognize noisy signals, CMOS input thresholds can be selected instead of the standard TTL thresholds for all the pins. These CMOS thresholds are defined above the TTL thresholds and feature a higher hysteresis to prevent the inputs from toggling while the respective input signal level is near the thresholds.

The Port Input Control registers PICON and XPICON are used to select these thresholds for each Byte of the indicated ports, this means the 8-bit ports P0L, P0H, P1L, P1H, P4, P7 and P8 are controlled by one bit each while ports P2, P3 and P5 are controlled by two bits each.

All options for individual direction and output mode control are available for each pin, independent of the selected input threshold.

12.3 Alternate port functions

Each port line has one associated programmable alternate input or output function.

● PORT0 and PORT1 may be used as address and data lines when accessing external

memory. Besides, PORT1 provides also:

– Input capture lines

– 8 additional analog input channels to the A/D converter

● Port 2, Port 7 and Port 8 are associated with the capture inputs or compare outputs of

the CAPCOM units and/or with the outputs of the PWM0 module, of the PWM1 module and of the ASC1. Port 2 is also used for fast external interrupt inputs and for timer 7 input.

● Port 3 includes the alternate functions of timers, serial interfaces, the optional bus

control signal BHE

● Port 4 outputs the additional segment address bit A23...A16 in systems where more

than 64 Kbytes of memory are to be access directly. In addition, CAN1, CAN2 and I lines are provided.

● Port 5 is used as analog input channels of the A/D converter or as timer control signals.

● Port 6 provides optional bus arbitration signals (BREQ, HLDA, HOLD) and chip select

signals and the SSC1 lines.

and the system clock output (CLKOUT).

If the alternate output function of a pin is to be used, the direction of this pin must be programmed for output (DPx.y=‘1’), except for some signals that are used directly after reset and are configured automatically. Otherwise the pin remains in the high-impedance state and is not effected by the alternate output function. The respective port latch should hold a ‘1’, because its output is ANDed with the alternate output data (except for PWM output signals).

If the alternate input function of a pin is used, the direction of the pin must be programmed for input (DPx.y=‘0’) if an external device is driving the pin. The input direction is the default after reset. If no external device is connected to the pin, however, one can also set the direction for this pin to output. In this case, the pin reflects the state of the port output latch. Thus, the alternate input function reads the value stored in the port output latch. This can be used for testing purposes to allow a software trigger of an alternate input function by writing to the port output latch.

On most of the port lines, the user software is responsible for setting the proper direction when using an alternate input or output function of a pin.

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ST10F276E Parallel ports

This is done by setting or clearing the direction control bit DPx.y of the pin before enabling the alternate function.

There are port lines, however, where the direction of the port line is switched automatically.

For instance, in the multiplexed external bus modes of PORT0, the direction must be switched several times for an instruction fetch in order to output the addresses and to input the data.

Obviously, this cannot be done through instructions. In these cases, the direction of the port line is switched automatically by hardware if the alternate function of such a pin is enabled.

To determine the appropriate level of the port output latches check how the alternate data output is combined with the respective port latch output.

There is one basic structure for all port lines with only an alternate input function. Port lines with only an alternate output function, however, have different structures due to the way the direction of the pin is switched and depending on whether the pin is accessible by the user software or not in the alternate function mode.

All port lines that are not used for these alternate functions may be used as general purpose I/O lines.

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A/D converter ST10F276E

13 A/D converter

A 10-bit A/D converter with 16+8 multiplexed input channels and a sample and hold circuit is integrated on-chip. An automatic self-calibration adjusts the A/D converter module to process parameter variations at each reset event. The sample time (for loading the capacitors) and the conversion time is programmable and can be adjusted to the external circuitry.

The ST10F276E has 16+8 multiplexed input channels on Port 5 and Port 1. The selection between Port 5 and Port 1 is made via a bit in a XBus register. Refer to the user manual for a detailed description.

A different accuracy is guaranteed (Total Unadjusted Error) on Port 5 and Port 1 analog channels (with higher restrictions when overload conditions occur); in particular, Port 5 channels are more accurate than the Port 1 ones. Refer to Chapter 23: Electrical

characteristics for details.

The A/D converter input bandwidth is limited by the achievable accuracy: supposing a maximum error of 0.5 LSB (2mV) impacting the global TUE (TUE depends also on other causes), in worst case of temperature and process, the maximum frequency for a sine wave analog signal is around 7.5 kHz. Of course, to reduce the effect of the input signal variation on the accuracy down to 0.05 LSB, the maximum input frequency of the sine wave shall be reduced to 800 Hz.

If static signal is applied during sampling phase, series resistance shall not be greater than 20kΩ (this taking into account eventual input leakage). It is suggested to not connect any capacitance on analog input pins, in order to reduce the effect of charge partitioning (and consequent voltage drop error) between the external and the internal capacitance: in case an RC filter is necessary the external capacitance must be greater than 10nF to minimize the accuracy impact.

Overrun error detection / protection is controlled by the ADDAT register. Either an interrupt request is generated when the result of a previous conversion has not been read from the result register at the time the next conversion is complete, or the next conversion is suspended until the previous result has been read. For applications which require less than 16+8 analog input channels, the remaining channel inputs can be used as digital input port pins.

The A/D converter of the ST10F276E supports different conversion modes:

● Single channel single conversion: The analog level of the selected channel is

sampled once and converted. The result of the conversion is stored in the ADDAT register.

● Single channel continuous conversion: The analog level of the selected channel is

repeatedly sampled and converted. The result of the conversion is stored in the ADDAT register.

● Auto scan single conversion: The analog level of the selected channels are sampled

once and converted. After each conversion the result is stored in the ADDAT register. The data can be transferred to the RAM by interrupt software management or using the powerful Peripheral Event Controller (PEC) data transfer.

● Auto scan continuous conversion: The analog level of the selected channels are

repeatedly sampled and converted. The result of the conversion is stored in the ADDAT

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ST10F276E A/D converter

● Wait for ADDAT read mode: When using continuous modes, in order to avoid to

overwrite the result of the current conversion by the next one, the ADWR bit of ADCON control register must be activated. Then, until the ADDAT register is read, the new result is stored in a temporary buffer and the conversion is on hold.

● Channel injection mode: When using continuous modes, a selected channel can be

converted in between without changing the current operating mode. The 10-bit data of the conversion are stored in ADRES field of ADDAT2. The current continuous mode remains active after the single conversion is completed.

A full calibration sequence is performed after a reset. This full calibration lasts up to 40.630 CPU clock cycles. During this time, the busy flag ADBSY is set to indicate the operation. It compensates the capacitance mismatch, so the calibration procedure does not need any update during normal operation.

No conversion can be performed during this time: the bit ADBSY shall be polled to verify when the calibration is over, and the module is able to start a conversion.

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Serial channels ST10F276E

14 Serial channels

Serial communication with other microcontrollers, microprocessors, terminals or external peripheral components is provided by up to four serial interfaces: two asynchronous / synchronous serial channels (ASC0 and ASC1) and two high-speed synchronous serial channel (SSC0 and SSC1). Dedicated Baud rate generators set up all standard Baud rates without the requirement of oscillator tuning. For transmission, reception and erroneous reception, separate interrupt vectors are provided for ASC0 and SSC0 serial channel. A more complex mechanism of interrupt sources multiplexing is implemented for ASC1 and SSC1 (XBUS mapped).

14.1 Asynchronous / synchronous serial interfaces

The asynchronous / synchronous serial interfaces (ASC0 and ASC1) provides serial communication between the ST10F276E and other microcontrollers, microprocessors or external peripherals.

14.2 ASCx in asynchronous mode

In asynchronous mode, 8- or 9-bit data transfer, parity generation and the number of stop bits can be selected. Parity framing and overrun error detection is provided to increase the reliability of data transfers. Transmission and reception of data is double-buffered. Fullduplex communication up to 2M bauds (at 64 MHz of f

Table 52. ASC asynchronous baud rates by reload value and deviation errors (f

S0BRS = ‘0’, f

Baud rate

(baud)

1 250 000 0.0% / 0.0% 0000 / 0000 833 333 0.0% / 0.0% 0000 / 0000

112 000 +1.5% / -7.0% 000A / 000B 112 000 +6.3% / -7.0% 0006 / 0007

56 000 +1.5% / -3.0% 0015 / 0016 56 000 +6.3% / -0.8% 000D / 000E

38 400 +1.7% / -1.4% 001F / 0020 38 400 +3.3% / -1.4% 0014 / 0015

19 200 +0.2% / -1.4% 0040 / 0041 19 200 +0.9% / -1.4% 002A / 002B

9 600 +0.2% / -0.6% 0081 / 0082 9 600 +0.9% / -0.2% 0055 / 0056

4 800 +0.2% / -0.2% 0103 / 0104 4 800 +0.4% / -0.2% 00AC / 00AD

2 400 +0.2% / 0.0% 0207 / 0208 2 400 +0.1% / -0.2% 015A / 015B

1 200 0.1% / 0.0% 0410 / 0411 1 200 +0.1% / -0.1% 02B5 / 02B6

600 0.0% / 0.0% 0822 / 0823 600 +0.1% / 0.0% 056B / 056C

Deviation error

= 40 MHz S0BRS = ‘1’, f

CPU

Reload value

(hex)

Baud rate

(baud)

) is supported in this mode.

CPU

= 40 MHz

CPU

Deviation error

= 40 MHz)

Reload value

(hex)

300 0.0% / 0.0% 1045 / 1046 300 0.0% / 0.0% 0AD8 / 0AD9

153 0.0% / 0.0% 1FE8 / 1FE9 102 0.0% / 0.0% 1FE8 / 1FE9

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ST10F276E Serial channels

Table 53. ASC asynchronous baud rates by reload value and deviation errors (f

S0BRS = ‘0’, f

= 64 MHz S0BRS = ‘1’, f

CPU

= 64 MHz

CPU

= 64 MHz)

CPU

Baud rate

(baud)

Deviation error

Reload value

(hex)

Baud rate

(baud)

Deviation error

Reload value

(hex)

2 000 000 0.0% / 0.0% 0000 / 0000 1 333 333 0.0% / 0.0% 0000 / 0000

112 000 +1.5% / -7.0% 0010 / 0011 112 000 +6.3% / -7.0% 000A / 000B

56 000 +1.5% / -3.0% 0022 / 0023 56 000 +6.3% / -0.8% 0016 / 0017

38 400 +1.7% / -1.4% 0033 / 0034 38 400 +3.3% / -1.4% 0021 / 0022

19 200 +0.2% / -1.4% 0067 / 0068 19 200 +0.9% / -1.4% 0044 / 0045

9 600 +0.2% / -0.6% 00CF / 00D0 9 600 +0.9% / -0.2% 0089 / 008A

4 800 +0.2% / -0.2% 019F / 01A0 4 800 +0.4% / -0.2% 0114 / 0115

2 400 +0.2% / 0.0% 0340 / 0341 2 400 +0.1% / -0.2% 022A / 015B

1 200 0.1% / 0.0% 0681 / 0682 1 200 +0.1% / -0.1% 0456 / 0457

600 0.0% / 0.0% 0D04 / 0D05 600 +0.1% / 0.0% 08AD / 08AE

300 0.0% / 0.0% 1A09 / 1A0A 300 0.0% / 0.0% 115B / 115C

245 0.0% / 0.0% 1FE2 / 1FE3 163 0.0% / 0.0% 1FF2 / 1FF3

Note: The deviation errors given in the Ta b le 5 2 and Ta b l e 53 are rounded. To avoid deviation

errors use a Baud rate crystal (providing a multiple of the ASC0 sampling frequency).

14.3 ASCx in synchronous mode

In synchronous mode, data is transmitted or received synchronously to a shift clock which is generated by the ST10F276E. Half-duplex communication up to 8M baud (at 40 MHz of f

) is possible in this mode.

CPU

Table 54. ASC synchronous baud rates by reload value and deviation errors (f

S0BRS = ‘0’, f

Baud rate

(baud)

Deviation error

5 000 000 0.0% / 0.0% 0000 / 0000 3 333 333 0.0% / 0.0% 0000 / 0000

112 000 +1.5% / -0.8% 002B / 002C 112 000 +2.6% / -0.8% 001C / 001D

56 000 +0.3% / -0.8% 0058 / 0059 56 000 +0.9% / -0.8% 003A / 003B

38 400 +0.2% / -0.6% 0081 / 0082 38 400 +0.9% / -0.2% 0055 / 0056

19 200 +0.2% / -0.2% 0103 / 0104 19 200 +0.4% / -0.2% 00AC / 00AD

9 600 +0.2% / 0.0% 0207 / 0208 9 600 +0.1% / -0.2% 015A / 015B

4 800 +0.1% / 0.0% 0410 / 0411 4 800 +0.1% / -0.1% 02B5 / 02B6

2 400 0.0% / 0.0% 0822 / 0823 2 400 +0.1% / 0.0% 056B / 056C

1 200 0.0% / 0.0% 1045 / 1046 1 200 0.0% / 0.0% 0AD8 / 0AD9

= 40 MHz S0BRS = ‘1’, f

CPU

Reload value

(hex)

Baud rate

(baud)

CPU

Deviation error

CPU

= 40 MHz

= 40 MHz)

Reload value

(hex)

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Serial channels ST10F276E

Table 54. ASC synchronous baud rates by reload value and deviation errors (f

S0BRS = ‘0’, f

Baud rate

(baud)

900 0.0% / 0.0% 15B2 / 15B3 600 0.0% / 0.0% 15B2 / 15B3

612 0.0% / 0.0% 1FE8 / 1FE9 407 0.0% / 0.0% 1FFD / 1FFE

Table 55. ASC synchronous baud rates by reload value and deviation errors (f

S0BRS = ‘0’, f

Baud rate

(baud)

8 000 000 0.0% / 0.0% 0000 / 0000 5 333 333 0.0% / 0.0% 0000 / 0000

112 000 +0.6% / -0.8% 0046 / 0047 112 000 +1.3% / -0.8% 002E / 002F

56 000 +0.6% / -0.1% 008D / 008E 56 000 +0.3% / -0.8% 005E / 005F

38 400 +0.2% / -0.3% 00CF / 00D0 38 400 +0.6% / -0.1% 0089 / 008A

19 200 +0.2% / -0.1% 019F / 01A0 19 200 +0.3% / -0.1% 0114 / 0115

9 600 +0.0% / -0.1% 0340 / 0341 9 600 +0.1% / -0.1% 022A / 022B

4 800 0.0% / 0.0% 0681 / 0682 4 800 0.0% / -0.1% 0456 / 0457

Deviation error

= 40 MHz S0BRS = ‘1’, f

CPU

Reload value

(hex)

= 64 MHz S0BRS = ‘1’, f

CPU

Reload value

(hex)

Baud rate

(baud)

Baud rate

(baud)

CPU

Deviation error

CPU

Deviation error

CPU

= 40 MHz

CPU

= 64 MHz

= 40 MHz)

Reload value

(hex)

= 64 MHz)

Reload value

(hex)

2 400 0.0% / 0.0% 0D04 / 0D05 2 400 0.0% / 0.0% 08AD / 08AE

1 200 0.0% / 0.0% 1A09 / 1A0A 1 200 0.0% / 0.0% 115B / 115C

977 0.0% / 0.0% 1FFB / 1FFC 900 0.0% / 0.0% 1724 / 1725

652 0.0% / 0.0% 1FF2 / 1FF3

Note: The deviation errors given in the Ta b le 5 4 and Ta b l e 55 are rounded. To avoid deviation

errors use a Baud rate crystal (providing a multiple of the ASC0 sampling frequency)

14.4 High speed synchronous serial interfaces

The High-Speed Synchronous Serial Interfaces (SSC0 and SSC1) provides flexible highspeed serial communication between the ST10F276E and other microcontrollers, microprocessors or external peripherals.

The SSCx supports full-duplex and half-duplex synchronous communication. The serial clock signal can be generated by the SSCx itself (master mode) or be received from an external master (slave mode). Data width, shift direction, clock polarity and phase are programmable.

This allows communication with SPI-compatible devices. Transmission and reception of data is double-buffered. A 16-bit Baud rate generator provides the SSCx with a separate serial clock signal. The serial channel SSCx has its own dedicated 16-bit Baud rate generator with 16-bit reload capability, allowing Baud rate generation independent from the timers.

Ta bl e 5 6 and Ta bl e 5 7 list some possible Baud rates against the required reload values and

the resulting bit times for 40 MHz and 64 MHz CPU clock respectively. The maximum is anyway limited to 8 Mbaud.

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ST10F276E Serial channels

Table 56. Synchronous baud rate and reload values (f

Baud rate Bit time Reload value

Reserved --- 0000h

Can be used only with f

6.6M Baud 150ns 0002h

5M Baud 200ns 0003h

2.5M Baud 400ns 0007h

1M Baud 1µs 0013h

100K Baud 10µs 00C7h

10K Baud 100µs 07CFh

1K Baud 1ms 4E1Fh

306 Baud 3.26ms FF4Eh

Table 57. Synchronous baud rate and reload values (f

Reserved --- 0000h

= 32 MHz (or lower) --- 0001h

CPU

Baud rate Bit time Reload value

= 40 MHz)

CPU

= 64 MHz)

CPU

Can be used only with f

= 32 MHz (or lower) --- 0001h

CPU

= 48 MHz (or lower) --- 0002h

CPU

8M Baud 125ns 0003h

4M Baud 250ns 0007h

1M Baud 1µs 001Fh

100K Baud 10µs 013Fh

10K Baud 100µs 0C7Fh

1K Baud 1ms 7CFFh

489 Baud 2.04ms FF9Eh

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I2C interface ST10F276E

15 I2C interface

The integrated I2C Bus Module handles the transmission and reception of frames over the two-line SDA/SCL in accordance with the I

C Bus specification. The I2C Module can operate in slave mode, in master mode or in multi-master mode. It can receive and transmit data using 7-bit or 10-bit addressing. Data can be transferred at speeds up to 400 Kbit/s (both Standard and Fast I

C bus modes are supported).

The module can generate three different types of interrupt:

● Requests related to bus events, like start or stop events, arbitration lost, etc.

● Requests related to data transmission

● Requests related to data reception

These requests are issued to the interrupt controller by three different lines, and identified as Error, Transmit, and Receive interrupt lines.

When the I

C module is enabled by setting bit XI2CEN in XPERCON register, pins P4.4 and P4.7 (where SCL and SDA are respectively mapped as alternate functions) are automatically configured as bidirectional open-drain: the value of the external pull-up resistor depends on the application. P4, DP4 and ODP4 cannot influence the pin configuration.

When the I

C cell is disabled (clearing bit XI2CEN), P4.4 and P4.7 pins are standard I/ O controlled by P4, DP4 and ODP4.

The speed of the I

Fast I

C mode (100 to 400 kHz).

C interface may be selected between Standard mode (0 to 100 kHz) and

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ST10F276E CAN modules

16 CAN modules

The two integrated CAN modules (CAN1 and CAN2) are identical and handle the completely autonomous transmission and reception of CAN frames according to the CAN specification V2.0 part B (active). It is based on the C-CAN specification.

Each on-chip CAN module can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers.

Because of duplication of the CAN controllers, the following adjustments are to be considered:

● Same internal register addresses of both CAN controllers, but with base addresses

differing in address bit A8; separate chip select for each CAN module. Refer to

Chapter 4: Internal Flash memory.

● The CAN1 transmit line (CAN1_TxD) is the alternate function of the Port P4.6 pin and

the receive line (CAN1_RxD) is the alternate function of the Port P4.5 pin.

● The CAN2 transmit line (CAN2_TxD) is the alternate function of the Port P4.7 pin and

the receive line (CAN2_RxD) is the alternate function of the Port P4.4 pin.

● Interrupt request lines of the CAN1 and CAN2 modules are connected to the XBUS

interrupt lines together with other X-Peripherals sharing the four vectors.

● The CAN modules must be selected with corresponding CANxEN bit of XPERCON

● The reset default configuration is: CAN1 enabled, CAN2 disabled.

Note: If one or both CAN modules is used, Port 4 cannot be programmed to output all 8 segment

address lines. Thus, only four segment address lines can be used, reducing the external memory space to 5 Mbytes (1 Mbyte per CS

line).

16.1 Configuration support

It is possible that both CAN controllers are working on the same CAN bus, supporting together up to 64 message objects. In this configuration, both receive signals and both transmit signals are linked together when using the same CAN transceiver. This configuration is especially supported by providing open drain outputs for the CAN1_Txd and CAN2_TxD signals. The open drain function is controlled with the ODP4 register for port P4: in this way it is possible to connect together P4.4 with P4.5 (receive lines) and P4.6 with P4.7 (transmit lines configured to be configured as Open-Drain).

The user is also allowed to map internally both CAN modules on the same pins P4.5 and P4.6. In this way, P4.4 and P4.7 may be used either as general purpose I/O lines, or used

for I

C interface. This is possible by setting bit CANPAR of XMISC register. To access this register it is necessary to set bit XMISCEN of XPERCON register and bit XPEN of SYSCON register.

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CAN modules ST10F276E

16.2 CAN bus configurations

Depending on application, CAN bus configuration may be one single bus with a single or multiple interfaces or a multiple bus with a single or multiple interfaces. The ST10F276E is able to support these two cases.

Single CAN bus

The single CAN Bus multiple interfaces configuration may be implemented using two CAN transceivers as shown in Figure 20.

Figure 20. Connection to single CAN bus via separate CAN transceivers

XMISC.CANPAR = 0

CAN_H

CAN_L

CAN1

RX TX

CAN CAN

CAN bus

CAN2

RX TX

P4.4 P4.7P4.5 P4.6

TransceiverTransceiver

The ST10F276E also supports single CAN Bus multiple (dual) interfaces using the open drain option of the CANx_TxD output as shown in Figure 21. Thanks to the OR-Wired Connection, only one transceiver is required. In this case the design of the application must take in account the wire length and the noise environment.

Figure 21. Connection to single CAN bus via common CAN transceivers

XMISC.CANPAR = 0

2.7kW

CAN1

RX TX

+5V

CAN2

RX TX

P4.4 P4.7P4.5 P4.6

CAN

Transceiver

CAN_H

CAN_L

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CAN bus

OD = Open Drain Output

ST ST10F276E User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

1 Introduction

Figure 1. Logic symbol

2 Pin data

Figure 2. Pin configuration (top view)

Table 1. Pin description

3 Functional description

Figure 3. Block diagram

4 Internal Flash memory

4.1 Overview

Figure 4. Flash modules structure

4.2 Functional description

4.2.1 Structure

Table 2. Flash modules absolute mapping

4.2.2 Modules structure

Table 3. Flash modules sectorization (read operations)

Table 4. Flash modules sectorization (write operations or with ROMS1 = ‘1’)

Table 5. Control register interface

4.2.3 Low power mode

4.2.4 Write operation

4.2.5 Power supply drop

4.3 Registers description

4.3.1 Flash control register 0 low

Table 6. Flash control register 0 low

4.3.2 Flash control register 0 high

Table 7. Flash control register 0 high

4.3.3 Flash control register 1 low

Table 8. Flash control register 1 low

4.3.4 Flash control register 1 high

Table 9. Flash control register 1 high

Table 10. Banks (BxS) and sectors (BxFy) status bits meaning

4.3.5 Flash data register 0 low

Table 11. Flash data register 0 low

4.3.6 Flash data register 0 high

Table 12. Flash data register 0 high

4.3.7 Flash data register 1 low

Table 13. Flash data register 1 low

4.3.8 Flash data register 1 high

Table 14. Flash data register 1 high

4.3.9 Flash address register low

Table 15. Flash address register low

4.3.10 Flash address register high

Table 16. Flash address register high

4.3.11 Flash error register

Table 17. Flash error register

4.3.12 XFlash interface control register

Table 18. XFlash interface control register

4.4 Protection strategy

4.4.1 Protection registers

4.4.2 Flash non-volatile write protection X register low

Table 19. Flash non-volatile write protection X register low

4.4.3 Flash non-volatile write protection X register high

Table 20. Flash non-volatile write protection X register high

4.4.4 Flash non-volatile write protection I register low

Table 21. Flash non-volatile write protection I register low

4.4.5 Flash non-volatile write protection I register high

Table 22. Flash non-volatile write protection I register high

4.4.6 Flash non-volatile access protection register 0

Table 23. Flash non-volatile access protection register 0

4.4.7 Flash non-volatile access protection register 1 low

Table 24. Flash non-volatile access protection register 1 low

4.4.8 Flash non-volatile access protection register 1 high

Table 25. Flash non-volatile access protection register 1 high

4.4.9 Access protection

Table 26. Summary of access protection level

4.4.10 Write protection

4.4.11 Temporary unprotection

4.5 Write operation examples

4.6 Write operation summary

Table 27. Flash write operations

5 Bootstrap loader

5.1 Selection among user-code, standard or alternate bootstrap

Table 28. ST10F276E boot mode selection

5.2 Standard bootstrap loader

5.2.1 Entering the standard bootstrap loader

5.2.2 ST10 configuration in BSL

Table 29. ST10 configuration in BSL mode