ST ST10F276E, ST10F276Z5 User Manual

UM0404

User manual

High performance ST10F276Z5 and ST10F276E

16

-bit microcontrollers

Introduction

This manual describes the functionality of the ST10F276Z5 and ST10F276E devices.

An architectural overview describes the CPU performance, the on-chip system resources,
the on-chip clock generator, the on-chip peripheral blocks and the protected bits.

The operation of the CPU and the on-chip peripherals, and the different operating modes ­such as system reset, power reduction modes, interrupt handling, and system programming

- are described in individual sections.

The explanation of memory configuration has been restricted to that of the internal
addressable memory space. The ST10F276Z5 and ST10F276E Flash configurations are
not discussed in this manual. Refer to the ST10F276Z5 and ST10F276E datasheets for
detailed information (see Appendix B: Document references).

The Special Functional Registers are listed both by name and hexadecimal address. The
instruction set is covered in full in the ST10 Family Programming Manual and is, therefore,
not discussed in this manual. However, software programming feature - including constructs
for modularity, loops, and context switching - are described in Section 27: System

programming on page 525.

The DC and AC electrical specifications of the device and the pin description for each
available package, are not covered in this manual but are listed in the specific device
datasheets.

Before starting on a new design, verify the device characteristics and pinout with an up-to­date copy of the device datasheet.

The ST10F276Z5 and ST10F276E software and hardware development tools include:

• Compilers (C, C++), macro-assemblers, linkers, locators, library managers, format-

converters from Tasking & Keil

• HLL debuggers

• Real-time operating systems

• In-circuit emulators (based on Bond-out ST chips) from Hitex, Lauterbach, Nohau

• Logic analyzer disassemblers

• Evaluation boards with monitor programs from FORTH

• Industrial embedded Flash programming software from PLS

• Network driver software (CAN)

May 2013 DocID13284 Rev 2 1/564

www.st.com

Contents UM0404

Contents

1 Architectural overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

1.1 Basic CPU concepts and optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

1.1.1 High instruction bandwidth / fast execution . . . . . . . . . . . . . . . . . . . . . . 24

1.1.2 High function 8-bit and 16-bit ALU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

1.1.3 Extended bit processing and peripheral control . . . . . . . . . . . . . . . . . . . 25

1.1.4 High performance branch, call and loop processing . . . . . . . . . . . . . . . 25

1.1.5 Consistent and optimized instruction formats . . . . . . . . . . . . . . . . . . . . 26

1.1.6 Programmable multiple priority interrupt system . . . . . . . . . . . . . . . . . . 27

1.2 On-chip system resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

1.2.1 Peripheral event control and interrupt control . . . . . . . . . . . . . . . . . . . . 28

1.2.2 Memory areas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

1.2.3 External bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

1.3 Clock generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

1.3.1 PLL operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

1.3.2 Prescaler operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

1.3.3 Direct drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

1.3.4 Oscillator watchdog (OWD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

1.4 On-chip peripheral blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

1.4.1 Peripheral interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

1.4.2 Peripheral timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

1.4.3 Programming hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

1.4.4 Parallel ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

1.4.5 Serial channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

1.4.6 General purpose timer (GPT) unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

1.4.7 Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

1.4.8 Capture / compare (CAPCOM) units . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

1.4.9 Pulse width modulation unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

1.4.10 A/D converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

1.4.11 CAN module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

1.4.12 I2C serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

1.5 Real time clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

1.6 Protected bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

2 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

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2.1 Word, byte and bit storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

2.2 On-chip Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

2.3 IRAM and SFR area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

2.3.1 System stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

2.3.2 General purpose registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

2.3.3 PEC source and destination pointers . . . . . . . . . . . . . . . . . . . . . . . . . . 47

2.3.4 Special function registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

2.4 The on-chip XRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

2.4.1 XRAM access via external masters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

2.5 External memory space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

2.6 Crossing memory boundaries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

3 The central processing unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

3.1 Instruction pipelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

3.1.1 Sequential instruction processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

3.1.2 Standard branch instruction processing . . . . . . . . . . . . . . . . . . . . . . . . . 55

3.1.3 Cache jump instruction processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

3.1.4 Particular pipeline effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

3.2 Bit-handling and bit-protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

3.3 Instruction execution times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

3.4 CPU special function registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

3.4.1 The system configuration register SYSCON . . . . . . . . . . . . . . . . . . . . . 62

3.4.2 X-Peripherals control register (XPERCON) . . . . . . . . . . . . . . . . . . . . . . 65

3.4.3 XPERCON and XPEREMU registers . . . . . . . . . . . . . . . . . . . . . . . . . . 66

3.4.4 Emulation dedicated registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

3.4.5 The processor status word PSW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

3.4.6 The instruction pointer IP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

3.4.7 The code segment pointer CSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

3.4.8 The data page pointers DPP0, DPP1, DPP2, DPP3 . . . . . . . . . . . . . . . 72

3.4.9 The context pointer CP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

3.4.10 The stack pointer SP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

3.4.11 The stack overflow pointer STKOV . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

3.4.12 The stack underflow pointer STKUN . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

3.4.13 The multiply / divide high register MDH . . . . . . . . . . . . . . . . . . . . . . . . . 78

3.4.14 The multiply / divide low register MDL . . . . . . . . . . . . . . . . . . . . . . . . . . 78

3.4.15 The multiply / divide control register MDC . . . . . . . . . . . . . . . . . . . . . . . 79

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3.4.16 The constant zeros register ZEROS . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

3.4.17 The constant ones register ONES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

4 Multiply-accumulate unit (MAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

4.1 MAC features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

4.2 MAC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

4.2.1 Instruction pipelining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

4.2.2 Particular pipeline effects with the MAC unit . . . . . . . . . . . . . . . . . . . . . 84

4.2.3 Address generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

4.2.4 16 x 16 signed/unsigned parallel multiplier . . . . . . . . . . . . . . . . . . . . . . 86

4.2.5 40-bit signed arithmetic unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

4.2.6 The 40-bit signed accumulator register . . . . . . . . . . . . . . . . . . . . . . . . . 87

4.2.7 The 40-bit adder / subtracter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

4.2.8 Data limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

4.2.9 The accumulator shifter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

4.2.10 Repeat unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

4.2.11 MAC interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

4.2.12 Number representation & rounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

4.3 MAC register set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

4.3.1 Address registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

4.3.2 Accumulator & control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

4.4 MAC instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

5 Interrupt and trap functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

5.1 Interrupt system structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

5.1.1 Normal interrupt processing and PEC service . . . . . . . . . . . . . . . . . . . 100

5.1.2 Interrupt system register description . . . . . . . . . . . . . . . . . . . . . . . . . . 100

5.1.3 Interrupt control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

5.1.4 Interrupt priority level and group level . . . . . . . . . . . . . . . . . . . . . . . . . 101

5.1.5 Interrupt control functions in the PSW . . . . . . . . . . . . . . . . . . . . . . . . . 103

5.2 Operation of the PEC channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

5.3 Prioritizing interrupt & PEC service requests . . . . . . . . . . . . . . . . . . . . . 106

5.3.1 Enabling and disabling interrupt requests . . . . . . . . . . . . . . . . . . . . . . 106

5.3.2 Interrupt class management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

5.4 Saving the status during interrupt service . . . . . . . . . . . . . . . . . . . . . . . 108

5.4.1 Context switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

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5.5 Interrupt response times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110

5.5.1 PEC response times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

5.6 External interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113

5.6.1 Fast external interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

5.7 X-peripheral interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117

5.8 Trap functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

5.8.1 Software traps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

5.8.2 Hardware traps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

5.8.3 External NMI trap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

5.8.4 Stack overflow trap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

5.8.5 Stack underflow trap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

5.8.6 Undefined opcode trap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

5.8.7 MAC interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

5.8.8 Protection fault trap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

5.8.9 Illegal word operand access trap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

5.8.10 Illegal instruction access trap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

5.8.11 Illegal external bus access trap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

6 Parallel ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

6.1.1 Open drain mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

6.1.2 Input threshold control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

6.1.3 Alternate port functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

6.2 PORT0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

6.2.1 Alternate functions of PORT0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

6.3 PORT1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

6.3.1 Alternate functions of PORT1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

6.3.2 PORT1 analog inputs disturb protection . . . . . . . . . . . . . . . . . . . . . . . 144

6.4 Port2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

6.4.1 Alternate functions of Port2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

6.4.2 External interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

6.5 Port3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

6.5.1 Alternate functions of Port3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

6.6 Port4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

6.6.1 Alternate functions of Port4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

6.7 Port5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

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6.7.1 Alternate functions of Port5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

6.7.2 Port5 analog inputs disturb protection . . . . . . . . . . . . . . . . . . . . . . . . . 163

6.8 Port6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

6.8.1 Alternate functions of Port6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

6.9 Port7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

6.9.1 Alternate functions of Port7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

6.10 Port8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

6.10.1 Alternate functions of Port8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

7 Dedicated pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

8 The external bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

8.1 Single chip mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

8.2 External bus modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

8.2.1 Multiplexed bus modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

8.2.2 De-multiplexed bus modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

8.2.3 Switching between the bus modes . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

8.2.4 External data bus width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186

8.2.5 Disable / enable control for pin BHE (BYTDIS) . . . . . . . . . . . . . . . . . . 187

8.2.6 Segment address generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

8.2.7 CS signal generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188

8.2.8 Segment address versus chip select . . . . . . . . . . . . . . . . . . . . . . . . . . 189

8.3 Programmable bus characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190

8.3.1 ALE length control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190

8.3.2 Programmable memory cycle time . . . . . . . . . . . . . . . . . . . . . . . . . . . 191

8.3.3 Programmable memory tri-state time . . . . . . . . . . . . . . . . . . . . . . . . . 192

8.3.4 Read / write signal delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193

8.3.5 READY polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194

8.3.6 READY / READY controlled bus cycles . . . . . . . . . . . . . . . . . . . . . . . . 194

8.3.7 Programmable chip select timing control . . . . . . . . . . . . . . . . . . . . . . . 196

8.4 Controlling the external bus controller . . . . . . . . . . . . . . . . . . . . . . . . . . 196

8.4.1 Definition of address areas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201

8.4.2 Address window arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201

8.4.3 Precautions and hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203

8.5 EBC idle state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203

8.6 External bus arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204

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8.6.1 Connecting bus masters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204

8.6.2 Entering the hold state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205

8.6.3 Exiting the hold state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206

8.7 The XBUS interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207

8.8 EA functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213

9 The general purpose timer units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215

9.1 Timer block GPT1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215

9.1.1 GPT1 core timer T3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217

9.1.2 GPT1 auxiliary timers T2 and T4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224

9.1.3 Interrupt control for GPT1 timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231

9.2 Timer block GPT2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232

9.2.1 GPT2 core timer T6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234

9.2.2 Interrupt control for GPT2 timers and CAPREL . . . . . . . . . . . . . . . . . . 244

10 Asynchronous / synchronous serial interface . . . . . . . . . . . . . . . . . . 246

10.1 Asynchronous operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249

10.2 Synchronous operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251

10.3 Hardware error detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253

10.4 ASC0 baud rate generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253

10.5 ASC0 interrupt control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254

11 XBUS asynchronous / synchronous serial interface . . . . . . . . . . . . . 257

11.1 Asynchronous operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261

11.2 Synchronous operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264

11.3 Hardware error detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266

11.4 XASC baud rate generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266

11.5 XASC interrupt control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267

12 High-speed synchronous serial interface . . . . . . . . . . . . . . . . . . . . . . 270

12.1 Full-duplex operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275

12.2 Half duplex operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278

12.2.1 Port control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279

12.3 Baud rate generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280

12.4 Error detection mechanisms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281

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12.5 SSC interrupt control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282

13 XBUS high-speed synchronous serial interface . . . . . . . . . . . . . . . . 284

13.1 Full-duplex operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290

13.2 Half duplex operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293

13.2.1 Port control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294

13.3 Baud rate generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294

13.4 Error detection mechanisms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295

13.5 XSSC interrupt control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296

14 Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297

14.1 Operation of the watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298

15 The bootstrap loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302

15.1 Selection among user-code, standard or alternate bootstrap . . . . . . . . 302

15.2 Standard bootstrap loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303

15.2.1 Entering the standard bootstrap loader . . . . . . . . . . . . . . . . . . . . . . . . 303

15.2.2 ST10 configuration in BSL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305

15.2.3 Booting steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305

15.2.4 Hardware to activate BSL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306

15.2.5 Memory configuration in bootstrap loader mode . . . . . . . . . . . . . . . . . 307

15.2.6 Loading the start-up code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308

15.2.7 Exiting bootstrap loader mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308

15.2.8 Hardware requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309

15.3 Standard bootstrap with UART (RS232 or K-Line) . . . . . . . . . . . . . . . . . 309

15.3.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309

15.3.2 Entering bootstrap via UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310

15.3.3 ST10 configuration in UART BSL (RS232 or K-line) . . . . . . . . . . . . . . 310

15.3.4 Loading the start-up code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311

15.3.5 Choosing the baud rate for the BSL via UART . . . . . . . . . . . . . . . . . . 312

15.4 Standard bootstrap with CAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313

15.4.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313

15.4.2 Entering the CAN bootstrap loader . . . . . . . . . . . . . . . . . . . . . . . . . . . 314

15.4.3 ST10 configuration in CAN BSL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315

15.4.4 Loading the start-up code via CAN . . . . . . . . . . . . . . . . . . . . . . . . . . . 315

15.4.5 Choosing the baudrate for the BSL via CAN . . . . . . . . . . . . . . . . . . . . 316

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15.4.6 How to compute the baud rate error . . . . . . . . . . . . . . . . . . . . . . . . . . 318

15.4.7 Bootstrap via CAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319

15.5 Comparing the old and the new bootstrap loader . . . . . . . . . . . . . . . . . 319

15.5.1 Software aspects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319

15.5.2 Hardware aspects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320

15.6 Alternate boot mode (ABM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320

15.6.1 Activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320

15.6.2 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320

15.6.3 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320

15.6.4 ST10 configuration in alternate boot mode . . . . . . . . . . . . . . . . . . . . . 321

15.6.5 Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321

15.6.6 Exiting alternate boot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321

15.6.7 Alternate boot user software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322

15.6.8 User/alternate mode signature integrity check . . . . . . . . . . . . . . . . . . 322

15.6.9 Alternate boot user software aspects . . . . . . . . . . . . . . . . . . . . . . . . . . 322

15.6.10 EMUCON register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322

15.6.11 Internal decoding of test modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323

15.6.12 Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323

15.7 Selective boot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323

16 The capture / compare units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326

16.1 CAPCOM timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329

16.2 CAPCOM unit timer interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333

16.3 Capture / compare registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333

16.3.1 Selection of capture modes and compare modes . . . . . . . . . . . . . . . . 335

16.4 Capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336

16.5 Compare modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336

16.5.1 Compare mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337

16.5.2 Compare mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338

16.5.3 Compare mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339

16.5.4 Compare mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340

16.5.5 Double register compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341

16.6 Capture / compare interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343

17 Pulse width modulation module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345

17.1 Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347

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17.1.1 Mode 0: standard PWM generation (edge aligned PWM) . . . . . . . . . . 347

17.1.2 Mode 1: symmetrical PWM generation (center aligned PWM) . . . . . . 348

17.1.3 Burst mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349

17.1.4 Single shot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350

17.2 PWM module registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351

17.3 Interrupt request generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354

17.4 PWM output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355

18 XBUS pulse width modulation module . . . . . . . . . . . . . . . . . . . . . . . . 357

18.1 Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359

18.1.1 Mode 0: standard PWM generation (edge aligned PWM) . . . . . . . . . . 359

18.1.2 Mode 1: symmetrical PWM generation (center aligned PWM) . . . . . . 360

18.1.3 Burst mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361

18.1.4 Single shot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362

18.2 XPWM module registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363

18.3 Interrupt request generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367

18.4 XPWM output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368

19 Analog / digital converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370

19.1 Mode selection and operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372

19.1.1 Fixed channel conversion modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375

19.1.2 Auto scan conversion modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376

19.1.3 Wait for ADDAT read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377

19.1.4 Channel injection mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377

19.1.5 ADC power off (ADOFF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380

19.2 Conversion timing control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381

19.3 A/D converter interrupt control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382

19.4 Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383

19.5 A/D conversion accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383

19.5.1 Total unadjusted error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384

19.5.2 Analog reference pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385

19.5.3 Analog input pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385

19.5.4 Example of external network sizing . . . . . . . . . . . . . . . . . . . . . . . . . . . 390

20 I2C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392

20.1 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392

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20.2 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393

20.2.1 Mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393

20.2.2 Communication flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393

20.2.3 SDA/SCL line control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394

20.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395

20.3.1 Slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395

20.3.2 Master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397

20.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400

20.5 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403

21 CAN modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410

21.1 Memory and pin mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410

21.1.1 CAN1 mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410

21.1.2 CAN2 mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410

21.1.3 Register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410

21.2 Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413

21.3 Configuration support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413

21.3.1 Configuration examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414

21.4 Clock Prescaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416

21.5 CAN module: functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417

21.6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418

21.7 Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418

21.7.1 Software initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418

21.7.2 CAN message transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419

21.7.3 Disabled automatic re-transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . 419

21.7.4 Test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420

21.7.5 Silent mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420

21.7.6 Loop back mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420

21.7.7 Loop back combined with silent mode . . . . . . . . . . . . . . . . . . . . . . . . . 421

21.7.8 Basic mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422

21.7.9 Software control of pin CAN_TxD . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422

21.8 Programmer’s model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422

21.8.1 Hardware reset description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424

21.8.2 CAN protocol related registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424

21.8.3 Message interface register sets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429

21.8.4 Message handler registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441

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21.9 CAN application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 444

21.9.1 Management of message objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . 444

21.9.2 Message handler state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445

21.9.3 Configuration of a transmit object . . . . . . . . . . . . . . . . . . . . . . . . . . . . 448

21.9.4 Updating a transmit object . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 448

21.9.5 Configuration of a receive object . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 448

21.9.6 Handling of received messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 449

21.9.7 Configuration of a FIFO buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 449

21.9.8 Reception of messages with FIFO buffers . . . . . . . . . . . . . . . . . . . . . . 450

21.9.9 Handling of interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 451

21.9.10 Configuration of the bit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 452

22 Real time clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 464

22.1 RTC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 466

22.1.1 RTCCON: RTC control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 466

22.1.2 RTCPH & RTCPL: RTC prescaler registers . . . . . . . . . . . . . . . . . . . . 467

22.1.3 RTCDH & RTCDL: RTC divider counters . . . . . . . . . . . . . . . . . . . . . . 468

22.1.4 RTCH & RTCL: RTC programmable counter registers . . . . . . . . . . . . 469

22.1.5 RTCAH & RTCAL: RTC alarm registers . . . . . . . . . . . . . . . . . . . . . . . 469

22.2 Programming the RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470

23 System reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 472

23.1 Input filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 472

23.2 Asynchronous reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 472

23.3 Synchronous reset (warm reset) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477

23.4 Software reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483

23.5 Watchdog timer reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 484

23.6 Bidirectional reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 486

23.7 Reset circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 490

23.8 Reset application examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492

23.9 Reset summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495

23.9.1 System start-up configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496

24 Power reduction modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502

24.1 Idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503

24.2 Power down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504

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24.2.1 Protected power down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506

24.2.2 Interruptible power down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506

24.3 Stand-by mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509

24.3.1 Entering stand-by mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510

24.3.2 Exiting stand-by mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511

24.3.3 Real time clock and stand-by mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 511

24.4 Output pin status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .511

25 Programmable output clock divider . . . . . . . . . . . . . . . . . . . . . . . . . . 514

26 Register set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 515

26.1 Register description format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 515

26.2 General purpose registers (GPRs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 516

26.3 Special function registers ordered by name . . . . . . . . . . . . . . . . . . . . . . 517

26.4 Special function registers ordered by address . . . . . . . . . . . . . . . . . . . . 524

26.5 X-Registers ordered by name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 531

26.6 X-Registers ordered by address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 536

26.7 Flash registers ordered by name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 541

26.8 Flash registers ordered by address . . . . . . . . . . . . . . . . . . . . . . . . . . . . 541

26.9 Special notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542

26.10 Identification registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 543

27 System programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 545

27.1 Stack operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 547

27.2 Register banking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 551

27.3 Procedure call entry and exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 551

27.4 Table searching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 553

27.5 Peripheral control and interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 554

27.6 Floating point support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 554

27.7 Trap / interrupt entry and exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 554

27.8 Inseparable instruction sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 555

27.9 Overriding the DPP addressing mechanism . . . . . . . . . . . . . . . . . . . . . 555

27.10 Handling the internal Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 556

27.11 Pits, traps and mines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 558

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Appendix A Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 559

Appendix B Document references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 560

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 561

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List of tables

Table 1. Protected bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 2. Segment 8 address range mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 3. 512 Kbyte IFlash memory block organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 4. 320 Kbyte XFlash memory block organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 5. Stack size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 6. Mapping of general purpose registers to RAM addresses . . . . . . . . . . . . . . . . . . . . . . . . . 47

Table 7. Minimum execution times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Table 8. Stack size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Table 9. Shift right rounding error evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Table 10. Pointer post-modification combinations for IDXi and Rwn . . . . . . . . . . . . . . . . . . . . . . . . . 85

Table 11. Parallel data move addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Table 12. Limiter output using CoSTORE instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Table 13. MAC register address in CoReg addressing mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Table 14. MAC instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Table 15. Interrupt and PEC service request sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Table 16. Vector locations and status for hardware traps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Table 17. PEC control register addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Table 18. Example of software controlled interrupt classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Table 19. Pins to be used as external interrupt inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

Table 20. X-Interrupt detailed mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

Table 21. Trap priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

Table 22. Port2 alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

Table 23. Port3 alternative functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

Table 24. Port4 alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

Table 25. Port5 alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

Table 26. Port6 alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

Table 27. Port7 alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

Table 28. Port8 alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

Table 29. Summary of dedicated pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

Table 30. Definition of address areas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201

Table 31. Status of the external bus interface during EBC idle state . . . . . . . . . . . . . . . . . . . . . . . . 203

Table 32. Definition of XBUS address areas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208

Table 33. GPT1 core timer T3 count direction control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218

Table 34. GPT1 timer resolutions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220

Table 35. GPT1 core timer T3 (counter mode) input edge selection . . . . . . . . . . . . . . . . . . . . . . . . 221

Table 36. GPT1 core timer T3 (incremental interface mode) input edge selection. . . . . . . . . . . . . . 222

Table 37. GPT1 auxiliary timer (counter mode) input edge selection . . . . . . . . . . . . . . . . . . . . . . . . 226

Table 38. GPT2 core timer T6 count direction control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235

Table 39. GPT2 timer resolution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237

Table 40. GPT2 core timer T6 (counter mode) input edge selection . . . . . . . . . . . . . . . . . . . . . . . . 238

Table 41. GPT2 auxiliary timer (counter mode) input edge selection . . . . . . . . . . . . . . . . . . . . . . . . 240

Table 42. WDTCON bits value on different resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299

Table 43. WDTREL reload value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300

Table 44. Reset events summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300

Table 45. ST10F276x boot mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303

Table 46. Ranges of timer contents versus BRP value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317

Table 47. Software topics summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319

Table 48. Hardware topics summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320

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List of tables UM0404

Table 49. Summary of compare modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337

Table 50. Register pairs for double-register compare mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341

Table 51. CAPCOM unit interrupt control register addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344

Table 52. PWM frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352

Table 53. PWM module channel specific register addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353

Table 54. XPWM frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364

Table 55. XPWM module channel specific register addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365

Table 56. ADC sampling and conversion timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382

Table 57. Interrupt event summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401

Table 58. CAN1 register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411

Table 59. CAN2 register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412

Table 60. C-CAN register memory space summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423

Table 61. IF1 and IF2 message interface register sets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429

Table 62. Parameters of the CAN bit time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453

Table 63. Reset event definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 472

Table 64. Reset events summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495

Table 65. PORT0 latched configuration for the different reset events . . . . . . . . . . . . . . . . . . . . . . . 497

Table 66. Power reduction modes summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503

Table 67. Output pin state during Idle and power down modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512

Table 68. General purpose registers (GPRs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 516

Table 69. General purpose registers (GPRs) bit wise addressing . . . . . . . . . . . . . . . . . . . . . . . . . . 516

Table 70. Special function registers ordered by name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 517

Table 71. Special function registers ordered by address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 524

Table 72. X-Registers ordered by name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 531

Table 73. X-Registers ordered by address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 536

Table 74. Flash registers ordered by name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 541

Table 75. Flash registers ordered by address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 541

Table 76. Stack size selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 548

Table 77. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 561

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List of figures

Figure 1. ST10F276x functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 2. CPU block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 3. Clock block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 4. ST10F276 memory mapping (user mode: Flash Read operation) . . . . . . . . . . . . . . . . . . . 41

Figure 5. Storage of words, bytes and bits in a byte organized memory . . . . . . . . . . . . . . . . . . . . . . 42

Figure 6. On-chip RAM and SFR/ESFR areas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Figure 7. Location of the PEC pointers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Figure 8. CPU block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Figure 9. Sequential instruction pipelining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Figure 10. Standard branch instruction pipelining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Figure 11. Cache jump instruction pipelining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Figure 12. Addressing via the code segment pointer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Figure 13. Addressing via the data page pointers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Figure 14. Register bank selection via register CP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Figure 15. Implicit CP use by short GPR addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Figure 16. MAC architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Figure 17. Example of parallel data move . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Figure 18. Pipeline diagram for MAC interrupt response time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Figure 19. Priority levels and PEC channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Figure 20. Mapping of PEC pointers into the IRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Figure 21. Task status saved on the system stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Figure 22. Pipeline diagram for interrupt response time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

Figure 23. Pipeline diagram for PEC response time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

Figure 24. X-Interrupt basic structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

Figure 25. SFRs, XBUS registers and pins associated with the parallel ports. . . . . . . . . . . . . . . . . . 136

Figure 26. Output drivers in push-pull mode and in open drain mode . . . . . . . . . . . . . . . . . . . . . . . . 137

Figure 27. Hysteresis concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

Figure 28. PORT0 I/O and alternate functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

Figure 29. Block diagram of a PORT0 pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

Figure 30. PORT1 I/O and alternate functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

Figure 31. Block diagram of input section of a P1L pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

Figure 32. Block diagram of a PORT1 pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

Figure 33. Port2 I/O and alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

Figure 34. Block diagram of a Port2 pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

Figure 35. Port3 I/O and alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

Figure 36. Block diagram of a Port3 pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

Figure 37. Block diagram of P3.15 (CLKOUT) and P3.12 (BHE/WRH) pins . . . . . . . . . . . . . . . . . . . 154

Figure 38. Port4 I/O and alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

Figure 39. Block diagram of Port4 pins 3...0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

Figure 40. Block diagram of P4.4 pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

Figure 41. Block diagram of P4.5 pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

Figure 42. Block diagram of P4.6 pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

Figure 43. Block diagram of P4.7 pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

Figure 44. Port5 I/O and alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

Figure 45. Block diagram of a Port5 pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

Figure 46. Port6 I/O and alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

Figure 47. Block diagram of Port6 pins 4...0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

Figure 48. Block diagram of P6.5 pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

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Figure 49. Port7 I/O and alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

Figure 50. Block diagram of Port7 pins 3...0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

Figure 51. Block diagram of Port7 pins 7...4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

Figure 52. Port8 I/O and alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

Figure 53. Block diagram of Port8 pins 3...0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

Figure 54. Block diagram of P8.4 and P8.5 pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

Figure 55. Block diagram of P8.6 pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

Figure 56. RPD external RC circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

Figure 57. SFRs and port pins associated with the external bus interface . . . . . . . . . . . . . . . . . . . . 182

Figure 58. Multiplexed bus cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

Figure 59. De-multiplexed bus cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

Figure 60. Switching from de-multiplexed to multiplexed bus mode . . . . . . . . . . . . . . . . . . . . . . . . . 187

Figure 61. Programmable external bus cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190

Figure 62. ALE length control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191

Figure 63. Memory cycle time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

Figure 64. Memory tri-state time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193

Figure 65. Read / write delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194

Figure 66. READY/READY controlled bus cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

Figure 67. Chip select delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

Figure 68. Address window arbitration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202

Figure 69. Sharing external resources using slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205

Figure 70. External bus arbitration, releasing the bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206

Figure 71. External bus arbitration, (regaining the bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207

Figure 72. Memory mapping (User mode: Flash read operations / XADRS = 800Bh) . . . . . . . . . . . 210

Figure 73. Memory mapping (User mode: Flash read operations / XADRS = C00Ah) . . . . . . . . . . . 211

Figure 74. EA / VSTBY external circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214

Figure 75. SFRs and port pins associated with timer block GPT1. . . . . . . . . . . . . . . . . . . . . . . . . . . 216

Figure 76. GPT1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217

Figure 77. Core timer T3 in timer mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219

Figure 78. Core timer T3 in gated timer mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221

Figure 79. Core timer T3 in counter mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221

Figure 80. Core timer T3 in incremental interface mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222

Figure 81. Connection of the encoder to the ST10F276 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223

Figure 82. Evaluation of the incremental encoder signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224

Figure 83. Evaluation of the incremental encoder signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224

Figure 84. Auxiliary timer in counter mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226

Figure 85. Concatenation of core timer T3 and an auxiliary timer . . . . . . . . . . . . . . . . . . . . . . . . . . . 228

Figure 86. GPT1 auxiliary timer in reload mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228

Figure 87. GPT1 timer reload configuration for PWM generation . . . . . . . . . . . . . . . . . . . . . . . . . . . 230

Figure 88. GPT1 auxiliary timer in capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231

Figure 89. SFRs and port pins associated with timer block GPT2. . . . . . . . . . . . . . . . . . . . . . . . . . . 233

Figure 90. GPT2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234

Figure 91. Block diagram of core timer T6 in timer mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236

Figure 92. Block diagram of core timer T6 in gated timer mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237

Figure 93. Block diagram of core timer T6 in counter mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238

Figure 94. Block diagram of auxiliary timer T5 in counter mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240

Figure 95. Concatenation of core timer T6 and auxiliary timer T5 . . . . . . . . . . . . . . . . . . . . . . . . . . . 242

Figure 96. GPT2 register CAPREL in capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242

Figure 97. GPT2 register CAPREL in reload mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243

Figure 98. GPT2 register CAPREL in capture-and-reload mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244

Figure 99. SFRs and port pins associated with ASC0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246

Figure 100. Asynchronous mode of serial channel ASC0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249

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Figure 101. Asynchronous 8-bit data frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250

Figure 102. Asynchronous 9-bit data frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251

Figure 103. Synchronous mode of serial channel ASC0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252

Figure 104. ASC0 interrupt generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256

Figure 105. XBUS registers and port pins associated with XASC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258

Figure 106. Asynchronous mode of serial channel XASC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262

Figure 107. Asynchronous 8-bit data frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262

Figure 108. Asynchronous 9-bit data frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264

Figure 109. Synchronous mode of serial channel XASC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265

Figure 110. XASC interrupt generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269

Figure 111. SFRs and port pins associated with the SSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271

Figure 112. Synchronous serial channel SSC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272

Figure 113. Serial clock phase and polarity options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276

Figure 114. SSC full duplex configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276

Figure 115. SSC half duplex configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279

Figure 116. SSC error interrupt control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282

Figure 117. XBUS registers and port pins associated with the XSSC . . . . . . . . . . . . . . . . . . . . . . . . . 285

Figure 118. Synchronous serial channel XSSC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286

Figure 119. Serial clock phase and polarity options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290

Figure 120. XSSC full duplex configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291

Figure 121. XSSC half duplex configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293

Figure 122. SFRs and port pins associated with the watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . 297

Figure 123. Watchdog timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297

Figure 124. ST10F276x new standard bootstrap loader program flow . . . . . . . . . . . . . . . . . . . . . . . . 304

Figure 125. Booting steps for ST10F276 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306

Figure 126. Hardware provisions to activate the BSL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307

Figure 127. Memory configuration after reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308

Figure 128. UART bootstrap loader sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310

Figure 129. Baudrate deviation between host and ST10F276. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312

Figure 130. CAN bootstrap loader sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313

Figure 131. Bitrate measurement over a predefined zero-frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316

Figure 132. Reset boot sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325

Figure 133. SFRs and Port Pins associated with the CAPCOM units . . . . . . . . . . . . . . . . . . . . . . . . . 327

Figure 134. CAPCOM unit block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329

Figure 135. Block diagram of CAPCOM timers T0 and T7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330

Figure 136. Block diagram of CAPCOM timers T1 and T8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330

Figure 137. Capture mode block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336

Figure 138. Compare mode 0 and 1 block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338

Figure 139. Timing example for compare modes 0 and 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339

Figure 140. Compare mode 2 and 3 block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340

Figure 141. Timing example for compare modes 2 and 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340

Figure 142. Double register compare mode block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342

Figure 143. Timing example for double register compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343

Figure 144. SFRs and port pins associated with the PWM module . . . . . . . . . . . . . . . . . . . . . . . . . . . 346

Figure 145. PWM channel block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347

Figure 146. Operation and output waveform in mode 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348

Figure 147. Operation and output waveform in mode 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349

Figure 148. Operation and output waveform in burst mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350

Figure 149. Operation and output waveform in single shot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351

Figure 150. PWM output signal generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356

Figure 151. XBUS registers and port pins associated with the XPWM module . . . . . . . . . . . . . . . . . . 358

Figure 152. XPWM channel block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359

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Figure 153. Operation and output waveform in mode 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360

Figure 154. Operation and output waveform in mode 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361

Figure 155. Operation and output waveform in burst mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362

Figure 156. Operation and output waveform in single shot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363

Figure 157. XPWM output signal generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369

Figure 158. SFRs, XBUS registers and port pins associated with the A/D converter . . . . . . . . . . . . . 371

Figure 159. Analog / digital converter block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372

Figure 160. Auto scan conversion mode example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376

Figure 161. Wait for read mode example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377

Figure 162. Channel injection example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379

Figure 163. Channel injection example with wait for read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380

Figure 164. A/D conversion characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385

Figure 165. A/D converter input pins scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386

Figure 166. Charge sharing timing diagram during sampling phase . . . . . . . . . . . . . . . . . . . . . . . . . . 387

Figure 167. Anti-aliasing filter and conversion rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389

Figure 168. I2C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393

2

Figure 169. I

C interface block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395

Figure 170. Transfer sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399

Figure 171. Event flags and interrupt generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401

Figure 172. Connection to single CAN bus via separate CAN transceivers . . . . . . . . . . . . . . . . . . . . 415

Figure 173. Connection to single CAN bus via one common transceiver . . . . . . . . . . . . . . . . . . . . . . 415

Figure 174. Connection to two different CAN buses (e.g. for gateway application). . . . . . . . . . . . . . . 416

Figure 175. Connection to one CAN bus with internal parallel mode enabled. . . . . . . . . . . . . . . . . . . 416

Figure 176. Block diagram of the C-CAN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418

Figure 177. CAN core in silent mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420

Figure 178. CAN core in loop back mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421

Figure 179. CAN core in loop back combined with silent mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421

Figure 180. Data transfer between IFx registers and message RAM . . . . . . . . . . . . . . . . . . . . . . . . . 446

Figure 181. CPU handling of a FIFO buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 451

Figure 182. Bit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453

Figure 183. The propagation time segment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454

Figure 184. Synchronization on “late” and “early” edges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456

Figure 185. Filtering of short dominant spikes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457

Figure 186. Structure of the CAN Core’s CAN protocol controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461

Figure 187. SFRs associated with the RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 465

Figure 188. XBUS registers associated with the RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 465

Figure 189. RTC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 466

Figure 190. Prescaler register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 468

Figure 191. Divider counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 469

Figure 192. Asynchronous power-on RESET (EA = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474

Figure 193. Asynchronous power-on RESET (EA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475

Figure 194. Asynchronous hardware RESET (EA = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476

Figure 195. Asynchronous hardware RESET (EA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477

Figure 196. Synchronous short / long hardware RESET (EA = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 480

Figure 197. Synchronous short / long hardware RESET (EA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 481

Figure 198. Synchronous long hardware RESET (EA = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 482

Figure 199. Synchronous long hardware RESET (EA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483

Figure 200. SW / WDT unidirectional RESET (EA = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485

Figure 201. SW / WDT unidirectional RESET (EA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 486

Figure 202. SW / WDT bidirectional RESET(EA = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 488

Figure 203. SW / WDT bidirectional RESET (EA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489

Figure 204. SW / WDT bidirectional RESET (EA = 0) followed by a HW RESET . . . . . . . . . . . . . . . . 490

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UM0404 List of figures

Figure 205. Minimum external reset circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491

Figure 206. System reset circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492

Figure 207. Example of software or watchdog bidirectional reset (EA = 1) . . . . . . . . . . . . . . . . . . . . . 493

Figure 208. Example of software or watchdog bidirectional reset (EA = 0) . . . . . . . . . . . . . . . . . . . . . 494

Figure 209. PORT0 bits latched into the different registers after reset . . . . . . . . . . . . . . . . . . . . . . . . 497

Figure 210. Transitions between Idle mode and active mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504

Figure 211. RPD pin: external circuit to exit power down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 507

Figure 212. Simplified power down exit circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 508

Figure 213. Power down exit sequence using an external interrupt (PLL x 2) real time clock and power

down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509

Figure 214. Physical stack address generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 549

Figure 215. Local registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 553

DocID13284 Rev 2 21/564

Architectural overview UM0404

1 Architectural overview

ST10F276 architecture combines the advantages of both RISC and CISC processors with

an advanced peripheral subsystem. The following block diagram gives an overview of the

different on-chip components and of the advanced, high bandwidth internal bus structure of

the ST10F276 (see Figure 1).

1.1 Basic CPU concepts and optimization

The main core of the CPU includes a 4-stage instruction pipeline, a 16-bit arithmetic and

logic unit (ALU) and dedicated SFRs.

Additional hardware is provided for a separate multiply and divide unit, a bit-mask generator

and a barrel shifter (see Figure 2).

Several areas of the processor core have been optimized for performance and flexibility.

Functional blocks in the CPU core are controlled by signals from the instruction decode

logic. The core improvements are summarized below, and described in detail in the

following sections:

1. High instruction bandwidth / fast execution

2. High function 8-bit and 16-bit arithmetic and logic unit

3. Extended bit processing and peripheral control

4. High performance branch, call and loop processing

5. Consistent and optimized instruction formats

6. Programmable multiple priority interrupt structure

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UM0404 Architectural overview

External Bus

Controller

10-bit ADC

GPT1 / GPT2

ASC0

BRG BRG

SSC0

PWM

CAPCOM2

CAPCOM1

Por t 0Por t 1Por t 4

Por t 6 Por t 5

CPU-Core and MAC Unit

XCAN2

XSSC

XASC

XCAN1

XI2C

XRAM

2K

XRAM

16K

XRAM

48K

(STBY)

(PEC)

XFLASH

320K

IFLASH

512K

32

16

16

16

16

16 16

16 16

16 16

16

PEC

Interrupt Controller

Por t 3 Por t 7 Por t 8

16

Watchdog

IRAM

2K

16

XRTC

Oscillator

PLL

5V-1.8V

Vol ta ge

Regulator

Por t 2

16

16

8

81615 8 8

16

16

32 kHz

Oscillator

XPWM

16

16

Figure 1. ST10F276x functional block diagram

DocID13284 Rev 2 23/564

Architectural overview UM0404

CPU

SP

STKOV

STKUN

Execution Unit

Instruction Pointer

4-Stage
Pipeline

PSW

SYSCON

MDH

MDL

Multiplication

Bit-Mask

Barrel-Shift

CP

16-bit

ALU

R15

R0

ADDRSEL 1

ADDRSEL 2

ADDRSEL 3

ADDRSEL 4

BUSCON 0

BUSCON 1

BUSCON 2

BUSCON 3

BUSCON 4

Code Segment Data Page

General
Purpose

Registers

2 Kbyte

Bank n

Bank i

Bank 0

16

16

512 Kbyte

IFlash

64 + 2 Kbyte

32

Division Hardware

Generator

PointerPointers

XRAM

IRAM

320 Kbyte

XFlash

16

Figure 2. CPU block diagram

1.1.1 High instruction bandwidth / fast execution

Most of the ST10F276’s instructions are executed in one instruction cycle. For example,

shift and rotate instructions are processed independent of the number of bits to be shifted.

Multiple-cycle instructions have been optimized: branches are carried out in 2 instruction

cycles, 16 × 16 bit multiplication in 5 instruction cycles and a 32/16-bit division in 10

instruction cycles. The jump cache reduces the execution time of repeatedly performed

jumps in a loop, from 2 instruction cycles to 1 instruction cycle.

The instruction cycle time has been reduced by instruction pipelining. This technique allows

the core CPU to process, in parallel, portions of multiple sequential instruction stages. The

following four stage pipeline provides the optimum balancing for the CPU core:

• Fetch: In this stage, an instruction is fetched from the internal Flash or RAM or from the

external memory, based on the current IP value.

• Decode: In this stage, the previously fetched instruction is decoded and the required

operands are fetched.

• Execute: In this stage, the specified operation is performed on the previously fetched

operands.

• Write back: In this stage, the result is written to the specified location.

If this technique is not used, each instruction would require four instruction cycles. Pipelining

offers increased performance.

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UM0404 Architectural overview

1.1.2 High function 8-bit and 16-bit ALU

All standard arithmetic and logical operations are performed in a 16-bit ALU. In addition, the

condition flags for byte operations are provided from the sixth and seventh bit of the ALU

result.

Multiple precision arithmetic is provided through a 'CARRY-IN' signal to the ALU, from

previously calculated portions of the desired operation. Most of the internal execution blocks

have been optimized to perform operations on either 8-bit or 16-bit data.

Once the pipeline has been filled, one instruction is completed per instruction cycle, except

for multiply and divide. An advanced Booth algorithm has been incorporated to allow 4 bits

to be multiplied and 2 bits to be divided per instruction cycle. Thus, these operations use

two coupled 16-bit registers, MDL and MDH, and require four and nine instruction cycles,

respectively, to perform a 16-bit by 16-bit (or 32-bit by 16-bit) calculation plus one instruction

cycle to setup and adjust the operands and the result.

Even these longer multiply and divide instructions can be interrupted during their execution

to allow very fast interrupt response.

Instructions have also been provided to allow byte packing in memory while providing sign

extension of byte for word wide arithmetic operations.

The internal bus structure also allows transfers of byte or words to or from peripherals

based on the peripheral requirements.

A set of consistent flags is automatically updated in the PSW register after each arithmetic,

logical, shift, or movement operation.

These flags allow branching on specific conditions. Support for both signed and unsigned

arithmetic is provided through user-specifiable branch tests. These flags are also preserved

automatically by the CPU upon entry into an interrupt or trap routine.

All targets for branch calculations are also computed in the central ALU.

A 16-bit barrel shifter provides multiple bit shifts in a single instruction cycle. Rotate and

arithmetic shifts are also supported.

1.1.3 Extended bit processing and peripheral control

A large number of instructions are dedicated to bit processing. These instructions provide

efficient control and testing of peripherals and they enhance data manipulation. Unlike other

microcontrollers, these instructions provide direct access to two operands in the bit-

addressable space, without the need to move them into temporary flags.

The same logical instructions available for words and byte, are also supported for bit. This

allows the user to compare and modify a control bit for a peripheral, in one instruction.

Multiple bit shift instructions have been included to avoid long instruction streams of single

bit shift operations. These are also performed in a single instruction cycle. In addition, bit

field instructions have been provided to allow the modification of multiple bit from one

operand in a single instruction.

1.1.4 High performance branch, call and loop processing

Due to the high percentage of branching in controller applications, branch instructions have

been optimized to require one extra instruction cycle only when a branch is taken. This is

implemented by pre-calculating the target address while decoding the instruction.

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Architectural overview UM0404

To decrease loop execution overhead, three enhancements have been provided:

1. Single cycle branch execution is provided after the first iteration of a loop. Therefore,
only one instruction cycle is lost during the execution of the entire loop. In loops which
fall through upon completion, no instruction cycle is lost when exiting the loop. No
special instruction is required to perform loops, and loops are automatically detected
during execution of branch instructions.

2. Detection of the end of a table avoids the use of two compare instructions embedded in
loops. One simply places the lowest negative number at the end of the specific table,
and specifies branching if neither this value nor the compared value have been found.
Otherwise the loop is terminated if either condition has been met. The terminating
condition can then be tested.

3. The third loop enhancement provides a more flexible solution than the Decrement and
Skip on Zero instruction which is found in other microcontrollers. Through the use of
Compare and Increment or Decrement instructions, the user can make comparisons to
any value. This allows loop counters to cover any range. This is particularly powerful in
table searching.

Saving of system state is automatically performed on the internal system stack avoiding the
use of instructions to preserve state upon entry and exit of interrupt or trap routines. Call
instructions push the value of the IP on the system stack, and require the same execution
time as branch instructions.

Instructions have also been provided to support indirect branch and call instructions. This
supports implementation of multiple CASE statement branching in assembler macros and
high level languages.

1.1.5 Consistent and optimized instruction formats

To obtain optimum performance in a pipeline design, an instruction set has been designed
using concepts of Reduced Instruction Set Computing (RISC).

These concepts primarily allow fast decoding of the instructions and operands, while
reducing pipeline holds. These concepts, however, do not preclude the use of complex
instructions, which are required by microcontroller users.

The following goals were used to design the instruction set:

• To provide powerful instructions to perform operations which currently require
sequences of instructions and which are frequently used. To avoid transfer into and out
of temporary registers such as accumulators and carry bit. To perform tasks in parallel
such as saving state upon entry into interrupt routines or subroutines.

• To avoid complex encoding schemes by placing operands in consistent fields for each
instruction. Also to avoid complex addressing modes which are not frequently used.
This decreases the instruction decode time while also simplifying the development of
compilers and assemblers.

• To provide most frequently used instructions with one-word instruction formats. All
other instructions are placed into two-word formats. This allows all instructions to be
placed on word boundaries, which alleviates the need for complex alignment hardware.
It also has the benefit of increasing the range for relative branching instructions.

The high performance offered by the hardware implementation of the CPU can efficiently be
used by a programmer via the highly functional ST10F276 instruction set. Possible operand
types are bits, bytes and words. Specific instruction support the conversion (extension) of
bytes to words. A variety of direct, indirect or immediate addressing modes are provided to

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UM0404 Architectural overview

specify the required operands.

1.1.6 Programmable multiple priority interrupt system

The following enhancements have been included to allow processing of a large number of
interrupt sources:

• Peripheral Event Controller (PEC): This processor is used to off-load many interrupt
requests from the CPU. It avoids the overhead of entering and exiting interrupt or trap
routines by performing single cycle interrupt-driven byte or word data transfers
between any two locations in segment 0 with an optional increment of either the PEC
source or the destination pointer. Just one cycle is 'stolen' from the current CPU activity
to perform a PEC service.

• Multiple Priority Interrupt Controller: This controller allows all interrupts to be placed at
any specified priority. Interrupts may also be grouped, which provides the user with the
ability to prevent similar priority tasks from interrupting each other. For each of the
possible interrupt sources there is a separate control register, which contains an
interrupt request flag, an interrupt enable flag and an interrupt priority bit-field. Once
having been accepted by the CPU, an interrupt service can only be interrupted by a
higher prioritized service request. For standard interrupt processing, each of the
possible interrupt sources has a dedicated vector location.

• Multiple Register Banks: This feature allows the user to specify up to sixteen general
purpose registers located anywhere in the IRAM. A single “one instruction cycle”
instruction is used to switch register banks from one task to another.

• Interruptible Multiple Cycle Instructions: Reduced interrupt latency is provided by
allowing multiple-cycle instructions (multiply, divide) to be interruptible.

With an interrupt response time within a range from just 5 to 12 CPU clock periods, the
ST10F276 is capable of fast reaction to non-deterministic events.

The ST10F276 also provides an excellent mechanism to identify and to process exceptions
or error conditions that arise during run-time, so called ‘Hardware Traps’. Hardware traps
cause an immediate non-maskable system reaction which is similar to a standard interrupt
service (branching to a dedicated vector table location).

The occurrence of a hardware trap is additionally signified by an individual bit in the trap flag
register (TFR).

Except for another higher prioritized trap service being in progress, a hardware trap will
interrupt any current program execution. In turn, hardware trap services can normally not be
interrupted by standard or PEC interrupts.

Software interrupts are supported by means of the 'TRAP' instruction in combination with an
individual trap (interrupt) number.

1.2 On-chip system resources

The ST10F276 controllers provide a number of powerful system resources designed around
the CPU. The combination of CPU and these resources results in the high performance of
the members of this controller family.

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Architectural overview UM0404

1.2.1 Peripheral event control and interrupt control

The Peripheral Event Controller (PEC) makes it possible to respond to an interrupt request
with a single data transfer (word or byte) which only consumes one instruction cycle and
does not require a save and restore of the machine status.

Each interrupt source is prioritized in every instruction cycle in the interrupt control block. If a
PEC service is selected, a PEC transfer is started. If CPU interrupt service is requested, the
current CPU priority level stored in the PSW register is tested to determine whether a higher
priority interrupt is currently being serviced.

When an interrupt is acknowledged, the current state of the machine is saved on the internal
system stack and the CPU branches to the system specific vector for the peripheral.

The PEC contains a set of SFRs which store the count value and control bit for eight data
transfer channels. In addition, the PEC uses a dedicated area of RAM which contains the
source and destination addresses. The PEC is controlled similarly to any other peripheral
through SFRs containing the desired configuration of each channel.

An individual PEC transfer counter is implicitly decremented for each PEC service except
forming in the continuous transfer mode. When this counter reaches zero, a standard
interrupt is performed to the vector location related to the corresponding source. PEC
services are very well suited, for example, to move register contents to/from a memory
table. The ST10F276 has eight PEC channels each of which offers such fast interrupt-driven
data transfer capabilities.

1.2.2 Memory areas

The memory space of the ST10F276 is organized as a unified memory which means that
code memory, data memory, registers and I/O ports are organized within the same linear
address space which covers up to 16 Mbytes. The entire memory space can be accessed
byte wise or word wise. Particular portions of the on-chip memory have additionally been
made directly bit addressable.

A 2 Kbyte 16-bit wide IRAM provides fast access to General Purpose Registers (GPRs),

user data (variables) and system stack. The IRAM may also be used for code. A unique
decoding scheme provides flexible user register banks in the internal memory while
optimizing the remaining RAM for user data.

The CPU contains an actual register context, consisting of up to 16 word wide and/or byte
wide GPRs which are physically located within the IRAM area.

A Context Pointer (CP) register determines the base address of the active register bank to
be accessed by the CPU at a time. The number of register banks is only restricted by the
available IRAM space. For easy parameter passing, one register bank may overlap others.

A system stack of up to 1024 words is provided as a storage for temporary data. The system
stack is also located within the IRAM area, and it is accessed by the CPU via the stack
pointer (SP) register. Two separate SFRs, STKOV and STKUN, are implicitly compared
against the stack pointer value upon each stack access for the detection of a stack overflow
or underflow.

Hardware detection of the selected memory space is placed at the internal memory
decoders and allows the user to specify any address directly or indirectly and obtain the
desired data without using temporary registers or special instructions.

A 66 Kbyte 16-bit wide on-chip XRAM provides fast access to user data (variables), user

stacks and code. The on-chip XRAM is an X-Peripheral and appears to the software as an

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UM0404 Architectural overview

external RAM. Therefore it cannot store register banks and is not bit addressable. The
XRAM allows 16-bit accesses with maximum speed. A portion of the on-chip XRAM (16
Kbytes) represents the Stand-by RAM, which can be maintained biased through EA
pin when main supply V

is turned off.

DD

/V

STBY

A 512 Kbyte on-chip internal Flash (IFlash) provides for both code and constant data

storage. This memory area is connected to the CPU via a 32-bit wide bus. Thus, an entire
double-word instruction can be fetched in just one instruction cycle. Program execution from
the on-chip IFlash is the fastest of all possible alternatives.

A 320 Kbyte on-chip extended Flash (XFlash) is also provided for both code and constant

data storage. It is seen as an X-Peripheral and appears to the software as an external
Flash: it allows 16-bit accesses with maximum speed up to 40 MHz. A wait state should be
added when a higher CPU frequency is used.

For Special Function Registers 1024 bytes of the address space are reserved. The

standard Special Function Register area (SFR) uses 512 bytes, while the Extended Special
Function Register area (ESFR) uses the other 512 bytes. (E)SFRs are word wide registers
which are used for controlling and monitoring functions of the different on-chip units. Unused
ESFR addresses are reserved for future members of the ST10F276 family.

1.2.3 External bus interface

In addition to the internal memory, the application can address up to 16 Mbytes of external
memory via the external bus interface.

The integrated External Bus Controller (EBC) allows flexible access to external memory
and/or peripheral resources. For up to five address areas the bus mode (multiplexed / de­multiplexed), the data bus width (8-bit / 16-bit) and even the length of a bus cycle (wait­states, signal delays) can be selected independently.

This allows access to a variety of memory and peripheral components, directly and with
maximum efficiency. If the device does not run in Single Chip Mode, where no external
memory is required, the EBC can control external accesses in one of the following four
different external access modes:

• 16-/18-/20-/24-bit Addresses, and 16-bit data, de-multiplexed.

• 16-/18-/20-/24-bit Addresses, and 8-bit data, de-multiplexed.

• 16-/18-/20-/24-bit Addresses, and 16-bit data, multiplexed.

• 16-/18-/20-/24-bit Addresses, and 8-bit data, multiplexed.

The de-multiplexed bus modes use PORT1 for addresses and PORT0 for data input/output.
The multiplexed bus modes use PORT0 for both addresses and data input/output.

Important timing characteristics of the external bus interface (wait-states, ALE length and
Read/Write Delay) have been made programmable to support a wide range of different
memory peripheral types. Access to very slow memories or peripherals is supported via a
particular 'Ready' function.

To address more than 64 Kbytes of external memory, Port4 is used to generate the address
lines A16...A23. Otherwise Port4 can be used as standard I/O.

The on-chip XBUS is an internal representation of the external bus and allows to access

integrated application-specific peripherals/modules in the same way as external
components. It provides a defined interface for these customized peripherals.

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Architectural overview UM0404

MUX

Oscillator

Circuit

Reset

PWRDN

XBUS interrupt

f

PLL

f

XTAL

f

CPU

XTAL2

XTAL1

Oscillator

Watchdog

Prescaler

(÷ 2)

MUX

P0H.7

MUX

P0H.6 P0H.5

PLL Circuit

f

PLL

= F x f

IN

reset sleep

Unlock

Factor

The on-chip XRAM and XFlash, the on-chip CAN-Modules, the XASC, the XSSC, the

2

XPWM, the I

C interface, the RTC are all examples for these X-Peripherals.

1.3 Clock generator

The on-chip clock generator provides the ST10F276 with its basic clock signal that controls
the activities of the controller hardware. Its oscillator amplifier can run with an external
crystal and appropriate oscillator circuitry (see Section 7: Dedicated pins on page 179), or
can be driven by an external clock source.

Direct Drive mode allows to feed the device with an external clock signal to provide directly
the clock to the CPU, up to maximum internally allowed speed. In this mode, the on-chip
oscillator amplifier is bypassed, so there is no limit imposed by the bandwidth of the
amplifier circuit itself.

On the contrary, for all the other configurations, the on-chip oscillator amplifier is not
bypassed, so the external clock can be provided by a crystal or resonator only, according to
the limited frequency ranges (refer to datasheet for more details).

The resulting internal clock signal is also referred to as “CPU clock”. Two separated clock
signals are generated for the CPU itself and the peripheral part of the chip.

While the CPU clock is stopped during idle mode, the peripheral clock keeps running. Both
clocks are switched off when the Power Down mode is entered.

The on-chip PLL circuit allows operation of the ST10F276 with a low frequency external
clock while still providing maximum performance.

The PLL multiplies the external clock frequency by a selectable factor F (0.5, 1, 3, 4, 5, 8,
10, 16) and generates a CPU clock signal with 50% duty cycle.

The PLL also provides fail safe mechanisms which allows the detection of frequency
deviations and the execution of emergency actions in case of an external clock failure even

when PLL is bypassed (see Section 1.3.4: Oscillator watchdog (OWD) on page 32).

Figure 3. Clock block diagram

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UM0404 Architectural overview

1.3.1 PLL operation

The PLL is enabled except when P0H.[7..5] = ‘011’ or ‘001’ during reset (Direct Drive and
Prescaler modes). At Power-On, the PLL provides a stable clock signal in less than 1ms
after V
PLL will run on its basic frequency of 750 kHz to 3 MHz). Refer to datasheet for more details
about PLL characteristics.

The PLL starts synchronizing with the external clock signal as soon as it is available. Within
1ms after stable oscillations of the external clock within the specified frequency range, the
PLL will be synchronous with this clock at a frequency of F x f
external clock.

Note: The ST10F276 is required to operate on the desired CPU clock directly after reset: make

sure that RSTIN
circuit immediately after reset will disconnect crystal reference clock path from the PLL
input, so the CPU clock will be provided by the PLL free running frequency.

The PLL constantly synchronizes to the external clock signal. Due to the fact that the
external frequency is 1/F’th of the PLL output frequency, the output frequency may be
slightly higher or lower than the desired frequency.

This jitter is irrelevant for longer time periods. For short periods (few CPU clock cycles), it
remains below the specified value (refer to datasheet for details).

has reached 5V±10%, even if there is no external clock signal (in this case, the

DD

, and the PLL locks to the

XTAL

remains active until the PLL has locked, on the contrary unlock detection

When the PLL is detected no longer locked (no longer stable), it generates an interrupt
request (on the PLL Unlock interrupt node).

This occurs when the input clock is unstable and especially when the input clock fails
completely (for example due to a broken crystal). In this case, the synchronization
mechanism will reduce the PLL output frequency down to the PLL’s basic frequency
(750 kHz to 3 MHz). The basic frequency is still generated and allows the CPU to execute
emergency actions in case of an external clock loss.

1.3.2 Prescaler operation

When pins P0H.[7..5] = ‘001’ during reset, the CPU clock is derived from the internal
oscillator (input clock signal) by a 2:1 prescaler. Note that it is not possible to force a clock
signal through an external clock generator unless Direct Drive is selected.

The frequency of f

is half the frequency of f

CPU

The PLL is still running on its basic frequency of 750 kHz to 3 MHz, and delivers the clock
signal for the Oscillator Watchdog, except if bit OWDDIS is set: in this case the PLL is
switched off.

1.3.3 Direct drive

When pins P0H.[7..5] = ‘011’ during reset, the CPU clock is directly driven from the internal
oscillator with the input clock signal (this means f
frequency depends on the clock signal’s duty cycle, because the minimum values for the
clock phases (TCLs) must be respected.

XTAL

CPU

.

= f

). The maximum input clock

XTAL

The PLL runs on its basic frequency of 750 kHz to 3 MHz, and delivers the clock signal for
the Oscillator Watchdog, except if bit OWDDIS is set: in this case the PLL is switched off.

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Architectural overview UM0404

1.3.4 Oscillator watchdog (OWD)

In order to provide a fail safe mechanism for the instance of a loss of the external clock, an
oscillator watchdog is implemented when the selected clock option is direct drive or direct
drive with prescaler.

The oscillator watchdog operates as follows:

• The Oscillator WatchDog (OWD) is enabled by default after reset. To disable the OWD,
set bit OWDDIS of the SYSCON register.

• When the OWD is enabled, the PLL runs on its free-running frequency, and increments
the Oscillator Watchdog counter.

• On each transition of XTAL1 pin, the Oscillator Watchdog counter is cleared.

If an external clock failure occurs, then the Oscillator Watchdog counter overflows (after 16
PLL clock cycles). The CPU clock signal will be switched to the PLL clock signal (in this
case, the PLL will run on its basic frequency of 750 kHz to 3 MHz), and the Oscillator
Watchdog Interrupt Request is flagged.

The CPU clock will not switch back to the external clock even if a valid external clock is
applied on XTAL1 pin. Only a hardware reset can switch the CPU clock source back to
external clock input.

When the OWD is disabled, the CPU clock is always fed from the oscillator input and the
PLL is switched off to decrease power supply current.

1.4 On-chip peripheral blocks

The ST10 family of devices separates peripherals from the core. This allows peripherals to
be added or removed without modifications to the core. Each functional block processes
data independently and communicates information over common buses. Peripherals are
controlled by data written to the respective Special Function Registers (SFRs). These SFRs
are located either within the standard SFR area (00’FE00h...00’FFFFh), or within the
extended ESFR area (00’F000h...00’F1FFh).

The built in peripherals are used for interfacing the CPU to the external world, or to provide
on-chip functions. The ST10F276 generic peripherals are:

• Nine I/O ports with a total of 111 I/O lines,

• Two Serial Interfaces (ASC0 and SSC),

• Two General Purpose Timer Blocks (GPT1 and GPT2),

• A Watchdog Timer,

• Two 16-channel Capture / Compare units (CAPCOM1 and CAPCOM2),

• A 4-channel Pulse Width Modulation unit (PWM),

• A 10-bit Analog / Digital Converter.

Each peripheral also contains a set of Special Function Registers (SFRs), which control the
functionality of the peripheral and temporarily store intermediate data results. Each
peripheral has an associated set of status flags. Individually selected clock signals are
generated for each peripheral from binary multiples of the CPU clock.

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UM0404 Architectural overview

In order to enhance the performance of the device, a set of additional on-chip X-Peripherals
are available on ST10F276 and controlled through dedicated set of registers:

• Two CAN interfaces,

• Two additional Serial Interfaces (XASC and XSSC),

2

• A I

• An additional 4-channel Pulse Width Modulation unit (XPWM),

• A Real Time Clock module.

C Serial Interface,

1.4.1 Peripheral interfaces

The on-chip peripherals generally have two different types of interfaces: an interface to the
CPU and an interface to external hardware. Communication between CPU and peripherals
is performed through Special Function Registers (SFRs) and interrupts. The SFRs serve as
control/status and data registers for the peripherals. Interrupt requests are generated by the
peripherals based on specific events which occur during their operation such as end of task,
new event, or errors.

Specific pins of the parallel ports are used for interfacing with external hardware when an
input or output function has been selected for a peripheral. During this time, the port pins are
controlled by the peripheral (when used as outputs) or by the external hardware which
controls the peripheral (when used as inputs). This is called the ‘alternate (input or output)
function’ of a port pin, in contrast to its function as a general purpose I/O pin.

Similarly, the on-chip X-Peripherals communicate with the CPU through a dedicated set of
registers and dedicated structure of interrupt management system.

1.4.2 Peripheral timing

Internal operation of CPU and peripherals is based on the CPU clock (f
oscillator derives the CPU clock from the crystal or from the external clock signal.

The clock signal which is gated to the peripherals is independent from the clock signal which
feeds the CPU. During Idle mode the CPU’s clock is stopped while the peripherals continue
their operation.

When an SFR is written to by software in the same state where it is also to be modified by
the peripheral, the software write operation has priority. Further details on peripheral timing
are included in the specific sections about each peripheral.

1.4.3 Programming hints

Access to SFRs: All SFRs reside in data page 3 of the memory space. The following

addressing mechanisms are used to access the SFRs:

• Indirect or direct addressing with 16-bit (mem) addresses it must be guaranteed that

the used data page pointer (DPP0...DPP3) selects data in memory space page 3.

• accesses via the Peripheral Event Controller (PEC) use the SRCPx and DSTPx

pointers instead of the data page pointers.

• short 8-bit (reg) addresses to the standard SFR area do not use the data page

pointers but directly access the registers within this 512 byte area.

• short 8-bit (reg) addresses to the extended ESFR area require switching to the 512

byte extended SFR area. This is done via the EXTension instructions EXTR, EXTP(R),
EXTS(R).

). The on-chip

CPU

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Architectural overview UM0404

Byte write operations to word wide SFRs via indirect or direct 16-bit (mem) addressing or

byte transfers via the PEC, force zeros in the non-addressed byte. Byte write operations via
short 8-bit (reg) addressing can only access the low byte of an SFR and force zeros in the
high byte. It is therefore recommended, to use the bit-field instructions (BFLDL and BFLDH)
to write to any number of bit in either byte of an SFR without disturbing the non-addressed
byte and the unselected bit.

Reserved bit: some of the bits which are contained in the ST10F276's SFRs are marked as

'Reserved'. User software must write '0's to reserved bits.

These bits are currently not implemented and may be used in future products to invoke new
functions. In this case, the active state for these functions will be '1', and the inactive state
will be '0'. Therefore writing only ‘0’s to reserved locations provides portability of the current
software to future devices. Read accesses to reserved bits return ‘0’s.

1.4.4 Parallel ports

The ST10F276 provides up to 111 I/O lines which are organized into eight input/output ports
and one input port. All port lines are bit-addressable, and all input/output lines are
individually (bit wise) programmable as inputs or outputs via direction registers. The I/O
ports are true bidirectional ports which are switched to high impedance state when
configured as inputs.

The output drivers of three I/O ports can be configured (pin by pin) for push-pull operation or
open-drain operation via control registers. During the internal reset, all port pins are
configured as inputs.

All pins of I/O ports also support an alternate programmable function:

• PORT0 and PORT1 may be used as data and address lines respectively when
accessing external memory. Four CAPCOM2 input-only lines and additional ADC
channels are also mapped on this port.

• Port2, accepts the fast external interrupt inputs and provides inputs/outputs for
CAPCOM1 unit.

• Port3 includes the alternate functions of timers, serial interfaces, the optional bus
control signal BHE

• Port4 outputs the additional segment address bit A16 to A23 in systems where
segmentation is enabled to access more than 64 Kbytes of memory. CAN modules and

2

C serial interface are alternate function on this port also.

I

• Port5 is used as analog input channels of the A/D converter or as timer control signals.

• Port6 provides optional bus arbitration signals (BREQ

signals and XSSC signals.

• Port7 provides the output signals from the PWM unit and inputs/outputs for the
CAPCOM2 unit.

• Port8 provides inputs/outputs for the CAPCOM2 unit, for the XPWM and for the XASC.

All port lines that are not used for alternate functions may be used as general purpose I/O
lines.

1.4.5 Serial channels

and the system clock output (CLKOUT).

, HLDA, HOLD), chip select

Serial communication with other microcontrollers, processors, terminals or external
peripheral components is provided by four serial interfaces with different functionality: two

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UM0404 Architectural overview

Asynchronous/Synchronous Serial Channels (ASC0 and XASC) and two High-Speed
Synchronous Serial Channels (SSC and XSSC).

They support full-duplex asynchronous communication and half-duplex synchronous
communication. The SSC may be configured so it interfaces with serially linked peripheral
components. Two dedicated Baud rate generators allow to set up all standard Baud rates
without oscillator tuning. For transmission, reception and error handling three separate
interrupt vectors are provided on channel SSC, four vectors are provided on channel ASC0.

In asynchronous mode, 8- or 9-bit data frames are transmitted or received, preceded by a
start bit and terminated by one or two stop bits. For multiprocessor communication, a
mechanism to distinguish address from data byte has been included (8-bit data plus wake
up bit mode).

In synchronous mode, the ASC0 transmits or receives byte (8-bit) synchronously to a shift
clock which is generated by the ASC0. The SSC transmits or receives characters of 2...16­bit length synchronously to a shift clock which can be generated by the SSC (master mode)
or by an external master (slave mode). The SSC can start shifting with the LSB or with the
MSB, while the ASC0 always shifts the LSB first. A loop back option is available for testing
purposes.

A number of optional hardware error detection capabilities has been included to increase
the reliability of data transfers. A parity bit can automatically be generated on transmission
or be checked on reception. Framing error detection allows to recognize data frames with
missing stop bit. An overrun error will be generated, if the last character received has not
been read out of the receive buffer register at the time the reception of a new character is
complete.

The XASC is another USART which is functionally identical with the ASC0. The XASC is an
X-Peripheral (no bit handling) and supports three interrupt vectors. The port line and
interrupt handling is slightly different from that of the ASC0.

Similarly, the XSSC is a Synchronous Serial link functionally identical with the SSC. The
XSSC is an X-Peripheral (no bit handling) and supports three interrupt sources. The port
line and interrupt handling is slightly different from that of the SSC.

1.4.6 General purpose timer (GPT) unit

The GPT unit is a flexible multifunctional timer/counter structure which may be used for time
related tasks, such as event timing and counting, pulse width and duty cycle measurements,
pulse generation, pulse multiplication or incremental interface.

The five 16-bit timers are organized into two separate modules, GPT1 and GPT2. Each
timer in each module may operate independently in a number of different modes, or may be
concatenated with another timer of the same module.

Each timer can be configured individually for one of three basic modes of operation, which
are Timer, Gated Timer, and Counter Mode. In Timer Mode the input clock for a timer is
derived from the internal CPU clock divided by a programmable prescaler, while Counter
Mode allows a timer to be clocked in reference to external events (via TxIN). Pulse width or
duty cycle measurement is supported in Gated Timer Mode where the operation of a timer is
controlled by the ‘gate’ level on its external input pin TxIN.

The count direction (up/down) for each timer is programmable by software or may
additionally be altered dynamically by an external signal (TxEUD) to facilitate for example
position tracking.

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Architectural overview UM0404

The core timers T3 and T6 have output toggle latches (TxOTL) which change their state on
each timer overflow / underflow. The state of these latches may be output on port pins
(TxOUT) or may be used internally to concatenate the core timers with the respective
auxiliary timers resulting in 32/33-bit timers/counters for measuring long time periods with
high resolution.

Various reload or capture functions can be selected to reload timers or capture a timer’s
contents triggered by an external signal or a selectable transition of toggle latch TxOTL.

1.4.7 Watchdog timer

The Watchdog Timer is a fail-safe mechanism. It limits the maximum malfunction time of the
controller.

The Watchdog Timer is always enabled after a reset of the chip, and can only be disabled in
the time interval until the EINIT (end of initialization) instruction has been executed. In this
way the chip’s start-up procedure is always monitored. The software must be designed to
service the Watchdog Timer before it overflows. If, due to hardware or software related
failures, the software fails to do so, the Watchdog Timer overflows and generates an internal
hardware reset and pulls the RSTOUT
components to be reset.

The Watchdog Timer is a 16-bit timer, clocked with the system clock divided either by 2 or by

128. The high byte of the watchdog Timer register can be set to a pre-specified reload value

(stored in WDTREL) in order to allow further variation of the monitored time interval. Each
time it is serviced by the application software, the high byte of the Watchdog Timer is
reloaded.

pin low in order to allow external hardware

1.4.8 Capture / compare (CAPCOM) units

The two CAPCOM units support generation and control of timing sequences on up to 32
channels. The CAPCOM units are typically used to handle high speed I/O tasks such as
pulse and waveform generation, pulse width modulation (PWM), Digital to Analog (D/A)
conversion, software timing, or time recording relative to external events.

Four 16-bit timers (T0/T1, T7/T8) with reload registers, provide two independent time bases
for the capture/compare register array.

The input clock for the timers is programmable to several pre-scaled values of the internal
system clock, or may be derived from an overflow/underflow of timer T6 in module GPT2.

This provides a wide range of variation for the timer period and resolution and allows
precise adjustments to the application specific requirements. In addition, external count
inputs for CAPCOM timers T0 and T7 allow event scheduling for the capture/compare
registers relative to external events.

Both of the two capture/compare register arrays contain 16 dual purpose capture/compare
registers, each of which may be individually allocated to either CAPCOM timer T0 or T1 (T7
or T8, respectively), and programmed for capture or compare function.

Each register has one port pin associated with it which is an input pin for triggering the
capture function, or is an output pin (except for CC24...CC27) to indicate the occurrence of
a compare event.

When a capture/compare register has been selected for capture mode, the current contents
of the allocated timer will be latched (captured) into the capture/compare register in
response to an external event at the port pin which is associated with this register.

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UM0404 Architectural overview

In addition, a specific interrupt request for this capture/compare register is generated. Either
a positive, a negative, or both a positive and a negative external signal transition at the pin
can be selected as the triggering event.

The contents of all registers which have been selected for one of the five compare modes
are continuously compared with the contents of the allocated timers.

When a match occurs between the timer value and the value in a capture/compare register,
specific actions will be taken, based on the selected compare mode.

1.4.9 Pulse width modulation unit

The Pulse Width Modulation Module can generate up to four PWM output signals using
edge-aligned or centre-aligned PWM. In addition the PWM module can generate PWM burst
signals and single shot outputs.

In Burst Mode two channels can be combined with their output signals ANDed, where one
channel gates the output signal of the other channel. In Single Shot Mode, a single output
pulse is generated (retriggerable) under software control.

Each PWM channel is controlled by an up/down counter with associated reload and
compare registers. The polarity of the PWM output signals may be controlled via the
respective port output latch (combination via EXOR).

The XPWM is an additional 4-channel PWM unit, functionally identical with the standard
PWM. The XPWM is an X-Peripheral (no bit handling) and support 1 interrupt source. The
port line and interrupt handling is slightly different from that of the standard PWM unit.

1.4.10 A/D converter

A 10-bit A/D converter with 16 multiplexed input channels and a sample and hold circuit has
been integrated on-chip for analog signal measurement. An additional eight multiplexed
channels are also available on Port1 with a reduced accuracy.

It uses a successive approximation method. The sample time (for loading the capacitors)
and conversion time is programmable and can be modified for the external circuitry.

Overrun error detection/protection is provided for the conversion result register (ADDAT).
When the result of a previous conversion has not been read from the result register at the
time the next conversion is complete, either an interrupt request is generated, or the next
conversion is suspended, until the previous result has been read.

For applications which require less than 24 analog input channels, the remaining channel
inputs can be used as digital input/output port pins (note that Port5 is input only, while Port1
is input/output).

The A/D converter of the ST10F276 supports four different conversion modes:

• Standard Single Channel conversion mode: the analog level on a specified channel is
sampled once and converted to a digital result.

• Single Channel Continuous mode: the analog level on a specified channel is
repeatedly sampled and converted without software intervention.

• For the Auto Scan mode: the analog levels on a pre-specified number of channels are
sampled and converted in sequence.

• In the Auto Scan Continuous mode: the number of pre-specified channels is repeatedly
sampled and converted.

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Architectural overview UM0404

In addition, the conversion of a specific channel can be inserted (injected) into a running
sequence without disturbing this sequence. This is called Channel Injection Mode. The
Peripheral Event Controller (PEC) may be used to automatically store the conversion results
into a table in memory for later evaluation, without the overhead of interrupt routines for
each data transfer.

Also, in the Wait for ADDAT read mode, a conversion will not be started as long as the result
from the previous one has not been read.

1.4.11 CAN module

The integrated CAN Module handles the completely autonomous transmission and
reception of CAN frames in accordance with the CAN specification V2.0 part A and B
(active). The on-chip CAN Module can receive and transmit standard frames with 11-bit
identifiers as well as extended frames with 29-bit identifiers.

The module provides full CAN functionality on up to 32 message objects: each message
object has its own identifier mask. Message objects may be concatenated in a
Programmable FIFO mode.

All message objects can be updated independent from the other objects and are equipped
for the maximum message length of 8 bytes. The bit timing is derived from the X-Peripheral
clock (XCLK, typically equal to CPU clock, apart from idle mode) and is programmable up to
a data rate of 1M Baud. The CAN Module uses two pins to interface to a bus transceiver.

1.4.12 I2C serial interface

The integrated I2C Serial Interface handles the transmission and reception of frames over
the two-line I
can transmit and receive data using 7-bit or 10-bit addressing and it can operate in slave
mode, in master mode or in multi-master mode.

The I
transferred at speeds up to 400 Kbit/s. The I
supports three interrupt sources.

Note: Once I

drivers only, as required by the standard bus specification.

2

2

C bus in accordance with the I2C Bus specification. The on-chip I2C Module

C module uses two pins to interface with the external serial bus. Data can be

2

C module is enabled, the port pins associated with the peripheral feature open drain

1.5 Real time clock

The Real Time Clock is an independent timer, which clock is directly derived from the
oscillator clock (either the main on-chip oscillator or the 32 kHz on-chip oscillator), so that it
can be maintained running even in Power Down mode (if enabled to) or in Stand-by mode
(only if 32 kHz oscillator is used). Registers access is implemented onto the XBUS. This
module is designed for the following purposes:

• Generate the current time and date for the system.

• Provide cyclic time based interrupt on Port2 external interrupts every ‘RTC basic clock

tick’ and every n ‘RTC basic clock tick’ (n is programmable) if enabled.

• Long term measurements (thanks to a 58-bit timer).

• Exit the ST10F276 from Power Down mode (if PWDCFG of SYSCON set) after a

programmed delay.

2

C is an X-Peripheral (no bit handling) and

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UM0404 Architectural overview

1.6 Protected bits

The ST10F276x MCU provides up to 106 protected bits. These bits are modified by the on­chip hardware during special events such as Power-On reset, power failure, or application
hardware. These bits cannot be modified by some wrong software accesses.

Register Bit name Notes

T2IC, T3IC, T4IC T2IR, T3IR, T4IR GPT1 timer interrupt request flags

T5IC, T6IC T5IR, T6IR GPT2 timer interrupt request flags

CRIC CRIR GPT2 CAPREL interrupt request flag

T3CON, T6CON T3OTL, T6OTL GPTx timer output toggle latches

T0IC, T1IC T0IR, T1IR CAPCOM1 timer interrupt request flags

T7IC, T8IC T7IR, T8IR CAPCOM2 timer interrupt request flags

S0TIC, S0TBIC S0TIR, S0TBIR ASC0 transmit (buffer) interrupt request flags

S0RIC, S0EIC S0RIR, S0EIR ASC0 receive/error interrupt request flags

S0CON S0REN ASC0 receiver enable flag

Table 1. Protected bit

Note:

SSCTIC, SSCRIC SSCTIR, SSCRIR SSC transmit/receive interrupt request flags

SSCEIC SSCEIR SSC error interrupt request flag

SSCCON SSCBSY SSC busy flag

SSCCON SSCBE, SSCPE SSC error flags

SSCCON SSCRE, SSCTE SSC error flags

ADCIC, ADEIC ADCIR, ADEIR ADC end-of-conversion/overrun interrupt request flags

ADCON ADST, ADCRQ ADC start flag / injection request flag

CC31IC...CC16IC CC31IR...CC16IR CAPCOM2 interrupt request flags

CC15IC...CC0IC CC15IR...CC0IR CAPCOM1 interrupt request flags

PWMIC PWMIR PWM module interrupt request flag

TFR TFR.15,14,13 Class A trap flags

TFR TFR.7,3,2,1,0 Class B trap flags

P2 P2.15...P2.0 All bits of Port2

P7 P7.7...P7.0 All bits of Port7

P8 P8.7...P8.0 All bits of Port8

XPyIC (y=3...0) XPyIR (y=3...0) X-Peripheral y interrupt request flag

Σ

= 106 protected bit.

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Memory organization UM0404

2 Memory organization

The memory space of the ST10F276 is organized as a unified memory. Code memory, data
memory, registers and I/O ports are organized within the same linear address space.

All of the physically separated memory areas, including on-chip IFlash, IRAM, the internal
Special Function Register Areas (SFRs and ESFRs), the address areas for integrated
XBUS peripherals and external memory are mapped into one common address space.

The ST10F276 provides a total addressable memory space of 16 Mbytes. This address
space is arranged as 256 segments of 64 Kbytes each, and each segment is again
subdivided into four data pages of 16 Kbytes each (see Figure 4 on page 41).

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UM0404 Memory organization

* Blocks B0F0, B0F1, B0F2, B0F3 may be remapped from segment 0 to segment 1 by setting SYSCON-ROMS1 (before EINIT).

Absolut e Memory Addres s are hexad ecimal val ues, whil e Data Page Numb er are deci mal values .

FF FFFF

00 0000

16 MB

255

0

Code Data

Page

1023

0

Data
Page

1

3

5

7

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

07 FFFF

06 0000
05 FFFF

04 0000
03 FFFF

02 0000
01 FFFF

00 0000

B0F4

B0F5

B0F8

B1F1

00 C000

00 FFFF

XCAN1

ESFR

SFR

IRAM

Reserved

Ext. Memory

00 DFFF

00 E000

00 E7FF

00 E800

00 FDFF

00 FE00

00 F1FF

00 F200

00 F5FF

00 F600

8K

256

512

1K

2K

512

Data Page 3 (Segment 0) - 16Kbyte

256

XCAN2

9

20

21

22

23

0A 0000
09 FFFF

08 0000

B2F0

11

24

25

26

27

0C 0000
0B FFFF

13

28

29

30

31

0E 0000
0D FFFF

B3F1

15

32

33

34

35

0F FFFF

00 F000

CAN1

CAN2

00 EFFF

00 F000

00 EEFF

00 EF00

00 EDFF

00 EE00

00 EAFF

00 EB00

256

256

256

256

XSSC

00 E7FF

00 E800

XRAM1

2K

14

0F 0000
0E FFFF

12

0D 0000
0C FFFF

10

0B 0000
0A FFFF

8

6

4

05 0000
04 FFFF

07 0000
06 FFFF

09 0000
08 FFFF

2

03 0000
02 FFFF

0

0

B0F0

B0F1

B0F2

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

B0F6

B0F9

B1F0

B2F1

B0F7

01 0000
00 FFFF

XRAM2

64K

B3F0

Code

Segment

64

65

66

67

64

65

66

67

16

17

10 0000

10 FFFF

11 0000

11 FFFF

FLASH + XRAM - 1Mbyte

Flash Registers

+

FPEC RAM/ R OM

RTC

00 EFFF

B2F2

(IFLASH)

(XFLASH)

(XFLASH)

(XFLASH)

(XFLASH)

(XFLASH)

XSSC

XASC

XI

2

C

256
256

256

XRTC

XASC

I

2

C

256

256

00 E8FF

00 E900

00 E9FF

00 EA00

Stand-by RAM

256

00 ECFF

00 ED00

256

(IFLASH)

(IFLASH)

(IFLASH)

(IFLASH)

(IFLASH)

(IFLASH)

(IFLASH)

XPWM

256

XPWM

256

256

00 EBFF

00 EC00

XMiscellaneous

XMiscellaneous

X-Peripherals (2Kbyte)

Segment

B0F3

Ext. Memory

Ext. Memory

Ext. Memory

Ext. Memory

Figure 4. ST10F276 memory mapping (user mode: Flash Read operation)

2.1 Word, byte and bit storage

Bytes are stored at even or odd byte addresses. Words are stored in ascending memory
locations with the low byte at an even byte address being followed by the high byte at the
next odd byte address.

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Memory organization UM0404

...

... Bit ...

... Bit ...

Byte

Byte

Word (high byte)

Word (low byte)

15 14 8

76 0

xxxx6h

xxxx5h

xxxx4h

xxxx3h

xxxx2h

xxxx1h

xxxx0h

xxxxFh

...

Double words (code only) are stored in ascending memory locations as two subsequent
words. Single bit are always stored in the specified bit position at a word address.

Bit position 0 is the least significant bit of the byte at an even byte address, and bit position
15 is the most significant bit of the byte at the next odd byte address. Bit addressing is
supported for a part of the Special Function Registers, a part of the IRAM and for the
General Purpose Registers.

Figure 5. Storage of words, bytes and bits in a byte organized memory

Note: Byte units forming a single word or a double word must always be stored within the same

physical (internal, external, Flash, RAM) and organizational (page, segment) memory area.

2.2 On-chip Flash

The ST10F276 reserves an address area of 512+320 Kbytes for on-chip Flash memory.

In standard mode (the normal operating mode) the first portion (512 Kbytes) of the Flash
(IFlash) appears like an on-chip ROM with the same timing and functionality. The IFlash
module offers a fast access time, allowing zero wait-state access with CPU frequency up to
64 MHz. Instruction fetches and data operand reads are performed with all addressing
modes of the ST10F276 instruction set. The second portion (320 Kbytes) appears like an
on-chip X-Peripheral: it can be accessed like an external memory in 16-bit demultiplexed
bus-mode without read/write delay at zero wait-states with CPU frequency up to 40 MHz,
while one wait-state should be added for higher frequency rates.

In order to optimize the programming time of the internal Flash, up to four different Banks
divided in blocks of 8 Kbytes, 16 Kbytes, 32 Kbytes and 64 Kbytes can be used. Reading
from one Bank while programming another Bank is possible. For a complete memory
mapping summary, see details in Table 3 and Tabl e 4.

In the table below, the Segment 8 address range mapping is summarized, varying ROMEN
(related with EA
XPERCON (bits XRAM2EN and XFLASHEN) programming.

42/564 DocID13284 Rev 2

pin status under reset) and XPEN bits status in SYSCON register and

UM0404 Memory organization

Table 2. Segment 8 address range mapping

ROMEN XPEN XRAM2EN XFLASHEN Segment 8

0 0 x x External Memory

0100 External Memory

011x Reserved

01x1 Reserved

1 x x x IFlash (B1F1)

Note: The symbol ‘x’ in the table above stands for ‘do not care’.

Table 3. 512 Kbyte IFlash memory block organization

Block

Addresses

(ROMS1 = ‘0’)

Addresses

(ROMS1 = ‘1’)

Size (bytes)

B0F0 00’0000h - 00’1FFFh 01’0000h - 00’1FFFh 8K

B0F1 00’2000h - 00’3FFFh 01’2000h - 00’3FFFh 8K

B0F2 00’4000h - 00’5FFFh 01’4000h - 00’5FFFh 8K

B0F3 00’6000h - 00’7FFFh 01’6000h - 00’7FFFh 8K

B0F4 01’8000h - 01’FFFFh 01’8000h - 01’FFFFh 32K

B0F5 02’0000h - 02’FFFFh 02’0000h - 02’FFFFh 64K

B0F6 03’0000h - 03’FFFFh 03’0000h - 03’FFFFh 64K

B0F7 04’0000h - 04’FFFFh 04’0000h - 04’FFFFh 64K

B0F8 05’0000h - 05’FFFFh 05’0000h - 05’FFFFh 64K

B0F9 06’0000h - 06’FFFFh 06’0000h - 06’FFFFh 64K

B1F0 07’0000h - 07’FFFFh 07’0000h - 07’FFFFh 64K

B1F1 08’0000h - 08’FFFFh 08’0000h - 08’FFFFh 64K

Block

Table 4. 320 Kbyte XFlash memory block organization

Addresses

(ROMS1=’0’)

Addresses

(ROMS1=’1’)

Size (bytes)

B2F0 09’0000h - 09’FFFFh 09’0000h - 09’FFFFh 64K

B2F1 0A’0000h - 0A’FFFFh 0A’0000h - 0A’FFFFh 64K

B2F2 0B’0000h - 0B’FFFFh 0B’0000h - 0B’FFFFh 64K

B3F0 0C’0000h - 0C’FFFFh 0C’0000h - 0C’FFFFh 64K

B3F1 0D’0000h - 0D’FFFFh 0D’0000h - 0D’FFFFh 64K

CTRL Registers 0E’0000h - 0E’FFFFh 0E’0000h - 0E’FFFFh 64K

DocID13284 Rev 2 43/564

Memory organization UM0404

Code fetches are always made on even byte addresses. The last valid code location must
contain a branch instruction (unconditional), because sequential boundary crossing from
internal Flash to external memory is not supported and causes erroneous results.

Any word and byte data read accesses may use the indirect or long 16-bit addressing
modes. There is no short addressing mode for internal Flash operands. Any word data
access is made to an even byte address.

For PEC data transfers the internal Flash can be accessed independently of the contents of
the DPP registers via the PEC source and destination pointers.

The internal Flash is not provided for single bit storage, and therefore it is not bit
addressable.

The first 32 Kbytes of the internal Flash may be mapped into segment 0 or segment 1 under
software control. Section 27.10: Handling the internal Flash on page 556 describes the
mapping procedures and precautions.

2.3 IRAM and SFR area

The IRAM/SFR area is located within data page 3 and provides access to the 2 Kbyte IRAM
(organized as 1K x 16) and to two 512 byte blocks of Special Function Registers (SFRs).
The IRAM is used as:

• System stack (programmable size),

• General purpose register banks (GPRs),

• Source and destination pointers for the peripheral event controller (PEC),

• Variable and other data storage, or Code storage.

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UM0404 Memory organization

FF FFFF

00 0000

16 MB

255

0

Code Data

Page

1023

0

Data

Page

1

3

5

7

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

07 FFFF

06 0000
05 FFFF

04 0000
03 FFFF

02 0000
01 FFFF

00 0000

B0F4

B0F5

B0F8

B1F1

00 C000

00 FFFF

XCAN1

ESFR

SFR

IRAM

Reserved

Ext. Memory

00 DFFF

00 E000

00 E7FF

00 E800

00 FDFF

00 FE00

00 F1FF

00 F200

00 F5FF

00 F600

8K

256

512

1K

2K

512

Data Page 3 (Segment 0) - 16Kbyte

256

XCAN2

9

20

21

22

23

0A 0000
09 FFFF

08 0000

B2F0

11

24

25

26

27

0C 0000
0B FFFF

13

28

29

30

31

0E 0000
0D FFFF

B3F1

15

32

33

34

35

0F FFFF

00 F000

SFR

00 FFFF

01 0000

00 FDFF

00 FE00

512

512

00 EFFF

00 F000

XRAM1

2K

14

0F 0000
0E FFFF

12

0D 0000
0C FFFF

10

0B 0000
0A FFFF

8

6

4

05 0000
04 FFFF

07 0000
06 FFFF

09 0000
08 FFFF

2

03 0000
02 FFFF

0

0

B0F0

B0F1

B0F2

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

B0F6

B0F9

B1F0

B2F1

B0F7

01 0000
00 FFFF

XRAM2

64K

B3F0

Code

Segment

64

65

66

67

64

65

66

67

16

17

10 0000

10 FFFF

11 0000

11 FFFF

FLASH + XRAM - 1Mbyte

Flash Registers

+

FPEC RAM/ R OM

IRAM

00 EFFF

B2F2

(IFLASH)

(XFLASH)

(XFLASH)

(XFLASH)

(XFLASH)

(XFLASH)

XSSC

XASC

XI

2

C

256
256

256

XRTC

1K

00 F1FF

00 F200

00 F5FF

00 F600

Stand-by RAM

256

(IFLASH)

(IFLASH)

(IFLASH)

(IFLASH)

(IFLASH)

(IFLASH)

(IFLASH)

XPWM

256
256

2K

XMiscellaneous

RAM / SFR (4Kbyte)

Segment

B0F3

ESFR

Reserved

Bit-addressable M emory

Ext. Memory

Ext. Memory

Ext. Memory

Ext. Memory

Figure 6. On-chip RAM and SFR/ESFR areas

Note: 1 The upper 256 bytes of SFR area, ESFR area and IRAM are bit-addressable.

2 Read or write access in reserved locations may cause unexpected behavior.

Code accesses are always made on even byte addresses. The last valid code location must
contain a branch instruction (unconditional), because sequential boundary crossing from
IRAM to the SFR area is not supported and can causes erroneous results.

Any word and byte data in the IRAM can be accessed via indirect or long 16-bit addressing
modes, if the selected DPP register points to data page 3. Any word data access is made on
an even byte address. For PEC data transfers, the IRAM can be accessed independently of
the contents of the DPP registers via the PEC source and destination pointers.

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Memory organization UM0404

The upper 256 bytes of the IRAM (00’FD00h through 00’FDFFh) and the GPRs of the
current bank are provided for single bit storage, and therefore, they are bit addressable (see

Figure 1 on page 23).

2.3.1 System stack

The system stack may be defined within the IRAM. The size of the system stack is
controlled by bit-field STKSZ in the SYSCON register (see Table 5).

For all system stack operations the IRAM is accessed via the Stack Pointer (SP) register.
The stack grows downward from higher towards lower IRAM address locations.

Only word accesses are supported by the system stack. A stack overflow (STKOV) and a
stack underflow (STKUN) register are provided to control the lower and upper limits of the
selected stack area.

These two stack boundary registers can be used, not only for protection against data
destruction, but also allow to implement a circular stack with hardware supported system
stack flushing and filling (except for the 2 Kbyte stack option).

The technique of implementing this circular stack is described in Section 27.1: Stack

operations on page 547.

Table 5. Stack size

(STKSZ) Stack size (words) IRAM addresses (words)

0 0 0b 256 00’FBFEh...00’FA00h (Default after Reset)

0 0 1b 128 00’FBFEh...00’FB00h

0 1 0b 64 00’FBFEh...00’FB80h

0 1 1b 32 00’FBFEh...00’FBC0h

1 0 0b 512 00’FBFEh...00’F800h

1 0 1b --- Reserved. Do not use this combination.

1 1 0b --- Reserved. Do not use this combination.

1 1 1b 1024 00’FDFEh...00’F600h (Note: No circular stack)

2.3.2 General purpose registers

The general purpose registers (GPRs) use a block of 16 consecutive words within the
IRAM. The Context Pointer (CP) register determines the base address of the currently
active register bank. This register bank may consist of up to 16 word GPRs (R0, R1, ... ,
R15) and/or of up to 16 byte GPRs (RL0, RH0, ... , RL7, RH7) and 8 word registers R8-R15.
The 16 byte GPRs are mapped onto the first eight word GPRs (see Table 6).

In contrast to the system stack, a register bank grows from lower towards higher address
locations and occupies a maximum space of 32 bytes.

The GPRs are accessed via short 2-, 4- or 8-bit addressing modes using the context pointer
(CP) register as base address (independent of the current DPP register contents).
Additionally, each bit in the currently active register bank can be accessed individually.

The ST10F276 supports fast register bank (context) switching. Multiple register banks can
physically exist within the IRAM at the same time. Only the register bank selected by the

46/564 DocID13284 Rev 2

UM0404 Memory organization

Context Pointer register (CP) is active at a given time. Selecting a new active register bank
is simply done by updating the CP register.

A particular Switch Context (SCXT) instruction performs register bank switching and an
automatic saving of the previous context. The number of implemented register banks
(arbitrary sizes) is only limited by the size of the available IRAM.

Details on using, switching and overlapping register banks are described in Register
Banking Section 27.2: Register banking on page 551.

Table 6. Mapping of general purpose registers to RAM addresses

IRAM address Byte registers Word register

(CP) + 1Eh --- R15

(CP) + 1Ch --- R14

(CP) + 1Ah --- R13

(CP) + 18h --- R12

(CP) + 16h --- R11

(CP) + 14h --- R10

(CP) + 12h --- R9

(CP) + 10h --- R8

(CP) + 0Eh RH7, RL7 R7

(CP) + 0Ch RH6, RL6 R6

(CP) + 0Ah RH5, RL5 R5

(CP) + 08h RH4, RL4 R4

(CP) + 06h RH3, RL3 R3

(CP) + 04h RH2, RL2 R2

(CP) + 02h RH1, RL1 R1

(CP) + 00h RH0, RL0 R0

2.3.3 PEC source and destination pointers

The 16 word locations in the IRAM from 00’FCE0h to 00’FCFEh are provided as source and
destination address pointers for data transfers on the eight PEC channels. Each channel
uses a pair of pointers stored in two subsequent word locations with the source pointer
(SRCPx) on the lower and the destination pointer (DSTPx) on the higher word address (x =

7...0) (see Figure 7 on page 48).

Whenever a PEC data transfer is performed, the pair of source and destination pointers
selected by the specified PEC channel number is accessed independently of the current
DPP register contents. The locations referred to by these pointers are accessed
independently of the current DPP register contents. If a PEC channel is not used, the
corresponding pointer locates the area available and can be used for word or byte data
storage.

For more details about the use of the source and destination pointers for PEC data
transfers, see Section 27: System programming on page 545.

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Memory organization UM0404

00’FCFEh

00’FCFCh

00’FCE2h

00’FCE0h

DSTP7

SRCP7

DSTP0

SRCP0

00’F600h

00’FCDEh

00’FCE0h

00’FCFEh

00’FD00h

00’F5FEh

Internal
RAM

PEC
source &
destination
pointers

Figure 7. Location of the PEC pointers

2.3.4 Special function registers

The functions of the CPU, the bus interface, the I/O ports and the on-chip peripherals of the
ST10F276 are controlled via a number of so-called Special Function Registers (SFRs).

These SFRs are arranged within two areas, each of 512 byte size. The first register block, is
called the SFR area, and is located in the 512 byte above the IRAM (00’FFFFh...00’FE00h),
the second register block, the Extended SFR (ESFR) area, is located in the 512 byte below
the IRAM (00’F1FFh...00’F000h).

Special function registers can be addressed via indirect and long 16-bit addressing modes.
Using an 8-bit offset, together with an implicit base address, makes it possible to address

word SFRs and their respective low byte. This does not work for the respective high byte!

Note: Writing to any byte of an SFR causes the non-addressed complementary byte to be cleared!

The upper half of each register block is bit-addressable, so the respective control/status bit
can be directly modified or checked by using bit addressing. When accessing registers in
the ESFR area using 8-bit addresses or direct bit addressing, an Extend Register (EXTR)
instruction is required before, to switch the short addressing mechanism from the standard
SFR area to the Extended SFR area.

This is not required for 16-bit and indirect addresses. The GPRs R15...R0 are duplicated,
and they are accessible within both register blocks via short 2-, 4- or 8-bit addresses without
switching.

Example:

EXTR #3 ;Switch to ESFR area for the next 3 instructions

MOV

ODP2,
#data16

;this instruction uses 8-bit reg addressing

;(EXTR mandatory)

BSET DP1h.7

48/564 DocID13284 Rev 2

;this instructiion uses direct bit addressing

;(EXTR mandatory)

UM0404 Memory organization

;This instruction uses 16-bit address to access

MOV T8REL, R1

;----- ;------ ;The scope of the EXTR #3 instruction ends here!

MOV T8REL, R1

;ESFR T8REL. R1 is duplicated and also ;accessible via
the ESFR mode

;(EXTR is not required for this access)

;This instruction uses 16-bit address, and does

;not require switching

In order to minimize the use of the EXTR instructions, the ESFR area mostly holds registers
which are required for initialization and mode selection. Wherever possible, registers that
need to be accessed frequently are allocated in the standard SFR area.

Note: The tools are equipped to monitor accesses to the ESFR area and will automatically insert

EXTR instructions, or issue a warning in case of missing or excessive EXTR instructions.

2.4 The on-chip XRAM

The 66 Kbytes of on-chip extension RAM (single port XRAM) is provided as a storage for

data, user stack and code. It is partially located within data page 3 (XRAM1 - 2 Kbytes), and
partially in code segment 15 (XRAM2 - 64 Kbytes).

Both the XRAM modules are connected to the internal XBUS and are accessed like an
external memory in 16-bit de-multiplexed bus mode without wait-state or read/write delay
(31.25 ns access at 64 MHz CPU clock). Byte and word accesses are allowed.

As the XRAM is connected to the internal XBUS it is accessed like external memory,
however, no external bus cycles are executed for these accesses.

XRAM accesses are globally enabled or disabled via bit XPEN in the SYSCON register.
This bit is cleared after reset and may be set via software during the initialization to allow
accesses to the on-chip XRAM. When bit VISIBLE in the SYSCON register is set also,
accesses to the on-chip XRAM are made visible on the external Port pins. Code fetches are
always made on even byte addresses. Any word and byte data read accesses may use the
indirect or long 16-bit addressing modes. There is no short addressing mode for XRAM
operands. Sequential boundary crossing from XRAM to external memory is not supported
and causes erroneous results.

The XRAM1 address range is 00’E000h - 00’E7FFh if XPEN (bit 2 of SYSCON register),
and XRAM1EN (bit 2 of XPERCON register) are set. If XRAM1EN or XPEN is cleared, then
any access in the address range 00’E000h - 00’E7FFh will be directed to external memory
interface, using the BUSCONx register corresponding to address matching ADDRSELx
register.

The XRAM2 address range is 0F’0000h - 0F’FFFFh if XPEN (bit 2 of SYSCON register),
and XRAM2EN (bit 3 of XPERCON register) are set. If bit XPEN is cleared, then any access
in the address range 0F’0000h - 00’FFFFh will be directed to external memory interface,
using the BUSCONx register corresponding to address matching ADDRSELx register; the
same occurs when bit XPEN is set, but both bits XRAM2EN and XFLASHEN are cleared.

The lower 16 Kbyte portion of XRAM2 (Address range 0F’0000h-0F’3FFFh) represents the
Stand-by RAM, which can be maintained biased through EA

is turned off. As the XRAM appears like external memory, it cannot be used as system

V

DD

/V

pin when main supply

STBY

stack or as register banks. The XRAM is not provided for single bit storage and therefore is
not bit addressable.

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Memory organization UM0404

Any word and byte data read accesses may use the indirect or long 16-bit addressing
modes. There is no short addressing mode for XRAM operands. Any word data access is
made to an even byte address. For PEC data transfers XRAM1 can be accessed
independently of the contents of the DPP registers, via the PEC source and destination
pointers. XRAM2 is not PEC addressable, since not mapped in code segment 0.

The on-chip XRAM is accessed without any wait-states, using 16-bit de-multiplexed bus
cycles which takes one instruction cycle. Even if the XRAM is used as external memory, it
does not occupy BUSCONx / ADDRSELx registers, but it is selected via additional
dedicated XBCON / XADRS registers. In general, these registers are mask-programmed
and are not user accessible. The address area of 00’E000h to 00’E7FFh is reserved for
XRAM1 accesses, and the address area of 0F’0000h - 0F’FFFFh is reserved for XRAM2
accesses. In ST10F276 the register XADRS3 used for XRAM2 and XFLASH memory range
is user programmable: this allows to redefine the size and starting address of the memory
window, making possible to play with on-chip and external memory resources (refer to

Section 8.7: The XBUS interface on page 207 for details).

2.4.1 XRAM access via external masters

When bit XPER-SHARE in register SYSCON is set the on-chip XRAM of the ST10F276 can
be accessed by an external master during hold mode, via the ST10F276’s bus interface.
These external accesses must use the same configuration as the internally programmed.
No wait-states are required.

The configuration in register SYSCON cannot be changed after the execution of the EINIT
instruction.

External accesses to the other XBUS peripherals are not guaranteed in terms of AC
Timings. Note that setting XPER-SHARE Mode affects the system configuration: since the
bus control functions BREQ, HLDA and HOLD are mapped as alternate functions of
P6(7:5), the XSSC module is not accessible when arbitration is in use. For similar reasons,
in case segment lines A(23:20) on Port4 have to be used (SALSEL = 10), the CAN1, CAN2

2

C modules might not be accessible.

and I

2.5 External memory space

The ST10F276 is capable of using an address space of up to 16 Mbytes. Only parts of this
address space are occupied by internal memory areas. All addresses which are not used for
on-chip memory (Flash) or for registers, may refer to external memory locations. This
external memory is accessed via the ST10F276’s external bus interface.

Four memory bank sizes are supported:

• Non-segmented mode: 64 Kbytes with A15...A0 on PORT0 or PORT1

• 2-bit segmented mode: 256 Kbytes with A17...A16 on Port4 and A15...A0 on PORT0 or

PORT1

• 4-bit segmented mode: 1 Mbyte with A19...A16 on Port4 and A15...A0 on PORT0 or
PORT1

• 8-bit segmented mode: 16 Mbytes with A23...A16 on Port4 and A15...A0 on PORT0 or
PORT1

Each bank can be directly addressed via the address bus while the programmable chip
select signals that can be used to select various memory banks.

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UM0404 Memory organization

The ST10F276 also supports four different bus types:

• Multiplexed 16-bit Bus with address and data on PORT0 (Default after Reset)

• Multiplexed 8-bit Bus with address and data on PORT0 (P0L)

• De-multiplexed 16-bit Bus with address on PORT1 and data on PORT0

• De-multiplexed 8-bit Bus with address on PORT1 and data on PORT0 (P0L)

Memory model and bus mode are selected during reset by pin EA
further details about the external bus configuration and control see Section 8: The external

bus interface on page 181.

External word and byte data can only be accessed via indirect or long 16-bit addressing
modes, using one of the four DPP registers. There is no short addressing mode for external
operands. Any word data access is made to an even byte address.

For PEC data transfers the external memory in segment 0 can be accessed independent of
the contents of the DPP registers via the PEC source and destination pointers.

The external memory is not provided for single bit storage therefore it is not bit addressable.

2.6 Crossing memory boundaries

The address space of the ST10F276 is implicitly divided into equally sized blocks of different
granularity and into logical memory areas. Crossing the boundaries between these blocks
(code or data) or areas requires special attention to ensure that the controller executes the
desired operations.

Memory Areas are partitions of the address space that represent different kinds of memory

(if provided at all). These memory areas are the IRAM/SFR area, the internal Flash Memory,
the on-chip X-Peripherals (if integrated) and the external memory.

Accessing subsequent data locations that belong to different memory areas is no problem.
However, when executing code, the different memory areas must be switched explicitly via
branch instructions. Sequential boundary crossing is not supported and leads to erroneous
results.

and PORT0 pins. For

Note: Changing from the external memory area to the IRAM/SFR area takes place within

segment 0.

Segments are contiguous blocks of 64 Kbytes each. They are referenced via the code

segment pointer CSP for code fetches and via an explicit segment number for data
accesses overriding the standard DPP scheme.

During code fetching segments are not changed automatically, but rather must be switched
explicitly. The instructions JMPS, CALLS and RETS will do this.

In larger sequential programs make sure that the highest used code location of a segment
contains an unconditional branch instruction to the respective following segment, to prevent
the prefetcher from trying to leave the current segment.

Data Pages are contiguous blocks of 16 Kbytes each. They are referenced via the data

page pointers DPP3...0 and via an explicit data page number for data accesses overriding
the standard DPP scheme. Each DPP register can select one of the possible 1024 data
pages. The DPP register that is used for the current access is selected via the two upper
bits of the 16-bit data address. Subsequent 16-bit data addresses that cross the 16 Kbytes
data page boundaries therefore will use different data page pointers, while the physical
locations need not be subsequent within memory.

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The central processing unit (CPU) UM0404

3 The central processing unit (CPU)

The CPU is used to fetch and decode instructions, to supply operands for the arithmetic and
logic unit (ALU), to perform operations on these operands in the ALU, and to store the
previously calculated results.

A four stage pipeline is implemented, where up to four instructions can be processed in
parallel. Most instructions of the ST10F276 are executed in one instruction cycle due to this
parallelism.

This section describes how the pipeline works for sequential and branch instructions in
general, and which hardware provisions have been made to speed the execution of jump
instructions in particular. The general instruction timing is described, including standard and
exceptional timing.

While internal memory accesses are normally performed by the CPU itself, external
peripheral or memory accesses are performed by a particular on-chip External Bus
Controller (EBC), which is automatically invoked by the CPU whenever a code or data
address refers to the external address space.

If possible, the CPU continues to operate while an external memory access is in progress. If
external data are required but are not yet available, or if a new external memory access is
requested by the CPU, before a previous access has been completed, the CPU will be held
by the EBC until the request can be satisfied. The EBC is described in Section 8: The

external bus interface on page 181.

The on-chip peripheral units of the ST10F276 are almost independent of the CPU, with a
separate clock generator. Data and control information is interchanged between the CPU
and these peripherals via Special Function Registers (SFRs).

Whenever peripherals need a non-deterministic CPU action, an on-chip Interrupt Controller
compares all pending peripheral interrupt requests and prioritizes one of them.

If the priority of the current CPU operation is lower than the priority of the selected peripheral
request, an interrupt service will occur. There are two types of interrupt processing:

1. Standard interrupt processing forces the CPU to save the current program status

and return address on the stack before branching to the interrupt vector jump table.

2. PEC interrupt processing steals just one instruction cycle from the current CPU

activity to perform a single data transfer via the on-chip PEC.

System errors detected during program execution (so called hardware traps), or an external
non-maskable interrupt, are also processed as high priority standard interrupts.

There is a close conjunction between the watchdog timer and the CPU. If enabled, the
watchdog timer expects to be serviced by the CPU within a programmable period of time,
otherwise it will reset the chip.

Therefore, the watchdog timer is able to prevent the CPU from erratic behaviour when
executing erroneous code. After reset, the watchdog timer starts counting automatically, but
if necessary it can be disabled via software.

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UM0404 The central processing unit (CPU)

Beside its normal operation there are the following particular CPU states:

• RESET state: Any reset (hardware, software, watchdog) forces the CPU into a pre-

defined active state.

• IDLE state: The clock signal to the CPU itself is switched off, while the clocks for the

on-chip peripherals keep running.

• POWER DOWN state: All of the on-chip clocks are switched off.

A transition into an active CPU state is forced by an interrupt (if being IDLE) or by a reset (if
being in POWER DOWN mode).

The IDLE, POWER DOWN and RESET states can be entered by particular ST10F276
system control instructions. A set of Special Function Registers is dedicated to the functions
of the CPU core:

• General System Configuration: SYSCON (RP0H)

• CPU Status Indication and Control: PSW

• Code Access Control: IP, CSP

• Data Paging Control: DPP0, DPP1, DPP2, DPP3

• GPRs Access Control: CP

• System Stack Access Control: SP, STKUN, STKOV

• Multiply and Divide Support: MDL, MDH, MDC

• ALU Constants Support: ZEROS, ONES

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The central processing unit (CPU) UM0404

CPU

SP

STKOV

STKUN

Execution Unit

Instruction Pointer

4-Stage
Pipeline

PSW

SYSCON

MDH

MDL

Multiplication

Bit-Mask

Barrel-Shift

CP

16-bit

ALU

R15

R0

ADDRSEL 1

ADDRSEL 2

ADDRSEL 3

ADDRSEL 4

BUSCON 0

BUSCON 1

BUSCON 2

BUSCON 3

BUSCON 4

Code Segment Data Page

General
Purpose

Registers

2 Kbyte

Bank n

Bank i

Bank 0

16

16

512 Kbyte

IFlash

64 + 2 Kbyte

32

Division Hardware

Generator

PointerPointers

XRAM

IRAM

320 Kbyte

XFlash

16

Figure 8. CPU block diagram

3.1 Instruction pipelines

The instruction pipeline breaks down CPU processing into the four following stages:

• Fetch: An instruction selected by the Instruction Pointer (IP) and the Code Segment
Pointer (CSP) is fetched from either the internal memory, IRAM, XRAM or external
memory.

• Decode: Instructions are decoded and, if required, the operand addresses are

calculated and the respective operands are fetched.
For all instructions, which implicitly access the system stack, the SP register is either
decremented or incremented, as specified.
For branch instructions the Instruction Pointer and the Code Segment Pointer are
updated with the desired branch target address (provided that the branch is taken).

• Execute: An operation is performed on the previously fetched operands in the ALU.

Additionally, the condition flags in the PSW register are updated as specified by the
instruction. All explicit writes to the SFR memory space and all auto-increment or auto­decrement writes to GPRs used as indirect address pointers are performed during the
execute stage of an instruction, too.

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UM0404 The central processing unit (CPU)

1 instruction

cycle

FETCH I

2

I

1

I

3

I

2

I

1

I

4

I

3

I

2

I

1

I

6

I

5

I

4

I

3

I

5

I

4

I

3

I

2

I

1

DECODE

EXECUTE

WRITEBACK

time

• Write back: All external operands and the remaining operands within the IRAM space

are written back.

Injected instructions are generated internally by the machine to provide extra time for
instructions that require more than one instruction cycle. Instructions are automatically
injected into the decode stage of the pipeline, they pass through the remaining stages like
every standard instruction. Program interrupts are performed by the same method of
injecting instructions.

Figure 9. Sequential instruction pipelining

3.1.1 Sequential instruction processing

Each single instruction has to pass through each of the four pipeline stages regardless of
whether all possible stage operations are really performed or not. Since passing through
one pipeline stage takes at least one instruction cycle, any isolated instruction takes at least
four instruction cycles to be completed. Pipelining, however, allows parallel (simultaneous)
processing of up to four instructions. Therefore, as soon as the pipeline has been filled,
most instructions appear to be processed during one instruction cycle (see Figure 9 on

page 55).

Specification of instruction execution time always refers to the average execution time for

(see

pipelined parallel instruction processing

Figure 9 on page 55).

3.1.2 Standard branch instruction processing

When a branch is taken, it is necessary to perform the branched target instruction, before
the current instruction in the pipeline. Therefore, at least one additional instruction cycle is
required to fetch the branch target instruction.

This extra instruction cycle is provided by means of an injected instruction (see Figure 10 on

page 56). If a conditional branch is not taken, there is no deviation from the sequential

program flow, and thus no extra time is required. In this case the instruction after the branch
instruction will enter the decode stage of the pipeline at the beginning of the next instruction
cycle after decode of the conditional branch instruction.

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The central processing unit (CPU) UM0404

1 instruction

cycle

FETCH I

n+2

BRANCH

I

n

. . .

I

TARGET

(I

INJECT

)

BRANCH

I

n

I

TARGET+1

I

TARGET

(I

INJECT

)

BRANCH

I

TARGET+3

I

TARGET+2

I

TARGET+1

I

TARGET

I

TARGET+2

I

TARGET+1

I

TARGET

(I

INJECT

)

BRANCH

I

n

. . .

. . .

DECODE

EXECUTE

WRITEBACK

time

Injection

I

n+2

Cache Jmp

I

n

. . .

I

TARGET+1

I

TARGET

Cache Jmp

I

n

I

TARGET+2

I

TARGET+1

I

TARGET

Cache Jmp

I

n+2

Cache Jmp

I

n

. . .

I

TARGET

(I

INJECT

)

Cache Jmp

I

n

I

TARGET+1

I

TARGET

(I

INJECT

)

Cache Jmp

1 instruction

cycle

FETCH

DECODE

EXECUTE

WRITEBACK

1st loop iteration

Injection

Injection of cached
Target Instruction

Repeated loop iteration

Figure 10. Standard branch instruction pipelining

3.1.3 Cache jump instruction processing

The ST10F276 incorporates a jump cache. This minimizes the time taken for conditional
jumps which are repeatedly processed in a loop. Whenever a cache jump instruction passes
through the decode stage of the pipeline for the first time (provided that the jump condition is
met), the sequential instruction is fetched as usual, causing a time delay of one instruction
cycle.

If the instruction is repeated in a loop, the target instruction is additionally stored in the
cache. For execution of the repeated cache jump instruction, the jump target instruction is
not fetched from program memory but taken from the cache and immediately injected into
the decode stage of the pipeline (see Figure 11 on page 56).

A time saving jump on cache is always taken after the second and any further occurrence of
the same cache jump instruction, unless an instruction which has the fundamental capability
of changing the CSP register contents (JMPS, CALLS, RETS, TRAP, RETI), or any
standard interrupt has been processed during the period of time between two following
occurrences of the same cache jump instruction.

Figure 11. Cache jump instruction pipelining

3.1.4 Particular pipeline effects

Since up to four different instructions are processed simultaneously, additional hardware
has been included in the ST10F276 to take into account dependencies between instructions
in different stages of the pipeline.

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This extra hardware like a forwarding operand read and write values, resolves most of the
possible conflicts like multiple usage of buses.

UM0404 The central processing unit (CPU)

This prevents delays that would cause the pipeline to become noticeable to the user.
However, there are some cases where allowances must be made by the programmer, for
the pipeline architecture of the ST10F276.

In these cases the delays caused by pipeline conflicts can be used for other instructions in
order to optimize performance.

Context pointer updating

An instruction which calculates a physical GPR operand address via the CP register, is
generally not capable of using a new CP value, which is to be updated by an immediately
preceding instruction. Therefore, to make sure that the new CP value is used, at least one
instruction must be inserted between a CP changing and a subsequent GPR using
instruction, as shown in the example.

In : SCXT CP, #0FC00h ; select a new context

In+1 : .... ; must not be an instruction using a GPR

In+2 : MOV R0, #dataX ; write to GPR 0 in the new context

Data page pointer updating

An instruction which calculates a physical operand address via a particular DPPn (n=0 to 3)
register, is generally not capable of using a new DPPn register value, which is to be updated
by an immediately preceding instruction. Therefore, to make sure that the new DPPn
register value is used, at least one instruction must be inserted between a DPPn-changing
instruction and a subsequent instruction which implicitly uses DPPn via a long or indirect
addressing mode, as shown in the example.

In : MOV DPP0, #4 ; select data page 4 via DPP0

In+1 : .... ; must not be an instr using DPP0

In+2 : MOV DPP0:0000h, R1

; move contents of R1 to address loc
; 01’0000h

; (in dp 4) supposed segmentation is
; enabled

Explicit stack pointer updating

None of the RET, RETI, RETS, RETP or POP instructions are capable of correctly using a
new SP register value, which is to be updated by an immediately preceding instruction.
Therefore, in order to use the new SP register value without erroneously performed stack
accesses, at least one instruction must be inserted between an explicit SP writing and any
subsequent of the just mentioned implicitly SP using instructions, as shown in the example.

In : MOV SP, #0FA40h ; select a new top of stack

In+1 : ....

In+2 : POP R0

; must not be an instruction popping
; operands from the system stack

; pop Word value from new top of stack
; into R0

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The central processing unit (CPU) UM0404

External memory access sequences

The effect described here will only become noticeable, when watching the external memory
access sequences on the external bus by means of a Logic Analyzer. Different pipeline
stages can simultaneously put a request on the External Bus Controller (EBC).

The sequence of instructions processed by the CPU may diverge from the sequence of the
corresponding external memory accesses performed by the EBC, due to the predefined
priority of external memory accesses.

1st Write Data

2nd Fetch Code

3rd Read Data

Controlling interrupts

Software modifications (implicit or explicit) of the PSW are done in the execute phase of the
respective instructions. In order to maintain fast interrupt responses, however, the current
interrupt prioritization round does not consider these changes. For example an interrupt
request may be acknowledged after the instruction that disables interrupts via IEN or ILVL or
after the following instructions.

Time critical instruction sequences, therefore, should not begin directly after the instruction
disabling interrupts, as shown in the example.

INT_OFF: BCLR IEN ; globally disable interrupts

IN-1 ; non-critical instruction

CRIT_1ST: IN

. . .

CRIT_LAST: IN+x

INT_ON: BSET IEN ; globally re-enable interrupts

; start of non-interruptible critical
; sequence

; end of non-interruptible critical
; sequence

Note: The described delay of 1 instruction also applies for enabling the interrupts system that

means no interrupt requests are acknowledged until the instruction following the enabling
instruction.

Initialization of port pins

Modifications of the direction of port pins (input or output) become effective only after the
instruction following the modifying instruction. As bit instructions (BSET, BCLR) use internal
read-modify-write sequences accessing the whole port, instructions modifying the port
direction should be followed by an instruction that does not access the same port.

WRONG: BSET DP3.13 ; change direction of P3.13 to output

BSET P3.5

RIGHT: BSET DP3.13 ; change direction of P3.13 to output

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; P3.13 is still input, the read-modify-write

; reads pin P3.13

UM0404 The central processing unit (CPU)

NOP ; any instruction not accessing Port3

BSET P3.5 ; P3.13 is now output,

; the read-modify-write reads the P3.13 output
; latch

Changing the system configuration

The instruction following an instruction that changes the system configuration via register
SYSCON (like the mapping of the internal memory, like segmentation, like stack size),
cannot use the new resources (Memory or stack). This instruction must not access the new
resources.

Code accesses to the new Memory area are only possible after an absolute branch to this
area. As a rule, instructions that change Memory mapping must be executed from IRAM or
external memory.

BUSCON/ADDRSEL

The (I

) instruction following an (In) instruction that changes the properties of an external

n+1

address area, cannot access operands within the new area.

This instruction (I

) must not access this memory area. Code accesses to the new

n+1

address area must be made after an absolute branch to this area.

Note: As a rule, instructions that change external bus properties must not be executed from the

respective external memory area.

Timing

Pipeline architecture drastically reduces the average instruction processing time. The mean
ratio is about four to one instruction cycle. Some peculiar cases of pipeline configuration
extend the instruction processing time by half or by one cycle.

These cases have to be taken into account for the time critical software routines. Besides a
general execution time description, the following section provides some hints on how to
optimize time-critical program parts with regard to such pipeline-caused timing
particularities.

3.2 Bit-handling and bit-protection

The ST10F276 provides several mechanisms for bit manipulation. These mechanisms,
either handle software flags within the IRAM, control on-chip peripherals via control bits in
their respective SFRs, or control I/O functions via port pins.

The instructions BSET, BCLR, BAND, BOR, BXOR, BMOV and BMOVN, explicitly set or
clear specific bits. The instructions BFLDL and BFLDH make it possible to change up to 8
bits of a specific byte at a time.

The instructions JBC and JNBS implicitly clear or set the specified bit when the jump is
taken. The instructions JB and JNB (also conditional jump instructions that refer to flags)
evaluate the specified bit to determine if the jump is to be taken.

Note: Bit operations on undefined bit locations will always read a bit value of ‘0’, while the write

access will not affect the respective bit location.

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The central processing unit (CPU) UM0404

All instructions that change single bit or bit groups internally use a read-modify-write
sequence that accesses the whole word containing the specified bit(s). This method has
several consequences:

• Bit can only be modified within the internal specific address areas (IRAM, SFRs...).
External locations cannot be used with bit instructions.

• The upper 256 bytes of the SFR area, the ESFR area and the IRAM are bit­addressable (see Section 2: Memory organization on page 40). Those register bits
located within the respective sections can be directly manipulated using bit instructions.
The other SFRs must be accessed byte or word wise.

Note: All GPRs are bit-addressable independently of the allocation of the register bank via the

context pointer CP. Even GPRs which are allocated in not bit-addressable RAM locations
provide this feature.

• The read-modify-write approach may be critical with hardware-effected bits. In these
cases the hardware may change specific bit while the read-modify-write operation is in
progress, where the writeback would overwrite the new bit value generated by the
hardware. The solution is either the implemented hardware protection (see below) or
realized through special programming (see Section 3.1.4: Particular pipeline effects on

page 56).

Protected bits: As mentioned in Section 1.6: Protected bits on page 39 (hardware set) are

not modified during a read-modify-write sequence, even if an interrupt request rises
between read and write time. The hardware protection logic guarantees that only the
intended bit(s) is/are effected by the write-back operation.

Note: If a conflict occurs between a bit manipulation generated by hardware and an intended

software access the software access has priority and determines the final value of the
respective bit (see Section 1.6: Protected bits on page 39).

3.3 Instruction execution times

Instruction execution time depends on where the instruction is fetched from and where
operands are read from or written to. When a program is fetched from internal memory,
most of the instructions can be processed in one instruction cycle. All external memory
accesses are performed by the on-chip External Bus Controller (EBC) which works in
parallel with the CPU. This section summarizes the execution times. A detailed description
of the execution times for the various instructions and the specific exceptions can be found
in the ST10 Family Programming Manual. Ta ble 7 shows the minimum execution times
required to process a ST10F276 instruction fetched from the internal IFlash, the IRAM, or
from external memory. The values are in CPU clock cycles and assume no wait-states. Two
CPU clock cycles are equal to one instruction cycle.

These execution times apply to most of the ST10F276 instructions except some of the
branches, the multiplication, the division and a special move instruction. In case of
execution from the internal Program Memory, there is no execution time dependency on the
instruction length, except for some special branch situations. Because of the short execution
time, execution from on-chip RAM (IRAM and XRAM) is flexible for loadable and modifiable
code. Execution from external memory depends on the selected bus mode and the

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UM0404 The central processing unit (CPU)

programming of the bus cycles (wait-states). The operand and instruction accesses listed
below can extend the execution time of an instruction:

• Internal IFlash Memory operand reads (same for byte and word operand reads),

• Internal IRAM operand reads via indirect addressing modes,

• Internal SFR operand reads immediately after writing,

• External operand reads,

• External operand writes,

• Jumps to non-aligned double word instructions in the internal IFlash Memory space,

• Testing Branch Conditions immediately after PSW writes.

Memory area

Internal Memory (IFlash) 2 2

Internal Memory (XFlash) 2 4

Internal IRAM 6 8

Table 7. Minimum execution times

Instruction fetch

Word instruction

(CPU clock cycles)

Double word instruction

(CPU clock cycles)

Internal XRAM 2 4

16-bit De-multiplex Bus 2 4

16-bit Multiplexed Bus 3 6

8-bit De-multiplex Bus 4 8

8-bit Multiplexed Bus 6 12

3.4 CPU special function registers

The CPU requires a set of Special Function Registers (SFRs) to maintain the system state
information, to supply the ALU with register- addressable constants and to control system
and bus configuration, multiply and divide ALU operations, code memory segmentation,
data memory paging, and accesses to the General Purpose Registers and the System
Stack.

The access mechanism for these SFRs in the CPU core is identical to the access
mechanism for any other SFR. Since all SFRs can be controlled by means of any instruction
which is able to address the SFR memory space, a lot of flexibility has been gained without
creating a set of system-specific instructions.

Note, however, that there are user access restrictions for some of the CPU core SFRs to
ensure proper processor operations. The instruction pointer IP and code segment pointer
CSP cannot be accessed directly. They can only be changed indirectly via branch
instructions. The PSW, SP, and MDC registers can be modified, not only explicitly by the
programmer, but also implicitly by the CPU during normal instruction processing.

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The central processing unit (CPU) UM0404

Note: 1 Note that any explicit write request (via software) to an SFR supersedes a simultaneous

modification of the same register, by hardware.

2 Any write operation to a single byte of an SFR clears the non-addressed complementary

byte within the specified SFR. Non-implemented (reserved) SFR bits cannot be modified,
and will always supply a read value of '0'.

3.4.1 The system configuration register SYSCON

This bit-addressable register provides general system configuration and control functions.
The reset value for register SYSCON depends on the state of the PORT0 pins during reset
(see hardware affectable bits).

SYSCON (FF12h / 89h) SFR Reset Value: 0xx0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

STKSZ

RW RW RW

ROMS1SGT

Reset Value: 0000 0xx0 x000 0000b

Bit Function

ROMENBYT

DIS

RW RW RW RW RW RW RW RW RW RW RW

DIS

CLK

EN

WR

CFG

CS

CFG

PWD

CFG

OWD

DIS

BDR

STEN

XPEN

VISI
BLE

XPER-

SHARE

XPER-SHARE

VISIBLE

XPEN

BDRSTEN

OWDDIS

XBUS Peripheral Share Mode Control

‘0’: External accesses to XBUS peripherals are disabled.
‘1’: XRAM1 and XRAM2 are accessible via the external bus during hold

mode. External accesses to the other XBUS peripherals are not guaranteed
in terms of AC timings. See Section 2.4.1: XRAM access via external

masters on page 50 for additional details.

Visible Mode Control

‘0’: Accesses to XBUS peripherals and XRAM are done internally.
‘1’: XBUS peripheral accesses are made visible on the external pins.

XBUS Peripheral Enable bit

‘0’: Accesses to the on-chip X-peripherals and XRAM are disabled.
‘1’: The on-chip X-peripherals are enabled.

Bidirectional Reset Enable
‘0’: RSTIN

this pin.
‘1’: RSTIN

sequence.

Oscillator Watchdog Disable Control

‘0’: Oscillator Watchdog (OWD) is enabled. If PLL is bypassed, the OWD
monitors XTAL1 activity. If there is no activity on XTAL1 for at least 1 μs, the
CPU clock is switched automatically to PLL’s base frequency (from 750 kHz
to 3 MHz).

‘1’: OWD is disabled. If the PLL is bypassed, the CPU clock is always driven
by XTAL1 signal. The PLL is turned off to reduce power supply current.

pin is an input pin only. SW Reset or WDT Reset have no effect on

pin is a bidirectional pin. This pin is pulled low during internal reset

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UM0404 The central processing unit (CPU)

Bit Function

Power Down Mode Configuration Control

‘0’: Power Down Mode can only be entered during PWRDN instruction

PWDCFG

CSCFG

WRCFG

CLKEN

BYTDIS

execution if NMI
Power Down Mode, an external reset must occur by asserting the RSTIN

‘1’: Power Down Mode can only be entered during PWRDN instruction
execution if all enabled fast external interrupt EXxIN pins are in their inactive
level. Exiting this mode can be done by asserting one enabled EXxIN pin (or
alternate source see Section 5.6.1: Fast external interrupts on page 115) or
with external reset.

Chip Select Configuration Control

‘0’: Latched Chip Select lines, CSx changes 1 TCL after rising edge of ALE.
‘1’: Unlatched Chip Select lines, CSx changes with rising edge of ALE.

Write Configuration Control (Inverted copy of WRC bit of RP0H)
‘0’: Pins WR and BHE retain their normal function.
‘1’: Pin WR

System Clock Output Enable (CLKOUT)
‘0’: CLKOUT disabled, pin may be used for general purpose I/O.
‘1’: CLKOUT enabled, pin outputs the system clock signal or a prescaled

value of system clock according to XCLKOUTDIV register setting.
Disable/Enable Control for Pin BHE (Set according to data bus width)

‘0’: Pin BHE
‘1’: Pin BHE disabled, pin may be used for general purpose I/O.

pin is low, otherwise the instruction has no effect. To exit

pin.

acts as WRL, pin BHE acts as WRH.

enabled.

during reset)

ROMEN

SGTDIS

ROMS1

STKSZ

Internal Memory Enable (Set according to pin EA
‘0’: Internal memory disabled: accesses to the IFlash Memory area use the

external bus.
‘1’: Internal memory enabled.

Segmentation Disable/Enable Control

‘0’: Segmentation enabled (CSP is saved/restored during interrupt entry/exit).
‘1’: Segmentation disabled (Only IP is saved/restored).

Internal Memory Mapping

‘0’: Internal memory area mapped to segment 0 (00’0000h...00’7FFFh).
‘1’: Internal memory area mapped to segment 1 (01’0000h...01’7FFFh).

System Stack Size

Selects the size of the system stack (in the IRAM) from 32 to 1024 words.

Note: Register SYSCON cannot be changed after execution of the EINIT instruction.

The function of bit XPER-SHARE, VISIBLE, WRCFG, BYTDIS, ROMEN and ROMS1 is
described in more detail in Section 8.2: External bus modes on page 183.

System clock output enable (CLKEN)

The system clock output function is enabled by setting bit CLKEN in register SYSCON to '1'.
If enabled, port pin P3.15 takes on its alternate function as CLKOUT output pin. The clock
output is a 50 % duty cycle clock whose frequency equals the CPU operating frequency

= f

(f

OUT

). In case XCLKOUTDIV register is used, the f

CPU

can be equal to the

OUT

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The central processing unit (CPU) UM0404

programmed prescaled value of the f

(prescaler factor is programmable from 1 to 256

CPU

linearly, default value after reset is 1).

Note: The output driver of port pin P3.15 is switched on automatically, when the CLKOUT function

is enabled. The port direction bit is disregarded.
After reset, the clock output function is disabled (CLKEN = ‘0’).

Segmentation disable/enable control (SGTDIS)

Bit SGTDIS allows to select either the segmented or non-segmented memory mode.

In non-segmented memory mode (SGTDIS = '1') it is assumed that the code address

space is restricted to 64 Kbytes (segment 0) and thus 16 bits are sufficient to represent all
code addresses.

For implicit stack operations (CALL or RET) the CSP register is totally ignored and only the
IP is saved to and restored from the stack.

In segmented memory mode (SGTDIS = '0') it is assumed that the whole address space is

available for instructions. For implicit stack operations (CALL or RET) the CSP register and
the IP are saved to and restored from the stack. After reset the segmented memory mode is
selected.

Note: Bit SGTDIS controls if the CSP register is pushed onto the system stack in addition to the IP

register before an interrupt service routine is entered, and it is re-popped when the interrupt
service routine is left again.

System stack size (STKSZ)

This bit-field defines the size of the physical system stack, which is located in the IRAM of
the ST10F276. An area of 32...1024 words or all of the IRAM may be dedicated to the
system stack. A so-called “circular stack” mechanism allows to use a bigger virtual stack
than this dedicated IRAM area. These techniques as well as the encoding of bit-field STKSZ
are described in more detail in Stack Operations (see Section 27.1: Stack operations on

page 547).

(STKSZ) Stack size (words) IRAM addresses (words)

0 0 0b 256 00’FBFEh...00’FA00h (Default after Reset)

0 0 1b 128 00’FBFEh...00’FB00h

0 1 0b 64 00’FBFEh...00’FB80h

0 1 1b 32 00’FBFEh...00’FBC0h

1 0 0b 512 00’FBFEh...00’F800h

1 0 1b --- Reserved. Do not use this combination.

1 1 0b --- Reserved. Do not use this combination.

1 1 1b 1024 00’FDFEh...00’F600h (Note: No circular stack)

Table 8. Stack size

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UM0404 The central processing unit (CPU)

3.4.2 X-Peripherals control register (XPERCON)

XPERCON (F024h / 12h) ESFR Reset Value: - 005h

1514131211109876543210

-----

XMISCENXI2CENXSSCENXASCENXPWMENXFLAS

RW RW RW RW RW RW RW RW RW RW RW

Bit Function

CAN1 Enable Bit

‘0’: Accesses to the on-chip CAN1 XPeripheral and its functions are disabled (P4.5

CAN1EN

and P4.6 pins can be used as general purpose IOs, but address range 00’EF00h­00’EFFFh is directed to external memory only if CAN2EN, XRTCEN, XASCEN,
XSSCEN, XI2CEN, XPWMEN an XMISCEN are ‘0’ also).

‘1’: The on-chip CAN1 XPeripheral is enabled and can be accessed.

CAN2 Enable Bit

‘0’: Accesses to the on-chip CAN2 XPeripheral and its functions are disabled (P4.4

CAN2EN

and P4.7 pins can be used as general purpose IOs, but address range 00’EE00h­00’EEFFh is directed to external memory only if CAN1EN, XRTCEN, XASCEN,
XSSCEN, XI2CEN, XPWMEN and XMISCEN are ‘0’ also).

‘1’: The on-chip CAN2 XPeripheral is enabled and can be accessed.

XRTCENXRAM2ENXRAM1ENCAN2ENCAN1

HEN

EN

XRAM1EN

XRAM2EN

XRTCEN

XPWMEN

XFLASHEN

XRAM1 Enable Bit

‘0’: Accesses to the on-chip 2 Kbyte XRAM are disabled. Address range 00’EE00h­00’EEFFh is directed to external memory.

‘1’: The on-chip 2 Kbyte XRAM is enabled and can be accessed.

XRAM2 Enable Bit

‘0’: Accesses to the on-chip 64 Kbyte XRAM are disabled, external access performed.
Address range 0F’0000h-0F’FFFFh is directed to external memory only if XFLASHEN
is ‘0’ also.

‘1’: The on-chip 64 Kbyte XRAM is enabled and can be accessed.

RTC Enable

‘0’: Accesses to the on-chip RTC module are disabled, external access performed.
Address range 00’ED00h-00’EDFF is directed to external memory only if CAN1EN,
CAN2EN, XASCEN, XSSCEN, XI2CEN, XPWMEN and XMISCEN are ‘0’ also.

‘1’: The on-chip RTC module is enabled and can be accessed.

XPWM Enable

‘0’: Accesses to the on-chip XPWM module are disabled, external access performed.
Address range 00’EC00h-00’ECFF is directed to external memory only if CAN1EN,
CAN2EN, XASCEN, XSSCEN, XI2CEN, XRTCEN and XMISCEN are ‘0’ also.

‘1’: The on-chip XPWM module is enabled and can be accessed.

XFlash Enable Bit

‘0’: Accesses to the on-chip XFlash and Flash control registers are disabled, external
access performed. Address range 09’0000h-0E’FFFFh is directed to external memory
only if XRAM2EN is ‘0’ also.

‘1’: The on-chip XFlash is enabled and can be accessed.

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The central processing unit (CPU) UM0404

Bit Function

XASC Enable Bit

‘0’: Accesses to the on-chip XASC are disabled, external access performed. Address

XASCEN

XSSCEN

XI2CEN

XMISCEN

range 00’E900h-00’E9FFh is directed to external memory only if CAN1EN, CAN2EN,
XRTCEN, XASCEN, XI2CEN, XPWMEN and XMISCEN are ‘0’ also.

‘1’: The on-chip XASC is enabled and can be accessed.

XSSC Enable Bit

‘0’: Accesses to the on-chip XSSC are disabled, external access performed. Address
range 00’E800h-00’E8FFh is directed to external memory only if CAN1EN, CAN2EN,
XRTCEN, XASCEN, XI2CEN, XPWMEN and XMISCEN are ‘0’ also.

‘1’: The on-chip XSSC is enabled and can be accessed.

2

I

C Enable Bit

‘0’: Accesses to the on-chip I2C are disabled, external access performed. Address
range 00’EA00h-00’EAFFh is directed to external memory only if CAN1EN, CAN2EN,
XRTCEN, XASCEN, XSSCEN, XPWMEN and XMISCEN are ‘0’ also.

‘1’: The on-chip I2C is enabled and can be accessed.

XBUS Additional Features Enable Bit

‘0’: Accesses to the Additional Miscellaneous Features is disabled. Address range
00’EB00h-00’EBFFh is directed to external memory only if CAN1EN, CAN2EN,
XRTCEN, XASCEN, XSSCEN, XPWMEN and XI2CEN are ‘0’ also.

‘1’: The Additional Features are enabled and can be accessed.

When CAN1, CAN2, RTC, XASC, XSSC, I2C, XPWM and the XBUS Additional Features
are all disabled via XPERCON setting, then any access in the address range 00’E800h ­00’EFFFh will be directed to external memory interface, using the BUSCONx register
corresponding to address matching ADDRSELx register. All pins involved with X­Peripherals, can be used as General Purpose IO whenever the related module is not
enabled.

The default X-Peripheral configuration after reset is such that only CAN1 and XRAM1 are
pre-selected: they will be enabled once XPEN bit in SYSCON register is set.

Register XPERCON cannot be changed after the global enabling of X-Peripherals, that is,
after setting of bit XPEN in SYSCON register.

In Emulation mode, all the X-Peripherals are enabled (XPERCON bits are all set). It is up to
the emulation device to redirect or not an access to external memory or to XBUS. Register
XPEREMU has been created to allow a dynamic selection of this redirection instead of a
static configuration of the emulator at the start-up.

Reserved bits of XPERCON register should always be written to ‘0’.

3.4.3 XPERCON and XPEREMU registers

As already mentioned, XPERCON register has to be programmed to enable the single
XBUS modules separately. The XPERCON is a read/write ESFR register; the XPEREMU
register is a write-only register mapped on XBUS memory space (address EB7Eh).

Once the XPEN bit of SYSCON register is set and at least one of the X-peripherals (except
memories) is activated, the register XPEREMU must be written with the same content of
XPERCON: this is mandatory in order to allow a correct emulation of the new set of features

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UM0404 The central processing unit (CPU)

introduced on XBUS for the new ST10 generation. The following instructions must be added
inside the initialization routine:

if (SYSCON.XPEN && (XPERCON & 0x07D3))
then { XPEREMU = XPERCON }

Of course, XPEREMU must be programmed after XPERCON and after SYSCON, in such a
way the final configuration for X-Peripherals is stored in XPEREMU and used for the
emulation hardware setup.

XPEREMU (EB7Eh) XBUS Reset Value: xxxxh

1514131211109876543210

-----

XMISCENXI2CENXSSCENXASCENXPWMENXFLAS

WWWWWWWWWWW

XRTCENXRAM2ENXRAM1ENCAN2ENCAN1

HEN

EN

The bit meaning is exactly the same as XPERCON.

3.4.4 Emulation dedicated registers

Four additional registers are implemented for emulation purpose only. Similarly to
XPEREMU, they are write only registers and reserved for emulator software usage. User
should not write to these registers.

XEMU0 (EB76h) XBUS Reset Value: xxxxh

1514131211109876543210

XEMU0(15:0)

W

XEMU1 (EB78h) XBUS Reset Value: xxxxh

1514131211109876543210

XEMU1(15:0)

XEMU2 (EB7Ah) XBUS Reset Value: xxxxh

1514131211109876543210

XEMU2(15:0)

XEMU3 (EB7Ch) XBUS Reset Value: xxxxh

1514131211109876543210

XEMU3(15:0)

3.4.5 The processor status word PSW

This bit-addressable register reflects the current state of the microcontroller. Two groups of
bits represent the current ALU status, and the current CPU interrupt status. A separate bit
(USR0) within register PSW is provided as a general purpose user flag.

W

W

W

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The central processing unit (CPU) UM0404

PSW (FF10h / 88h) SFR Reset Value: 0000h

1514131211109876543210

ILVL IEN

RW RW RW RW RW RW RW RW RW RW

Bit Function

HLD

EN

---USR0

MUL

EZVCN

IP

N

C

V

Z

E

MULIP

USR0

HLDEN,

ILVL, IEN

Negative Result

Set when the result of an ALU operation is negative.

Carry Flag

Set when the result of an ALU operation produces a carry bit.

Overflow Result

Set when the result of an ALU operation produces an overflow.

Zero Flag

Set when the result of an ALU operation is zero.

End of Table Flag

Set when the source operand of an instruction is 8000h or 80h.

Multiplication/Division In Progress

‘0’: There is no multiplication/division in progress.
‘1’: A multiplication/division has been interrupted.

User General Purpose Flag

May be used by the application software.

Interrupt and EBC Control Fields

Define the response to interrupt requests and enable external bus Arbitration
(Described in Section 5: Interrupt and trap functions on page 96).

ALU status (N, C, V, Z, E, MULIP)

The condition flags (N, C, V, Z, E) within the PSW indicate the ALU status due to the last
performed ALU operation. They are set by most of the instructions due to specific rules,
which depend on the ALU or data movement operation performed by an instruction.

After execution of an instruction which explicitly updates the PSW register, the condition
flags cannot be interpreted as described in the following, because any explicit write to the
PSW register supersedes the condition flag values, which are implicitly generated by the
CPU.

Explicitly reading the PSW register supplies a read value which represents the state of the
PSW register after execution of the immediately preceding instruction.

Note: After reset, all of the ALU status bits are cleared.

N-Flag: For most of the ALU operations, the N-flag is set to '1' if the most significant bit of

the result contains a '1', otherwise it is cleared. In the case of integer operations the N-flag
can be interpreted as the sign bit of the result (negative: N=’1’, positive: N=’0’). Negative
numbers are always represented as the 2's complement of the corresponding positive
number. The range of signed numbers extends from '–8000h' to '+7FFFh' for the word data
type, or from '–80h' to '+7Fh' for the byte data type. For Boolean bit operations with only one

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UM0404 The central processing unit (CPU)

operand the N-flag represents the previous state of the specified bit. For Boolean bit
operations with two operands the N-flag represents the logical XOR of the two specified bits.

C-Flag: After an addition the C-flag indicates that a carry from the most significant bit of the

specified word or byte data type has been generated. After a subtraction or a comparison
the C-flag indicates a borrow, which represents the logical negation of a carry for the
addition.

This means that the C-flag is set to '1' if no carry from the most significant bit of the specified

word or byte data type has been generated during a subtraction, which is performed
internally by the ALU as a 2's complement addition, and the C-flag is cleared when this
complement addition caused a carry. The C-flag is always cleared for logical, multiply and
divide ALU operations, because these operations cannot cause a carry anyhow.

For shift and rotate operations the C-flag represents the value of the bit shifted out last. If a
shift count of zero is specified, the C-flag will be cleared. The C-flag is also cleared for a
prioritize ALU operation, because a '1' is never shifted out of the MSB during the
normalization of an operand. For Boolean bit operations with only one operand the C-flag is
always cleared. For Boolean bit operations with two operands the C-flag represents the
logical ANDing of the two specified bits.

V-Flag: For addition, subtraction and 2's complementation the V-flag is always set to '1' if

the result overflows the maximum range of signed numbers, which are representable by
either 16-bit for word operations ('–8000h' to '+7FFFh'), or by 8-bit for byte operations ('–
80h' to '+7Fh'), otherwise the V-flag is cleared. The result of an integer addition, integer
subtraction, or 2's complement is not valid if the V-flag indicates an arithmetic overflow.

For multiplication and division the V-flag is set to '1' if the result cannot be represented in a
word data type, otherwise it is cleared. A division by zero will always cause an overflow. In
contrast to the result of a division, the result of a multiplication is valid regardless of whether
the V-flag is set to '1' or not. Since logical ALU operations cannot produce an invalid result,
the V-flag is cleared by these operations.

The V-flag is also used as 'Sticky bit' for rotate right and shift right operations. With only
using the C-flag, a rounding error caused by a shift right operation can be estimated up to a
quantity of one half of the LSB of the result. In conjunction with the V-flag, the C-flag allows
evaluating the rounding error with a finer resolution (see Table 9). For Boolean bit
operations with only one operand the V-flag is always cleared. For Boolean bit operations
with two operands the V-flag represents the logical ORing of the two specified bits.

C-flag V-flag Rounding error quantity

0
0
1
1

T able 9. Shift right rounding error evaluation

0
1
0
1

No rounding error
0 <Rounding error<

Rounding error=
Rounding error>

1

/2 LSB

1

/2 LSB

1

/2 LSB

Z-Flag: The Z-flag is normally set to '1' if the result of an ALU operation equals zero,

otherwise it is cleared. For the addition and subtraction with carry the Z-flag is only set to '1'
if the Z-flag already contains a '1' and the result of the current ALU operation additionally
equals zero. This mechanism is provided for the support of multiple precision calculations.

For Boolean bit operations with only one operand the Z-flag represents the logical negation
of the previous state of the specified bit. For Boolean bit operations with two operands the Z-

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The central processing unit (CPU) UM0404

flag represents the logical NORing of the two specified bits. For the prioritize ALU operation
the Z-flag indicates, if the second operand was zero or not.

E-Flag: The E-flag can be altered by instructions, which perform ALU or data movement

operations. The E-flag is cleared by those instructions which cannot be reasonably used for
table search operations. In all other cases the E-flag is set depending on the value of the
source operand to signify whether the end of a search table is reached or not.

If the value of the source operand of an instruction equals the lowest negative number,
which is representable by the data format of the corresponding instruction ('8000h' for the
word data type, or '80h' for the byte data type), the E-flag is set to '1', otherwise it is cleared.

MULIP-Flag: The MULIP-flag is set to '1' by hardware upon the entrance into an interrupt

service routine, when a multiply or divide ALU operation is interrupted before completion.
Depending on the state of the MULIP bit, the hardware decides whether a multiplication or
division must be continued or not after the end of an interrupt service. The MULIP bit is
overwritten with the contents of the stacked MULIP-flag when the return-from-interrupt­instruction (RETI) is executed. This normally means that the MULIP-flag is cleared again
after that.

Note: The MULIP flag is a part of the task environment. When the interrupting service routine does

not return to the interrupted multiply/divide instruction (for example in case of a task
scheduler that switches between independent tasks), the MULIP flag must be saved as part
of the task environment and must be updated accordingly for the new task before this task is
entered.

CPU interrupt status (IEN, ILVL): The Interrupt Enable bit allows to globally enable

(IEN=’1’) or disable (IEN=’0’) interrupts. The 4-bit Interrupt Level field (ILVL) specifies the
priority of the current CPU activity.

The interrupt level is updated by hardware upon entry into an interrupt service routine, but it
can also be modified via software to prevent other interrupts from being acknowledged. In
case an interrupt level '15' has been assigned to the CPU, it has the highest possible
priority, and thus the current CPU operation cannot be interrupted except by hardware traps
or external non-maskable interrupts. For details refer to Section 5: Interrupt and trap

functions on page 96.

After reset all interrupts are globally disabled, and the lowest priority (ILVL=0) is assigned to
the initial CPU activity.

3.4.6 The instruction pointer IP

This register determines the 16-bit intra-segment address of the currently fetched instruction
within the code segment selected by the CSP register.

The IP register is not mapped into the MCU address space, and thus it is not directly
accessible by the programmer. The IP can, however, be modified indirectly via the stack by
means of a return instruction.

The IP register is implicitly updated by the CPU for branch instructions and after instruction
fetch operations.

IP (---- / --) --- Reset Value: 0000h

1514131211109876543210

IP

(R)(W)

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Code Segment

255

254

1

0

FF’FFFFh

FE’0000h

01’0000h

00’0000h

15 0

CSP Register

15 0

IP Register

24 / 20 / 18-bit Physical Code Address

Bit Function

Instruction Pointer

IP

Specifies the intra segment offset, from where the current instruction is to be fetched. IP
refers to the current segment (SEGNR bit field of CSP register).

3.4.7 The code se gment pointer CSP

This non-bit-addressable register selects the code segment being used at run-time to
access instructions. The lower 8 bits of register CSP select one of up to 256 segments of 64
Kbytes each, while the upper 8 bits are reserved for future use.

CSP (FE08h / 04h) SFR Reset Value: 0000h

1514131211109876543210

-------- SEGNR

R

Bit Function

Segment Number

SEGNR

Specifies the code segment, from where the current instruction is to be fetched. SEGNR
is ignored, when segmentation is disabled.

Figure 12. Addressing via the code segment pointer

Note: When segmentation is disabled, the IP value is used directly as the 16-bit address.

Code memory addresses are generated by directly extending the 16-bit contents of the IP
register by the contents of the CSP register as shown in the Figure 1 on page 23.

In case of the segmented memory mode the selected number of segment address bits
(7...0, 3...0 or 1...0) of register CSP is output on the segment address pins A23...A16 of
Port4 for all external code accesses. For non-segmented memory mode the content of this
register is not significant, because all code accesses are automatically restricted to
segment 0.

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The central processing unit (CPU) UM0404

The CSP register can only be read but not written by data operations. It is, however,
modified either directly by means of the JMPS and CALLS instructions, or indirectly via the
stack by means of the RETS and RETI instructions.

Upon the acceptance of an interrupt or the execution of a software TRAP instruction, the
CSP register is automatically set to zero.

3.4.8 The data page pointers DPP0, DPP1, DPP2, DPP3

These four non-bit-addressable registers select up to four different data pages being active
simultaneously at run-time. The lower 10 bits of each DPP register select one of the 1024
possible 16 Kbyte data pages while the upper 6 bits are reserved for future use. The DPP
registers make it possible to access the entire memory space, in pages of 16 Kbytes each.

The DPP registers are implicitly used whenever data accesses to any memory location are
made via indirect, or direct long 16-bit addressing modes (except for override accesses via
EXTended instructions and PEC data transfers). After reset, the Data Page Pointers are
initialized in a way that all indirect or direct long 16-bit addresses result in identical 18-bit
addresses. This allows to access data pages 3...0 within segment 0 as shown in the

Figure 13 on page 73. If the user does not want to use any data paging, no further action is

required.

DPP0 (FE00h / 00h) SFR Reset Value: 0000h

1514131211109876543210

------ DPP0PN

RW

DPP1 (FE02h / 01h) SFR Reset Value: 0001h

1514131211109876543210

------ DPP1PN

RW

DPP2 (FE04h / 02h) SFR Reset Value: 0002h

1514131211109876543210

------ DPP2PN

RW

DPP3 (FE06h / 03h) SFR Reset Value: 0003h

1514131211109876543210

------ DPP3PN

RW

Bit Function

Data Page Number of DPPx

DPPxPN

Specifies the data page selected via DPPx. Only the 2 least significant bits of DPPx
are used when segmentation is disabled.

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UM0404 The central processing unit (CPU)

Data Pages

1023

1022

1021

3

2

1

0

DPP Registers

DPP3-11

DPP2-10

DPP1-01

DPP0-00

After reset or with segmentation disabled the DPP registers select data pages 3...0.
All of the internal memory is accessible in these cases.

1415 0

16-bit Data Address

90

14-bit

10-bit

13

DPP register concatenated with 14-bit
Intra-Page Address gives 24-bit address.

Data paging is performed by concatenating the lower 14 bits of an indirect or direct, long 16
bit address with the contents of the DPP register, selected by the upper two bits of the 16-bit
address. The content of the selected DPP register specifies one of 1024 possible data
pages. This data page base address, together with the 14-bit page offset forms the physical
24-/20-/18-bit address. In case of non-segmented memory mode, only the two least
significant bits of the implicitly selected DPP register are used to generate the physical
address. Thus, extreme care should be taken when changing the content of a DPP register,
if a non-segmented memory model is selected, because unexpected results could occur.

In case of the segmented memory mode the selected number of segment address bits
(9...2, 5...2 or 3...2) of the respective DPP register is output on the segment address pins
A23/A19/A17/A16 of Port4 for all external data accesses. A DPP register can be updated
via any instruction, which is capable of modifying an SFR.

Due to the internal instruction pipeline, a new DPP value is not yet usable for the operand
address calculation of the instruction, immediately following the instruction updating the
DPP register.

Figure 13. Addressing via the data page pointers

3.4.9 The context pointer CP

This non-bit-addressable register is used to select the current register context. This means
that the CP register value determines the address of the first General Purpose Register
(GPR) within the current register bank of up to 16 word wide and/or byte wide GPRs.

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The central processing unit (CPU) UM0404

CP (FE10h / 08h) SFR Reset Value:FC00h

1514131211109876543210

1111 CP 0

RRRR RW

Bit Function

Modifiable portion of register CP

CP

Specifies the (word) base address of the current register bank. When writing a value
to register CP with bit CP.11...CP.9 = ‘000’, bit CP.11...CP.10 are set to ‘11’ by
hardware, in all other cases all bits of bit-field “CP” receive the written value.

R

It is the user's responsibility to ensure that the physical GPR address, specified via the CP
register plus the short GPR address, must always be an IRAM location. If this condition is
not met, unexpected results may occur.

• Do not set CP below the IRAM start address, 00’F600h (2 Kbytes).

• Do not set CP above 00’FDFEh.

• Be careful using the upper GPRs with CP above 00’FDE0h.

The CP register can be updated via any instruction which is capable of modifying an SFR.

Note: Due to the internal instruction pipeline, a new CP value is not yet usable for GPR address

calculations of the instruction immediately following the instruction updating the CP register.

The Switch Context instruction (SCXT) makes it possible to save the content of register CP
on the stack and updating it with a new value in just one instruction cycle.

Several addressing modes use register CP implicitly for address calculations.

Short 4-bit GPR addresses (mnemonic: Rw or Rb) specify an address relative to the

memory location specified by the contents of the CP register, which is the base of the
current register bank.

Depending on whether a relative word (Rw) or byte (Rb) GPR address is specified, the short
4-bit GPR address is either multiplied by two or not before it is added to the content of
register CP (see Figure 15 on page 75).

Thus, both byte and word GPR accesses are possible in this way. GPRs used as indirect
address pointers are always accessed word wise.

For some instructions only the first four GPRs can be used as indirect address pointers.
These GPRs are specified via short 2-bit GPR addresses. The respective physical address
calculation is identical to that for the short 4-bit GPR addresses.

Short 8-bit register addresses (mnemonic: reg or bitoff) within a range from F0h to FFh

interpret the four least significant bits as short 4-bit GPR address, while the four most
significant bits are ignored.

The respective physical GPR address calculation is identical to that for the short 4-bit GPR
addresses. For single bit accesses on a GPR, the GPR's word address is calculated as just
described, but the position of the bits within the word is specified by a separate additional 4­bit value.

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UM0404 The central processing unit (CPU)

R15

R14

R13

R12

R11

R10

R9

R8

R7

R6

R5

R4

R3

R2

R1

R0

(CP) + 30

(CP) + 28

(CP) + 2

(CP)

IRAM

Context

Pointer

Context Pointer 4-bit GPR Address1111

Specified by register or bitoff

+

x2

Control

For byte GPR

accesses

For word GPR

accesses

IRAM

GPRs

Must be
within the
IRAM area

Figure 14. Register bank selection via register CP

Figure 15. Implicit CP use by short GPR addressing modes

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The central processing unit (CPU) UM0404

3.4.10 The stack pointer SP

This non-bit-addressable register is used to point to the top of the internal system stack
(TOS). The SP register is pre-decremented whenever data is to be pushed onto the stack,
and it is post-incremented whenever data is to be popped from the stack. Thus, the system
stack grows from higher toward lower memory locations.

Since the least significant bit of register SP is tied to '0' and bits 15 through 12 are tied to '1'
by hardware, the SP register can only contain values from F000h to FFFEh. This allows to
access a physical stack within the IRAM of the MCU. A virtual stack (usually bigger) can be
realized via software. This mechanism is supported by registers STKOV and STKUN (see
respective descriptions below).

The SP register can be updated via any instruction which is capable of modifying an SFR.

Note: Due to the internal instruction pipeline, a POP or RETURN instructions must not

immediately follow an instruction updating the SP register.

SP (FE12h / 09h) SFR Reset Value:FC00h

1514131211109876543210

1111 SP 0

RRRR

RW R

Bit Function

SP

Modifiable portion of register SP

Specifies the top of the internal system stack.

3.4.11 The stack overflow pointer STKOV

This non-bit-addressable register is compared against the SP register after each operation,
which pushes data onto the system stack (PUSH and CALL instructions or interrupts) and
after each subtraction from the SP register. If the content of the SP register is less than the
content of the STKOV register, a stack overflow hardware trap will occur. Since the least
significant bit of register STKOV is tied to '0' and bits 15 through 12 are tied to '1' by
hardware, the STKOV register can only contain values from F000h to FFFEh.

STKOV (FE14h / 0Ah) SFR Reset Value: FA00h

1514131211109876543210

1111 STKOV 0

RRRR RW

Bit Function

STKOV

Modifiable portion of register STKOV

Specifies the lower limit of the internal system stack.

R

The Stack Overflow Trap (entered when (SP) < (STKOV)) may be used in two different
ways:

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Fatal error indication treats the stack overflow as a system error through the associated

trap service routine. Under these circumstances data in the bottom of the stack may have
been overwritten by the status information stacked upon servicing the stack overflow trap.

Automatic system stack flushing allows to use the system stack as a 'Stack Cache' for a

bigger external user stack. In this case register STKOV should be initialized to a value,
which represents the desired lowest Top of Stack address plus 12 according to the selected
maximum stack size. This considers the worst case that will occur when a stack overflow
condition is detected just during entry into an interrupt service routine. Then, six additional
stack word locations are required to push IP, PSW and CSP for both the interrupt service
routine and the hardware trap service routine.

More details about the stack overflow trap service routine and virtual stack management are
given in Section 27: System programming on page 545.

3.4.12 The stack underflow pointer STKUN

This non-bit-addressable register is compared against the SP register after each operation,
which pops data from the system stack (POP and RET instructions) and after each addition
to the SP register. If the content of the SP register is greater than the content of the STKUN
register, a stack underflow hardware trap will occur.

Since the least significant bit of register STKUN is tied to '0' and bits 15 through 12 are tied
to '1' by hardware, the STKUN register can only contain values from F000h to FFFEh.

STKUN (FE16h / 0Bh) SFR Reset Value:FC00h

1514131211109876543210

1111 STKUN 0

RRRR RW

R

Bit Function

STKUN

Modifiable portion of register STKUN

Specifies the upper limit of the internal system stack.

The Stack Underflow Trap (entered when (SP) > (STKUN)) may be used in two different
ways:

• Fatal error indication treats the stack underflow as a system error through the

associated trap service routine.

• Automatic system stack refilling allows to use the system stack as a 'Stack Cache'

for a bigger external user stack. In this case register STKUN should be initialized to a
value, which represents the desired highest Bottom of Stack address.

More details about the stack underflow trap service routine and virtual stack management
are given in Section 27: System programming on page 545.

Scope of stack limit control

The stack limit control realized by the register pair STKOV and STKUN detects cases where
the stack pointer SP is moved outside the defined stack area either by ADD or SUB
instructions or by PUSH or POP operations (explicit or implicit, CALL or RET instructions).

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The central processing unit (CPU) UM0404

This control mechanism is not triggered, and no stack trap is generated, when:

• The stack pointer SP is directly updated via MOV instructions.

• The limits of the stack area (STKOV, STKUN) are changed, so that SP is outside of the

new limits.

3.4.13 The multiply / divide high register MDH

This register is a part of the 32-bit multiply/divide register, which is implicitly used by the
CPU, when it performs a multiplication or a division. After a multiplication, this non-bit­addressable register represents the high order 16 bits of the 32-bit result. For long divisions,
the MDH register must be loaded with the high order 16 bits of the 32-bit dividend before the
division is started. After any division, register MDH represents the 16-bit remainder.

MDH (FE0Ch / 06h) SFR Reset Value: 0000h

1514131211109876543210

mdh

RW

Bit Function

MDH Specifies the high order 16 bits of the 32-bit multiply and divide register MD.

Whenever this register is updated via software, the Multiply/Divide Register In Use (MDRIU)
flag in the Multiply/Divide Control register (MDC) is set to '1'. When a multiplication or
division is interrupted before its completion and when a new multiply or divide operation is to
be performed within the interrupt service routine, register MDH must be saved along with
registers MDL and MDC to avoid erroneous results.

A detailed description of how to use the MDH register for programming multiply and divide
algorithms can be found in Section 27: System programming on page 545.

3.4.14 The multiply / divide low register MDL

This register is a part of the 32-bit multiply/divide register, which is implicitly used by the
CPU, when it performs a multiplication or a division. After a multiplication, this non-bit­addressable register represents the low order 16 bits of the 32-bit result. For long divisions,
the MDL register must be loaded with the low order 16 bits of the 32-bit dividend before the
division is started. After any division, register MDL represents the 16-bit quotient.

MDL (FE0Eh / 07h) SFR Reset Value: 0000h

1514131211109876543210

mdl

RW

Bit Function

mdl Specifies the low order 16 bits of the 32-bit multiply and divide register MD.

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UM0404 The central processing unit (CPU)

Whenever this register is updated via software, the Multiply/Divide Register In Use (MDRIU)
flag in the Multiply/Divide Control register (MDC) is set to '1'. The MDRIU flag is cleared,
whenever the MDL register is read via software. When a multiplication or division is
interrupted before its completion and when a new multiply or divide operation is to be
performed within the interrupt service routine, register MDL must be saved along with
registers MDH and MDC to avoid erroneous results.

A detailed description of how to use the MDL register for programming multiply and divide
algorithms can be found in Section 27: System programming on page 545.

3.4.15 The multiply / divide control register MDC

This bit-addressable 16-bit register is implicitly used by the CPU, when it performs a
multiplication or a division. It is used to store the required control information for the
corresponding multiply or divide operation. Register MDC is updated by hardware during
each single cycle of a multiply or divide instruction.

MDC (FF0Eh / 87h) SFR Reset Value: 0000h

1514131211109876543210

--------MSMSMS

RW RW RW RW RW RW RW RW

MDR

MS MS MS MS

IU

Bit Function

Internal Machine Status

MS

MDRIU

The multiply/divide unit uses these bits to control internal operations.
Never modify these bits without saving and restoring register MDC.

Multiply/Divide Register In Use

‘0’: Cleared, when register MDL is read via software.
‘1’:Set when register MDL or MDH is written via software, or when a multiply or

divide instruction is executed.

When a division or multiplication was interrupted before its completion and the
multiply/divide unit is required, the MDC register must first be saved along with registers
MDH and MDL (to be able to restart the interrupted operation later), and then it must be
cleared, preparing it for the new calculation. After completion of the new division or
multiplication, the state of the interrupted multiply or divide operation must be restored. The
MDRIU flag is the only portion of the MDC register which might be of interest for the user.
The remaining portions of the MDC register are reserved for dedicated use by the hardware,
and should never be modified by the user in another way than described above. Otherwise,
a correct continuation of an interrupted multiply or divide operation cannot be guaranteed.

A detailed description of how to use the MDC register for programming multiply and divide
algorithms can be found in Section 27: System programming on page 545.

3.4.16 The constant zeros register ZEROS

All bits of this bit-addressable register are fixed to '0' by hardware. This register is read only.
Register ZEROS can be used as a register-addressable constant of all zeros, for bit

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The central processing unit (CPU) UM0404

manipulation or mask generation. It can be accessed via any instruction which is capable of
addressing an SFR.

ZEROS (FF1Ch / 8Eh) SFR Reset Value: 0000h

1514131211109876543210

0000000000000000

RRRRRRRRRRRRRRRR

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UM0404 The central processing unit (CPU)

3.4.17 The constant ones register ONES

All bits of this bit-addressable register are fixed to '1' by hardware. This register is read only.
Register ONES can be used as a register-addressable constant of all ones, for bit
manipulation or mask generation. It can be accessed via any instruction which is capable of
addressing an SFR.

ONES (FF1Eh / 8Fh) SFR Reset Value:FFFFh

1514131211109876543210

1111111111111111

RRRRRRRRRRRRRRRR

Example

Mask for FFFFh values used to increment or decrement memory:

sub mem, ones ;mem=mem+1

;increments the memory location in one instruction
;instead of three, as described below

mov R13, mem ;mem -> R13

add R13, #1 ;R13 + 1

mov mem, R13 ;R13 -> mem

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Multiply-accumulate unit (MAC) UM0404

4 Multiply-accumulate unit (MAC)

The MAC is a specialized co-processor added to the ST10F276 CPU core to improve the
performance of signal processing algorithms. It includes:

• A multiply-accumulate unit.

• An address generation unit, able to feed the MAC unit with 2 operands per cycle.

• A repeat unit, to execute a series of multiply-accumulate instructions.

New addressing capabilities enable the CPU to supply the MAC with up to 2 operands per
instruction cycle. MAC instructions (multiply, multiply-accumulate, 32-bit signed arithmetic
operations and the CoMOV transfer instruction) have been added to the standard instruction
set. Full details are provided in the ST10 Family Programming Manual.

4.1 MAC features

Enhanced addressing capabilities

• Double indirect addressing mode with pointer post-modification.

• Parallel Data Move allowing one operand move during Multiply-Accumulate

instructions without penalty.

• CoSTORE instruction (for fast access to the MAC SFRs) and CoMOV (for fast memory
to memory table transfer).

General

• Two-cycle execution for all MAC operations.

• 16 x 16 signed/unsigned parallel multiplier.

• 40-bit signed arithmetic unit with automatic saturation mode.

• 40-bit accumulator.

• 8-bit left/right shifter.

• Scaler (one-bit left shifter)

• Data limiter

• Full instruction set with multiply and multiply-accumulate, 32-bit signed arithmetic and

compare instructions.

• Three 16-bit status and control registers (MSW: MAC Status Word, MCW: MAC Control
Word, MRW: MAC Repeat Word).

The working register of the MAC Unit is a dedicated 40-bit wide Accumulator register. A set
of consistent flags is automatically updated in the MSW register (see Section 4.3.2:

Accumulator & control registers on page 91) after each MAC operation. These flags allow

branching on specific conditions. Unlike the PSW flags, these flags are not preserved
automatically by the CPU upon entry into an interrupt or trap routine.

Note: All dedicated MAC registers must be saved on the stack if the MAC unit is shared

between different tasks and interrupts.

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UM0404 Multiply-accumulate unit (MAC)

Operand 2Operand 1

Control Unit

Repeat Unit

ST10 CPU

Interrupt

Controller

MSW

MRW

MAH MAL

MCW

Flags MAE

Mux

8-bit Left/Right

Shifter

Mux

Mux

Sign Extend

16 x 16

Concatenation

signed/unsigned

Multiplier

40-bit Signed Arithmetic Unit

0h 0h08000h

40

16

40 40

32 32

16

40

40

40

40

40

Scaler

AB

40

GPR Pointers *

IDX0 Pointer
IDX1 Pointer

QR0 GPR Offset Register
QR1 GPR Offset Register

QX0 IDX Offset Register
QX1 IDX Offset Register

Data

Limiter

(MA-bus) (MB-bus)

Program control

• Repeat Unit allowing some MAC co-processor instructions to be repeated up to 8192
times. Repeated instructions may be interrupted.

• MAC interrupt (Class B Trap) on MAC condition flags.

4.2 MAC operation

Figure 16. MAC architecture

1. * Shared with standard ALU.

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Multiply-accumulate unit (MAC) UM0404

4.2.1 Instruction pipelining

All MAC instructions use the 4-stage pipeline. During each stage the following tasks are
performed:

• FETCH: All new instructions are double-word instructions.

• DECODE: If required, operand addresses are calculated and the resulting operands

are fetched. IDX and GPR pointers are post-modified if necessary.

• EXECUTE: Performs the MAC operation. At the end of the cycle, the Accumulator and
the MAC condition flags are updated if required. Modified GPR pointers are written­back during this stage, if required.

• WRITEBACK: Operand write-back in the case of parallel data move.

4.2.2 Particular pipeline effects with the MAC unit

Because the registers used by the MAC are shared with the standard ALU and because of
the MAC instructions pipelining, some care must be taken when switching from the
‘standard instruction set’ to the ‘MAC instruction set’.

Initialization of the pointers and offset regist ers

The new MAC instructions which use IDXi pointers is mostly not capable of using a new IDXi
register value, which is to be updated by an immediately preceding instruction. Thus, to
make sure that the new IDX
between a IDX

-changing instruction and one MAC instruction which explicitly uses IDXi in

i

its addressing mode as shown in the following example:

MOV IDX0,

In:

#0F200h

register value is used, at least one instruction must be inserted

i

; update IDX0 register

I

: ... ; must not be a CoXXX [IDX0⊗], [Rwm⊗] instruction

n+1

CoXXX

:

I

n+2

[IDX0+QX1], [R2]

Same requirements between the update of one of the offset reg. QX

; first operand read at (IDX0) address to provide the MAC function

; parallel data move to (((IDX0))-((QX1))) address (if CoXXX is
CoMACM)

; move (R2) content to (IDX0) address (if CoXXX is CoMOV)

; (IDX0) <-- (IDX0) + (QX1) post modification of the pointer

& QRi and their next

i

use.

Read Access to MAC registers (CoReg)

At least one instruction which does not use the MAC must be inserted between a MAC
instruction (CoXXX) writing to a MAC register (MAH, MAL, MSW, MRW, MCW) and a
standard instruction reading this register. This is because the accumulator and the status of
the MAC are modified during the execute stage.

Example 1

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UM0404 Multiply-accumulate unit (MAC)

Code MSW (before) MSW (after) Comment

MOV MSW, #0 - 0000h

MOV R0, #0 - -

CoADD R0, R0 0000h 0200h MSW.Z set at execute

BFLDL MSW, #FFh, #FFh 0200h 00FFh Error!

In this example, the BFLDL instruction performs a read access to the MSW during the
decode stage while the MSW.Z flag is only set at the end of the execute stage of the
CoADD.

4.2.3 Address generation

MAC instructions can use some standard ST10 addressing modes such as GPR direct or
#data4 for immediate shift value.

New addressing modes have been added to supply the MAC with two new operands per
instruction cycle. These allow indirect addressing with address pointer post-modification.

Double indirect addressing requires two pointers. Any GPR can be used for one pointer, the
other pointer is provided by one of two specific SFRs IDX0 and IDX1. Two pairs of offset
registers QR0/QR1 and QX0/QX1 are associated with each pointer (GPR or IDX
pointer allows access to the entire memory space, but IDX

are limited to the internal IRAM,

i

except for the CoMOV instruction.

). The GPR

i

The following table shows the various combinations of pointer post-modification for each of
these two new addressing modes. In this document the symbols “[Rw

⊗]” and “[IDXi⊗]”

n

refer to these addressing modes.

“[IDX

“[Rw

Table 10. Pointer post-modification combinations for IDXi and Rwn

Symbol Mnemonic Address pointer operation

⊗]” stands for

i

⊗]” stands for

n

](IDX

[IDX

i

[IDX

+](IDX

i

-] (IDXi) ← (IDXi) -2 (i = 0,1)

[IDX

i

[IDX

+ QXj](IDX

i

[IDX

- QXj](IDX

i

[Rw

](Rw

n

[Rw

+](Rw

n

[Rw

-] (Rwn) ← (Rwn) -2 (k = 0-15)

n

[Rwn+QRj](Rw

[Rw

- QRj](Rw

n

) ← (IDXi) (no-op)

i

) ← (IDXi) +2 (i = 0,1)

i

) ← (IDXi) + (QXj) (i, j = 0,1)

i

) ← (IDXi) - (QXj) (i, j = 0,1)

i

) ← (Rwn) (no-op)

n

) ← (Rwn) +2 (n = 0-15)

n

) ← (Rwn) + (QRj) (n = 0-15; j = 0,1)

n

) ← (Rwn) - (QRj) (n = 0-15; j = 0,1)

n

For the CoMACM class of instruction, Parallel Data Move mechanism is implemented. This
class of instruction is only available with double indirect addressing mode. Parallel Data
Move allows the operand pointed by IDX

to be moved to a new location in parallel with the

i

MAC operation. The write-back address of Parallel Data Move is calculated depending on

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Multiply-accumulate unit (MAC) UM0404

CoMACM [IDX0+], [R2+]

X

n+2

n

n-2

n-4

16-bit

IDX0 X

X

n+2

n

n-2

n-4

IDX0

Parallel Data Move

After ExecutionBefore Execution

the post-modification of IDXi. It is obtained by the reverse operation than the one used to
calculate the new value of IDX

Instruction Writeback address

. The following table shows these rules.

i

Table 11. Parallel data move addressing

CoMACM [IDX

CoMACM [IDX

+],... <IDXi-2>

i

-],... <IDXi+2>

i

CoMACM [IDXi+QXj],... <IDXi-QXj>

CoMACM [IDX

-QXj],... <IDXi+QXj>

i

The Parallel Data Move shifts a table of operands in parallel with a computation on those
operands. Its specific use is for signal processing algorithms like filter computation. The
following figure gives an example of Parallel Data Move with CoMACM instruction.

Figure 17. Example of parallel data move

4.2.4 16 x 16 signed/unsigned parallel multiplier

The multiplier executes 16 x 16-bit parallel signed/unsigned fractional and integer multiplies.
The multiplier has two 16-bit input ports, and a 32-bit product output port. The input ports
can accept data from the MA-bus and from the MB-bus. The output is sign-extended and
then feeds a scaler that shifts the multiplier output according to the shift mode bit MP
specified in the co-processor Control Word (MCW). The product can be shifted one bit left to
compensate for the extra sign bit gained in multiplying two 16-bit signed (2’s complement)
fractional numbers if bit MP is set.

4.2.5 40-bit signed arithmetic unit

The arithmetic unit over 32-bit wide to allow intermediate overflow in a series of
multiply/accumulate operations. The extension flag E, contained in the most significant byte
of MSW, is set when the Accumulator has overflowed beyond the 32-bit boundary, that is,
when there are significant (non-sign) bits in the top eight (signed arithmetic) bits of the
Accumulator.

The 40-bit arithmetic unit has two 40-bit input ports A and B. The A-input port accepts data

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from four possible sources: 00’0000’0000h, 00’0000’8000h (round), the sign-extended
product, or the sign-extended data conveyed by the 32-bit bus resulting from the

UM0404 Multiply-accumulate unit (MAC)

concatenation of MA- and MB-buses. Product and Concatenation can be shifted left by one
according to MP for the multiplier or to the instruction for the concatenation. The B-input port
is fed either by the 40-bit shifted/not shifted and inverted/not inverted accumulator or by
00’0000’0000h. A-input and B-input ports can receive 00’0000’0000h to allow direct
transfers from the B-source and A-source, respectively, to the Accumulator (case of
Multiplication and Shift). The output of the arithmetic unit goes to the Accumulator.

It is also possible to saturate the Accumulator on a 32-bit value, automatically after every
accumulation. Automatic saturation is enabled by setting the saturation bit MS in the MCW
register. When the Accumulator is in the saturation mode and a 32-bit overflow occurs, the
accumulator is loaded with either the most positive or the most negative value representable
in a 32-bit value, depending on the direction of the overflow. The value of the Accumulator
upon saturation is 00’7FFF’FFFFh (positive) or FF’8000’0000h (negative) in signed
arithmetic. Automatic saturation sets the SL flag MSW. This flag is a sticky flag which means
it stays set until it is explicitly reset by the user.

40-bit overflow of the Accumulator sets the SV flag in MSW. This flag is also a sticky flag.

4.2.6 The 40-bit signed accumulator register

The 40-bit accumulator consists of three smaller registers, MAL, MAH, and MAE. MAH and
MAL are 16-bit wide, MAE is 8-bit wide. MAE is the most significant byte (MSB) of the 40-bit
accumulator, however it is accessed as the least significant byte (LSB) of the MSW register
and performs guarding function.

On MAH write operations, the value of the accumulator is automatically adjusted to signed
extended 40-bit format. This means:

• MAE is automatically loaded by zeros for positive numbers (MAH has 0 in the most
significant bit). In case the of a negative number (MAH has 1 in the most significant bit)
the MAE is loaded with ones, representing the extended 40-bit negative number in 2’s
complement notation. Then the extended 40-bit value is equal to the 32-bit value
without extension. In other words, after this extension, MAE does not contain significant
bits. Generally, this condition is present when the highest 9 bits of the 40-bit signed
result are the same.

• MAL is automatically loaded with zeros.

During the 40-bit accumulator operations the result may be greater than 32 bits and
therefore, the MAE content changes. The MSW.ME extension flag is set because the signed
result of the 40-bit accumulator has overflown the 32-bit boundary. This condition is right
when the highest 9 bits of the 40-bit signed result are not the same. This also means that
MAE contains significant bits.

Note: Most of the CoXXX operations specify the 40-bit accumulator register as a source or a

destination operand. Operands loaded in 32-bit format are extended to 40-bit signed
numbers with MAE equal to 00h (for positive numbers) or FFh (for negative numbers).

Because writing to MAH forces zero value in MAL and sign extension in MAE, MAH must be
written first and MAL second. Some care must be taken in the order these registers are
handled, for example in saving status stacking as shown in the following example:

PUSH MSW
PUSH MAL
PUSH MAH ; Last one because later impact on MAE, MAL

POP MAH ; First one because impact on MAE, MAL

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Multiply-accumulate unit (MAC) UM0404

POP MAL
POP MSW

4.2.7 The 40-bit adder / subtracter

The 40-bit Adder/Subtracter allows intermediate overflows in a series of multiply/accumulate
operations. The Adder/Subtracter has two input ports. One input is the feedback of the 40­bit Signed Accumulator output through the ACCU-Shifter. The second input is the 32-bit
operand coming from the One-bit Scaler. The 32-bit operands are sign-extended to 40-bit
before the addition/subtraction is performed.

The output of the Adder/Subtracter goes to the 40-bit Signed Accumulator. It is also possible

to round and to saturate the result to 32-bit automatically after every accumulation before to
be loaded into the accumulator. The round operation is performed by adding 00’0000’8000h

to the result. Automatic saturation is enabled by setting the MCW.MS saturation bit.

When the 40-bit Signed Accumulator is in the overflow saturation mode and an overflow
occurs, the accumulator is loaded with either the most positive or the most negative possible
32-bit value, depending on the direction of the overflow as well as the arithmetic used. The
value of the accumulator upon saturation is 00’7FFF’FFFFh (positive) or FF’8000’0000h
(negative).

4.2.8 Data limiter

Saturation arithmetic is also provided to selectively limit overflow, when reading the
accumulator by means of a ‘CoSTORE <destination> <MAS> instruction’. Limiting is
performed on the MAC Accumulator. If the contents of the Accumulator can be represented
in the destination operand size without overflow, the data limiter is disabled and the operand
is not modified. If the contents of the accumulator cannot be represented without overflow in
the destination operand size, the limiter will substitute a ‘limited’ data as explained in the
following table.

ME-flag MN-flag MAS value (saturated MAH value)

0 x Unchanged

1 0 7FFFh

1 1 8000h

Table 12. Limiter output using CoSTORE instruction

3

1

2

2

Note: 1 When data limiter is disabled, a reading with ‘CoSTORE <destination>, <MAH> instruction’

or ‘CoSTORE <destination>, <MAS> instruction’ gives the same result

2 If data limiter is activated, a read with ‘CoSTORE <destination>, <MAH> instruction’ or

‘CoSTORE <destination>, <MAS> instruction’ gives different results. MAS gives the
saturated value of MAH. The reading of MAL and MSW (MAE) are not saturated.

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UM0404 Multiply-accumulate unit (MAC)

4.2.9 The accumulator shifter

The accumulator shifter is a parallel shifter with a 40-bit input and a 40-bit output. The
source accumulator shifting operations are:

• No shift (Unmodified)

• Up to 8-bit Arithmetic Left Shift

• Up to 8-bit Arithmetic Right Shift

Notice that MSW.ME, MSW.MSV and MSW.MSL bits (see MSW register description) are
affected by left shifts, therefore, if the saturation detection is enabled (MCW.MS bit is set),
the behavior is similar to the one of the Adder/Subtracter.

Some precautions are required in case of left shift with enabled saturation. If

MSW.MAE bit-field (most significant byte of the 40-bit Signed Accumulator) contains
significant bits, then the 32-bit value in the accumulator is generally saturated. However, it is
possible that a left shift may move out of the Accumulator some significant bits. The 40-bit
result will be misinterpreted and will be either not saturated or saturated wrong. There is a
chance that the result of a left shift may produce a result which can saturate an original
positive number to the minimum negative value, or vice versa.

4.2.10 Repeat unit

The MAC includes a repeat unit allowing the repetition of some co-processor instructions up

13

(8192) times. The repeat count may be specified either by an immediate value (up to

to 2
31 times) or by the content of the Repeat Count (bits 12 to 0) in the MAC Repeat Word
(MRW). If the Repeat Count equals “N” the instruction will be executed “N+1” times. At each
iteration of a cumulative instruction the Repeat Count is tested for zero. If it is zero the
instruction is terminated else the Repeat Count is decremented and the instruction is
repeated. During such a repeat sequence, the Repeat Flag in MRW is set until the last
execution of the repeated instruction.

The syntax of repeated instructions is shown in the following examples:

1 Repeat #24 times

CoMAC[IDX0+],[R0+] ; repeated 24 times

In example 1, the instruction is repeated according to a 5-bit immediate value. The Repeat
Count in MRW is automatically loaded with this value minus one (MRW=23).

2 MOV MRW, #00FFh ; load MRW with 255

NOP ; instruction latency

Repeat MRW times

CoMACM [IDX1-],[R2+] ; repeated 256 times

In this second example, the instruction is repeated according to the Repeat Count in MRW.
Notice that due to the pipeline processing at least one instruction should be inserted
between the write of MRW and the next repeated instruction.

Repeat sequences may be interrupted. When an interrupt occurs during a repeat sequence,
the sequence is stopped and the interrupt routine is executed. The repeat sequence
resumes at the end of the interrupt routine. During the interrupt, MR remains set, indicating
that a repeated instruction has been interrupted and the Repeat Count holds the number
(minus 1) of repetition that remains to complete the sequence. If the Repeat Unit is used in

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Multiply-accumulate unit (MAC) UM0404

N

N

N

I1

I1

N

N+2

N+1

N-1

N-1

N-2

N-3

N+1

N-1

N-2

N+4

TRAP (1)

N+2

N+1

TRAP (1)

N+2

I2

TRAP (2)

TRAP (1)

N+3

N+2

N+1

FETCH
DECODE

EXECUTE
WRITEBACK

MAC Interrupt Request

Response Time

TRAP (2)

the interrupt routine, MRW must be saved by the user and restored before the end of the
interrupt routine.

Note: The Repeat Count should be used with caution. In this case MR should be written as 0. In

general MR should not be set by the user otherwise correct instruction processing cannot be
guaranteed.

4.2.11 MAC interrupt

The MAC can generate an interrupt according to the value of the status flags C (carry), SV
(overflow), E (extension) or SL (limit) of the MSW register. The MAC interrupt is globally
enabled when the MIE flag in MCW is set. When it is enabled, the flags C, SV, E or SL can
trigger a MAC interrupt whenever they are set, provided that the corresponding mask flag
CM, VM, EM or LM in MCW is also set. A MAC interrupt request sets the MIR flag in MSW:
this flag must be reset by the user during the interrupt routine, otherwise the interrupt
processing restarts when returning from the interrupt routine.

The MAC interrupt is implemented as a Class B hardware trap (trap number Ah - trap
priority I). The associated Trap Flag in the TFR register is MACTRP, bit #6 of the TFR
(remember that this flag must also be reset by the user in case of a MAC interrupt request).

As the MAC status flags are updated (or eventually written by software) during the Execute
stage of the pipeline, the response time of a MAC interrupt request is three instruction
cycles (see Figure 18). It is the number of instruction cycles required between the time the
request is sent and the time the first instruction located at the interrupt vector location enters
the pipeline. Note that the IP value stacked after a MAC interrupt does not point to the
instruction that triggers the interrupt.

Figure 18. Pipeline diagram for MAC interrupt response time

4.2.12 Number representation & rounding

The MAC supports the 2’s-complement representation of binary numbers. In this format, the
sign bit is the MSB of the binary word. This is set to zero for positive numbers and set to one
for negative numbers. Unsigned numbers are supported only by multiply/multiply­accumulate instructions which specifies whether each operand is signed or unsigned.

In 2’s complement fractional format, the N-bit operand is represented using the 1.[N-1]
format (1 signed bit, N-1 fractional bits). Such a format can represent numbers between -1
and +1-2

-[N-1]

. This format is supported when MP of MCW is set.

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UM0404 Multiply-accumulate unit (MAC)

The MAC implements ‘2’s complement rounding’. With this rounding type, one is added to
the bit to the right of the rounding point (bit 15 of MAL), before truncation (MAL is cleared).

4.3 MAC register set

4.3.1 Address registers

The new addressing modes require new (E)SFRs: Two address pointers IDX0 / IDX1 and
four offset registers QX0 / QX1 and QR0 / QR1.

IDX0 (FF08h / 84h) SFR Reset Value: 0000h
IDX1 (FF0Ah / 85h) SFR Reset Value: 0000h

1514131211109876543210

IDXy

RW

Bit Function

IDXy 16-bit IDXy address (y = 0, 1)

QX0 (F000h / 00h) ESFR Reset Value: 0000h

QX1 (F002h / 01h) ESFR Reset Value: 0000h
QR0 (F004h / 02h) ESFR Reset Value: 0000h
QR1 (F006h / 03h) ESFR Reset Value: 0000h

1514131211109876543210

QXz/QRz 0

Bit Function

16-bit address offset for IDXy pointers (QXz) or GPR pointers (QRz).

QRz/QXz

As MAC instructions handle word operands, bit 0 of these offset registers is
hardwired to ‘0’.

4.3.2 Accumulator & control registers

The MAC unit SFRs include the 40-bit Accumulator (MAL, MAH and the low byte of MSW)
and three control registers: the status word MSW, the control word MCW and the repeat
word MRW.

MAH and MAL are located in the non bit-addressable SFR space.

MAH (FE5Eh / 2Fh) SFR Reset Value: 0000h

1514131211109876543210

RW R

MAH

RW

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Multiply-accumulate unit (MAC) UM0404

Bit Function

MAH MAC Unit Accumulator High (bits [31...16])

MAL (FE5Ch / 2Eh) SFR Reset Value: 0000h

1514131211109876543210

MAL

RW

Bit Function

MAL MAC Unit Accumulator Low (bits [15...0])

MSW (FFDEh / EFh) SFR Reset Value: 0200h

1514131211109876543210

MIR - SL E SV C Z N MAE

R RWRWRWRWRWRW RW

Bit Function

MAE Accumulator Extension (bits [39:32])

N

Z

C

Negative Flag

Set when the Accumulator is negative at the end of a MAC operation.

Zero Flag

Set when the Accumulator is zero at the end of a MAC operation.

Carry Flag

Set when a MAC operation produces a carry or a borrow bit.

Sticky Overflow Flag

SV

Set when a MAC operation produces a 40-bit arithmetic overflow. It remains set until
it is explicitly reset by software.

E

Extension Flag

Set when MAE contains significant bits at the end of a MAC operation

Sticky Limit Flag

SL

Set when the result of a MAC operation is automatically saturated. Also used for
CoMIN, CoMAX instructions to indicate that the Accumulator has changed. It
remains set until it is explicitly reset by software.

MIR

MAC Interrupt Request

Set when the MAC Unit generates an interrupt request.

Note: The MAC condition flags are evaluated if required by the instruction being executed. In

particular they are not affected by any instruction of the regular instruction set. In
consequence, their values may not be consistent with the Accumulator content. For
example, loading the Accumulator with MOV instructions will not modify the condition flags.

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UM0404 Multiply-accumulate unit (MAC)

MCW (FFDCh / EEh) SFR Reset Value: 0000h

1514131211109876543210

MIE LM EM VM CM MP MS -

RW RW RW RW RW RW RW

Bit Function

MS

Saturation Mode

When set, enables automatic 32-bit saturation of the result of a MAC operation.

Product Shift Mode

MP

When set, enables the one-bit left shift of the multiplier output in case of a signed­signed multiplication.

CM

VM

EM

LM

C Mask

When set, the C Flag can generate a MAC interrupt request.

SV Mask

When set, the SV Flag can generate a MAC interrupt request.

E Mask

When set, the E Flag can generate a MAC interrupt request.

SL Mask

When set, the SL Flag can generate a MAC interrupt request.

MAC Interrupt Enable

MIE

‘0’: MAC interrupt globally disabled.
‘1’: MAC interrupt globally enabled.

MRW (FFDAh / EDh) SFR Reset Value: 0000h

1514131211109876543210

MR - - Repeat Count

RW RW

Bit Function

Repeat Count

MR

13-bit unsigned integer value

Indicates the number of time minus one a repeated instruction must be executed.

Repeat Flag

Set when a repeated instruction is executed.

Note: As for the CPU Core SFRs, any write operation with the regular instruction set to a single

byte of a MAC SFR clears the non-addressed complementary byte within the specified SFR.
Non-implemented SFR bits cannot be modified and will always supply a read value of ‘0’.

These registers are mapped in the SFR space and can be addressed by the regular
instruction set like any SFR. As mentioned previously, they can also be addressed by the
new instruction CoSTORE. This instruction allows the user to access the MAC registers
without any pipeline side effect. CoSTORE uses a specific 5-bit addressing mode called
CoReg. The following table gives the address of the MAC registers in this CoReg
addressing mode.

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Multiply-accumulate unit (MAC) UM0404

Table 13. MAC register address in CoReg addressing mode

Registers Description Address

MSW MAC-Unit Status Word 00000b

MAH MAC-Unit Accumulator High 00001b

MAS “limited” MAH /signed 00010b

MAL MAC-Unit Accumulator Low 00100b

MCW MAC-Unit Control Word 00101b

MRW MAC-Unit Repeat Word 00110b

4.4 MAC instruction set summary

The following table gives an overview of the MAC instruction set. All the mnemonics are
listed with the addressing modes that can be used with each instruction.
For each combination of mnemonic and addressing mode this table indicates if it is
repeatable or not.

For full details of the MAC instruction set, refer to the ST10 Family Programming Manual.

Mnemonic Addressing modes Repeatable

Table 14. MAC instruction set summary

Rwn, Rwm

CoMUL(u,s,-,rnd)

[IDXi⊗], [Rwm⊗]
Rwn, [Rwm⊗]

CoMAC(u, s, -, rnd)
CoMACR( u, s, rnd)

CoMACM (u, s, -, rnd)
CoMACMR(u, s, rnd)

Rw
[IDXi⊗], [Rwm⊗]
Rw

[IDX

[Rw

CoNOP

[IDX
[IDX

CoNEG
CoNEG, rnd

-No

CoRND

CoSTORE

Rw
[Rwn⊗], Coreg

CoMOV [IDX

CoADD(2)
CoSUB(2)
CoSUB(2)R
CoMax

Rw
[IDXi⊗], [Rwm⊗]
Rw

CoMin

, Rwm

n

, [Rwm⊗]

n

⊗], [Rwm⊗] Yes

i

⊗]

m

⊗]

i

⊗], [Rwm⊗]

i

, CoReg

n

⊗], [Rwm⊗] Yes

i

, Rw

n

m

, [Rwm⊗]

n

No

No
Yes
Yes

Yes

No
Yes

No
Yes
Yes

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UM0404 Multiply-accumulate unit (MAC)

Table 14. MAC instruction set summary (continued)

Mnemonic Addressing modes Repeatable

CoLOAD( 2, -)
CoCMP

CoSHL
CoSHR
CoASHR
CoASHR, rnd

CoABS

Rwn, Rw

m

[IDXi⊗], [Rwm⊗]
Rw

, [Rwm⊗]

n

Rw

m

#data4
[Rwm⊗]

­Rw

, Rw

n

m

[IDXi⊗], [Rwm⊗]
Rwn, [Rwm⊗]

No

Yes
No
Yes

No

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Interrupt and trap functions UM0404

5 Interrupt and trap functions

The architecture of the ST10F276 supports several mechanisms for fast and flexible
response to service requests that can be generated from various sources internal or
external to the microcontroller. These mechanisms include:

• Normal interrupt processing: The CPU temporarily suspends the current program

execution and branches to an interrupt service routine in order to service an interrupt
requesting device. The current program status (IP, PSW, in segmentation mode also
CSP) is saved on the internal system stack. A prioritization scheme with 16 priority
levels allows the user to specify the order in which multiple interrupt requests are to be
handled.

• Interrupt processing via the peripheral event controller (PEC): A faster alternative

to normal software controlled interrupt processing is servicing an interrupt requesting
device with the ST10F276's integrated Peripheral Event Controller (PEC). Triggered by
an interrupt request, the PEC performs a single word or byte data transfer between any
two locations in segment 0 (data pages 0 through 3) through one of eight
programmable PEC Service Channels. During a PEC transfer the normal program
execution of the CPU is halted for just 1 instruction cycle. No internal program status
information needs to be saved. The same prioritization scheme is used for PEC service
as for normal interrupt processing. PEC transfers share the two highest priority levels.

• Trap functions: Trap functions are activated in response to special conditions that

occur during the execution of instructions. A trap can also be caused externally by the
Non-Maskable Interrupt pin NMI
handling erroneous conditions and exceptions that arise during the execution of an
instruction. Hardware traps always have highest priority and cause immediate system
reaction. The software trap function is invoked by the TRAP instruction, which
generates a software interrupt for a specified interrupt vector. For all types of traps the
current program status is saved on the system stack.

• External interrupt processing: Although the ST10F276 does not provide dedicated

interrupt pins, it allows to connect external interrupt sources and provides several
mechanisms to react on external events, including standard inputs, non-maskable
interrupts and fast external interrupts. These interrupt functions are alternate port
functions, except for the non-maskable interrupt and the reset input.

. Several hardware trap functions are provided for

5.1 Interrupt system structure

The ST10F276 provides 56 separate interrupt nodes that may be assigned to 16 priority
levels. In order to support modular and consistent software design techniques, each source
of an interrupt or PEC request is supplied with a separate interrupt control register and
interrupt vector.

The control register contains the interrupt request flag, the interrupt enable bit, and the
interrupt priority of the associated source. Each source request is activated by one specific
event, depending on the selected operating mode of the respective device.

The only exceptions are the two serial channels of the ST10F276, where an error interrupt
request can be generated by different kinds of error. However, specific status flags which
identify the type of error are implemented in the serial channels’ control registers.

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The ST10F276 provides a vectored interrupt system. In this system specific vector locations
in the memory space are reserved for the reset, trap, and interrupt service functions.

Whenever a request occurs, the CPU branches to the location that is associated with the
respective interrupt source.

This allows direct identification of the source that caused the request. The only exceptions
are the class B hardware traps, which all share the same interrupt vector.

The status flags in the Trap Flag Register (TFR) can then be used to determine which
exception caused the trap. For the special software TRAP instruction, the vector address is
specified by the operand field of the instruction, which is a seven bit trap number.

The reserved vector locations build a jump table in the low end of the ST10F276’s address
space (segment 0).

The jump table is made up of the appropriate jump instructions that transfer control to the
interrupt or trap service routines, which may be located anywhere within the address space.

The entries of the jump table are located at the lowest addresses in code segment 0 of the
address space. Each entry occupies 2 words, except for the reset vector and the hardware
trap vectors, which occupy 4 or 8 words.

The Tabl e 15 lists all sources that are capable of requesting interrupt or PEC service in the
ST10F276, the associated interrupt vectors, their locations and the associated trap
numbers. It also lists the mnemonics of the affected Interrupt Request flags and their
corresponding Interrupt Enable flags. The mnemonics are composed of a part that specifies
the respective source, followed by a part that specifies their function (IR = Interrupt Request
flag, IE = Interrupt Enable flag).

Each entry of the interrupt vector table provides room for two word instructions or one
double-word instruction. The respective vector location results from multiplying the trap
number by 4 (4 bytes per entry).

Source of interrupt or

PEC service request

CAPCOM Register 0 CC0IR CC0IE CC0INT 00’0040h 10h

CAPCOM Register 1 CC1IR CC1IE CC1INT 00’0044h 11h

CAPCOM Register 2 CC2IR CC2IE CC2INT 00’0048h 12h

CAPCOM Register 3 CC3IR CC3IE CC3INT 00’004Ch 13h

CAPCOM Register 4 CC4IR CC4IE CC4INT 00’0050h 14h

CAPCOM Register 5 CC5IR CC5IE CC5INT 00’0054h 15h

CAPCOM Register 6 CC6IR CC6IE CC6INT 00’0058h 16h

CAPCOM Register 7 CC7IR CC7IE CC7INT 00’005Ch 17h

CAPCOM Register 8 CC8IR CC8IE CC8INT 00’0060h 18h

CAPCOM Register 9 CC9IR CC9IE CC9INT 00’0064h 19h

CAPCOM Register 10 CC10IR CC10IE CC10INT 00’0068h 1Ah

CAPCOM Register 11 CC11IR CC11IE CC11INT 00’006Ch 1Bh

T able 15. Interrupt and PEC service request sources

Request

flag

Enable

flag

Interrupt

vector

Vector

location

Trap

number

CAPCOM Register 12 CC12IR CC12IE CC12INT 00’0070h 1Ch

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Table 15. Interrupt and PEC service request sources (continued)

Source of interrupt or

PEC service request

CAPCOM Register 13 CC13IR CC13IE CC13INT 00’0074h 1Dh

CAPCOM Register 14 CC14IR CC14IE CC14INT 00’0078h 1Eh

CAPCOM Register 15 CC15IR CC15IE CC15INT 00’007Ch 1Fh

CAPCOM Register 16 CC16IR CC16IE CC16INT 00’00C0h 30h

CAPCOM Register 17 CC17IR CC17IE CC17INT 00’00C4h 31h

CAPCOM Register 18 CC18IR CC18IE CC18INT 00’00C8h 32h

CAPCOM Register 19 CC19IR CC19IE CC19INT 00’00CCh 33h

CAPCOM Register 20 CC20IR CC20IE CC20INT 00’00D0h 34h

CAPCOM Register 21 CC21IR CC21IE CC21INT 00’00D4h 35h

CAPCOM Register 22 CC22IR CC22IE CC22INT 00’00D8h 36h

CAPCOM Register 23 CC23IR CC23IE CC23INT 00’00DCh 37h

CAPCOM Register 24 CC24IR CC24IE CC24INT 00’00E0h 38h

CAPCOM Register 25 CC25IR CC25IE CC25INT 00’00E4h 39h

CAPCOM Register 26 CC26IR CC26IE CC26INT 00’00E8h 3Ah

CAPCOM Register 27 CC27IR CC27IE CC27INT 00’00ECh 3Bh

CAPCOM Register 28 CC28IR CC28IE CC28INT 00’00E0h 3Ch

CAPCOM Register 29 CC29IR CC29IE CC29INT 00’0110h 44h

Request

flag

Enable

flag

Interrupt

vector

Vector

location

Trap

number

CAPCOM Register 30 CC30IR CC30IE CC30INT 00’0114h 45h

CAPCOM Register 31 CC31IR CC31IE CC31INT 00’0118h 46h

CAPCOM Timer 0 T0IR T0IE T0INT 00’0080h 20h

CAPCOM Timer 1 T1IR T1IE T1INT 00’0084h 21h

CAPCOM Timer 7 T7IR T7IE T7INT 00’00F4h 3Dh

CAPCOM Timer 8 T8IR T8IE T8INT 00’00F8h 3Eh

GPT1 Timer 2 T2IR T2IE T2INT 00’0088h 22h

GPT1 Timer 3 T3IR T3IE T3INT 00’008Ch 23h

GPT1 Timer 4 T4IR T4IE T4INT 00’0090h 24h

GPT2 Timer 5 T5IR T5IE T5INT 00’0094h 25h

GPT2 Timer 6 T6IR T6IE T6INT 00’0098h 26h

GPT2 CAPREL Register CRIR CRIE CRINT 00’009Ch 27h

A/D Conversion Complete ADCIR ADCIE ADCINT 00’00A0h 28h

A/D Overrun Error ADEIR ADEIE ADEINT 00’00A4h 29h

ASC0 Transmit S0TIR S0TIE S0TINT 00’00A8h 2Ah

ASC0 Transmit Buffer S0TBIR S0TBIE S0TBINT 00’011Ch 47h

ASC0 Receive S0RIR S0RIE S0RINT 00’00ACh 2Bh

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Table 15. Interrupt and PEC service request sources (continued)

Source of interrupt or

PEC service request

ASC0 Error S0EIR S0EIE S0EINT 00’00B0h 2Ch

SSC Transmit SSCTIR SSCTIE SSCTINT 00’00B4h 2Dh

SSC Receive SSCRIR SSCRIE SSCRINT 00’00B8h 2Eh

SSC Error SSCEIR SSCEIE SSCEINT 00’00BCh 2Fh

PWM Channel 0...3 PWMIR PWMIE PWMINT 00’00FCh 3Fh

See Section 5.7 XP0IR XP0IE XP0INT 00’0100h 40h

See Section 5.7 XP1IR XP1IE XP1INT 00’0104h 41h

See Section 5.7 XP2IR XP2IE XP2INT 00’0108h 42h

See Section 5.7 XP3IR XP3IE XP3INT 00’010Ch 43h

Exception condition

RESET Functions:
Hardware RESET

Software RESET
Watchdog Timer Overflow

Request

flag

Enable

flag

Interrupt

vector

Vector

location

Table 16. Vector locations and status for hardware traps

Trap

flag

Trap

vector

RESET
RESET
RESET

Vector

location

00’0000h
00’0000h
00’0000h

Trap

number

00h
00h
00h

Trap

number

Trap

priority

MAXIMAL
III

III
III

Class A Hardware Traps:
Non-Maskable Interrupt

Stack Overflow
Stack Underflow

Class B Hardware Traps:
Undefined Opcode

MAC Interruption
Protected Instruction Fault
Illegal Word Operand Access
Illegal Instruction Access
Illegal External Bus Access

Reserved [2Ch –3Ch] [0Bh – 0Fh]

Software Traps
TRAP Instruction

NMI
STKOF
STKUF

UNDOPC
MACTRP
PRTFLT
ILLOPA
ILLINA
ILLBUS

NMITRAP
STOTRAP
STUTRAP

BTRAP
BTRAP
BTRAP
BTRAP
BTRAP
BTRAP

00’0008h
00’0010h
00’0018h

00’0028h
00’0028h
00’0028h
00’0028h
00’0028h
00’0028h

Any
[00’0000h–
00’01FCh]
in steps of
4h

02h
04h
06h

0Ah
0Ah
0Ah
0Ah
0Ah
0Ah

Any
[00h – 7Fh]

II
II
II

I
I
I
I
I
I minimal

Current
CPU
Priority

The Tab le 16 lists the vector locations for hardware traps and the corresponding status flags
in register TFR.

It also lists the priorities of trap service for cases, where more than one trap condition might
be detected within the same instruction.

After any reset (hardware reset, software reset instruction SRST, or reset by watchdog timer
overflow) program execution starts at the reset vector at location 00’0000h.

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Interrupt and trap functions UM0404

Reset conditions have priority over every other system activity and therefore have the
highest priority (trap priority III).

Software traps may be initiated to any vector location between 00’0000h and 00’01FCh. A
service routine entered via a software TRAP instruction is always executed on the current
CPU priority level which is indicated in bit-field ILVL in register PSW.

This means that routines entered via the software TRAP instruction can be interrupted by all
hardware traps or higher level interrupt requests.

5.1.1 Normal interrupt processing and PE C service

At each instruction cycle, among all the sources, which require a PEC or an interrupt
processing, only the one with the highest priority is selected. The priority of interrupts and
PEC requests is programmable in two levels. Each requesting source can be assigned to a
specific priority.

A second level (called “group priority”) allows to specify an internal order for simultaneous
requests from a group of different sources on the same priority level.

At the end of each instruction cycle the request with the highest current priority will be
determined by the interrupt system. The request will be serviced. If its priority is higher than
the current CPU priority which is stored in the register PSW.

5.1.2 Interrupt system register description

Interrupt processing is globally controlled by register PSW through a general interrupt
enable bit (IEN) and the CPU priority field (ILVL). Additionally the different interrupt sources
are individually controlled by their specific interrupt control registers (...IC).

Thus, the acceptance of requests by the CPU is determined by both the individual interrupt
control registers and the PSW. PEC services are controlled by the respective PECCx
register and the source and destination pointers, which specify the task of the respective
PEC service channel.

5.1.3 Interrupt control registers

All interrupt control registers are identically organized. The lower 8 bits of an interrupt
control register contain the complete interrupt status information of the associated source,
which is required during one round of prioritization, the upper 8 bits of the respective register
are reserved. All interrupt control registers are bit addressable and all bits can be read or
written via software.

This allows each interrupt source to be programmed or modified with just one instruction.
When accessing interrupt control registers through instructions which operate on word data
types, their upper 8 bits (15...8) will return zeros, when read, and will discard written data.

The layout of the Interrupt Control registers shown below applies to each xxIC register,
where xx stands for the mnemonic for the respective source.

xxIC (yyyyh / zzh) SFR Reset Value: - - 00h

1514131211109876543210

--------xxIR xxIE ILVL GLVL

RW RW RW RW

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