ST ST10F273M User Manual

ST10F273M

16-bit MCU with 512 Kbyte Flash memory and 36 Kbyte RAM

Features

■High performance 16-bit CPU with DSP functions

–50ns instruction cycle time at 40 MHz max CPU clock

–Multiply/accumulate unit (MAC) 16 x 16-bit multiplication, 40-bit accumulator

–Enhanced boolean bit manipulations

–Single-cycle context switching support

■Memory organization

–512 Kbyte on-chip Flash memory single voltage with erase/program controller (full performance, 32-bit fetch)

–100K erasing/programming cycles.

–Up to 16 Mbyte linear address space for code and data (5 Mbytes with CAN or I2C)

–2 Kbyte on-chip internal RAM (IRAM)

–34 Kbyte on-chip extension RAM (XRAM)

–Programmable external bus configuration and characteristics for different address ranges

–5 programmable chip-select signals

–Hold-acknowledge bus arbitration support

■Interrupt

–8-channel peripheral event controller for single cycle interrupt driven data transfer

–16-priority-level interrupt system with 56 sources, sampling rate down to 25ns

■Timers

–2 multifunctional general purpose timer units with 5 timers

■Two 16-channel capture / compare units

■4-channel PWM unit + 4-channel XPWM

PQFP144 (28 x 28 x 3.4mm)	LQFP144 (20 x 20 x 1.4mm)
(Plastic Quad Flat Package)	(Low Profile Quad Flat Package)

■24-channel A/D converter

–16-channel 10-bit, accuracy +/-2 LSB

–8-channel 10-bit, accuracy +/-5 LSB

–4.85µs Minimum conversion time

■Serial channels

–2 synch. / asynch. serial channels

–2 high-speed synchronous channels

–I2C standard interface

■2 CAN 2.0B interfaces operating on 1 or 2 CAN buses (64 or 2x32 messages, C-CAN version)

■Fail-safe protection

–Programmable watchdog timer

–Oscillator watchdog

■On-chip bootstrap loader

■Clock generation

–On-chip PLL and 4 to 12 MHz oscillator

–Direct or prescaled clock input

■Real time clock and 32 kHz on-chip oscillator

■Up to 111 general purpose I/O lines

–Individually programmable as input, output or special function

–Programmable threshold (hysteresis)

■Idle, power down and standby modes

■Single voltage supply: 5 V ±10% (embedded regulator for 1.8V core supply)

■Temperature range: -40 / +125 °C

July 2007

Rev 2

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Contents	ST10F273M

Contents

1	Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		11
	1.1	Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	11
	1.2	Special characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	11

1.2.1 X-Peripheral clock gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.2.2 Improved supply ring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2	Pin data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		13
3	Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		20
4	Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		21
5	Internal Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		27
	5.1	Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	27
	5.2	Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	27

5.2.1 Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.2.2 Module structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.2.3 Low power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

5.3 Write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.4 Flash control registers description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

5.4.1 Flash control register 0 low (FCR0L) . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.4.2 Flash control register 0 high (FCR0H) . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.4.3 Flash control register 1 low (FCR1L) . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.4.4 Flash control register 1 high (FCR1H) . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.4.5 Flash data register 0 low (FDR0L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.4.6 Flash data register 0 high (FDR0H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5.4.7 Flash data register 1 low (FDR1L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 5.4.8 Flash data register 1 high (FDR1H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 5.4.9 Flash address register low (FARL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 5.4.10 Flash address register high (FARH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5.4.11 Flash error register (FER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5.4.12 XFlash interface control dummy register (XFICR) . . . . . . . . . . . . . . . . . 39

5.5	Protection strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		39
	5.5.1	Protection registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	40

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5.5.2 Flash non-volatile write protection I register low (FNVWPIRL) . . . . . . . 40 5.5.3 Flash non-volatile write protection I register high (FNVWPIRH) . . . . . . 41

5.5.4Flash non-volatile write protection I register low Mirror (FNVWPIRL-m) 41

5.5.5Flash non-volatile write protection I register high Mirror (FVWPIRH-m) 41

5.5.6 Flash non-volatile access protection register 0 (FNVAPR0) . . . . . . . . . 42

5.5.7Flash non-volatile access protection register 1 low (FNVAPR1L) . . . . . 42

5.5.8Flash non-volatile access protection register 1 high (FNVAPR1H) . . . . 43

5.5.9 Access protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 5.5.10 Write protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 5.5.11 Temporary unprotection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

5.6 Write operation examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 5.7 Write operation summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

6	Bootstrap loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		48
	6.1	Selection among user-code, standard or selective bootstrap . . . . . . . . . .	48
	6.2	Standard bootstrap loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	48
	6.3	Alternate and selective boot mode (ABM and SBM) . . . . . . . . . . . . . . . .	49

6.3.1 Activation of the ABM and SBM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 6.3.2 User mode signature integrity check . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 6.3.3 Selective boot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

7	Central processing unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		50
	7.1	Multiplier-accumulator unit (MAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	51
	7.2	Instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	52
	7.3	MAC co-processor specific instructions . . . . . . . . . . . . . . . . . . . . . . . . . .	54
8	External bus controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		55
9	Interrupt system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		56
	9.1	X-Peripheral interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	58
	9.2	Exception and error traps list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	60
10	Capture / compare (CAPCOM) units . . . . . . . . . . . . . . . . . . . . . . . . . . .		61
11	General purpose timer unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		63
	11.1	GPT1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	63

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Contents				ST10F273M
	11.2	GPT2 .	. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . 65
12	PWM modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			. . . . . . 67
13	Parallel ports		. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . 68
	13.1	Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. . . . . . . 68
	13.2	I/O’s special features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. . . . . . 68
		13.2.1	Open drain mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . 68
		13.2.2	Input threshold control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . 69
	13.3	Alternate port functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. . . . . . 69
14	A/D converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			. . . . . . 71
15	Serial channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			. . . . . . 73

15.1 Asynchronous / synchronous serial interfaces . . . . . . . . . . . . . . . . . . . . . 73 15.2 ASCx in asynchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 15.3 ASCx in synchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 15.4 High speed synchronous serial interfaces . . . . . . . . . . . . . . . . . . . . . . . . 74

16	I2C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		76
17	CAN modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		77
	17.1	Configuration support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	77
	17.2	CAN bus configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	77

17.2.1 Single CAN bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 17.2.2 Multiple CAN bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 17.2.3 Parallel mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

18	Real time clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		80
19	Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		81
20	System reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		82
	20.1	Input filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	82
	20.2	Asynchronous reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	83
	20.3	Synchronous reset (warm reset) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	88

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20.4 Software reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 20.5 Watchdog timer reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 20.6 Bidirectional reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 20.7 Reset circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 20.8 Reset application examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 20.9 Reset summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

21	Power reduction modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		108
	21.1	Idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	108
	21.2	Power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	108

21.2.1 Protected power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 21.2.2 Interruptible power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

21.3 Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

21.3.1 Entering standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 21.3.2 Exiting standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 21.3.3 Real time clock and standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 21.3.4 Power reduction modes summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

22	Programmable output clock divider . . . . . . . . . . . . . . . . . . . . . . . . . .		113
23	Register set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		114
	23.1	Special function registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	114
	23.2	X-registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	121
	23.3	Flash registers ordered by name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	126
	23.4	Identification registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	126
24	Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		129

24.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 24.2 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 24.3 Power considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 24.4 Parameter interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 24.5 DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 24.6 Flash characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 24.7 A/D converter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

24.7.1 Conversion timing control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

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24.7.2 A/D conversion accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 24.7.3 Total unadjusted error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 24.7.4 Analog reference pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

24.8 AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		147
24.8.1	Test waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	147
24.8.2	Definition of internal timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	147
24.8.3	Clock generation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	148
24.8.4	Prescaler operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	149
24.8.5	Direct drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	149
24.8.6	Oscillator watchdog (OWD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	149
24.8.7	Phase locked loop (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	150
24.8.8	Voltage controlled oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	150
24.8.9	PLL jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	151
24.8.10	PLL lock / unlock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	153
24.8.11	Main oscillator specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	154
24.8.12	32 kHz oscillator specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	155
24.8.13	External clock drive XTAL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	156
24.8.14	Memory cycle variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	157
24.8.15	External memory bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	157
24.8.16	Multiplexed bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	157
24.8.17	Demultiplexed bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	164
24.8.18	CLKOUT and READY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	170
24.8.19	External bus arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	171
24.8.20	High-speed synchronous serial interface (SSC) timing . . . . . . . . . . . .	174

25	Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		177
	25.1	ECOPACK® . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	177
	25.2	Mechanical data and package dimensions . . . . . . . . . . . . . . . . . . . . . .	177
26	Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		180
27	Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		181

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ST10F273M	List of tables

List of tables

Table 1. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 2. Summary of IFlash address range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 3. Flash module address space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 4. Flash module sectorization (read operations). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 5. Flash module sectorization (write operations, or ROMS1 = ‘1’) . . . . . . . . . . . . . . . . . . . . . 29 Table 6. Flash control registers summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 7. FCR0L register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 8. FCR0H register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 9. FCR1L register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 10. FCR1H register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 11. Bank (BxS) and sectors (BxFy) status bits meaning. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 12. FDR0L register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 13. FDR0H register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 14. FDR1L register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 15. FDR1H register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 16. FARL register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 17. FARH register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 18. FER register bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 19. XFlash interface control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Table 20. FNVWPIRL register bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 21. FNVWPRIH register bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Table 22. FNVAPR0 register bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Table 23. FNVAPR1L register bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Table 24. FNVAPR1H register bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Table 25. Summary of access protection level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Table 26. Flash write operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Table 27. ST10F273M boot mode selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Table 28. Standard instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Table 29. MAC instruction set summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Table 30. Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Table 31. X-Interrupt detailed mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Table 32. Trap priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Table 33. Compare modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Table 34. CAPCOM timer input frequencies, resolutions and periods at 40 MHz . . . . . . . . . . . . . . . 62 Table 35. GPT1 timer input frequencies, resolutions and periods at 40 MHz. . . . . . . . . . . . . . . . . . . 63 Table 36. GPT2 timer input frequencies, resolutions and periods at 40 MHz. . . . . . . . . . . . . . . . . . . 65 Table 37. PWM unit frequencies and resolutions at 40 MHz CPU clock . . . . . . . . . . . . . . . . . . . . . . 67 Table 38. ASC asynchronous baudrates by reload value and deviation errors . . . . . . . . . . . . . . . . . 73 Table 39. ASC synchronous baudrates by reload value and deviation errors . . . . . . . . . . . . . . . . . . 74 Table 40. SSC synchronous baudrate and reload values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Table 41. WDTREL reload value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Table 42. Reset event definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Table 43. Reset event. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Table 44. PORT0 latched configuration for the different reset events . . . . . . . . . . . . . . . . . . . . . . . 106 Table 45. Power reduction modes summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Table 46. List of special function registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Table 47. List of XBus registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Table 48. List of Flash control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

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List of tables	ST10F273M

Table 49. IDMANUF register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Table 50. IDCHIP register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Table 51. IDMEM register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Table 52. IDPROG register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 Table 53. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Table 54. Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Table 55. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Table 56. Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Table 57. DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Table 58. Flash characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Table 59. Flash data retention characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 Table 60. A/D converter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 Table 61. A/D converter programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Table 62. On-chip clock generator selections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 Table 63. Internal PLL divider mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 Table 64. PLL characteristics (VDD = 5V ± 10%, VSS = 0V, TA = -40°C to +125°C) . . . . . . . . . . . . 153 Table 65. Main oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 Table 66. Main oscillator negative resistance (module) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 Table 67. 32 kHz oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 Table 68. Minimum values of negative resistance (module) for 32 kHz oscillator . . . . . . . . . . . . . . 155 Table 69. External clock drive XTAL1 timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 Table 70. Memory cycle variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 Table 71. Multiplexed bus timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 Table 72. Demultiplexed bus timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 Table 73. CLKOUT and READY timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 Table 74. External bus arbitration timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 Table 75. SSC master mode timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 Table 76. SSC slave mode timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 Table 77. Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 Table 78. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

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ST10F273M	List of figures

List of figures

Figure 1. ST10F273M Logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 2. Pin configuration (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 3. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 4. ST10F273M memory mapping (XADRS3 = 800Bh - reset value) . . . . . . . . . . . . . . . . . . . 25 Figure 5. ST10F273M memory mapping (XADRS3 = E009h - user programmed value) . . . . . . . . . 26 Figure 6. Flash structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 7. Write operation control flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Figure 8. CPU block diagram (MAC unit not included) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Figure 9. MAC unit architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Figure 10. X-Interrupt basic structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Figure 11. Block diagram of GPT1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Figure 12. Block diagram of GPT2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Figure 13. Block diagram of PWM module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Figure 14. Connection to single CAN bus via separate CAN transceivers . . . . . . . . . . . . . . . . . . . . . 78 Figure 15. Connection to single CAN bus via common CAN transceivers. . . . . . . . . . . . . . . . . . . . . . 78 Figure 16. Connection to two different CAN buses (for example for gateway application) . . . . . . . . . 79 Figure 17. Connection to one CAN bus with internal parallel mode enabled. . . . . . . . . . . . . . . . . . . . 79 Figure 18. Asynchronous power-on RESET (EA = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Figure 19. Asynchronous power-on RESET (EA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Figure 20. Asynchronous hardware RESET (EA = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Figure 21. Asynchronous hardware RESET (EA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Figure 22. Synchronous short / long hardware RESET (EA = 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Figure 23. Synchronous short / long hardware RESET (EA = 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Figure 24. Synchronous long hardware RESET (EA = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Figure 25. Synchronous long hardware RESET (EA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Figure 26. SW / WDT unidirectional RESET (EA = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Figure 27. SW / WDT unidirectional RESET (EA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Figure 28. SW / WDT bidirectional RESET (EA = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Figure 29. SW / WDT bidirectional RESET (EA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Figure 30. SW / WDT bidirectional RESET (EA = 0) followed by a HW RESET . . . . . . . . . . . . . . . . 100 Figure 31. Minimum external reset circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Figure 32. System reset circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Figure 33. Internal (simplified) reset circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Figure 34. Example of software or watchdog bidirectional reset (EA = 1) . . . . . . . . . . . . . . . . . . . . . 103 Figure 35. Example of software or watchdog bidirectional reset (EA = 0) . . . . . . . . . . . . . . . . . . . . . 104 Figure 36. PORT0 bits latched into the different registers after reset . . . . . . . . . . . . . . . . . . . . . . . . 107 Figure 37. External RC circuitry on RPD pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Figure 38. Port2 test mode structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Figure 39. Supply current versus the operating frequency (RUN and IDLE modes) . . . . . . . . . . . . . 135 Figure 40. A/D conversion characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 Figure 41. A/D converter input pins scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 Figure 42. Charge-sharing timing diagram during sampling phase . . . . . . . . . . . . . . . . . . . . . . . . . . 143 Figure 43. Anti-aliasing filter and conversion rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 Figure 44. Input/output waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 Figure 45. Float waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 Figure 46. Generation mechanisms for the CPU clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 Figure 47. ST10F273M PLL jitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 Figure 48. Crystal oscillator and resonator connection diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

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List of figures	ST10F273M

Figure 49. 32 kHz crystal oscillator connection diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 Figure 50. External clock drive XTAL1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 Figure 51. External memory cycle: Multiplexed bus, with/without read/write delay, normal ALE. . . . 160 Figure 52. External memory cycle: Multiplexed bus, with/without read/write delay, extended ALE. . 161 Figure 53. External memory cycle: Multiplexed bus, with/without r/w delay, normal ALE, r/w CS. . . 162 Figure 54. External memory cycle: Multiplexed bus, with/without r/w delay, extended ALE, r/w CS . 163 Figure 55. External memory cycle: Demultiplexed bus, with/without r/w delay, normal ALE . . . . . . . 166 Figure 56. External memory cycle: Demultiplexed bus, with/without r/w delay, extended ALE . . . . . 167 Figure 57. External memory cycle: Demultipl. bus, with/without r/w delay, normal ALE, r/w CS . . . . 168 Figure 58. External memory cycle: Demultiplexed bus, without r/w delay, extended ALE, r/w CS . . 169 Figure 59. CLKOUT and READY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 Figure 60. External bus arbitration (releasing the bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 Figure 61. External bus arbitration (regaining the bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 Figure 62. SSC master timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 Figure 63. SSC slave timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 Figure 64. PQFP144 mechanical data and package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 Figure 65. LQFP144 mechanical data and package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

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ST10F273M	Introduction

1 Introduction

1.1Description

The ST10F273M device is a new derivative of the STMicroelectronics ST10 family of 16-bit single-chip CMOS microcontrollers.

The ST10F273M combines high CPU performance (up to 20 million instructions per second) with high peripheral functionality and enhanced I/O capabilities. It also provides on-chip high-speed single voltage Flash memory, on-chip high-speed RAM, and clock generation via PLL.

The ST10F273M is processed in 0.18mm CMOS technology. The MCU core and the logic is supplied with a 5V to 1.8V on-chip voltage regulator. The part is supplied with a single 5V supply and I/Os work at 5V.

The ST10F273M is an optimized version of the ST10F273E, upward compatible with the following set of differences:

●Maximum CPU frequency is 40 MHz

●A single bank of IFlash has been implemented but the programming interface has been kept compatible with the ST10F273E

●Identification registers: the IDMEM register reflects the Flash type difference and allows to differentiate the two devices by software

●Improved EMC behavior thanks to the introduction of an internal RC filter on the 5V for the ballast transistors

●The clock to the X-Peripherals is gated: X-Peripheral not used will not get the clock in order to reduce the power consumption.

1.2Special characteristics

1.2.1X-Peripheral clock gating

This new feature have been implemented on the ST10F273M: Once the EINIT instruction has been executed, only the X-Peripherals enabled in the XPERCON register will be clocked.

The new feature allows to reduce the power consumption and also should improve the emissions as it avoids to propagate useless clock signals across the device.

1.2.2Improved supply ring

An RC filter has been introduced in the 5V power supply ring of the ballast transistor. In addition, the supply rings for the internal voltage regulators and the IOs have been split.

These two modifications should improve the behavior of the device regarding conducted emissions.

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Introduction	ST10F273M

Figure 1. ST10F273M Logic symbol

XTAL1

XTAL2

XTAL3

XTAL4

RSTIN

RSTOUT

VAREF

VAGND

NMI

EA / VSTBY

READY

ALE

RD

WR / WRL

Port 5

16-bit

V18 VDD VSS

Port 0 16-bit

Port 1 16-bit

Port 2 16-bit

Port 3 15-bit

ST10F273M		Port 4
		8-bit

Port 6 8-bit

Port 7 8-bit

Port 8 8-bit

RPD

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ST10F273M	Pin data

2 Pin data

Figure 2. Pin configuration (top view)

P6.0 / CS0 1

P6.1 / CS1 2

P6.2 / CS2 3

P6.3 / CS3 4

P6.4 / CS4 5

P6.5 / HOLD / SCLK1 6

P6.6 / HLDA / MTSR1 7

P6.7 / BREQ / MRST1 8

P8.0 / XPOUT0 / CC16IO 9

P8.1 / XPOUT1 / CC17IO 10

P8.2 / XPOUT2 / CC18IO 11

P8.3 / XPOUT3 / CC19IO 12

P8.4 / CC20IO 13

P8.5 / CC21IO 14

P8.6 / RxD1 / CC22IO 15

P8.7 / TxD1 / CC23IO 16 VDD 17 VSS 18

P7.0 / POUT0 19

P7.1 / POUT1 20

P7.2 / POUT2 21

P7.3 / POUT3 22

P7.4 / CC28IO 23

P7.5 / CC29IO 24

P7.6 / CC30IO 25

P7.7 / CC31IO 26

P5.0 / AN0 27

P5.1 / AN1 28

P5.2 / AN2 29

P5.3 / AN3 30

P5.4 / AN4 31

P5.5 / AN5 32

P5.6 / AN6 33

P5.7 / AN7 34

P5.8 / AN8 35

P5.9 / AN9 36

XTAL4			XTAL3					NMI				RSTOUT				RSTIN VSS XTAL1 XTAL2 VDD P1H.7 / A15 / CC27I																							P1H.6 / A14 / CC26I				P1H.5 / A13 / CC25I				P1H.4 / A12 / CC24I				P1H.3 / A11				P1H.2 / A10				P1H.1 / A9				P1H.0 / A8				VSS VDD P1L.7 / A7 / AN23												P1L.6 / A6 / AN22				P1L.5 / A5 / AN21				P1L.4 / A4 / AN20				P1L.3 / A3 / AN19				P1L.2 / A2 / AN18				P1L.1 / A1 / AN17				P1L.0 / A0 / AN16				P0H.7 / AD15				P0H.6 / AD14
144			143				142				141				140				139				138				137				136				135				134				133				132				131				130				129				128				127				126				125				124				123				122				121				120				119				118				117				116

ST10F273M

37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65

VAREF VAGND P5.10 / AN10 / T6EUD P5.11 / AN11 / T5EUD P5.12 / AN12 / T6IN P5.13 / AN13 / T5IN P5.14 / AN14 / T4EUD P5.15 / AN15 / T2EUD VSS VDD P2.0 / CC0IO P2.1 / CC1IO P2.2 / CC2IO P2.3 / CC3IO P2.4 / CC4IO P2.5 / CC5IO P2.6 / CC6IO P2.7 / CC7IO VSS V18 P2.8 / CC8IO / EX0IN P2.9 / CC9IO / EX1IN P2.10 / CC10IO / EX2IN P2.11 / CC11IO / EX3IN P2.12 / CC12IO / EX4IN P2.13 / CC13IO / EX5IN P2.14 / CC14IO / EX6IN / CC15IO / EX7IN / T7IN

P3.0 / T0IN

P2.15

P0H.5 / AD13			P0H.4 / AD12
115			114

P3.1 / T6OUT 66 P3.2 / CAPIN 67

113 P0H.3 / AD11

P3.3 / T3OUT 68

P0H.2 / AD10			P0H.1 / AD9
112			111

P3.4 / T3EUD 69 P3.5 / T4IN 70

110 VSS

VSS 71

VDD

109

108

P0H.0 / AD8

107

P0L.7 / AD7

106

P0L.6 / AD6

105

P0L.5 / AD5

104

P0L.4 / AD4

103

P0L.3 / AD3

102

P0L.2 / AD2

101

P0L.1 / AD1

100

P0L.0

/ AD0

99

EA / VSTBY

98

ALE

97

READY

96

WR

/WRL

95

RD

94

VSS

93

VDD

92

P4.7

/ A23 / CAN2_TxD / SDA

91

P4.6

/ A22 / CAN1_TxD / CAN2_TxD

90

P4.5

/ A21 / CAN1_RxD / CAN2_RxD

89

P4.4

/ A20 / CAN2_RxD / SCL

88

P4.3

/

A19

87

P4.2

/

A18

86

P4.1

/

A17

85

P4.0

/

A16

84

RPD

83

VSS

82

VDD

81

P3.15

/ CLKOUT

80

P3.13

/ SCLK0

79

P3.12

/ BHE /

WRH

78

P3.11

/ RxD0

77

P3.10

/ TxD0

76

P3.9

/ MTSR0

75

P3.8

/ MRST0

74

P3.7

/ T2IN

73

P3.6

/ T3IN

72

VDD

13/182

Pin data

ST10F273M

Table 1.

Pin description

Symbol

Pin

Type

Function

8-bit bidirectional I/O port, bit-wise programmable for input or output via direction

bit. Programming an I/O pin as input forces the corresponding output driver to

1 - 8

I/O

high impedance state. Port 6 outputs can be configured as push-pull or open

drain drivers. The input threshold of Port 6 is selectable (TTL or CMOS). The

following Port 6 pins have alternate functions:

1

O

P6.0

CS0

Chip select 0 output

...

...

...

...

...

5

O

P6.4

Chip select 4 output

P6.0 - P6.7

CS4

I

P6.5

External master hold request input

6

HOLD

I/O

SCLK1

SSC1: master clock output / slave clock input

O

P6.6

Hold acknowledge output

7

HLDA

I/O

MTSR1

SSC1: master-transmitter / slave-receiver O/I

O

P6.7

Bus request output

8

BREQ

I/O

MRST1

SSC1: master-receiver / slave-transmitter I/O

8-bit bidirectional I/O port, bit-wise programmable for input or output via direction

bit. Programming an I/O pin as input forces the corresponding output driver to

9-16

I/O

high impedance state. Port 8 outputs can be configured as push-pull or open

drain drivers. The input threshold of Port 8 is selectable (TTL or CMOS).

The following Port 8 pins have alternate functions:

9

I/O

P8.0

CC16IO

CAPCOM2: CC16 capture input / compare output

O

XPWM0

PWM1: channel 0 output

...

...

...

...

...

P8.0 - P8.7

12

I/O

P8.3

CC19IO

CAPCOM2: CC19 capture input / compare output

O

XPWM0

PWM1: channel 3 output

13

I/O

P8.4

CC20IO

CAPCOM2: CC20 capture input / compare output

14

I/O

P8.5

CC21IO

CAPCOM2: CC21 capture input / compare output

15

I/O

P8.6

CC22IO

CAPCOM2: CC22 capture input / compare output

I/O

RxD1

ASC1: Data input (Asynchronous) or I/O (Synchronous)

16

I/O

P8.7

CC23IO

CAPCOM2: CC23 capture input / compare output

O

TxD1

ASC1: Clock / Data output (Asynchronous/Synchronous)

14/182

ST10F273M						Pin data
Table 1.	Pin description (continued)
Symbol		Pin	Type			Function
				8-bit bidirectional I/O port, bit-wise programmable for input or output via direction
				bit. Programming an I/O pin as input forces the corresponding output driver to
		19-26	I/O	high impedance state. Port 7 outputs can be configured as push-pull or open
				drain drivers. The input threshold of Port 7 is selectable (TTL or CMOS).
				The following Port 7 pins have alternate functions:
		19	O	P7.0	POUT0	PWM0: channel 0 output
P7.0 - P7.7
		...	...	...	...	...
		22	O	P7.3	POUT3	PWM0: channel 3 output
		23	I/O	P7.4	CC28IO	CAPCOM2: CC28 capture input / compare output
		...	...	...	...	...
		26	I/O	P7.7	CC31IO	CAPCOM2: CC31 capture input / compare output
				16-bit input-only port with Schmitt-Trigger characteristics. The pins of Port 5 can
		27-36	I	be the analog input channels (up to 16) for the A/D converter, where P5.x equals
				ANx (Analog input channel x), or they are timer inputs. The input threshold of
		39-44	I
				Port 5 is selectable (TTL or CMOS). The following Port 5 pins have alternate
				functions:
P5.0 - P5.9		39	I	P5.10	T6EUD	GPT2: timer T6 external up/down control input
		40	I	P5.11	T5EUD	GPT2: timer T5 external up/down control input
P5.10 - P5.15
		41	I	P5.12	T6IN	GPT2: timer T6 count input
		42	I	P5.13	T5IN	GPT2: timer T5 count input
		43	I	P5.14	T4EUD	GPT1: timer T4 external up/down control input
		44	I	P5.15	T2EUD	GPT1: timer T2 external up/down control input
				16-bit bidirectional I/O port, bit-wise programmable for input or output via
		47-54		direction bit. Programming an I/O pin as input forces the corresponding output
			I/O	driver to high impedance state. Port 2 outputs can be configured as push-pull or
		57-64
				open drain drivers. The input threshold of Port 2 is selectable (TTL or CMOS).
				The following Port 2 pins have alternate functions:
		47	I/O	P2.0	CC0IO	CAPCOM: CC0 capture input/compare output
		...	...	...	...	...
P2.0 - P2.7
		54	I/O	P2.7	CC7IO	CAPCOM: CC7 capture input/compare output
P2.8 - P2.15
		57	I/O	P2.8	CC8IO	CAPCOM: CC8 capture input/compare output
			I		EX0IN	Fast external interrupt 0 input
		...	...	...	...	...
			I/O		CC15IO	CAPCOM: CC15 capture input/compare output
		64	I	P2.15	EX7IN	Fast external interrupt 7 input
			I		T7IN	CAPCOM2: timer T7 count input

15/182

Pin data									ST10F273M
Table 1.	Pin description (continued)
Symbol		Pin	Type						Function
				15-bit (P3.14 is missing) bidirectional I/O port, bit-wise programmable for input or
		65-70,	I/O	output via direction bit. Programming an I/O pin as input forces the
		73-80,	I/O	corresponding output driver to high impedance state. Port 3 outputs can be
		81	I/O	configured as push-pull or open drain drivers. The input threshold of Port 3 is
				selectable (TTL or CMOS). The following Port 3 pins have alternate functions:
		65	I	P3.0		T0IN			CAPCOM1: timer T0 count input
		66	O	P3.1	T6OUT				GPT2: timer T6 toggle latch output
		67	I	P3.2		CAPIN			GPT2: register CAPREL capture input
		68	O	P3.3	T3OUT				GPT1: timer T3 toggle latch output
		69	I	P3.4	T3EUD				GPT1: timer T3 external up/down control input
P3.0 - P3.5		70	I	P3.5	T4IN				GPT1; timer T4 input for count/gate/reload/capture
		73	I	P3.6	T3IN				GPT1: timer T3 count/gate input
P3.6 - P3.13,
P3.15
		74	I	P3.7	T2IN				GPT1: timer T2 input for count/gate/reload / capture
		75	I/O	P3.8		MRST0			SSC0: master-receiver/slave-transmitter I/O
		76	I/O	P3.9	MTSR0				SSC0: master-transmitter/slave-receiver O/I
		77	O	P3.10	TxD0				ASC0: clock / data output (asynchronous/synchronous)
		78	I/O	P3.11		RxD0			ASC0: data input (asynchronous) or I/O (synchronous)
									External memory high byte enable signal
		79	O	P3.12		BHE
									External memory high byte write strobe
						WRH
		80	I/O	P3.13	SCLK0				SSC0: master clock output / slave clock input
		81	O	P3.15	CLKOUT				System clock output (programmable divider on CPU
									clock)

16/182

ST10F273M

Pin data

Table 1.

Pin description (continued)

Symbol

Pin

Type

Function

Port 4 is an 8-bit bidirectional I/O port. It is bit-wise programmable for input or

output via direction bit. Programming an I/O pin as input forces the

corresponding output driver to high impedance state. The input threshold is

85-92

I/O

selectable (TTL or CMOS). Port 4.4, 4.5, 4.6 and 4.7 outputs can be configured

as push-pull or open drain drivers.

In case of an external bus configuration, Port 4 can be used to output the

segment address lines:

85

O

P4.0

A16

Segment address line

86

O

P4.1

A17

Segment address line

87

O

P4.2

A18

Segment address line

88

O

P4.3

A19

Segment address line

O

A20

Segment address line

P4.0 –P4.7

89

I

P4.4

CAN2_RxD

CAN2: receive data input

I/O

SCL

I2C Interface: serial clock

O

A21

Segment address line

90

I

P4.5

CAN1_RxD

CAN1: receive data input

I

CAN2_RxD

CAN2: receive data input

O

A22

Segment address line

91

O

P4.6

CAN1_TxD

CAN1: transmit data output

O

CAN2_TxD

CAN2: transmit data output

O

A23

Most significant segment address line

92

O

P4.7

CAN2_TxD

CAN2: transmit data output

I/O

SDA

I2C Interface: serial data

External memory read strobe.

is activated for every external instruction or

RD

RD

95

O

data read access.

External memory write strobe. In

-mode this pin is activated for every

WR

external data write access. In

WRL

mode this pin is activated for low byte data

WR/WRL

96

O

write accesses on a 16-bit bus, and for every data write access on an 8-bit bus.

See WRCFG in the SYSCON register for mode selection.

Ready input. The active level is programmable. When the ready function is

READY/

97

I

enabled, the selected inactive level at this pin, during an external memory

READY

access, will force the insertion of waitstate cycles until the pin returns to the

selected active level.

ALE

98

O

Address latch enable output. In case of use of external addressing or of

multiplexed mode, this signal is the latch command of the address lines.

17/182

Pin data								ST10F273M
Table 1.			Pin description (continued)
	Symbol			Pin	Type			Function
						External access enable pin.
						A low level applied to this pin during and after Reset forces the ST10F273M to
						start the program from the external memory space. A high level forces
						ST10F273M to start in the internal memory space. This pin is also used (when
						Standby mode is entered, that is ST10F273M under reset and main VDD turned
						off) to bias the 32 kHz oscillator amplifier circuit and to provide a reference
						voltage for the low-power embedded voltage regulator which generates the
	EA / VSTBY			99	I
						internal 1.8V supply for the RTC module (when not disabled) and to retain data
						inside the Standby portion of the XRAM (16 Kbyte).
						It can range from 4.5 to 5.5V (6V for a reduced amount of time during the device
						life, 4.0V when RTC and 32 kHz on-chip oscillator amplifier are turned off). In
						running mode, this pin can be tied low during reset without affecting 32 kHz
						oscillator, RTC and XRAM activities, since the presence of a stable VDD
						guarantees the proper biasing of all those modules.
						Two 8-bit bidirectional I/O ports P0L and P0H, bit-wise programmable for input or
						output via direction bit. Programming an I/O pin as input forces the
						corresponding output driver to high impedance state. The input threshold of
						Port 0 is selectable (TTL or CMOS).
						In case of an external bus configuration, PORT0 serves as the address (A) and
						as the address / data (AD) bus in multiplexed bus modes and as the data (D) bus
						in demultiplexed bus modes.
						Demultiplexed bus modes
P0L.0 -P0L.7,				100-107,		Data path width	8-bit	16-bit
	P0H.0			108,	I/O
P0H.1 - P0H.7				111-117		P0L.0 – P0L.7:	D0 – D7	D0 - D7
						P0H.0 – P0H.7:	I/O	D8 - D15
						Multiplexed bus modes
						Data path width	8-bit	16-bit
						P0L.0 – P0L.7:	AD0 – AD7	AD0 - AD7
						P0H.0 – P0H.7:	A8 – A15	AD8 - AD15
						Two 8-bit bidirectional I/O ports P1L and P1H, bit-wise programmable for input or
						output via direction bit. Programming an I/O pin as input forces the
						corresponding output driver to high impedance state. PORT1 is used as the 16-
						bit address bus (A) in demultiplexed bus modes: if at least BUSCONx is
				118-125		configured such the demultiplexed mode is selected, the pis of PORT1 are not
					I/O available for general purpose I/O function. The input threshold of Port 1 is
				128-135
						selectable (TTL or CMOS).

P1L.0 - P1L.7

The pins of P1L also serve as the additional (up to 8) analog input channels for

P1H.0 - P1H.7

the A/D converter, where P1L.x equals ANy (Analog input channel y, where y = x + 16). This additional function have higher priority on demultiplexed bus function. The following PORT1 pins have alternate functions:

	132	I	P1H.4	CC24IO	CAPCOM2: CC24 capture input
	133	I	P1H.5	CC25IO	CAPCOM2: CC25 capture input
	134	I	P1H.6	CC26IO	CAPCOM2: CC26 capture input
	135	I	P1H.7	CC27IO	CAPCOM2: CC27 capture input

18/182

ST10F273M

Pin data

Table 1.

Pin description (continued)

Symbol

Pin

Type

Function

XTAL1

138

I

XTAL1

Main oscillator amplifier circuit and/or external clock input.

XTAL2

137

O

XTAL2

Main oscillator amplifier circuit output.

To clock the device from an external source, drive XTAL1 while leaving XTAL2

unconnected. Minimum and maximum high / low and rise / fall times specified in

the AC Characteristics must be observed.

XTAL3

143

I

XTAL3

32 kHz oscillator amplifier circuit input

XTAL4

144

O

XTAL4

32 kHz oscillator amplifier circuit output

When 32 kHz oscillator amplifier is not used, to avoid spurious consumption,

XTAL3 shall be tied to ground while XTAL4 shall be left open. Besides, bit OFF32

in RTCCON register shall be set. 32 kHz oscillator can only be driven by an

external crystal, and not by a different clock source.

Reset Input with CMOS Schmitt-Trigger characteristics. A low level at this pin for

a specified duration while the oscillator is running resets the ST10F273M. An

140

I

internal pull-up resistor permits power-on reset using only a capacitor connected

RSTIN

to VSS. In bidirectional reset mode (enabled by setting bit BDRSTEN in

SYSCON register), the

RSTIN

line is pulled low for the duration of the internal

reset sequence.

Internal Reset Indication Output. This pin is driven to a low level during

RSTOUT

141

O

hardware, software or watchdog timer reset.

RSTOUT

remains low until the EINIT

(end of initialization) instruction is executed.

Non-Maskable Interrupt Input. A high to low transition at this pin causes the CPU

to vector to the NMI trap routine. If bit PWDCFG = ‘0’ in SYSCON register, when

the PWRDN (power down) instruction is executed, the

NMI

pin must be low in

NMI

142

I

order to force the ST10F273M to go into power down mode. If

NMI

is high and

PWDCFG = ‘0’, when PWRDN is executed, the part will continue to run in

normal mode.

If not used, pin

should be pulled high externally.

NMI

VAREF

37

-

A/D converter reference voltage and analog supply

VAGND

38

-

A/D converter reference and analog ground

RPD

84

-

Timing pin for the return from interruptible power down mode and synchronous /

asynchronous reset selection.

17, 46,

Digital supply voltage = + 5V during normal operation, idle and power down

72,82,93,

VDD

-

modes.

109, 126,

It can be turned off when Standby RAM mode is selected.

136

18,45,

55,71,

VSS

83,94,

-

Digital ground

110, 127,

139

V18

56

-

1.8V decoupling pin: a decoupling capacitor (typical value of 10nF, max 100nF)

must be connected between this pin and nearest VSS pin.

19/182

Functional description	ST10F273M

3 Functional description

The architecture of the ST10F273M combines advantages of both RISC and CISC processors and an advanced peripheral subsystem. The block diagram gives an overview of the different on-chip components and the high bandwidth internal bus structure of the ST10F273M.

Figure 3. Block diagram

16

IFlash

32

16

CPU-core and MAC unit

IRAM

512K

2K

XRAM1

16

Watchdog

2K

16

PEC

(PEC)

XRAM2

16

16

Oscillator

16

32K

32 kHz

(16K STBY)

XPWM

oscillator

XRTC

16

16

Interrupt controller

PLL

XASC

16

16

5V-1.8V

XI2C

XSSC

16

16

voltage

regulator

XCAN1

XCAN2

16

0

Port 1 Port

GPT1 / GPT2

16

External bus

controller

10-bit ADC

ASC0

SSC0

PWM

CAPCOM2

CAPCOM1

Port 2

16

8

4

BRG

BRG

Port

Port 6

Port 5

Port 3

Port 7

Port 8

8

16

15

8

8

20/182

ST10F273M	Memory organization

4 Memory organization

The memory space of the ST10F273M is configured in a unified memory architecture. Code memory, data memory, registers and I/O ports are organized within the same linear address space of 16 Mbytes. The entire memory space can be accessed Bytewise or Wordwise.

Particular portions of the on-chip memory have additionally been made directly bit addressable.

IFlash: 512 Kbytes of on-chip Flash memory implemented as a unique Bank (Bank0). Bank0 is divided in 12 blocks (B0F0...B0F11).

Note:	Read-while-write operations are not allowed: Write commands must be executed from a non
	IFlash memory area (on-chip RAM or external memory).
	When Bootstrap mode is selected, the Test-Flash Block B0TF (4 Kbytes) appears at
	address 00’0000h: Refer to the device User Manual for more details on the memory
	mapping in Bootstrap mode. The summary of address range for IFlash is the following:
	Table 2.	Summary of IFlash address range
		Blocks	User mode	Size (bytes)
		B0TF	Not visible	4 K
		B0F0	00’0000h - 00’1FFFh	8 K
		B0F1	00’2000h - 00’3FFFh	8 K
		B0F2	00’4000h - 00’5FFFh	8 K
		B0F3	00’6000h - 00’7FFFh	8 K
		B0F4	01’8000h - 01’FFFFh	32 K
		B0F5	02’0000h - 02’FFFFh	64 K
		B0F6	03’0000h - 03’FFFFh	64 K
		B0F7	04’0000h - 04’FFFFh	64 K
		B0F8	05’0000h - 05’FFFFh	64 K
		B0F9	06’0000h - 06’FFFFh	64 K
	B1F0 / B0F10 (1)		07’0000h - 07’FFFFh	64 K
	B1F1 / B0F11 (1)		08’0000h - 08’FFFFh	64 K
Note:	A single Flash bank is implemented on the ST10F273M compared to the ST10F273E. The
	last two sectors (B0F10 and B0F11) can be seen as the Bank1 of the ST10F273E in order
	to maintain the compatibility with the existing Flash programming drivers. For this, the

control and status bit of the blocks B0F10 and B0F11 have been duplicated to be usable as blocks B1F0 and B1F1 of the ST10F273E.

XFLASH / Flash Control Registers: Address range 0E’0000h-0E’FFFFh is reserved for the Flash Control Register and other internal service memory space used by the Flash Program/Erase Controller. XFLASHEN bit in XPERCON register must be set to access the Flash Control Register. Note that when Flash Control Registers are not accessible, no program/erase operations are possible. The Flash Control Registers are accessed in 16-bit demultiplexed bus-mode without read/write delay. Byte and word accesses are allowed.

21/182

Memory organization				ST10F273M
	IRAM: 2 Kbytes of on-chip internal RAM (dual-port) is provided as a storage for data,
	system stack, general purpose register banks and code. A register bank is 16 Wordwide (R0
	to R15) and / or Bytewide (RL0, RH0, …, RL7, RH7) general purpose registers group.
	XRAM: 34 Kbytes of on-chip extension RAM (single port XRAM) is provided as a storage for
	data, user stack and code.
	The XRAM is divided into two areas, the first 2 Kbytes named XRAM1 and the second
	32 Kbytes named XRAM2, connected to the internal XBUS and are accessed like an
	external memory in 16-bit demultiplexed bus-mode without wait state or read/write delay
	(50ns access at 40 MHz CPU clock). Byte and Word accesses are allowed.
	The XRAM1 address range is 00’E000h - 00’E7FFh if XPEN (bit 2 of SYSCON register),
	and XRAM1EN (bit 2 of XPERCON register) are set.
	If XRAM1EN or XPEN is cleared, then any access in the address range 00’E000h -
	00’E7FFh will be directed to external memory interface, using the BUSCONx register
	corresponding to address matching ADDRSELx register.
	The XRAM2 address range is F’0000h - F’7FFFFh if XPEN (bit 2 of SYSCON register), and
	XRAM2EN (bit 3 of XPERCON register) are set.
	If bit XPEN is cleared, then any access in the address range programmed for XRAM2 will be
	directed to external memory interface, using the BUSCONx register corresponding to
	address matching ADDRSELx register.
	The 16 kbytes lower portion of the XRAM2 (address range F’0000h - F’3FFFFh) represents
	also the Standby RAM, which can be maintained biased through	EA	/ VSTBY pin when the
	main supply VDD is turned off.
	As the XRAM appears like external memory, it cannot be used as system stack or as
	register banks. The XRAM is not provided for single bit storage and therefore is not bit
	addressable.
	SFR/ESFR: 1024 bytes (2 x 512 bytes) of address space is reserved for the special function
	register (SFR) areas. SFRs are Wordwide registers which are used to control and to monitor
	the function of the different on-chip units.
	CAN1: Address range 00’EF00h - 00’EFFFh is reserved for the CAN1 Module access. The
	CAN1 is enabled by setting XPEN bit 2 of the SYSCON register and by setting CAN1EN bit
	0 of the XPERCON register. Accesses to the CAN Module use demultiplexed addresses
	and a 16-bit data bus (only word accesses are possible). Two wait states give an access
	time of 100ns at 40 MHz CPU clock. No tri-state wait states are used.
	CAN2: Address range 00’EE00h - 00’EEFFh is reserved for the CAN2 Module access. The
	CAN2 is enabled by setting XPEN bit 2 of the SYSCON register and by setting CAN2EN bit
	1 of the new XPERCON register. Accesses to the CAN Module use demultiplexed
	addresses and a 16-bit data bus (only word accesses are possible). Two wait states give an
	access time of 100ns at 40 MHz CPU clock. No tri-state wait states are used.
Note:	If one or the two CAN modules are used, Port 4 cannot be programmed to output all eight
	segment address lines. Thus, only four segment address lines can be used, reducing the
	external memory space to 5 Mbytes (1 Mbyte per CS line).

RTC: Address range 00’ED00h - 00’EDFFh is reserved for the RTC Module access. The RTC is enabled by setting XPEN bit 2 of the SYSCON register and bit 4 of the XPERCON register. Accesses to the RTC Module use demultiplexed addresses and a 16-bit data bus (only word accesses are possible). Two waitstates give an access time of 100ns at 40 MHz CPU clock. No tristate waitstate is used.

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ST10F273M	Memory organization

PWM1: Address range 00’EC00h - 00’ECFFh is reserved for the PWM1 Module access. The PWM1 is enabled by setting XPEN bit 2 of the SYSCON register and bit 6 of the XPERCON register. Accesses to the PWM1 Module use demultiplexed addresses and a 16bit data bus (only word accesses are possible). Two waitstates give an access time of 100ns at 40 MHz CPU clock. No tristate waitstate is used. Only word access is allowed.

ASC1: Address range 00’E900h - 00’E9FFh is reserved for the ASC1 Module access. The ASC1 is enabled by setting XPEN bit 2 of the SYSCON register and bit 7 of the XPERCON register. Accesses to the ASC1 Module use demultiplexed addresses and a 16-bit data bus (only word accesses are possible). Two waitstates give an access time of 100ns at 40 MHz CPU clock. No tristate waitstate is used.

SSC1: Address range 00’E800h - 00’E8FFh is reserved for the SSC1 Module access. The SSC1 is enabled by setting XPEN bit 2 of the SYSCON register and bit 8 of the XPERCON register. Accesses to the SSC1 Module use demultiplexed addresses and a 16-bit data bus (only word accesses are possible). Two waitstates give an access time of 100ns at 40 MHz CPU clock. No tristate waitstate is used.

I2C: Address range 00’EA00h - 00’EAFFh is reserved for the I2C Module access. The I2C is enabled by setting XPEN bit 2 of the SYSCON register and bit 9 of the XPERCON register. Accesses to the I2C Module use demultiplexed addresses and a 16-bit data bus (only word accesses are possible). Two waitstates give an access time of 100ns at 40 MHz CPU clock. No tristate waitstate is used.

X-Miscellaneous: Address range 00’EB00h - 00’EBFFh is reserved for the access to a set of XBUS additional features. They are enabled by setting XPEN bit 2 of the SYSCON register and bit 10 of the XPERCON register. Accesses to this additional features use demultiplexed addresses and a 16-bit data bus (only word accesses are possible). Two waitstates give an access time of 100ns at 40 MHz CPU clock. No tristate waitstate is used. The following set of features are provided:

●CLKOUT programmable divider

●XBUS interrupt management registers

●ADC multiplexing on P1L register

●Port1L digital disable register for extra ADC channels

●CAN2 multiplexing on P4.5/P4.6

●CAN1-2 main clock prescaler

●Main Voltage Regulator disable for power-down mode

●TTL / CMOS threshold selection for Port0, Port1 and Port5

In order to meet the needs of designs where more memory is required than is provided on chip, up to 16 Mbytes of external memory can be connected to the microcontroller.

Visibility of XBUS peripherals

In order to keep the ST10F273M compatible with the ST10F168 / ST10F269, the XBUS peripherals can be selected to be visible on the external address / data bus. Different bits for X-Peripheral enabling in XPERCON register must be set. If these bits are cleared before the global enabling with XPEN bit in SYSCON register, the corresponding address space, port pins and interrupts are not occupied by the peripherals, thus the peripheral is not visible and not available. Refer to Chapter 23: Register set on page 114.

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Memory organization ST10F273M

	XPERCON and X-Peripheral clock gating
	As already mentioned, the XPERCON register must be programmed to enable the single
	XBus modules separately. The XPERCON is a read/write ESFR register.
	The new feature of Clock Gating has been implemented by means of this register: Once the
	EINIT instruction has been executed, all the peripherals (except RAMs and XMISC) not
	enabled in the XPERCON register are not be clocked. The clock gating can reduce power
	consumption and improve EMI when the user does not use all X-Peripherals.
Note:	When the clock has been gated in the disabled peripherals, no Reset will be raised once the
	EINIT instruction has been executed.

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ST10F273M	Memory organization

Figure 4. ST10F273M memory mapping (XADRS3 = 800Bh - reset value)

Code	Data	Code	Data
Segment	Page	Segment	Page

FF FFFF	1023 11 FFFF			67
255		17		66
				65
		11 0000		64
		10 FFFF		67
		16		66
				65
		10 0000	Reserved	64
		0F FFFF		63
		15		62
			XRAM2	61	32K
		0F 0000	(StandBy)	60
		0E FFFF	Flash	59
				58	64K	Default)
		0D FFFF	Control
				55
		14		57
		0E 0000	Registers	56
			B3F1	54		-
		0C FFFF	Reserved	51		(512K
		13	(XFLASH)	53
		0D 0000		52		800Bh=
		0B FFFF		47
		12	B3F0	50
			Reserved	49
			(XFLASH)
		0C 0000		48
		11	B2F2	46		XADRS3
			Reserved	45
			(XFLASH)
		0B 0000		44
		0A FFFF		43
		10	B2F1	42
			Reserved(XFLASH)	41
		0A 0000		40
		09 FFFF		39
		9	B2F0	38
			Reserved(XFLASH)	37
		09 0000		36
		08 FFFF	B0F11	35
		8		34
			(B1F1)	33
		08 0000		32
		07 FFFF	B0F10	31
		7		30
			(B1F0)	29
		07 0000		28
		06 FFFF	B0F9	27
		6		26
				25
		06 0000		24
		05 FFFF	B0F8	23
		5		22
				21
		05 0000		20
		04 FFFF	B0F7	19
		4		18
				17
		04 0000		16
		03 FFFF		15
		3	B0F6	14
				13
		03 0000		12
		02 FFFF	B0F5	11
		2		10
				9
		02 0000		8
		01 FFFF	B0F4	7
		1		6
			Ext. Mem	5
		01 0000		4
				3
		00 FFFF	Ext. Mem
		0		2
0	0		B0F3
		00 0000	B0F2	1
			B0F1
00 0000			B0F0	0

16 MB

Flash + XRAM - 1Mbyte

	00 FFFF	SFR	512
	00 FE00
	00 FDFF

X-Peripherals (2Kbyte)

I-RAM

2K

00 F000

00 F600

00 EFFF

XCAN1

256

00 F5FF

00 EF00

Reserved

1K

00 EEFF

XCAN2

256

00 F200

00 EE00

00 F1FF

ESFR

512

00 EDFF

00 F000

XRTC

256

00 EFFF

XCAN1

256

00 ED00

XCAN2

256

XRTC

256

00 ECFF

XPWM

XPWM

256

00 EC00

256

XMiscellaneous

256

XI2C

256

00 EBFF

XMiscellaneous

256

XASC

256

00 E800

XSSC

256

00 EB00

00 E7FF

00 EAFF

XI2C

256

XRAM1

00 EA00

2K

00 E9FF

XASC

256

00 E900

00 E000

00 E8FF

XSSC

256

00 DFFF

00 E800

00 E7FF

Ext. Memory 8K

Address Area defined by

XADRS3 by default after reset

00 C000

Data Page 3 (Segment 0) - 16Kbyte

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Memory organization	ST10F273M

Figure 5. ST10F273M memory mapping (XADRS3 = E009h - user programmed value)

Code	Data	Code	Data
Segment	Page	Segment	Page

FF FFFF	1023 11 FFFF		67
255	17		66
			65
	11 0000		64
	10 FFFF		67
	16		66
			65
	10 0000	XRAM2	64		E009h
	15		61
	0F FFFF	Reserved	63	32K
			62
	0F 0000	(StandBy)	60	32K	=
					XADRS3
	0E 0000	Registers	56
	0E FFFF	Flash	59
	14	Control	5758	64K
	0D FFFF		55
	13		54
			53

			0D 0000		52
			0C FFFF		51
			12		50
					49
			0C 0000	Ext	48
			0B FFFF		47
			11	Memory 4546
			0B 0000		44
			0A FFFF		43
			10		42
					41
			0A 0000		40
			09 FFFF		39
			9		38
					37
			09 0000		36
			08 FFFF	B0F11	35
			8		34
				(B1F1)	33
			08 0000		32
			07 FFFF	B0F10	31
			7		30
				(B1F0)	29
			07 0000		28
			06 FFFF	B0F9	27
			6		26
					25
			06 0000		24
			05 FFFF	B0F8	23
			5		22
					21
			05 0000		20
			04 FFFF		19
			4	B0F7	18
					17
			04 0000		16
			03 FFFF		15
			3	B0F6	14
					13
			03 0000		12
			02 FFFF	B0F5	11
			2		10
					9
			02 0000		8
			01 FFFF	B0F4	7
			1		6
				Ext Mem	5
			01 0000		4
			00 FFFF		3
0			0	Ext Mem	2
	0		00 0000	B0F3	1
				B0F2
				B0F1
00 0000				B0F0	0

00 FFFF
		SFR		512
00 FE00
00 FDFF		I-RAM			2K
00 F600
00 F5FF					1K
		Reserved
00 F200
00 F1FF		ESFR		512
00 F000
00 EFFF		XCAN1		256
		XCAN2		256
		XRTC		256
		XPWM		256
	XMiscellaneous			256
		XI2C		256
		XASC		256
00 E800		XSSC			256
00 E7FF		XRAM1			2K
00 E000
00 DFFF

Ext. Memory 8K

00 C000

X-Peripherals (2Kbyte)

00 F000

00 EFFF

XCAN1 256

00 EF00

00 EEFF

XCAN2 256

00 EE00

00 EDFF

XRTC 256

00 ED00

00 ECFF

XPWM 256

00 EC00

00 EBFF

XMiscellaneous 256

00 EB00

00 EAFF

XI2C 256

00 EA00

00 E9FF XASC 256

00 E900

00 E8FF

XSSC 256

00 E800

00 E7FF

Address Area defined by

XADRS3 after reprogramming

Note: E009h defines a 128K wide window starting from 0E’0000h

16 MB

Flash + XRAM - 1Mbyte

Data Page 3 (Segment 0) - 16Kbyte

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ST10F273M	Internal Flash memory

5 Internal Flash memory

5.1Overview

The on-chip Flash is composed of one matrix module of one bank of 512 Kbytes, named Bank0, that can be read and modified. This module is called IFlash because it is on the ST10 Internal bus.

Figure 6. Flash structure

IFlash

Bank 0: 512 Kbyte

program memory

+

4 Kbyte Test-Flash

Control Section

HV and Ref.

generator

Program/erase

controller

+

Flash control

registers

I-BUS interface		X-BUS interface

The programming operations of the Flash are managed by an embedded Flash Program/Erase Controller (FPEC). The high voltages needed for Program/Erase operations are generated internally.

The Data bus is 32-bit wide for fetch accesses to IFlash. Read/write accesses to IFlash Control Registers area are 16-bit wide.

5.2Functional description

5.2.1Structure

Table 3 below shows the address space reserved for the Flash module.

Table 3.	Flash module address space
	Description		Addresses	Size
IFlash sectors		0x00	0000 to 0x08 FFFF	512 Kbytes
Registers and Flash internal reserved area		0x0E	0000 to 0x0E FFFF	64 Kbytes

5.2.2Module structure

The IFlash module is composed of a bank (Bank 0) of 512 Kbytes of program memory divided in 12 sectors (B0F0...B0F11). Bank 0 also contains a reserved sector named TestFlash.

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Internal Flash memory	ST10F273M

The Addresses from 0x0E 0000 to 0x0E FFFF are reserved for the Control Register Interface and other internal service memory space used by the Flash Program/Erase controller.

The following tables show the memory mapping of the Flash when it is accessed in read mode (Table 4: Flash module sectorization (read operations)), and when accessed in write or erase mode (Table 5: Flash module sectorization (write operations, or ROMS1 = ‘1’)).

Note:	With this second mapping, the first four sectors are remapped into code segment 1 (same
	as obtained setting bit ROMS1 in SYSCON register).
	Table 4.		Flash module sectorization (read operations)
	Bank		Description	Addresses	Size (bytes)
			Bank 0 Flash 0 (B0F0)	0x00 0000 - 0x00 1FFF	8 K
			Bank 0 Flash 1 (B0F1)	0x00 2000 - 0x00 3FFF	8 K
			Bank 0 Flash 2 (B0F2)	0x00 4000 - 0x00 5FFF	8 K
			Bank 0 Flash 3 (B0F3)	0x00 6000 - 0x00 7FFF	8 K
			Bank 0 Flash 4 (B0F4)	0x01 8000 - 0x01 FFFF	32 K
	B0		Bank 0 Flash 5 (B0F5)	0x02 0000 - 0x02 FFFF	64 K
			Bank 0 Flash 6 (B0F6)	0x03 0000 - 0x03 FFFF	64 K
			Bank 0 Flash 7 (B0F7)	0x04 0000 - 0x04 FFFF	64 K
			Bank 0 Flash 8 (B0F8)	0x05 0000 - 0x05 FFFF	64 K
			Bank 0 Flash 9 (B0F9)	0x06 0000 - 0x06 FFFF	64 K
			Bank 0 Flash 10 (B0F10 / B1F0) (1)	0x07 0000 - 0x07 FFFF	64 K
			Bank 0 Flash 11 (B0F11 / B1F1) (1)	0x08 0000 - 0x08 FFFF	64 K

1.A single bank is implemented but the last two sectors can be seen as a Bank 1 in order to maintain compatibility with the Flash Programming routines developed for the ST10F273E (based on ST10F276E). This means that the Control and Status flags for the blocks B0F10 and B0F11 are duplicated to also be accessible as blocks B1F0 and B1F1.

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ST10F273M	Internal Flash memory

Table 5. Flash module sectorization (write operations, or ROMS1 = ‘1’)

Bank	Description	Addresses	Size (bytes)
	Bank 0 Test-Flash (B0TF)	0x00 0000 - 0x00 0FFF	4 K
	Bank 0 Flash 0 (B0F0)	0x01 0000 - 0x01 1FFF	8 K
	Bank 0 Flash 1 (B0F1)	0x01 2000 - 0x01 3FFF	8 K
	Bank 0 Flash 2 (B0F2)	0x01 4000 - 0x01 5FFF	8 K
	Bank 0 Flash 3 (B0F3)	0x01 6000 - 0x01 7FFF	32 K
	Bank 0 Flash 4 (B0F4)	0x01 8000 - 0x01 FFFF	64 K
B0
	Bank 0 Flash 5 (B0F5)	0x02 0000 - 0x02 FFFF	64 K
	Bank 0 Flash 6 (B0F6)	0x03 0000 - 0x03 FFFF	64 K
	Bank 0 Flash 7 (B0F7)	0x04 0000 - 0x04 FFFF	64 K
	Bank 0 Flash 8 (B0F8)	0x05 0000 - 0x05 FFFF	64 K
	Bank 0 Flash 9 (B0F9)	0x06 0000 - 0x06 FFFF	64 K
	Bank 0 Flash 10 (B0F10 / B1F0) (1)	0x07 0000 - 0x07 FFFF	64 K
	Bank 0 Flash 11 (B0F11 / B1F1) (1)	0x08 0000 - 0x08 FFFF	8 K

1.A single bank is implemented but the last two sectors can be seen as a Bank 1 in order to maintain compatibility with the Flash Programming routines developed for the ST10F273E (based on ST10F276E). This means that the Control and Status flags for the blocks B0F10 and B0F11 are duplicated to also be accessible as blocks B1F0 and B1F1.

Table 5 above refers to the configuration when bit ROMS1 of SYSCON register is set.

When Bootstrap mode is entered:

●Test-Flash is seen and available for code fetches (address 0x00 0000)

●User IFlash is only available for read and write accesses

●Write accesses must be made with addresses starting in segment 1 from 0x01 0000, whatever ROMS1 bit in SYSCON value

●Read accesses are made in segment 0 or in segment 1 depending of ROMS1 value.

In Bootstrap mode, by default ROMS1 = 0, so the first 32 Kbytes of IFlash are mapped in segment 0.

Example:

In default configuration, to program address 0, the user must put the value 0x01 0000 in the FARL and FARH registers but to verify the content of the address 0, a read to 0x00 0000 must be performed.

The next Table 6 shows the Control Register interface composition: This set of registers can be addressed by the CPU .

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Internal Flash memory					ST10F273M
	Table 6.	Flash control registers summary
	Name		Description	Addresses	Size	Bus size
	FCR1 - 0		Flash control registers 1 - 0 High &	0x0E 0000 - 0x0E 0007	8 byte
			Low
	FDR1 - 0		Flash data registers 1 - 0 High &	0x0E 0008 - 0x0E 000F	8 byte
			Low
	FAR		Flash address registers	0x0E 0010 - 0x0E 0013	4 byte
	FER		Flash error register	0x0E 0014 - 0x0E 0015	2 byte
	FVWPIR-mirror		Flash non-volatile protection I	0x0E DFB0 - 0x0E DFB3	4 byte	16-bit
			registers mirrored
						(XBus)
	FVWPIR		Flash volatile protection I registers	0x0E DFB4 - 0x0E DFB7	4 byte
	FVAPR0		Flash volatile access protection	0x0E DFB8 - 0x0E DFB9	2 byte
			register 0
	FVAPR1		Flash non-volatile access	0x0E DFBC - 0x0E DFBF	4 byte
			protection register 1
	XFICR		XFlash Interface Control register	0x0E E000 - 0x0E E001	2 byte
			(dummy register)
Note:	FVWPIR-mirror is a mirror of the FVWPIR to maintain software compatibility with the
	ST10F273E in the handling of the last two blocks B0F10/B1F0 and B0F11/B1F1.

XFICR is a dummy register that can be read and written (for compatibility with the ST10F273E) but its content has no effect on the XBus timings.

5.2.3Low power mode

	The Flash module is automatically switched off executing PWRDN instruction. The
	consumption is drastically reduced, but exiting this state can require a long time (tPD).
	Recovery time from Power-down mode for the Flash modules is anyway shorter than the
	main oscillator start-up time. To avoid any problem in restarting to fetch code from the Flash,
	it is important to size properly the external circuit on RPD pin.
Note:	PWRDN instruction must not be executed while a Flash program/erase operation is in
	progress.

5.3 Write operation

The Flash module has a single register interface mapped in the XBus memory space 0x0E 0000 - 0x0E 0015. All the operations are enabled through four 16-bit control registers: Flash Control Register 1-0 High/Low (FCR1H/L-FCR0H/L). Eight other 16-bit registers are used to store Flash Address and Data for Program operations (FARH/L and FDR1H/L- FDR0H/L) and Write Operation Error flags (FER). All registers are accessible with 8- and 16-bit instructions (since they are mapped on the XBus).

Note: To have access to the Flash Control Registers used for program/erasing operations, bit 5 (XFLASHEN) in XPERCON register must be set.

Caution: During a Flash write operation any attempt to read the IFlash will output the invalid data 009Bh (corresponding, for code fetch, to the software trap 009Bh). This means that the

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