ST SRK2000 User Manual

Synchronous rectifier smart driver for LLC resonant converters

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Features

SRK2000

■ Secondary-side synchronous rectifier

controller optimized for LLC resonant
converters

■ Protection against current reversal

■ Safe management of load transient, light load

and startup condition

■ Intelligent automatic sleep-mode at light load

■ Dual gate driver for N-channel MOSFETs with

1 A source and 3.5 A sink drive current

■ Operating voltage range 4.5 to 32 V

■ Programmable UVLO with hysteresis

■ 250 µA quiescent consumption

■ Operating frequency up to 500 kHz

■ SO8 package

Applications

■ All-in-one PC

■ High-power AC-DC adapters

■ 80+/85+ compliant ATX SMPS

■ 90+/92+ compliant server SMPS

■ Industrial SMPS

SO-8

corresponding half-winding starts conducting and
switched off as its current goes to zero. A unique
feature of this IC is its intelligent automatic sleep­mode. It allows the detection of a low-power
operating condition for the converter and puts the
IC into a low consumption sleep-mode where gate
driving is stopped and quiescent consumption is
reduced. In this way, converter efficiency
improves at light load, where synchronous
rectification is no longer beneficial. The IC
automatically exits sleep-mode and restarts
switching as it recognizes that the load for the
converter has increased.

A noticeable feature is the very low external
component count required.

Figure 1. Internal block diagram

Description

The SRK2000 smart driver implements a control
scheme specific to secondary-side synchronous
rectification in LLC resonant converters that use a
transformer with center-tap secondary winding for
full-wave rectification.

It provides two high-current gate-drive outputs,
each capable of driving one or more N-channel
Power MOSFETs. Each gate driver is controlled
separately and an interlocking logic circuit
prevents the two synchronous rectifier MOSFETs
from conducting simultaneously.

The control scheme in this IC allows for each
synchronous rectifier to be switched on as the

February 2012 Doc ID 17811 Rev 2 1/17

Table 1. Device summary

Order code Package Packing

SRK2000D

Tube

SO-8

SRK2000DTR Tape and reel

www.st.com

17

Contents SRK2000

Contents

1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3 Typical application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

5 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

5.1 EN pin: pin function and usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

5.1.1 Pull-up resistor configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

5.1.2 Resistor divider configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

5.1.3 Remote on/off control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

5.2 Drain voltage sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

5.3 Gate driving . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

5.4 Intelligent automatic sleep-mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

5.5 Protection against current reversal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5.6 Layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

6 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2/17 Doc ID 17811 Rev 2

SRK2000 Pin description

1 Pin description

Figure 2. Pin configuration

SGND

SGND

EN

EN

DVS1

DVS1

DVS2

DVS2

1

1

2

2

3

3

4

4

Table 2. Pin description

n. Name Function

Signal ground. Return of the bias current of the device and 0 V reference for

1SGND

2EN

3
4

DVS 1
DVS 2

drain-to-source voltage monitors of both sections. Route this pin directly to
PGND.

Drain voltage threshold setting for synchronous rectifier MOSFET turn-off. UVLO
threshold programming. This pin is typically biased by either a pull-up resistor
connected to Vcc or by a resistor divider sensing Vcc. Pulling the pin to ground
disables the gate driver outputs GD1 and GD2 and can therefore be used also
as Enable input.

Drain voltage sensing for sections 1 and 2. These pins are to be connected to
the respective drain terminals of the corresponding synchronous rectifier
MOSFET via limiting resistors. When the voltage on either pin goes negative,
the corresponding synchronous rectifier MOSFET is switched on; as its
(negative) voltage exceeds a threshold defined by the EN pin, the MOSFET is
switched off. An internal logic rejects switching noise, however, extreme care in
the proper routing of the drain connection is recommended.

Vcc

8

Vcc

8

GD1

7

GD1

7

PGND

6

PGND

6

GD2

5 GD2

5

5
7

GD2
GD1

drive Power MOSFETs with a peak current of 1 A source and 3.5 A sink. The
high-level voltage of these pins is clamped at about 12 V to avoid excessive gate
voltages in case the device is supplied with a high Vcc.

Power ground. Return for gate-drive currents. Route this pin to the common

Gate driver output for sections 2 and 1. Each totem pole output stage is able to

6PGND

point where the source terminals of both synchronous rectifier MOSFETs are
connected.

Supply voltage of the device. A small bypass capacitor (0.1 µF typ.) to SGND,
located as close to the IC’s pins as possible, may be useful to obtain a clean

8Vcc

supply voltage for the internal control circuitry. A similar bypass capacitor to
PGND, again located as close to the IC’s pins as possible, may be an effective
energy buffer for the pulsed gate-drive currents.

Doc ID 17811 Rev 2 3/17

Pin description SRK2000

Figure 3. Typical system block diagram

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4/17 Doc ID 17811 Rev 2

SRK2000 Maximum ratings

2 Maximum ratings

Table 3. Absolute maximum ratings

Symbol Pin Parameter Value Unit

Vcc 8 DC supply voltage -0.3 to Vcc

Icc

Z

8 Internal Zener maximum current 25 mA

--- 2, 3, 4 Analog inputs voltage rating -0.3 to Vcc

I

DVS1,2_sk

I

DVS1,2_sr

Table 4. Thermal data

3, 4 Analog inputs max. sink current (single pin) 25 mA

3, 4 Analog inputs max. source current (single pin) -5 mA

Symbol Parameter Value Unit

R

Max. thermal resistance, junction-to-ambient 150 °C/W

thJA

Ptot Power dissipation @ TA = 50 °C 0.65 W

T

Junction temperature operating range -40 to 150 °C

J

T

Storage temperature -55 to 150 °C

stg

3 Typical application schematic

Figure 4. Typical application schematic

Z

Z

V

V

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Doc ID 17811 Rev 2 5/17

Electrical characteristics SRK2000

4 Electrical characteristics

TJ = -25 to 125 °C, VCC = 12 V, C
specified; typical values refer to T

Table 5. Electrical characteristics

= C

GD1

= 25 °C.

J

= 4.7 nF, EN = VCC; unless otherwise

GD2

Symbol Parameter Test condition Min. Typ. Max. Unit

Supply voltage

V

V

CCOn

V

CCOff

CC

Operating range After turn-on 4.5 32 V

Turn-on threshold

Turn-off threshold

(1)

(1)

4.25 4.5 4.75 V

4 4.25 4.5 V

Hys Hysteresis 0.25 V

Vcc

Zener voltage IccZ = 20 mA 33 36 39 V

Z

Supply current

I

start-up

Startup current Before turn-on, Vcc = 4 V 45 70 µA

Iq Quiescent current After turn-on 250 500 µA

I

CC

Operating supply current @ 300 kHz 35 mA

Iq Quiescent current EN = SGND 150 250 µA

Drain sensing inputs and synch functions

V

DVS1,2_H

I

DVS1,2_b

V

DVS1,2_A

Upper clamp voltage I

Input bias current V

Arming voltage
(positive-going edge)

= 20 mA Vcc

DVS1,2

DVS1,2

= 0 to Vcc

(2)

Z

-1 1 µA

1.4 V

V

V

DVS1,2_PT

V

DVS1,2_TH

I

DVS1,2_On

V

DVS1,2_Off

T

PD_On

T

PD_Off

T

ON_min

D

OFF

D

ON

Gate-drive enable function

V

EN_On

Pre-triggering voltage
(negative-going edge)

Turn-on threshold -250 -200 -180

Turn-on source current V

Turn-off threshold
(positive-going edge)

Turn-on debounce delay After sourcing I

Turn-off propagation delay After crossing V

Minimum on-time 150 ns

Min. operating duty-cycle 40 %

Restart duty-cycle 60 %

Enable threshold Positive-going edge

Hyst Hysteresis Below V

6/17 Doc ID 17811 Rev 2

0.7 V

= -250 mV -50 µA

DVS1,2

R = 680 kΩ from EN to Vcc -18 -25 -32

R = 270 kΩ from EN to Vcc -9 -12.5 -16

DS1,2_On

DS1,2_Off

(1)

EN_On

250 ns

60 ns

1.7 1.8 1.9 V

45 mV

mV