Synchronous rectifier smart driver for LLC resonant converters
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Features
SRK2000
■ Secondary-side synchronous rectifier
controller optimized for LLC resonant
converters
■ Protection against current reversal
■ Safe management of load transient, light load
and startup condition
■ Intelligent automatic sleep-mode at light load
■ Dual gate driver for N-channel MOSFETs with
1 A source and 3.5 A sink drive current
■ Operating voltage range 4.5 to 32 V
■ Programmable UVLO with hysteresis
■ 250 µA quiescent consumption
■ Operating frequency up to 500 kHz
■ SO8 package
Applications
■ All-in-one PC
■ High-power AC-DC adapters
■ 80+/85+ compliant ATX SMPS
■ 90+/92+ compliant server SMPS
■ Industrial SMPS
SO-8
corresponding half-winding starts conducting and
switched off as its current goes to zero. A unique
feature of this IC is its intelligent automatic sleepmode. It allows the detection of a low-power
operating condition for the converter and puts the
IC into a low consumption sleep-mode where gate
driving is stopped and quiescent consumption is
reduced. In this way, converter efficiency
improves at light load, where synchronous
rectification is no longer beneficial. The IC
automatically exits sleep-mode and restarts
switching as it recognizes that the load for the
converter has increased.
A noticeable feature is the very low external
component count required.
Figure 1. Internal block diagram
Description
The SRK2000 smart driver implements a control
scheme specific to secondary-side synchronous
rectification in LLC resonant converters that use a
transformer with center-tap secondary winding for
full-wave rectification.
It provides two high-current gate-drive outputs,
each capable of driving one or more N-channel
Power MOSFETs. Each gate driver is controlled
separately and an interlocking logic circuit
prevents the two synchronous rectifier MOSFETs
from conducting simultaneously.
The control scheme in this IC allows for each
synchronous rectifier to be switched on as the
February 2012 Doc ID 17811 Rev 2 1/17
Table 1. Device summary
Order code Package Packing
SRK2000D
Tube
SO-8
SRK2000DTR Tape and reel
www.st.com
17
Contents SRK2000
Contents
1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3 Typical application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
5 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5.1 EN pin: pin function and usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5.1.1 Pull-up resistor configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5.1.2 Resistor divider configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5.1.3 Remote on/off control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5.2 Drain voltage sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5.3 Gate driving . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.4 Intelligent automatic sleep-mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.5 Protection against current reversal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.6 Layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2/17 Doc ID 17811 Rev 2
SRK2000 Pin description
1 Pin description
Figure 2. Pin configuration
SGND
SGND
EN
EN
DVS1
DVS1
DVS2
DVS2
1
1
2
2
3
3
4
4
Table 2. Pin description
n. Name Function
Signal ground. Return of the bias current of the device and 0 V reference for
1SGND
2EN
3
4
DVS 1
DVS 2
drain-to-source voltage monitors of both sections. Route this pin directly to
PGND.
Drain voltage threshold setting for synchronous rectifier MOSFET turn-off. UVLO
threshold programming. This pin is typically biased by either a pull-up resistor
connected to Vcc or by a resistor divider sensing Vcc. Pulling the pin to ground
disables the gate driver outputs GD1 and GD2 and can therefore be used also
as Enable input.
Drain voltage sensing for sections 1 and 2. These pins are to be connected to
the respective drain terminals of the corresponding synchronous rectifier
MOSFET via limiting resistors. When the voltage on either pin goes negative,
the corresponding synchronous rectifier MOSFET is switched on; as its
(negative) voltage exceeds a threshold defined by the EN pin, the MOSFET is
switched off. An internal logic rejects switching noise, however, extreme care in
the proper routing of the drain connection is recommended.
Vcc
8
Vcc
8
GD1
7
GD1
7
PGND
6
PGND
6
GD2
5 GD2
5
5
7
GD2
GD1
drive Power MOSFETs with a peak current of 1 A source and 3.5 A sink. The
high-level voltage of these pins is clamped at about 12 V to avoid excessive gate
voltages in case the device is supplied with a high Vcc.
Power ground. Return for gate-drive currents. Route this pin to the common
Gate driver output for sections 2 and 1. Each totem pole output stage is able to
6PGND
point where the source terminals of both synchronous rectifier MOSFETs are
connected.
Supply voltage of the device. A small bypass capacitor (0.1 µF typ.) to SGND,
located as close to the IC’s pins as possible, may be useful to obtain a clean
8Vcc
supply voltage for the internal control circuitry. A similar bypass capacitor to
PGND, again located as close to the IC’s pins as possible, may be an effective
energy buffer for the pulsed gate-drive currents.
Doc ID 17811 Rev 2 3/17
Pin description SRK2000
Figure 3. Typical system block diagram
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SRK2000 Maximum ratings
2 Maximum ratings
Table 3. Absolute maximum ratings
Symbol Pin Parameter Value Unit
Vcc 8 DC supply voltage -0.3 to Vcc
Icc
Z
8 Internal Zener maximum current 25 mA
--- 2, 3, 4 Analog inputs voltage rating -0.3 to Vcc
I
DVS1,2_sk
I
DVS1,2_sr
Table 4. Thermal data
3, 4 Analog inputs max. sink current (single pin) 25 mA
3, 4 Analog inputs max. source current (single pin) -5 mA
Symbol Parameter Value Unit
R
Max. thermal resistance, junction-to-ambient 150 °C/W
thJA
Ptot Power dissipation @ TA = 50 °C 0.65 W
T
Junction temperature operating range -40 to 150 °C
J
T
Storage temperature -55 to 150 °C
stg
3 Typical application schematic
Figure 4. Typical application schematic
Z
Z
V
V
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Doc ID 17811 Rev 2 5/17
Electrical characteristics SRK2000
4 Electrical characteristics
TJ = -25 to 125 °C, VCC = 12 V, C
specified; typical values refer to T
Table 5. Electrical characteristics
= C
GD1
= 25 °C.
J
= 4.7 nF, EN = VCC; unless otherwise
GD2
Symbol Parameter Test condition Min. Typ. Max. Unit
Supply voltage
V
V
CCOn
V
CCOff
CC
Operating range After turn-on 4.5 32 V
Turn-on threshold
Turn-off threshold
(1)
(1)
4.25 4.5 4.75 V
4 4.25 4.5 V
Hys Hysteresis 0.25 V
Vcc
Zener voltage IccZ = 20 mA 33 36 39 V
Z
Supply current
I
start-up
Startup current Before turn-on, Vcc = 4 V 45 70 µA
Iq Quiescent current After turn-on 250 500 µA
I
CC
Operating supply current @ 300 kHz 35 mA
Iq Quiescent current EN = SGND 150 250 µA
Drain sensing inputs and synch functions
V
DVS1,2_H
I
DVS1,2_b
V
DVS1,2_A
Upper clamp voltage I
Input bias current V
Arming voltage
(positive-going edge)
= 20 mA Vcc
DVS1,2
DVS1,2
= 0 to Vcc
(2)
Z
-1 1 µA
1.4 V
V
V
DVS1,2_PT
V
DVS1,2_TH
I
DVS1,2_On
V
DVS1,2_Off
T
PD_On
T
PD_Off
T
ON_min
D
OFF
D
ON
Gate-drive enable function
V
EN_On
Pre-triggering voltage
(negative-going edge)
Turn-on threshold -250 -200 -180
Turn-on source current V
Turn-off threshold
(positive-going edge)
Turn-on debounce delay After sourcing I
Turn-off propagation delay After crossing V
Minimum on-time 150 ns
Min. operating duty-cycle 40 %
Restart duty-cycle 60 %
Enable threshold Positive-going edge
Hyst Hysteresis Below V
6/17 Doc ID 17811 Rev 2
0.7 V
= -250 mV -50 µA
DVS1,2
R = 680 kΩ from EN to Vcc -18 -25 -32
R = 270 kΩ from EN to Vcc -9 -12.5 -16
DS1,2_On
DS1,2_Off
(1)
EN_On
250 ns
60 ns
1.7 1.8 1.9 V
45 mV
mV
SRK2000 Electrical characteristics
Table 5. Electrical characteristics (continued)
Symbol Parameter Test condition Min. Typ. Max. Unit
I
EN
Bias current VEN = V
Turn-off threshold selection
V
EN-Th
I
EN
Selection threshold VCC = V
Pull-down current VEN = V
Gate drivers
V
GDH
V
GDL
I
sourcepk
I
sinkpk
t
t
V
GDclamp
V
GDL_UVLO
1. Parameters tracking each other.
2. For Vcc>30 V I
internal clamp Zener (few tens of µA).
Output high voltage
Output low voltage
Output source peak current -1 A
Output sink peak current 3.5 A
Fall time 18 ns
f
Rise time 40 ns
r
Output clamp voltage I
UVLO saturation
may be greater than 1 µA because of the possible current contribution of the
DVS1,2_b
EN_On
CCOn
, VCC = V
EN_Th
I
GDsource
I
GDsource
I
GDsink
I
GDsink
GDsource
Vcc = 0 to V
= 5 mA 11.75 11.9
= 5 mA, Vcc = 5 V 4.75 4.9
= 200 mA 0.2
= 200 mA, Vcc = 5 V 0.2
= 5 mA; Vcc = 20 V 12 13 15 V
CCon
CCOn
Isink = 5 mA
1µA
0.32 0.36 0.40 V
71013µA
V
V
11.3V
Doc ID 17811 Rev 2 7/17
Application information SRK2000
−
−=→Ω>
−=→
Ω
5 Application information
5.1 EN pin: pin function and usage
This pin can perform three different functions: it sets the threshold V
to-source voltage of either synchronous rectifier (SR) Power MOSFET to determine their
turn-off in each conduction cycle; it allows the user to program the UVLO thresholds of the
gate drivers and can be used as Enable (remote on/off control).
5.1.1 Pull-up resistor configuration
At startup, an internal 10 µA current sink (IEN) is active as long as the device supply voltage
Vcc is below the startup threshold V
voltage V
on the EN pin determines the turn-off threshold V
EN
of both synchronous rectifiers during their cycle-by-cycle operation: if V
V) the threshold is set at -25 mV, otherwise at -12 mV. Once the decision is made, the
setting is frozen as long as Vcc is greater than the turn-off level V
A simple pull-up resistor R
to Vcc can be used to set V
1
voltage on the EN pin as the device turns on is given by:
Then, considering worst-case scenarios, we have:
CCOn
. The moment Vcc equals V
DVS1,2_Off
CCOff
DVS1,2_Off
=
1RIVV
ENCCOnEN
Off_2,1DVS
turn-off threshold. The
mV25Vk6331R
DVS1,2_Off
CCOn
for the drain-
(4.5 V typ.), the
for the drain voltage
EN
< V
EN_Th
(= 0.36
(4.25 V typ.).
<
Some additional margin (equal to the resistor's tolerance) needs to be considered;
assuming 5% tolerance, the use of the standard values R
= 270 kΩ in the second case, is suggested.
Figure 5. EN pin biased with a pull-up resistor (for logic-level MOSFET driving)
As Vcc exceeds V
, the internal current sink IEN is switched off and the enable function
CCOn
is activated. The voltage on the pin is then compared to an internal reference V
8/17 Doc ID 17811 Rev 2
Off_2,1DVS
mV12Vk2961R
= 680 kΩ in the first case and R1
1
EN_On
set at
SRK2000 Application information
1.8 V: if this threshold is exceeded the gate drivers GD1 and GD2 are enabled and the SR
MOSFET is operated; otherwise, the device stays in an idle condition and the SR MOSFET
in the off state.
Using the pull-up resistor R
to Vcc, therefore exceeding V
, the voltage on the EN pin rises as IEN is switched off and tends
P
and enabling the operation of both SR MOSFETs.
EN_On
Essentially, this results in enabling the gate-driving as Vcc exceeds V
as Vcc falls below V
. This configuration is thereby recommended when SR MOSFETs
CCOn
are logic-level types.
5.1.2 Resistor divider configuration
To enable gate-driving with a Vcc voltage higher than a predefined value V
drive a standard SR MOSFET, the EN pin is biased by a resistor divider (R1 upper resistor,
R2 lower resistor) whose value is chosen so as to exceed V
also to set the desired V
DVS 1,2_O ff
at a Vcc level about 2.5% lower than V
comparator.
The equations that describe the circuit in the two crucial conditions Vcc = V
decision of the V
DVS1,2_Off
level is made) and Vcc = V
enabled) are respectively:
Figure 6. EN pin biased with a resistor divider to program the gate-drive UVLO
threshold V
CC_G
level. Note that, with a falling Vcc, gate-driving is disabled
CCOn
when Vcc = V
EN_On
, because of the 45 mV hysteresis of the
CC_G
(when gate-driving is to be
CC_G
and disabling it
, to properly
CC_G
and
CC_G
(when the
CCOn
Equation 1
−
⎧
⎪
⎨
⎪
V
⎩
Solving these equations for R
and R2 we get:
1
VV
ENCCOn
1R
2R
+
2R1R
Doc ID 17811 Rev 2 9/17
V
EN
+=
I
EN
=
2R
V
On_ENG_CC
Application information SRK2000
Equation 2
V
−
VV
ENCCOn
I
EN
V
−
G_CC
V
On_EN
On_EN
VV
On_ENG_CC
If V
of V
⎧
⎪
⎪
=
1R
⎪
⎨
⎪
1R2R
=
⎪
⎪
⎩
is not too low (<8÷9 V), its tolerance is not critical because it is related only to that
CC_G
(±5.6%) and of the external resistors R1, R2 (±1% each is recommended). Then,
EN_On
some care needs to be taken only as far as the selection of the -12/-25 mV threshold is
concerned: in fact, the large spread of I
the device turns on, a value that can be found by solving the first of (1) for V
considerably affects the voltage on the EN pin as
EN
EN
:
Equation 3
1RIV
−
V
=
EN
ENCCOn
1R
1
+
2R
A couple of examples clarify the suggested calculation methodology.
Example 1 V
In this case, V
= 10 V, V
CC_G
must definitely be lower than the minimum value of V
EN
DVS1,2_Off
= - 25 mV.
EN_Th
(= 0.32 V).
From the second of (2), the nominal ratio of R1 to R2 is (10 – 1.8) / 1.8 = 4.555. Substituting
the appropriate extreme values in (3) it must be (4.75 - 7·10
-6
·R1) / (1 + 4.555) < 0.32;
solving for R1 yields R1 > 425 kΩ; let us consider an additional 4% margin to take both the
tolerance and the granularity of the R1 and R2 values into account, so that: R1 > 425·1.04 =
442 kΩ. Choose R1 = 442 kΩ (E48 standard value) and, from the second of (2), R2 =
442/4.555 = 97 kΩ; use 97.6 kΩ (E48 standard value).
Example 2 V
In this case, V
= 10 V, V
CC_G
must definitely be higher than the maximum value of V
EN
DVS1,2_Off
= - 12 mV.
EN_Th
(= 0.40 V).
From the second of (2), the nominal ratio of R1 to R2 is (10 – 1.8) / 1.8 = 4.555. Substituting
the appropriate extreme values in (3) it must be (4.25 - 13·10
-6
·R1) / (1 + 4.555) > 0.4;
solving for R1 yields R1 < 156 kΩ; with 4% additional margin R1 < 156/1.04 = 150 kΩ.
Choose R1 = 147 kΩ (E48 standard value) and, from the second of (2), R2 = 147/4.555 =
32.3 kΩ; use 32.4 kΩ (E48 standard value).
Note: In both examples the gate drivers are disabled as Vcc falls below 9.75 V (nominal value), as
the voltage on the EN pin falls 45 mV below V
10/17 Doc ID 17811 Rev 2
EN_On
.
SRK2000 Application information
5.1.3 Remote on/off control
Whichever configuration is used, since a voltage on the EN pin 45 mV below V
disables the gate drivers, any small-signal transistor can be used to pull down the EN pin
and force the gate drivers into an off state.
Finally, it should be noted that during power-up, power-down, and under overload or shortcircuit conditions, the gate drivers are shut down if the Vcc voltage is insufficient: < V
case of pull-up resistor configuration, < 0.975 ÞV
configuration (the coefficient 0.975 depends on the hysteresis on the Enable pin threshold).
5.2 Drain voltage sensing
In the following explanations it is assumed that the reader is familiar with the LLC resonant
half bridge topology and its waveforms, especially those on the secondary side with a
center-tap transformer winding for full-wave rectification.
To understand the polarity and the level of the current flowing in the SR MOSFETs (or their
body diodes, or diodes in parallel to the MOSFETs) the IC is provided with two pins, DVS12, able to sense the voltage level of the MOSFET drains.
Figure 7. Typical waveform seen on the drain voltage sensing pins
in case of resistor divider
CC_G
EN_On
CCOff
in
The logic that controls the driving of the two SR MOSFETs is based on two gate-driver state
machines working in parallel in an interlocked way to avoid both gate drivers being switched
on at the same time.
There are four significant drain voltage thresholds: the first one, V
DVS 1,2_ A
(= 1.4 V),
sensitive to positive-going edges, arms the opposite gate driver (interlock function); the
second, V
DVS1,2_PT
gate driver; the third is the (negative) threshold V
(=0.7 V), sensitive to negative-going edges, provides a pre-trigger of the
that triggers the gate driver as the
TH-ON
body diode of the SR MOSFET starts conducting; the fourth is the internal (negative)
threshold V
-25 mV by properly biasing the EN pin).
The value of the ON threshold V
DVS1,2_Off
where the SR MOSFET is switched off (selectable between -12 mV or
is affected by the external resistor in series to each
TH-ON
DVS1-2 pin needed essentially to limit the current that might be injected into the pins when
one SR MOSFET is off and the other SR MOSFET is conducting. In fact, on the one hand,
when one MOSFET is off (and the other one is conducting), its drain-to-source voltage is
Doc ID 17811 Rev 2 11/17
Application information SRK2000
+
slightly higher than twice the output voltage; if this exceeds the voltage rating of the internal
clamp (Vcc
= 36 V typ.), a series resistor RD must limit the injected current below an
Z
appropriate value, lower than the maximum rating (25 mA) and taking the related power
dissipation into account. On the other hand, when current starts flowing into the body diode
of one MOSFET (or in the diode in parallel with the MOSFET), the drain-to-source voltage is
negative (
0.2V typ.), an internal current source I
≅ -0.7 V); when the voltage on pins DVS1,2 reaches the threshold V
DVS1,2_On
is activated; as this current exceeds 50 µA,
DVS1,2_TH
(-
the gate of the MOSFET is turned on. Therefore, the actual triggering threshold can be
determined by the following formula:
VIRV
TH_2,1DVSOn2,1DVSDONTH
For instance, with R
−
= 2 kΩ, the triggering threshold is located at - (2 kΩ ⋅ 50 µA) - 0.2 V =
D
⋅=
-0.3 V.
To avoid false triggering of the gate driver, a debounce delay T
sourcing I
DS1,2_On
(i.e. the current sourced by the pin must exceed 50 µA for more than 250
(= 250 ns) is used after
PD_On
ns before the gate driver is turned on). This delay is not critical for the converter’s efficiency
because the initial current is close to zero or anyway much lower than the peak value.
Once the SR MOSFET has been switched on, its drain-to-source voltage drops to a value
given by the flowing current times the MOSFET R
low, the voltage drop across the R
may exceed the turn-off threshold V
DS(on)
. Again, since the initial current is
DS(on)
DVS1,2_Off
, and
determine an improper turn-off. To prevent this, the state machine enables the turn-off
comparator referenced to V
DVS1,2_Off
only in the second half of the conduction cycle, based
on the information of the duration of the previous cycle. In the first half of the conduction
cycle only an additional comparator, referenced to zero, is active to prevent the current of
the SR MOSFET from reversing, which would impair the operation of the LLC converter.
Once the threshold V
DVS1,2_Off
is crossed (in the second half of the conduction cycle) and
the GATE is turned off, the current again flows through the body diode causing the drain-tosource voltage to have a negative jump, going again below V
. The interlock logic,
TH-ON
however, prevents a false turn-on. It is worth pointing out that, due to the fact that each
MOSFET is turned on after its body diode starts conducting, the ON transition happens with
the drain-source voltage equal to the body diode forward drop; therefore there is neither a
Miller effect nor switching losses at MOSFET turn-on. Also at turn-off the switching losses
are not present, in fact, the current is always flowing from source to drain and, when the
MOSFET is switched off, it goes on flowing through the body diode (or the external diode in
parallel to the MOSFET).
Unlike at turn-on, the turn-off speed is critical to avoid current reversal on the secondary
side, especially when the converter operates above the resonance frequency, where the
current flowing through the MOSFET exhibits a very steep edge while decreasing down to
zero: the turn-off propagation T
delay has a maximum value of 60 ns.
PD_Off
The interlock logic, in addition to checking for consistent secondary voltage waveforms (one
MOSFET can be turned on only if the other one has a positive drain-to-source voltage >
V
DVS1,2_A
one gate driver has been turned off, it cannot be turned on again before the other gate drive
has had its own on/off cycle.
) to prevent simultaneous conduction, allows only one switching per cycle: after
The IC logic also prevents unbalanced current in the two SR MOSFETs: if one SR MOSFET
fails to turn on in one cycle, the other SR MOSFET is also not turned on in the next cycle.
12/17 Doc ID 17811 Rev 2
SRK2000 Application information
Figure 8. Typical connection of the SRK2000 to the SR MOSFET
5.3 Gate driving
The IC is provided with two high-current gate-drive outputs (1 A source and 3.5 A sink),
each capable of driving one or more N-channel Power MOSFETs. Thanks to the
programmable gate-drive UVLO, it is possible to drive both standard MOSFETs and logic
level MOSFETs.
The high-level voltage provided by the driver is clamped at V
excessive voltage levels on the gate in case the device is supplied with a high Vcc.
To Xfo rme r
To Xfo rme r
I
I
SR1
SR1
SR1
SR1
R
R
D
D
R
R
G
G
SRK2000
SRK2000
DVS1
DVS1
GD1
GD1
GDclamp
(=12 V) to avoid
The two gate drivers have a pull-down capability that ensures the SR MOSFETs cannot be
spuriously turned on even at low Vcc: in fact, the drivers have a 1 V (typ.) UVLO saturation
level at Vcc below the turn-on threshold.
5.4 Intelligent automatic sleep-mode
A unique feature of this IC is its intelligent automatic sleep-mode. The logic circuitry is able
to detect a light load condition for the converter and stop gate driving, also reducing the IC’s
quiescent consumption. This improves converter efficiency at light load, where the power
losses on the rectification body diodes (or external diodes in parallel to the MOSFETs) go
lower than the power losses in the MOSFETs and those related to their driving.
The IC is also able to detect an increase of the converter’s load and automatically restart
gate driving.
The algorithm used by the intelligent automatic sleep-mode is based on a dual time
measurement system. The duration of a switching cycle of an SR MOSFET (that is one half
of the resonant converter switching period) is measured using a combination of the
negative-going edge of the drain-to-source voltage falling below V
positive-going edge exceeding V
measured from the moment its body diode starts conducting (drain-to-source voltage falling
below V
) to the moment the gate drive is turned off (in case the device is operating) or
TH-ON
the moment the body diode ceases to conduct (drain-to-source voltage going over V
While at full load the SR MOSFET conduction time occupies almost 100% of the switching
cycle, as the load is reduced, the conduction time is reduced and as it falls below 40%
(D
) of the SR MOSFET switching cycle the device enters sleep-mode. To prevent
OFF
DVS1,2_A
DVS1,2_PT
and the
; the duration of the SR MOSFET conduction is
TH-ON
).
Doc ID 17811 Rev 2 13/17
Application information SRK2000
erroneous decisions, the sleep-mode condition must be confirmed for 16 consecutive
switching cycles of the resonant converter (i.e. 16 consecutive cycles for each SR MOSFET
of the center-tap).
Once in sleep-mode, SR MOSFET gate driving is re-enabled when the conduction time of
the body diode (or the external diodes in parallel to the MOSFET) exceeds 60% (D
) of the
ON
switching cycles. Also in this case the decision is made considering the measurement on 8
consecutive switching cycles (i.e. 8 consecutive cycles for each SR MOSFET of the centertap). Furthermore, after each sleep-mode entering/exiting transition, the timing is ignored for
a certain number of cycles, to let the resulting transient in the output current fade out; then
the time check is enabled. The number of ignored resonant converter switching cycles is
128 after entering sleep-mode and 256 after exiting sleep-mode.
5.5 Protection against current reversal
The IC provides protection against SR MOSFET current reversal. If a current reversal
condition is detected for two consecutive switching cycles, the IC goes into sleep-mode,
avoiding the turn-on of the SR MOSFETs until a safe condition is restored.
5.6 Layout guidelines
The IC is designed with two grounds, SGND and PGND.
SGND is used as the ground reference for all the internal high-precision analog blocks,
while PGND is the ground reference for all the noisy digital blocks, as well as the current
return for the gate drivers. In addition, it is also the ground for the ESD protection circuits.
SGND is protected by ESD events versus PGND through two anti-parallel diodes.
When laying out the PCB, make sure to keep the source terminals of both SR MOSFETs as
close as possible to one another and to route the trace that goes to PGND separately from
the load current return path. This trace should be as short as possible and be as close to the
physical source terminals as possible. A layout that is as geometrically symmetrical as
possible helps the circuit to operate in the most electrically symmetrical way as possible.
SGND should be directly connected to PGND using a path as short as possible (under the
device body).
Also drain voltage sensing should be performed as physically close to the drain terminals as
possible: any stray inductance crossed by the load current that is in the drain-to-source
voltage sensing circuit may significantly alter the current reading, leading to a premature
turn-off of the SR MOSFET. It is worth mentioning that, especially in higher power
applications or at higher operating frequencies, even the stray inductance of the internal
wire bonding can be detrimental. In this case, a cautious selection of the SR MOSFET
package is required.
The use of bypass capacitors between Vcc and both SGND and PGND is recommended.
They should be low-ESR, low-ESL types and located as close to the IC pins as possible.
Sometimes a series resistor (in the tens) between the converter's output voltage and the
Vcc pin, forming an RC filter along with the bypass capacitor, is useful in order to get a
cleaner Vcc voltage.
14/17 Doc ID 17811 Rev 2
SRK2000 Package mechanical data
6 Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
®
ECOPACK
specifications, grade definitions and product status are available at:
packages, depending on their level of environmental compliance. ECOPACK
www.st.com
. ECOPACK
is an ST trademark.
Table 1. SO-8 mechanical data
Dim.
Min. Typ. Max. Min. Typ. Max.
A 1.35 1.75 0.053 0.069
A1 0.10 0.25 0.004 0.010
A2 1.10 1.65 0.043 0.065
B 0.33 0.51 0.013 0.020
C 0.19 0.25 0.007 0.010
(1)
D
4.80 5.00 0.189 0.197
E 3.80 4.00 0.15 0.157
e 1.27 0.050
H 5.80 6.20 0.228 0.244
h 0.25 0.50 0.010 0.020
L 0.40 1.27 0.016 0.050
k 0° (min.), 8° (max.)
ddd 0.10 0.004
mm. inch
1. D dimensions do not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs
should not exceed 0.15 mm (.006 inch) in total (both sides).
Figure 9. Package dimensions
Doc ID 17811 Rev 2 15/17
Revision history SRK2000
7 Revision history
Table 6. Document revision history
Date Revision Changes
10-Aug-2010 1 Initial release.
Minor text changes to improve readability in features, on cover
08-Feb-2012 2
page, and
Added
Chapter 5
Chapter 5.5: Protection against current reversal
Document status promoted from preliminary data to datasheet.
.
.
16/17 Doc ID 17811 Rev 2
SRK2000
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