ST SRIX4K User Manual
13.56 MHz short-range contactless memory chip
–Unsawn wafer
– Bumped and sawn wafer
with 4096-bit EEPROM, anticollision and anti-clone functions
Features
■ ISO 14443-2 Type B air interface compliant
■ ISO 14443-3 Type B frame format compliant
■ 13.56 MHz carrier frequency
■ 847 kHz subcarrier frequency
■ 106 Kbit/second data transfer
■ France Telecom proprietary anti-clone function
■ 8 bit Chip_ID based anticollision system
■ 2 count-down binary counters with automated
antitearing protection
■ 64-bit unique identifier
■ 4096-bit EEPROM with write protect feature
■ Read_block and Write_block (32 bits)
■ Internal tuning capacitor
■ 1million erase/write cycles
■ 40-year data retention
■ Self-timed programming cycle
■ 5 ms typical programming time
SRIX4K
September 2011 Doc 8887 Rev 9 1/48
www.st.com
1
Contents SRIX4K
Contents
1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.0.1 AC1, AC0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3 Data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1 Input data transfer from the reader to the SRIX4K (request frame) . . . . . . 9
3.1.1 Character transmission format for request frame . . . . . . . . . . . . . . . . . . 9
3.1.2 Request start of frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1.3 Request end of frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.2 Output data transfer from the SRIX4K to the reader (answer frame) . . . . 11
3.2.1 Character transmission format for answer frame . . . . . . . . . . . . . . . . . . 11
3.2.2 Answer start of frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.2.3 Answer end of frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.3 Transmission frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.4 CRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.1 Resettable OTP area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.2 32-bit binary counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.3 EEPROM area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.4 System area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.4.1 OTP_Lock_Reg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.4.2 Fixed Chip_ID (Option) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5 SRIX4K operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6 SRIX4K states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.1 Power-off state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.2 Ready state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.3 Inventory state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.4 Selected state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.5 Deselected state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2/48 Doc 8887 Rev 9
SRIX4K Contents
6.6 Deactivated state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7 Anticollision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.1 Description of an anticollision sequence . . . . . . . . . . . . . . . . . . . . . . . . . 25
8 Anti-clone function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
9 SRIX4K commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
9.1 Initiate() command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
9.2 Pcall16() command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
9.3 Slot_marker(SN) command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
9.4 Select(Chip_ID) command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
9.5 Completion() command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
9.6 Reset_to_inventory() command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
9.7 Read_block(Addr) command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
9.8 Write_block (Addr, Data) command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
9.9 Get_UID() command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
9.10 Power-on state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
10 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
11 DC and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
12 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Appendix A ISO 14443 Type B CRC calculation . . . . . . . . . . . . . . . . . . . . . . . . . 44
Appendix B SRIX4K command summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Doc 8887 Rev 9 3/48
List of tables SRIX4K
List of tables
Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 2. Bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 3. Standard anticollision sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 4. Command code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 5. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 6. Operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 7. DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 8. AC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 9. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 10. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4/48 Doc 8887 Rev 9
SRIX4K List of figures
List of figures
Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 2. Die floor plan. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 3. 10% ASK modulation of the received wave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 4. SRIX4K request frame character format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 5. Request start of frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 6. Request end of frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 7. Wave transmitted using BPSK subcarrier modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 8. Answer start of frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 9. Answer end of frame. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 10. Example of a complete transmission frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 11. CRC transmission rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 12. SRIX4K memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 13. Resettable OTP area (addresses 0 to 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 14. Write_block update in Standard mode (binary format) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 15. Write_block update in Reload mode (binary format). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 16. Binary counter (addresses 5 to 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 17. Count down example (binary format) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 18. EEPROM (addresses 7 to 127) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 19. System area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 20. State transition diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 21. SRIX4K Chip_ID description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 22. Description of a possible anticollision sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 23. Example of an anticollision sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 24. Initiate request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 25. Initiate response format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 26. Initiate frame exchange between reader and SRIX4K . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 27. Pcall16 request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 28. Pcall16 response format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 29. Pcall16 frame exchange between reader and SRIX4K . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 30. Slot_marker request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 31. Slot_marker response format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 32. Slot_marker frame exchange between reader and SRIX4K. . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 33. Select request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 34. Select response format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 35. Select frame exchange between reader and SRIX4K . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 36. Completion request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 37. Completion response format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 38. Completion frame exchange between reader and SRIX4K . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 39. Reset_to_inventory request format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 40. Reset_to_inventory response format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 41. Reset_to_inventory frame exchange between reader and SRIX4K . . . . . . . . . . . . . . . . . . 35
Figure 42. Read_block request format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 43. Read_block response format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 44. Read_block frame exchange between reader and SRIX4K . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 45. Write_block request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 46. Write_block response format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 47. Write_block frame exchange between reader and SRIX4K . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 48. Get_UID request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Doc 8887 Rev 9 5/48
List of figures SRIX4K
Figure 49. Get_UID response format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 50. 64-bit unique identifier of the SRIX4K. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 51. Get_UID frame exchange between reader and SRIX4K . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 52. SRIX4K synchronous timing, transmit and receive. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 53. Initiate frame exchange between reader and SRIX4K . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 54. Pcall16 frame exchange between reader and SRIX4K . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 55. Slot_marker frame exchange between reader and SRIX4K. . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 56. Select frame exchange between reader and SRIX4K . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 57. Completion frame exchange between reader and SRIX4K . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 58. Reset_to_inventory frame exchange between reader and SRIX4K . . . . . . . . . . . . . . . . . . 46
Figure 59. Read_block frame exchange between reader and SRIX4K . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 60. Write_block frame exchange between reader and SRIX4K . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 61. Get_UID frame exchange between reader and SRIX4K . . . . . . . . . . . . . . . . . . . . . . . . . . 46
6/48 Doc 8887 Rev 9
SRIX4K Description
AI06829
AC1
SRIX4K
AC0
Power
Supply
Regulator
BPSK
Load
Modulator
ASK
Demodulator
4 Kbit
User
EEPROM
1 Description
The SRIX4K is a contactless memory, powered by an externally transmitted radio wave. It
contains a 4096-bit user EEPROM. The memory is organized as 128 blocks of 32 bits. The
SRIX4K is accessed via the 13.56 MHz carrier. Incoming data are demodulated and
decoded from the received amplitude shift keying (ASK) modulation signal and outgoing
data are generated by load variation using bit phase shift keying (BPSK) coding of a 847
kHz subcarrier. The received ASK wave is 10% modulated. The data transfer rate between
the SRIX4K and the reader is 106 Kbit/s in both reception and emission modes.
The SRIX4K follows the ISO 14443-2 Type B recommendation for the radio-frequency
power and signal interface.
Figure 1. Logic diagram
The SRIX4K is specifically designed for short range applications that need secure and reusable products. The SRIX4K includes an anticollision mechanism that allows it to detect
and select tags present at the same time within range of the reader. The anticollision is
based on a probabilistic scanning method using slot markers. The SRIX4K provides an anticlone function which allows its authentication. Using the STMicroelectronics single chip
coupler, CRX14, it is easy to design a reader with the authentication capability and to build a
system with a high level of security.
Table 1. Signal names
AC1 Antenna coil
AC0 Antenna coil
Signal name Description
Doc 8887 Rev 9 7/48
Signal description SRIX4K
AI09055
AC1AC0
The SRIX4K contactless EEPROM can be randomly read and written in block mode (each
block containing 32 bits). The instruction set includes the following ten commands:
● Read_block
● Write_block
● Initiate
● Pcall16
● Slot_marker
● Select
● Completion
● Reset_to_inventory
● Authenticate
● Get_UID
The SRIX4K memory is organized in three areas, as described in Figure 12. The first area is
a resettable OTP (one time programmable) area in which bits can only be switched from 1 to
0. Using a special command, it is possible to erase all bits of this area to 1. The second area
provides two 32-bit binary counters which can only be decremented from FFFF FFFFh to
0000 0000h, and gives a capacity of 4,294,967,296 units per counter. The last area is the
EEPROM memory. It is accessible by block of 32 bits and includes an auto-erase cycle
during each Write_block command.
Figure 2. Die floor plan
2 Signal description
2.0.1 AC1, AC0
The pads for the antenna coil. AC1 and AC0 must be directly bonded to the antenna.
8/48 Doc 8887 Rev 9
SRIX4K Data transfer
DATA BIT TO TRANSMIT
TO THE
10% ASK MODULATION
OF THE 13.56MHz WAVE,
GENERATED BY THE READER
Transfer time for one data bit is 1/106 kHz
SRIX4K
AI05729
ai07664
1 ETU
Start
"0"
Stop
"1"
MSbLSb Information Byte
b0 b1 b2 b3 b4 b5 b6 b7 b8 b9
3 Data transfer
3.1 Input data transfer from the reader to the SRIX4K (request frame)
The reader must generate a 13.56 MHz sinusoidal carrier frequency at its antenna, with
enough energy to “remote-power” the memory. The energy received at the SRIX4K’s
antenna is transformed into a supply voltage by a regulator, and into data bits by the ASK
demodulator. For the SRIX4K to decode correctly the information it receives, the reader
must 10% amplitude-modulate the 13.56 MHz wave before sending it to the SRIX4K. This is
represented in Figure 3. The data transfer rate is 106 Kbits/s.
Figure 3. 10% ASK modulation of the received wave
3.1.1 Character transmission format for request frame
The SRIX4K transmits and receives data bytes as 10-bit characters, with the least
significant bit (b
(elementary time unit), is equal to 9.44 µs (1/106 kHz).
These characters, framed by a start of frame (SOF) and an end of frame (EOF), are put
together to form a command frame as shown in Figure 10. A frame includes an SOF,
commands, addresses, data, a CRC and an EOF as defined in the ISO 14443-3 Type B
Standard. If an error is detected during data transfer, the SRIX4K does not execute the
command, but it does not generate an error frame.
Figure 4. SRIX4K request frame character format
) transmitted first, as shown in Figure 4. Each bit duration, an ETU
0
Doc 8887 Rev 9 9/48
Data transfer SRIX4K
ai07665
ETU
b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11
000000000011
ai07666
ETU
b0 b1 b2 b3 b4 b5 b6 b7 b8 b9
0000000000
Table 2. Bit description
Bit Description Value
b
0
b1 to b
b
9
Start bit used to synchronize the transmission b0 = 0
Information byte (command, address or data)
8
Stop bit used to indicate the end of a character b9 = 1
3.1.2 Request start of frame
The SOF described in Figure 5 is composed of:
● one falling edge,
● followed by 10 ETUs at logic-0,
● followed by a single rising edge,
● followed by at least 2 ETUs (and at most 3) at logic-1.
Figure 5. Request start of frame
The information byte is sent with the
least significant bit first
3.1.3 Request end of frame
The EOF shown in Figure 6 is composed of:
● one falling edge,
● followed by 10 ETUs at logic-0,
● followed by a single rising edge.
Figure 6. Request end of frame
10/48 Doc 8887 Rev 9
SRIX4K Data transfer
Or
AI05730
Data Bit to be Transmitted
to the Reader
847kHz BPSK Modulation
Generated by the SRIX4K
BPSK Modulation at 847kHz
During a One-bit Data Transfer Time (1/106kHz)
ai07665
ETU
b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11
000000000011
3.2 Output data transfer from the SRIX4K to the reader (answer frame)
The data bits issued by the SRIX4K use retro-modulation. Retro-modulation is obtained by
modifying the SRIX4K current consumption at the antenna (load modulation). The load
modulation causes a variation at the reader antenna by inductive coupling. With appropriate
detector circuitry, the reader is able to pick up information from the SRIX4K. To improve
load-modulation detection, data is transmitted using a BPSK encoded, 847 kHz subcarrier
frequency ƒ
Figure 7. Wave transmitted using BPSK subcarrier modulation
as shown in Figure 7, and as specified in the ISO 14443-2 Type B Standard.
s
3.2.1 Character transmission format for answer frame
3.2.2 Answer start of frame
The character format is the same as for input data transfer (Figure 4). The transmitted
frames are made up of an SOF, data, a CRC and an EOF (Figure 10). As with an input data
transfer, if an error occurs, the reader does not issue an error code to the SRIX4K, but it
should be able to detect it and manage the situation. The data transfer rate is
106 Kbits/second.
The SOF described in Figure 8 is composed of:
● followed by 10 ETUs at logic-0
● followed by 2 ETUs at logic-1
Figure 8. Answer start of frame
Doc 8887 Rev 9 11/48
Data transfer SRIX4K
ai07665
ETU
b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11
000000000011
12 bits
10 bits
Sync
128/fs
128/fs
fs=847.5kHz
t
DR
t
0
t
1
SOF
Cmd
Data CRC CRC
EOF
10 bits 10 bits 10 bits 10 bits
12 bits
10 bits 10 bits 10 bits
Data CRC CRC
SOF
EOF
12 bits
SOF
t
2
AI05731
Input data transfer using ASK Output data transfer using BPSK
Sent by the
Reader
Sent by the
SRIX4K
at 106kb/s
3.2.3 Answer end of frame
The EOF shown in Figure 9 is composed of:
● followed by 10 ETUs at logic-0,
● followed by 2 ETUs at logic-1.
Figure 9. Answer end of frame
3.3 Transmission frame
Between the request data transfer and the Answer data transfer, all ASK and BPSK
modulations are suspended for a minimum time of t
to switch from Transmission to Reception mode. It is repeated after each frame. After t
13.56 MHz carrier frequency is modulated by the SRIX4K at 847 kHz for a period of
t
=128/ƒS to allow the reader to synchronize. After t1, the first phase transition generated
1
by the SRIX4K forms the start bit (‘0’) of the Answer SOF. After the falling edge of the
Answer EOF, the reader waits a minimum time, t
the SRIX4K.
= 128/ƒS. This delay allows the reader
0
0
, before sending a new request frame to
2
, the
Figure 10. Example of a complete transmission frame
12/48 Doc 8887 Rev 9
SRIX4K Data transfer
CRC 16 (8 bits) CRC 16 (8 bits)
LSbit MSbit LSbit MSbit
LSByte MSByte
ai07667
3.4 CRC
The 16-bit CRC used by the SRIX4K is generated in compliance with the ISO 14443 Type B
recommendation. For further information, please see Appendix A. The initial register
contents are all 1s: FFFFh.
The two-byte CRC is present in every request and in every answer frame, before the EOF.
The CRC is calculated on all the bytes between SOF (not included) and the CRC field.
Upon reception of a request from a reader, the SRIX4K verifies that the CRC value is valid.
If it is invalid, the SRIX4K discards the frame and does not answer the reader.
Upon reception of an Answer from the SRIX4K, the reader should verify the validity of the
CRC. In case of error, the actions to be taken are the reader designer’s responsibility.
The CRC is transmitted with the least significant byte first and each byte is transmitted with
the least significant bit first.
Figure 11. CRC transmission rules
Doc 8887 Rev 9 13/48
Memory mapping SRIX4K
4 Memory mapping
The SRIX4K is organized as 128 blocks of 32 bits as shown in Figure 12. All blocks are
accessible by the Read_block command. Depending on the write access, they can be
updated by the Write_block command. A Write_block updates all the 32 bits of the block.
Figure 12. SRIX4K memory mapping
Block
Addr
Msb 32-bit block Lsb
b
31
b
24 b23
b16 b
15
0 32 bits Boolean area
1 32 bits Boolean area
2 32 bits Boolean area
3 32 bits Boolean area
4 32 bits Boolean area
5 32 bits binary counter
6 32 bits binary counter
7 User area
8 User area
9 User area
10 User area
11 User area
12 User area
13 User area
14 User area
15 User area
16 User area
b8 b
7
b
Description
0
Resettable OTP
bits
Count down
counter
Lockable
EEPROM
127 User area
255 OTP_Lock_Reg ST Reserved
UID0
64 bits UID area ROM
UID1
14/48 Doc 8887 Rev 9
Fixed Chip_ID
(Option)
EEPROM... User area
System OTP bits
SRIX4K Memory mapping
Block
address
MSb
b31
32-bit block
b16 b15b24 b23 b8 b7
LSb
b0
Description
Resettable
OTP bit
0
1
2
3
4
32-bit Boolean area
32-bit Boolean area
32-bit Boolean area
32-bit Boolean area
32-bit Boolean area
ai07657b
ai07658
1 ... 1 1 01011111 0 11
1 ... 1 0 01011001 1 11
1 ... 1 0 01011001 0 11
Previous data stored in block
Data to be written
New data stored in block
b31 b0
4.1 Resettable OTP area
In this area contains five individual 32-bit Boolean words (see Figure 13 for a map of the
area). A Write_block command will not erase the previous contents of the block as the write
cycle is not preceded by an auto-erase cycle. This feature can be used to reset selected bits
from 1 to 0. All bits previously at 0 remain unchanged. When the 32 bits of a block are all at
0, the block is empty, and cannot be updated any more. See Figure 14 and Figure 15 for
examples of the result of the Write_block command in the resettable OTP area.
Figure 13. Resettable OTP area (addresses 0 to 4)
Figure 14. Write_block update in Standard mode (binary format)
The five 32-bit blocks making up the resettable OTP area can be erased in one go by adding
an auto-erase cycle to the Write_block command. An auto-erase cycle is added each time
the SRIX4K detects a Reload command. The Reload command is implemented through a
specific update of the 32-bit binary counter located at block address 6 (see Section 4.2: 32-
bit binary counters for details).
Doc 8887 Rev 9 15/48
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