ST SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3 User Manual

SPC560P34L1, SPC560P34L3
SPC560P40L1, SPC560P40L3

32-bit Power Architecture® based MCU with 320 KB Flash memory

and 20 KB RAM for automotive chassis and safety applications

Features

■ Up to 64 MHz, single issue, 32-bit CPU core

complex (e200z0h)
– Compliant with Power Architecture

embedded category

– Variable Length Encoding (VLE)

■ Memory organization

– Up to 256 KB on-chip code flash memory

with ECC and erase/program controller

– Additional 64 (4 × 16) KB on-chip data

flash memory with ECC for EEPROM
emulation

– Up to 20 KB on-chip SRAM with ECC

■ Fail-safe protection

– Programmable watchdog timer
– Non-maskable interrupt
– Fault collection unit

■ Nexus Class 1 interface

■ Interrupts and events

– 16-channel eDMA controller
– 16 priority level controller
– Up to 25 external interrupts
– PIT implements four 32-bit timers
– 120 interrupts are routed via INTC

■ 1 general purpose eTimer unit

– 6 timers each with up/down capabilities
– 16-bit resolution, cascadable counters
– Quadrature decode with rotation direction

flag

– Double buffer input capture and output

compare

■ GPIO (37 on LQFP64; 64 on LQFP100)

individually programmable as I/O or special
function

■ Communications interfaces

– 2 LINFlex channels (1× Master/Slave, 1×

Master only)

®

LQFP100 (14 x 14 x 1.4 mm)

– Up to 3 DSPI channels with automatic chip

LQFP64 (10 x 10 x 1.4 mm

select generation (up to 8/4/4 chip selects)

– Up to 2 FlexCAN interface (2.0B Active)

with 32 message buffers

– 1 safety port based on FlexCAN with 32

message buffers and up to 8 Mbit/s at
64 MHz capability usable as second CAN
when not used as safety port

■ One 10-bit analog-to-digital converter (ADC)

– Up to 16 input channels (16 on LQFP100 /

12 on LQFP64)

– Conversion time < 1 µs including sampling

time at full precision
– Programmable Cross Triggering Unit (CTU)
– 4 analog watchdogs with interrupt

capability

■ On-chip CAN/UART bootstrap loader with Boot

Assist Module (BAM)

■ 1 FlexPWM unit: 8 complementary or

independent outputs with ADC synchronization
signals

Table 1. Device summary

Package

LQFP100 SPC560P34L3 SPC560P40L3

LQFP64 SPC560P34L1 SPC560P40L1

192 Kbyte

Code Flash

256 Kbyte

Code Flash

December 2011 Doc ID 16100 Rev 5 1/103

www.st.com

1

Contents SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3

Contents

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.1 Document overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.3 Device comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

1.5 Feature details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

1.5.1 High performance e200z0 core processor . . . . . . . . . . . . . . . . . . . . . . . 13

1.5.2 Crossbar switch (XBAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

1.5.3 Enhanced direct memory access (eDMA) . . . . . . . . . . . . . . . . . . . . . . . 14

1.5.4 Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

1.5.5 Static random access memory (SRAM) . . . . . . . . . . . . . . . . . . . . . . . . . 15

1.5.6 Interrupt controller (INTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

1.5.7 System status and configuration module (SSCM) . . . . . . . . . . . . . . . . . 16

1.5.8 System clocks and clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

1.5.9 Frequency-modulated phase-locked loop (FMPLL) . . . . . . . . . . . . . . . . 17

1.5.10 Main oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

1.5.11 Internal RC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

1.5.12 Periodic interrupt timer (PIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

1.5.13 System timer module (STM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

1.5.14 Software watchdog timer (SWT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

1.5.15 Fault collection unit (FCU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

1.5.16 System integration unit – Lite (SIUL) . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

1.5.17 Boot and censorship . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

1.5.18 Error correction status module (ECSM) . . . . . . . . . . . . . . . . . . . . . . . . . 19

1.5.19 Peripheral bridge (PBRIDGE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

1.5.20 Controller area network (FlexCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

1.5.21 Safety port (FlexCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

1.5.22 Serial communication interface module (LINFlex) . . . . . . . . . . . . . . . . . 22

1.5.23 Deserial serial peripheral interface (DSPI) . . . . . . . . . . . . . . . . . . . . . . 22

1.5.24 Pulse width modulator (FlexPWM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

1.5.25 eTimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

1.5.26 Analog-to-digital converter (ADC) module . . . . . . . . . . . . . . . . . . . . . . . 25

1.5.27 Cross triggering unit (CTU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

1.5.28 Nexus Development Interface (NDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

2/103 Doc ID 16100 Rev 5

SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3 Contents

1.5.29 Cyclic redundancy check (CRC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

1.5.30 IEEE 1149.1 JTAG controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

1.5.31 On-chip voltage regulator (VREG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

2 Package pinouts and signal descriptions . . . . . . . . . . . . . . . . . . . . . . . 29

2.1 Package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

2.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

2.2.1 Power supply and reference voltage pins . . . . . . . . . . . . . . . . . . . . . . . 32

2.2.2 System pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

2.2.3 Pin multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

3.2 Parameter classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

3.3 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

3.4 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

3.5 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

3.5.1 Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

3.5.2 General notes for specifications at maximum junction temperature . . . 52

3.6 Electromagnetic interference (EMI) characteristics . . . . . . . . . . . . . . . . . 54

3.7 Electrostatic discharge (ESD) characteristics . . . . . . . . . . . . . . . . . . . . . 54

3.8 Power management electrical characteristics . . . . . . . . . . . . . . . . . . . . . 54

3.8.1 Voltage regulator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . 54

3.8.2 Voltage monitor electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . 56

3.9 Power up/down sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

3.10 DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

3.10.1 NVUSRO register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

3.10.2 DC electrical characteristics (5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

3.10.3 DC electrical characteristics (3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

3.10.4 Input DC electrical characteristics definition . . . . . . . . . . . . . . . . . . . . . 63

3.10.5 I/O pad current specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

3.11 Main oscillator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 64

3.12 FMPLL electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

3.13 16 MHz RC oscillator electrical characteristics . . . . . . . . . . . . . . . . . . . . 67

3.14 Analog-to-digital converter (ADC) electrical characteristics . . . . . . . . . . . 67

Doc ID 16100 Rev 5 3/103

Contents SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3

3.14.1 Input impedance and ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

3.14.2 ADC conversion characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

3.15 Flash memory electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 73

3.15.1 Program/Erase characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

3.15.2 Flash memory power supply DC characteristics . . . . . . . . . . . . . . . . . . 75

3.15.3 Start-up/Switch-off timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

3.16 AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

3.16.1 Pad AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

3.17 AC timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

3.17.1 RESET pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

3.17.2 IEEE 1149.1 interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

3.17.3 Nexus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

3.17.4 External interrupt timing (IRQ pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

3.17.5 DSPI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

4 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

4.1 ECOPACK® . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

4.2 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

4.2.1 LQFP100 mechanical outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . 92

4.2.2 LQFP64 mechanical outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

5 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Appendix A Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

4/103 Doc ID 16100 Rev 5

SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3 List of tables

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. SPC560P34/SPC560P40 device comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 3. SPC560P40 device configuration differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 4. SPC560P34/SPC560P40 series block summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 5. Supply pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 6. System pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 7. Pin muxing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 8. Parameter classifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 9. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 10. Recommended operating conditions (5.0 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Table 11. Recommended operating conditions (3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 12. LQFP thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Table 13. EMI testing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Table 14. ESD ratings, . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Table 15. Approved NPN ballast components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Table 16. Voltage regulator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Table 17. Low voltage monitor electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Table 18. PAD3V5V field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Table 19. DC electrical characteristics (5.0 V, NVUSRO[PAD3V5V] = 0) . . . . . . . . . . . . . . . . . . . . . 60

Table 20. Supply current (5.0 V, NVUSRO[PAD3V5V] = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Table 21. DC electrical characteristics (3.3 V, NVUSRO[PAD3V5V] = 1) . . . . . . . . . . . . . . . . . . . . . 61

Table 22. Supply current (3.3 V, NVUSRO[PAD3V5V] = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Table 23. I/O supply segment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Table 24. I/O consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Table 25. Main oscillator output electrical characteristics (5.0 V, NVUSRO[PAD3V5V] = 0) . . . . . . . 65

Table 26. Main oscillator output electrical characteristics (3.3 V, NVUSRO[PAD3V5V] = 1) . . . . . . . 65

Table 27. Input clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Table 28. FMPLL electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Table 29. 16 MHz RC oscillator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Table 30. ADC conversion characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Table 31. Program and erase specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Table 32. Flash memory module life. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Table 33. Flash memory read access timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Table 34. Flash memory power supply DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 75

Table 35. Start-up time/Switch-off time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Table 36. Output pin transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Table 37. RESET electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Table 38. JTAG pin AC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Table 39. Nexus debug port timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Table 40. External interrupt timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Table 41. DSPI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Table 42. LQFP100 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Table 43. LQFP64 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Table 44. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Doc ID 16100 Rev 5 5/103

List of figures SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3

List of figures

Figure 1. Block diagram (SPC560P40 full-featured configuration) . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 2. 64-pin LQFP pinout – Full featured configuration (top view) . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 3. 64-pin LQFP pinout – airbag configuration (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 4. 100-pin LQFP pinout – full featured configuration (top view) . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 5. 100-pin LQFP pinout – airbag configuration (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 6. Power supplies constraints (–0.3 V ≤ V
Figure 7. Independent ADC supply (–0.3 V ≤ V
Figure 8. Power supplies constraints (3.0 V ≤ V
Figure 9. Independent ADC supply (3.0 V ≤ V

DD_HV_IOx

DD_HV_REG

DD_HV_IOx

DD_HV_REG

Figure 10. Voltage regulator configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Figure 11. Power-up typical sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Figure 12. Power-down typical sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Figure 13. Brown-out typical sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Figure 14. Input DC electrical characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Figure 15. ADC characteristics and error definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Figure 16. Input equivalent circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Figure 17. Transient behavior during sampling phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Figure 18. Spectral representation of input signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Figure 19. Pad output delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Figure 20. Start-up reset requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Figure 21. Noise filtering on reset signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Figure 22. JTAG test clock input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Figure 23. JTAG test access port timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Figure 24. JTAG boundary scan timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Figure 25. Nexus output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Figure 26. Nexus event trigger and test clock timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Figure 27. Nexus TDI, TMS, TDO timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Figure 28. External interrupt timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Figure 29. DSPI classic SPI timing – Master, CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Figure 30. DSPI classic SPI timing – Master, CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Figure 31. DSPI classic SPI timing – Slave, CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Figure 32. DSPI classic SPI timing – Slave, CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Figure 33. DSPI modified transfer format timing – Master, CPHA = 0. . . . . . . . . . . . . . . . . . . . . . . . . 88

Figure 34. DSPI modified transfer format timing – Master, CPHA = 1. . . . . . . . . . . . . . . . . . . . . . . . . 89

Figure 35. DSPI modified transfer format timing – Slave, CPHA = 0. . . . . . . . . . . . . . . . . . . . . . . . . . 89

Figure 36. DSPI modified transfer format timing – Slave, CPHA = 1. . . . . . . . . . . . . . . . . . . . . . . . . . 90

Figure 37. DSPI PCS Strobe (PCSS) timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Figure 38. LQFP100 package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Figure 39. LQFP64 package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Figure 40. Commercial product code structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

≤ 6.0 V). . . . . . . . . . . . . . . . . . . . . . . . . 47

≤ 6.0 V) . . . . . . . . . . . . . . . . . . . . . . . . . 48

≤ 5.5 V). . . . . . . . . . . . . . . . . . . . . . . . . . 51

≤ 5.5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . 51

6/103 Doc ID 16100 Rev 5

SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3 Introduction

1 Introduction

1.1 Document overview

This document provides electrical specifications, pin assignments, and package diagrams
for the SPC560P34/40 series of microcontroller units (MCUs). It also describes the device
features and highlights important electrical and physical characteristics. For functional
characteristics, refer to the device reference manual.

1.2 Description

This 32-bit system-on-chip (SoC) automotive microcontroller family is the latest achievement
in integrated automotive application controllers. It belongs to an expanding range of
automotive-focused products designed to address chassis applications—specifically,
electrical hydraulic power steering (EHPS) and electric power steering (EPS)—as well as
airbag applications.

This family is one of a series of next-generation integrated automotive microcontrollers
based on the Power Architecture technology.

The advanced and cost-efficient host processor core of this automotive controller family
complies with the Power Architecture embedded category. It operates at speeds of up to
64 MHz and offers high performance processing optimized for low power consumption. It
capitalizes on the available development infrastructure of current Power Architecture
devices and is supported with software drivers, operating systems and configuration code to
assist with users implementations.

1.3 Device comparison

Ta bl e 2

and their features—relative to full-featured version—to enable a comparison among the
family members and an understanding of the range of functionality offered within this family.

Table 2. SPC560P34/SPC560P40 device comparison

provides a summary of different members of the SPC560P34/SPC560P40 family

Feature

Code flash memory (with ECC) 192 KB 256 KB

Data flash memory / EE option (with ECC) 64 KB

SRAM (with ECC) 12 KB 20 KB

Processor core 32-bit e200z0h

Instruction set VLE (variable length encoding)

CPU performance 0–64 MHz

FMPLL (frequency-modulated phase-locked loop)
module

INTC (interrupt controller) channels 120

PIT (periodic interrupt timer) 1 (with four 32-bit timers)

SPC560P34 SPC560P40

Full-featured

1

Doc ID 16100 Rev 5 7/103

Introduction SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3

Table 2. SPC560P34/SPC560P40 device comparison (continued)

Feature

eDMA (enhanced direct memory access)
channels

FlexCAN (controller area network) 1

Safety port No

SPC560P34 SPC560P40

Full-featured

16

(1)

(1),(2)

2

Yes (via second

FlexCAN module)

FCU (fault collection unit) Yes

CTU (cross triggering unit) Yes Yes

eTimer 1 (16-bit, 6 channels)

FlexPWM (pulse-width modulation) channels

8

(capture capabity not

supported)

(capture capability not

8

supported)

Analog-to-digital converter (ADC) 1 (10-bit, 16 channels)

LINFlex

2

(1 × Master/Slave,

1 × Master only)

(1 × Master/Slave,

2

1 × Master only)

DSPI (deserial serial peripheral interface) 2 3

CRC (cyclic redundancy check) unit Yes

Junction temperature sensor No

JTAG controller Yes

Nexus port controller (NPC) Yes (Nexus Class 1)

Digital power supply

(3)

3.3 V or 5 V single supply with external transistor

Analog power supply 3.3 V or 5 V

Supply

Internal RC oscillator 16 MHz

External crystal oscillator 4–40 MHz

Packages

LQFP64

LQFP100

Temperature Standard ambient temperature –40 to 125 °C

1. Each FlexCAN module has 32 message buffers.

2. One FlexCAN module can act as a safety port with a bit rate as high as 8 Mbit/s at 64 MHz.

3. The different supply voltages vary according to the part number ordered.

SPC560P34/SPC560P40 is available in two configurations having different features: Full­featured and airbag.

Ta bl e 3

shows the main differences between the two versions of the

SPC560P40 MCU.

8/103 Doc ID 16100 Rev 5

SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3 Introduction

Table 3.

SRAM (with ECC) 16 KB 20 KB

FlexCAN (controller area network) 1 2

Safety port No

FlexPWM (pulse-width modulation) channels No

CTU (cross triggering unit) No Yes

SPC560P40 device configuration differences

Feature

Configuration

Airbag Full-featured

Ye s

(via second FlexCAN module)

8

(capture capability not

supported)

1.4 Block diagram

Figure 1

summarizes the functions of the blocks.

shows a top-level block diagram of the SPC560P34/SPC560P40 MCU.

Ta bl e 4

Doc ID 16100 Rev 5 9/103

Introduction SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3

Figure 1. Block diagram (SPC560P40 full-featured configuration)

External ballast

1.2 V regulator
control

XOSC

16 MHz

RC oscillator

FMPLL_0

(System)

JTAG

Nexus port

controller

eDMA

eDMA

16 channels

16 channels

Master

e200z0 Core

32-bit

general

purpose

registers

Integer

execu tion

unit

Nexus 1

Instruction

32-bit

Master

Crossbar switch (XBAR, AMBA 2.0 v6 AHB)

Slave SlaveSlave

Special

purpose

registers

Instruction

unit

Branch

prediction

unit

Exception

handler

Var iable

length

encoded

instructions

Load/store

unit

Data
32-bit

Master

Interrupt

controller

Code Flash

(with ECC)

Legend:

ADC Analog-to-digital converter
BAM Boot assist module
CRC Cyclic redundancy check
CTU Cross triggering unit
DSPI Deserial serial peripheral interface
ECSM Error correction status module
eDMA Enhanced direct memory access
eTimer Enhanced timer
FCU Fault collection unit
Flash Flash memory
FlexCAN Controller area network
FlexPWM Flexible pulse width modulation
FMPLL Frequency-modulated phase-locked loop
INTC Interrupt controller
JTAG JTAG controller

Data Flash
(with ECC)

CTU

FlexPWM

SRAM

(with ECC)

ADC

(10 bit, 16 ch)

PIT

WKPU

Peripheral bridge

STM

CRC

SSCM

LINFlex Serial communication interface (LIN support)
MC_CGM Clock generation module
MC_ME Mode entry module
MC_PCU Power control unit
MC_RGM Reset generation module
PIT Periodic interrupt timer
SIUL System Integration unit Lite
SRAM Static random-access memory
SSCM System status and configuration module
STM System timer module
SWT Software watchdog timer
WKPU Wakeup unit
XOSC External oscillator
XBAR Crossbar switch

SWT

MC_RGM

3×

eTimer

DSPI

(6 ch)

MC_CGM

2×

MC_ME

LINFlex

SIUL

BAM

FlexCAN

Safety port

ECSM

FCU

10/103 Doc ID 16100 Rev 5

SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3 Introduction

Table 4. SPC560P34/SPC560P40 series block summary

Block Function

Analog-to-digital converter (ADC) Multi-channel, 10-bit analog-to-digital converter

Boot assist module (BAM)

Clock generation module
(MC_CGM)

Controller area network
(FlexCAN)

Cross triggering unit (CTU)

Crossbar switch (XBAR)

Block of read-only memory containing VLE code which is executed according to
the boot mode of the device

Provides logic and control required for the generation of system and peripheral
clocks

Supports the standard CAN communications protocol

Enables synchronization of ADC conversions with a timer event from the eMIOS
or from the PIT

Supports simultaneous connections between two master ports and three slave
ports; supports a 32-bit address bus width and a 32-bit data bus width

Cyclic redundancy check (CRC) CRC checksum generator

Deserial serial peripheral
interface (DSPI)

Enhanced direct memory access
(eDMA)

Provides a synchronous serial interface for communication with external
devices

Performs complex data transfers with minimal intervention from a host
processor via “

n

” programmable channels

Enhanced timer (eTimer) Provides enhanced programmable up/down modulo counting

Provides a myriad of miscellaneous control functions for the device including
Error correction status module
(ECSM)

program-visible information about configuration and revision levels, a reset

status register, wakeup control for exiting sleep modes, and optional features

such as information on memory errors reported by error-correcting codes

External oscillator (XOSC)

Provides an output clock used as input reference for FMPLL_0 or as reference

clock for specific modules depending on system needs

Fault collection unit (FCU) Provides functional safety to the device

Flash memory Provides non-volatile storage for program code, constants and variables

Frequency-modulated phase­locked loop (FMPLL)

Generates high-speed system clocks and supports programmable frequency

modulation

Interrupt controller (INTC) Provides priority-based preemptive scheduling of interrupt requests

JTAG controller

LINFlex controller

Provides the means to test chip functionality and connectivity while remaining

transparent to system logic when not in test mode

Manages a high number of LIN (Local Interconnect Network protocol)

messages efficiently with a minimum of CPU load

Provides a mechanism for controlling the device operational mode and mode

Mode entry module (MC_ME)

transition sequences in all functional states; also manages the power control

unit, reset generation module and clock generation module, and holds the

configuration, control and status registers accessible for applications

Periodic interrupt timer (PIT) Produces periodic interrupts and triggers

Peripheral bridge (PBRIDGE) Is the interface between the system bus and on-chip peripherals

Power control unit (MC_PCU)

Reduces the overall power consumption by disconnecting parts of the device

from the power supply via a power switching device; device components are

grouped into sections called “power domains” which are controlled by the PCU

Doc ID 16100 Rev 5 11/103

Introduction SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3

Table 4. SPC560P34/SPC560P40 series block summary (continued)

Block Function

Pulse width modulator
(FlexPWM)

Reset generation module
(MC_RGM)

Static random-access memory
(SRAM)

Contains four PWM submodules, each of which capable of controlling a single

half-bridge power stage and two fault input channels

Centralizes reset sources and manages the device reset sequence of the

device

Provides storage for program code, constants, and variables

Provides control over all the electrical pad controls and up 32 ports with 16 bits
System integration unit lite (SIUL)

of bidirectional, general-purpose input and output signals and supports up to 32

external interrupts with trigger event configuration

System status and configuration
module (SSCM)

System timer module (STM)

Provides system configuration and status data (such as memory size and

status, device mode and security status), device identification data, debug

status port enable and selection, and bus and peripheral abort enable/disable

Provides a set of output compare events to support AUTOSAR

system tasks

System watchdog timer (SWT) Provides protection from runaway code

Supports up to 18 external sources that can generate interrupts or wakeup
Wakeup unit (WKPU)

events, of which 1 can cause non-maskable interrupt requests or wakeup

events

1. AUTOSAR: AUTomotive Open System ARchitecture (see www.autosar.org)

(1)

and operating

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SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3 Introduction

1.5 Feature details

1.5.1 High performance e200z0 core processor

The e200z0 Power Architecture core provides the following features:

● High performance e200z0 core processor for managing peripherals and interrupts

● Single issue 4-stage pipeline in-order execution 32-bit Power Architecture CPU

● Harvard architecture

● Variable length encoding (VLE), allowing mixed 16- and 32-bit instructions

– Results in smaller code size footprint

– Minimizes impact on performance

● Branch processing acceleration using lookahead instruction buffer

● Load/store unit

– 1-cycle load latency

– Misaligned access support

– No load-to-use pipeline bubbles

● Thirty-two 32-bit general purpose registers (GPRs)

● Separate instruction bus and load/store bus Harvard architecture

● Hardware vectored interrupt support

● Reservation instructions for implementing read-modify-write constructs

● Long cycle time instructions, except for guarded loads, do not increase interrupt latency

● Extensive system development support through Nexus debug port

● Non-maskable interrupt support

1.5.2 Crossbar switch (XBAR)

The XBAR multi-port crossbar switch supports simultaneous connections between three
master ports and three slave ports. The crossbar supports a 32-bit address bus width and a
32-bit data bus width.

The crossbar allows for two concurrent transactions to occur from any master port to any
slave port; but one of those transfers must be an instruction fetch from internal flash
memory. If a slave port is simultaneously requested by more than one master port,
arbitration logic will select the higher priority master and grant it ownership of the slave port.
All other masters requesting that slave port will be stalled until the higher priority master
completes its transactions. Requesting masters will be treated with equal priority and will be
granted access a slave port in round-robin fashion, based upon the ID of the last master to
be granted access.

Doc ID 16100 Rev 5 13/103

Introduction SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3

The crossbar provides the following features:

● 3 master ports:

– e200z0 core complex instruction port

– e200z0 core complex Load/Store Data port

–eDMA

● 3 slave ports:

– Flash memory (Code and Data)

–SRAM

– Peripheral bridge

● 32-bit internal address, 32-bit internal data paths

● Fixed Priority Arbitration based on Port Master

● Temporary dynamic priority elevation of masters

1.5.3 Enhanced direct memory access (eDMA)

The enhanced direct memory access (eDMA) controller is a second-generation module
capable of performing complex data movements via 16 programmable channels, with
minimal intervention from the host processor. The hardware micro architecture includes a
DMA engine which performs source and destination address calculations, and the actual
data movement operations, along with an SRAM-based memory containing the transfer
control descriptors (TCD) for the channels.

The eDMA module provides the following features:

● 16 channels support independent 8-, 16- or 32-bit single value or block transfers

● Supports variable-sized queues and circular queues

● Source and destination address registers are independently configured to either post-

increment or to remain constant

● Each transfer is initiated by a peripheral, CPU, or eDMA channel request

● Each eDMA channel can optionally send an interrupt request to the CPU on completion

of a single value or block transfer

● DMA transfers possible between system memories, DSPIs, ADC, FlexPWM, eTimer

and CTU

● Programmable DMA channel multiplexer allows assignment of any DMA source to any

available DMA channel with as many as 30 request sources

● eDMA abort operation through software

1.5.4 Flash memory

The SPC560P34/SPC560P40 provides 320 KB of programmable, non-volatile, flash
memory. The non-volatile memory (NVM) can be used for instruction and/or data storage.
The flash memory module is interfaced to the system bus by a dedicated flash memory
controller. It supports a 32-bit data bus width at the system bus port, and a 128-bit read data
interface to flash memory. The module contains four 128-bit wide prefetch buffers. Prefetch
buffer hits allow no-wait responses. Normal flash memory array accesses are registered and
are forwarded to the system bus on the following cycle, incurring two wait-states.

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SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3 Introduction

The flash memory module provides the following features:

● As much as 320 KB flash memory

– 6 blocks (32 KB + 2×16 KB + 32 KB + 32 KB + 128 KB) code flash memory

– 4 blocks (16 KB + 16 KB + 16 KB + 16 KB) data flash memory

– Full Read-While-Write (RWW) capability between code flash memory and data

flash memory

● Four 128-bit wide prefetch buffers to provide single cycle in-line accesses (prefetch

buffers can be configured to prefetch code or data or both)

● Typical flash memory access time: no wait-state for buffer hits, 2 wait-states for page

buffer miss at 64 MHz

● Hardware managed flash memory writes handled by 32-bit RISC Krypton engine

● Hardware and software configurable read and write access protections on a per-master

basis

● Configurable access timing allowing use in a wide range of system frequencies

● Multiple-mapping support and mapping-based block access timing (up to 31 additional

cycles) allowing use for emulation of other memory types

● Software programmable block program/erase restriction control

● Erase of selected block(s)

● Read page sizes

– Code flash memory: 128 bits (4 words)

– Data flash memory: 32 bits (1 word)

● ECC with single-bit correction, double-bit detection for data integrity

– Code flash memory: 64-bit ECC

– Data flash memory: 32-bit ECC

● Embedded hardware program and erase algorithm

● Erase suspend and program abort

● Censorship protection scheme to prevent flash memory content visibility

● Hardware support for EEPROM emulation

1.5.5 Static random access memory (SRAM)

The SPC560P34/SPC560P40 SRAM module provides up to 20 KB of general-purpose
memory.

The SRAM module provides the following features:

● Supports read/write accesses mapped to the SRAM from any master

● Up to 20 KB general purpose SRAM

● Supports byte (8-bit), half word (16-bit), and word (32-bit) writes for optimal use of

memory

● Typical SRAM access time: no wait-state for reads and 32-bit writes; 1 wait-state for 8-

and 16-bit writes if back-to-back with a read to same memory block

Doc ID 16100 Rev 5 15/103

Introduction SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3

1.5.6 Interrupt controller (INTC)

The interrupt controller (INTC) provides priority-based preemptive scheduling of interrupt
requests, suitable for statically scheduled hard real-time systems. The INTC handles 128
selectable-priority interrupt sources.

For high-priority interrupt requests, the time from the assertion of the interrupt request by
the peripheral to the execution of the interrupt service routine (ISR) by the processor has
been minimized. The INTC provides a unique vector for each interrupt request source for
quick determination of which ISR has to be executed. It also provides a wide number of
priorities so that lower priority ISRs do not delay the execution of higher priority ISRs. To
allow the appropriate priorities for each source of interrupt request, the priority of each
interrupt request is software configurable.

When multiple tasks share a resource, coherent accesses to that resource need to be
supported. The INTC supports the priority ceiling protocol (PCP) for coherent accesses. By
providing a modifiable priority mask, the priority can be raised temporarily so that all tasks
which share the same resource can not preempt each other.

The INTC provides the following features:

● Unique 9-bit vector for each separate interrupt source

● 8 software triggerable interrupt sources

● 16 priority levels with fixed hardware arbitration within priority levels for each interrupt

source

● Ability to modify the ISR or task priority: modifying the priority can be used to

implement the priority ceiling protocol for accessing shared resources.

● 1 external high priority interrupt (NMI) directly accessing the main core and I/O

processor (IOP) critical interrupt mechanism

1.5.7 System status and configuration module (SSCM)

The system status and configuration module (SSCM) provides central device functionality.

The SSCM includes these features:

● System configuration and status

– Memory sizes/status

– Device mode and security status

– Determine boot vector

– Search code flash for bootable sector

– DMA status

● Debug status port enable and selection

● Bus and peripheral abort enable/disable

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SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3 Introduction

1.5.8 System clocks and clock generation

The following list summarizes the system clock and clock generation on the
SPC560P34/SPC560P40:

● Lock detect circuitry continuously monitors lock status

● Loss of clock (LOC) detection for PLL outputs

● Programmable output clock divider (÷1, ÷2, ÷4, ÷8)

● FlexPWM module and eTimer module running at the same frequency as the e200z0h

core

● Internal 16 MHz RC oscillator for rapid start-up and safe mode: supports frequency

trimming by user application

1.5.9 Frequency-modulated phase-locked loop (FMPLL)

The FMPLL allows the user to generate high speed system clocks from a 4–40 MHz input
clock. Further, the FMPLL supports programmable frequency modulation of the system
clock. The PLL multiplication factor, output clock divider ratio are all software configurable.

The FMPLL has the following major features:

● Input clock frequency: 4–40 MHz

● Maximum output frequency: 64 MHz

● Voltage controlled oscillator (VCO)—frequency 256–512 MHz

● Reduced frequency divider (RFD) for reduced frequency operation without forcing the

FMPLL to relock

● Frequency-modulated PLL

– Modulation enabled/disabled through software

– Triangle wave modulation

● Programmable modulation depth (±0.25% to ±4% deviation from center frequency):

programmable modulation frequency dependent on reference frequency

● Self-clocked mode (SCM) operation

1.5.10 Main oscillator

The main oscillator provides these features:

● Input frequency range: 4–40 MHz

● Crystal input mode or oscillator input mode

● PLL reference

1.5.11 Internal RC oscillator

This device has an RC ladder phase-shift oscillator. The architecture uses constant current
charging of a capacitor. The voltage at the capacitor is compared by the stable bandgap
reference voltage.

Doc ID 16100 Rev 5 17/103

Introduction SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3

The RC oscillator provides these features:

● Nominal frequency 16 MHz

● ±5 % variation over voltage and temperature after process trim

● Clock output of the RC oscillator serves as system clock source in case loss of lock or

loss of clock is detected by the PLL

● RC oscillator is used as the default system clock during startup

1.5.12 Periodic interrupt timer (PIT)

The PIT module implements these features:

● 4 general-purpose interrupt timers

● 32-bit counter resolution

● Clocked by system clock frequency

● Each channel usable as trigger for a DMA request

1.5.13 System timer module (STM)

The STM implements these features:

● One 32-bit up counter with 8-bit prescaler

● Four 32-bit compare channels

● Independent interrupt source for each channel

● Counter can be stopped in debug mode

1.5.14 Software watchdog timer (SWT)

The SWT has the following features:

● 32-bit time-out register to set the time-out period

● Programmable selection of window mode or regular servicing

● Programmable selection of reset or interrupt on an initial time-out

● Master access protection

● Hard and soft configuration lock bits

● Reset configuration inputs allow timer to be enabled out of reset

1.5.15 Fault collection unit (FCU)

The FCU provides an independent fault reporting mechanism even if the CPU is
malfunctioning.

The FCU module has the following features:

● FCU status register reporting the device status

● Continuous monitoring of critical fault signals

● User selection of critical signals from different fault sources inside the device

● Critical fault events trigger 2 external pins (user selected signal protocol) that can be

used externally to reset the device and/or other circuitry (for example, a safety relay)

● Faults are latched into a register

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SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3 Introduction

1.5.16 System integration unit – Lite (SIUL)

The SPC560P34/SPC560P40 SIUL controls MCU pad configuration, external interrupt,
general purpose I/O (GPIO), and internal peripheral multiplexing.

The pad configuration block controls the static electrical characteristics of I/O pins. The
GPIO block provides uniform and discrete input/output control of the I/O pins of the MCU.

The SIUL provides the following features:

● Centralized general purpose input output (GPIO) control of up to 49 input/output pins

and 16 analog input-only pads (package dependent)

● All GPIO pins can be independently configured to support pull-up, pull-down, or no pull

● Reading and writing to GPIO supported both as individual pins and 16-bit wide ports

● All peripheral pins, except ADC channels, can be alternatively configured as both

general purpose input or output pins

● ADC channels support alternative configuration as general purpose inputs

● Direct readback of the pin value is supported on all pins through the SIUL

● Configurable digital input filter that can be applied to some general purpose input pins

for noise elimination

● Up to 4 internal functions can be multiplexed onto 1 pin

1.5.17 Boot and censorship

Different booting modes are available in the SPC560P34/SPC560P40: booting from internal
flash memory and booting via a serial link.

The default booting scheme uses the internal flash memory (an internal pull-down resistor is
used to select this mode). Optionally, the user can boot via FlexCAN or LINFlex (using the
boot assist module software).

A censorship scheme is provided to protect the content of the flash memory and offer
increased security for the entire device.

A password mechanism is designed to grant the legitimate user access to the non-volatile
memory.

Boot assist module (BAM)

The BAM is a block of read-only memory that is programmed once and is identical for all
SPC560Pxx devices that are based on the e200z0h core. The BAM program is executed
every time the device is powered on if the alternate boot mode has been selected by the
user.

The BAM provides the following features:

● Serial bootloading via FlexCAN or LINFlex

● Ability to accept a password via the used serial communication channel to grant the

legitimate user access to the non-volatile memory

1.5.18 Error correction status module (ECSM)

The ECSM provides a myriad of miscellaneous control functions regarding program-visible
information about the platform configuration and revision levels, a reset status register, a
software watchdog timer, wakeup control for exiting sleep modes, and information on

Doc ID 16100 Rev 5 19/103

Introduction SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3

platform memory errors reported by error-correcting codes and/or generic access error
information for certain processor cores.

The Error Correction Status Module supports a number of miscellaneous control functions
for the platform. The ECSM includes these features:

● Registers for capturing information on platform memory errors if error-correcting codes

(ECC) are implemented

● For test purposes, optional registers to specify the generation of double-bit memory

errors are enabled on the SPC560P34/SPC560P40.

The sources of the ECC errors are:

● Flash memory

● SRAM

1.5.19 Peripheral bridge (PBRIDGE)

The PBRIDGE implements the following features:

● Duplicated periphery

● Master access privilege level per peripheral (per master: read access enable; write

access enable)

● Write buffering for peripherals

● Checker applied on PBRIDGE output toward periphery

● Byte endianess swap capability

1.5.20 Controller area network (FlexCAN)

The SPC560P34/SPC560P40 MCU contains one controller area network (FlexCAN)
module. This module is a communication controller implementing the CAN protocol
according to Bosch Specification version 2.0B. The CAN protocol was designed to be used
primarily as a vehicle serial data bus, meeting the specific requirements of this field: real­time processing, reliable operation in the EMI environment of a vehicle, cost-effectiveness
and required bandwidth. The FlexCAN module contains 32 message buffers.

20/103 Doc ID 16100 Rev 5

SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3 Introduction

The FlexCAN module provides the following features:

● Full implementation of the CAN protocol specification, version 2.0B

– Standard data and remote frames

– Extended data and remote frames

– Up to 8-bytes data length

– Programmable bit rate up to 1 Mbit/s

● 32 message buffers of up to 8-bytes data length

● Each message buffer configurable as Rx or Tx, all supporting standard and extended

messages

● Programmable loop-back mode supporting self-test operation

● 3 programmable mask registers

● Programmable transmit-first scheme: lowest ID or lowest buffer number

● Time stamp based on 16-bit free-running timer

● Global network time, synchronized by a specific message

● Maskable interrupts

● Independent of the transmission medium (an external transceiver is assumed)

● High immunity to EMI

● Short latency time due to an arbitration scheme for high-priority messages

● Transmit features

– Supports configuration of multiple mailboxes to form message queues of scalable

depth

– Arbitration scheme according to message ID or message buffer number

– Internal arbitration to guarantee no inner or outer priority inversion

– Transmit abort procedure and notification

● Receive features

– Individual programmable filters for each mailbox

– 8 mailboxes configurable as a 6-entry receive FIFO

– 8 programmable acceptance filters for receive FIFO

● Programmable clock source

– System clock

– Direct oscillator clock to avoid PLL jitter

1.5.21 Safety port (FlexCAN)

The SPC560P34/SPC560P40 MCU has a second CAN controller synthesized to run at high
bit rates to be used as a safety port. The CAN module of the safety port provides the
following features:

● Identical to the FlexCAN module

● Bit rate up to 8 Mbit/s at 64 MHz CPU clock using direct connection between CAN

modules (no physical transceiver required)

● 32 message buffers of up to 8-bytes data length

● Can be used as a second independent CAN module

Doc ID 16100 Rev 5 21/103

Introduction SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3

1.5.22 Serial communication interface module (LINFlex)

The LINFlex (local interconnect network flexible) on the SPC560P34/SPC560P40 features
the following:

● Supports LIN Master mode (both instances), LIN Slave mode (only one instance) and

UART mode

● LIN state machine compliant to LIN1.3, 2.0 and 2.1 specifications

● Handles LIN frame transmission and reception without CPU intervention

● LIN features

– Autonomous LIN frame handling

– Message buffer to store Identifier and up to 8 data bytes

– Supports message length of up to 64 bytes

– Detection and flagging of LIN errors (sync field, delimiter, ID parity, bit framing,

checksum, and time-out)

– Classic or extended checksum calculation

– Configurable Break duration of up to 36-bit times

– Programmable baud rate prescalers (13-bit mantissa, 4-bit fractional)

– Diagnostic features: Loop back; Self Test; LIN bus stuck dominant detection

– Interrupt-driven operation with 16 interrupt sources

● LIN slave mode features:

– Autonomous LIN header handling

– Autonomous LIN response handling

– Optional discarding of irrelevant LIN responses using ID filter

● UART mode:

– Full-duplex operation

– Standard non return-to-zero (NRZ) mark/space format

– Data buffers with 4-byte receive, 4-byte transmit

– Configurable word length (8-bit or 9-bit words)

– Error detection and flagging

– Parity, Noise and Framing errors

– Interrupt-driven operation with four interrupt sources

– Separate transmitter and receiver CPU interrupt sources

– 16-bit programmable baud-rate modulus counter and 16-bit fractional

– 2 receiver wake-up methods

1.5.23 Deserial serial peripheral interface (DSPI)

The deserial serial peripheral interface (DSPI) module provides a synchronous serial
interface for communication between the SPC560P34/SPC560P40 MCU and external
devices.

22/103 Doc ID 16100 Rev 5

SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3 Introduction

The DSPI modules provide these features:

● Full duplex, synchronous transfers

● Master or slave operation

● Programmable master bit rates

● Programmable clock polarity and phase

● End-of-transmission interrupt flag

● Programmable transfer baud rate

● Programmable data frames from 4 to 16 bits

● Up to 8 chip select lines available:

–8 on DSPI_0

– 4 each on DSPI_1 and DSPI_2

● 8 clock and transfer attributes registers

● Chip select strobe available as alternate function on one of the chip select pins for

deglitching

● FIFOs for buffering up to 4 transfers on the transmit and receive side

● Queueing operation possible through use of the I/O processor or eDMA

● General purpose I/O functionality on pins when not used for SPI

1.5.24 Pulse width modulator (FlexPWM)

The pulse width modulator module (PWM) contains four PWM submodules each of which is
set up to control a single half-bridge power stage. There are also three fault channels.

This PWM is capable of controlling most motor types: AC induction motors (ACIM),
permanent magnet AC motors (PMAC), both brushless (BLDC) and brush DC motors
(BDC), switched (SRM) and variable reluctance motors (VRM), and stepper motors.

Doc ID 16100 Rev 5 23/103

Introduction SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3

The FlexPWM block implements the following features:

● 16-bit resolution for center, edge-aligned, and asymmetrical PWMs

● Clock frequency same as that used for e200z0h core

● PWM outputs can operate as complementary pairs or independent channels

● Can accept signed numbers for PWM generation

● Independent control of both edges of each PWM output

● Synchronization to external hardware or other PWM supported

● Double buffered PWM registers

– Integral reload rates from 1 to 16

– Half cycle reload capability

● Multiple ADC trigger events can be generated per PWM cycle via hardware

● Write protection for critical registers

● Fault inputs can be assigned to control multiple PWM outputs

● Programmable filters for fault inputs

● Independently programmable PWM output polarity

● Independent top and bottom deadtime insertion

● Each complementary pair can operate with its own PWM frequency and deadtime

values

● Individual software-control for each PWM output

● All outputs can be programmed to change simultaneously via a “Force Out” event

● PWMX pin can optionally output a third PWM signal from each submodule

● Channels not used for PWM generation can be used for buffered output compare

functions

● Channels not used for PWM generation can be used for input capture functions

● Enhanced dual-edge capture functionality

● eDMA support with automatic reload

● 2 fault inputs

● Capture capability for PWMA, PWMB, and PWMX channels not supported

24/103 Doc ID 16100 Rev 5

SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3 Introduction

1.5.25 eTimer

The SPC560P34/SPC560P40 includes one eTimer module which provides six 16-bit
general purpose up/down timer/counter units with the following features:

● Clock frequency same as that used for the e200z0h core

● Individual channel capability

– Input capture trigger

– Output compare

– Double buffer (to capture rising edge and falling edge)

– Separate prescaler for each counter

– Selectable clock source

– 0–100% pulse measurement

– Rotation direction flag (quad decoder mode)

● Maximum count rate

– External event counting: max. count rate = peripheral clock/2

– Internal clock counting: max. count rate = peripheral clock

● Counters are:

– Cascadable

– Preloadable

● Programmable count modulo

● Quadrature decode capabilities

● Counters can share available input pins

● Count once or repeatedly

● Pins available as GPIO when timer functionality not in use

1.5.26 Analog-to-digital converter (ADC) module

The ADC module provides the following features:

Analog part:

● 1 on-chip analog-to-digital converter

– 10-bit AD resolution

– 1 sample and hold unit

– Conversion time, including sampling time, less than 1 µs (at full precision)

– Typical sampling time is 150 ns minimum (at full precision)

– DNL/INL ±1 LSB

–TUE <1.5LSB

– Single-ended input signal up to 3.3 V/5.0 V

– 3.3 V/5.0 V input reference voltage

– ADC and its reference can be supplied with a voltage independent from V

– ADC supply can be equal or higher than V

– ADC supply and ADC reference are not independent from each other (both

internally bonded to same pad)

– Sample times of 2 (default), 8, 64 or 128 ADC clock cycles

DDIO

DDIO

Doc ID 16100 Rev 5 25/103

Introduction SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3

Digital part:

● 16 input channels

● 4 analog watchdogs comparing ADC results against predefined levels (low, high,

range) before results are stored in the appropriate ADC result location

● 2 modes of operation: Motor Control mode or Regular mode

● Regular mode features

– Register based interface with the CPU: control register, status register and 1 result

register per channel

– ADC state machine managing 3 request flows: regular command, hardware

injected command and software injected command

– Selectable priority between software and hardware injected commands

– DMA compatible interface

● CTU-controlled mode features

– Triggered mode only

– 4 independent result queues (1×16 entries, 2×8 entries, 1×4 entries)

– Result alignment circuitry (left justified and right justified)

– 32-bit read mode allows to have channel ID on one of the 16-bit part

– DMA compatible interfaces

1.5.27 Cross triggering unit (CTU)

The cross triggering unit allows automatic generation of ADC conversion requests on user
selected conditions without CPU load during the PWM period and with minimized CPU load
for dynamic configuration.

It implements the following features:

● Double buffered trigger generation unit with up to 8 independent triggers generated

from external triggers

● Trigger generation unit configurable in sequential mode or in triggered mode

● Each trigger can be appropriately delayed to compensate the delay of external low

pass filter

● Double buffered global trigger unit allowing eTimer synchronization and/or ADC

command generation

● Double buffered ADC command list pointers to minimize ADC-trigger unit update

● Double buffered ADC conversion command list with up to 24 ADC commands

● Each trigger capable of generating consecutive commands

● ADC conversion command allows to control ADC channel, single or synchronous

sampling, independent result queue selection

1.5.28 Nexus Development Interface (NDI)

The NDI (Nexus Development Interface) block is compliant with Nexus Class 1 of the IEEE­ISTO 5001-2003 standard. This development support is supplied for MCUs without requiring
external address and data pins for internal visibility. The NDI block is an integration of
several individual Nexus blocks that are selected to provide the development support
interface for this device. The NDI block interfaces to the host processor and internal busses
to provide development support as per the IEEE-ISTO 5001-2003 Nexus Class 1 standard.

26/103 Doc ID 16100 Rev 5

SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3 Introduction

The development support provided includes access to the MCU’s internal memory map and
access to the processor’s internal registers.

The NDI provides the following features:

● Configured via the IEEE 1149.1

● All Nexus port pins operate at V

● Nexus Class 1 supports Static debug

(no dedicated power supply)

DDIO

1.5.29 Cyclic redundancy check (CRC)

The CRC computing unit is dedicated to the computation of CRC off-loading the CPU. The
CRC module features:

● Support for CRC-16-CCITT (

16

12

26

+

+

5

x

+ 1

23

x

+

–

x

+

x

● Support for CRC-32 (Ethernet protocol):

32

–

x

+

x

● Zero wait states for each write/read operations to the CRC_CFG and CRC_INP

x

25 protocol):

22

16

12

11

10

8

7

5

4

x

+

x

+

x

+

x

+

x

+

x

+

x

+

x

+

2

x

+

x

+ x + 1

registers at the maximum frequency

1.5.30 IEEE 1149.1 JTAG controller

The JTAG controller (JTAGC) block provides the means to test chip functionality and
connectivity while remaining transparent to system logic when not in test mode. All data
input to and output from the JTAGC block is communicated in serial format. The JTAGC
block is compliant with the IEEE standard.

The JTAG controller provides the following features:

● IEEE test access port (TAP) interface 4 pins (TDI, TMS, TCK, TDO)

● Selectable modes of operation include JTAGC/debug or normal system operation.

● 5-bit instruction register that supports the following IEEE 1149.1-2001 defined

instructions:

– BYPASS

– IDCODE

–EXTEST

– SAMPLE

– SAMPLE/PRELOAD

● 5-bit instruction register that supports the additional following public instructions:

– ACCESS_AUX_TAP_NPC

– ACCESS_AUX_TAP_ONCE

● 3 test data registers:

– Bypass register

– Boundary scan register (size parameterized to support a variety of boundary scan

chain lengths)

– Device identification register

● TAP controller state machine that controls the operation of the data registers,

instruction register and associated circuitry

Doc ID 16100 Rev 5 27/103

Introduction SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3

1.5.31 On-chip voltage regulator (VREG)

The on-chip voltage regulator module provides the following features:

● Uses external NPN (negative-positive-negative) transistor

● Regulates external 3.3 V/5.0 V down to 1.2 V for the core logic

● Low voltage detection on the internal 1.2 V and I/O voltage 3.3 V

28/103 Doc ID 16100 Rev 5

SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3 Package pinouts and signal descrip-

2 Package pinouts and signal descriptions

2.1 Package pinouts

The LQFP pinouts are shown in the following figures. For pin signal descriptions, please
refer to

Figure 2. 64-pin LQFP pinout – Full featured configuration (top view)

Ta bl e 7

VDD_HV_IO1

VSS_HV_IO1

VDD_HV_OSC

VSS_HV_OSC

VSS_LV_COR0
VDD_LV_COR0

.

RESET

NMI
A[6]
A[7]
A[8]
A[5]

D[9]

XTAL

EXTAL

D[8]

A[15]

A[14]

B[6]

A[13]

A[9]

VSS_LV_COR2

VDD_LV_COR2

C[8]

VSS_HV_IO3

VDD_HV_IO3

646362616059585756555453525150

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

LQFP64

A[12]

A[11]

A[10]

B[2]

B[1]

B[0]

49

A[4]

48

VPP TEST

47

D[14]]

46

D[12]

45

D[13

44

VSS_LV_COR1

43

VDD_LV_COR1

42

A[3]

41

VDD_HV_IO2

40

VSS_HV_IO2

39

TDO

38

TCK

37

TMS

36

TDI

35

C[12]

34

C[11]

33

171819202122232425

E[1]

B[7]

D[7]

C[1]

C[2]

B[8]

E[2]

B[9]

26272829303132

B[10]

B[11]

B[12]

E[3]/B[13]

VSS_HV_AD0

VDD_HV_AD0

BCTRL

VDD_HV_REG

Doc ID 16100 Rev 5 29/103

Package pinouts and signal descriptions SPC560P34L1, SPC560P34L3, SPC560P40L1,

Figure 3. 64-pin LQFP pinout – airbag configuration (top view)

A[15]

A[14]

B[6]

A[13]

A[9]

VSS_LV_COR2

VDD_LV_COR2

C[8]

VSS_HV_IO3

VDD_HV_IO3

A[12]

A[11]

A[10]

B[2]

B[1]]

B[0]

NMI

A[6]
A[7]
A[8]

A[5]
VDD_HV_IO1
VSS_HV_IO1

VDD_HV_OSC

VSS_HV_OSC

VSS_LV_COR0

VDD_LV_COR0

D[9]

XTAL

EXTAL

RESET

D[8]

646362616059585756555453525150

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

LQFP64

49

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33

A[4]
VPP TEST
D[14]
D[12]
D[13]
VSS_LV_COR1
VDD_LV_COR1
A[3]
VDD_HV_IO2
VSS_HV_IO2
TDO
TCK
TMS
TDI
C[12]
C[11]

171819202122232425

E[1]

B[7]

D[7]

C[1]

C[2]

B[8]

E[2]

B[9]

26272829303132

B[10]

B[11]

B[12]

VSS_HV_AD0

VDD_HV_AD0

BCTRL

E[3]/B[13]

VDD_HV_REG

30/103 Doc ID 16100 Rev 5

SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3 Package pinouts and signal descrip-

Figure 4. 100-pin LQFP pinout – full featured configuration (top view)

A[15]

A[14]

C[6]

D[2]

B[6]

A[13]

A[9]

VSS_LV_COR2

VDD_LV_COR2

C[8]

D[4]

D[3]

VSS_HV_IO3

VDD_HV_IO3

D[0]

C[15]

C[9]

A[12]

A[11]

A[10]

B[3]

B[2]

C[10]

B[1]

B[0]

NMI
A[6]
D[1]
A[7]
C[4]
A[8]
C[5]
A[5]
C[7]

C[3]
N.C.
N.C.

VDD_HV_IO1

VSS_HV_IO1

VDD_HV_OSC

VSS_HV_OSC

VSS_LV_COR0
VDD_LV_COR0

D[9]

XTAL

EXTAL

RESET

D[8]

D[5]

D[6]

9998979695949392919089888786858483828180797877

100
1
2
3
4
5
6
7
8
9
10

11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

26272829303132333435363738394041424344454647484950

E[1]

B[7]

D[7]

B[8]

C[1]

C[2]

E[2]

N.C.

LQFP100

B[9]

N.C.

B[10]

B[11]

B[12]

E[6]/C[0]

E[3]/B[13]

E[5]/B[15]

E[4]/B[14]

E[7]/D[15]

VSS_HV_AD0

VDD_HV_AD0

N.C.

N.C.

N.C.

BCTRL

76

VDD_HV_REG

75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

A[4]
VPP TEST
D[14]
C[14]
C[13]
D[12]
N.C.
N.C.
D[13]
VSS_LV_COR1
VDD_LV_COR1
A[3]
VDD_HV_IO2
VSS_HV_IO2
TDO
TCK
TMS
TDI
A[2]
C[12]
C[11]
D[11]
D[10]
A[1]
A[0]

Doc ID 16100 Rev 5 31/103

Package pinouts and signal descriptions SPC560P34L1, SPC560P34L3, SPC560P40L1,

Figure 5. 100-pin LQFP pinout – airbag configuration (top view)

A[15]

A[14]

C[6]

D[2]

B[6]

A[13]

A[9]

VSS_LV_COR2

VDD_LV_COR2

C[8]

D[4]

D[3]

VSS_HV_IO3

VDD_HV_IO3

D[0]

C[15]

C[9]

A[12]

A[11]

A[10]

B[3]

B[2]

C[10]

B[1]

B[0]

NMI
A[6]
D[1]
A[7]
C[4]
A[8]
C[5]
A[5]
C[7]

C[3]
N.C.
N.C.

VDD_HV_IO1

VSS_HV_IO1

VDD_HV_OSC

VSS_HV_OSC

VSS_LV_COR0

VDD_LV_COR0

D[9]

XTAL

EXTAL

RESET

D[8]

D[5]

D[6]

9998979695949392919089888786858483828180797877

100

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

26272829303132333435363738394041424344454647484950

E[1]

B[7]

D[7]

B[8]

C[1]

C[2]

E[2]

N.C.

LQFP100

B[9]

N.C.

B[10]

B[11]

B[12]

E[6]/C[0]

E[3]/B[13]

E[5]/B[15]

E[4]/B[14]

E[7]/D[15]

VSS_HV_AD0

VDD_HV_AD0

76

75

A[4]

74

VPP TEST

73

D[14]

72

C[14]

71

C[13]

70

D[12]

69

N.C.

68

N.C.

67

D[13]

66

VSS_LV_COR1

65

VDD_LV_COR1

64

A[3]

63

VDD_HV_IO2

62

VSS_HV_IO2

61

TDO

60

TCK

59

TMS

58

TDI

57

A[2]

56

C[12]

55

C[11]

54

D[11]

53

D[10]

52

A[1]

51

A[0]

N.C.

N.C.

N.C.

BCTRL

VDD_HV_REG

2.2 Pin description

The following sections provide signal descriptions and related information about the
functionality and configuration of the SPC560P34/SPC560P40 devices.

2.2.1 Power supply and reference voltage pins

Ta bl e 5

devices.

32/103 Doc ID 16100 Rev 5

lists the power supply and reference voltage for the SPC560P34/SPC560P40

SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3 Package pinouts and signal descrip-

Table 5. Supply pins

Supply Pin

Symbol Description 64-pin 100-pin

VREG control and power supply pins. Pins available on 64-pin and 100-pin packages

BCTRL Voltage regulator external NPN ballast base control pin 31 47

V

DD_HV_REG

(3.3 V or 5.0 V)

Voltage regulator supply voltage 32 50

ADC_0 reference and supply voltage. Pins available on 64-pin and 100-pin packages

V

DD_HV_ADC0

V

SS_HV_ADC0

(1)

ADC_0 supply and high reference voltage 28 39

ADC_0 ground and low reference voltage 29 40

Power supply pins (3.3 V or 5.0 V). Pins available on 64-pin and 100-pin packages

V

DD_HV_IO1

V

SS_HV_IO1

V

DD_HV_IO2

V

SS_HV_IO2

V

DD_HV_IO3

V

SS_HV_IO3

V

DD_HV_OSC

V

SS_HV_OSC

Input/output supply voltage 6 13

Input/output ground 7 14

Input/output supply voltage and data Flash memory supply voltage 40 63

Input/output ground and Flash memory HV ground 39 62

Input/output supply voltage and code Flash memory supply voltage 55 87

Input/output ground and code Flash memory HV ground 56 88

Crystal oscillator amplifier supply voltage 9 16

Crystal oscillator amplifier ground 10 17

Power supply pins (1.2 V). Pins available on 64-pin and 100-pin packages

V

DD_LV_COR0

V

SS_LV_COR0

1.2 V supply pins for core logic and PLL. Decoupling capacitor must be
connected between these pins and the nearest V

SS_LV_COR

pin.

1.2 V supply pins for core logic and PLL. Decoupling capacitor must be
connected between these pins and the nearest V

DD_LV_COR

pin.

16 25

15 24

1.2 V supply pins for core logic and data Flash. Decoupling capacitor

V

DD_LV_COR1

must be connected between these pins and the nearest V

SS_LV_COR

42 65

pin.

1.2 V supply pins for core logic and data Flash. Decoupling capacitor

V

SS_LV_COR1

must be connected between these pins and the nearest V

DD_LV_COR

43 66

pin.

1.2 V supply pins for core logic and code Flash. Decoupling capacitor

V

DD_LV_COR2

must be connected between these pins and the nearest V

SS_LV_COR

58 92

pin.

1.2 V supply pins for core logic and code Flash. Decoupling capacitor

V

SS_LV_COR2

must be connected betwee.n these pins and the nearest V

DD_LV_COR

59 93

pin.

1. Analog supply/ground and high/low reference lines are internally physically separate, but are shorted via a double-bonding
connection on V

DD_HV_ADCx/VSS_HV_ADCx

pins.

Doc ID 16100 Rev 5 33/103

Package pinouts and signal descriptions SPC560P34L1, SPC560P34L3, SPC560P40L1,

2.2.2 System pins

Ta bl e 6

devices. The pins listed in

and

Ta bl e 7

contain information on pin functions for the SPC560P34/SPC560P40

Ta bl e 6

are single-function pins. The pins shown in

Ta bl e 7

multi-function pins, programmable via their respective pad configuration register (PCR)
values.

Table 6. System pins

Symbol Description Direction

NMI Non-maskable Interrupt Input only Slow — 1 1

XTAL

EXTAL

TDI JTAG test data input Input only Slow — 35 58

TMS JTAG state machine control Input only Slow — 36 59

TCK JTAG clock Input only Slow — 37 60

Dedicated pins

Analog output of the oscillator amplifier
circuit—needs to be grounded if oscillator is
used in bypass mode

Analog input of the oscillator amplifier circuit,
when the oscillator is not in bypass mode

Analog input for the clock generator when the
oscillator is in bypass mode

Pad speed

SRC = 0 SRC = 1 64-pin 100-pin

———1118

———1219

(1)

are

Pin

TDO JTAG test data output Output only Slow Fast 38 61

Reset pin

RESET

VPP_TEST

1. SRC values refer to the value assigned to the Slew Rate Control bits of the pad configuration register.

Bidirectional reset with Schmitt trigger
characteristics and noise filter

Te s t p i n

Pin for testing purpose only. To be tied to
ground in normal operating mode.

Bidirectional Medium — 13 20

———4774

2.2.3 Pin multiplexing

Ta bl e 7

Each row of
functions. The default function assigned to each pin after reset is the ALT0 function.

SPC560P34/SPC560P40 devices provide three main I/O pad types, depending on the
associated functions:

●

●

●

defines the pin list and muxing for the SPC560P34/SPC560P40 devices.

Ta bl e 7

Slow pads

shows all the possible ways of configuring each pin, via alternate

are the most common, providing a compromise between transition time and

low electromagnetic emission.

Medium pads

provide fast enough transition for serial communication channels with

controlled current to reduce electromagnetic emission.

Fast pads

provide maximum speed. They are used for improved NEXUS debugging

capability.

34/103 Doc ID 16100 Rev 5

SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3 Package pinouts and signal descrip-

Medium and Fast pads can use slow configuration to reduce electromagnetic emission, at
the cost of reducing AC performance. For more information, see

specifications

Table 7. Pin muxing

Port

pin

A[0] PCR[0]

A[1] PCR[1]

A[2] PCR[2]

PCR

register

Alternate

function

(2)

ALT0
ALT1
ALT2
ALT3

—

ALT0
ALT1
ALT2
ALT3

—

ALT0
ALT1
ALT2
ALT3

—
—
—

.

(1),

Functions Peripheral

GPIO[0]

ETC[0]

SCK

F[0]

EIRQ[0]

GPIO[1]

ETC[1]

SOUT

F[1]

EIRQ[1]

GPIO[2]

ETC[2]

—
A[3]
SIN

ABS[0]

EIRQ[2]

Port A (16-bit)

SIUL

eTimer_0

DSPI_2

FCU_0

SIUL

SIUL

eTimer_0

DSPI_2

FCU_0

SIUL

SIUL

eTimer_0

—

FlexPWM_0

DSPI_2

MC_RGM

SIUL

(3)

I/O

direction

(4)

I/O
I/O
I/O

O

I

I/O
I/O

O
O

I

I/O
I/O

—

O

I
I
I

SRC = 0 SRC = 1 64-pin 100-pin

Slow Medium — 51

Slow Medium — 52

Slow Medium — 57

Section 3.16.1: Pad AC

Pad speed

(5)

Pin

A[3] PCR[3]

A[4] PCR[4]

A[5] PCR[5]

ALT0
ALT1
ALT2
ALT3

—
—

ALT0
ALT1
ALT2
ALT3

—
—

ALT0
ALT1
ALT2
ALT3

—

GPIO[3]

ETC[3]

CS0

B[3]

ABS[1]

EIRQ[3]

GPIO[4]

—

CS1

ETC[4]

FAB

EIRQ[4]

GPIO[5]

CS0

—

CS7

EIRQ[5]

SIUL

eTimer_0

DSPI_2

FlexPWM_0

MC_RGM

SIUL

SIUL

—

DSPI_2

eTimer_0

MC_RGM

SIUL

SIUL

DSPI_1

—

DSPI_0

SIUL

I/O
I/O
I/O

O

I/O

—

O

I/O

I/O
I/O

—

O

Slow Medium 41 64

I
I

Slow Medium 48 75

I
I

Slow Medium 5 8

I

Doc ID 16100 Rev 5 35/103

Package pinouts and signal descriptions SPC560P34L1, SPC560P34L3, SPC560P40L1,

Table 7. Pin muxing (continued)

Port

pin

PCR

register

Alternate

function

(2)

(1),

Functions Peripheral

(3)

I/O

direction

(4)

Pad speed

SRC = 0 SRC = 1 64-pin 100-pin

(5)

Pin

A[6] PCR[6]

A[7] PCR[7]

A[8] PCR[8]

A[9] PCR[9]

A[10] PCR[10]

ALT0
ALT1
ALT2
ALT3

—

ALT0
ALT1
ALT2
ALT3

—

ALT0
ALT1
ALT2
ALT3

—
—

ALT0
ALT1
ALT2
ALT3

—

ALT0
ALT1
ALT2
ALT3

—

GPIO[6]

SCK

—

—

EIRQ[6]

GPIO[7]

SOUT

—

—

EIRQ[7]

GPIO[8]

—

—

—
SIN

EIRQ[8]

GPIO[9]

CS1

—
B[3]

FAULT[ 0]

GPIO[10]

CS0

B[0]
X[2]

EIRQ[9]

SIUL

DSPI_1

—
—

SIUL

SIUL

DSPI_1

—
—

SIUL

SIUL

—
—
—

DSPI_1

SIUL

SIUL

DSPI_2

—
FlexPWM_0
FlexPWM_0

SIUL

DSPI_2
FlexPWM_0
FlexPWM_0

SIUL

I/O
I/O

—
—

I/O

O
—
—

I/O

—
—
—

I/O

O
—

O

I/O
I/O

O

O

Slow Medium 2 2

I

Slow Medium 3 4

I

Slow Medium 4 6

I
I

Slow Medium 60 94

I

Slow Medium 52 81

I

A[11] PCR[11]

A[12] PCR[12]

ALT0
ALT1
ALT2
ALT3

—

ALT0
ALT1
ALT2
ALT3

—

GPIO[11]

SCK

A[0]
A[2]

EIRQ[10]

GPIO[12]

SOUT

A[2]
B[2]

EIRQ[11]

SIUL

DSPI_2
FlexPWM_0
FlexPWM_0

SIUL

SIUL

DSPI_2
FlexPWM_0
FlexPWM_0

SIUL

36/103 Doc ID 16100 Rev 5

I/O
I/O

O
O

I/O

O
O
O

Slow Medium 53 82

I

Slow Medium 54 83

I

SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3 Package pinouts and signal descrip-

Table 7. Pin muxing (continued)

Port

pin

PCR

register

Alternate

function

(2)

(1),

Functions Peripheral

(3)

I/O

direction

(4)

Pad speed

SRC = 0 SRC = 1 64-pin 100-pin

(5)

Pin

A[13] PCR[13]

A[14] PCR[14]

A[15] PCR[15]

B[0] PCR[16]

ALT0
ALT1
ALT2
ALT3

—
—
—

ALT0
ALT1
ALT2
ALT3

—

ALT0
ALT1
ALT2
ALT3

—
—

ALT0
ALT1
ALT2
ALT3

—

GPIO[13]

—

B[2]

—

SIN
FAULT[ 0]
EIRQ[12]

GPIO[14]

TXD

—
—

EIRQ[13]

GPIO[15]

—
—
—

RXD

EIRQ[14]

GPIO[16]

TXD

—

DEBUG[0]

EIRQ[15]

SIUL

—

FlexPWM_0

—

DSPI_2

FlexPWM_0

SIUL

SIUL

Safety Port_0

—
—

SIUL

SIUL

—
—
—

Safety Port_0

SIUL

Port B (16-bit)

SIUL

FlexCAN_0

—

SSCM

SIUL

I/O

—

O

—

I/O

O
—
—

I/O

—
—
—

I/O

O
—
—

Slow Medium 61 95
I
I
I

Slow Medium 63 99

I

Slow Medium 64 100

I
I

Slow Medium 49 76

I

B[1] PCR[17]

B[2] PCR[18]

B[3] PCR[19]

ALT0
ALT1
ALT2
ALT3

—
—

ALT0
ALT1
ALT2
ALT3

—

ALT0
ALT1
ALT2
ALT3

—

GPIO[17]

—
—

DEBUG[1]

RXD

EIRQ[16]

GPIO[18]

TXD

—

DEBUG[2]

EIRQ[17]

GPIO[19]

—
—

DEBUG[3]

RXD

SIUL

—
—

SSCM

FlexCAN_0

SIUL

SIUL

LIN_0

—

SSCM

SIUL

SIUL

—
—

SSCM

LIN_0

I/O

—
—
—

I/O

O
—
—

I/O

—
—
—

Slow Medium 50 77

I
I

Slow Medium 51 79

I

Slow Medium — 80

I

Doc ID 16100 Rev 5 37/103

Package pinouts and signal descriptions SPC560P34L1, SPC560P34L3, SPC560P40L1,

Table 7. Pin muxing (continued)

Port

pin

PCR

register

Alternate

function

(2)

(1),

Functions Peripheral

(3)

I/O

direction

(4)

Pad speed

SRC = 0 SRC = 1 64-pin 100-pin

(5)

Pin

B[6] PCR[22]

B[7] PCR[23]

B[8] PCR[24]

B[9] PCR[25]

ALT0
ALT1
ALT2
ALT3

—

ALT0
ALT1
ALT2
ALT3

—
—

ALT0
ALT1
ALT2
ALT3

—
—

ALT0
ALT1
ALT2
ALT3

—

GPIO[22]

CLKOUT

CS2

—

EIRQ[18]

GPIO[23]

—
—
—

AN[0]

RXD

GPIO[24]

—
—
—

AN[1]

ETC[5]

GPIO[25]

—
—
—

AN[11]

SIUL

Control

DSPI_2

—

SIUL

SIUL

—
—
—

ADC_0

LIN_0

SIUL

—
—
—

ADC_0

eTimer_0

SIUL

—
—
—

ADC_0

I/O

O

O

Slow Medium 62 96

—

I

Input only — — 20 29

Input only — — 22 31

Input only — — 24 35

B[10] PCR[26]

B[11] PCR[27]

B[12] PCR[28]

ALT0
ALT1
ALT2
ALT3

—

ALT0
ALT1
ALT2
ALT3

—

ALT0
ALT1
ALT2
ALT3

—

GPIO[26]

—
—
—

AN[12]

GPIO[27]

—
—
—

AN[13]

GPIO[28]

—
—
—

AN[14]

SIUL

—
—
—

ADC_0

SIUL

—
—
—

ADC_0

SIUL

—
—
—

ADC_0

Input only — — 25 36

Input only — — 26 37

Input only — — 27 38

38/103 Doc ID 16100 Rev 5

SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3 Package pinouts and signal descrip-

Table 7. Pin muxing (continued)

Port

pin

PCR

register

Alternate

function

(2)

(1),

Functions Peripheral

(3)

I/O

direction

(4)

Pad speed

SRC = 0 SRC = 1 64-pin 100-pin

(5)

Pin

B[13] PCR[29]

B[14] PCR[30]

B[15] PCR[31]

ALT0
ALT1
ALT2
ALT3

—
—
—

ALT0
ALT1
ALT2
ALT3

—
—
—
—

ALT0
ALT1
ALT2
ALT3

—
—
—

GPIO[29]

—
—
—

AN[6]

emu. AN[0]

RXD

GPIO[30]

—
—
—

AN[7]

emu. AN[1]

ETC[4]

EIRQ[19]

GPIO[31]

—
—
—

AN[8]

emu. AN[2]

EIRQ[20]

SIUL

—
—
—

ADC_0

emu. ADC_1

LIN_1

SIUL

—
—
—

ADC_0

emu. ADC_1

eTimer_0

SIUL

SIUL

—
—
—

ADC_0

emu. ADC_1

SIUL

Input only — — 30 42

(6)

Input only — — — 44

(6)

Input only — — — 43

(6)

C[0] PCR[32]

C[1] PCR[33]

C[2] PCR[34]

ALT0
ALT1
ALT2
ALT3

—
—

ALT0
ALT1
ALT2
ALT3

—

ALT0
ALT1
ALT2
ALT3

—

GPIO[32]

—
—
—

AN[9]

emu. AN[3]

GPIO[33]

—
—
—

AN[2]

GPIO[34]

—
—
—

AN[3]

Port C (16-bit)

SIUL

—
—
—

ADC_0

emu. ADC_1

SIUL

—
—
—

ADC_0

SIUL

—
—
—

ADC_0

Input only — — — 45

(6)

Input only — — 19 28

Input only — — 21 30

Doc ID 16100 Rev 5 39/103

Package pinouts and signal descriptions SPC560P34L1, SPC560P34L3, SPC560P40L1,

Table 7. Pin muxing (continued)

Port

pin

PCR

register

Alternate

function

(2)

(1),

Functions Peripheral

(3)

I/O

direction

(4)

Pad speed

SRC = 0 SRC = 1 64-pin 100-pin

(5)

Pin

C[3] PCR[35]

C[4] PCR[36]

C[5] PCR[37]

C[6] PCR[38]

C[7] PCR[39]

C[8] PCR[40]

ALT0
ALT1
ALT2
ALT3

—

ALT0
ALT1
ALT2
ALT3

—

ALT0
ALT1
ALT2
ALT3

—

ALT0
ALT1
ALT2
ALT3

—

ALT0
ALT1
ALT2
ALT3

—

ALT0
ALT1
ALT2
ALT3

GPIO[35]

CS1

—

TXD

EIRQ[21]

GPIO[36]

CS0

X[1]

DEBUG[4]

EIRQ[22]

GPIO[37]

SCK

—

DEBUG[5]

EIRQ[23]

GPIO[38]

SOUT

B[1]

DEBUG[6]

EIRQ[24]

GPIO[39]

—

A[1]

DEBUG[7]

SIN

GPIO[40]

CS1

—

CS6

SIUL

DSPI_0

—

LIN_1

SIUL

SIUL

DSPI_0

FlexPWM_0

SSCM

SIUL

SIUL

DSPI_0

—

SSCM

SIUL

SIUL

DSPI_0

FlexPWM_0

SSCM

SIUL

SIUL

—

FlexPWM_0

SSCM

DSPI_0

SIUL

DSPI_1

—

DSPI_0

I/O

O
—

O

I/O
I/O

O
—

I/O
I/O

—
—

I/O

O

O
—

I/O

—

O
—

I/O

O
—

O

Slow Medium — 10

I

Slow Medium — 5

I

Slow Medium — 7

I

Slow Medium — 98

I

Slow Medium — 9

I

Slow Medium 57 91

C[9] PCR[41]

C[10] PCR[42]

ALT0
ALT1
ALT2
ALT3

ALT0
ALT1
ALT2
ALT3

—

GPIO[41]

CS3

—

X[3]

GPIO[42]

CS2

—

A[3]

FAULT[ 1]

SIUL

DSPI_2

—

FlexPWM_0

SIUL

DSPI_2

—
FlexPWM_0
FlexPWM_0

40/103 Doc ID 16100 Rev 5

I/O

O

—

O

I/O

O

—

O

Slow Medium — 84

Slow Medium — 78

I

SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3 Package pinouts and signal descrip-

Table 7. Pin muxing (continued)

Port

pin

PCR

register

Alternate

function

(2)

(1),

Functions Peripheral

(3)

I/O

direction

(4)

Pad speed

SRC = 0 SRC = 1 64-pin 100-pin

(5)

Pin

C[11] PCR[43]

C[12] PCR[44]

C[13] PCR[45]

C[14] PCR[46]

C[15] PCR[47]

ALT0
ALT1
ALT2
ALT3

ALT0
ALT1
ALT2
ALT3

ALT0
ALT1
ALT2
ALT3

—
—

ALT0
ALT1
ALT2
ALT3

ALT0
ALT1
ALT2
ALT3

—
—

GPIO[43]

ETC[4]

CS2

—

GPIO[44]

ETC[5]

CS3

—

GPIO[45]

—
—
—

EXT_IN

EXT_SYNC

GPIO[46]

—

EXT_TGR

—

GPIO[47]

—
—

A[1]

EXT_IN

EXT_SYNC

SIUL

eTimer_0

DSPI_2

—

SIUL

eTimer_0

DSPI_2

—

SIUL

—

—

—

CTU_0

FlexPWM_0

SIUL

—

CTU_0

—

SIUL

—

—
FlexPWM_0

CTU_0

FlexPWM_0

I/O
I/O

O

—

I/O
I/O

O

—

I/O

—
—
—

I/O

—

O

—

I/O

—
—

O

Slow Medium 33 55

Slow Medium 34 56

Slow Medium — 71

I
I

Slow Medium — 72

Slow Medium — 85

I
I

D[0] PCR[48]

D[1] PCR[49]

D[2] PCR[50]

D[3] PCR[51]

ALT0
ALT1
ALT2
ALT3

ALT0
ALT1
ALT2
ALT3

ALT0
ALT1
ALT2
ALT3

ALT0
ALT1
ALT2
ALT3

GPIO[48]

—
—

B[1]

GPIO[49]

—
—

EXT_TRG

GPIO[50]

—
—

X[3]

GPIO[51]

—
—

A[3]

Port D (16-bit)

SIUL

—

—
FlexPWM_0

SIUL

—

—

CTU_0

SIUL

—

—
FlexPWM_0

SIUL

—

—
FlexPWM_0

I/O

—
—

O

I/O

—
—

O

I/O

—
—

O

I/O

—
—

O

Slow Medium — 86

Slow Medium — 3

Slow Medium — 97

Slow Medium — 89

Doc ID 16100 Rev 5 41/103

Package pinouts and signal descriptions SPC560P34L1, SPC560P34L3, SPC560P40L1,

Table 7. Pin muxing (continued)

Port

pin

PCR

register

Alternate

function

(2)

(1),

Functions Peripheral

(3)

I/O

direction

(4)

Pad speed

SRC = 0 SRC = 1 64-pin 100-pin

(5)

Pin

D[4] PCR[52]

D[5] PCR[53]

D[6] PCR[54]

D[7] PCR[55]

D[8] PCR[56]

ALT0
ALT1
ALT2
ALT3

ALT0
ALT1
ALT2
ALT3

ALT0
ALT1
ALT2
ALT3

—

ALT0
ALT1
ALT2
ALT3

ALT0
ALT1
ALT2
ALT3

GPIO[52]

—
—

B[3]

GPIO[53]

CS3

F[0]

—

GPIO[54]

CS2

—
—

FAULT[ 1]

GPIO[55]

CS3

F[1]

CS4

GPIO[56]

CS2

—

CS5

SIUL

—

—
FlexPWM_0

SIUL

DSPI_0

FCU_0

—

SIUL

DSPI_0

—

—
FlexPWM_0

SIUL

DSPI_1

FCU_0

DSPI_0

SIUL

DSPI_1

—

DSPI_0

I/O

—
—

O

I/O

O
O

—

I/O

O
—
—

I/O

O

O

O

I/O

O
—

O

Slow Medium — 90

Slow Medium — 22

Slow Medium — 23

I

Slow Medium 17 26

Slow Medium 14 21

D[9] PCR[57]

D[10] PCR[58]

D[11] PCR[59]

D[12] PCR[60]

ALT0
ALT1
ALT2
ALT3

ALT0
ALT1
ALT2
ALT3

ALT0
ALT1
ALT2
ALT3

ALT0
ALT1
ALT2
ALT3

—

GPIO[57]

X[0]

TXD

—

GPIO[58]

A[0]

—
—

GPIO[59]

B[0]

—
—

GPIO[60]

X[1]

—
—

RXD

SIUL

FlexPWM_0

LIN_1

—

SIUL

FlexPWM_0

—
—

SIUL

FlexPWM_0

—
—

SIUL

FlexPWM_0

—
—

LIN_1

I/O

O

O
—

I/O

O
—
—

I/O

O
—
—

I/O

O
—
—

Slow Medium 8 15

Slow Medium — 53

Slow Medium — 54

Slow Medium 45 70

I

42/103 Doc ID 16100 Rev 5

SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3 Package pinouts and signal descrip-

Table 7. Pin muxing (continued)

Port

pin

PCR

register

Alternate

function

(2)

(1),

Functions Peripheral

(3)

I/O

direction

(4)

Pad speed

SRC = 0 SRC = 1 64-pin 100-pin

(5)

Pin

D[13] PCR[61]

D[14] PCR[62]

D[15] PCR[63]

E[1] PCR[65]

E[2] PCR[66]

ALT0
ALT1
ALT2
ALT3

ALT0
ALT1
ALT2
ALT3

ALT0
ALT1
ALT2
ALT3

—
—

ALT0
ALT1
ALT2
ALT3

—

ALT0
ALT1
ALT2
ALT3

—

GPIO[61]

A[1]

—
—

GPIO[62]

B[1]

—
—

GPIO[63]

—
—
—

AN[10]

emu. AN[4]

GPIO[65]

—
—
—

AN[4]

GPIO[66]

—
—
—

AN[5]

SIUL

FlexPWM_0

—
—

SIUL

FlexPWM_0

—
—

SIUL

—
—
—

ADC_0

emu. ADC_1

Port E (16-bit)

SIUL

—
—
—

ADC_0

SIUL

—
—
—

ADC_0

I/O

O
—

Slow Medium 44 67

—

I/O

O
—

Slow Medium 46 73

—

Input only — — — 41

(6)

Input only — — 18 27

Input only — — 23 32

E[3] PCR[67]

E[4] PCR[68]

E[5] PCR[69]

ALT0
ALT1
ALT2
ALT3

—

ALT0
ALT1
ALT2
ALT3

—

ALT0
ALT1
ALT2
ALT3

—

GPIO[67]

—
—
—

AN[6]

GPIO[68]

—
—
—

AN[7]

GPIO[69]

—
—
—

AN[8]

SIUL

—
—

Input only — — 30 42

—

ADC_0

SIUL

—
—

Input only — — — 44

—

ADC_0

SIUL

—
—

Input only — — — 43

—

ADC_0

Doc ID 16100 Rev 5 43/103

Package pinouts and signal descriptions SPC560P34L1, SPC560P34L3, SPC560P40L1,

Table 7. Pin muxing (continued)

Port

pin

PCR

register

Alternate

function

(2)

(1),

Functions Peripheral

(3)

I/O

direction

(4)

Pad speed

SRC = 0 SRC = 1 64-pin 100-pin

(5)

Pin

ALT0
ALT1

E[6] PCR[70]

ALT2
ALT3

—

ALT0
ALT1

E[7] PCR[71]

ALT2
ALT3

—

1. ALT0 is the primary (default) function for each port after reset.

2. Alternate functions are chosen by setting the values of the PCR.PA bitfields inside the SIU module. PCR.PA = 00 → ALT0;
PCR.PA = 01 → ALT1; PCR.PA = 10 → ALT2; PCR.PA = 11 → ALT3. This is intended to select the output functions; to
use one of the input functions, the PCR.IBE bit must be written to ‘1’, regardless of the values selected in the PCR.PA
bitfields. For this reason, the value corresponding to an input only function is reported as “—”.

3. Module included on the MCU.

4. Multiple inputs are routed to all respective modules internally. The input of some modules must be configured by setting the
values of the PSMIO.PADSELx bitfields inside the SIUL module.

5. Programmable via the SRC (Slew Rate Control) bits in the respective Pad Configuration Register.

6. ADC0.AN emulates ADC1.AN. This feature is used to provide software compatibility between SPC560P34/SPC560P40
and SPC560P50. Refer to ADC chapter of reference manual for more details.

GPIO[70]

—
—
—

AN[9]

GPIO[71]

—
—
—

AN[10]

SIUL

—
—
—

ADC_0

SIUL

—
—
—

ADC_0

Input only — — — 45

Input only — — — 41

44/103 Doc ID 16100 Rev 5

SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3 Electrical characteristics

3 Electrical characteristics

3.1 Introduction

This section contains device electrical characteristics as well as temperature and power
considerations.

This microcontroller contains input protection against damage due to high static voltages.
However, it is advisable to take precautions to avoid application of any voltage higher than
the specified maximum rated voltages.

To enhance reliability, unused inputs can be driven to an appropriate logic voltage level (V
or V

). This can be done by the internal pull-up or pull-down resistors, which are provided

SS

by the device for most general purpose pins.

The following tables provide the device characteristics and its demands on the system.

In the tables where the device logic provides signals with their respective timing
characteristics, the symbol “CC” for Controller Characteristics is included in the Symbol
column.

In the tables where the external system must provide signals with their respective timing
characteristics to the device, the symbol “SR” for System Requirement is included in the
Symbol column.

Caution: All of the following parameter values can vary depending on the application and must be

confirmed during silicon characterization or silicon reliability trial.

3.2 Parameter classification

The electrical parameters are guaranteed by various methods. To give the customer a better
understanding, the classifications listed in
accordingly in the tables where appropriate.

Table 8. Parameter classifications

Classification tag Tag description

Ta bl e 8

are used and the parameters are tagged

DD

P Those parameters are guaranteed during production testing on each individual device.

C

T

D Those parameters are derived mainly from simulations.

Those parameters are achieved by the design characterization by measuring a statistically
relevant sample size across process variations.

Those parameters are achieved by design characterization on a small sample size from typical
devices under typical conditions unless otherwise noted. All values shown in the typical
column are within this category.

Note: The classification is shown in the column labeled “C” in the parameter tables where

appropriate.

Doc ID 16100 Rev 5 45/103

Electrical characteristics SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3

3.3 Absolute maximum ratings

Table 9. Absolute maximum ratings

(1)

Symbol Parameter Conditions

V

SS

SR Device ground — 0 0 V

3.3 V/5.0 V input/output supply
voltage (supply).

V

DD_HV_IOx

(3)

SR

Code flash memory supply with
V

DD_HV_IO3

memory with V

and data flash

DD_HV_IO2

3.3 V/5.0 V input/output supply
voltage (ground).

V

SS_HV_IOx

V

DD_HV_OSC

V

SS_HV_OSC

V

DD_HV_ADC0

V

SS_HV_ADC0

V

DD_HV_REG

TV

DD

SR

Code flash memory ground with
V

SS_HV_IO3

memory with V

3.3 V/5.0 V crystal oscillator

SR

amplifier supply voltage (supply)

3.3 V/5.0 V crystal oscillator

SR

amplifier supply voltage (ground)

3.3 V/5.0 V ADC_0 supply and

SR

high- reference voltage

3.3 V/5.0 V ADC_0 ground and

SR

low- reference voltage

3.3 V/5.0 V voltage-regulator

SR

supply voltage

Slope characteristics on all V

SR

during power up

and data flash

SS_HV_IO2

(4)

DD

Relative to V

V

DD_HV_REG

V

DD_HV_REG

Relative to V

Value

Unit

Min Max

(2)

—–0.36.0V

—–0.10.1V

—–0.36.0

V

DD_HV_IOx

–0.3 V

DD_HV_IOx

+0.3

—–0.10.1V

< 2.7 V –0.3 V

DD_HV_REG

+0.3

V

> 2.7 V –0.3 6.0

—–0.10.1V

—–0.36.0

V

DD_HV_IOx

–0.3 V

DD_HV_IOx

+0.3

— 0.5 250 V/ms

V

DD_LV_CORx

V

SS_LV_CORx

V

IN

I

INJPAD

I

INJSUM

T

STG

T

J

1. Functional operating conditions are given in the DC electrical characteristics. Absolute maximum ratings are stress ratings
only, and functional operation at the maxima is not guaranteed. Stress beyond the listed maxima may affect device
reliability or cause permanent damage to the device.

CC1.2 V supply pins for core logic

(supply)

1.2 V supply pins for core logic

SR

(ground)

Voltage on any pin with respect

SR

to ground (V

Input current on any pin during

SR

overload condition

Absolute sum of all input currents

SR

during overload condition

SS_HV_IOx

)

Relative to V

—–0.11.5V

—–0.10.1V

—–0.36.0

DD_HV_IOx

–0.3 V

DD_HV_IOx

+0.3

(5)

— –10 10 mA

— –50 50 mA

SR Storage temperature — –55 150 °C
SR Junction temperature under bias — −40 150 °C

46/103 Doc ID 16100 Rev 5

V

SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3 Electrical characteristics

2. Absolute maximum voltages are currently maximum burn-in voltages.

3. The difference between each couple of voltage supplies must be less than 300 mV, ⏐V

4. Guaranteed by device validation.

5. Only when V

DD_HV_IOx

< 5.2 V.

DD_HV_IOy–VDD_HV_IOx

⏐ < 300 mV.

Figure 6

shows the constraints of the different power supplies.

Figure 6. Power supplies constraints (–0.3 V ≤ V

VDD_HV_xxx

6.0 V

–0.3 V

–0.3 V

The SPC560P34/SPC560P40 supply architecture allows the ADC supply to be managed
independently from the standard V

DD_HV

power supply.

DD_HV_IOx

supply.

≤ 6.0 V)

Figure 7

VDD_HV_IOx

6.0 V

shows the constraints of the ADC

Doc ID 16100 Rev 5 47/103

Electrical characteristics SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3

Figure 7. Independent ADC supply (–0.3 V ≤ V

VDD_HV_ADCx

6.0 V

–0.3 V

–0.3 V

2.7 V

DD_HV_REG

≤ 6.0 V)

VDD_HV_REG

6.0 V

3.4 Recommended operating conditions

Table 10. Recommended operating conditions (5.0 V)

V

DD_HV_IOx

V

SS_HV_IOx

V

DD_HV_OSC

V

SS_HV_OSC

V

DD_HV_REG

Symbol Parameter Conditions

V

SS

SR Device ground — 0 0 V

(2)

5.0 V input/output supply

SR

voltage

Input/output ground

SR

voltage

—4.5 5.5V

—0 0V

—4.5 5.5

5.0 V crystal oscillator

SR

amplifier supply voltage

Relative to
V

DD_HV_IOx

5.0 V crystal oscillator

SR

amplifier reference

—0 0V

voltage

—4.5 5.5

5.0 V voltage regulator

SR

supply voltage

Relative to
V

DD_HV_IOx

V

DD_HV_IOx

V

DD_HV_IOx

Val ue

Min Max

–0.1 V

–0.1 V

DD_HV_IOx

DD_HV_IOx

(1)

Unit

V

+0.1

V

+0.1

48/103 Doc ID 16100 Rev 5

SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3 Electrical characteristics

Table 10. Recommended operating conditions (5.0 V) (continued)

Val ue

Symbol Parameter Conditions

Min Max

(1)

Unit

V

DD_HV_ADC0

V

SS_HV_ADC0

V

DD_LV_REGCOR

,(4)

V

SS_LV_REGCOR

V

DD_LV_CORx

V

SS_LV_CORx

T

1. Full functionality cannot be guaranteed when voltage drops below 4.5 V. In particular, ADC electrical characteristics and
I/Os DC electrical specification may not be guaranteed.

2. The difference between each couple of voltage supplies must be less than 100 mV,

V

DD_HV_IOx

3. To be connected to emitter of external NPN. Low voltage supplies are not under user control—they are produced by an on­chip voltage regulator—but for the device to function properly the low voltage grounds (V
voltage grounds (V
emitter.

4. The low voltage supplies (V
– V

DD_LV_COR1

voltage supply to the data flash memory module. Similarly, V
– V

DD_LV_REGCOR

(3)

(3)

3,4

3

A

⏐ < 100 mV.

and V

5.0 V ADC_0 supply and

SR

high reference voltage

ADC_0 ground and low

SR

reference voltage

Relative to
V

DD_HV_REG

V

DD_HV_REG

–0.1 —

—0 0V

CC Internal supply voltage — — — V

SR Internal reference voltage — 0 0 V

CC Internal supply voltage — — — V

SR Internal reference voltage — 0 0 V

f

=60MHz −40 125 °C

Ambient temperature

SR

under bias

SS_HV_xxx

and V

) and the low voltage supply pins (V

DD_LV_xxx

DD_LV_COR2

DD_LV_RECORx

) are not all independent.

are shorted internally via double bonding connections with lines that provide the low

are physically shorted internally, as are V

CPU

f

=64MHz −40 105 °C

CPU

DD_LV_xxx

SS_LV_COR1

⏐V

DD_HV_IOy

) must be connected to the external ballast

and V

SS_LV_COR2

SS_LV_xxx

SS_LV_REGCOR

–

) must be shorted to high

are internally shorted.

and V

SS_LV_CORx

.

—4.5 5.5

V

Table 11. Recommended operating conditions (3.3 V)

Symbol Parameter Conditions

V

SS

V

DD_HV_IOx

V

SS_HV_IOx

SR Device ground — 0 0 V

(2)

3.3 V input/output supply

SR

voltage

Input/output ground

SR

voltage

—3.0 3.6V

—0 0V

—3.0 3.6

3.3 V crystal oscillator

V

DD_HV_OSC

SR

amplifier supply voltage

Relative to
V

DD_HV_IOx

3.3 V crystal oscillator

V

SS_HV_OSC

SR

amplifier reference

—0 0V

voltage

Doc ID 16100 Rev 5 49/103

Min Max

V

DD_HV_IOx

–0.1 V

Val ue

DD_HV_IOx

(1)

Unit

V

+0.1

Electrical characteristics SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3

Table 11. Recommended operating conditions (3.3 V) (continued)

Val ue

Symbol Parameter Conditions

Min Max

(1)

Unit

V

DD_HV_REG

3.3 V voltage regulator

SR

supply voltage

Relative to
V

DD_HV_IOx

V

DD_HV_IOx

–0.1 V

DD_HV_IOx

+0.1

—3.0 5.5

3.3 V ADC_0 supply and

—3.0 3.6

(3)

SR

high reference voltage

ADC_0 ground and low

SR

reference voltage

Relative to
V

DD_HV_REG

V

DD_HV_REG

− 0.1 5.5

—0 0V

CC Internal supply voltage — — — V

(3)

SR Internal reference voltage — 0 0 V

(3),(4)

CC Internal supply voltage — — — V

(3)

SR Internal reference voltage — 0 0 V

f

=60MHz −40 125 °C

SR

⏐ < 100 mV.

SS_HV_xxx

and V

DD_LV_COR2

and V

Ambient temperature
under bias

) and the low voltage supply pins (V

DD_LV_xxx

DD_LV_RECORx

) are not all independent.

are shorted internally via double bonding connections with lines that provide the low

are physically shorted internally, as are V

CPU

f

=64MHz −40 105 °C

CPU

DD_LV_xxx

SS_LV_COR1

⏐V

DD_HV_IOy

) must be connected to the external ballast

and V

SS_LV_COR2

SS_LV_xxx

SS_LV_REGCOR

–

) must be shorted to high

are internally shorted.

and V

SS_LV_CORx

.

V

DD_HV_ADC0

V

SS_HV_ADC0

V

DD_LV_REGCOR

,(4)

V

SS_LV_REGCOR

V

DD_LV_CORx

V

SS_LV_CORx

T

A

1. Full functionality cannot be guaranteed when voltage drops below 3.0 V. In particular, ADC electrical characteristics and
I/Os DC electrical specification may not be guaranteed.

2. The difference between each couple of voltage supplies must be less than 100 mV,

V

DD_HV_IOx

3. To be connected to emitter of external NPN. Low voltage supplies are not under user control—they are produced by an on­chip voltage regulator—but for the device to function properly the low voltage grounds (V
voltage grounds (V
emitter.

4. The low voltage supplies (V
– V

DD_LV_COR1

voltage supply to the data flash memory module. Similarly, V
– V

DD_LV_REGCOR

V

V

Figure 8

shows the constraints of the different power supplies.

50/103 Doc ID 16100 Rev 5

SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3 Electrical characteristics

Figure 8. Power supplies constraints

VDD_HV_xxx

5.5 V

3.3 V

3.0 V

The SPC560P34/SPC560P40 supply architecture allows the ADC supply to be managed
independently from the standard V
power supply.

(a)

(3.0 V ≤ V

3.0 V

DD_HV

DD_HV_IOx

3.3 V

supply.

≤ 5.5 V)

Figure 9

VDD_HV_IOx

5.5 V

shows the constraints of the ADC

Figure 9. Independent ADC supply (3.0 V ≤

VDD_HV_ADCx

5.5 V

3.0 V

V

DD_HV_REG

3.0 V

≤ 5.5 V)

VDD_HV_REG

5.5 V

a. IO AC and DC characteristics are guaranteed only in the range of 3.0–3.6 V when PAD3V5V is low, and in the range of

4.5–5.5 V when PAD3V5V is high.

Doc ID 16100 Rev 5 51/103

Electrical characteristics SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3

3.5 Thermal characteristics

3.5.1 Package thermal characteristics

Table 12. LQFP thermal characteristics

Typical value

Symbol Parameter Conditions

Unit

100-pin 64-pin

R

R

R

θJCtop

Ψ
Ψ

1. Junction-to-ambient thermal resistance determined per JEDEC JESD51-7. Thermal test board meets JEDEC specification

2. Junction-to-board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC specification for

3. Junction-to-case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate temperature is

4. Thermal characterization parameter indicating the temperature difference between the board and the junction temperature

5. Thermal characterization parameter indicating the temperature difference between the package top and the junction

Thermal resistance junction-to-ambient, natural

θJA

convection

Thermal resistance junction-to-board

θJB

Thermal resistance junction-to-case (top)

Junction-to-board, natural convection

JB

Junction-to-case, natural convection

JC

for this package.

the specified package. When Greek letters are not available, the symbols are typed as RthJB or Theta-JB.

used for the case temperature. Reported value includes the thermal resistance of the interface layer.

per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JB.

temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written
as Psi-JC.

(1)

(2)

(3)

(4)

(5)

Single layer board—1s 63 57 °C/W

Four layer board—2s2p 51 41 °C/W

Four layer board—2s2p 33 22 °C/W

Single layer board—1s 15 13 °C/W

Operating conditions 33 22 °C/W

Operating conditions 1 1 °C/W

3.5.2 General notes for specifications at maximum junction temperature

An estimation of the chip junction temperature, TJ, can be obtained from

Equation 1 T

= TA + (R

J

θJA

* PD)

where:

T

= ambient temperature for the package (°C)

A

R

= junction-to-ambient thermal resistance (°C/W)

θJA

P

= power dissipation in the package (W)

D

The junction-to-ambient thermal resistance is an industry standard value that provides a
quick and easy estimation of thermal performance. Unfortunately, there are two values in
common usage: the value determined on a single layer board and the value obtained on a
board with two planes. For packages such as the PBGA, these values can be different by a
factor of two. Which value is closer to the application depends on the power dissipated by
other components on the board. The value obtained on a single layer board is appropriate
for the tightly packed printed circuit board. The value obtained on the board with the internal
planes is usually appropriate if the board has low power dissipation and the components are
well separated.

When a heat sink is used, the thermal resistance is expressed in

Equation 2

junction-to-case thermal resistance and a case-to-ambient thermal resistance:

Equation 1

:

as the sum of a

52/103 Doc ID 16100 Rev 5

SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3 Electrical characteristics

Equation 2 R

θJA

= R

θJC

+ R

θCA

where:

R

= junction-to-ambient thermal resistance (°C/W)

θJA

R

= junction-to-case thermal resistance (°C/W)

θJC

R

= case-to-ambient thermal resistance (°C/W)

θCA

R

is device related and cannot be influenced by the user. The user controls the thermal

θJC

environment to change the case-to-ambient thermal resistance, R

. For instance, the user

θCA

can change the size of the heat sink, the air flow around the device, the interface material,
the mounting arrangement on printed circuit board, or change the thermal dissipation on the
printed circuit board surrounding the device.

To determine the junction temperature of the device in the application when heat sinks are
not used, the Thermal Characterization Parameter (Ψ

) can be used to determine the

JT

junction temperature with a measurement of the temperature at the top center of the
package case using

Equation 3 T

J

Equation 3

= TT + (ΨJT x PD)

:

where:

T

= thermocouple temperature on top of the package (°C)

T

Ψ

= thermal characterization parameter (°C/W)

JT

P

= power dissipation in the package (W)

D

The thermal characterization parameter is measured per JESD51-2 specification using a 40
gauge type T thermocouple epoxied to the top center of the package case. The
thermocouple should be positioned so that the thermocouple junction rests on the package.
A small amount of epoxy is placed over the thermocouple junction and over about 1 mm of
wire extending from the junction. The thermocouple wire is placed flat against the package
case to avoid measurement errors caused by cooling effects of the thermocouple wire.

References:

Semiconductor Equipment and Materials International
3081 Zanker Road
San Jose, CA 95134U.S.A.
[phone]

MIL-SPEC and EIA/JESD (JEDEC) specifications are available from Global Engineering
Documents at [phone] or [phone].

JEDEC specifications are available on the WEB at http://www.jedec.org.

1. C.E. Triplett and B. Joiner,

Automotive Engine Controller Module

An Experimental Characterization of a 272 PBGA Within an

, Proceedings of SemiTherm, San Diego, 1998,

pp. 47–54.

2. G. Kromann, S. Shidore, and S. Addison,

Applications

3. B. Joiner and V. Adams,

, Electronic Packaging and Production, pp. 53–58, March 1998.

Measurement and Simulation of Junction to Board Thermal

Resistance and Its Application in Thermal Modeling

Thermal Modeling of a PBGA for Air-Cooled

, Proceedings of SemiTherm, San

Diego, 1999, pp. 212–220.

Doc ID 16100 Rev 5 53/103

Electrical characteristics SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3

3.6 Electromagnetic interference (EMI) characteristics

Table 13. EMI testing specifications

Symbol Parameter Conditions Clocks Frequency

150 kHz–150 MHz 11

150–1000 MHz 13

IEC level M —

150 kHz–150 MHz 8

150–1000 MHz 12

IEC level N —

150 kHz–150 MHz 9

150–1000 MHz 12

IEC level M —

150 kHz–150 MHz 7

150–1000 MHz 12

IEC level N —

V

EME

Radiated
emissions

= 5.0 V; TA=25°C

V

DD

Other device configuration,
test conditions and EM
testing per standard
IEC61967-2

= 3.3 V; TA=25°C

V

DD

Other device configuration,
test conditions and EM
testing per standard
IEC61967-2

=8MHz

f

OSC

f

=64MHz

CPU

No PLL frequency
modulation

f

=8MHz

OSC

f

=64MHz

CPU

±4% PLL frequency
modulation

f

=8MHz

OSC

f

=64MHz

CPU

No PLL frequency
modulation

f

=8MHz

OSC

f

=64MHz

CPU

±4% PLL frequency
modulation

Level

(Typ)

Unit

dBµV

dBµV

dBµV

dBµV

3.7 Electrostatic discharge (ESD) characteristics

Table 14. ESD ratings

Symbol Parameter Conditions Value Unit

V

ESD(HBM)

V

ESD(CDM)

1. All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits.

2. A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device specification
requirements. Complete DC parametric and functional testing shall be performed per applicable device specification at
room temperature followed by hot temperature, unless specified otherwise in the device specification.

SR Electrostatic discharge (Human Body Model) — 2000 V

SR Electrostatic discharge (Charged Device Model) —

(1),(2)

750 (corners)

500 (other)

3.8 Power management electrical characteristics

3.8.1 Voltage regulator electrical characteristics

The internal voltage regulator requires an external NPN ballast, approved ballast list
availbale in
placed on the board as near as possible to the associated pins. Care should also be taken
to limit the serial inductance of the V
L

(refer to

Reg

Ta bl e 1 5

Figure 16

, to be connected as shown in

DD_HV_REG

, BCTRL and V

).

Figure 10

. Capacitances should be

DD_LV_CORx

pins to less than

V

54/103 Doc ID 16100 Rev 5

SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3 Electrical characteristics

Note: The voltage regulator output cannot be used to drive external circuits. Output pins are to be

used only for decoupling capacitance.

V

DD_LV_COR

possible to provide V

must be generated using internal regulator and external NPN transistor. It is not

DD_LV_COR

through external regulator.

For the SPC560P34/SPC560P40 microcontroller, capacitor(s), with total values not below
C

, should be placed between V

DEC1

DD_LV_CORx/VSS_LV_CORx

transistor emitter. 4 capacitors, with total values not below C
microcontroller pins between each V
V

DD_LV_REGCOR/VSS_LV_REGCOR

C

, should be placed between the V

DEC3

DD_LV_CORx/VSS_LV_CORx

pair. Additionally, capacitor(s) with total values not below

DD_HV_REG/VSS_HV_REG

close to external ballast

, should be placed close to

DEC2

supply pairs and the

pins close to ballast
collector. Capacitors values have to take into account capacitor accuracy, aging and
variation versus temperature.

All reported information are valid for voltage and temperature ranges described in
recommended operating condition,

Ta bl e 1 0

and

Ta b le 1 1

.

Figure 10. Voltage regulator configuration

VDD_HV_REG

SPC560P34/SPC560P40

BCTRL

VDD_LV_COR

1. Refer to

Table 15. Approved NPN ballast components

BCP68

Table 15

Part Manufacturer Approved derivatives

.

ON Semi BCP68

NXP BCP68-25

Infineon BCP68-25

C

DEC2

BJT

(1)

C

DEC1

C

DEC3

(1)

BCX68 Infineon BCX68-10; BCX68-16; BCX-25

BC868 NXP BC868

BC817

Infineon BC817-16; BC817-25; BC817SU

NXP BC817-16; BC817-25

Doc ID 16100 Rev 5 55/103

Electrical characteristics SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3

Table 15. Approved NPN ballast components (continued)

Part Manufacturer Approved derivatives

ST BCP56-16

(1)

BCP56

Infineon BCP56-10; BCP56-16

ON Semi BCP56-10

NXP BCP56-10; BCP56-16

1. For automotive applications please check with the appropriate transistor vendor for automotive grade

certification

Table 16. Voltage regulator electrical characteristics

Symbol C Parameter Conditions

Output voltage under

V

DD_LV_REGCOR

CC P

maximum load run
supply current

Post-trimming 1.15 — 1.32 V

configuration

BJT from
capacitors (i.e. X7R or X8R

C

DEC1

SR —

External
decoupling/stability

capacitors) with nominal value
of 10 µF

ceramic capacitor

BJT BC817, one capacitance of
22 µF

R

C

C

REG

DEC2

DEC3

SR —

SR —

SR —

Resulting ESR of either
one or all three C

DEC1

External
decoupling/stability
ceramic capacitor

External
decoupling/stability
ceramic capacitor on
VDD_HV_REG

Absolute maximum value
between 100 kHz and 10 MHz

Four capacitances (i.e. X7R or
X8R capacitors) with nominal
value of 440 nF

Three capacitors (i.e. X7R or
X8R capacitors) with nominal
value of 10 µF; C
equal or greater than C

Resulting ESL of

L

Reg

SR —

V

DD_HV_REG

and V

DD_LV_CORx

, BCTRL

pins

Val ue

Unit

Min Typ Max

Ta b l e 1 5

. Three

19.5 30 — µF

14.3 22 — µF

——45mΩ

1200 1760 — nF

DEC3

has to be

DEC1

19.5 30 — µF

———5nH

3.8.2 Voltage monitor electrical characteristics

The device implements a power on reset module to ensure correct power-up initialization, as
well as three low voltage detectors to monitor the V
is supplied:

● POR monitors V

during the power-up phase to ensure device is maintained in a safe

DD

reset state

● LVDHV3 monitors V

● LVDHV5 monitors V

● LVDLVCOR monitors low voltage digital power domain

56/103 Doc ID 16100 Rev 5

to ensure device reset below minimum functional supply

DD

when application uses device in the 5.0 V ± 10% range

DD

DD

and the V

voltage while device

DD_LV

SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3 Electrical characteristics

Table 17. Low voltage monitor electrical characteristics

Symbol C Parameter Conditions

V

PORH

V

PORUP

V

REGLVDMOK_H

V

REGLVDMOK_L

V

FLLVDMOK_H

V

FLLVDMOK_L

V

IOLVDMOK_H

V

IOLVDMOK_L

V

IOLVDM5OK_H

V

IOLVDM5OK_L

V

MLVDDOK_H

V

MLVDDOK_L

1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 °C to T

T Power-on reset threshold — 1.5 2.7 V

P Supply for functional POR module TA = 25 °C 1.0 — V

P Regulator low voltage detector high threshold — — 2.95 V

P Regulator low voltage detector low threshold — 2.6 — V

P Flash low voltage detector high threshold — — 2.95 V

P Flash low voltage detector low threshold — 2.6 — V

P I/O low voltage detector high threshold — — 2.95 V

P I/O low voltage detector low threshold — 2.6 — V

P I/O 5 V low voltage detector high threshold — — 4.4 V

P I/O 5 V low voltage detector low threshold — 3.8 — V

P Digital supply low voltage detector high — — 1.145 V

P Digital supply low voltage detector low — 1.08 — V

, unless otherwise specified.

A MAX

(1)

Value

Unit

Min Max

3.9 Power up/down sequencing

To prevent an overstress event or a malfunction within and outside the device, the
SPC560P34/SPC560P40 implements the following sequence to ensure each module is
started only when all conditions for switching it ON are available:

● A POWER_ON module working on voltage regulator supply controls the correct start-

up of the regulator. This is a key module ensuring safe configuration for all voltage
regulator functionality when supply is below 1.5 V. Associated POWER_ON (or POR)
signal is active low.

● Several low voltage detectors, working on voltage regulator supply monitor the voltage

of the critical modules (voltage regulator, I/Os, flash memory and low voltage domain).
LVDs are gated low when POWER_ON is active.

● A POWER_OK signal is generated when all critical supplies monitored by the LVD are

available. This signal is active high and released to all modules including I/Os, flash
memory and 16 MHz RC oscillator needed during power-up phase and reset phase.
When POWER_OK is low the associated modules are set into a safe state.

Doc ID 16100 Rev 5 57/103

Electrical characteristics SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3

Figure 11. Power-up typical sequence

V

LVDHV3H

VDD_HV_REG

POWER_ON

LVDM (HV)

VDD_LV_REGCOR

LVDD (LV)

POWER_OK

RC16MHz Oscillator

Internal Reset Generation Module
FSM

V

POR_UP

V

PORH

V

MLVDOK_H

~1us

P0 P1

3.3V

0V

3.3V

0V

3.3V

0V

1.2V
0V

3.3V

0V

3.3V

0V

1.2V
0V

1.2V
0V

Figure 12. Power-down typical sequence

V

LVDHV3L

V

VDD_HV_REG

LVDM (HV)

POWER_ON

VDD_LV_REGCOR

LVDD (LV)

POWER_OK

RC16MHz Oscillator

Internal Reset Generation Module
FSM

PORH

P0IDLE

3.3V

0V

3.3V

0V

3.3V

0V

1.2V
0V

3.3V

0V

3.3V

0V

1.2V
0V

1.2V
0V

58/103 Doc ID 16100 Rev 5

SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3 Electrical characteristics

Figure 13. Brown-out typical sequence

V

V

VDD_HV_REG

LVDM (HV)

POWER_ON

VDD_LV_REGCOR

LVDD (LV)

POWER_OK

RC16MHz Oscillator

Internal Reset Generation Module
FSM

LVDHV3L

LVDHV3H

P0IDLE

~1us

P1

3.3V

0V

3.3V

0V

3.3V

0V

1.2V
0V

3.3V

0V

3.3V

0V

1.2V
0V

1.2V
0V

3.10 DC electrical characteristics

3.10.1 NVUSRO register

Portions of the device configuration, such as high voltage supply and watchdog
enable/disable after reset are controlled via bit values in the non-volatile user options
(NVUSRO) register.

For a detailed description of the NVUSRO register, please refer to the device reference
manual.

NVUSRO[PAD3V5V] field description

The DC electrical characteristics are dependent on the PAD3V5V bit value.
how NVUSRO[PAD3V5V] controls the device configuration.

Table 18. PAD3V5V field description

(1)

Val ue

0 High voltage supply is 5.0 V

1 High voltage supply is 3.3 V

1. Default manufacturing value before flash initialization is ‘1’ (3.3 V).

Description

Ta bl e 1 8

shows

Doc ID 16100 Rev 5 59/103

Electrical characteristics SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3

3.10.2 DC electrical characteristics (5 V)

Ta bl e 1 9

gives the DC electrical characteristics at 5 V (4.5 V < V

NVUSRO[PAD3V5V] = 0).

Table 19. DC electrical characteristics (5.0 V, NVUSRO[PAD3V5V] = 0)

Symbol C Parameter Conditions

V

IL

V

IH

V

HYS

V

OL_S

V

OH_S

V

OL_M

V

OH_M

Min Max

D

— −0.4

(1)

Low level input voltage

P——0.35V

P

High level input voltage

—0.65V

DD_HV_IOx

D——V

T Schmitt trigger hysteresis — 0.1 V

Slow, low level output

P

voltage

Slow, high level output

P

voltage

Medium, low level output

P

voltage

Medium, high level output

P

voltage

=3mA — 0.1V

I

OL

IOH= −3mA 0.8V

=3mA — 0.1V

I

OL

= −3mA 0.8V

I

OH

DD_HV_IOx

DD_HV_IOx

DD_HV_IOx

DD_HV_IOx

Val ue

DD_HV_IOx

< 5.5 V,

Unit

—V

(1)

V

V

V

V

DD_HV_IOx

—V

+0.4

—V

DD_HV_IOx

—V

DD_HV_IOx

—V

V

OL_F

V

OH_F

I

PU

I

PD

I

IL

I

IL

C

IN

1. “SR” parameter values must not exceed the absolute maximum ratings shown in

Fast, low level output

P

voltage

Fast, high level output

P

voltage

P Equivalent pull-up current

P Equivalent pull-down current

Input leakage current

P

(all bidirectional ports)

Input leakage current

P

(all ADC input-only ports)

IOL=14mA — 0.1V

= −14 mA 0.8 V

I

OH

V

IN=VIL

V

IN=VIH

V

IN=VIL

V

IN=VIH

= −40 to 125 °C −11µA

T

A

= −40 to 125 °C −0.5 0.5 µA

T

A

D Input capacitance — — 10 pF

V

DD_HV_IOx

DD_HV_IOx

—V

−130 —

µA

— −10

10 —

µA

—130

Table 9

.

60/103 Doc ID 16100 Rev 5

SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3 Electrical characteristics

Table 20. Supply current (5.0 V, NVUSRO[PAD3V5V] = 0)

(1)

Value

Symbol C Parameter Conditions

Typ Max

T

RUN—Maximum mode

(2)

40 MHz 44 55

P 64 MHz 52 65

I

DD_LV_CORx

T RUN—Typical mode

P

HALT mode

STOP mode

(4)

(5)

(3)

Flash during read V

I

DD_FLASH

Supply current

T

Flash during erase
operation on 1 flash module

I

DD_ADC

I

DD_OSC

1. All values to be confirmed after characterization/data collection.

2. Maximum mode: FlexPWM, ADC, CTU, DSPI, LINFlex, FlexCAN, 15 output pins, PLL_0 enabled, 125 °C ambient. I/O
supply current excluded.

3. Typical mode configurations: DSPI, LINFlex, FlexCAN, 15 output pins, PLL_0, 105 °C ambient. I/O supply current
excluded.

4. Halt mode configurations: Code fetched from SRAM, code flash memory and data flash memory in low power mode,
OSC/PLL_0 are OFF, core clock frozen, all peripherals disabled.

5. STOP “P” mode Device Under Test (DUT) configuration: Code fetched from SRAM, code flash memory and data flash
memory off, OSC/PLL_0 are OFF, core clock frozen, all peripherals disabled.

TADC

T Oscillator V

V

DD_LV_CORx

forced at 1.3 V

DD_HV_FL

V

DD_HV_FL

V

DD_HV_ADC0

f

=16MHz

ADC

DD_HV_OSC

externally

at 5.0 V — 8 10

at 5.0 V — 15 19

at 5.0 V

at 5.0 V 8 MHz 2.6 3.2

40 MHz 38 46

64 MHz 45 54

—1.510

—110

ADC_0 3 4

Unit

mA

3.10.3 DC electrical characteristics (3.3 V)

Ta bl e 2 1

NVUSRO[PAD3V5V] = 1); see

Table 21. DC electrical characteristics (3.3 V, NVUSRO[PAD3V5V] = 1)

Symbol C Parameter Conditions

V

IL

V

IH

V

HYS

V

OL_S

V

OH_S

V

OL_M

D

Low level input voltage

P——0.35V

P

High level input voltage

D——V

T Schmitt trigger hysteresis — 0.1 V

P Slow, low level output voltage IOL= 1.5 mA — 0.5 V

P Slow, high level output voltage IOH= −1.5 mA V

P Medium, low level output voltage IOL=2mA — 0.5 V

gives the DC electrical characteristics at 3.3 V (3.0 V < V

Figure 14

Doc ID 16100 Rev 5 61/103

.

Min Max

— −0.4

—0.65V

DD_HV_IOx

(2)

DD_HV_IOx

DD_HV_IOx

− 0.8 — V

DD_HV_IOx

(1)

Val ue

DD_HV_IOx

< 3.6 V,

Unit

—V

(2)

V

V

DD_HV_IOx

—V

+0.4

—V

Electrical characteristics SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3

Table 21. DC electrical characteristics (3.3 V, NVUSRO[PAD3V5V] = 1)

Symbol C Parameter Conditions

Min Max

V

OH_M

V

OL_F

V

OH_F

I

PU

I

PD

I

IL

I

IL

C

IN

1. These specifications are design targets and subject to change per device characterization.

2. “SR” parameter values must not exceed the absolute maximum ratings shown in

Medium, high level output

P

voltage

= −2mA V

I

OH

DD_HV_IOx

− 0.8 — V

P Fast, low level output voltage IOL=11mA — 0.5 V

P Fast, high level output voltage IOH= −11 mA V

V

P Equivalent pull-up current

P Equivalent pull-down current

Input leakage current (all

P

bidirectional ports)

Input leakage current (all ADC

P

input-only ports)

IN=VIL

VIN=V

V

IN=VIL

V

IN=VIH

= −40 to

T

A

125 °C

= −40 to

T

A

125 °C

IH

DD_HV_IOx

− 0.8 — V

−130 —
— −10

10 —

—130

—1µA

—0.5µA

D Input capacitance — — 10 pF

Table 9

.

(1)

(continued)

Val ue

Unit

µA

µA

Table 22. Supply current (3.3 V, NVUSRO[PAD3V5V] = 1)

(1)

Val ue

Symbol C Parameter Conditions

Typ M ax

RUN—Maximum mode

(2)

40 MHz 44 55

64 MHz 52 65

T

I

DD_LV_CORx

P

I

DD_ADC

I

DD_OSC

1. All values to be confirmed after characterization/data collection.

2. Maximum mode: FlexPWM, ADC, CTU, DSPI, LINFlex, FlexCAN, 15 output pins, PLL_0 enabled, 125 °C ambient. I/O
supply current excluded.

3. Typical mode configurations: DSPI, LINFlex, FlexCAN, 15 output pins, PLL_0, 105 °C ambient. I/O supply current
excluded.

4. Halt mode configurations: Code fetched from SRAM, code flash memory and data flash memory in low power mode,
OSC/PLL_0 are OFF, core clock frozen, all peripherals disabled.

5. STOP “P” mode Device Under Test (DUT) configuration: Code fetched from SRAM, code flash memory and data flash
memory off, OSC/PLL_0 are OFF, core clock frozen, all peripherals disabled.

TADC

T Oscillator V

RUN—Typical mode

HALT mode

STOP mode

Supply current

(4)

(5)

(3)

V

DD_LV_CORx

forced at 1.3 V

V

DD_HV_ADC0

f

=16MHz

ADC

DD_HV_OSC

externally

at 3.3 V

at 3.3 V 8 MHz 2.6 3.2

40 MHz 38 46

64 MHz 45 54

—1.510

—110

ADC_0 3 4

Unit

mA

62/103 Doc ID 16100 Rev 5

SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3 Electrical characteristics

3.10.4 Input DC electrical characteristics definition

Figure 14

shows the DC electrical characteristics behavior as function of time.

Figure 14. Input DC electrical characteristics definition

V

IN

V

DD

V

IH

V

IL

(GPDI register of SIUL)

PDIx = ‘1’

PDIx = ‘0’

3.10.5 I/O pad current specification

V

HYS

The I/O pads are distributed across the I/O supply segment. Each I/O supply segment is
associated to a V

Table 23. I/O supply segment

DD/VSS

Package

12345

LQFP100 pin15–pin26 pin27–pin46 pin51–pin61 pin64–pin86 pin89–pin10

LQFP64 pin8–pin17 pin18–pin30 pin33–pin38 pin41–pin54 pin57–pin5

Table 24. I/O consumption

Symbol C Parameter Conditions

Dynamic I/O current

C

I

SWTSLW

(2)

C

D

for SLOW
configuration

supply pair as described in

Supply segment

V

DD

C

L

= 25 pF

PAD3V5V = 0

V

DD

PAD3V5V = 1

Ta b le 2 3

(1)

.

= 5.0 V ± 10%,

= 3.3 V ± 10%,

Val ue

Min Typ Max

——20

——16

Unit

mA

Doc ID 16100 Rev 5 63/103

Electrical characteristics SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3

Table 24. I/O consumption (continued)

Symbol C Parameter Conditions

Dynamic I/O current

C

I

SWTMED

(2)

C

D

for MEDIUM
configuration

CL = 25 pF

(1)

V

= 5.0 V ± 10%,

DD

PAD3V5V = 0

= 3.3 V ± 10%,

V

DD

PAD3V5V = 1

V

= 5.0 V ± 10%,

DD

PAD3V5V = 0

= 3.3 V ± 10%,

V

DD

I

SWTFST

(2)

Dynamic I/O current

C

D

for FAST

C

configuration

C

L

= 25 pF

PAD3V5V = 1

CL = 25 pF, 2 MHz

V

= 5.0 V ± 10%,

DD

PAD3V5V = 0

V

= 3.3 V ± 10%,

DD

PAD3V5V = 1

I

RMSSLW

Root medium

C

square I/O current

D

C

for SLOW
configuration

C

= 25 pF, 4 MHz — — 3.2

L

C

= 100 pF, 2 MHz — — 6.6

L

CL = 25 pF, 2 MHz

C

= 25 pF, 4 MHz — — 2.3

L

C

= 100 pF, 2 MHz — — 4.7

L

CL = 25 pF, 13 MHz

V

= 5.0 V ± 10%,

DD

PAD3V5V = 0

V

= 3.3 V ± 10%,

DD

PAD3V5V = 1

I

RMSMED

Root medium

C

square I/O current

D

C

for MEDIUM
configuration

C

= 25 pF, 40 MHz — — 13.4

L

C

= 100 pF, 13 MHz — — 18.3

L

CL = 25 pF, 13 MHz

C

= 25 pF, 40 MHz — — 8.5

L

C

= 100 pF, 13 MHz — — 11

L

CL = 25 pF, 40 MHz

V

= 5.0 V ± 10%,

C

= 25 pF, 64 MHz — — 33

Root medium

C

I

RMSFST

square I/O current

D

C

for FAST
configuration

Sum of all the static

I

AVGSEG

1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = –40 to 125 °C, unless otherwise specified.

2. Stated maximum values represent peak consumption that lasts only a few ns during I/O transition.

S

D

I/O current within a

R

supply segment

L

C

= 100 pF, 40 MHz — — 56

L

= 25 pF, 40 MHz

C

L

C

= 25 pF, 64 MHz — — 20

L

C

= 100 pF, 40 MHz — — 35

L

= 5.0 V ± 10%, PAD3V5V = 0 — — 70

V

DD

= 3.3 V ± 10%, PAD3V5V = 1 — — 65

V

DD

DD

PAD3V5V = 0

V

= 3.3 V ± 10%,

DD

PAD3V5V = 1

Val ue

Unit

Min Typ Max

——29

mA

——17

——110

mA

——50

——2.3

mA

——1.6

——6.6

mA

——5

——22

mA

——14

mA

3.11 Main oscillator electrical characteristics

The SPC560P34/SPC560P40 provides an oscillator/resonator driver.

64/103 Doc ID 16100 Rev 5

SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3 Electrical characteristics

Table 25. Main oscillator output electrical characteristics (5.0 V,

NVUSRO[PAD3V5V] = 0)

Value

Symbol C Parameter Conditions

Min Max

Unit

f

V

t

OSCSU

SR — Oscillator frequency 4 40 MHz

OSC

g

— P Transconductance 6.5 25 mA/V

m

— T Oscillation amplitude on XTAL pin 1 — V

OSC

— T Start-up time

T

(1),(2)

8—ms

4MHz 5 30

T8MHz526

CLCC

T12MHz523

XTAL load capacitance

(3)

T16MHz519

T20MHz516

T40MHz58

1. The start-up time is dependent upon crystal characteristics, board leakage, etc. High ESR and excessive
capacitive loads can cause long start-up time.

2. Value captured when amplitude reaches 90% of XTAL.

3. This value is determined by the crystal manufacturer and board design. For 4 MHz to 40 MHz crystals
specified for this oscillator, load capacitors should not exceed these limits.

Table 26. Main oscillator output electrical characteristics (3.3 V,

NVUSRO[PAD3V5V] = 1)

Val ue

Symbol C Parameter Conditions

Min Max

Unit

pf

f

V

t

OSCSU

SR — Oscillator frequency 4 40 MHz

OSC

— P Transconductance 4 20 mA/V

g

m

— T Oscillation amplitude on XTAL pin 1 — V

OSC

— T Start-up time

T

(1),(2)

8—ms

4MHz 5 30

T8MHz526

C

T12MHz523

CC

L

XTAL load capacitance

T16MHz519

(3)

T20MHz516

T40MHz58

1. The start-up time is dependent upon crystal characteristics, board leakage, etc. High ESR and excessive
capacitive loads can cause long start-up time.

2. Value captured when amplitude reaches 90% of XTAL.

3. This value is determined by the crystal manufacturer and board design. For 4 MHz to 40 MHz crystals
specified for this oscillator, load capacitors should not exceed these limits.

Doc ID 16100 Rev 5 65/103

pf

Electrical characteristics SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3

Table 27. Input clock characteristics

Value

Symbol Parameter

Min Typ Max

Unit

f

OSC

f

t

rCLK

t

SR Oscillator frequency 4 — 40 MHz

SR Frequency in bypass — — 64 MHz

CLK

SR Rise/fall time in bypass — — 1 ns

SR Duty cycle 47.5 50 52.5 %

DC

3.12 FMPLL electrical characteristics

Table 28. FMPLL electrical characteristics

Symbol C Parameter Conditions

f

ref_crystal

f

ref_ext

f

PLLIN

f

FMPLLOUT

f

FREE

t

CYC

f

LORL

f

LORH

f

SCM

C

JITTER

t

lpll

t

dc

f

LCK

f

UL

f

CS

f

DS

f

MOD

1. V

DD_LV_CORx

2. Considering operation with PLL not bypassed.

3. “Loss of Reference Frequency” window is the reference frequency range outside of which the PLL is in self clocked mode.

(1)

Val ue

Unit

Min Max

D PLL reference frequency range

Phase detector input frequency range

D

(after pre-divider)

(2)

Crystal reference 4 40 MHz

—416MHz

D Clock frequency range in normal mode — 16 64 MHz

P Free-running frequency

D System clock period — — 1 / f

D

Loss of reference frequency window

Measured using clock
division—typically /16

Lower limit 1.6 3.7

(3)

20 150 MHz

SYS

ns

MHz

D Upper limit 24 56

D Self-clocked mode frequency

Short-term jitter

CLKOUT period

T

jitter

(6),(7),(8),(9)

Long-term jitter
(average over 2 ms
interval)

DPLL lock time

(11), (12)

(4),(5)

(10)

—20150MHz

f

maximum −44%f

SYS

f

=16MHz

PLLIN

(resonator), f

PLLCLK

at

—10 ns

64 MHz, 4000 cycles

——200µs

CLKOUT

D Duty cycle of reference — 40 60 %
D Frequency LOCK range — −66%f
D Frequency un-LOCK range — −18 18 % f

D

Modulation depth

Center spread ±0.25

±4.0

(13)

%f

SYS

SYS

SYS

DDown spread−0.5 −8.0

D Modulation frequency

= 1.2 V ±10%; VSS = 0 V; TA = –40 to 125 °C, unless otherwise specified.

(14)

——70kHz

66/103 Doc ID 16100 Rev 5

SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3 Electrical characteristics

4. Self clocked mode frequency is the frequency that the PLL operates at when the reference frequency falls outside the f
window.

5. f

6. This value is determined by the crystal manufacturer and board design.

7. Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f

8. Proper PC board layout procedures must be followed to achieve specifications.

9. Values are obtained with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of C

10. Short term jitter is measured on the clock rising edge at cycle n and cycle n+4.

11. This value is determined by the crystal manufacturer and board design. For 4 MHz to 20 MHz crystals specified for this

12. This specification applies to the period required for the PLL to relock after changing the MFD frequency control bits in the

13. This value is true when operating at frequencies above 60 MHz, otherwise f

14. Modulation depth will be attenuated from depth setting when operating at modulation frequencies above 50 kHz.

self clock range is 20–150 MHz. f

VCO

mode.

Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise
injected into the PLL circuitry via V
C

percentage for a given interval.

JITTER

or f

and either f

PLL, load capacitors should not exceed these limits.

synthesizer control register (SYNCR).

CS

(depending on whether center spread or down spread modulation is enabled).

DS

represents f

SCM

DD_LV_COR0

and V

after PLL output divider (ERFD) of 2 through 16 in enhanced

SYS

SS_LV_COR0

and variation in crystal oscillator frequency increase the

is 2% (above 64 MHz).

CS

SYS

JITTER

LOR

.

3.13 16 MHz RC oscillator electrical characteristics

Table 29. 16 MHz RC oscillator electrical characteristics

Symbol C Parameter Conditions

Value

Min Typ Max

Unit

f

RC

P RC oscillator frequency TA = 25 °C — 16 — MHz

Fast internal RC oscillator variation over

Δ

RCMVAR

P

temperature and supply with respect to f

= 25 °C in high-frequency configuration

T

A

RC

at

— −5— 5%

3.14 Analog-to-digital converter (ADC) electrical characteristics

The device provides a 10-bit Successive Approximation Register (SAR) analog-to-digital
converter.

Doc ID 16100 Rev 5 67/103

Electrical characteristics SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3

Figure 15. ADC characteristics and error definitions

code out

1023

1022

1021

1020

1019

1018

Offset Error (EO)

1 LSB ideal = V

(2)

7

(1)

6

5

(5)

4

3

2

(4)

(3)

(1) Example of an actual transfer curve

(2) The ideal transfer cur ve

(3) Differential non-linearity error (DNL)

(4) Integral non-linearity error (INL)

(5) Center of a step of the actual transfer curve

Gain Error (E

/ 1024

DD_ADC

)

G

1

0

1 2 3 4 5 6 7 1017 1018 1019 1020 1021 1022 1023

Offset Error (E

O

)

1 LSB (ideal)

V

(LSB

in(A)

3.14.1 Input impedance and ADC accuracy

To preserve the accuracy of the A/D converter, it is necessary that analog input pins have
low AC impedance. Placing a capacitor with good high-frequency characteristics at the input
pin of the device can be effective: the capacitor should be as large as possible, ideally
infinite. This capacitor contributes to attenuating the noise present on the input pin; it
sources charge during the sampling phase, when the analog signal source is a high­impedance source.

A real filter can typically be obtained by using a series resistance with a capacitor on the
input pin (simple RC filter). The RC filtering may be limited according to the source
impedance value of the transducer or circuit supplying the analog signal to be measured.

68/103 Doc ID 16100 Rev 5

ideal

)

SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3 Electrical characteristics

The filter at the input pins must be designed taking into account the dynamic characteristics
of the input signal (bandwidth) and the equivalent input impedance of the ADC itself.

In fact a current sink contributor is represented by the charge sharing effects with the
sampling capacitance: C

being substantially a switched capacitance, with a frequency

S

equal to the ADC conversion rate, it can be seen as a resistive path to ground. For instance,
assuming a conversion rate of 1 MHz, with C
obtained (R

= 1 / (fc × CS), where fc represents the conversion rate at the considered

EQ

equal to 3 pF, a resistance of 330 kΩ is

S

channel). To minimize the error induced by the voltage partitioning between this resistance
(sampled voltage on C
must be designed to respect the

) and the sum of RS + RF + RL + RSW + RAD, the external circuit

S

Equation 4

:

Equation 4

RSRFRLR

V

A

Equation 4

generates a constraint for external network design, in particular on resistive path.

Internal switch resistances (R

+++ +

-------------------------------------------------------------------------- -

•

and RAD) can be neglected with respect to external

SW

R

EQ

SWRAD

<

1

-- -LSB
2

resistances.

Figure 16. Input equivalent circuit

EXTERNAL CIRCUIT INTERNAL CIRCUIT SCHEME

V

DD

Source Filter Current Limiter

R

S

V

A

RS: Source impedance
R

: Filter resistance

F

: Filter capacitance

C

F

: Current limiter resistance

R

L

R

: Channel selection switch impedance

SW1

: Sampling switch impedance

R

AD

: Pin capacitance (two contributions, C

C

P

: Sampling capacitance

C

S

R

F

C

F

and CP2)

P1

Channel

Selection

R

L

C

P1

R

SW1

Sampling

R

AD

C

P2

C

S

A second aspect involving the capacitance network shall be considered. Assuming the three
capacitances C
equivalent circuit reported in

, CP1 and C

F

are initially charged at the source voltage VA (refer to the

P2

Figure 16

): A charge sharing phenomenon is installed when

the sampling phase is started (A/D switch closed).

Doc ID 16100 Rev 5 69/103

Electrical characteristics SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3

Figure 17. Transient behavior during sampling phase

V

CS

V

A

V

A2

V

A1

Voltage Transient on C

1

2

S

t

s

ΔV < 0.5 LSB

τ1 < (RSW + RAD) CS << t

τ2 = RL (CS + CP1 + CP2)

t

s

In particular two different transient periods can be distinguished:

● A first and quick charge transfer from the internal capacitance C

sampling capacitance C

occurs (CS is supposed initially completely discharged):

S

and CP2 to the

P1

considering a worst case (since the time constant in reality would be faster) in which
C

is reported in parallel to C

P2

C

are in series, and the time constant is

S

(call CP = CP1 + CP2), the two capacitances CP and

P1

Equation 5

•

CPC

τ

R

1

+()=

SWRAD

--------------------- -

•

S

CPCS+

Equation 5

can again be simplified considering only CS as an additional worst
condition. In reality, the transient is faster, but the A/D converter circuitry has been
designed to be robust also in the very worst case: the sampling time t
much longer than the internal time constant:

Equation 6

The charge of C
the voltage V

A1

τ

1RSWRAD

and CP2 is redistributed also on CS, determining a new value of

P1

on the capacitance according to

+()< C

Equation 7

V

A1CSCP1CP2

● A second charge transfer involves also C

capacitance) through the resistance R
and C

were in parallel to CP1 (since the time constant in reality would be faster), the

S

++()• V

: again considering the worst case in which CP2

L

time constant is:

is always

s

t

«•

s

S

Equation 7

C

A

(that is typically bigger than the on-chip

F

+()•=

P1CP2

:

70/103 Doc ID 16100 Rev 5

SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3 Electrical characteristics

Equation 8

τ

< C

2RL

++()•

SCP1CP2

In this case, the time constant depends on the external circuit: in particular
imposing that the transient is completed well before the end of sampling time t
constraints on R

sizing is obtained:

L

s

, a

Equation 9

10 τ

• 10 R

2

Of course, R
combination with R

shall be sized also according to the current limitation constraints, in

L

(source impedance) and RF (filter resistance). Being CF

S

definitively bigger than C

LCSCP1CP2

, CP2 and CS, then the final voltage V

P1

the charge transfer transient) will be much higher than V
respected (charge balance assuming now C

++()••= t

already charged at VA1):

S

<

s

.

Equation 10

A1

(at the end of

A2

must be

Equation 10

V

A2CSCP1CP2CF

+++()• V

The two transients above are not influenced by the voltage source that, due to the presence
of the R
C

with respect to the ideal source VA; the time constant RFCF of the filter is very high with

S

respect to the sampling time (t

filter, is not able to provide the extra charge to compensate the voltage drop on

FCF

). The filter is typically designed to act as anti-aliasing.

s

Figure 18. Spectral representation of input signal

Analog Source Bandwidth (VA)

Noise

f

0

Anti-Aliasing Filter (fF = RC Filter pole)

f

F

f

f

t

fF = f0

2 f0 ≤ f

Sampled Signal Spectrum (fC = conversion Rate)

• V

+CP1CP2+C

ACF

≤ 2 RFC

c

(Conversion Rate vs. Filter Pole)

F

(Anti-aliasing Filtering Condition)

(Nyquist)

C

f

0

A1

+()•=

S

f

C

f

Calling f
the anti-aliasing filter, f
least 2f
the conversion period (T
t

, which is just a portion of it, even when fixed channel continuous conversion mode is

s

the bandwidth of the source signal (and as a consequence the cut-off frequency of

0

; it means that the constant time of the filter is greater than or at least equal to twice

0

), according to the Nyquist theorem the conversion rate fC must be at

F

). Again the conversion period tc is longer than the sampling time

C

selected (fastest conversion rate at a specific channel): in conclusion it is evident that the
time constant of the filter R

is definitively much higher than the sampling time ts, so the

FCF

Doc ID 16100 Rev 5 71/103

Electrical characteristics SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3

charge level on CS cannot be modified by the analog signal source during the time in which
the sampling switch is closed.

The considerations above lead to impose new constraints on the external circuit, to reduce
the accuracy error due to the voltage drop on C
above, it is simple to derive

Equation 11

between the ideal and real sampled voltage on CS:

; from the two charge balance equations

S

Equation 11

C

+C

V

A

----------- ­V

A2

P1CP2

------------------------------------------------------- -=
C

+CFC

P1CP2

+

F

++

S

From this formula, in the worst case (when V

is maximum, that is for instance 5 V),

A

assuming to accept a maximum error of half a count, a constraint is evident on C

Equation 12

CF2048 C

•>

3.14.2 ADC conversion characteristics

Table 30. ADC conversion characteristics

Symbol C Parameter Conditions

f

CK

f

s

t

s

t

c

ADC clock frequency (depends on

S

ADC configuration)

—

R

(The duty cycle depends on ADC

(2)

frequency)

clock

S

— Sampling frequency — — — 1.53 MHz

R

f

= 20 MHz, INPSAMP = 3 125 — — ns

— D Sampling time

(4)

— P Conversion time

(5)

ADC

f

= 9 MHz, INPSAMP = 255 — — 28.2 µs

ADC

f

= 20 MHz

ADC

value:

F

S

(1)

—3

(6)

, INPCMP = 1

Val ue

Min Typ Max

(3)

—60MHz

0.65
——µs

0

Unit

ADC power-up delay (time needed

t

ADC_PU

C

C

C

R

SW1

R

S

—

for ADC to settle exiting from

R

software power down; PWDN bit = 0)

(7)

— D ADC input sampling capacitance — — — 2.5 pF

S

(7)

— D ADC input pin capacitance 1 — — — 3 pF

P1

(7)

— D ADC input pin capacitance 2 — — — 1 pF

P2

V

(7)

— D Internal resistance of analog source

(7)

— D Internal resistance of analog source — — — 2 kΩ

AD

DD_HV_ADC0

V

DD_HV_ADC0

72/103 Doc ID 16100 Rev 5

———1.5µs

= 5 V ± 10% — — 0.6 kΩ
= 3.3 V ± 10% — — 3 kΩ

SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3 Electrical characteristics

Table 30. ADC conversion characteristics (continued)

Val ue

Symbol C Parameter Conditions

(1)

Min Typ Max

Current injection on one ADC

I

— T Input current injection

INJ

input, different from the
converted one. Remains

-5 — 5 mA

within TUE specification

INL

DNL

TUE

TUE

1. VDD = 3.3 V to 3.6 V / 4.5 V to 5.5 V, TA = −40 °C to T

2. AD_clk clock is always half of the ADC module input clock defined via the auxiliary clock divider for the ADC.

3. When configured to allow 60 MHz ADC, the minimum ADC clock speed is 9 MHz, below which the precision is lost.

4. During the sampling time the input capacitance CS can be charged/discharged by the external source. The internal

5. This parameter includes the sampling time t

6. 20 MHz ADC clock. Specific prescaler is programmed on MC_PLL_CLK to provide 20 MHz clock to the ADC.

7. See

C

P Integral non-linearity No overload −1.5 — 1.5 LSB

C

C

P Differential non-linearity No overload −1.0 — 1.0 LSB

C

C

E

O

E

G

V

SS_HV_ADC0

resistance of the analog source must allow the capacitance to reach its final voltage level within t
sampling time ts, changes of the analog input voltage have no effect on the conversion result. Values for the sample clock

depend on programming.

t

s

T Offset error — — ±1 — LSB

C

C

T Gain error — — ±1 — LSB

C

C

Total unadjusted error without

C

C
C

Figure 16

P

current injection

Total unadjusted error with current

T

injection

to V

DD_HV_ADC0

.

.

.

s

, unless otherwise specified and analog input voltage from

A MAX

—-2.5—2.5LSB

— −3— 3LSB

. After the end of the

s

Unit

3.15 Flash memory electrical characteristics

3.15.1 Program/Erase characteristics

Table 31. Program and erase specifications

Symbol C Parameter

T

wprogram

T

dwprogram

T

BKPRG

P Word Program Time for data flash memory

(4)

P Double Word Program Time for code flash memory

P Bank Program (256 KB)

P Bank Program (64 KB)

4(5)

(4)(5)

Doc ID 16100 Rev 5 73/103

Min Typ

—3070500µs

(4)

—2250500µs

— 0.73 0.83 17.5 s

—0.491.24.1s

Val ue

(1)

Initial

Max

(2)

Max

(3)

Unit

Electrical characteristics SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3

Table 31. Program and erase specifications (continued)

Val ue

Symbol C Parameter

Min Typ

(1)

Initial

Max

(2)

Max

(3)

Unit

16 KB Block Pre-program and Erase Time for code
flash memory

T

16kpperase

P

16 KB Block Pre-program and Erase Time for data
flash memory

T

32kpperase

T

128kpperase

1. Typical program and erase times assume nominal supply values and operation at 25 °C. All times are subject to change
pending device characterization.

2. Initial factory condition: < 100 program/erase cycles, 25 °C, typical supply voltage.

3. The maximum program and erase times occur after the specified number of program/erase cycles. These maximum values
are characterized but not guaranteed.

4. Actual hardware programming times. This does not include software overhead.

5. Typical Bank programming time assumes that all cells are programmed in a single pulse. In reality some cells will require
more than one pulse, adding a small overhead to total bank programming time (see “Initial Max” column).

Table 32. Flash memory module life

P 32 KB Block Pre-program and Erase Time — 400 600 5000 ms

P 128 KB Block Pre-program and Erase Time — 800 1300 7500 ms

— 300 500 5000

— 700 800 5000

Val ue

Symbol C Parameter Conditions

Unit

Min Typ

Number of program/erase cycles per

P/E C

block for 16 KB blocks over the
operating temperature range (T

— 100000 — cycles

)

J

Number of program/erase cycles per

P/E C

block for 32 KB blocks over the
operating temperature range (T

— 10000 100000 cycles

)

J

Number of program/erase cycles per

P/E C

block for 128 KB blocks over the
operating temperature range (T

— 1000 100000 cycles

)

J

Blocks with 0–1000 P/E cycles 20 — years

Retention C

Minimum data retention at 85 °C
average ambient temperature

(1)

Blocks with 10000 P/E cycles 10 — years

Blocks with 100000 P/E cycles 5 — years

1. Ambient temperature averaged over duration of application, not to exceed recommended product operating temperature
range.

ms

Table 33. Flash memory read access timing

Symbol C Parameter Conditions

f

max

f

max

1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = -40 to 125 °C, unless otherwise specified.

Maximum working frequency for code flash memory at given

C

number of wait states in worst conditions

Maximum working frequency for data flash memory at given

C

number of wait states in worst conditions

2 wait states 66

0 wait states 18

8 wait states 66 MHz

74/103 Doc ID 16100 Rev 5

(1)

Max value Unit

MHz

SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3 Electrical characteristics

3.15.2 Flash memory power supply DC characteristics

Table 34.

Table 34. Flash memory power supply DC electrical characteristics

shows the power supply DC characteristics on external supply.

Symbol C Parameter Conditions

C

I

FLPW

I

FPWD

1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified.

Sum of the current consumption on V

D

C

and V

DD_LV_CORx

C

Sum of the current consumption on V

D

C

and V

DD_LV_CORx

during low-power mode

during power-down mode

DD_HV_IOx

DD_HV_IOx

Code flash memory — — 900 µA

Code flash memory — — 150

Data flash memory — — 150

3.15.3 Start-up/Switch-off timings

Table 35. Start-up time/Switch-off time

Symbol C Parameter Conditions

T

FLARSTEXIT

T

C

Delay for Flash module to exit reset mode

C

T Data flash memory — — 125

Code flash memory — — 125

(1)

Min Typ Max

(1)

Min Typ Max

Value

Unit

µA

Value

Unit

C

T

FLALPEXIT

T

FLAPDEXIT

T

FLALPENTRY

1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified.

Delay for Flash module to exit low-power

D

C

mode

T

C

Delay for Flash module to exit power-down

C

mode

T Data flash memory — — 30

C

Delay for Flash module to enter low-power

D

C

mode

Code flash memory — — 0.5

Code flash memory — — 30

Code flash memory — — 0.5

µs

Doc ID 16100 Rev 5 75/103

Electrical characteristics SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3

3.16 AC specifications

3.16.1 Pad AC specifications

Table 36. Output pin transition times

Symbol C Parameter Conditions

D

TC

DC

t

CC

tr

Output transition time output pin
SLOW configuration

DC

(2)

TC

DC

D

TC

DC

t

CC

tr

Output transition time output pin
MEDIUM configuration

DC

(2)

TC

DC

(2)

t

CC D

tr

t

SYM

CC T

(3)

1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 °C to T

includes device and package capacitances (C

2. C

L

3. Transition timing of both positive and negative slopes will differ maximum 50%.

Output transition time output pin
FAST configuration

Symmetric transition time, same drive
strength between N and P transistor

A MAX

PKG

= 25 pF

C

L

= 50 pF — — 100

L

= 100 pF — — 125

L

= 25 pF

L

= 50 pF — — 50

L

= 100 pF — — 75

L

= 25 pF

C

L

= 50 pF — — 20

L

= 100 pF — — 40

L

= 25 pF

L

= 50 pF — — 25

L

= 100 pF — — 40

L

= 25 pF

C

L

C

= 50 pF — — 6

L

C

= 100 pF — — 12

L

C

= 25 pF

L

C

= 50 pF — — 7

L

C

= 100 pF — — 12

L

V

= 5.0 V ± 10%, PAD3V5V = 0 — — 4

DD

V

= 3.3 V ± 10%, PAD3V5V = 1 — — 5

DD

, unless otherwise specified.

< 5 pF).

V

DD

PAD3V5V = 0

V

DD

PAD3V5V = 1

V

DD

PAD3V5V = 0
SIUL.PCRx.SRC = 1

V

DD

PAD3V5V = 1
SIUL.PCRx.SRC = 1

V

DD

PAD3V5V = 0
SIUL.PCRx.SRC = 1

V

DD

PAD3V5V = 1
SIUL.PCRx.SRC = 1

(1)

= 5.0 V ± 10%,

= 3.3 V ± 10%,

= 5.0 V ± 10%,

= 3.3 V ± 10%,

= 5.0 V ± 10%,

= 3.3 V ± 10%,

Val ue

Unit

Min Typ Max

——50

ns

——40

——10

ns

——12

—— 4

ns

—— 4

ns

76/103 Doc ID 16100 Rev 5

SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3 Electrical characteristics

Figure 19. Pad output delay

Pad
Data Input

Rising
Edge
Output
Delay

Pad
Output

3.17 AC timing characteristics

3.17.1 RESET pin characteristics

The SPC560P34/SPC560P40 implements a dedicated bidirectional RESET pin.

Figure 20. Start-up reset requirements

Falling
Edge
Output
Delay

V

DD_HV_IOx

V

OH

V

OL

/2

V

DDMIN

V

RESET

V

V

DD

IH

V

IL

device reset forced by V

t

POR

RESET

device start-up phase

Doc ID 16100 Rev 5 77/103

Electrical characteristics SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3

Figure 21. Noise filtering on reset signal

V

RESET

hw_rst

V

DD

V

IH

V

IL

filtered by
hysteresis

filtered by
lowpass filter

W

FRST

filtered by
lowpass filter

W

FRST

unknown reset
state

W

NFRST

device under hardware reset

‘1’

‘0’

Table 37. RESET electrical characteristics

Symbol C Parameter Conditions

Input high level

S

CMOS

P

R

(Schmitt Trigger)

Input low level CMOS

S

P

R

(Schmitt Trigger)

Input hysteresis

C

CMOS

C

C

(Schmitt Trigger)

Push Pull, I

= 5.0 V ± 10%, PAD3V5V = 0

V

DD

= 2 mA,

OL

V

V

V

HYS

IH

IL

(recommended)

Push Pull, I

= 5.0 V ± 10%, PAD3V5V =

V

DD

(3)

1

OL

C

P Output low level

C

V

Push Pull, I

= 3.3 V ± 10%, PAD3V5V = 1

V

DD

= 1 mA,

OL

= 1 mA,

OL

(recommended)

(2)

(1)

Value

Min Typ Max

—0.65V

DD

—VDD+0.4 V

— −0.4 — 0.35V

—0.1V

DD

——V

——0.1V

——0.1V

——0.5

DD

DD

DD

Unit

V

V

78/103 Doc ID 16100 Rev 5

SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3 Electrical characteristics

Table 37. RESET electrical characteristics (continued)

(2)

Value

Unit

——10

——20

——40

ns

——12

——25

——40

Symbol C Parameter Conditions

= 25 pF,

C

L

= 5.0 V ± 10%, PAD3V5V = 0

V

DD

CL = 50 pF,

= 5.0 V ± 10%, PAD3V5V = 0

V

DD

= 100 pF,

Output transition time
C
C

output pin

D

MEDIUM

t

tr

(4)

configuration

C

L

V

= 5.0 V ± 10%, PAD3V5V = 0

DD

= 25 pF,

C

L

= 3.3 V ± 10%, PAD3V5V = 1

V

DD

CL = 50 pF,

= 3.3 V ± 10%, PAD3V5V = 1

V

DD

= 100 pF,

C

L

V

= 3.3 V ± 10%, PAD3V5V = 1

DD

W

FRST

RESET

S

P

R

pulse

input filtered

———40ns

(1)

Min Typ Max

W

NFRS

T

RESET
S

filtered

P

R

pulse

input not

— 500 — — ns

Maximum delay

before internal reset

t

POR

C

D

is released after all
C

V

DD_HV

reach

Monotonic V

supply ramp — — 1 ms

DD_HV

nominal supply

V

= 3.3 V ± 10%, PAD3V5V = 1 10 — 150

DD

Weak pull-up current

|I

WPU

1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified.

2. All values need to be confirmed during device validation.

3. This is a transient configuration during power-up, up to the end of reset PHASE2 (refer to RGM module section of device

4. C

5. The configuration PAD3V5 = 1 when V

C

|

P

C

absolute value

reference manual).

includes device and package capacitance (C

L

Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state.

= 5.0 V ± 10%, PAD3V5V = 0 10 — 150

V

DD

V

= 5.0 V ± 10%, PAD3V5V =

DD

(5)

1

<5pF).

PKG

= 5 V is only transient configuration during power-up. All pads but RESET and

DD

10 — 250

µA

Doc ID 16100 Rev 5 79/103

Electrical characteristics SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3

3.17.2 IEEE 1149.1 interface timing

Table 38. JTAG pin AC electrical characteristics

No. Symbol C Parameter Conditions

1t

JCYC

2t

3t

4

5

6t

7t

8t

9t

10 t

11 t

12 t

13 t

JDC

TCKRISE

t

TMSS,

t

TDIS

t

TMSH,

t

TDIH

TDOV

TDOI

TDOHZ

BSDV

BSDVZ

BSDHZ

BSDST

BSDHT

CC D TCK cycle time — 100 — ns

CC D TCK clock pulse width (measured at V

DD_HV_IOx

/2) — 40 60 ns

CC D TCK rise and fall times (40 %–70 %) — — 3 ns

CC D TMS, TDI data setup time — 5 — ns

CC D TMS, TDI data hold time — 25 — ns

CC D TCK low to TDO data valid — — 40 ns

CC D TCK low to TDO data invalid — 0 — ns

CC D TCK low to TDO high impedance — 40 — ns

CC D TCK falling edge to output valid — — 50 ns

CC D

TCK falling edge to output valid out of high
impedance

— — 50 ns

CC D TCK falling edge to output high impedance — — 50 ns

CC D Boundary scan input valid to TCK rising edge — 50 — ns

CC D TCK rising edge to boundary scan input invalid — 50 — ns

Val ue

Unit

Min Max

Figure 22. JTAG test clock input timing

TCK

3

1

2

2

3

80/103 Doc ID 16100 Rev 5

SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3 Electrical characteristics

Figure 23. JTAG test access port timing

TCK

4

5

TMS, TDI

6

TDO

7

8

Doc ID 16100 Rev 5 81/103

Electrical characteristics SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3

Figure 24. JTAG boundary scan timing

TCK

Output
Signals

Output
Signals

Input
Signals

11

12

13

14

15

3.17.3 Nexus timing

Table 39. Nexus debug port timing

No. Symbol C Parameter

1t

TCYC

t

NTDIS

2

t

NTMSS

t

NTDIH

3

t

NTMSH

4t

TDOV

5t

TDOI

1. All Nexus timing relative to MCKO is measured from 50 % of MCKO and 50 % of the respective signal.

2. Lower frequency is required to be fully compliant to standard.

CC D TCK cycle time 4

CC D TDI data setup time 5 — — ns

CC D TMS data setup time 5 — — ns

CC D TDI data hold time 25 — — ns

CC D TMS data hold time 25 — — ns

CC D TCK low to TDO data valid 10 — 20 ns

CC D TCK low to TDO data invalid — — — ns

82/103 Doc ID 16100 Rev 5

(1)

Val ue

Min Typ Max

(2)

——t

Unit

CYC

SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3 Electrical characteristics

Figure 25. Nexus output timing

1

MCKO

2

3

4

MDO
MSEO
EVTO

Output Data Valid

Figure 26. Nexus event trigger and test clock timing

TCK

EVTI
EVTO

5

Doc ID 16100 Rev 5 83/103

Electrical characteristics SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3

Figure 27. Nexus TDI, TMS, TDO timing

TCK

6

7

TMS, TDI

9

8

TDO

3.17.4 External interrupt timing (IRQ pin)

Table 40. External interrupt timing

No. Symbol C Parameter Conditions

1t

IPWL

2t

IPWH

3t

ICYC

1. IRQ timing specified at f

2. Applies when IRQ pins are configured for rising edge or falling edge events, but not both.

3. N = ISR time to clear the flag.

CC D IRQ pulse width low — 4 — t

CC D IRQ pulse width high — 4 — t

CC D IRQ edge to edge time

= 64 MHz and V

SYS

(1)

DD_HV_IOx

(2)

= 3.0 V to 5.5 V, TA=TL to TH, and CL= 200 pF with SRC = 0b00.

—4+N

Val ue

Min Max

(3)

—t

Unit

CYC

CYC

CYC

84/103 Doc ID 16100 Rev 5

SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3 Electrical characteristics

Figure 28. External interrupt timing

IRQ

1

2

3

3.17.5 DSPI timing

Table 41. DSPI timing

(1)

No. Symbol C Parameter Conditions

Master (MTFE = 0)

1t

2t

3t

4t

5t

6t

7t

8t

CC D DSPI cycle time

SCK

CC D CS to SCK delay — 16 — ns

CSC

CC D After SCK delay — 26 — ns

ASC

CC D SCK duty cycle — 0.4 * t

SDC

CC D Slave access time SS active to SOUT valid — 30 ns

A

CC D

DIS

CC D PCSx to PCSS time — 13 — ns

PCSC

CC D PCSS to PCSx time — 13 — ns

PASC

Slave SOUT disable
time

Slave (MTFE = 0) 60 —

inactive to SOUT high

SS
impedance or invalid

Master (MTFE = 0)

9t

SUI

CC D

Data setup time for
inputs

Slave

Master (MTFE = 1, CPHA = 0)

Master (MTFE = 1, CPHA = 1) 35 —

Value

Unit

Min Max

60 —

0.6 * t

SCK

SCK

— 16 ns

35 —

4—

35 —

ns

ns

ns

10 t

CC D Data hold time for inputs

HI

Master (MTFE = 0) −5 —

Slave 4 —

ns

Master (MTFE = 1, CPHA = 0) 11 —
Master (MTFE = 1, CPHA = 1) −5—

Doc ID 16100 Rev 5 85/103

Electrical characteristics SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3

Table 41. DSPI timing

(1)

(continued)

No. Symbol C Parameter Conditions

Master (MTFE = 0) — 12

11 t

SUO

CC D

Data valid (after SCK
edge)

Slave — 36

Master (MTFE = 1, CPHA = 0) — 12

Master (MTFE = 1, CPHA = 1) — 12
Master (MTFE = 0) −2—

12 t

HO

CC D

Data hold time for
outputs

Slave 6 —

Master (MTFE = 1, CPHA = 0) 6 —
Master (MTFE = 1, CPHA = 1) −2—

1. All timing are provided with 50 pF capacitance on output, 1 ns transition time on input signal.

Figure 29. DSPI classic SPI timing – Master, CPHA = 0

2

PCSx

Value

Unit

Min Max

ns

ns

3

4

SCK Output
(CPOL=0)

4

SCK Output
(CPOL=1)

10

9

SIN

First Data

Data

12

SOUT

First Data Data Last Data

Note: Numbers shown reference Tab l e 4 1 .

1

Last Data

11

86/103 Doc ID 16100 Rev 5

SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3 Electrical characteristics

Figure 30. DSPI classic SPI timing – Master, CPHA = 1

Note

: Numbers shown reference

Ta bl e 4 1

.

Figure 31. DSPI classic SPI timing – Slave, CPHA = 0

2

SS

10

4

4

12

Data

Data

Last Data

SCK Input
(CPOL=0)

SCK Input
(CPOL=1)

SOUT

SIN

5

9

First Data

11

3

1

6

Note

: Numbers shown reference

Doc ID 16100 Rev 5 87/103

Ta b l e 4 1

.

Electrical characteristics SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3

Figure 32. DSPI classic SPI timing – Slave, CPHA = 1

SS

SCK Input
(CPOL=0)

SCK Input
(CPOL=1)

11

5

12

6

SOUT

SIN

Note: Numbers shown reference Ta b l e 4 1 .

First Data

9

First Data

10

Data

Data

Last Data

Last Data

Figure 33. DSPI modified transfer format timing – Master, CPHA = 0

3

PCSx

4

2

SCK Output
(CPOL=0)

SCK Output
(CPOL=1)

1

4

9

SIN

SOUT

Note: Numbers shown reference Tab l e 4 1 .

88/103 Doc ID 16100 Rev 5

First Data

12

First Data

Data

Data

10

Last Data

11

Last Data

SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3 Electrical characteristics

Figure 34. DSPI modified transfer format timing – Master, CPHA = 1

PCSx

SCK Output
(CPOL=0)

SCK Output
(CPOL=1)

9

10

SIN

SOUT

Note: Numbers shown reference Tab l e 4 1 .

First Data

First Data

Data

12

Data

Last Data

11

Last Data

Figure 35. DSPI modified transfer format timing – Slave, CPHA = 0

3

1

4

12

SS

SCK Input
(CPOL=0)

SCK Input
(CPOL=1)

2

4

5

11

6

SOUT

SIN

Note: Numbers shown reference Table 41.

First Data

9

First Data

Doc ID 16100 Rev 5 89/103

Data

Data

Last Data

10

Last Data

Electrical characteristics SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3

Figure 36. DSPI modified transfer format timing – Slave, CPHA = 1

SS

SCK Input
(CPOL=0)

SCK Input
(CPOL=1)

11

5

12

6

SOUT

SIN

Note: Numbers shown reference Tab l e 4 1 .

First Data

9

First Data

Figure 37. DSPI PCS Strobe (PCSS

7

PCSS

PCSx

Note: Numbers shown reference Tab l e 4 1 .

10

) timing

Data

Data

Last Data

Last Data

8

90/103 Doc ID 16100 Rev 5

SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3 Package characteristics

4 Package characteristics

4.1 ECOPACK

In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
specifications, grade definitions and product status are available at:
ECOPACK

®

packages, depending on their level of environmental compliance. ECOPACK®

®

is an ST trademark.

®

www.st.com

.

Doc ID 16100 Rev 5 91/103

Package characteristics SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3

4.2 Package mechanical data

4.2.1 LQFP100 mechanical outline drawing

Figure 38. LQFP100 package mechanical drawing

0.25 mm

0.10 inch

GAGE PLANE

k

D

D1

D3

75

51

L

L1

C

76

b

100 26

Pin 1
identification

50

E3 E1 E

125

e

SEATING PLANE

C

Cccc

A1

A2

A

1L_ME

92/103 Doc ID 16100 Rev 5

SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3 Package characteristics

Table 42. LQFP100 package mechanical data

Dimensions

Symbol

mm inches

(1)

Min Typ Max Min Typ Max

A — — 1.600 — — 0.0630

A1 0.050 — 0.150 0.0020 — 0.0059

A2 1.350 1.400 1.450 0.0531 0.0551 0.0571

b 0.170 0.220 0.270 0.0067 0.0087 0.0106

c 0.090 — 0.200 0.0035 — 0.0079

D 15.800 16.000 16.200 0.6220 0.6299 0.6378

D1 13.800 14.000 14.200 0.5433 0.5512 0.5591

D3 — 12.000 — — 0.4724 —

E 15.800 16.000 16.200 0.6220 0.6299 0.6378

E1 13.800 14.000 14.200 0.5433 0.5512 0.5591

E3 — 12.000 — — 0.4724 —

e — 0.500 — — 0.0197 —

L 0.450 0.600 0.750 0.0177 0.0236 0.0295

L1 — 1.000 — — 0.0394 —

k 0.0° 3.5° 7.0° 0.0° 3.5° 7.0°

(2)

ccc

1. Values in inches are converted from millimeters (mm) and rounded to four decimal digits.

2. Tolerance.

0.08 0.0031

Doc ID 16100 Rev 5 93/103

Package characteristics SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3

4.2.2 LQFP64 mechanical outline drawing

Figure 39. LQFP64 package mechanical drawing

D

C

ccc

A

A2

48

D1

D3

33

16

17

32

E3

E1 E

L1

A1 K

c

5W_ME

L

49

b

64

Pin 1
identification

Table 43. LQFP64 package mechanical data

1

Dimensions

Symbol

mm inches

(1)

Min Typ Max Min Typ Max

A——1.6——0.063

A1 0.05 — 0.15 0.002 — 0.0059

A2 1.35 1.4 1.45 0.0531 0.0551 0.0571

b 0.17 0.22 0.27 0.0067 0.0087 0.0106

c 0.09 — 0.2 0.0035 — 0.0079

D 11.8 12 12.2 0.4646 0.4724 0.4803

D1 9.8 10 10.2 0.3858 0.3937 0.4016

D3 — 7.5 — — 0.2953 —

E 11.8 12 12.2 0.4646 0.4724 0.4803

E1 9.8 10 10.2 0.3858 0.3937 0.4016

E3 — 7.5 — — 0.2953 —

e — 0.5 — — 0.0197 —

L 0.45 0.6 0.75 0.0177 0.0236 0.0295

L1 — 1 — — 0.0394 —

94/103 Doc ID 16100 Rev 5

SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3 Package characteristics

Table 43. LQFP64 package mechanical data (continued)

Dimensions

Symbol

mm inches

Min Typ Max Min Typ Max

k 0.0° 3.5° 7.0° 0.0° 3.5° 7.0°

(2)

ccc

1. Values in inches are converted from millimeters (mm) and rounded to four decimal digits.

2. Tolerance.

0.08 0.0031

(1)

Doc ID 16100 Rev 5 95/103

Ordering information SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3

5 Ordering information

Figure 40. Commercial product code structure

Example code:

Product identifier

Memory Pac kingCore Family

TemperaturePackage Custom vers.

SPC56 40 Y0P CL3 E F A

Y = Tray
R = Tape and Reel
X = Tape and Reel 90°

A = 64 MHz, 5 V
B = 64 MHz, 3.3 V
C = 40 MHz, 5 V
D = 40 MHz, 3.3 V

F = Full-featured
A = Airbag

E = Data Flash
0 = No Data Flash

B = –40 to 105 °C
C = –40 to 125 °C

L1 = LQFP64
L3 = LQFP100

34 = 192 KB
40 = 256 KB

P = SPC560Px family

0 = e200z0

SPC56 = Power Architecture in 90 nm

96/103 Doc ID 16100 Rev 5

SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3 Abbreviations

Appendix A Abbreviations

Ta bl e 4 4

Table 44. Abbreviations

lists abbreviations used in this document.

Abbreviation Meaning

CMOS Complementary metal–oxide–semiconductor

CPHA Clock phase

CPOL Clock polarity

CS Peripheral chip select

DUT Device under test

ECC Error code correction

EVTO Event out

GPIO General purpose input / output

MC Modulus counter

MCKO Message clock out

MCU Microcontroller unit

MDO Message data out

MSEO Message start/end out

MTFE Modified timing format enable

NPN Negative-positive-negative

NVUSRO Non-volatile user options register

PTF Post trimming frequency

PWM Pulse width modulation

RISC Reduced instruction set computer

SCK Serial communications clock

SOUT Serial data out

TBC To be confirmed

TBD To be defined

TCK Test clock input

TDI Test data input

TDO Test data output

TMS Test mode select

Doc ID 16100 Rev 5 97/103

Revision history SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3

Revision history

Table 45. Document revision history

Date Revision Changes

01-Sep-2009 1 Initial release.

Editorial updates
Updated the following items in the “SPC560P34/SPC560P40 device comparison”

table:
– The heading
– The “SRAM” row
– The “FlexCAN” row
– The “CTU” row
– The “FlexPWM” row
– The “LINFlex” row
– The “DSPI” row
– The “Nexus” row
Updated the “SPC560P34/SPC560P40 device configuration difference” table:
– Editorial updates
– Added the “CTU” row
– Deleted the “temperature” row
– Swapped the content of Airbag and Full Featured cells
Added the “Wakeup unit” block in the SPC560P34/SPC560P40 block diagram
Updated the “Absolute Maximum Ratings“ table
Updated the “Recommended operating conditions (5.0 V)“ table

21-May-2010 2

Updated the “Recommended operating conditions (3.3 V)“ table
Updated the “Thermal characteristics for 100-pin LQFP“ table:
– Ψ

: changed the typical value

JT

Updated the “EMI testing specifications“ table: replaced all values in “Level (Max)“
column with TBD

Updated the “Electrical characteristics“ section:
– Added the “Introduction” section
– Added the “Parameter classification“ section
– Added the “NVUSRO register“ section
– Added the “Power supplies constraints (–0.3 V ≤ V
– Added the “Independent ADC supply (–0.3 V ≤ V
– Added the “Power supplies constraints (3.0 V ≤ V
– Added the “Independent ADC supply (3.0 V ≤ V
Updated the “Power management electrical characteristics” section
Updated the “Power Up/Down sequencing” section
Updated the “DC electrical characteristics“ section
– Deleted the “NVUSRO register” section
– Updated the “DC electrical characteristics (5.0 V, NVUSRO[PAD3V5V] = 0)“ section:

– Deleted all rows concerning RESET
– Deleted “I
– Added the max value for C

VPP

“ row

IN

DD_HV_IOx

DD_HV_REG

DD_HV_IOx

DD_HV_REG

≤ 6.0 V)” figure

≤ 6.0 V)“ figure

≤ 5.5 V)“ figure

≤ 5.5 V)“ figure

98/103 Doc ID 16100 Rev 5

SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3 Revision history

Table 45. Document revision history (continued)

Date Revision Changes

– Updated the “DC electrical characteristics (3.3 V, NVUSRO[PAD3V5V] = 0)“ section:

– Deleted all rows concerning RESET

21-May-2010

(continued)

23-Dec-2010 3

2

– Deleted “I

– Added the max value for C
Added the “I/O pad current specification“ section
Updated the Order codes table.
Added “Appendix A”

“Introduction” section:
– Changed title (was “Overview“)
– Updated contents
“SPC560P34/SPC560P40 device comparison” table:
– Added sentence above table
– Removed “FlexRay” row
– “FlexCAN” row: removed link to footnote 2 for SPC560P34
– Updated “Safety port” row for SPC560P34
– Updated “DSPI” row for SPC560P34
“SPC560P34/SPC560P40 block diagram”: added the following blocks: MC_CGM,

MC_ME, MC_PCU, MC_RGM, CRC, and SSCM
Added “SPC560P34/SPC560P40 series block summary” table
“Pin muxing” section: removed information on “Symmetric pads”
“Electrical characteristics” section:

– Updated “Caution” note
– Demoted “NVUSRO register” section to subsection of “DC electrical characteristics”

section

– “NVUSRO register” section: deleted “NVUSRO[WATCHDOG_EN] field description“

section

Updated “EMI testing specifications” table
“Low voltage monitor electrical characteristics” table: updated V
“DC electrical characteristics (5.0 V, NVUSRO[PAD3V5V] = 0)” table: removed

and V

OH_SYM

“Supply current (5.0 V, NVUSRO[PAD3V5V] = 0)” table:
–I

DD_LV_CORE

–I

DD_LV_CORE

–I

DD_LV_CORE

–I

DD_FLASH

–I
–I

, Maximum mode: updated typ/max values

DD_ADC

DD_OSC

: updated max value

Updated “DC electrical characteristics (3.3 V, NVUSRO[PAD3V5V] = 1)” table
“Supply current (3.3 V, NVUSRO[PAD3V5V] = 1)” table:

–I

DD_LV_CORE

–I

DD_LV_CORE

–I

DD_FLASH

–I
–I

, Maximum mode: updated typ/max values

DD_ADC

DD_OSC

: updated max value

Added “I/O consumption” table
Removed “I/O weight” table

“ row

VPP

IN

MLVDDOK_H

rows

, RUN—Maximum mode, 40/64 MHz: updated typ/max values
, RUN—Airbag mode, 40/64 MHz: updated typ/max values
, RUN—Maximum mode, “P” parameter classification: removed

: removed rows

, RUN—Maximum mode, 40/64 MHz: updated typ/max values
, RUN—Airbag mode, 40/64 MHz: updated typ/max values

: removed rows

max value

VOL_SYM

,

Doc ID 16100 Rev 5 99/103

Revision history SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3

Table 45. Document revision history (continued)

Date Revision Changes

Updated “Main oscillator electrical characteristics (5.0 V, NVUSRO[PAD3V5V] = 0)”

table
Updated “Main oscillator electrical characteristics (3.3 V, NVUSRO[PAD3V5V] = 1)”

table

max value

CLK

= 1.08 V to 1.32 V, VSS = V

in the table title

MCYC

”, “t

MDOV

”, “t

SSPLL

MSEOV

= 0 V,

”, and

23-Dec-2010

3

(continued)

“Input clock characteristics” table: updated f
“PLLMRFM electrical specifications (V

A=TL

to TH)” table:

T
– Updated supply voltage range for V
– Updated f
– Updated C
– Updated f

max value

SCM

JITTER

max value

MOD

row

DDPLL

DDPLL

Updated “16 MHz RC oscillator electrical characteristics” table
Updated “ADC conversion characteristics” table
“Program and erase specifications” table:

–T
–T

wprogram

BKPRG

: updated initial max and max values

, 64 KB: updated initial max and max values
– added information about “erase time” for Data Flash
“Flash module life” table:
– P/E, 32 KB: added typ value
– P/E, 128 KB: added typ value
Replaced “Pad AC specifications (5.0 V, NVUSRO[PAD3V5V] = 0)” and “Pad AC

specifications (3.3 V, INVUSRO[PAD3V5V] = 1)” tables with “Output pin transition
times” table

“JTAG pin AC electrical characteristics” table:
–t

: updated max value

TDOV

–t

: added min value and removed max value

TDOHZ

“Nexus debug port timing” table: removed the rows “t

”

“t

EVTOV

Updated “External interrupt timing (IRQ pin)” table
Updated “FlexCAN timing” table
Updated “DSPI timing” table
Updated “Ordering information” section

100/103 Doc ID 16100 Rev 5