ST SPC560P34, SPC560P40 Reference Manual

RM0046

Reference manual

SPC560P34/SPC560P40 32-bit MCU family

built on the embedded Power Architecture

Introduction

The SPC560P40/34 microcontroller is built on the Power Architecture® platform. The Power
Architecture based 32-bit microcontrollers represent the latest achievement in integrated
automotive application controllers. This device family integrates the most advanced and up­to-date motor control design features.

The safety features included in SPC560P40/34 (such us fault collection unit, safety port or
flash memory and SRAM with ECC) support the design of system applications where safety
is a requirement.

®

September 2013 Doc ID 16912 Rev 5 1/936

www.st.com

Contents RM0046

Contents

Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Audience. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Chapter organization and device-specific information . . . . . . . . . . . . . . . . . . . . . 45

References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

1.1 The SPC560P40/34 microcontroller family . . . . . . . . . . . . . . . . . . . . . . . 46

1.2 Target applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

1.2.1 Application examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

1.4 Critical performance parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

1.5 Chip-level features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

1.6 Module features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

1.6.1 High performance e200z0 core processor . . . . . . . . . . . . . . . . . . . . . . . 53

1.6.2 Crossbar switch (XBAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

1.6.3 Enhanced direct memory access (eDMA) . . . . . . . . . . . . . . . . . . . . . . . 54

1.6.4 Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

1.6.5 Static random access memory (SRAM) . . . . . . . . . . . . . . . . . . . . . . . . . 56

1.6.6 Interrupt controller (INTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

1.6.7 System status and configuration module (SSCM) . . . . . . . . . . . . . . . . . 57

1.6.8 System clocks and clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

1.6.9 Frequency-modulated phase-locked loop (FMPLL) . . . . . . . . . . . . . . . . 57

1.6.10 Main oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

1.6.11 Internal RC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

1.6.12 Periodic interrupt timer (PIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

1.6.13 System timer module (STM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

1.6.14 Software watchdog timer (SWT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

1.6.15 Fault collection unit (FCU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

1.6.16 System integration unit – Lite (SIUL) . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

1.6.17 Boot and censorship . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

1.6.18 Error correction status module (ECSM) . . . . . . . . . . . . . . . . . . . . . . . . . 60

1.6.19 Peripheral bridge (PBRIDGE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

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1.6.20 Controller area network (FlexCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

1.6.21 Safety port (FlexCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

1.6.22 Serial communication interface module (LINFlex) . . . . . . . . . . . . . . . . . 62

1.6.23 Deserial serial peripheral interface (DSPI) . . . . . . . . . . . . . . . . . . . . . . 62

1.6.24 Pulse width modulator (FlexPWM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

1.6.25 eTimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

1.6.26 Analog-to-digital converter (ADC) module . . . . . . . . . . . . . . . . . . . . . . . 65

1.6.27 Cross triggering unit (CTU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

1.6.28 Nexus Development Interface (NDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

1.6.29 Cyclic redundancy check (CRC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

1.6.30 IEEE 1149.1 JTAG controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

1.6.31 On-chip voltage regulator (VREG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

1.7 Developer environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

1.8 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

2 SPC560P40/34 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

3 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

3.1 100-pin LQFP pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

3.2 64-pin LQFP pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

3.3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

3.3.1 Power supply and reference voltage pins . . . . . . . . . . . . . . . . . . . . . . . 75

3.3.2 System pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

3.3.3 Pin multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

3.4 CTU / ADC / FlexPWM / eTimer connections . . . . . . . . . . . . . . . . . . . . . 88

4 Clock Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

4.1 Clock architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

4.2 Available clock domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

4.2.1 FMPLL input reference clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

4.2.2 Clock selectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

4.2.3 Auxiliary Clock Selector 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

4.2.4 Auxiliary Clock Selector 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

4.2.5 Auxiliary Clock Selector 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

4.2.6 Auxiliary clock dividers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

4.2.7 External clock divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

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4.3 Alternate module clock domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

4.3.1 FlexCAN clock domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

4.3.2 SWT clock domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

4.3.3 Cross Triggering Unit (CTU) clock domains . . . . . . . . . . . . . . . . . . . . . . 96

4.3.4 Peripherals behind the IPS bus clock sync bridge . . . . . . . . . . . . . . . . . 96

4.4 Clock behavior in STOP and HALT mode . . . . . . . . . . . . . . . . . . . . . . . . 97

4.5 System clock functional safety . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

4.6 IRC 16 MHz internal RC oscillator (RC_CTL) . . . . . . . . . . . . . . . . . . . . . 98

4.7 XOSC external crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

4.7.1 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

4.7.2 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

4.8 Frequency Modulated Phase Locked Loop (FMPLL) . . . . . . . . . . . . . . . 100

4.8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

4.8.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

4.8.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

4.8.4 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

4.8.5 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

4.8.6 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

4.8.7 Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

4.9 Clock Monitor Unit (CMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

4.9.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

4.9.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

4.9.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

4.9.4 Memory map and register description . . . . . . . . . . . . . . . . . . . . . . . . . 111

5 Clock Generation Module (MC_CGM). . . . . . . . . . . . . . . . . . . . . . . . . . 116

5.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

5.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

5.3 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

5.4 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

5.5 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

5.5.1 Output Clock Enable Register (CGM_OC_EN) . . . . . . . . . . . . . . . . . . 124

5.5.2 Output Clock Division Select Register (CGM_OCDS_SC) . . . . . . . . . 124

5.5.3 System Clock Select Status Register (CGM_SC_SS) . . . . . . . . . . . . . 125

5.5.4 System Clock Divider Configuration Register (CGM_SC_DC0) . . . . . 126

5.5.5 Auxiliary Clock 0 Select Control Register (CGM_AC0_SC) . . . . . . . . . 127

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5.5.6 Auxiliary Clock 0 Divider Configuration Register (CGM_AC0_DC0) . . 128

5.5.7 Auxiliary Clock 1 Select Control Register (CGM_AC1_SC) . . . . . . . . . 128

5.5.8 Auxiliary Clock 1 Divider Configuration Register (CGM_AC1_DC0) . . 129

5.5.9 Auxiliary Clock 2 Select Control Register (CGM_AC2_SC) . . . . . . . . . 130

5.5.10 Auxiliary Clock 2 Divider Configuration Register (CGM_AC2_DC0) . . 131

5.6 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

5.7 System Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

5.7.1 System Clock Source Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

5.7.2 System Clock Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

5.7.3 System Clock Dividers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

5.8 Auxiliary Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

5.8.1 Auxiliary Clock Source Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

5.8.2 Auxiliary Clock Dividers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

5.9 Dividers Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

5.10 Output Clock Multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

5.11 Output Clock Division Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

6 Mode Entry Module (MC_ME) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

6.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

6.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

6.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

6.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

6.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

6.3.1 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

6.3.2 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

6.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

6.4.1 Mode Transition Request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

6.4.2 Modes Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

6.4.3 Mode Transition Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

6.4.4 Protection of Mode Configuration Registers . . . . . . . . . . . . . . . . . . . . 180

6.4.5 Mode Transition Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

6.4.6 Peripheral Clock Gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

6.4.7 Application Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

7 Power Control Unit (MC_PCU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

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7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

7.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

7.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

7.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

7.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

7.3.1 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

7.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186

8 Reset Generation Module (MC_RGM). . . . . . . . . . . . . . . . . . . . . . . . . . 187

8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

8.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

8.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189

8.1.3 Reset Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189

8.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190

8.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . 190

8.3.1 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

8.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202

8.4.1 Reset State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202

8.4.2 Destructive Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204

8.4.3 External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205

8.4.4 Functional Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205

8.4.5 Alternate Event Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206

8.4.6 Boot Mode Capturing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206

9 Interrupt Controller (INTC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208

9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208

9.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208

9.3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210

9.4 Modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210

9.4.1 Normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210

9.5 Memory map and registers description . . . . . . . . . . . . . . . . . . . . . . . . . 212

9.5.1 Module memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212

9.5.2 Registers description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212

9.6 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220

9.6.1 Interrupt request sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228

9.6.2 Priority management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228

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9.6.3 Handshaking with processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230

9.7 Initialization/application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232

9.7.1 Initialization flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232

9.7.2 Interrupt exception handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232

9.7.3 ISR, RTOS, and task hierarchy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234

9.7.4 Order of execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235

9.7.5 Priority ceiling protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236

9.7.6 Selecting priorities according to request rates and deadlines . . . . . . . 237

9.7.7 Software configurable interrupt requests . . . . . . . . . . . . . . . . . . . . . . . 237

9.7.8 Lowering priority within an ISR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238

9.7.9 Negating an interrupt request outside of its ISR . . . . . . . . . . . . . . . . . 238

9.7.10 Examining LIFO contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239

10 System Status and Configuration Module (SSCM) . . . . . . . . . . . . . . . 240

10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240

10.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240

10.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240

10.1.3 Modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241

10.2 Memory map and register description . . . . . . . . . . . . . . . . . . . . . . . . . . 241

10.2.1 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241

10.2.2 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241

10.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247

10.4 Initialization/application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247

10.4.1 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247

11 System Integration Unit Lite (SIUL) . . . . . . . . . . . . . . . . . . . . . . . . . . . 248

11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248

11.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248

11.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249

11.3.1 Register protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250

11.4 External signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250

11.4.1 Detailed signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250

11.5 Memory map and register description . . . . . . . . . . . . . . . . . . . . . . . . . . 251

11.5.1 SIUL memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251

11.5.2 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252

11.6 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267

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11.6.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267

11.6.2 Pad control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267

11.6.3 General purpose input and output pads (GPIO) . . . . . . . . . . . . . . . . . 267

11.6.4 External interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268

11.7 Pin muxing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269

12 e200z0 and e200z0h Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270

12.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270

12.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270

12.2.1 Microarchitecture summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271

12.3 Core registers and programmer’s model . . . . . . . . . . . . . . . . . . . . . . . . 275

12.3.1 Unimplemented SPRs and read-only SPRs . . . . . . . . . . . . . . . . . . . . 278

12.4 Instruction summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278

13 Peripheral Bridge (PBRIDGE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279

13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279

13.1.1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279

13.1.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279

13.1.3 Modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279

13.2 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280

13.2.1 Access support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280

13.2.2 General operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280

14 Crossbar Switch (XBAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281

14.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281

14.2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281

14.3 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282

14.4 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282

14.5 Modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282

14.5.1 Normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282

14.5.2 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282

14.6 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282

14.6.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282

14.6.2 General operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283

14.6.3 Master ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283

14.6.4 Slave ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284

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14.6.5 Priority assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284

14.6.6 Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284

15 Error Correction Status Module (ECSM) . . . . . . . . . . . . . . . . . . . . . . . 286

15.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286

15.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286

15.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286

15.4 Memory map and registers description . . . . . . . . . . . . . . . . . . . . . . . . . 286

15.4.1 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287

15.4.2 Registers description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288

15.4.3 ECSM_reg_protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306

16 Internal Static RAM (SRAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308

16.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308

16.2 SRAM operating mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308

16.3 Module memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308

16.4 Register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308

16.5 SRAM ECC mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308

16.5.1 Access timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309

16.5.2 Reset effects on SRAM accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310

16.6 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310

16.7 Initialization and application information . . . . . . . . . . . . . . . . . . . . . . . . . 310

17 Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311

17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311

17.2 Platform Flash controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311

17.2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311

17.2.2 Modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313

17.2.3 External signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313

17.2.4 Memory map and registers description . . . . . . . . . . . . . . . . . . . . . . . . 313

17.2.5 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315

17.2.6 Basic interface protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315

17.2.7 Access protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316

17.2.8 Read cycles — buffer miss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316

17.2.9 Read cycles — buffer hit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316

17.2.10 Write cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317

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17.2.11 Error termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317

17.2.12 Access pipelining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317

17.2.13 Flash error response operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318

17.2.14 Bank0 page read buffers and prefetch operation . . . . . . . . . . . . . . . . . 318

17.2.15 Bank1 temporary holding register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320

17.2.16 Read-While-Write functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321

17.2.17 Wait state emulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322

17.2.18 Timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323

17.3 Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330

17.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330

17.3.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330

17.3.3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330

17.3.4 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332

17.3.5 Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336

17.3.6 Registers description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339

17.3.7 Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339

17.3.8 Code Flash programming considerations . . . . . . . . . . . . . . . . . . . . . . 370

18 Enhanced Direct Memory Access (eDMA) . . . . . . . . . . . . . . . . . . . . . . 382

18.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382

18.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382

18.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383

18.4 Modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383

18.4.1 Normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383

18.4.2 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384

18.5 Memory map and register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384

18.5.1 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384

18.5.2 Register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386

18.6 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406

18.6.1 eDMA microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406

18.6.2 eDMA basic data flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407

18.6.3 eDMA performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410

18.7 Initialization / application information . . . . . . . . . . . . . . . . . . . . . . . . . . . 414

18.7.1 eDMA initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414

18.7.2 DMA programming errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416

18.7.3 DMA request assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416

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18.7.4 DMA arbitration mode considerations . . . . . . . . . . . . . . . . . . . . . . . . . 417

18.7.5 DMA transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417

18.7.6 TCD status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421

18.7.7 Channel linking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422

18.7.8 Dynamic programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423

19 DMA Channel Mux (DMA_MUX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424

19.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424

19.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424

19.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424

19.1.3 Modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425

19.2 External signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425

19.2.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425

19.3 Memory map and register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425

19.3.1 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425

19.3.2 Register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427

19.4 DMA request mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 428

19.5 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429

19.5.1 DMA channels with periodic triggering capability . . . . . . . . . . . . . . . . 429

19.5.2 DMA channels with no triggering capability . . . . . . . . . . . . . . . . . . . . . 432

19.6 Initialization/application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432

19.6.1 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432

19.6.2 Enabling and configuring sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432

20 Deserial Serial Peripheral Interface (DSPI) . . . . . . . . . . . . . . . . . . . . . 437

20.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437

20.2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437

20.3 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 438

20.4 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 438

20.5 Modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439

20.5.1 Master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 440

20.5.2 Slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 440

20.5.3 Module disable mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 440

20.5.4 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 440

20.6 External signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 440

20.6.1 Signal overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 440

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20.6.2 Signal names and descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441

20.7 Memory map and registers description . . . . . . . . . . . . . . . . . . . . . . . . . 442

20.7.1 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 442

20.7.2 Registers description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443

20.8 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460

20.8.1 Modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461

20.8.2 Start and stop of DSPI transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 462

20.8.3 Serial Peripheral Interface (SPI) configuration . . . . . . . . . . . . . . . . . . . 463

20.8.4 DSPI baud rate and clock delay generation . . . . . . . . . . . . . . . . . . . . . 466

20.8.5 Transfer formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 469

20.8.6 Continuous Serial communications clock . . . . . . . . . . . . . . . . . . . . . . 476

20.8.7 Interrupts/DMA requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 478

20.8.8 Power saving features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 479

20.9 Initialization and application information . . . . . . . . . . . . . . . . . . . . . . . . . 480

20.9.1 Managing queues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 480

20.9.2 Baud rate settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 480

20.9.3 Delay settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 482

20.9.4 Calculation of FIFO pointer addresses . . . . . . . . . . . . . . . . . . . . . . . . 482

21 LIN Controller (LINFlex) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485

21.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485

21.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485

21.2.1 LIN mode features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485

21.2.2 UART mode features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485

21.2.3 Features common to LIN and UART . . . . . . . . . . . . . . . . . . . . . . . . . . 486

21.3 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 486

21.4 Fractional baud rate generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 487

21.5 Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489

21.5.1 Initialization mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489

21.5.2 Normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489

21.5.3 Low power mode (Sleep) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489

21.6 Test modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 490

21.6.1 Loop Back mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 490

21.6.2 Self Test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 490

21.7 Memory map and registers description . . . . . . . . . . . . . . . . . . . . . . . . . 491

21.7.1 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491

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21.8 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 518

21.8.1 UART mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 518

21.8.2 LIN mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 520

21.8.3 8-bit timeout counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 528

21.8.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 529

22 FlexCAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 531

22.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 531

22.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 531

22.1.2 FlexCAN module features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 532

22.1.3 Modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533

22.2 External signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 534

22.2.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 534

22.2.2 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 534

22.3 Memory map and registers description . . . . . . . . . . . . . . . . . . . . . . . . . 534

22.3.1 FlexCAN memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 534

22.3.2 Message buffer structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 536

22.3.3 Rx FIFO structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 540

22.3.4 Registers description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542

22.4 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 560

22.4.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 560

22.4.2 Transmit process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 560

22.4.3 Arbitration process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 561

22.4.4 Receive process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 561

22.4.5 Matching process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 563

22.4.6 Data coherence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 564

22.4.7 Rx FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 566

22.4.8 CAN protocol related features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 567

22.4.9 Modes of operation details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 571

22.4.10 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572

22.4.11 Bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 573

22.5 Initialization/application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 573

22.5.1 FlexCAN initialization sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 574

23 Analog-to-Digital Converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 575

23.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 575

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23.1.1 Device-specific features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 575

23.1.2 Device-specific pin configuration features . . . . . . . . . . . . . . . . . . . . . . 575

23.1.3 Device-specific implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 576

23.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 576

23.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 577

23.3.1 Analog channel conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 577

23.3.2 Analog clock generator and conversion timings . . . . . . . . . . . . . . . . . . 580

23.3.3 ADC sampling and conversion timing . . . . . . . . . . . . . . . . . . . . . . . . . 581

23.3.4 ADC CTU (Cross Triggering Unit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 583

23.3.5 Programmable analog watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 584

23.3.6 DMA functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 585

23.3.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 585

23.3.8 Power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 586

23.3.9 Auto-clock-off mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 586

23.4 Register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 586

23.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 586

23.4.2 Control logic registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 588

23.4.3 Interrupt registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 591

23.4.4 DMA registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 595

23.4.5 Threshold registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 597

23.4.6 Conversion Timing Registers CTR[0] . . . . . . . . . . . . . . . . . . . . . . . . . 599

23.4.7 Mask registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 599

23.4.8 Delay registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 601

23.4.9 Data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 601

24 Cross Triggering Unit (CTU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 603

24.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 603

24.2 CTU overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 603

24.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 604

24.3.1 Trigger events features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 604

24.3.2 Trigger generator subunit (TGS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 605

24.3.3 TGS in triggered mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 605

24.3.4 TGS in sequential mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 606

24.3.5 TGS counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 607

24.4 Scheduler subunit (SU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 608

24.4.1 ADC commands list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 610

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24.4.2 ADC commands list format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 610

24.4.3 ADC results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 612

24.5 Reload mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 613

24.6 Power safety mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 614

24.6.1 MDIS bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 614

24.6.2 STOP mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 614

24.7 Interrupts and DMA requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 615

24.7.1 DMA support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 615

24.7.2 CTU faults and errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 615

24.7.3 CTU interrupt/DMA requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 616

24.8 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 617

24.8.1 Trigger Generator Sub-unit Input Selection Register (TGSISR) . . . . . 621

24.8.2 Trigger Generator Sub-unit Control Register (TGSCR) . . . . . . . . . . . . 624

24.8.3 Trigger x Compare Register (TxCR, x = 0...7) . . . . . . . . . . . . . . . . . . . 624

24.8.4 TGS Counter Compare Register (TGSCCR) . . . . . . . . . . . . . . . . . . . . 625

24.8.5 TGS Counter Reload Register (TGSCRR) . . . . . . . . . . . . . . . . . . . . . 625

24.8.6 Commands list control register 1 (CLCR1) . . . . . . . . . . . . . . . . . . . . . 626

24.8.7 Commands list control register 2 (CLCR2) . . . . . . . . . . . . . . . . . . . . . 626

24.8.8 Trigger handler control register 1 (THCR1) . . . . . . . . . . . . . . . . . . . . . 627

24.8.9 Trigger handler control register 2 (THCR2) . . . . . . . . . . . . . . . . . . . . . 629

24.8.10 Commands list register x (x = 1,...,24) (CLRx) . . . . . . . . . . . . . . . . . . . 631

24.8.11 FIFO DMA control register (FDCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 632

24.8.12 FIFO control register (FCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 633

24.8.13 FIFO threshold register (FTH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 634

24.8.14 FIFO status register (FST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 635

24.8.15 FIFO Right aligned data x (x = 0,...,3) (FRx) . . . . . . . . . . . . . . . . . . . . 636

24.8.16 FIFO signed Left aligned data x (x = 0,...,3) (FLx) . . . . . . . . . . . . . . . . 637

24.8.17 Cross triggering unit error flag register (CTUEFR) . . . . . . . . . . . . . . . 637

24.8.18 Cross triggering unit interrupt flag register (CTUIFR) . . . . . . . . . . . . . 638

24.8.19 Cross triggering unit interrupt/DMA register (CTUIR) . . . . . . . . . . . . . 639

24.8.20 Control ON time register (COTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 640

24.8.21 Cross triggering unit control register (CTUCR) . . . . . . . . . . . . . . . . . . 641

24.8.22 Cross triggering unit digital filter (CTUDF) . . . . . . . . . . . . . . . . . . . . . . 642

24.8.23 Cross triggering unit power control register (CTUPCR) . . . . . . . . . . . . 642

25 FlexPWM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 643

25.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 643

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25.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 643

25.3 Modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 644

25.4 Block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 645

25.4.1 Module level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 645

25.4.2 PWM submodule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 646

25.5 External signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 647

25.5.1 PWMA[n] and PWMB[n] — external PWM pair . . . . . . . . . . . . . . . . . . 647

25.5.2 PWMX[n] — auxiliary PWM signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . 647

25.5.3 FAULT[n] — fault inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 647

25.5.4 EXT_SYNC — external synchronization signal . . . . . . . . . . . . . . . . . . 647

25.5.5 EXT_FORCE — external output force signal . . . . . . . . . . . . . . . . . . . . 647

25.5.6 OUT_TRIG0[n] and OUT_TRIG1[n] — output triggers . . . . . . . . . . . . 647

25.5.7 EXT_CLK — external clock signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . 647

25.6 Memory map and registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 648

25.6.1 FlexPWM module memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 648

25.6.2 Register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 650

25.6.3 Submodule registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 651

25.6.4 Configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 665

25.6.5 Fault channel registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 671

25.7 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 675

25.7.1 Center-aligned PWMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 675

25.7.2 Edge-aligned PWMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 676

25.7.3 Phase-shifted PWMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 676

25.7.4 Double switching PWMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 678

25.7.5 ADC triggering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 679

25.7.6 Synchronous switching of multiple outputs . . . . . . . . . . . . . . . . . . . . . 681

25.8 Functional details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 682

25.8.1 PWM clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 683

25.8.2 Register reload logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 683

25.8.3 Counter synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 684

25.8.4 PWM generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 685

25.8.5 Output compare capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 687

25.8.6 Force out logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 687

25.8.7 Independent or complementary channel operation . . . . . . . . . . . . . . . 688

25.8.8 Deadtime insertion logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 689

25.8.9 Top/bottom correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 691

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25.8.10 Manual correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 693

25.8.11 Output logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 694

25.8.12 Fault protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 695

25.8.13 Fault pin filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 696

25.8.14 Automatic fault clearing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 697

25.8.15 Manual fault clearing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 697

25.8.16 Fault testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 698

25.9 PWM generator loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 698

25.9.1 Load enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 698

25.9.2 Load frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 699

25.9.3 Reload flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 700

25.9.4 Reload errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 700

25.9.5 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 700

25.10 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 701

25.11 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 701

25.12 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 702

26 eTimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 703

26.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 703

26.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 704

26.3 Module block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 705

26.4 Channel block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 706

26.5 External signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 706

26.5.1 ETC[5:0]—eTimer input/outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 706

26.6 Memory map and registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 706

26.6.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 706

26.6.2 Timer channel registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 710

26.6.3 Watchdog timer registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 725

26.6.4 Configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 726

26.7 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 729

26.7.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 729

26.7.2 Counting modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 729

26.7.3 Other features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 734

26.8 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 735

26.9 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 736

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26.10 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 736

27 Functional Safety . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 737

27.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 737

27.2 Register protection module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 737

27.2.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 737

27.2.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 738

27.2.3 Modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 738

27.2.4 External signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 738

27.2.5 Memory map and registers description . . . . . . . . . . . . . . . . . . . . . . . . 738

27.2.6 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 742

27.2.7 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 745

27.3 Software Watchdog Timer (SWT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 745

27.3.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 745

27.3.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 746

27.3.3 Modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 746

27.3.4 External signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 746

27.3.5 SWT memory map and registers description . . . . . . . . . . . . . . . . . . . 746

27.3.6 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 752

28 Fault Collection Unit (FCU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 754

28.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 754

28.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 754

28.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 757

28.1.3 Modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 757

28.2 Memory map and register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . 757

28.2.1 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 758

28.2.2 Register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 758

28.2.3 Register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 760

28.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 771

28.3.1 State machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 772

28.3.2 Output generation protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 773

29 Wakeup Unit (WKPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 776

29.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 776

29.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 776

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29.3 External signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 776

29.4 Memory map and registers description . . . . . . . . . . . . . . . . . . . . . . . . . 776

29.4.1 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 776

29.4.2 Registers description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 777

29.5 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 779

29.5.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 779

29.5.2 Non-Maskable Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 779

30 Periodic Interrupt Timer (PIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 781

30.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 781

30.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 781

30.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 781

30.2 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 782

30.3 Memory map and registers description . . . . . . . . . . . . . . . . . . . . . . . . . 782

30.3.1 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 782

30.3.2 Registers description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 783

30.4 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 787

30.4.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 787

30.4.2 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 789

30.5 Initialization and application information . . . . . . . . . . . . . . . . . . . . . . . . . 789

30.5.1 Example configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 789

31 System Timer Module (STM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 790

31.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 790

31.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 790

31.3 Modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 790

31.4 External signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 790

31.5 Memory map and registers description . . . . . . . . . . . . . . . . . . . . . . . . . 790

31.5.1 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 790

31.5.2 Registers description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 791

31.6 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 795

32 Cyclic Redundancy Check (CRC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 796

32.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 796

32.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 796

32.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 796

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32.2.1 Standard features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 796

32.3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 796

32.3.1 IPS bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 797

32.4 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 797

32.5 Memory map and registers description . . . . . . . . . . . . . . . . . . . . . . . . . 799

32.5.1 CRC Configuration Register (CRC_CFG) . . . . . . . . . . . . . . . . . . . . . . 800

32.5.2 CRC Input Register (CRC_INP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 801

32.5.3 CRC Current Status Register (CRC_CSTAT) . . . . . . . . . . . . . . . . . . . 802

32.5.4 CRC Output Register (CRC_OUTP) . . . . . . . . . . . . . . . . . . . . . . . . . . 802

32.6 Use cases and limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 803

33 Boot Assist Module (BAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 806

33.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 806

33.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 806

33.3 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 806

33.4 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 806

33.5 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 807

33.5.1 Entering boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 807

33.5.2 SPC560P40/34 boot pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 808

33.5.3 Reset Configuration Half Word (RCHW) . . . . . . . . . . . . . . . . . . . . . . . 809

33.5.4 Single chip boot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 810

33.5.5 Boot through BAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 811

33.5.6 Boot from UART—autobaud disabled . . . . . . . . . . . . . . . . . . . . . . . . . 817

33.5.7 Bootstrap with FlexCAN—autobaud disabled . . . . . . . . . . . . . . . . . . . 818

33.6 FlexCAN boot mode download protocol . . . . . . . . . . . . . . . . . . . . . . . . . 819

33.6.1 Autobaud feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 819

33.6.2 Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 831

33.7 Censorship . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 831

34 Voltage Regulators and Power Supplies . . . . . . . . . . . . . . . . . . . . . . . 836

34.1 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 836

34.1.1 High Power or Main Regulator (HPREG) . . . . . . . . . . . . . . . . . . . . . . . 836

34.1.2 Low Voltage Detectors (LVD) and Power On Reset (POR) . . . . . . . . . 836

34.1.3 VREG digital interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 837

34.1.4 Registers Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 838

34.2 Power supply strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 839

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35 IEEE 1149.1 Test Access Port Controller (JTAGC) . . . . . . . . . . . . . . . 841

35.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 841

35.2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 841

35.3 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 841

35.4 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 842

35.5 Modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 842

35.5.1 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 842

35.5.2 IEEE 1149.1-2001 defined test modes . . . . . . . . . . . . . . . . . . . . . . . . 842

35.6 External signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 843

35.7 Memory map and registers description . . . . . . . . . . . . . . . . . . . . . . . . . 843

35.7.1 Instruction register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 844

35.7.2 Bypass register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 844

35.7.3 Device identification register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 844

35.7.4 Boundary scan register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 845

35.8 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 845

35.8.1 JTAGC reset configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 845

35.8.2 IEEE 1149.1-2001 (JTAG) Test Access Port (TAP) . . . . . . . . . . . . . . . 845

35.8.3 TAP controller state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 846

35.8.4 JTAGC instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 848

35.8.5 Boundary scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 850

35.9 e200z0 OnCE controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 850

35.9.1 e200z0 OnCE controller block diagram . . . . . . . . . . . . . . . . . . . . . . . . 850

35.9.2 e200z0 OnCE controller functional description . . . . . . . . . . . . . . . . . . 851

35.9.3 e200z0 OnCE controller registers description . . . . . . . . . . . . . . . . . . . 851

35.10 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 853

36 Nexus Development Interface (NDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . 854

36.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 854

36.2 Information specific to this device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 854

36.2.1 Features not supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 854

36.3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 855

36.4 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 855

36.5 Modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 856

36.5.1 Nexus reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 856

36.5.2 NDI modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 856

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Contents RM0046

36.6 External signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 856

36.7 Memory map and registers description . . . . . . . . . . . . . . . . . . . . . . . . . 857

36.8 Interrupts and Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 857

36.9 Debug support overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 858

36.9.1 Software Debug Facilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 858

36.9.2 Additional Debug Facilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 858

36.9.3 Hardware Debug Facilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 859

36.9.4 Sharing Debug Resources by Software/Hardware . . . . . . . . . . . . . . . 859

36.10 Software Debug Events and Exceptions . . . . . . . . . . . . . . . . . . . . . . . . 861

36.10.1 Instruction Address Compare Event . . . . . . . . . . . . . . . . . . . . . . . . . . 862

36.10.2 Data Address Compare Event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 863

36.10.3 Linked Instruction Address and Data Address Compare Event . . . . . . 865

36.10.4 Trap Debug Event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 866

36.10.5 Branch Taken Debug Event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 866

36.10.6 Instruction Complete Debug Event . . . . . . . . . . . . . . . . . . . . . . . . . . . 866

36.10.7 Interrupt Taken Debug Event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 866

36.10.8 Critical Interrupt Taken Debug Event . . . . . . . . . . . . . . . . . . . . . . . . . . 867

36.10.9 Return Debug Event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 867

36.10.10 Critical Return Debug Event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 867

36.10.11 External Debug Event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 867

36.10.12 Unconditional Debug Event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 868

36.11 Debug Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 868

36.11.1 Debug Address and Value Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 868

36.11.2 Debug Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 869

36.11.3 Debug External Resource Control Register (DBERC0) . . . . . . . . . . . . 882

36.12 External Debug Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 888

36.12.1 OnCE Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 888

36.12.2 JTAG/OnCE Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 891

36.12.3 OnCE Internal Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 891

36.12.4 OnCE Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 892

36.12.5 e200z0h OnCE Controller and Serial Interface . . . . . . . . . . . . . . . . . . 893

36.12.6 Access to Debug Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 901

36.12.7 Methods of Entering Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 903

36.12.8 CPU Status and Control Scan Chain Register (CPUSCR) . . . . . . . . . 904

36.13 Watchpoint Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 910

36.14 Basic Steps for Enabling, Using, and Exiting External Debug Mode . . . 911

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36.15 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 912

36.15.1 Enabling Nexus clients for TAP access . . . . . . . . . . . . . . . . . . . . . . . . 912

36.15.2 Debug mode control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 913

Appendix A Registers Under Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 914

Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 925

Doc ID 16912 Rev 5 23/936

List of tables RM0046

List of tables

Table 1. SPC560P40/34 device comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Table 2. SPC560P40 device configuration differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 3. Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Table 4. Supply pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Table 5. System pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Table 6. Pin muxing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Table 7. CTU / ADC / FlexPWM / eTimer connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Table 8. RC_CTL field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Table 9. Crystal oscillator truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Table 10. OSC_CTL memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Table 11. OSC_CTL field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Table 12. FMPLL memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Table 13. CR field descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Table 14. MR field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Table 15. Progressive clock switching on pll_select rising edge . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Table 16. CMU module summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Table 17. CMU memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Table 18. CMU_0_CSR field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

Table 19. CMU_0_FDR field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Table 20. CMU_0_HFREFR_A field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Table 21. CMU_0_LFREFR_A fields descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

Table 22. CMU_0_ISR field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

Table 23. CMU_0_MDR field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Table 24. MC_CGM Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

Table 25. MC_CGM Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Table 26. Output Clock Enable Register (CGM_OC_EN) Field Descriptions. . . . . . . . . . . . . . . . . . 124

Table 27. Output Clock Division Select Register (CGM_OCDS_SC) Field Descriptions . . . . . . . . . 125

Table 28. System Clock Select Status Register (CGM_SC_SS) Field Descriptions . . . . . . . . . . . . 126

Table 29. System Clock Divider Configuration Register (CGM_SC_DC0) Field Descriptions . . . . . 126

Table 30. Auxiliary Clock 0 Select Control Register (CGM_AC0_SC) Field Descriptions . . . . . . . . 127

Table 31. Auxiliary Clock 0 Divider Configuration Register (CGM_AC0_DC0) Field Descriptions. . 128

Table 32. Auxiliary Clock 1 Select Control Register (CGM_AC1_SC) Field Descriptions . . . . . . . . 129

Table 33. Auxiliary Clock 1 Divider Configuration Register (CGM_AC1_DC0) Field Descriptions. . 129

Table 34. Auxiliary Clock 2 Select Control Register (CGM_AC2_SC) Field Descriptions . . . . . . . . 130

Table 35. Auxiliary Clock 2 Divider Configuration Register (CGM_AC2_DC0) Field Descriptions. . 131

Table 36. MC_ME Mode Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

Table 37. MC_ME Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

Table 38. MC_ME Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

Table 39. Global Status Register (ME_GS) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

Table 40. Mode Control Register (ME_MCTL) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . 150

Table 41. Mode Enable Register (ME_ME) Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

Table 42. Interrupt Status Register (ME_IS) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

Table 43. Interrupt Mask Register (ME_IM) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

Table 44. Invalid Mode Transition Status Register (ME_IMTS) Field Descriptions . . . . . . . . . . . . . 154

Table 45. Debug Mode Transition Status Register (ME_DMTS) Field Descriptions . . . . . . . . . . . . 156

Table 46. Mode Configuration Registers (ME_<mode>_MC) Field Descriptions . . . . . . . . . . . . . . . 162

Table 47. Peripheral Status Registers 0…4 (ME_PS0…4) Field Descriptions. . . . . . . . . . . . . . . . . 165

Table 48. Run Peripheral Configuration Registers (ME_RUN_PC0…7) Field Descriptions. . . . . . . 166

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Table 49. Low-Power Peripheral Configuration Registers (ME_LP_PC0…7) Field Descriptions. . . 167

Table 50. Peripheral Control Registers (ME_PCTL0…143) Field Descriptions . . . . . . . . . . . . . . . . 168

Table 51. MC_ME Resource Control Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

Table 52. MC_ME System Clock Selection Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

Table 53. MC_PCU Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

Table 54. MC_PCU Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

Table 55. Power Domain Status Register (PCU_PSTAT) Field Descriptions. . . . . . . . . . . . . . . . . . 186

Table 56. MC_RGM Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190

Table 57. MC_RGM Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191

Table 58. Functional Event Status Register (RGM_FES) Field Descriptions . . . . . . . . . . . . . . . . . . 193

Table 59. Destructive Event Status Register (RGM_DES) Field Descriptions . . . . . . . . . . . . . . . . . 194

Table 60. Functional Event Reset Disable Register (RGM_FERD) Field Descriptions . . . . . . . . . . 196

Table 61. Destructive Event Reset Disable Register (RGM_DERD) Field Descriptions . . . . . . . . . 197

Table 62. Functional Event Alternate Request Register (RGM_FEAR) Field Descriptions . . . . . . . 198

Table 63. Functional Event Short Sequence Register (RGM_FESS) Field Descriptions . . . . . . . . . 199

Table 64. Functional Bidirectional Reset Enable Register (RGM_FBRE) Field Descriptions. . . . . . 201

Table 65. MC_RGM Reset Implications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202

Table 66. MC_RGM Alternate Event Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206

Table 67. Interrupt sources available . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209

Table 68. INTC memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212

Table 69. INTC_MCR field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213

Table 70. INTC_CPR field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214

Table 71. INTC_IACKR field descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215

Table 72. INTC_SSCIR[0:7] field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217

Table 73. INTC_PSR0_3–INTC_PSR220–221 field descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . 218

Table 74. INTC Priority Select Register address offsets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218

Table 75. Interrupt vector table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220

Table 76. Order of ISR execution example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235

Table 77. SSCM memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241

Table 78. STATUS allowed register accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242

Table 79. STATUS field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242

Table 80. MEMCONFIG field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243

Table 81. MEMCONFIG allowed register accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243

Table 82. ERROR field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244

Table 83. ERROR allowed register accesses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244

Table 84. DEBUGPORT field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245

Table 85. Debug Status Port modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245

Table 86. DEBUGPORT allowed register accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246

Table 87. PWCMPH/L field descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246

Table 88. PWCMPH/L allowed register accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247

Table 89. SIUL signal properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250

Table 90. SIUL memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251

Table 91. MIDR1 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253

Table 92. MIDR2 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254

Table 93. ISR field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255

Table 94. IRER field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255

Table 95. IREER field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256

Table 96. IFEER field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256

Table 97. IFER field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257

Table 98. PCR[0:71] field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258

Table 99. PCR[n] reset value exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259

Table 100. PCR bit implementation by pad type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259

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List of tables RM0046

Table 101. PSMI[0_3:32_35] field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260

Table 102. Pad selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260

Table 103. GPDO[0_3:68_71] field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262

Table 104. GPDI[0_3:68_71] field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263

Table 105. PGPDO0_3 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263

Table 106. PGPDI[0:3] field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264

Table 107. MPGPDO[0:6] field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265

Table 108. IFMC[0:24] field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265

Table 109. IFCPR field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266

Table 110. Device XBAR switch ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281

Table 111. Hardwired bus master priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284

Table 112. ECSM registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287

Table 113. PCT field descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288

Table 114. REV field descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289

Table 115. PLAMC field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289

Table 116. ASC field descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290

Table 117. IMC field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290

Table 118. MRSR field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291

Table 119. MIR field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291

Table 120. MUDCR field descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292

Table 121. ECR field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294

Table 122. ESR field descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295

Table 123. EEGR field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297

Table 124. FEAR field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299

Table 125. FEMR field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299

Table 126. FEAT field descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300

Table 127. FEDR field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301

Table 128. REAR field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302

Table 129. RESR field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302

Table 130. RAM syndrome mapping for single-bit correctable errors. . . . . . . . . . . . . . . . . . . . . . . . . 302

Table 131. REMR field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304

Table 132. REAT field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305

Table 133. REDR field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306

Table 134. SRAM operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308

Table 135. SRAM memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308

Table 136. Number of wait states required for SRAM operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . 309

Table 137. Flash-related regions in the system memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314

Table 138. Platform Flash controller 32-bit memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315

Table 139. Platform Flash controller stall-while-write interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322

Table 140. Additional wait state encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323

Table 141. Extended additional wait state encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323

Table 142. 288 KB code Flash module sectorization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333

Table 143. 64 KB data Flash module sectorization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333

Table 144. TestFlash structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334

Table 145. Shadow sector structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336

Table 146. Flash registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339

Table 147. Flash 256 KB bank0 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339

Table 148. Flash 64 KB bank1 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341

Table 149. MCR field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342

Table 150. MCR bits set/clear priority levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346

Table 151. LML and NVLML field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347

Table 152. SLL and NVSLL field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350

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Table 153. LMS field descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352

Table 154. ADR field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352

Table 155. ADR content: priority list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353

Table 156. PFCR0 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354

Table 157. PFCR1 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357

Table 158. PFAPR field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359

Table 159. UT0 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361

Table 160. UT1 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363

Table 161. UT2 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363

Table 162. UMSIR0 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364

Table 163. UMISR1 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364

Table 164. UMISR2 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365

Table 165. UMISR3 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366

Table 166. UMISR4 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367

Table 167. NVPWD0 field descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367

Table 168. NVPWD1 field descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368

Table 169. NVSCI0 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368

Table 170. NVSCI1 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369

Table 171. NVUSRO field descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370

Table 172. Flash modify operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371

Table 173. Bits manipulation: double words with the same ECC value . . . . . . . . . . . . . . . . . . . . . . . 379

Table 174. Bits manipulation: censorship management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381

Table 175. eDMA memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384

Table 176. EDMA_CR field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387

Table 177. EDMA_ESR field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388

Table 178. EDMA_ERQRL field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390

Table 179. EDMA_EEIRL field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391

Table 180. EDMA_SERQR field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391

Table 181. EDMA_CERQR field descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392

Table 182. EDMA_SEEIR field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393

Table 183. EDMA_CEEIR field descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393

Table 184. EDMA_CIRQR field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394

Table 185. EDMA_CERR field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394

Table 186. EDMA_SSBR field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395

Table 187. EDMA_CDSBR field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396

Table 188. EDMA_IRQRL field descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396

Table 189. EDMA_ERL field descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397

Table 190. EDMA_HRSL field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398

Table 191. EDMA_CPRn field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399

Table 192. TCDn 32-bit memory structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399

Table 193. TCDn field descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401

Table 194. eDMA peak transfer rates (MB/Sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411

Table 195. eDMA peak request Rate (MReq/sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412

Table 196. TCD primary control and status fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414

Table 197. DMA request summary for eDMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416

Table 198. Modulo feature example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420

Table 199. Channel linking parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423

Table 200. DMA_MUX memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425

Table 201. CHCONFIG#x field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427

Table 202. Channel and trigger enabling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427

Table 203. DMA channel mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 428

Table 204. Signal properties. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441

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List of tables RM0046

Table 205. DSPI memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 442

Table 206. DSPIx_MCR field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 444

Table 207. DSPIx_TCR field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447

Table 208. DSPIx_CTARn field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 448

Table 209. DSPI SCK duty cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 451

Table 210. DSPI transfer frame size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 451

Table 211. DSPI PCS to SCK delay scaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 452

Table 212. DSPI after SCK delay scaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 452

Table 213. DSPI delay after transfer scaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 452

Table 214. DSPI baud rate scaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453

Table 215. DSPIx_SR field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453

Table 216. DSPIx_RSER field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455

Table 217. DSPIx_PUSHR field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457

Table 218. DSPIx_POPR field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459

Table 219. DSPIx_TXFRn field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460

Table 220. DSPIx_RXFRn field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460

Table 221. State transitions for start and stop of DSPI transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463

Table 222. Baud rate computation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 467

Table 223. CS to SCK delay computation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 467

Table 224. After SCK delay computation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 467

Table 225. Delay after transfer computation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 468

Table 226. Peripheral Chip Select strobe assert computation example . . . . . . . . . . . . . . . . . . . . . . . 469

Table 227. Peripheral Chip Select strobe negate computation example . . . . . . . . . . . . . . . . . . . . . . 469

Table 228. Delayed master sample point . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 472

Table 229. Interrupt and DMA request conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 478

Table 230. Baud rate values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 481

Table 231. Delay values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 482

Table 232. Error calculation for programmed baud rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 488

Table 233. LINFlex memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491

Table 234. LINCR1 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493

Table 235. Checksum bits configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494

Table 236. LIN master break length selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494

Table 237. Operating mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495

Table 238. LINIER field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496

Table 239. LINSR field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 498

Table 240. LINESR field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500

Table 241. UARTCR field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502

Table 242. UARTSR field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503

Table 243. LINTCSR field descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505

Table 244. LINOCR field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506

Table 245. LINTOCR field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 507

Table 246. LINFBRR field descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 507

Table 247. LINIBRR field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 508

Table 248. Integer baud rate selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 508

Table 249. LINCFR field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509

Table 250. LINCR2 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510

Table 251. BIDR field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511

Table 252. BDRL field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512

Table 253. BDRM field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513

Table 254. IFER field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513

Table 255. IFMI field descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 514

Table 256. IFMR field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 515

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Table 257. IFMR[IFM] configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 515

Table 258. IFCR2n field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 516

Table 259. IFCR2n + 1 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 517

Table 260. Message buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 519

Table 261. Filter to interrupt vector correlation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 525

Table 262. LINFlex interrupt control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 529

Table 263. FlexCAN signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 534

Table 264. FlexCAN module memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535

Table 265. FlexCAN register reset status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535

Table 266. Message Buffer MB0 memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 536

Table 267. Message Buffer structure field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537

Table 268. Message buffer code for Rx buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 538

Table 269. Message Buffer code for Tx buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 539

Table 270. MB0–MB31 addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 539

Table 271. ID Table 0 - 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 541

Table 272. Rx FIFO Structure field description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542

Table 273. MCR field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 543

Table 274. IDAM coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 546

Table 275. CTRL field descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 547

Table 276. TIMER field descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 550

Table 277. RXGMASK field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 551

Table 278. RX14MASK field description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 551

Table 279. RX15MASK field description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 552

Table 280. Error and Status Register (ESR) field description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 554

Table 281. Fault confinement state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 556

Table 282. IMASK1 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 557

Table 283. IFLAG1 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 557

Table 284. RXIMR0–RXIMR31 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 559

Table 285. RXIMR0–RXIMR31 addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 559

Table 286. Time segment syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 570

Table 287. CAN standard compliant bit time segment settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 570

Table 288. Minimum ratio between peripheral clock frequency and CAN bit rate . . . . . . . . . . . . . . . 571

Table 289. Configurations for starting normal conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 577

Table 290. ADC sampling and conversion timing at 5 V / 3.3 V for ADC0 . . . . . . . . . . . . . . . . . . . . . 582

Table 291. Max/Min ADC_clk frequency and related configuration settings at 5 V / 3.3 V for ADC0 . 583

Table 292. Values of WDGxH and WDGxL fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 584

Table 293. Example for Analog watchdog operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 585

Table 294. ADC digital registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 587

Table 295. MCR field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 589

Table 296. MSR field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 590

Table 297. ISR field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 592

Table 298. IMR field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 592

Table 299. WTISR field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 593

Table 300. WTIMR field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 594

Table 301. DMAE field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 595

Table 302. DMARx field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 596

Table 303. TRCx field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 597

Table 304. THRHLRx field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 598

Table 305. CTR field descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 599

Table 306. NCMR field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 600

Table 307. JCMR field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 600

Table 308. PDEDR field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 601

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Table 309. CDR field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 602

Table 310. ADC commands translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 611

Table 311. CTU interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 616

Table 312. CTU memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 617

Table 313. TGS registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 620

Table 314. SU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 620

Table 315. CTU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 620

Table 316. FIFO registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 621

Table 317. TGSISR field descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 622

Table 318. TGSCR field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 624

Table 319. TxCR field descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 625

Table 320. TGSCCR field format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 625

Table 321. TGSCRR field descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 625

Table 322. CLCR1 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 626

Table 323. CLCR2 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 626

Table 324. THCR1 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 627

Table 325. THCR2 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 629

Table 326. CLRx (CMS = 0) field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 631

Table 327. CLRx (CMS = 1) field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 632

Table 328. FDCR field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 632

Table 329. FCR field descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 633

Table 330. FTH field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 634

Table 331. FST field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 635

Table 332. FRx field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 637

Table 333. FLx field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 637

Table 334. CTUEFR field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 638

Table 335. CTUIFR field descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 639

Table 336. CTUIR field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 640

Table 337. COTR field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 641

Table 338. CTUCR field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 641

Table 339. CTUDF field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 642

Table 340. CTUPCR field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 642

Table 341. Modes when PWM operation is restricted . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 644

Table 342. FlexPWM memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 648

Table 343. CTRL2 field descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 652

Table 344. CTRL1 field descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 654

Table 345. PWM reload frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 655

Table 346. PWM prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 656

Table 347. OCTRL field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 659

Table 348. STS field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 661

Table 349. INTEN field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 662

Table 350. DMAEN field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 662

Table 351. TCTRL field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 663

Table 352. DISMAP field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 664

Table 353. OUTEN field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 666

Table 354. MASK field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 666

Table 355. SWCOUT field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 667

Table 356. DTSRCSEL field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 669

Table 357. MCTRL field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 671

Table 358. FCTRL field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 672

Table 359. FSTS field descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 673

Table 360. FFILT field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 673

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Table 361. Fault mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 696

Table 362. Interrupt summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 701

Table 363. DMA summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 702

Table 364. eTimer memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 707

Table 365. COMP1 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 711

Table 366. COMP2 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 711

Table 367. CAPT1 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 712

Table 368. CAPT2 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 712

Table 369. LOAD field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 713

Table 370. HOLD field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 713

Table 371. CNTR field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 714

Table 372. CTRL1 field descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 714

Table 373. Count source values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 715

Table 374. CTRL2 field descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 716

Table 375. CTRL3 field descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 719

Table 376. STS field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 720

Table 377. INTDMA field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 721

Table 378. CMPLD1 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 722

Table 379. CMPLD2 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 723

Table 380. CCCTRL field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 723

Table 381. FILT field descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 725

Table 382. WDTOL, WDTOH field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 726

Table 383. ENBL field descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 727

Table 384. DREQn field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 728

Table 385. Interrupt summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 736

Table 386. DMA summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 736

Table 387. Register protection memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 739

Table 388. SLBRn field descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 740

Table 389. Soft Lock Bits vs. Protected Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 741

Table 390. GCR field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 741

Table 391. SWT memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 747

Table 392. SWT_CR field descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 747

Table 393. SWT_IR field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 749

Table 394. SWT_TO field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 750

Table 395. SWT_WN field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 750

Table 396. SWT_SR field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 751

Table 397. SWT_CO field descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 752

Table 398. SWT_SR field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 752

Table 399. FCU memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 758

Table 400. Register summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 758

Table 401. FCU_MCR field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 761

Table 402. FCU_FFR field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 762

Table 403. Hardware/software fault description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 762

Table 404. FCU_FFFR field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 764

Table 405. FCU_FFGR field description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 764

Table 406. FCU_FER field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 765

Table 407. FCU_TR field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 766

Table 408. FCU_TER field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 767

Table 409. FCU_MSR field descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 768

Table 410. FCU_MCSR field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 769

Table 411. FCU_FMCSR field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

770

Table 412. Dual-rail coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 773

Doc ID 16912 Rev 5 31/936

List of tables RM0046

Table 413. Bi-stable coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 775

Table 414. WKPU memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 776

Table 415. NSR field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 777

Table 416. NCR field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 778

Table 417. PIT memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 782

Table 418. PITMCR field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 783

Table 419. LDVALn field descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 784

Table 420. CVALn field descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 785

Table 421. TCTRLn field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 786

Table 422. TFLGn field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 787

Table 423. STM memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 790

Table 424. STM_CR field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 792

Table 425. STM_CNT field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 792

Table 426. STM_CCRn field descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 793

Table 427. STM_CIRn field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 794

Table 428. STM_CMPn field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 794

Table 429. CRC memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 799

Table 430. CRC_CFG field descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 800

Table 431. CRC_INP field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 801

Table 432. CRC_CSTAT field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 802

Table 433. CRC_OUTP field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 803

Table 434. BAM memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 806

Table 435. Hardware configuration to select boot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 808

Table 436. SPC560P40/34 boot pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 808

Table 437. RCHW field descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 809

Table 438. Flash boot sector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 810

Table 439. Fields of SSCM STATUS register used by BAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 813

Table 440. Serial boot mode without autobaud—baud rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 813

Table 441. UART boot mode download protocol (autobaud disabled) . . . . . . . . . . . . . . . . . . . . . . . . 818

Table 442. FlexCAN boot mode download protocol (autobaud disabled) . . . . . . . . . . . . . . . . . . . . . 819

Table 443. System clock frequency related to external clock frequency . . . . . . . . . . . . . . . . . . . . . . 820

Table 444. Maximum and minimum recommended baud rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 824

Table 445. Prescaler/divider and time base values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 828

Table 446. FlexCAN standard compliant bit timing segment settings. . . . . . . . . . . . . . . . . . . . . . . . . 829

Table 447. Lookup table for FlexCAN bit timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 829

Table 448. PRESDIV + 1 = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 829

Table 449. PRESDIV + 1 > 1 (YY = PRESDIV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 830

Table 450. Examples of legal and illegal passwords . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 832

Table 451. Censorship configuration and truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 833

Table 452. VREG_CTL field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 838

Table 453. VREG_STATUS field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 839

Table 454. JTAG signal properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 843

Table 455. Device identification register field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 845

Table 456. JTAG instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 848

Table 457. e200z0 OnCE register addressing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 852

Table 458. DAC events and Resultant Updates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 864

Table 459. DBCR0 Bit Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 870

Table 460. DBCR1 Bit Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 873

Table 461. DBCR2 Bit Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 875

Table 462. DBCR4 Bit Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 879

Table 463. DBSR Bit Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 881

Table 464. DBERC0 Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 884

32/936 Doc ID 16912 Rev 5

RM0046 List of tables

Table 465. DBERC0 Resource Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 886

Table 466. JTAG/OnCE Primary Interface Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 891

Table 467. OnCE Status Register Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 895

Table 468. OnCE Command Register Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 896

Table 469. e200z0h OnCE Register Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 897

Table 470. OnCE Control Register Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 899

Table 471. OnCE Register Access Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 902

Table 472. Watchpoint Output Signal Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 910

Table 473. JTAGC Instruction opcodes to enable Nexus clients . . . . . . . . . . . . . . . . . . . . . . . . . . . . 913

Table 474. Nexus client JTAG instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 913

Table 475. Registers under protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 914

Table 476. Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 925

Doc ID 16912 Rev 5 33/936

List of figures RM0046

List of figures

Figure 1. Electric power steering application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Figure 2. Airbag application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Figure 3. Block diagram (SPC560P40 full-featured configuration) . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Figure 4. 100-pin LQFP pinout – Full featured configuration (top view) . . . . . . . . . . . . . . . . . . . . . . 72

Figure 5. 100-pin LQFP pinout – Airbag configuration (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Figure 6. 64-pin LQFP pinout – Full featured configuration (top view) . . . . . . . . . . . . . . . . . . . . . . . 74

Figure 7. 64-pin LQFP pinout – Airbag configuration (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Figure 8. CTU / ADC / FlexPWM / eTimer connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Figure 9. SPC560P40/34 system clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Figure 10. SPC560P40/34 system clock distribution Part A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Figure 11. SPC560P40/34 system clock distribution Part B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Figure 12. RC Control register (RC_CTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Figure 13. Crystal Oscillator Control register (OSC_CTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Figure 14. FMPLL block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Figure 15. Control Register (CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Figure 16. Modulation Register (MR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Figure 17. Progressive clock switching scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Figure 18. Frequency modulation depth spreads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Figure 19. SPC560P40/34CMU. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Figure 20. Control Status Register (CMU_0_CSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

Figure 21. Frequency Display Register (CMU_0_FDR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Figure 22. High Frequency Reference register FMPLL_0 (CMU_0_HFREFR_A). . . . . . . . . . . . . . . 113

Figure 23. Low Frequency Reference Register FMPLL_0 (CMU_0_LFREFR_A). . . . . . . . . . . . . . . 114

Figure 24. Interrupt Status Register (CMU_0_ISR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

Figure 25. Measurement Duration Register (CMU_0_MDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Figure 26. MC_CGM Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Figure 27. Output Clock Enable Register (CGM_OC_EN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

Figure 28. Output Clock Division Select Register (CGM_OCDS_SC). . . . . . . . . . . . . . . . . . . . . . . . 124

Figure 29. System Clock Select Status Register (CGM_SC_SS) . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

Figure 30. System Clock Divider Configuration Register (CGM_SC_DC0) . . . . . . . . . . . . . . . . . . . . 126

Figure 31. Auxiliary Clock 0 Select Control Register (CGM_AC0_SC) . . . . . . . . . . . . . . . . . . . . . . . 127

Figure 32. Auxiliary Clock 0 Divider Configuration Register (CGM_AC0_DC0) . . . . . . . . . . . . . . . . 128

Figure 33. Auxiliary Clock 1 Select Control Register (CGM_AC1_SC) . . . . . . . . . . . . . . . . . . . . . . . 128

Figure 34. Auxiliary Clock 1 Divider Configuration Register (CGM_AC1_DC0) . . . . . . . . . . . . . . . . 129

Figure 35. Auxiliary Clock 2 Select Control Register (CGM_AC2_SC) . . . . . . . . . . . . . . . . . . . . . . . 130

Figure 36. Auxiliary Clock 2 Divider Configuration Register (CGM_AC2_DC0) . . . . . . . . . . . . . . . . 131

Figure 37. MC_CGM System Clock Generation Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

Figure 38. MC_CGM Auxiliary Clock 0 Generation Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

Figure 39. MC_CGM Auxiliary Clock 1 Generation Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

Figure 40. MC_CGM Auxiliary Clock 2 Generation Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

Figure 41. MC_CGM Output Clock Multiplexer and PAD[22] Generation . . . . . . . . . . . . . . . . . . . . . 135

Figure 42. MC_ME Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

Figure 43. Global Status Register (ME_GS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

Figure 44. Mode Control Register (ME_MCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

Figure 45. Mode Enable Register (ME_ME) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

Figure 46. Interrupt Status Register (ME_IS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

Figure 47. Interrupt Mask Register (ME_IM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

Figure 48. Invalid Mode Transition Status Register (ME_IMTS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

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Figure 49. Debug Mode Transition Status Register (ME_DMTS) . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

Figure 50. RESET Mode Configuration Register (ME_RESET_MC). . . . . . . . . . . . . . . . . . . . . . . . . 158

Figure 51. TEST Mode Configuration Register (ME_TEST_MC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

Figure 52. SAFE Mode Configuration Register (ME_SAFE_MC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

Figure 53. DRUN Mode Configuration Register (ME_DRUN_MC) . . . . . . . . . . . . . . . . . . . . . . . . . . 160

Figure 54. RUN0…3 Mode Configuration Registers (ME_RUN0…3_MC) . . . . . . . . . . . . . . . . . . . . 161

Figure 55. HALT0 Mode Configuration Register (ME_HALT0_MC) . . . . . . . . . . . . . . . . . . . . . . . . . 161

Figure 56. STOP0 Mode Configuration Register (ME_STOP0_MC) . . . . . . . . . . . . . . . . . . . . . . . . . 162

Figure 57. Peripheral Status Register 0 (ME_PS0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

Figure 58. Peripheral Status Register 1 (ME_PS1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

Figure 59. Peripheral Status Register 2 (ME_PS2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

Figure 60. Run Peripheral Configuration Registers (ME_RUN_PC0…7) . . . . . . . . . . . . . . . . . . . . . 166

Figure 61. Low-Power Peripheral Configuration Registers (ME_LP_PC0…7) . . . . . . . . . . . . . . . . . 167

Figure 62. Peripheral Control Registers (ME_PCTL0…143) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

Figure 63. MC_ME Mode Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

Figure 64. MC_ME Transition Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

Figure 65. MC_ME Application Example Flow Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

Figure 66. MC_PCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

Figure 67. Power Domain Status Register (PCU_PSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186

Figure 68. MC_RGM Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188

Figure 69. Functional Event Status Register (RGM_FES) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

Figure 70. Destructive Event Status Register (RGM_DES). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194

Figure 71. Functional Event Reset Disable Register (RGM_FERD) . . . . . . . . . . . . . . . . . . . . . . . . . 195

Figure 72. Destructive Event Reset Disable Register (RGM_DERD) . . . . . . . . . . . . . . . . . . . . . . . . 197

Figure 73. Functional Event Alternate Request Register (RGM_FEAR) . . . . . . . . . . . . . . . . . . . . . . 198

Figure 74. Functional Event Short Sequence Register (RGM_FESS). . . . . . . . . . . . . . . . . . . . . . . . 199

Figure 75. Functional Bidirectional Reset Enable Register (RGM_FBRE) . . . . . . . . . . . . . . . . . . . . 200

Figure 76. MC_RGM State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203

Figure 77. INTC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210

Figure 78. INTC Module Configuration Register (INTC_MCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213

Figure 79. INTC Current Priority Register (INTC_CPR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213

Figure 80. INTC Interrupt Acknowledge Register (INTC_IACKR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 215

Figure 81. INTC End-of-Interrupt Register (INTC_EOIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216

Figure 82. INTC Software Set/Clear Interrupt Register 0–3 (INTC_SSCIR[0:3]). . . . . . . . . . . . . . . . 216

Figure 83. INTC Software Set/Clear Interrupt Register 4–7 (INTC_SSCIR[4:7]). . . . . . . . . . . . . . . . 217

Figure 84. INTC Priority Select Register 0–3 (INTC_PSR[0:3]). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218

Figure 85. INTC Priority Select Register 220–221 (INTC_PSR[220:221]). . . . . . . . . . . . . . . . . . . . . 218

Figure 86. Software vector mode handshaking timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231

Figure 87. Hardware vector mode handshaking timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232

Figure 88. SSCM block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240

Figure 89. Key to register fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241

Figure 90. Status (STATUS) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242

Figure 91. System memory configuration (MEMCONFIG) register . . . . . . . . . . . . . . . . . . . . . . . . . . 243

Figure 92. Error Configuration (ERROR) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244

Figure 93. Debug Status Port (DEBUGPORT) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245

Figure 94. Password Comparison Register High Word (PWCMPH) register. . . . . . . . . . . . . . . . . . . 246

Figure 95. Password Comparison Register Low Word (PWCMPL) register . . . . . . . . . . . . . . . . . . . 246

Figure 96. System Integration Unit Lite block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249

Figure 97. Key to register fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252

Figure 98. MCU ID Register #1 (MIDR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252

Figure 99. MCU ID Register #2 (MIDR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254

Figure 100. Interrupt Status Flag Register (ISR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255

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Figure 101. Interrupt Request Enable Register (IRER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255

Figure 102. Interrupt Rising-Edge Event Enable Register (IREER). . . . . . . . . . . . . . . . . . . . . . . . . . . 256

Figure 103. Interrupt Falling-Edge Event Enable Register (IFEER). . . . . . . . . . . . . . . . . . . . . . . . . . . 256

Figure 104. Interrupt Filter Enable Register (IFER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257

Figure 105. Pad Configuration Registers 0–71 (PCR[0:71]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257

Figure 106. Pad Selection for Multiplexed Inputs registers (PSMI[0_3:32_35]). . . . . . . . . . . . . . . . . . 260

Figure 107. Port GPIO Pad Data Output registers 0_3–68_71 (GPDO[0_3:68_71]). . . . . . . . . . . . . . 262

Figure 108. GPIO Pad Data Input registers 0_3–68_71 (GPDI[0_3:68_71]) . . . . . . . . . . . . . . . . . . . . 262

Figure 109. Parallel GPIO Pad Data Out register 0–3(PGPDO[0:3]). . . . . . . . . . . . . . . . . . . . . . . . . . 263

Figure 110. Parallel GPIO Pad Data In register 0–3 (PGPDI[0:3]) . . . . . . . . . . . . . . . . . . . . . . . . . . . 264

Figure 111. Masked Parallel GPIO Pad Data Out register 0–6 (MPGPDO[0:6]) . . . . . . . . . . . . . . . . . 264

Figure 112. Interrupt Filter Maximum Counter registers 0–24 (IFMC[0:24]) . . . . . . . . . . . . . . . . . . . . 265

Figure 113. Interrupt Filter Clock Prescaler Register (IFCPR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266

Figure 114. Data port example arrangement showing configuration for different port width accesses 267

Figure 115. External interrupt pad diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268

Figure 116. e200z0 block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272

Figure 117. e200z0h block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273

Figure 118. e200z0 Supervisor mode programmer’s model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276

Figure 119. e200z0h Supervisor mode programmer’s model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277

Figure 120. e200 User mode program model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278

Figure 121. PBRIDGE interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279

Figure 122. XBAR block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281

Figure 123. Processor core type (PCT) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288

Figure 124. Revision (REV) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288

Figure 125. Platform XBAR Master Configuration (PLAMC) register. . . . . . . . . . . . . . . . . . . . . . . . . . 289

Figure 126. Platform XBAR Slave Configuration (PLASC) register . . . . . . . . . . . . . . . . . . . . . . . . . . . 289

Figure 127. IPS Module Configuration (IMC) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290

Figure 128. Miscellaneous Reset Status Register (MRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291

Figure 129. Miscellaneous Interrupt Register (MIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291

Figure 130. Miscellaneous User-Defined Control register (MUDCR). . . . . . . . . . . . . . . . . . . . . . . . . . 292

Figure 131. ECC Configuration register (ECR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293

Figure 132. ECC Status register (ESR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295

Figure 133. ECC Error Generation register (EEGR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296

Figure 134. Flash ECC Address register (FEAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299

Figure 135. Flash ECC Master Number Register (FEMR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299

Figure 136. Flash ECC Attributes (FEAT) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300

Figure 137. Flash ECC Data register (FEDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301

Figure 138. RAM ECC Address register (REAR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301

Figure 139. RAM ECC Syndrome Register (RESR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302

Figure 140. RAM ECC Master Number register (REMR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304

Figure 141. RAM ECC Attributes (REAT) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305

Figure 142. Platform RAM ECC Data register (PREDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306

Figure 143. Spp_Ips_Reg_Protection block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307

Figure 144. SPC560P40/34 Flash memory architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311

Figure 145. 1-cycle access, no buffering, no prefetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324

Figure 146. 3-cycle access, no prefetch, buffering disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325

Figure 147. 3-cycle access, no prefetch, buffering enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326

Figure 148. 3-cycle access, prefetch and buffering enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327

Figure 149. 3-cycle access, stall-and-retry with BKn_RWWC = 11x . . . . . . . . . . . . . . . . . . . . . . . . . . 328

Figure 150. 3-cycle access, terminate-and-retry with BKn_RWWC = 10x. . . . . . . . . . . . . . . . . . . . . . 329

Figure 151. Data Flash module structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331

Figure 152. Code Flash module structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332

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Figure 153. Module Configuration Register (MCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342

Figure 154. Low/Mid Address Space Block Locking register (LML). . . . . . . . . . . . . . . . . . . . . . . . . . . 347

Figure 155. Non-Volatile Low/Mid Address Space Block Locking register (NVLML) . . . . . . . . . . . . . . 347

Figure 156. Secondary Low/mid address space block Locking reg (SLL) . . . . . . . . . . . . . . . . . . . . . . 349

Figure 157. Non-Volatile Secondary Low/Mid Address Space Block Locking register (NVSLL) . . . . . 349

Figure 158. Low/Mid Address Space Block Select register (LMS). . . . . . . . . . . . . . . . . . . . . . . . . . . . 351

Figure 159. Address Register (ADR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352

Figure 160. Platform Flash Configuration Register 0 (PFCR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354

Figure 161. Platform Flash Configuration Register 1 (PFCR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357

Figure 162. Platform Flash Access Protection Register (PFAPR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359

Figure 163. User Test 0 register (UT0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360

Figure 164. User Test 1 register (UT1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362

Figure 165. User Test 2 register (UT2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363

Figure 166. User Multiple Input Signature Register 0 (UMISR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364

Figure 167. User Multiple Input Signature Register 1 (UMISR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364

Figure 168. User Multiple Input Signature Register 2 (UMISR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365

Figure 169. User Multiple Input Signature Register 3 (UMISR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366

Figure 170. User Multiple Input Signature Register 4 (UMISR4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366

Figure 171. Non-Volatile private Censorship Password 0 register (NVPWD0) . . . . . . . . . . . . . . . . . . 367

Figure 172. Non-Volatile Private Censorship Password 1 register (NVPWD1) . . . . . . . . . . . . . . . . . . 368

Figure 173. Non-Volatile System Censoring Information 0 register (NVSCI0). . . . . . . . . . . . . . . . . . . 368

Figure 174. Non-Volatile System Censoring Information 1 register (NVSCI1). . . . . . . . . . . . . . . . . . . 369

Figure 175. Non-Volatile User Options register (NVUSRO). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370

Figure 176. eDMA block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382

Figure 177. eDMA Control Register (EDMA_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386

Figure 178. eDMA Error Status Register (EDMA_ESR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388

Figure 179. eDMA Enable Request Low Register (EDMA_ERQRL) . . . . . . . . . . . . . . . . . . . . . . . . . . 390

Figure 180. eDMA Enable Error Interrupt Low Register (EDMA_EEIRL) . . . . . . . . . . . . . . . . . . . . . . 391

Figure 181. eDMA Set Enable Request Register (EDMA_SERQR) . . . . . . . . . . . . . . . . . . . . . . . . . . 391

Figure 182. eDMA Clear Enable Request Register (EDMA_CERQR). . . . . . . . . . . . . . . . . . . . . . . . . 392

Figure 183. eDMA Set Enable Error Interrupt Register (EDMA_SEEIR) . . . . . . . . . . . . . . . . . . . . . . . 392

Figure 184. eDMA Set Enable Error Interrupt Register (EDMA_SEEIR) . . . . . . . . . . . . . . . . . . . . . . . 393

Figure 185. eDMA Clear Interrupt Request (EDMA_CIRQR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394

Figure 186. eDMA Clear Error Register (EDMA_CERR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394

Figure 187. eDMA Set START Bit Register (EDMA_SSBR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395

Figure 188. eDMA Clear DONE Status Bit Register (EDMA_CDSBR) . . . . . . . . . . . . . . . . . . . . . . . . 395

Figure 189. eDMA Interrupt Request Low Register (EDMA_IRQRL) . . . . . . . . . . . . . . . . . . . . . . . . . 396

Figure 190. eDMA Error Low Register (EDMA_ERL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397

Figure 191. EDMA Hardware Request Status Register Low (EDMA_HRSL) . . . . . . . . . . . . . . . . . . . 398

Figure 192. eDMA Channel n Priority Register (EDMA_CPRn). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399

Figure 193. TCD structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401

Figure 194. eDMA operation, part 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408

Figure 195. eDMA operation, part 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409

Figure 196. eDMA operation, part 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410

Figure 197. Example of multiple loop iterations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415

Figure 198. Memory array terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416

Figure 199. DMA Mux block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424

Figure 200. Channel Configuration Registers (CHCONFIG#n) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427

Figure 201. DMA mux triggered channels diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430

Figure 202. DMA mux channel triggering: normal operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430

Figure 203. DMA mux channel triggering: ignored trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431

Figure 204. DMA mux channel 4–15 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432

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Figure 205. DSPI block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437

Figure 206. DSPI with queues and eDMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 438

Figure 207. DSPI Module Configuration Register (DSPIx_MCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 444

Figure 208. DSPI Transfer Count Register (DSPIx_TCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447

Figure 209. DSPI Clock and Transfer Attributes Registers 0–7 (DSPIx_CTARn) . . . . . . . . . . . . . . . . 448

Figure 210. DSPI Status Register (DSPIx_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453

Figure 211. DSPI DMA / Interrupt Request Select and Enable Register (DSPIx_RSER) . . . . . . . . . . 455

Figure 212. DSPI PUSH TX FIFO Register (DSPIx_PUSHR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457

Figure 213. DSPI POP RX FIFO Register (DSPIx_POPR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459

Figure 214. DSPI Transmit FIFO Register 0–4 (DSPIx_TXFRn). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459

Figure 215. DSPI Receive FIFO Registers 0–4 (DSPIx_RXFRn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460

Figure 216. SPI serial protocol overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461

Figure 217. DSPI start and stop state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463

Figure 218. Communications clock prescalers and scalers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 466

Figure 219. Peripheral Chip Select strobe timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 468

Figure 220. DSPI transfer timing diagram (MTFE = 0, CPHA = 0, FMSZ = 8) . . . . . . . . . . . . . . . . . . 470

Figure 221. DSPI transfer timing diagram (MTFE = 0, CPHA = 1, FMSZ = 8) . . . . . . . . . . . . . . . . . . 471

Figure 222. DSPI modified transfer format (MTFE = 1, CPHA = 0, f
Figure 223. DSPI modified transfer format (MTFE = 1, CPHA = 1, f

SCK=fSYS

SCK=fSYS

/ 4) . . . . . . . . . . . . . . 473

/ 4) . . . . . . . . . . . . . . 474

Figure 224. Example of non-continuous format (CPHA = 1, CONT = 0) . . . . . . . . . . . . . . . . . . . . . . . 474

Figure 225. Example of continuous transfer (CPHA = 1, CONT = 1). . . . . . . . . . . . . . . . . . . . . . . . . . 475

Figure 226. Polarity switching between frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476

Figure 227. Continuous SCK timing diagram (CONT = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477

Figure 228. Continuous SCK timing diagram (CONT = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477

Figure 229. TX FIFO pointers and counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483

Figure 230. LIN topology network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 487

Figure 231. LINFlex block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 487

Figure 232. LINFlex operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489

Figure 233. LINFlex in loop back mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 490

Figure 234. LINFlex in self test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491

Figure 235. LIN control register 1 (LINCR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492

Figure 236. LIN interrupt enable register (LINIER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495

Figure 237. LIN status register (LINSR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 497

Figure 238. LIN error status register (LINESR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500

Figure 239. UART mode control register (UARTCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 501

Figure 240. UART mode status register (UARTSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503

Figure 241. LIN timeout control status register (LINTCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505

Figure 242. LIN output compare register (LINOCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506

Figure 243. LIN timeout control register (LINTOCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506

Figure 244. LIN fractional baud rate register (LINFBRR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 507

Figure 245. LIN integer baud rate register (LINIBRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 508

Figure 246. LIN checksum field register (LINCFR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509

Figure 247. LIN control register 2 (LINCR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509

Figure 248. Buffer identifier register (BIDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511

Figure 249. Buffer data register LSB (BDRL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512

Figure 250. Buffer data register MSB (BDRM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512

Figure 251. Identifier filter enable register (IFER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513

Figure 252. Identifier filter match index (IFMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 514

Figure 253. Identifier filter mode register (IFMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 514

Figure 254. Identifier filter control register (IFCR2n) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 516

Figure 255. Identifier filter control register (IFCR2n + 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 517

Figure 256. UART mode 8-bit data frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 518

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Figure 257. UART mode 9-bit data frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 518

Figure 258. Filter configuration—register organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 525

Figure 259. Identifier match index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 526

Figure 260. LIN synch field measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 527

Figure 261. Header and response timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 529

Figure 262. FlexCAN block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 531

Figure 263. Message buffer structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537

Figure 264. Rx FIFO structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 541

Figure 265. Module Configuration Register (MCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 543

Figure 266. Control Register (CTRL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 546

Figure 267. Free Running Timer (TIMER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 550

Figure 268. Rx Global Mask register (RXGMASK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 550

Figure 269. Rx Buffer 14 Mask register (RX14MASK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 551

Figure 270. Rx Buffer 15 Mask register (RX15MASK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 552

Figure 271. Error Counter Register (ECR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 553

Figure 272. Error and Status Register (ESR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 554

Figure 273. Interrupt Masks 1 Register (IMASK1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 556

Figure 274. Interrupt Flags 1 Register (IFLAG1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 557

Figure 275. Rx Individual Mask Registers (RXIMR0–RXIMR31) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 558

Figure 276. CAN engine clocking scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 568

Figure 277. Segments within the bit time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 569

Figure 278. Arbitration, match, and move time windows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 570

Figure 279. ADC implementation diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 576

Figure 280. Normal conversion flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 578

Figure 281. Injected sample/conversion sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 579

Figure 282. Prescaler simplified block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 581

Figure 283. Sampling and conversion timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 582

Figure 284. Guarded area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 584

Figure 285. Main Configuration Register (MCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 588

Figure 286. Main Status Register (MSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 590

Figure 287. Interrupt Status Register (ISR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 591

Figure 288. Interrupt Mask Register (IMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 592

Figure 289. Channel Interrupt Mask Register 0 (CIMR0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 593

Figure 290. Watchdog Threshold Interrupt Status Register (WTISR) . . . . . . . . . . . . . . . . . . . . . . . . . 593

Figure 291. Watchdog Threshold Interrupt Mask Register (WTIMR). . . . . . . . . . . . . . . . . . . . . . . . . . 594

Figure 292. DMA Enable (DMAE) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 595

Figure 293. DMA Channel Select Register 0 (DMAR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 596

Figure 294. Threshold Control Register (TRCx, x = [0..3]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 597

Figure 295. Threshold Register (THRHLR[0:3]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 598

Figure 296. Conversion Timing Registers CTR[0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 599

Figure 297. Normal Conversion Mask Register 0 (NCMR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 600

Figure 298. Injected Conversion Mask Register 0 (JCMR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 600

Figure 299. Power-Down Exit Delay Register (PDEDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 601

Figure 300. Channel Data Registers (CDR[0..26]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 602

Figure 301. Cross triggering unit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 604

Figure 302. TGS in triggered mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 605

Figure 303. Example timing for TGS in triggered mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 606

Figure 304. TGS in sequential mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 607

Figure 305. Example timing for TGS in sequential mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 607

Figure 306. TGS counter cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 608

Figure 307. Scheduler subunit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 610

Figure 308. Reload error scenario . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 614

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Figure 309. Trigger Generator Sub-unit Input Selection Register (TGSISR) . . . . . . . . . . . . . . . . . . . . 621

Figure 310. Trigger Generator Sub-unit Control Register (TGSCR) . . . . . . . . . . . . . . . . . . . . . . . . . . 624

Figure 311. Trigger x Compare Register (TxCR, x = 0...7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 624

Figure 312. TGS Counter Compare Register (TGSCCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 625

Figure 313. TGS Counter Reload Register (TGSCRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 625

Figure 314. Commands list control register 1 (CLCR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 626

Figure 315. Commands list control register 2 (CLCR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 626

Figure 316. Trigger handler control register 1 (THCR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 627

Figure 317. Trigger handler control register 2 (THCR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 629

Figure 318. Commands list register x (x = 1,...,24) (CMS = 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 631

Figure 319. Commands list register x (x = 1,...,24) (CMS = 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 631

Figure 320. FIFO DMA control register (FDCR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 632

Figure 321. FIFO control register (FCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 633

Figure 322. FIFO threshold register (FTH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 634

Figure 323. FIFO status register (FST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 635

Figure 324. FIFO Right aligned data x (x = 0,...,3) (FRx). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 636

Figure 325. FIFO signed Left aligned data x (x = 0,...,3) (FLx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 637

Figure 326. Cross triggering unit error flag register (CTUEFR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 637

Figure 327. Cross triggering unit interrupt flag register (CTUIFR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 638

Figure 328. Cross triggering unit interrupt/DMA register (CTUIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 639

Figure 329. Control ON time register (COTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 640

Figure 330. Cross triggering unit control register (CTUCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 641

Figure 331. Cross triggering unit digital filter (CTUDF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 642

Figure 332. Cross triggering unit power control register (CTUPCR) . . . . . . . . . . . . . . . . . . . . . . . . . . 642

Figure 333. PWM block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 645

Figure 334. PWM submodule block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 646

Figure 335. Counter Register (CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 651

Figure 336. Initial Count Register (INIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 651

Figure 337. Control 2 Register (CTRL2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 652

Figure 338. Control 1 Register (CTRL1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 654

Figure 339. Value Register 0 (VAL0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 656

Figure 340. Value Register 1 (VAL1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 657

Figure 341. Value register 2 (VAL2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 657

Figure 342. Value register 3 (VAL3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 658

Figure 343. Value register 4 (VAL4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 658

Figure 344. Value register 5 (VAL5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 659

Figure 345. Output Control register (OCTRL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 659

Figure 346. Status register (STS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 660

Figure 347. Interrupt Enable register (INTEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 661

Figure 348. DMA Enable register (DMAEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 662

Figure 349. Output Trigger Control register (TCTRL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 663

Figure 350. Fault Disable Mapping register (DISMAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 664

Figure 351. Deadtime Count Register 0 (DTCNT0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 665

Figure 352. Deadtime Count register 1 (DTCNT1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 665

Figure 353. Output Enable register (OUTEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 665

Figure 354. Mask register (MASK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 666

Figure 355. Software Controlled Output Register (SWCOUT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 667

Figure 356. Deadtime Source Select Register (DTSRCSEL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 668

Figure 357. Master Control Register (MCTRL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 670

Figure 358. Fault Control Register (FCTRL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 671

Figure 359. Fault Status Register (FSTS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 672

Figure 360. Fault Filter Register (FFILT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 673

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Figure 361. Center-aligned example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 675

Figure 362. Edge-aligned example (INIT = VAL2 = VAL4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 676

Figure 363. Phase-shifted outputs example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 677

Figure 364. Phase-shifted PWMs applied to a transformer primary . . . . . . . . . . . . . . . . . . . . . . . . . . 678

Figure 365. Double switching output example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 679

Figure 366. Multiple output trigger generation in hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 680

Figure 367. Multiple output triggers over several PWM cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 681

Figure 368. Sensorless BLDC commutation using the force out function . . . . . . . . . . . . . . . . . . . . . . 682

Figure 369. Clocking block diagram for each PWM submodule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 683

Figure 370. Register reload logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 684

Figure 371. Submodule timer synchronization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 684

Figure 372. PWM generation hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 686

Figure 373. Force out logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 688

Figure 374. Complementary channel pair . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 689

Figure 375. Typical 3-phase AC motor drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 689

Figure 376. Deadtime insertion and fine control logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 690

Figure 377. Deadtime insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 691

Figure 378. Deadtime distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 692

Figure 379. Current-status sense scheme for deadtime correction . . . . . . . . . . . . . . . . . . . . . . . . . . . 693

Figure 380. Output voltage waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 694

Figure 381. Output logic section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 695

Figure 382. Fault decoder for PWMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 696

Figure 383. Automatic fault clearing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 697

Figure 384. Manual fault clearing (FSAFE = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 698

Figure 385. Manual fault clearing (FSAFE = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 698

Figure 386. Full cycle reload frequency change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 699

Figure 387. Half cycle reload frequency change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 699

Figure 388. Full and half cycle reload frequency change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 700

Figure 389. PWMF reload interrupt request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 700

Figure 390. eTimer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 705

Figure 391. eTimer channel block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 706

Figure 392. Compare register 1 (COMP1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 710

Figure 393. Compare register 2 (COMP2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 711

Figure 394. Capture register 1 (CAPT1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 711

Figure 395. Capture register 2 (CAPT2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 712

Figure 396. Load register (LOAD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 712

Figure 397. Hold register (HOLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 713

Figure 398. Counter register (CNTR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 713

Figure 399. Control register 1 (CTRL1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 714

Figure 400. Control register 2 (CTRL2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 716

Figure 401. Control register 3 (CTRL3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 718

Figure 402. Status register (STS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 719

Figure 403. Interrupt and DMA enable register (INTDMA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 721

Figure 404. Comparator Load 1 (CMPLD1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 722

Figure 405. Comparator Load 2 (CMPLD2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 722

Figure 406. Compare and Capture Control register (CCCTRL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 723

Figure 407. Input Filter register (FILT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 725

Figure 408. Watchdog Time-out Low Word register (WDTOL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 726

Figure 409. Watchdog Time-Out High Word register (WDTOH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 726

Figure 410. Channel Enable register (ENBL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 726

Figure 411. DMA Request 0 Select register (DREQ0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 727

Figure 412. DMA Request 1 Select register (DREQ1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 727

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Figure 413. Quadrature incremental position encoder. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 730

Figure 414. Triggered Count mode (length = 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 731

Figure 415. One-Shot mode (length = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 731

Figure 416. Pulse Output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 732

Figure 417. Variable PWM waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 733

Figure 418. Register protection module block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 737

Figure 419. Register protection memory diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 738

Figure 420. Soft Lock Bit Register (SLBRn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 740

Figure 421. Global Configuration Register (GCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 741

Figure 422. Change lock settings directly via area #4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 742

Figure 423. Change lock settings for 16-bit protected addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . 743

Figure 424. Change lock settings for 32-bit protected addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . 743

Figure 425. Change lock settings for mixed protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 744

Figure 426. Enable locking via mirror module space (area #3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 744

Figure 427. Enable locking for protected and unprotected addresses. . . . . . . . . . . . . . . . . . . . . . . . . 744

Figure 428. SWT Control Register (SWT_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 747

Figure 429. SWT Interrupt Register (SWT_IR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 749

Figure 430. SWT Time-Out register (SWT_TO). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 749

Figure 431. SWT Window register (SWT_WN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 750

Figure 432. SWT Service Register (SWT_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 751

Figure 433. SWT Counter Output register (SWT_CO). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 751

Figure 434. SWT Service Register (SWT_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 752

Figure 435. Fault Collection Unit (FCU) block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 755

Figure 436. FCU fault handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 756

Figure 437. Module Configuration Register (FCU_MCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 760

Figure 438. Fault Flag Register (FCU_FFR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 762

Figure 439. Frozen Fault Flag Register (FCU_FFFR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 763

Figure 440. Fake Fault Generation Register (FCU_FFGR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 764

Figure 441. Fault Enable Register (FCU_FER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 765

Figure 442. Key Register (FCU_KR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 766

Figure 443. Timeout Register (FCU_TR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 766

Figure 444. Timeout Enable Register (FCU_TER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 767

Figure 445. Module State Register (FCU_MSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 767

Figure 446. MC State Register (FCU_MCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 768

Figure 447. Frozen MC State Register (FCU_FMCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 770

Figure 448. Functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 771

Figure 449. Finite state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 772

Figure 450. Dual rail coding example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 774

Figure 451. Time switching protocol example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 774

Figure 452. Bi-stable coding example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 775

Figure 453. NMI Status Flag Register (NSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 777

Figure 454. NMI Configuration Register (NCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 778

Figure 455. NMI pad diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 779

Figure 456. PIT block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 781

Figure 457. PIT Module Control Register (PITMCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 783

Figure 458. Timer Load Value Register n (LDVALn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 784

Figure 459. Current Timer Value register n (CVALn). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 785

Figure 460. Timer Control register n (TCTRLn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 786

Figure 461. Timer Flag register n (TFLGn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 787

Figure 462. Stopping and starting a timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 788

Figure 463. Modifying running timer period . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 788

Figure 464. Dynamically setting a new load value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 788

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Figure 465. STM Control Register (STM_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 791

Figure 466. STM Count Register (STM_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 792

Figure 467. STM Channel Control Register (STM_CCRn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 793

Figure 468. STM Channel Interrupt Register (STM_CIRn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 793

Figure 469. STM Channel Compare Register (STM_CMPn). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 794

Figure 470. CRC top level diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 797

Figure 471. CRC-CCITT engine concept scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 798

Figure 472. CRC computation flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 799

Figure 473. CRC Configuration Register (CRC_CFG). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 800

Figure 474. CRC Input Register (CRC_INP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 801

Figure 475. CRC Current Status Register (CRC_CSTAT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 802

Figure 476. CRC Output Register (CRC_OUTP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 802

Figure 477. DMA-CRC Transmission Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 804

Figure 478. DMA-CRC Reception Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 805

Figure 479. Boot mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 807

Figure 480. Reset Configuration Half Word (RCHW). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 809

Figure 481. SPC560P40/34 Flash partitioning and RCHW search . . . . . . . . . . . . . . . . . . . . . . . . . . . 810

Figure 482. BAM logic flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 812

Figure 483. Password check flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 816

Figure 484. Start address, VLE bit and download size in bytes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 817

Figure 485. LINFlex bit timing in UART mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 818

Figure 486. FlexCAN bit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 819

Figure 487. BAM Autoscan code flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 822

Figure 488. Baud measurement on UART boot. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 822

Figure 489. BAM rate measurement flow during UART boot. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 823

Figure 490. Baud rate deviation between host and SPC560P40/34 . . . . . . . . . . . . . . . . . . . . . . . . . . 825

Figure 491. Bit time measure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 826

Figure 492. BAM rate measurement flow during FlexCAN boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 827

Figure 493. Censorship control in flash memory boot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 834

Figure 494. Censorship control in serial boot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 835

Figure 495. Voltage Regulator Control register (VREG_CTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 838

Figure 496. Voltage Regulator Status register (VREG_STATUS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 839

Figure 497. JTAG controller block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 841

Figure 498. 5-bit Instruction register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 844

Figure 499. Device identification register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 844

Figure 500. Shifting data through a register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 845

Figure 501. IEEE 1149.1-2001 TAP controller finite state machine. . . . . . . . . . . . . . . . . . . . . . . . . . . 847

Figure 502. e200z0 OnCE block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 851

Figure 503. OnCE Command register (OCMD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 852

Figure 504. NDI functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 855

Figure 505. e200z0h Debug Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 861

Figure 506. DVC1, DVC2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 869

Figure 507. DBCR0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 870

Figure 508. DBCR1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 872

Figure 509. DBCR2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 875

Figure 510. DBCR4 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 879

Figure 511. DBSR Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 880

Figure 512. DBERC0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 883

Figure 513. OnCE TAP Controller and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 889

Figure 514. IEEE 1149.1-2001 TAP Controller State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 890

Figure 515. e200z0h OnCE Controller and Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 894

Figure 516. OnCE Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 894

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List of figures RM0046

Figure 517. OnCE Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 896

Figure 518. OnCE Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 899

Figure 519. CPU Scan Chain Register (CPUSCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 905

Figure 520. Control State Register (CTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 906

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RM0046 Preface

Preface

Overview

The primary objective of this document is to define the functionality of the SPC560P40/34
family of microcontrollers for use by software and hardware developers. The SPC560P40/34
family is built on Power Architecture
important for today’s electrical hydraulic power steering (EHPS), electric power steering
(EPS), airbag applications, anti-lock braking systems (ABS), and motor control applications.

As with any technical documentation, it is the reader’s responsibility to be sure he or she is
using the most recent version of the documentation.

To locate any published errata or updates for this document, visit the ST Web site at
www.st.com.

Audience

This manual is intended for system software and hardware developers and applications
programmers who want to develop products with the SPC560P40/34 device. It is assumed
that the reader understands operating systems, microprocessor system design, basic
principles of software and hardware, and basic details of the Power Architecture.

®

technology and integrates technologies that are

Chapter organization and device-specific information

This document includes chapters that describe:

● The device as a whole

● The functionality of the individual modules on the device

In the latter, any device-specific information is presented in the section “Information Specific
to This Device” at the beginning of the chapter.

References

In addition to this reference manual, the following documents provide additional information
on the operation of the SPC560P40/34:

● IEEE-ISTO 5001™ - 2003 and 2010, The Nexus 5001™ Forum Standard for a Global

Embedded Processor Debug Interface

● IEEE 1149.1-2001 standard - IEEE Standard Test Access Port and Boundary-Scan

Architecture

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Introduction RM0046

1 Introduction

1.1 The SPC560P40/34 microcontroller family

The SPC560P40/34 microcontroller is built on the Power Architecture
Architecture
automotive application controllers. This device family integrates the most advanced and up­to-date motor control design features.

The safety features included in SPC560P40/34 (such us fault collection unit, safety port or
flash memory and SRAM with ECC) support the design of system applications where safety
is a requirement.

The SPC560P40/34 addresses low-end chassis applications and implements the Harvard
bus interface version of the e200z0h core.

The e200 processor family is a set of CPU cores that implement low-cost versions of the
Power Architecture Book E architecture. The e200 processors are designed for deeply
embedded control applications that require low cost solutions rather than maximum
performance. The e200z0h processor integrates an integer execution unit, branch control
unit, instruction fetch and load/store units, and a multi-ported register file capable to
sustaining three read and two write operations per clock. Most integer instructions execute
in a single clock cycle. Branch target prefetching is performed by branch unit to allow single­cycle branches in some cases. The e200z0h core is a single-issue, 32-bit Power
Architecture technology VLE only design with 32-bit general purpose registers (GPRs). All
arithmetic instructions that execute in the core operate on data in the general purpose
registers (GPRs). Instead of the base Power Architecture instruction set support, the
e200z0h core only implements the VLE (variable length encoding) APU, providing improved
code density.

based 32-bit microcontrollers represent the latest achievement in integrated

®

platform. The Power

The SPC560P40/34 has a single level of memory hierarchy consisting of 20 KB on-chip
SRAM and 320 KB (256 KB program + 64 KB data) of on-chip flash memory. Both the
SRAM and the flash memory can hold instructions and data.

The timer functions of the SPC560P40/34 are performed by the eTimer Modular Timer
System and FlexPWM. The eTimer module implements enhanced timer features (six
channels) including dedicated motor control quadrature decode functionality and DMA
support; the FlexPWM module consists of four submodules controlling a pair of PWM
channels each: three submodules may be used to control the three phases of a motor and
the additional pair to support DC-DC converter width modulation control.

Off-chip communication is performed by a suite of serial protocols including CANs,
enhanced SPIs (DSPI), and SCIs (LINFlex).

The System Integration Unit Lite (SIUL) performs several chip-wide configuration functions.
Pad configuration and general-purpose input/output (GPIO) are controlled from the SIUL.
External interrupts and reset control are also found in the SIUL. The internal multiplexer
sub-block (IOMUX) provides multiplexing of daisy chaining the DSPIs and external interrupt
signal.

As the SPC560P40/34 is built on a wider legacy of Power Architecture-based devices, when
applicable and possible, reuse or enhancement of existing IP, design and concepts is
adopted.

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RM0046 Introduction

Position Sensor

Gearbox

Sensor

Load

Position Sensor
Physical Layer

To rq u e

Relay

Relay Driver

Signal

Conditioning

Circuitry

Driver

PWM

3-phase Low Voltage Power Stage

PMSM

Signal

Conditioning

Circuitry

Driver

Reverse Bat

Protection

Fast AD C

<1 µs, 10-bit

Timer

Safety Port

Core

FlexCAN

Faul ts

Motor

Control

PWM

10 ns res

DSPI

SPC560P40/34

Vcc

Van alo g

Vref

Vcc
Van alo g

Vref

ID

System
Basis
Chip

Windowed
Watchdog

Hi-speed CAN
Physical Layer

CAN

Complex
Hardware
Watchdog

Input

Modules

Output Drivers

(Valves, Pump)

Sensors

n

n

Safety Relay

U DC Bus

1.2 Target applications

The SPC560P40/34 belongs to an expanding range of automotive-focused products
designed to address and target the following chassis and safety market segments:

● Electric hydraulic power steering (EHPS)

● Lower end of electric power steering (EPS)

● Airbag applications

● Anti-lock braking systems (ABS)

● Motor control applications

EHPS and EPS systems typically feature sophisticated and advanced electrical motor
control periphery with special enhancements in the area of pulse width modulation, highly
flexible timers, and functional safety.

1.2.1 Application examples

Electric power steering

Figure 1 outlines a typical electric power steering application built around the

SPC560P40/34 microcontroller.

Figure 1. Electric power steering application

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Introduction RM0046

SPI

Physical
Interface

Physical
Interface

Physical
Interface

Physical
Interface

Satellite I/F

Satellite I/F

Satellite I/F

Satellite I/F

Buckle I/F

Buckle I/F

V

IGN

Safing Unit

Power Supply Control Chain

DSPI

ADC

FlexCAN

LINFlex

DSPI DSPI

X/Y - accel.

CAN Physical

Layer

LIN Physical

Layer

Body network (dashboard)

Occupant detection

4-ch Squib

Driver

V

BOOST

Squib 1

Squib 2

Squib 3

Squib 4

Custom

Device

V

BOOST

V

BUCK

V

LOGIC

V

IO

SPC560P40/34

Airbag

Figure 2 outlines a typical airbag application built around the SPC560P40/34

microcontroller.

Figure 2. Airbag application

1.3 Features

Ta bl e 1 provides a summary of different members of the SPC560P40/34 family and their

features—relative to full-featured version—to enable a comparison among the family
members and an understanding of the range of functionality offered within this family.

Feature

SPC560P34

Full-featured

1

SPC560P40

Full-featured

Table 1. SPC560P40/34 device comparison

Code flash memory (with ECC) 192 KB 256 KB

Data flash memory / EE option (with ECC) 64 KB

SRAM (with ECC) 12 KB 20 KB

Processor core 32-bit e200z0h

Instruction set VLE (variable length encoding)

CPU performance 0–64 MHz

FMPLL (frequency-modulated phase-locked loop)
module

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RM0046 Introduction

Table 1. SPC560P40/34 device comparison (continued)

Feature

SPC560P34

Full-featured

SPC560P40

Full-featured

INTC (interrupt controller) channels 120

PIT (periodic interrupt timer) 1 (with four 32-bit timers)

eDMA (enhanced direct memory access) channels 16

FlexCAN (controller area network) 1

Safety port No

(1)

Yes (via second FlexCAN

1,(2)

2

module)

FCU (fault collection unit) Yes

CTU (cross triggering unit) Yes Yes

eTimer 1 (16-bit, 6 channels)

FlexPWM (pulse-width modulation) channels

8

(capture capabity not

supported)

(capture capability not

8

supported)

Analog-to-digital converter (ADC) 1 (10-bit, 16 channels)

LINFlex

2

(1 × Master/Slave,

1 × Master only)

(1 × Master/Slave,

2

1 × Master only)

DSPI (deserial serial peripheral interface) 2 3

CRC (cyclic redundancy check) unit Yes

Junction temperature sensor No

JTAG controller Yes

Nexus port controller (NPC) Yes (Nexus Class 1)

Digital power supply

(3)

3.3 V or 5 V single supply with external transistor

Analog power supply 3.3 V or 5 V

Supply

Internal RC oscillator 16 MHz

External crystal oscillator 4–40 MHz

Packages

LQFP64

LQFP100

Temperature Standard ambient temperature –40 to 125 °C

1. Each FlexCAN module has 32 message buffers.

2. One FlexCAN module can act as a safety port with a bit rate as high as 8 Mbit/s at 64 MHz.

3. The different supply voltages vary according to the part number ordered.

SPC560P40/34 is available in two configurations having different features: Full-featured and
airbag. Ta bl e 2 shows the main differences between the two versions of the SPC560P40
MCU.

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Introduction RM0046

Table 2.

SPC560P40 device configuration differences

Configuration

Feature

Airbag Full-featured

SRAM (with ECC) 16 KB 20 KB

FlexCAN (controller area network) 1 2

Safety port No

(via second FlexCAN module)

Ye s

8

FlexPWM (pulse-width modulation) channels No

(capture capability not

supported)

CTU (cross triggering unit) No Yes

Figure 1.4 shows a top-level block diagram of the SPC560P40/34 microcontroller.

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RM0046 Introduction

SRAM

(with ECC)

Slave SlaveSlave

Code Flash

(with ECC)

Data Flash
(with ECC)

PIT

STM

SWT

MC_RGM

MC_CGM

MC_ME

BAM

SIUL

WKPU

CRC

ECSM

e200z0 Core

32-bit

general

purpose

registers

Special

purpose

registers

Integer

execution

unit

Exception

handler

Var iabl e

length

encoded

instructions

Instruction

unit

Load/store

unit

Branch

prediction

unit

JTAG

1.2 V regulator
control

XOSC

16 MHz

RC oscillator

FMPLL_0

(System)

Nexus port

controller

Interrupt

controller

eDMA

16 channels

Master

Master

Instruction

32-bit

Master

Data
32-bit

Crossbar switch (XBAR, AMBA 2.0 v6 AHB)

Peripheral bridge

FCU

Legend:

ADC Analog-to-digital converter
BAM Boot assist module
CRC Cyclic redundancy check
CTU Cross triggering unit
DSPI Deserial serial peripheral interface
ECSM Error correction status module
eDMA Enhanced direct memory access
eTimer Enhanced timer
FCU Fault collection unit
Flash Flash memory
FlexCAN Controller area network
FlexPWM Flexible pulse width modulation
FMPLL Frequency-modulated phase-locked loop
INTC Interrupt controller
JTAG JTAG controller

LINFlex Serial communication interface (LIN support)
MC_CGM Clock generation module
MC_ME Mode entry module
MC_PCU Power control unit
MC_RGM Reset generation module
PIT Periodic interrupt timer
SIUL System Integration unit Lite
SRAM Static random-access memory
SSCM System status and configuration module
STM System timer module
SWT Software watchdog timer
WKPU Wakeup unit
XOSC External oscillator
XBAR Crossbar switch

External ballast

Nexus 1

eDMA

16 channels

FlexPWM

CTU

3×

eTimer

DSPI

2×

FlexCAN

LINFlex

Safety port

ADC

(6 ch)

SSCM

(10 bit, 16 ch)

Figure 3. Block diagram (SPC560P40 full-featured configuration)

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Introduction RM0046

1.4 Critical performance parameters

● Fully static operation, 0–64 MHz

● –40 °C to 150 °C junction temperature

● Low power design

– Less than 450 mW power dissipation

– Halt and STOP mode available for power reduction

– Resuming from Halt/STOP mode can be initiated via external pin

● Fabricated in 90 nm process

● 1.2 V nominal internal logic

● Nexus pins operate at V

– Unused pins configurable as GPIO

● 10-bit ADC conversion time < 1 µs

● Internal voltage regulator (VREG) with external ballast transistor enables control with a

single input rail

– 3.0 V–3.6 V or 4.5 V–5.5 V input supply voltage

● Configurable pins

– Selectable slew rate for EMI reduction

– Selectable pull-up, pull-down, or no pull on all pins

– Selectable open drain

– Support for 3.3 V or 5 V I/O levels

(no dedicated power supply)

DDIO

1.5 Chip-level features

On-chip modules available within the family include the following features:

● Single issue, 32-bit CPU core complex (e200z0h)

– Compliant with Power Architecture™ embedded category

– Variable Length Encoding (VLE)

● Memory

– Up to 256 KB on-chip Code Flash with ECC and erase/program controller

– Up to additional 64 (4 × 16) KB on-chip Data Flash with ECC for EEPROM

emulation

– Up to 20 KB on-chip SRAM with ECC

● Fail-safe protection

– Programmable watchdog timer

– Non-maskable interrupt

– Fault collection unit

● Nexus L1 interface

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RM0046 Introduction

● Interrupts and events

– 16-channel eDMA controller

– 16 priority level controller

– Up to 25 external interrupts

– PIT implements four 32-bit timers

– 120 interrupts are routed via INTC

● General purpose I/Os

– Individually programmable as input, output or special function

– 37 on LQFP64

– 64 on LQFP100

● 1 general purpose eTimer unit

– 6 timers each with up/down capabilities

– 16-bit resolution, cascadeable counters

– Quadrature decode with rotation direction flag

– Double buffer input capture and output compare

● Communications interfaces

– 2 LINFlex channels (1 × Master/Slave, 1 × Master Only)

– Up to 3 DSPI channels with automatic chip select generation (up to 8/4/4 chip

selects)

– 1 FlexCAN interface (2.0B Active) with 32 message buffers

– 1 safety port based on FlexCAN with 32 message buffers and up to 8 Mbit/s at

64 MHz capability usable as second CAN when not used as safety port

● One 10-bit analog-to-digital converter (ADC)

– Up to 16 input channels (16 ch on LQFP100 and 12 ch on LQFP64)
– Conversion time < 1 s including sampling time at full precision

– Programmable Cross Triggering Unit (CTU)

– 4 analog watchdogs with interrupt capability

● On-chip CAN/UART bootstrap loader with Boot Assist Module (BAM)

● 1 FlexPWM unit

– 8 complementary or independent outputs with ADC synchronization signals

1.6 Module features

1.6.1 High performance e200z0 core processor

The e200z0 Power Architecture core provides the following features:

● High performance e200z0 core processor for managing peripherals and interrupts

● Single issue 4-stage pipeline in-order execution 32-bit Power Architecture CPU

● Harvard architecture

● Variable length encoding (VLE), allowing mixed 16- and 32-bit instructions

– Results in smaller code size footprint

– Minimizes impact on performance

Doc ID 16912 Rev 5 53/936

Introduction RM0046

● Branch processing acceleration using lookahead instruction buffer

● Load/store unit

– 1-cycle load latency

– Misaligned access support

– No load-to-use pipeline bubbles

● Thirty-two 32-bit general purpose registers (GPRs)

● Separate instruction bus and load/store bus Harvard architecture

● Hardware vectored interrupt support

● Reservation instructions for implementing read-modify-write constructs

● Long cycle time instructions, except for guarded loads, do not increase interrupt latency

● Extensive system development support through Nexus debug port

● Non-maskable interrupt support

1.6.2 Crossbar switch (XBAR)

The XBAR multi-port crossbar switch supports simultaneous connections between three
master ports and three slave ports. The crossbar supports a 32-bit address bus width and a
32-bit data bus width.

The crossbar allows for two concurrent transactions to occur from any master port to any
slave port; but one of those transfers must be an instruction fetch from internal flash
memory. If a slave port is simultaneously requested by more than one master port,
arbitration logic will select the higher priority master and grant it ownership of the slave port.
All other masters requesting that slave port will be stalled until the higher priority master
completes its transactions. Requesting masters will be treated with equal priority and will be
granted access a slave port in round-robin fashion, based upon the ID of the last master to
be granted access.

The crossbar provides the following features:

● 3 master ports:

– e200z0 core complex instruction port

– e200z0 core complex Load/Store Data port

–eDMA

● 3 slave ports:

– Flash memory (Code and Data)

–SRAM

– Peripheral bridge

● 32-bit internal address, 32-bit internal data paths

● Fixed Priority Arbitration based on Port Master

● Temporary dynamic priority elevation of masters

1.6.3 Enhanced direct memory access (eDMA)

The enhanced direct memory access (eDMA) controller is a second-generation module
capable of performing complex data movements via 16 programmable channels, with
minimal intervention from the host processor. The hardware micro architecture includes a
DMA engine which performs source and destination address calculations, and the actual

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RM0046 Introduction

data movement operations, along with an SRAM-based memory containing the transfer
control descriptors (TCD) for the channels.

The eDMA module provides the following features:

● 16 channels support independent 8-, 16- or 32-bit single value or block transfers

● Supports variable-sized queues and circular queues

● Source and destination address registers are independently configured to either post-

increment or to remain constant

● Each transfer is initiated by a peripheral, CPU, or eDMA channel request

● Each eDMA channel can optionally send an interrupt request to the CPU on completion

of a single value or block transfer

● DMA transfers possible between system memories, DSPIs, ADC, FlexPWM, eTimer

and CTU

● Programmable DMA channel multiplexer allows assignment of any DMA source to any

available DMA channel with as many as 30 request sources

● eDMA abort operation through software

1.6.4 Flash memory

The SPC560P40/34 provides 320 KB of programmable, non-volatile, flash memory. The
non-volatile memory (NVM) can be used for instruction and/or data storage. The flash
memory module is interfaced to the system bus by a dedicated flash memory controller. It
supports a 32-bit data bus width at the system bus port, and a 128-bit read data interface to
flash memory. The module contains four 128-bit wide prefetch buffers. Prefetch buffer hits
allow no-wait responses. Normal flash memory array accesses are registered and are
forwarded to the system bus on the following cycle, incurring two wait-states.

The flash memory module provides the following features:

● As much as 320 KB flash memory

– 6 blocks (32 KB + 2×16 KB + 32 KB + 32 KB + 128 KB) code flash memory

– 4 blocks (16 KB + 16 KB + 16 KB + 16 KB) data flash memory

– Full Read-While-Write (RWW) capability between code flash memory and data

flash memory

● Four 128-bit wide prefetch buffers to provide single cycle in-line accesses (prefetch

buffers can be configured to prefetch code or data or both)

● Typical flash memory access time: no wait-state for buffer hits, 2 wait-states for page

buffer miss at 64 MHz

● Hardware managed flash memory writes handled by 32-bit RISC Krypton engine

● Hardware and software configurable read and write access protections on a per-master

basis

● Configurable access timing allowing use in a wide range of system frequencies

● Multiple-mapping support and mapping-based block access timing (up to 31 additional

cycles) allowing use for emulation of other memory types

● Software programmable block program/erase restriction control

● Erase of selected block(s)

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Introduction RM0046

● Read page sizes

– Code flash memory: 128 bits (4 words)

– Data flash memory: 32 bits (1 word)

● ECC with single-bit correction, double-bit detection for data integrity

– Code flash memory: 64-bit ECC

– Data flash memory: 32-bit ECC

● Embedded hardware program and erase algorithm

● Erase suspend and program abort

● Censorship protection scheme to prevent flash memory content visibility

● Hardware support for EEPROM emulation

1.6.5 Static random access memory (SRAM)

The SPC560P40/34 SRAM module provides up to 20 KB of general-purpose memory.

The SRAM module provides the following features:

● Supports read/write accesses mapped to the SRAM from any master

● Up to 20 KB general purpose SRAM

● Supports byte (8-bit), half word (16-bit), and word (32-bit) writes for optimal use of

memory

● Typical SRAM access time: no wait-state for reads and 32-bit writes; 1 wait-state for 8-

and 16-bit writes if back-to-back with a read to same memory block

1.6.6 Interrupt controller (INTC)

The interrupt controller (INTC) provides priority-based preemptive scheduling of interrupt
requests, suitable for statically scheduled hard real-time systems. The INTC handles 128
selectable-priority interrupt sources.

For high-priority interrupt requests, the time from the assertion of the interrupt request by
the peripheral to the execution of the interrupt service routine (ISR) by the processor has
been minimized. The INTC provides a unique vector for each interrupt request source for
quick determination of which ISR has to be executed. It also provides a wide number of
priorities so that lower priority ISRs do not delay the execution of higher priority ISRs. To
allow the appropriate priorities for each source of interrupt request, the priority of each
interrupt request is software configurable.

When multiple tasks share a resource, coherent accesses to that resource need to be
supported. The INTC supports the priority ceiling protocol (PCP) for coherent accesses. By
providing a modifiable priority mask, the priority can be raised temporarily so that all tasks
which share the same resource can not preempt each other.

The INTC provides the following features:

● Unique 9-bit vector for each separate interrupt source

● 8 software triggerable interrupt sources

● 16 priority levels with fixed hardware arbitration within priority levels for each interrupt

source

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RM0046 Introduction

● Ability to modify the ISR or task priority: modifying the priority can be used to

implement the priority ceiling protocol for accessing shared resources.

● 1 external high priority interrupt (NMI) directly accessing the main core and I/O

processor (IOP) critical interrupt mechanism

1.6.7 System status and configuration module (SSCM)

The system status and configuration module (SSCM) provides central device functionality.

The SSCM includes these features:

● System configuration and status

– Memory sizes/status

– Device mode and security status

– Determine boot vector

– Search code flash for bootable sector

–DMA status

● Debug status port enable and selection

● Bus and peripheral abort enable/disable

1.6.8 System clocks and clock generation

The following list summarizes the system clock and clock generation on the SPC560P40/34:

● Lock detect circuitry continuously monitors lock status

● Loss of clock (LOC) detection for PLL outputs

● Programmable output clock divider (1, 2, 4, 8)

● FlexPWM module and eTimer module running at the same frequency as the e200z0h

core

● Internal 16 MHz RC oscillator for rapid start-up and safe mode: supports frequency

trimming by user application

1.6.9 Frequency-modulated phase-locked loop (FMPLL)

The FMPLL allows the user to generate high speed system clocks from a 4–40 MHz input
clock. Further, the FMPLL supports programmable frequency modulation of the system
clock. The PLL multiplication factor, output clock divider ratio are all software configurable.

The FMPLL has the following major features:

● Input clock frequency: 4–40 MHz

● Maximum output frequency: 64 MHz

● Voltage controlled oscillator (VCO)—frequency 256–512 MHz

● Reduced frequency divider (RFD) for reduced frequency operation without forcing the

FMPLL to relock

● Frequency-modulated PLL

– Modulation enabled/disabled through software

– Triangle wave modulation

● Programmable modulation depth (±0.25% to ±4% deviation from center frequency):

programmable modulation frequency dependent on reference frequency

● Self-clocked mode (SCM) operation

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1.6.10 Main oscillator

The main oscillator provides these features:

● Input frequency range: 4–40 MHz

● Crystal input mode or oscillator input mode

● PLL reference

1.6.11 Internal RC oscillator

This device has an RC ladder phase-shift oscillator. The architecture uses constant current
charging of a capacitor. The voltage at the capacitor is compared by the stable bandgap
reference voltage.

The RC oscillator provides these features:

● Nominal frequency 16 MHz

● ±5% variation over voltage and temperature after process trim

● Clock output of the RC oscillator serves as system clock source in case loss of lock or

loss of clock is detected by the PLL

● RC oscillator is used as the default system clock during startup

1.6.12 Periodic interrupt timer (PIT)

The PIT module implements these features:

● 4 general-purpose interrupt timers

● 32-bit counter resolution

● Clocked by system clock frequency

● Each channel usable as trigger for a DMA request

1.6.13 System timer module (STM)

The STM implements these features:

● One 32-bit up counter with 8-bit prescaler

● Four 32-bit compare channels

● Independent interrupt source for each channel

● Counter can be stopped in debug mode

1.6.14 Software watchdog timer (SWT)

The SWT has the following features:

● 32-bit time-out register to set the time-out period

● Programmable selection of window mode or regular servicing

● Programmable selection of reset or interrupt on an initial time-out

● Master access protection

● Hard and soft configuration lock bits

● Reset configuration inputs allow timer to be enabled out of reset

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1.6.15 Fault collection unit (FCU)

The FCU provides an independent fault reporting mechanism even if the CPU is
malfunctioning.

The FCU module has the following features:

● FCU status register reporting the device status

● Continuous monitoring of critical fault signals

● User selection of critical signals from different fault sources inside the device

● Critical fault events trigger 2 external pins (user selected signal protocol) that can be

used externally to reset the device and/or other circuitry (for example, a safety relay)

● Faults are latched into a register

1.6.16 System integration unit – Lite (SIUL)

The SPC560P40/34 SIUL controls MCU pad configuration, external interrupt, general
purpose I/O (GPIO), and internal peripheral multiplexing.

The pad configuration block controls the static electrical characteristics of I/O pins. The
GPIO block provides uniform and discrete input/output control of the I/O pins of the MCU.

The SIUL provides the following features:

● Centralized general purpose input output (GPIO) control of up to 49 input/output pins

and 16 analog input-only pads (package dependent)

● All GPIO pins can be independently configured to support pull-up, pull-down, or no pull

● Reading and writing to GPIO supported both as individual pins and 16-bit wide ports

● All peripheral pins, except ADC channels, can be alternatively configured as both

general purpose input or output pins

● ADC channels support alternative configuration as general purpose inputs

● Direct readback of the pin value is supported on all pins through the SIUL

● Configurable digital input filter that can be applied to some general purpose input pins

for noise elimination

● Up to 4 internal functions can be multiplexed onto 1 pin

1.6.17 Boot and censorship

Different booting modes are available in the SPC560P40/34: booting from internal flash
memory and booting via a serial link.

The default booting scheme uses the internal flash memory (an internal pull-down resistor is
used to select this mode). Optionally, the user can boot via FlexCAN or LINFlex (using the
boot assist module software).

A censorship scheme is provided to protect the content of the flash memory and offer
increased security for the entire device.

A password mechanism is designed to grant the legitimate user access to the non-volatile
memory.

Boot assist module (BAM)

The BAM is a block of read-only memory that is programmed once and is identical for all
SPC560Pxx devices that are based on the e200z0h core. The BAM program is executed

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every time the device is powered on if the alternate boot mode has been selected by the
user.

The BAM provides the following features:

● Serial bootloading via FlexCAN or LINFlex

● Ability to accept a password via the used serial communication channel to grant the

legitimate user access to the non-volatile memory

1.6.18 Error correction status module (ECSM)

The ECSM provides a myriad of miscellaneous control functions regarding program-visible
information about the platform configuration and revision levels, a reset status register, a
software watchdog timer, wakeup control for exiting sleep modes, and information on
platform memory errors reported by error-correcting codes and/or generic access error
information for certain processor cores.

The Error Correction Status Module supports a number of miscellaneous control functions
for the platform. The ECSM includes these features:

● Registers for capturing information on platform memory errors if error-correcting codes

(ECC) are implemented

● For test purposes, optional registers to specify the generation of double-bit memory

errors are enabled on the SPC560P40/34.

The sources of the ECC errors are:

● Flash memory

● SRAM

1.6.19 Peripheral bridge (PBRIDGE)

The PBRIDGE implements the following features:

● Duplicated periphery

● Master access privilege level per peripheral (per master: read access enable; write

access enable)

● Write buffering for peripherals

● Checker applied on PBRIDGE output toward periphery

● Byte endianess swap capability

1.6.20 Controller area network (FlexCAN)

The SPC560P40/34 MCU contains one controller area network (FlexCAN) module. This
module is a communication controller implementing the CAN protocol according to Bosch
Specification version 2.0B. The CAN protocol was designed to be used primarily as a
vehicle serial data bus, meeting the specific requirements of this field: real-time processing,
reliable operation in the EMI environment of a vehicle, cost-effectiveness and required
bandwidth. The FlexCAN module contains 32 message buffers.

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The FlexCAN module provides the following features:

● Full implementation of the CAN protocol specification, version 2.0B

– Standard data and remote frames

– Extended data and remote frames

– Up to 8-bytes data length

– Programmable bit rate up to 1 Mbit/s

● 32 message buffers of up to 8-bytes data length

● Each message buffer configurable as Rx or Tx, all supporting standard and extended

messages

● Programmable loop-back mode supporting self-test operation

● 3 programmable mask registers

● Programmable transmit-first scheme: lowest ID or lowest buffer number

● Time stamp based on 16-bit free-running timer

● Global network time, synchronized by a specific message

● Maskable interrupts

● Independent of the transmission medium (an external transceiver is assumed)

● High immunity to EMI

● Short latency time due to an arbitration scheme for high-priority messages

● Transmit features

– Supports configuration of multiple mailboxes to form message queues of scalable

depth

– Arbitration scheme according to message ID or message buffer number

– Internal arbitration to guarantee no inner or outer priority inversion

– Transmit abort procedure and notification

● Receive features

– Individual programmable filters for each mailbox

– 8 mailboxes configurable as a 6-entry receive FIFO

– 8 programmable acceptance filters for receive FIFO

● Programmable clock source

– System clock

– Direct oscillator clock to avoid PLL jitter

1.6.21 Safety port (FlexCAN)

The SPC560P40/34 MCU has a second CAN controller synthesized to run at high bit rates
to be used as a safety port. The CAN module of the safety port provides the following
features:

● Identical to the FlexCAN module

● Bit rate up to 8 Mbit/s at 64 MHz CPU clock using direct connection between CAN

modules (no physical transceiver required)

● 32 message buffers of up to 8-bytes data length

● Can be used as a second independent CAN module

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1.6.22 Serial communication interface module (LINFlex)

The LINFlex (local interconnect network flexible) on the SPC560P40/34 features the
following:

● Supports LIN Master mode (both instances), LIN Slave mode (only one instance) and

UART mode

● LIN state machine compliant to LIN1.3, 2.0 and 2.1 specifications

● Handles LIN frame transmission and reception without CPU intervention

● LIN features

– Autonomous LIN frame handling

– Message buffer to store Identifier and up to 8 data bytes

– Supports message length of up to 64 bytes

– Detection and flagging of LIN errors (sync field, delimiter, ID parity, bit framing,

checksum, and time-out)

– Classic or extended checksum calculation

– Configurable Break duration of up to 36-bit times

– Programmable baud rate prescalers (13-bit mantissa, 4-bit fractional)

– Diagnostic features: Loop back; Self Test; LIN bus stuck dominant detection

– Interrupt-driven operation with 16 interrupt sources

● LIN slave mode features:

– Autonomous LIN header handling

– Autonomous LIN response handling

– Optional discarding of irrelevant LIN responses using ID filter

● UART mode:

– Full-duplex operation

– Standard non return-to-zero (NRZ) mark/space format

– Data buffers with 4-byte receive, 4-byte transmit

– Configurable word length (8-bit or 9-bit words)

– Error detection and flagging

– Parity, Noise and Framing errors

– Interrupt-driven operation with four interrupt sources

– Separate transmitter and receiver CPU interrupt sources

– 16-bit programmable baud-rate modulus counter and 16-bit fractional

– 2 receiver wake-up methods

1.6.23 Deserial serial peripheral interface (DSPI)

The deserial serial peripheral interface (DSPI) module provides a synchronous serial
interface for communication between the SPC560P40/34 MCU and external devices.

The DSPI modules provide these features:

● Full duplex, synchronous transfers

● Master or slave operation

● Programmable master bit rates

● Programmable clock polarity and phase

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● End-of-transmission interrupt flag

● Programmable transfer baud rate

● Programmable data frames from 4 to 16 bits

● Up to 8 chip select lines available:

– 8 on DSPI_0

– 4 each on DSPI_1 and DSPI_2

● 8 clock and transfer attributes registers

● Chip select strobe available as alternate function on one of the chip select pins for

deglitching

● FIFOs for buffering up to 4 transfers on the transmit and receive side

● Queueing operation possible through use of the I/O processor or eDMA

● General purpose I/O functionality on pins when not used for SPI

1.6.24 Pulse width modulator (FlexPWM)

The pulse width modulator module (PWM) contains four PWM submodules each of which is
set up to control a single half-bridge power stage. There are also three fault channels.

This PWM is capable of controlling most motor types: AC induction motors (ACIM),
permanent magnet AC motors (PMAC), both brushless (BLDC) and brush DC motors
(BDC), switched (SRM) and variable reluctance motors (VRM), and stepper motors.

The FlexPWM block implements the following features:

● 16-bit resolution for center, edge-aligned, and asymmetrical PWMs

● Clock frequency same as that used for e200z0h core

● PWM outputs can operate as complementary pairs or independent channels

● Can accept signed numbers for PWM generation

● Independent control of both edges of each PWM output

● Synchronization to external hardware or other PWM supported

● Double buffered PWM registers

– Integral reload rates from 1 to 16

– Half cycle reload capability

● Multiple ADC trigger events can be generated per PWM cycle via hardware

● Write protection for critical registers

● Fault inputs can be assigned to control multiple PWM outputs

● Programmable filters for fault inputs

● Independently programmable PWM output polarity

● Independent top and bottom deadtime insertion

● Each complementary pair can operate with its own PWM frequency and deadtime

values

● Individual software-control for each PWM output

● All outputs can be programmed to change simultaneously via a “Force Out” event

● PWMX pin can optionally output a third PWM signal from each submodule

● Channels not used for PWM generation can be used for buffered output compare

functions

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● Channels not used for PWM generation can be used for input capture functions

● Enhanced dual-edge capture functionality

● eDMA support with automatic reload

● 2 fault inputs

● Capture capability for PWMA, PWMB, and PWMX channels not supported

1.6.25 eTimer

The SPC560P40/34 includes one eTimer module which provides six 16-bit general purpose
up/down timer/counter units with the following features:

● Clock frequency same as that used for the e200z0h core

● Individual channel capability

– Input capture trigger

– Output compare

– Double buffer (to capture rising edge and falling edge)

– Separate prescaler for each counter

– Selectable clock source

– 0–100% pulse measurement

– Rotation direction flag (quad decoder mode)

● Maximum count rate

– External event counting: max. count rate = peripheral clock/2

– Internal clock counting: max. count rate = peripheral clock

● Counters are:

– Cascadable

– Preloadable

● Programmable count modulo

● Quadrature decode capabilities

● Counters can share available input pins

● Count once or repeatedly

● Pins available as GPIO when timer functionality not in use

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1.6.26 Analog-to-digital converter (ADC) module

The ADC module provides the following features:

Analog part:

● 1 on-chip analog-to-digital converter

– 10-bit AD resolution

– 1 sample and hold unit

– Conversion time, including sampling time, less than 1 µs (at full precision)

– Typical sampling time is 150 ns minimum (at full precision)

– DNL/INL ±1 LSB

– TUE < 1.5 LSB

– Single-ended input signal up to 3.3 V/5.0 V

– 3.3 V/5.0 V input reference voltage

– ADC and its reference can be supplied with a voltage independent from V

– ADC supply can be equal or higher than V

DDIO

– ADC supply and ADC reference are not independent from each other (both

internally bonded to same pad)

– Sample times of 2 (default), 8, 64 or 128 ADC clock cycles

DDIO

Digital part:

● 16 input channels

● 4 analog watchdogs comparing ADC results against predefined levels (low, high,

range) before results are stored in the appropriate ADC result location

● 2 modes of operation: Motor Control mode or Regular mode

● Regular mode features

– Register based interface with the CPU: control register, status register and 1 result

register per channel

– ADC state machine managing 3 request flows: regular command, hardware

injected command and software injected command

– Selectable priority between software and hardware injected commands

– DMA compatible interface

● CTU-controlled mode features

– Triggered mode only

– 4 independent result queues (1×16 entries, 2×8 entries, 1×4 entries)

– Result alignment circuitry (left justified and right justified)

– 32-bit read mode allows to have channel ID on one of the 16-bit part

– DMA compatible interfaces

1.6.27 Cross triggering unit (CTU)

The cross triggering unit allows automatic generation of ADC conversion requests on user
selected conditions without CPU load during the PWM period and with minimized CPU load
for dynamic configuration.

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It implements the following features:

● Double buffered trigger generation unit with up to 8 independent triggers generated

from external triggers

● Trigger generation unit configurable in sequential mode or in triggered mode

● Each trigger can be appropriately delayed to compensate the delay of external low

pass filter

● Double buffered global trigger unit allowing eTimer synchronization and/or ADC

command generation

● Double buffered ADC command list pointers to minimize ADC-trigger unit update

● Double buffered ADC conversion command list with up to 24 ADC commands

● Each trigger capable of generating consecutive commands

● ADC conversion command allows to control ADC channel, single or synchronous

sampling, independent result queue selection

1.6.28 Nexus Development Interface (NDI)

The NDI (Nexus Development Interface) block is compliant with Nexus Class 1 of the IEEE­ISTO 5001-2003 standard. This development support is supplied for MCUs without requiring
external address and data pins for internal visibility. The NDI block is an integration of
several individual Nexus blocks that are selected to provide the development support
interface for this device. The NDI block interfaces to the host processor and internal busses
to provide development support as per the IEEE-ISTO 5001-2003 Nexus Class 1 standard.
The development support provided includes access to the MCU’s internal memory map and
access to the processor’s internal registers.

The NDI provides the following features:

● Configured via the IEEE 1149.1

● All Nexus port pins operate at V

● Nexus Class 1 supports Static debug

DDIO

1.6.29 Cyclic redundancy check (CRC)

The CRC computing unit is dedicated to the computation of CRC off-loading the CPU. The
CRC module features:

● Support for CRC-16-CCITT (x25 protocol):

16

– x

● Support for CRC-32 (Ethernet protocol):

– x

● Zero wait states for each write/read operations to the CRC_CFG and CRC_INP

+ x12 + x5 + 1

32

+ x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x + 1

registers at the maximum frequency

1.6.30 IEEE 1149.1 JTAG controller

The JTAG controller (JTAGC) block provides the means to test chip functionality and
connectivity while remaining transparent to system logic when not in test mode. All data
input to and output from the JTAGC block is communicated in serial format. The JTAGC
block is compliant with the IEEE standard.

(no dedicated power supply)

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The JTAG controller provides the following features:

● IEEE test access port (TAP) interface 4 pins (TDI, TMS, TCK, TDO)

● Selectable modes of operation include JTAGC/debug or normal system operation.

● 5-bit instruction register that supports the following IEEE 1149.1-2001 defined

instructions:

– BYPASS

– IDCODE

–EXTEST

–SAMPLE

– SAMPLE/PRELOAD

● 5-bit instruction register that supports the additional following public instructions:

– ACCESS_AUX_TAP_NPC

– ACCESS_AUX_TAP_ONCE

● 3 test data registers:

– Bypass register

– Boundary scan register (size parameterized to support a variety of boundary scan

chain lengths)

– Device identification register

● TAP controller state machine that controls the operation of the data registers,

instruction register and associated circuitry

1.6.31 On-chip voltage regulator (VREG)

The on-chip voltage regulator module provides the following features:

● Uses external NPN (negative-positive-negative) transistor

● Regulates external 3.3 V/5.0 V down to 1.2 V for the core logic

● Low voltage detection on the internal 1.2 V and I/O voltage 3.3 V

1.7 Developer environment

The following development support is available:

● Automotive Evaluation Boards (EVBs) featuring CAN, LIN interfaces, and more

● Compilers

● Debuggers

● JTAG and Nexus interfaces

● Autocode generation tools

● Initialization tools

1.8 Package

In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK

®

packages, depending on their level of environmental compliance. ECOPACK®

®

is an ST trademark.

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SPC560P40/34 family members are offered in the following package types:

● 64-pin LQFP, 0.5 mm pitch, 10 mm × 10 mm outline

● 100-pin LQFP, 0.5 mm pitch, 14 mm × 14 mm outline

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RM0046 SPC560P40/34 memory map

2 SPC560P40/34 memory map

Ta bl e 3 shows the memory map for the SPC560P40/34. All addresses on the

SPC560P40/34, including those that are reserved, are identified in the table. The addresses
represent the physical addresses assigned to each IP block.

Table 3. Memory map

Start address End address

0x0000_0000 0x0003_FFFF 256 Code Flash Array 0

0x0004_0000 0x001F_FFFF 1792 Reserved

0x0020_0000 0x0020_3FFF 16 Code Flash Array 0 Shadow Sector

0x0020_4000 0x003F_FFFF 2032 Reserved

0x0040_0000 0x0040_3FFF 16 Code Flash Array 0 Test Sector

0x0040_4000 0x007F_FFFF 4080 Reserved

0x0080_0000 0x0080_FFFF 64 Data Flash Array 0

0x0081_0000 0x00C0_1FFF 4040 Reserved

0x00C0_2000 0x00C0_3FFF 8 Data Flash Array 0 Test Sector

0x00C0_4000 0x00FF_FFFF 4080 Reserved

0x0100_0000 0x1FFF_FFFF 507904 Flash Emulation Mapping

0x2000_0000 0x3FFF_FFFF 524288 Reserved

0x4000_0000 0x4000_4FFF 20 SRAM

0x4000_5000 0xC3F8_0000

Size
(KB)

104853

6

Region name

On-chip memory

Reserved

On-chip peripherals

0xC3F8_0000 0xC3F8_7FFF 32 Reserved

0xC3F8_8000 0xC3F8_BFFF 16 Code Flash 0 Configuration (CFLASH_0)

0xC3F8_C000 0xC3F8_FFFF 16 Data Flash 0 Configuration (DFLASH_0)

0xC3F9_0000 0xC3F9_3FFF 16 System Integration Unit Lite (SIUL)

0xC3F9_4000 0xC3F9_7FFF 16 WakeUp Unit (WKUP)

0xC3F9_8000 0xC3FD_7FFF 256 Reserved

0xC3FD_8000 0xC3FD_BFFF 16 System Status and Configuration Module (SSCM)

0xC3FD_C000 0xC3FD_FFFF 16 Mode Entry module (ME)

0xC3FE_0000 0xC3FE_3FFF 16 Clock Generation Module (CGM, XOSC, IRC, FMPLL_0, CMU0)

0xC3FE_4000 0xC3FE_7FFF 16 Reset Generation Module (RGM)

0xC3FE_8000 0xC3FE_BFFF 16 Power Control Unit (PCU)

0xC3FE_C000 0xC3FE_FFFF 16 Reserved

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SPC560P40/34 memory map RM0046

Table 3. Memory map (continued)

Start address End address

0xC3FF_0000 0xC3FF_3FFF 16 Periodic Interrupt Timer (PIT)

0xC3FF_4000 0xC3FF_FFFF 48 Reserved

0xFFE0_0000 0xFFE0_3FFF 16 Analog to Digital Converter 0 (ADC_0)

0xFFE0_4000 0xFFE0_BFFF 32 Reserved

0xFFE0_C000 0xFFE0_FFFF 16 CTU_0

0xFFE1_0000 0xFFE1_7FFF 32 Reserved

0xFFE1_8000 0xFFE1_BFFF 16 eTimer_0

0xFFE1_C000 0xFFE2_3FFF 32 Reserved

0xFFE2_4000 0xFFE2_7FFF 16 FlexPWM_0

0xFFE2_8000 0xFFE3_FFFF 96 Reserved

0xFFE4_0000 0xFFE4_3FFF 16 LINFlex_0

0xFFE4_4000 0xFFE4_7FFF 16 LINFlex_1

0xFFE5_0000 0xFFE6_7FFF 128 Reserved

0xFFE6_8000 0xFFE6_BFFF 16 Cyclic Redundancy Check (CRC)

0xFFE6_C000 0xFFE6_FFFF 16 Fault Collection Unit (FCU)

0xFFE7_0000 0xFFE7_FFFF 64 Reserved

Size
(KB)

Region name

0xFFE8_0000 0xFFEF_FFFF 512 Mirrored (range 0xC3F8_0000 – 0xC3FF_FFFF)

0xFFF0_0000 0xFFF3_7FFF 224 Reserved

0xFFF3_8000 0xFFF3_BFFF 16 Software Watchdog (SWT_0)

0xFFF3_C000 0xFFF3_FFFF 16 System Timer Module (STM_0)

0xFFF4_0000 0xFFF4_3FFF 16 Error Correction Status Module (ECSM)

0xFFF4_4000 0xFFF4_7FFF 16 Enhanced Direct Memory Access Controller (eDMA)

0xFFF4_8000 0xFFF4_BFFF 16 Interrupt Controller (INTC)

0xFFF4_C000 0xFFF8_FFFF 272 Reserved

0xFFF9_0000 0xFFF9_3FFF 16 DSPI_0

0xFFF9_4000 0xFFF9_7FFF 16 DSPI_1

0xFFF9_8000 0xFFF9_BFFF 16 DSPI_2

0xFFF9_C000 0xFFFB_FFFF 144 Reserved

0xFFFC_0000 0xFFFC_3FFF 16 FlexCAN_0 (CAN0)

0xFFFC_4000 0xFFFD_BFFF 96 Reserved

0xFFFD_C000 0xFFFD_FFFF 16 DMA Multiplexer (DMA_MUX)

0xFFFE_0000 0xFFFE_7FFF 32 Reserved

0xFFFE_8000 0xFFFE_BFFF 16 Safety Port (FlexCAN)

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RM0046 SPC560P40/34 memory map

Table 3. Memory map (continued)

Start address End address

0xFFFE_C000 0xFFFF_BFFF 64 Reserved

0xFFFF_C000 0xFFFF_FFFF 16 Boot Assist Module (BAM)

1. This address space contains also VREG registers. See 34, “Voltage Regulators and Power Supplies.”

Size
(KB)

Region name

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Signal Description RM0046

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

26272829303132333435363738394041424344454647484950

100

9998979695949392919089888786858483828180797877

76

NMI
A[6]
D[1]
A[7]
C[4]
A[8]
C[5]
A[5]
C[7]

C[3]
N.C.
N.C.

VDD_HV_IO1

VSS_HV_IO1

D[9]

VDD_HV_OSC

VSS_HV_OSC

XTAL

EXTAL

RESET

D[8]

D[5]

D[6]

VSS_LV_COR0

VDD_LV_COR0

A[4]
VPP_TEST
D[14]
C[14]
C[13]
D[12]
N.C.
N.C.
D[13]
VSS_LV_COR1
VDD_LV_COR1
A[3]
VDD_HV_IO2
VSS_HV_IO2
TDO
TCK
TMS
TDI
A[2]
C[12]
C[11]
D[11]
D[10]
A[1]
A[0]

D[7]

E[1]

C[1]

B[7]

C[2]

B[8]

E[2]

N.C.

N.C.

B[9]

B[10]

B[11]

B[12]

VDD_HV_ADC0

VSS_HV_ADC0

E[7]/D[15]

E[3]/B[13]

E[5]/B[15]

E[4]/B[14]

E[6]/C[0]

N.C.

BCTRL

N.C.

N.C.

VDD_HV_REG

A[15]

A[14]

C[6]

D[2]

B[6]

A[13]

A[9]

VSS_LV_COR2

VDD_LV_COR2

C[8]

D[4]

D[3]

VSS_HV_IO3

VDD_HV_IO3

D[0]

C[15]

C[9]

A[12]

A[11]

A[10]

B[3]

B[2]

C[10]

B[1]

B[0]

LQFP100

3 Signal Description

This chapter describes the signals of the SPC560P40/34. It includes a table of signal
properties and detailed descriptions of signals.

3.1 100-pin LQFP pinout

Figure 4 and Figure 5 shows the pinout of the 100-pin LQFP.

72/936 Doc ID 16912 Rev 5

Figure 4. 100-pin LQFP pinout – Full featured configuration (top view)

RM0046 Signal Description

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

26272829303132333435363738394041424344454647484950

100

9998979695949392919089888786858483828180797877

76

NMI
A[6]
D[1]
A[7]
C[4]
A[8]
C[5]
A[5]
C[7]

C[3]
N.C.
N.C.

VDD_HV_IO1

VSS_HV_IO1

D[9]

VDD_HV_OSC

VSS_HV_OSC

XTAL

EXTAL

RESET

D[8]

D[5]

D[6]

VSS_LV_COR0

VDD_LV_COR0

A[4]
VPP_TEST
D[14]
C[14]
C[13]
D[12]
N.C.
N.C.
D[13]
VSS_LV_COR1
VDD_LV_COR1
A[3]
VDD_HV_IO2
VSS_HV_IO2
TDO
TCK
TMS
TDI
A[2]
C[12]
C[11]
D[11]
D[10]
A[1]
A[0]

D[7]

E[1]

C[1]

B[7]

C[2]

B[8]

E[2]

N.C.

N.C.

B[9]

B[10]

B[11]

B[12]

VDD_HV_ADC0

VSS_HV_ADC0

E[7]/D[15]

E[3]/B[13]

E[5]/B[15]

E[4]/B[14]

E[6]/C[0]

N.C.

BCTRL

N.C.

N.C.

VDD_HV_REG

A[15]

A[14]

C[6]

D[2]

B[6]

A[13]

A[9]

VSS_LV_COR2

VDD_LV_COR2

C[8]

D[4]

D[3]

VSS_HV_IO3

VDD_HV_IO3

D[0]

C[15]

C[9]

A[12]

A[11]

A[10]

B[3]

B[2]

C[10]

B[1]

B[0]

LQFP100

Figure 5. 100-pin LQFP pinout – Airbag configuration (top view)

Doc ID 16912 Rev 5 73/936

Signal Description RM0046

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33

171819202122232425

26272829303132

646362616059585756555453525150

49

NMI
A[6]
A[7]
A[8]
A[5]

VDD_HV_IO1

VSS_HV_IO1

D[9]

VDD_HV_OSC

VSS_HV_OSC

XTAL

EXTAL

RESET

D[8]

VSS_LV_COR0

VDD_LV_COR0

A[4]
VPP_TEST
D[14]]
D[12]
D[13
VSS_LV_COR1
VDD_LV_COR1
A[3]
VDD_HV_IO2
VSS_HV_IO2
TDO
TCK
TMS
TDI
C[12]
C[11]

D[7]

E[1]

C[1]

B[7]

C[2]

B[8]

E[2]

B[9]

B[10]

B[11]

B[12]

VDD_HV_ADC0

VSS_HV_ADC0

E[3]/B[13]

BCTRL

VDD_HV_REG

A[15]

A[14]

B[6]

A[13]

A[9]

VSS_LV_COR2

VDD_LV_COR2

C[8]

VSS_HV_IO3

VDD_HV_IO3

A[12]

A[11]

A[10]

B[2]

B[1]

B[0]

LQFP64

3.2 64-pin LQFP pinout

Figure 6. 64-pin LQFP pinout – Full featured configuration (top view)

74/936 Doc ID 16912 Rev 5

RM0046 Signal Description

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33

171819202122232425

26272829303132

646362616059585756555453525150

49

NMI

A[6]
A[7]
A[8]
A[5]

VDD_HV_IO1

VSS_HV_IO1

D[9]

VDD_HV_OSC

VSS_HV_OSC

XTAL

EXTAL

RESET

D[8]
VSS_LV_COR0
VDD_LV_COR0

A[4]
VPP_TEST
D[14]
D[12]
D[13]
VSS_LV_COR1
VDD_LV_COR1
A[3]
VDD_HV_IO2
VSS_HV_IO2
TDO
TCK
TMS
TDI
C[12]
C[11]

D[7]

E[1]

C[1]

B[7]

C[2]

B[8]

E[2]

B[9]

B[10]

B[11]

B[12]

VDD_HV_ADC0

VSS_HV_ADC0

E[3]/B[13]

BCTRL

VDD_HV_REG

A[15]

A[14]

B[6]

A[13]

A[9]

VSS_LV_COR2

VDD_LV_COR2

C[8]

VSS_HV_IO3

VDD_HV_IO3

A[12]

A[11]

A[10]

B[2]

B[1]]

B[0]

LQFP64

Figure 7. 64-pin LQFP pinout – Airbag configuration (top view)

3.3 Pin description

3.3.1 Power supply and reference voltage pins

The following sections provide signal descriptions and related information about the
functionality and configuration of the SPC560P40/34 devices.

Ta bl e 4 lists the power supply and reference voltage for the SPC560P40/34 devices.

Doc ID 16912 Rev 5 75/936

Signal Description RM0046

Table 4. Supply pins

Supply Pin

Symbol Description 64-pin 100-pin

VREG control and power supply pins. Pins available on 64-pin and 100-pin packages

BCTRL Voltage regulator external NPN ballast base control pin 31 47

V

DD_HV_REG

(3.3 V or 5.0 V)

Voltage regulator supply voltage 32 50

ADC_0 reference and supply voltage. Pins available on 64-pin and 100-pin packages

(1)

V

DD_HV_ADC0

V

SS_HV_ADC0

ADC_0 supply and high reference voltage 28 39

ADC_0 ground and low reference voltage 29 40

Power supply pins (3.3 V or 5.0 V). Pins available on 64-pin and 100-pin packages

V

DD_HV_IO1

V

SS_HV_IO1

V

DD_HV_IO2

V

SS_HV_IO2

V

DD_HV_IO3

V

SS_HV_IO3

V

DD_HV_OSC

V

SS_HV_OSC

Input/output supply voltage 6 13

Input/output ground 7 14

Input/output supply voltage and data Flash memory supply voltage 40 63

Input/output ground and Flash memory HV ground 39 62

Input/output supply voltage and code Flash memory supply voltage 55 87

Input/output ground and code Flash memory HV ground 56 88

Crystal oscillator amplifier supply voltage 9 16

Crystal oscillator amplifier ground 10 17

Power supply pins (1.2 V). Pins available on 64-pin and 100-pin packages

V

DD_LV_COR0

V

SS_LV_COR0

V

DD_LV_COR1

V

SS_LV_COR1

V

DD_LV_COR2

V

SS_LV_COR2

1. Analog supply/ground and high/low reference lines are internally physically separate, but are shorted via a double-bonding
connection on V

1.2 V supply pins for core logic and PLL. Decoupling capacitor must be
connected between these pins and the nearest V

SS_LV_COR

pin.

1.2 V supply pins for core logic and PLL. Decoupling capacitor must be
connected between these pins and the nearest V

DD_LV_COR

pin.

1.2 V supply pins for core logic and data Flash. Decoupling capacitor must
be connected between these pins and the nearest V

SS_LV_COR

pin.

1.2 V supply pins for core logic and data Flash. Decoupling capacitor must
be connected between these pins and the nearest V

DD_LV_COR

pin.

1.2 V supply pins for core logic and code Flash. Decoupling capacitor
must be connected between these pins and the nearest V

SS_LV_COR

1.2 V supply pins for core logic and code Flash. Decoupling capacitor
must be connected betwee.n these pins and the nearest V

DD_HV_ADCx/VSS_HV_ADCx

pins.

DD_LV_COR

pin.

pin.

16 25

15 24

42 65

43 66

58 92

59 93

3.3.2 System pins

Ta bl e 5 and Ta bl e 6 contain information on pin functions for the SPC560P40/34 devices.

The pins listed in Ta bl e 5 are single-function pins. The pins shown in Ta b le 6 are multi­function pins, programmable via their respective pad configuration register (PCR) values.

76/936 Doc ID 16912 Rev 5

RM0046 Signal Description

Table 5. System pins

Pad speed

(1)

Symbol Description Direction

SRC = 0 SRC = 1 64-pin 100-pin

Dedicated pins

NMI Non-maskable Interrupt Input only Slow — 1 1

Analog output of the oscillator amplifier

XTAL

circuit—needs to be grounded if oscillator is

———1118

used in bypass mode

Analog input of the oscillator amplifier circuit,

EXTAL

when the oscillator is not in bypass mode
Analog input for the clock generator when the

———1219

oscillator is in bypass mode

TDI JTAG test data input Input only Slow — 35 58

TMS JTAG state machine control Input only Slow — 36 59

TCK JTAG clock Input only Slow — 37 60

TDO JTAG test data output Output only Slow Fast 38 61

Reset pin

RESET

Bidirectional reset with Schmitt trigger
characteristics and noise filter

Bidirectional Medium — 13 20

Test pin

VPP_TEST

1. SRC values refer to the value assigned to the Slew Rate Control bits of the pad configuration register.

Pin for testing purpose only. To be tied to
ground in normal operating mode.

———4774

Pin

3.3.3 Pin multiplexing

Ta bl e 6 defines the pin list and muxing for the SPC560P40/34 devices.

Each row of Ta bl e 6 shows all the possible ways of configuring each pin, via alternate
functions. The default function assigned to each pin after reset is the ALT0 function.

SPC560P40/34 devices provide three main I/O pad types, depending on the associated
functions:

● Slow pads are the most common, providing a compromise between transition time and

low electromagnetic emission.

● Medium pads provide fast enough transition for serial communication channels with

controlled current to reduce electromagnetic emission.

● Fast pads provide maximum speed. They are used for improved NEXUS debugging

capability.

Medium and Fast pads can use slow configuration to reduce electromagnetic emission, at
the cost of reducing AC performance. For more information, see “Pad AC Specifications” in
the device datasheet.

Doc ID 16912 Rev 5 77/936

Signal Description RM0046

Table 6. Pin muxing

Port

pin

PCR

register

Alternate

function

(2)

ALT0
ALT1

A[0] PCR[0]

ALT2
ALT3

—

ALT0
ALT1

A[1] PCR[1]

ALT2
ALT3

—

ALT0
ALT1
ALT2

A[2] PCR[2]

ALT3

—
—
—

(1),

Functions Peripheral

GPIO[0]

ETC[0]

SCK

F[0]

EIRQ[0]

GPIO[1]

ETC[1]

SOUT

F[1]

EIRQ[1]

GPIO[2]

ETC[2]

—
A[3]
SIN

ABS[0]

EIRQ[2]

Port A (16-bit)

SIUL

eTimer_0

DSPI_2

FCU_0

SIUL

SIUL

eTimer_0

DSPI_2

FCU_0

SIUL

SIUL

eTimer_0

—

FlexPWM_0

DSPI_2

MC_RGM

SIUL

(3)

I/O
direc­tion

I/O

I/O

I/O

O

I

I/O

I/O

O
O

I

I/O

I/O

—

O

I
I
I

Pad speed

(4)

SRC = 0 SRC = 1 64-pin 100-pin

(5)

Slow Medium — 51

Slow Medium — 52

Slow Medium — 57

Pin

A[3] PCR[3]

A[4] PCR[4]

A[5] PCR[5]

A[6] PCR[6]

ALT0
ALT1
ALT2
ALT3

—
—

ALT0
ALT1
ALT2
ALT3

—
—

ALT0
ALT1
ALT2
ALT3

—

ALT0
ALT1
ALT2
ALT3

—

GPIO[3]

ETC[3]

CS0

B[3]

ABS[1]

EIRQ[3]

GPIO[4]

—

CS1

ETC[4]

FAB

EIRQ[4]

GPIO[5]

CS0

—

CS7

EIRQ[5]

GPIO[6]

SCK

—
—

EIRQ[6]

SIUL

eTimer_0

DSPI_2

FlexPWM_0

MC_RGM

SIUL

SIUL

—

DSPI_2

eTimer_0

MC_RGM

SIUL

SIUL

DSPI_1

—

DSPI_0

SIUL

SIUL

DSPI_1

—
—

SIUL

I/O

I/O

I/O

O

I/O

—

O

I/O

I/O

I/O

—

O

I/O

I/O

—
—

Slow Medium 41 64

I
I

Slow Medium 48 75

I
I

Slow Medium 5 8

I

Slow Medium 2 2

I

78/936 Doc ID 16912 Rev 5

RM0046 Signal Description

Table 6. Pin muxing (continued)

Port

pin

PCR

register

Alternate

function

(2)

(1),

Functions Peripheral

(3)

I/O
direc­tion

Pad speed

(4)

SRC = 0 SRC = 1 64-pin 100-pin

(5)

Pin

A[7] PCR[7]

A[8] PCR[8]

A[9] PCR[9]

A[10] PCR[10]

A[11] PCR[11]

A[12] PCR[12]

ALT0
ALT1
ALT2
ALT3

—

ALT0
ALT1
ALT2
ALT3

—
—

ALT0
ALT1
ALT2
ALT3

—

ALT0
ALT1
ALT2
ALT3

—

ALT0
ALT1
ALT2
ALT3

—

ALT0
ALT1
ALT2
ALT3

—

GPIO[7]

SOUT

—
—

EIRQ[7]

GPIO[8]

—
—
—

SIN

EIRQ[8]

GPIO[9]

CS1

—

B[3]

FAULT[0]

GPIO[10]

CS0

B[0]
X[2]

EIRQ[9]

GPIO[11]

SCK

A[0]
A[2]

EIRQ[10]

GPIO[12]

SOUT

A[2]
B[2]

EIRQ[11]

SIUL

DSPI_1

—
—

SIUL

SIUL

—
—
—

DSPI_1

SIUL

SIUL

DSPI_2

—
FlexPWM_0
FlexPWM_0

SIUL

DSPI_2
FlexPWM_0
FlexPWM_0

SIUL

SIUL

DSPI_2
FlexPWM_0
FlexPWM_0

SIUL

SIUL

DSPI_2
FlexPWM_0
FlexPWM_0

SIUL

I/O

O
—
—

I/O

—
—
—

I/O

O
—

O

I/O
I/O

O

O

I/O
I/O

O

O

I/O

O

O

O

Slow Medium 3 4

I

Slow Medium 4 6

I
I

Slow Medium 60 94

I

Slow Medium 52 81

I

Slow Medium 53 82

I

Slow Medium 54 83

I

A[13] PCR[13]

ALT0
ALT1
ALT2
ALT3

—
—
—

GPIO[13]

—

B[2]

—

SIN
FAULT[0]
EIRQ[12]

SIUL

—

FlexPWM_0

—

DSPI_2

FlexPWM_0

SIUL

I/O

—

O

—

Slow Medium 61 95
I
I
I

Doc ID 16912 Rev 5 79/936

Signal Description RM0046

Table 6. Pin muxing (continued)

Port

pin

PCR

register

Alternate

function

(2)

(1),

Functions Peripheral

(3)

I/O
direc­tion

Pad speed

(4)

SRC = 0 SRC = 1 64-pin 100-pin

(5)

Pin

A[14] PCR[14]

A[15] PCR[15]

B[0] PCR[16]

B[1] PCR[17]

B[2] PCR[18]

B[3] PCR[19]

ALT0
ALT1
ALT2
ALT3

—

ALT0
ALT1
ALT2
ALT3

—
—

ALT0
ALT1
ALT2
ALT3

—

ALT0
ALT1
ALT2
ALT3

—
—

ALT0
ALT1
ALT2
ALT3

—

ALT0
ALT1
ALT2
ALT3

—

GPIO[14]

TXD

—
—

EIRQ[13]

GPIO[15]

—
—
—

RXD

EIRQ[14]

GPIO[16]

TXD

—

DEBUG[0]

EIRQ[15]

GPIO[17]

—
—

DEBUG[1]

RXD

EIRQ[16]

GPIO[18]

TXD

—

DEBUG[2]

EIRQ[17]

GPIO[19]

—
—

DEBUG[3]

RXD

SIUL

Safety Port_0

—
—

SIUL

SIUL

—
—
—

Safety Port_0

SIUL

Port B (16-bit)

SIUL

FlexCAN_0

—

SSCM

SIUL

SIUL

—
—

SSCM

FlexCAN_0

SIUL

SIUL

LIN_0

—

SSCM

SIUL

SIUL

—
—

SSCM

LIN_0

I/O

O
—
—

I/O

—
—
—

I/O

O
—
—

I/O

—
—
—

I/O

O
—
—

I/O

—
—
—

Slow Medium 63 99

I

Slow Medium 64 100

I
I

Slow Medium 49 76

I

Slow Medium 50 77

I
I

Slow Medium 51 79

I

Slow Medium — 80

I

B[6] PCR[22]

ALT0
ALT1
ALT2
ALT3

—

GPIO[22]

CLKOUT

CS2

—

EIRQ[18]

SIUL

Control

DSPI_2

—

SIUL

80/936 Doc ID 16912 Rev 5

I/O

O

O
—

Slow Medium 62 96

I

RM0046 Signal Description

Table 6. Pin muxing (continued)

Port

pin

PCR

register

Alternate

function

(2)

(1),

Functions Peripheral

(3)

I/O
direc­tion

Pad speed

(4)

SRC = 0 SRC = 1 64-pin 100-pin

(5)

Pin

B[7] PCR[23]

B[8] PCR[24]

B[9] PCR[25]

B[10] PCR[26]

B[11] PCR[27]

B[12] PCR[28]

B[13] PCR[29]

ALT0
ALT1
ALT2
ALT3

—
—

ALT0
ALT1
ALT2
ALT3

—
—

ALT0
ALT1
ALT2
ALT3

—

ALT0
ALT1
ALT2
ALT3

—

ALT0
ALT1
ALT2
ALT3

—

ALT0
ALT1
ALT2
ALT3

—

ALT0
ALT1
ALT2
ALT3

—
—
—

GPIO[23]

—
—
—

AN[0]

RXD

GPIO[24]

—
—
—

AN[1]

ETC[5]

GPIO[25]

—
—
—

AN[11]

GPIO[26]

—
—
—

AN[12]

GPIO[27]

—
—
—

AN[13]

GPIO[28]

—
—
—

AN[14]

GPIO[29]

—
—
—

AN[6]

emu. AN[0]

RXD

SIUL

—
—
—

ADC_0

LIN_0

SIUL

—
—
—

ADC_0

eTimer_0

SIUL

—
—
—

ADC_0

SIUL

—
—
—

ADC_0

SIUL

—
—
—

ADC_0

SIUL

—
—
—

ADC_0

SIUL

—
—
—

ADC_0

emu. ADC_1

LIN_1

Input only — — 20 29

Input only — — 22 31

Input only — — 24 35

Input only — — 25 36

Input only — — 26 37

Input only — — 27 38

Input only — — 30 42

(6)

Doc ID 16912 Rev 5 81/936

Signal Description RM0046

Table 6. Pin muxing (continued)

Port

pin

PCR

register

Alternate

function

(2)

(1),

Functions Peripheral

(3)

I/O
direc­tion

Pad speed

(4)

SRC = 0 SRC = 1 64-pin 100-pin

(5)

Pin

B[14] PCR[30]

B[15] PCR[31]

C[0] PCR[32]

C[1] PCR[33]

C[2] PCR[34]

C[3] PCR[35]

ALT0
ALT1
ALT2
ALT3

—
—
—
—

ALT0
ALT1
ALT2
ALT3

—
—
—

ALT0
ALT1
ALT2
ALT3

—
—

ALT0
ALT1
ALT2
ALT3

—

ALT0
ALT1
ALT2
ALT3

—

ALT0
ALT1
ALT2
ALT3

—

GPIO[30]

—
—
—

AN[7]

emu. AN[1]

ETC[4]

EIRQ[19]

GPIO[31]

—
—
—

AN[8]

emu. AN[2]

EIRQ[20]

GPIO[32]

—
—
—

AN[9]

emu. AN[3]

GPIO[33]

—
—
—

AN[2]

GPIO[34]

—
—
—

AN[3]

GPIO[35]

CS1

—

TXD

EIRQ[21]

SIUL

—
—
—

ADC_0

emu. ADC_1

eTimer_0

SIUL

SIUL

—
—
—

ADC_0

emu. ADC_1

SIUL

Port C (16-bit)

SIUL

—
—
—

ADC_0

emu. ADC_1

SIUL

—
—
—

ADC_0

SIUL

—
—
—

ADC_0

SIUL

DSPI_0

—

LIN_1

SIUL

Input only — — — 44

(6)

Input only — — — 43

(6)

Input only — — — 45

(6)

Input only — — 19 28

Input only — — 21 30

I/O

O

—

Slow Medium — 10

O

I

82/936 Doc ID 16912 Rev 5

RM0046 Signal Description

Table 6. Pin muxing (continued)

Port

pin

PCR

register

Alternate

function

(2)

(1),

Functions Peripheral

(3)

I/O
direc­tion

Pad speed

(4)

SRC = 0 SRC = 1 64-pin 100-pin

(5)

Pin

C[4] PCR[36]

C[5] PCR[37]

C[6] PCR[38]

C[7] PCR[39]

C[8] PCR[40]

C[9] PCR[41]

C[10] PCR[42]

ALT0
ALT1
ALT2
ALT3

—

ALT0
ALT1
ALT2
ALT3

—

ALT0
ALT1
ALT2
ALT3

—

ALT0
ALT1
ALT2
ALT3

—

ALT0
ALT1
ALT2
ALT3

ALT0
ALT1
ALT2
ALT3

ALT0
ALT1
ALT2
ALT3

—

GPIO[36]

CS0

X[1]

DEBUG[4]

EIRQ[22]

GPIO[37]

SCK

—

DEBUG[5]

EIRQ[23]

GPIO[38]

SOUT

B[1]

DEBUG[6]

EIRQ[24]

GPIO[39]

—

A[1]

DEBUG[7]

SIN

GPIO[40]

CS1

—

CS6

GPIO[41]

CS3

—

X[3]

GPIO[42]

CS2

—

A[3]

FAULT[1]

SIUL

DSPI_0

FlexPWM_0

SSCM

SIUL

SIUL

DSPI_0

—

SSCM

SIUL

SIUL

DSPI_0

FlexPWM_0

SSCM

SIUL

SIUL

—

FlexPWM_0

SSCM

DSPI_0

SIUL

DSPI_1

—

DSPI_0

SIUL

DSPI_2

—

FlexPWM_0

SIUL

DSPI_2

—
FlexPWM_0
FlexPWM_0

I/O
I/O

O

—

I/O
I/O

—
—

I/O

O
O

—

I/O

—

O

—

I/O

O

—

O

I/O

O

—

O

I/O

O

—

O

Slow Medium — 5

I

Slow Medium — 7

I

Slow Medium — 98

I

Slow Medium — 9

I

Slow Medium 57 91

Slow Medium — 84

Slow Medium — 78

I

C[11] PCR[43]

C[12] PCR[44]

ALT0
ALT1
ALT2
ALT3

ALT0
ALT1
ALT2
ALT3

GPIO[43]

ETC[4]

CS2

—

GPIO[44]

ETC[5]

CS3

—

SIUL

eTimer_0

DSPI_2

—

SIUL

eTimer_0

DSPI_2

—

I/O
I/O

O

—

I/O
I/O

O

—

Slow Medium 33 55

Slow Medium 34 56

Doc ID 16912 Rev 5 83/936

Signal Description RM0046

Table 6. Pin muxing (continued)

Port

pin

PCR

register

Alternate

function

(2)

(1),

Functions Peripheral

(3)

I/O
direc­tion

Pad speed

(4)

SRC = 0 SRC = 1 64-pin 100-pin

(5)

Pin

C[13] PCR[45]

C[14] PCR[46]

C[15] PCR[47]

D[0] PCR[48]

D[1] PCR[49]

D[2] PCR[50]

ALT0
ALT1
ALT2
ALT3

—
—

ALT0
ALT1
ALT2
ALT3

ALT0
ALT1
ALT2
ALT3

—
—

ALT0
ALT1
ALT2
ALT3

ALT0
ALT1
ALT2
ALT3

ALT0
ALT1
ALT2
ALT3

GPIO[45]

—
—
—

EXT_IN

EXT_SYNC

GPIO[46]

—

EXT_TGR

—

GPIO[47]

—
—

A[1]

EXT_IN

EXT_SYNC

GPIO[48]

—
—

B[1]

GPIO[49]

—
—

EXT_TRG

GPIO[50]

—
—

X[3]

SIUL

—
—
—

CTU_0

FlexPWM_0

SIUL

—

CTU_0

—

SIUL

—
—

FlexPWM_0

CTU_0

FlexPWM_0

Port D (16-bit)

SIUL

—
—

FlexPWM_0

SIUL

—
—

CTU_0

SIUL

—
—

FlexPWM_0

I/O

—
—
—

I/O

—

O

—

I/O

—
—

O

I/O

—
—

O

I/O

—
—

O

I/O

—
—

O

Slow Medium — 71

I
I

Slow Medium — 72

Slow Medium — 85

I
I

Slow Medium — 86

Slow Medium — 3

Slow Medium — 97

D[3] PCR[51]

D[4] PCR[52]

D[5] PCR[53]

ALT0
ALT1
ALT2
ALT3

ALT0
ALT1
ALT2
ALT3

ALT0
ALT1
ALT2
ALT3

GPIO[51]

—
—

A[3]

GPIO[52]

—
—

B[3]

GPIO[53]

CS3

F[0]

—

SIUL

—
—

FlexPWM_0

SIUL

—
—

FlexPWM_0

SIUL

DSPI_0

FCU_0

—

84/936 Doc ID 16912 Rev 5

I/O

—
—

O

I/O

—
—

O

I/O

O
O

—

Slow Medium — 89

Slow Medium — 90

Slow Medium — 22

RM0046 Signal Description

Table 6. Pin muxing (continued)

Port

pin

PCR

register

Alternate

function

(2)

(1),

Functions Peripheral

(3)

I/O
direc­tion

Pad speed

(4)

SRC = 0 SRC = 1 64-pin 100-pin

(5)

Pin

D[6] PCR[54]

D[7] PCR[55]

D[8] PCR[56]

D[9] PCR[57]

D[10] PCR[58]

D[11] PCR[59]

D[12] PCR[60]

ALT0
ALT1
ALT2
ALT3

—

ALT0
ALT1
ALT2
ALT3

ALT0
ALT1
ALT2
ALT3

ALT0
ALT1
ALT2
ALT3

ALT0
ALT1
ALT2
ALT3

ALT0
ALT1
ALT2
ALT3

ALT0
ALT1
ALT2
ALT3

—

GPIO[54]

CS2

—
—

FAULT[1]

GPIO[55]

CS3

F[1]

CS4

GPIO[56]

CS2

—

CS5

GPIO[57]

X[0]

TXD

—

GPIO[58]

A[0]

—
—

GPIO[59]

B[0]

—
—

GPIO[60]

X[1]

—
—

RXD

SIUL

DSPI_0

—
—

FlexPWM_0

SIUL

DSPI_1

FCU_0

DSPI_0

SIUL

DSPI_1

—

DSPI_0

SIUL

FlexPWM_0

LIN_1

—

SIUL

FlexPWM_0

—
—

SIUL

FlexPWM_0

—
—

SIUL

FlexPWM_0

—
—

LIN_1

I/O

O
—
—

I/O

O

O

O

I/O

O
—

O

I/O

O

O
—

I/O

O
—
—

I/O

O
—
—

I/O

O
—
—

Slow Medium — 23

I

Slow Medium 17 26

Slow Medium 14 21

Slow Medium 8 15

Slow Medium — 53

Slow Medium — 54

Slow Medium 45 70

I

D[13] PCR[61]

D[14] PCR[62]

ALT0
ALT1
ALT2
ALT3

ALT0
ALT1
ALT2
ALT3

GPIO[61]

A[1]

—
—

GPIO[62]

B[1]

—
—

SIUL

FlexPWM_0

—
—

SIUL

FlexPWM_0

—
—

I/O

O
—
—

I/O

O
—
—

Slow Medium 44 67

Slow Medium 46 73

Doc ID 16912 Rev 5 85/936

Signal Description RM0046

Table 6. Pin muxing (continued)

Port

pin

PCR

register

Alternate

function

(2)

(1),

Functions Peripheral

(3)

I/O
direc­tion

Pad speed

(4)

SRC = 0 SRC = 1 64-pin 100-pin

(5)

Pin

D[15] PCR[63]

E[1] PCR[65]

E[2] PCR[66]

E[3] PCR[67]

ALT0
ALT1
ALT2
ALT3

—
—

ALT0
ALT1
ALT2
ALT3

—

ALT0
ALT1
ALT2
ALT3

—

ALT0
ALT1
ALT2
ALT3

—

GPIO[63]

—
—
—

AN[10]

emu. AN[4]

GPIO[65]

—
—
—

AN[4]

GPIO[66]

—
—
—

AN[5]

GPIO[67]

—
—
—

AN[6]

SIUL

—
—
—

ADC_0

emu. ADC_1

Port E (16-bit)

SIUL

—
—
—

ADC_0

SIUL

—
—
—

ADC_0

SIUL

—
—
—

ADC_0

Input only — — — 41

(6)

Input only — — 18 27

Input only — — 23 32

Input only — — 30 42

E[4] PCR[68]

E[5] PCR[69]

ALT0
ALT1
ALT2
ALT3

—

ALT0
ALT1
ALT2
ALT3

—

GPIO[68]

—
—
—

AN[7]

GPIO[69]

—
—
—

AN[8]

SIUL

—
—
—

ADC_0

SIUL

—
—
—

ADC_0

Input only — — — 44

Input only — — — 43

86/936 Doc ID 16912 Rev 5

RM0046 Signal Description

Table 6. Pin muxing (continued)

Port

pin

PCR

register

Alternate

function

(2)

(1),

Functions Peripheral

(3)

I/O
direc­tion

Pad speed

(4)

SRC = 0 SRC = 1 64-pin 100-pin

(5)

Pin

ALT0
ALT1

E[6] PCR[70]

ALT2
ALT3

—

ALT0
ALT1

E[7] PCR[71]

ALT2
ALT3

—

1. ALT0 is the primary (default) function for each port after reset.

2. Alternate functions are chosen by setting the values of the PCR.PA bitfields inside the SIU module. PCR.PA = 00  ALT0;
PCR.PA = 01  ALT1; PCR.PA = 10  ALT2; PCR.PA = 11  ALT3. This is intended to select the output functions; to
use one of the input functions, the PCR.IBE bit must be written to ‘1’, regardless of the values selected in the PCR.PA
bitfields. For this reason, the value corresponding to an input only function is reported as “—”.

3. Module included on the MCU.

4. Multiple inputs are routed to all respective modules internally. The input of some modules must be configured by setting the
values of the PSMIO.PADSELx bitfields inside the SIUL module.

5. Programmable via the SRC (Slew Rate Control) bits in the respective Pad Configuration Register.

6. ADC0.AN emulates ADC1.AN. This feature is used to provide software compatibility between SPC560P40/34 and
SPC560P50. Refer to ADC chapter of reference manual for more details.

GPIO[70]

—
—
—

AN[9]

GPIO[71]

—
—
—

AN[10]

SIUL

—
—
—

ADC_0

SIUL

—
—
—

ADC_0

Input only — — — 45

Input only — — — 41

Doc ID 16912 Rev 5 87/936

Signal Description RM0046

External pins

PWMA0
PWMB0
PWMA1
PWMB1
PWMA2
PWMB2
PWMA3
PWMB3

Master reload

FAULT0
FAULT1

OUT_TRIG0_0
OUT_TRIG0_1
OUT_TRIG0_2
OUT_TRIG0_3
OUT_TRIG1_0
OUT_TRIG1_1
OUT_TRIG1_2
OUT_TRIG1_3

PWMX0
PWMX1
PWMX2
PWMX3

FlexPWM

EXT_FORCE

CLOCK

EXT_SYNC

PWM_REL
PWM_ODD_0
PWM_ODD_1
PWM_ODD_2
PWM_ODD_3
PWM_EVEN_0
PWM_EVEN_1
PWM_EVEN_2

TRIGGER_0

RPWM_0
RPWM_1

ADC_CMD_0

NEXT_CMD_0

FIFO_0

TRIGGER_1

ADC_CMD_1

NEXT_CMD_1

FIFO_1

EXT_IN

EXT_TRG

CTU

PWM_EVEN_3

RPWM_2
RPWM_3

ETMR0_IN

ETIMER0_TRG
ETIMER1_TRG

AUX_0
AUX_1
AUX_2

T0
T1
T2
T3
T4
T5

eTimer0

External pins

DSPI1

SCK

ADC0

(ipp_ind_injection_trg)

External pins

CTU/ADC

IP Interface

External pins

3.4 CTU / ADC / FlexPWM / eTimer connections

Figure 8 shows the interconnections between the CTU, ADC, FlexPWM, and eTimer.

Figure 8. CTU / ADC / FlexPWM / eTimer connections

Table 7. CTU / ADC / FlexPWM / eTimer connections

Source module

(Signal)

Target module

(Signal)

Comment

PWM (Master Reload) CTU (PWM Reload) From PWM sub-module 0

PWM (OUT_TRIG0_0) CTU (PWM_ODD_0) OUT_TRIG0 sub-module 0

PWM (OUT_TRIG1_0) CTU (PWM_EVEN_0) OUT_TRIG1 sub-module 0

PWM (PWMX0) CTU (PWM_REAL_0) —

PWM (OUT_TRIG0_1) CTU (PWM_ODD_1) OUT_TRIG0 sub-module 1

PWM (OUT_TRIG1_1) CTU (PWM_EVEN_1) OUT_TRIG1 sub-module 1

PWM (PWMX1) CTU (PWM_REAL_1) —

PWM (OUT_TRIG0_2) CTU (PWM_ODD_2) OUT_TRIG0 sub-module 2

PWM (OUT_TRIG1_2) CTU (PWM_EVEN_2) OUT_TRIG1 sub-module 2

PWM (PWMX2) CTU (PWM_REAL_2) —

88/936 Doc ID 16912 Rev 5

RM0046 Signal Description

Table 7. CTU / ADC / FlexPWM / eTimer connections (continued)

Source module

(Signal)

PWM (OUT_TRIG0_3) CTU (PWM_ODD_3) OUT_TRIG0 sub-module 3

PWM (OUT_TRIG1_3) CTU (PWM_EVEN_3) OUT_TRIG1 sub-module 3

PWM (PWMX3) CTU (PWM_REAL_3) —

PWM (PWMA0) SIU lite —

PWM (PWMB0) SIU lite —

PWM (PWMX1) SIU lite —

PWM (PWMA1) SIU lite —

PWM (PWMB1) SIU lite —

PWM (PWMX2) SIU lite —

PWM (PWMA2) SIU lite —

PWM (PWMB2) SIU lite —

PWM (PWMX3) SIU lite —

PWM (PWMA3) SIU lite —

PWM (PWMB3) SIU lite —

PWM (PWMX3) SIU lite —

eTimer_0 (T1) PWM (EXT_FORCE) —

eTimer_0 (T2) CTU (ETMR0_IN) —

eTimer_0 (T5) ADC_0

CTU (ETIMER0_TRG) eTimer_0 (AUX_0) —

CTU (ETIMER1_TRG) eTimer_0 (AUX_1) —

CTU (TRIGGER_0)

CTU (TRIGGER_1)

CTU (ADC_CMD_0)

CTU (ADC_CMD_1)

CTU (EXT_TGR) SIU lite —

ADC_0 (EOC) CTU (NEXT_CMD_0)

Virtual ADC_1 (EOC)

ADC_0 CTU (FIFO_0) 18-bit signal

Virtual ADC_1

Target module

(Signal)

ADC_0 (through
CTU/ADC IP Interface)

Virtual ADC_1 (through
CTU/ADC IP Interface)

ADC_0 (through
CTU/ADC IP Interface)

Virtual ADC_1 (through
CTU/ADC IP Interface)

CTU (NEXT_CMD_1)
(through CTU/ADC IP
Interface)

CTU (FIFO_1) (through
CTU/ADC IP Interface)

Comment

ADC injected conversion request signal (for non CTU mode of
operation)

—

—

16-bit signal

16-bit signal

End Of Conversion should be used as next command request
signal

End Of Conversion should be used as next command request
signal

18-bit signal

Doc ID 16912 Rev 5 89/936

Signal Description RM0046

Table 7. CTU / ADC / FlexPWM / eTimer connections (continued)

Source module

(Signal)

Target module

(Signal)

Comment

SIU lite CTU (EXT_IN)

SIU lite PWM (EXT_SYNC)

The same GPIO pin as used for CTU (EXT_IN) and the PWM
(EXT_SYNC)

The same GPIO pin as used for CTU (EXT_IN) and the PWM
(EXT_SYNC)

SIU lite PWM (FAULT0) —

SIU lite PWM (FAULT1) —

DSPI_1 (SCK) eTimer_0 (AUX_2) —

90/936 Doc ID 16912 Rev 5

RM0046 Clock Description

4 Clock Description

This chapter describes the clock architectural implementation for SPC560P40/34.

The following clock related modules are implemented on the SPC560P40/34:

● Clock, Reset, and Mode Handling

– Clock Generation Module (CGM) (see Chapter 5: Clock Generation Module

(MC_CGM))

– Reset Generation Module (RGM) (see Chapter 8: Reset Generation Module

(MC_RGM))

– Mode Entry Module (ME) (see Chapter 6: Mode Entry Module (MC_ME))

● High Frequency Oscillator (XOSC) (see Section 4.7, “XOSC external crystal oscillator)

● High Frequency RC Oscillator (IRC) (see Section 4.6, “IRC 16 MHz internal RC

oscillator (RC_CTL))

● FMPLL (FMPLL_0) (see Section 4.8, “Frequency Modulated Phase Locked Loop

(FMPLL))

● CMU (CMU_0) (see Section 4.9, “Clock Monitor Unit (CMU))

● Periodic Interrupt Timer (PIT) (see 30, “Periodic Interrupt Timer (PIT))

● System Timer Module (STM_0) (see 31, “System Timer Module (STM))

● Software Watchdog Timer (SWT_0) (see Section 27.3, “Software Watchdog Timer

(SWT))

4.1 Clock architecture

The system and peripheral clocks are generated from three sources:

● IRC—internal RC oscillator clock

● XOSC—oscillator clock

● FMPLL_0 clock output

The clock architecture is shown in Figure 9, Figure 10, and Figure 11.

The frequencies shown in Figure 9 represent only one possible setting.

Note: MC_PLL_CLK and SP_PLL_CLK are SYS_CLK.

Doc ID 16912 Rev 5 91/936

Clock Description RM0046

PHI_PCS

PHI

FMPLL_0

64 MHz

CMU_0

 1,  2,  3, ...  16

Clock Out Divider

MC_PLL Divider

CMU_PLL Divider

SP_PLL Divider

[0]

[2]

[4]

[5]

[8]

AUX Clock Selector 0

AUX Clock Selector 1

[0]

[2]

[4]

[5]

[8]

System Clock Selector 0

RC Oscillator

(IRC)

Oscillator

(XOSC40)

N.C.

IRC_CLK

16 MHz

SYS_CLK

64 MHz—50%

IRC_CLK

16 MHz

XOSC_CLK

8 MHz—50%

Clockout

30/32 MHz

 1,  2,  4,  8

Clock Out Selector

[0]

[1]

[2]

[3]

 1,  2,  3, ...  16

 1,  2,  3, ...  16

[0]

[2]

[4]

[5]

[8]

AUX Clock Selector 2

XOSC_CLK
8 MHz—50%

FMPLL_0_PCS_CLK

FMPLL_0_CLK

NOTE: FlexRay protocol clock does not support IRC as a clock source.

FMPLL_0_CLK

XOSC_CLK

IRC_CLK

FMPLL_0_PCS_CLK—64 MHz, 50%

FMPLL_0_CLK—64 MHz, 50%

SYS_CLK = System Clock

N.C.

N.C.

50%

Figure 9. SPC560P40/34 system clock generation

92/936 Doc ID 16912 Rev 5

RM0046 Clock Description

SafetyPort

Protocol Clock

Module Clock

XOSC_CLK
SP_CLK

eTimer_0

FlexPWM

ADC_0

Module Clock

DMA Support

CTU

SYS_CLK
MC_CLK

DSPI_0

DSPI_1

DSPI_2

CTU Trigger Output

CTU Sync Event Input

Legend:

BIU

IPS @ SYS_CLK

BIU

MC_CLK

Module Clock

BIU

MC_CLK

Module Clock
BIU

MC_CLK

Protocol Clock

Module Clock

BIU

Module Clock
BIU

SYS_CLK

Module Clock
BIU

SYS_CLK

Module Clock
BIU

SYS_CLK

SP_CLK

IPS @ MC_CLK

IPS @ MC_CLK

IPS @ MC_CLK

IPS @ SP_CLK

NOTE: MC_CLK and SP_CLK are SYS_CLK

Figure 10. SPC560P40/34 system clock distribution Part A

Doc ID 16912 Rev 5 93/936

Clock Description RM0046

SYS_CLK

SYS_CLK

SYS_CLK

SYS_CLK

SYS_CLK

SYS_CLK

SYS_CLK

IRCOSC_CLK

SYS_CLK

IRCOSC_CLK

XOSC_CLK
SYS_CLK

IPS
SYS_CLK

IPS
SYS_CLK

LINFlex_0

Module clock

BIU

LINFlex_1

Module clock

BIU

DMA Mux

Module clock

BIU

eDMA2

Module clock

BIU

INTC

Module clock

BIU

SWT

Module clock

Protocol clock

BIU

FlexCAN

Module clock

Protocol clock

BIU

FCU

Module clock

Protocol clock

BIU

STM

Module clock

BIU

ECSM

Module clock

BIU

SIUL

Module clock

BIU

SSCM

Module clock

BIU

WKPU

Module clock

BIU

PIT/RTI

Module clock

BIU

Data Flash 0

Code Flash 0

MC Unit

Module clock

BIU

ME
CGM
RGM
PCU
PMU
FMPLL_0
CQM_0
IRCOSC
XOSC

SYS_CLK

SYS_CLK

SYS_CLK

SYS_CLK

SYS_CLK

SYS_CLK

SYS_CLK

SYS_CLK

Platform Flash Controller

Module clock

BIU

Figure 11. SPC560P40/34 system clock distribution Part B

4.2 Available clock domains

4.2.1 FMPLL input reference clock

This section describes the various clock domains available on SPC560P40/34.

The input reference clock for FMPLL_0 is always the external crystal oscillator clock
(XOSC).

94/936 Doc ID 16912 Rev 5

RM0046 Clock Description

4.2.2 Clock selectors

System clock selector 0 for SYS_CLK

The system clock selector 0 selects the clock source for the system clock (SYS_CLK) from
clock signals:

● Internal RC oscillator clock (IRC)

● Progressive output clock of FMPLL_0

● Directly from the oscillator clock (XOSC)

Its behavior is configured via software through ME_x_MC register of the ME module.

When the standard boot from internal flash is selected via the boot configuration pins, the
clock source for the system clock (SYS_CLK) after reset (DRUN mode) is the internal RC
oscillator (IRC).

4.2.3 Auxiliary Clock Selector 0

There is no Auxiliary Clock present on SPC560P40/34 device, but to maintain the software
compatibility, corresponding register in MC_CGM (CGM_AC0_SC) has been implemented
through which user can select any clock source from the given auxiliary clock sources. As
there is no auxiliary clock, all the auxiliary clock sources have been tied to ‘0’.

4.2.4 Auxiliary Clock Selector 1

There is no Auxiliary Clock present on SPC560P40/34 device, but to maintain the software
compatibility, corresponding register in MC_CGM (CGM_AC1_SC) has been implemented
through which user can select any clock source from the given auxiliary clock sources. As
there is no auxiliary clock, all the auxiliary clock sources have been tied to ‘0’.

4.2.5 Auxiliary Clock Selector 2

There is no Auxiliary Clock present on SPC560P40/34 device, but to maintain the software
compatibility, corresponding register in MC_CGM (CGM_AC2_SC) has been implemented
through which user can select any clock source from the given auxiliary clock sources. As
there is no auxiliary clock, all the auxiliary clock sources have been tied to ‘0’.

4.2.6 Auxiliary clock dividers

As there is no auxiliary clock present on SPC560P40/34, there is no point in having the
auxiliary clock dividers. To maintain the software compatibility, one divider corresponding to
every auxiliary clock has been implemented. Corresponding registers have been
implemented in MC_CGM which can be accessed by user but have no impact in device.
These registers are CGM_AC0_DC0, CGM_AC1_DC0, and CGM_AC2_DC0

4.2.7 External clock divider

The output clock divider provides a nominal 50% duty cycle clock and allows the selected
output clock source to be divided with these divide options:

● ÷1, ÷2, ÷4, ÷8

Doc ID 16912 Rev 5 95/936

Clock Description RM0046

4.3 Alternate module clock domains

This section lists the different clock domains for each module. If not otherwise noted, all
modules on the SPC560P40/34 device are clocked on the SYS_CLK.

4.3.1 FlexCAN clock domains

The FlexCAN modules have two distinct software controlled clock domains. One of the clock
domains is always derived from the system clock. This clock domain includes the message
buffer logic. The source for the second clock domain can be either the system clock
(SYS_CLK) or a direct feed from the oscillator pin XOSC_CLK. The logic in the second
clock domain controls the CAN interface pins. The CLK_SRC bit in the FlexCAN CTRL
register selects between the system clock and the oscillator clock as the clock source for the
second domain. Selecting the oscillator as the clock source ensures very low jitter on the
CAN bus. System software can gate both clocks by writing to the MDIS bit in the FlexCAN
MCR. Figure 262 shows the two clock domains in the FlexCAN modules.

Refer to 22, “FlexCAN for more information on the FlexCAN modules.

4.3.2 SWT clock domains

The SWT module has two distinct clock domains. The first clock domain (Module Clock) is
always supplied from the SYS_CLK. This clock domain includes the register interface.

The source for the second clock domain (Protocol Clock) is always the IRC generated by the
internal RC oscillator.

4.3.3 Cross Triggering Unit (CTU) clock domains

The CTU module has two distinct clock domains. The first clock domain (Module Clock) is
supplied from the SYS_CLK. This clock domain includes the Command Buffer logic.

The source for the second clock domain (Protocol Clock) is the MC_PLL_CLK. The logic in
the Protocol Clock domain controls the CTU interface pins to the eTimer module and the
ADC module.

4.3.4 Peripherals behind the IPS bus clock sync bridge

FlexPWM clock domain

The FlexPWM module has only one clock domain. The FlexPWM module is clocked from
the MC_PLL_CLK. Therefore, it is placed behind the IPS bus clock sync bridge.

eTimer_0 clock domain

The eTimer_0 module has only one clock domain. The eTimer_0 module is clocked from the
MC_PLL_CLK. Therefore, it is placed behind the IPS bus clock sync bridge.

ADC_0 clock domain

The ADC_0 module has only one clock domain. The ADC_0 module is clocked from the
MC_PLL_CLK. Therefore, it is placed behind the IPS bus clock sync bridge.

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RM0046 Clock Description

Safety Port clock domains

The Safety Port module has two distinct software-controlled clock domains. The first clock
domain (Module Clock) is always supplied from the SP_PLL_CLK. The source for the
second clock domain (Protocol Clock) can either be the SP_PLL_CLK or the XOSC_CLK.

The user must ensure that the frequency of the first clock domain (Module Clock) clocked
from the MC_PLL_CLK is always the same or greater than the clock selected for the second
clock domain (Protocol Clock).

4.4 Clock behavior in STOP and HALT mode

In this section the term “resume” is used to describe the transition from STOP and HALT
mode back to a RUN mode.

The SPC560P40/34 supports the STOP and the HALT modes. These two modes allow to
put the device into a power saving mode with the configuration options defined in the ME
module.

The following constraints are applied on SPC560P40/34 to guarantee that in all modes of
operation a resume from STOP or HALT mode is always possible without the need to reset:

● STOP and HALT mode:

– SIUL clock is not gateable

– SIUL filter for external interrupt capable pins is always clocked with IRC

– Resume via interrupt that can be generated by any peripheral that clock is not

gated

– Resume via NMI

configuration that could block resume afterwards)

● STOP mode:

– IRC can NOT be switched off

– The System Clock Selector 0 is switched to the IRC and therefore the SYS_CLK is

feed by the IRC signal

– Resume via external interrupt pin is always possible (if not masked)

● HALT mode:

– The output of the System Clock Selector 0 can only be switched to a running clock

input

– Resume via external interrupt pin is always possible (if not masked) and IRC is not

switched off

pin is always possible if once enabled after reset (no software

4.5 System clock functional safety

This section shows the SPC560P40/34 modules used to detect clock failures:

● The Clock Monitoring Unit (CMU_0) monitors the clock frequency of the FMPLL_0 and

the XOSC signal against the IRC and provides clock out of range information about the
monitored clock signals.

● FMPLL_0 provides a signal that indicates a loss of lock. Each loss of lock signal is sent

to the CGM module.

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Clock Description RM0046

Upon the detection of one of the above mentioned failures, the SPC560P40/34 device either
asserts a reset, generates an interrupt, or sends the device into the SAFE state.

The reaction to each of the clock failures and system parameters (like active clocks and
SYS_CLK clock source) that become active in SAFE state are under software control and
can be configured in the ME module.

4.6 IRC 16 MHz internal RC oscillator (RC_CTL)

The IRC output frequency can be trimmed using RCTRIM bits. After a power-on reset, the
IRC is trimmed using a factory test value stored in test flash memory. However, after a
power-on reset the test flash memory value is not visible at RC_CTL[RCTRIM], and this field
shows a value of zero. Therefore, be aware that the RC_CTL[RCTRIM] field does not reflect
the current trim value until you have written to it. Pay particular attention to this feature when
you initiate a read-modify-write operation on RC_CTL, because a RCTRIM value of zero
may be unintentionally written back and this may alter the IRC frequency. In this case, you
should calibrate the IRC using the CMU.

In this oscillator, two's complement trimming method is implemented. So the trimming code
increases from -32 to 31. As the trimming code increases, the internal time constant
increases and frequency reduces. Please refer to device datasheet for average frequency
variation of the trimming step.

Figure 12. RC Control register (RC_CTL)

Address:

Table 8. RC_CTL field descriptions

0xC3FE_0060
(Base + 0x0000)

0123456789101112131415

R00000000 00

W

Reset0000000000000000

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

R00000000 00000000

W

Reset0000000000000000

Field Description

RCTRIM[5:0] Main RC trimming bits

Access: Supervisor read/write; User read-

RCTRIM[5:0]

4.7 XOSC external crystal oscillator

The external crystal oscillator (XOSC) operates in the range of 4 MHz to 40 MHz. The
XOSC digital interface contains the control and status registers accessible for the external
crystal oscillator.

only

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RM0046 Clock Description

Main features are:

● Oscillator clock available interrupt

● Oscillator bypass mode

4.7.1 Functional description

The crystal oscillator circuit includes an internal oscillator driver and an external crystal
circuitry. The XOSC provides an output clock to the PLL or it is used as a reference clock to
specific modules depending on system needs.

The crystal oscillator can be controlled by the ME:

● Control by ME module. The OSCON bit of the ME_xxx_MCRs controls the powerdown

of oscillator based on the current device mode while S_OSC of ME_GS register
provides the oscillator clock available status.

After system reset, the oscillator is put to power down state and software has to switch on
when required. Whenever the crystal oscillator is switched on from off state, OSCCNT
counter starts and when it reaches the value EOCV[7:0] × 512, oscillator clock is made
available to the system. Also an interrupt pending bit I_OSC of OSC_CTL register is set. An
interrupt will be generated if the interrupt mask bit M_OSC is set.

The oscillator circuit can be bypassed by setting OSC_CTL[OSCBYP]. This bit can only be
set by the software. System reset is needed to reset this bit. In this bypass mode, the output
clock has the same polarity as external clock applied on EXTAL pin and the oscillator status
is forced to ‘1’. The bypass configuration is independent of the powerdown mode of the
oscillator.

Ta bl e 9 shows the truth table of different configurations of oscillator.

Table 9. Crystal oscillator truth table

ENABLE BYP XTALIN EXTAL CK_OSCM XOSC Mode

00

x 1 x Ext clock EXTAL Bypass, XOSC disabled

1 0 Crystal Crystal EXTAL Normal, XOSC enabled

No crystal,

High Z

No crystal,

High Z

0 Power down, IDDQ

4.7.2 Register description

Table 10. OSC_CTL memory map

Offset from

OSC_CTL_BASE

(0xC3FE_0000)

0x0000 OSC_CTL—Oscillator control register R/W 0x0080_0000 on page 4-99

0x0004–0x000F Reserved

Register

Access

Reset value Location

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Clock Description RM0046

Figure 13. Crystal Oscillator Control register (OSC_CTL)

Address:

0xC3FE_0000

Access: Supervisor read/write; User read-

(Base + 0x0000)

0123456789101112131415

W

R

OSC
BYP

0000000

EOCV[7:0]

Reset0000000010000000

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

I_

OSC

w1c

0000000

W

R

0000000

M_

OSC

Reset0000000000000000

Table 11. OSC_CTL field descriptions

Field Description

Crystal Oscillator bypass
This bit specifies whether the oscillator should be bypassed or not. Software can only set this bit.

OSCBYP

System reset is needed to reset this bit.
0: Oscillator output is used as root clock.
1: EXTAL is used as root clock.

End of Count Value
These bits specify the end of count value to be used for comparison by the oscillator stabilization

counter OSCCNT after reset or whenever it is switched on from the off state. This counting period

EOCV[7:0]

ensures that external oscillator clock signal is stable before it can be selected by the system. When
oscillator counter reaches the value EOCV[7:0]*512, oscillator available interrupt request is
generated. The reset value of this field depends on the device specification. The OSCCNT counter
will be kept under reset if oscillator bypass mode is selected.

only

Crystal oscillator clock interrupt mask

M_OSC

0: Crystal oscillator clock interrupt masked
1: Crystal oscillator clock interrupt enabled

Crystal oscillator clock interrupt
This bit is set by hardware when OSCCNT counter reaches the count value EOCV[7:0]*512. It is

I_OSC

cleared by software by writing 1.
0: No oscillator clock interrupt occurred
1: Oscillator clock interrupt pending

4.8 Frequency Modulated Phase Locked Loop (FMPLL)

4.8.1 Introduction

This section describes the features and functions of the FMPLL module implemented in
SPC560P40/34.

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