ST SPC560D30L3, SPC560D40L3, SPC560D30L1, SPC560D40L1 User Manual

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Features

SPC560D30x SPC560D40x

32-bit MCU family built on the Power Architecture

for automotive body electronics applications

Preliminary data

■ High-performance up to 48 MHz e200z0h CPU

– 32-bit Power Architecture

technology CPU

– Variable length encoding (VLE)

■ Memory

– Up to 256 KB Code Flash with ECC – Up to 64 (4x16) KB Data Flash with ECC – Up to 16 KB SRAM with ECC

■ Interrupts

– 16 priority levels – Non-maskable interrupt (NMI) – Up to 38 external interrupts incl. 18 wakeup

lines

■ 16-channel eDMA

■ GPIOs: 45 (LQFP64), 79 (LQFP100)

■ Timer units

– 4-channel 32-bit periodic interrupt timers – 4-channel 32-bit system timer module – System watchdog timer – 32 bit real-time clock timer

■ 16-bit counter time-triggered I/Os

– Up to 28 channels with PWM/MC/IC/OC – 5 independent counters – 27 ch. with ADC trigger capability

■ 12-bit analog-to-digital converter (ADC) with up

to 33 channels – Up to 61 channels via external multiplexing – Individual conversion registers – Cross triggering unit (CTU)

■ Dedicated diagnostic module for lighting

– Advanced PWM generation – Time-triggered diagnostics – PWM-synchronized ADC measurements

LQFP100 (14 x 14 x 1.4 mm)

■ Communications interfaces

LQFP64 (10 x 10 x 1.4 mm)

– 1 FlexCAN interface (2.0B active) with

32 message buffers – 3 LINFlex/UART, 1 with DMA capability –2 DSPI

■ Clock generation

– 4 to 16 MHz fast external crystal oscillator – 16 MHz fast internal RC oscillator – 128 kHz slow internal RC oscillator – Software-controlled FMPLL – Clock monitoring unit

■ Exhaustive debugging capability

– Nexus1 on all packages – Nexus2+ available on emulation device

(SPC560B64B2-ENG)

■ On-chip CAN/UART bootstrap loader

■ Low power capabilities

– Several low power mode configurations – Ultra-low power standby with RTC,SRAM

and CAN monitoring – Fast wakeup schemes

■ Single 5 V or 3.3 V supply

■ Operates in ambient temperature range of

-40 to 125 °C

Table 1. Device summary

Part number

Package

LQFP100 SPC560D30L3 SPC560D40L3

LQFP64 SPC560D30L1 SPC560D40L1

128 Kbyte code

Flash

256 Kbyte code

Flash

December 2011 Doc ID 16315 Rev 5 1/82

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

www.st.com

Contents SPC560D30x, SPC560D40x

Contents

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.1 Document overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3 Package pinouts and signal descriptions . . . . . . . . . . . . . . . . . . . . . . . 11

3.1 Package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3.2 Pad configuration during reset phases . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3.3 Voltage supply pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3.4 Pad types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3.5 System pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3.6 Functional ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

4.2 Parameter classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

4.3 NVUSRO register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

4.3.1 NVUSRO[PAD3V5V] field description . . . . . . . . . . . . . . . . . . . . . . . . . . 27

4.3.2 NVUSRO[OSCILLATOR_MARGIN] field description . . . . . . . . . . . . . . . 27

4.3.3 NVUSRO[WATCHDOG_EN] field description . . . . . . . . . . . . . . . . . . . . 27

4.4 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

4.5 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

4.6 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

4.6.1 Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

4.6.2 Power considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

4.7 I/O pad electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

4.7.1 I/O pad types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

4.7.2 I/O input DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

4.7.3 I/O output DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

4.7.4 Output pin transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

4.7.5 I/O pad current specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

4.8 RESET electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

2/82 Doc ID 16315 Rev 5

SPC560D30x, SPC560D40x Contents

4.9 Power management electrical characteristics . . . . . . . . . . . . . . . . . . . . . 42

4.9.1 Voltage regulator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . 42

4.9.2 Low voltage detector electrical characteristics . . . . . . . . . . . . . . . . . . . . 45

4.10 Power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

4.11 Flash memory electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 47

4.11.1 Program/Erase characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

4.11.2 Flash power supply DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 49

4.11.3 Start-up/Switch-off timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

4.12 Electromagnetic compatibility (EMC) characteristics . . . . . . . . . . . . . . . . 50

4.12.1 Designing hardened software to avoid noise problems . . . . . . . . . . . . . 50

4.12.2 Electromagnetic interference (EMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

4.12.3 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 51

4.13 Fast external crystal oscillator (4 to 16 MHz) electrical characteristics . . 52

4.14 FMPLL electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

4.15 Fast internal RC oscillator (16 MHz) electrical characteristics . . . . . . . . . 56

4.16 Slow internal RC oscillator (128 kHz) electrical characteristics . . . . . . . . 57

4.17 ADC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

4.17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

4.17.2 Input impedance and ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

4.17.3 ADC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

4.18 On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

4.18.1 Current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

4.18.2 DSPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

4.18.3 JTAG characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

5 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

5.1 ECOPACK

5.2 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

5.2.1 LQFP100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

5.2.2 LQFP64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

® . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

6 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Appendix A Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Doc ID 16315 Rev 5 3/82

List of tables SPC560D30x, SPC560D40x

List of tables

Table 2. SPC560D30, SPC560D40 device comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Table 3. SPC560D30, SPC560D40 series block summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 4. Voltage supply pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 5. System pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 6. Functional port pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 7. Parameter classifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 8. PAD3V5V field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 9. OSCILLATOR_MARGIN field description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 10. WATCHDOG_EN field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 11. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 12. Recommended operating conditions (3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 13. Recommended operating conditions (5.0 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 14. LQFP thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 15. I/O input DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 16. I/O pull-up/pull-down DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 17. SLOW configuration output buffer electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 18. MEDIUM configuration output buffer electrical characteristics . . . . . . . . . . . . . . . . . . . . . . 35

Table 19. Output pin transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 20. I/O supply segment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 21. I/O consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 22. I/O weight . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 23. Reset electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Table 24. Voltage regulator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Table 25. Low voltage detector electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 26. Power consumption on VDD_BV and VDD_HV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 27. Program and erase specifications (code flash). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Table 28. Program and erase specifications (data flash) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Table 29. Flash module life. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Table 30. Flash memory read access timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 31. Flash power supply DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 32. Start-up time/Switch-off time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 33. EMI radiated emission measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Table 34. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Table 35. Latch-up results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Table 36. Crystal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Table 37. Fast external crystal oscillator (4 to 16 MHz) electrical characteristics. . . . . . . . . . . . . . . . 54

Table 38. FMPLL electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Table 39. Fast internal RC oscillator (16 MHz) electrical characteristics . . . . . . . . . . . . . . . . . . . . . . 56

Table 40. Slow internal RC oscillator (128 kHz) electrical characteristics . . . . . . . . . . . . . . . . . . . . . 57

Table 41. ADC input leakage current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Table 42. ADC conversion characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Table 43. On-chip peripherals current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Table 44. DSPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Table 45. JTAG characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Table 46. LQFP100 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Table 47. LQFP64 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Table 48. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Table 49. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

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SPC560D30x, SPC560D40x List of figures

List of figures

Figure 1. SPC560D30, SPC560D40 series block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 2. LQFP100 pin configuration (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 3. LQFP64 pin configuration (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 4. Input DC electrical characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 5. Start-up reset requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Figure 6. Noise filtering on reset signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Figure 7. Voltage regulator capacitance connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Figure 8. Low voltage detector vs reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Figure 9. Crystal oscillator and resonator connection scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Figure 10. Fast external crystal oscillator (4 to 16 MHz) timing diagram . . . . . . . . . . . . . . . . . . . . . . . 54

Figure 11. ADC characteristics and error definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Figure 12. Input equivalent circuit (precise channels) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Figure 13. Input equivalent circuit (extended channels) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Figure 14. Transient behavior during sampling phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Figure 15. Spectral representation of input signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Figure 16. DSPI classic SPI timing – master, CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Figure 17. DSPI classic SPI timing – master, CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Figure 18. DSPI classic SPI timing – slave, CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Figure 19. DSPI classic SPI timing – slave, CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Figure 20. DSPI modified transfer format timing – master, CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . 70

Figure 21. DSPI modified transfer format timing – master, CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . 70

Figure 22. DSPI modified transfer format timing – slave, CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Figure 23. DSPI modified transfer format timing – slave, CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Figure 24. Timing diagram – JTAG boundary scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Figure 25. LQFP100 mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Figure 26. LQFP64 mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Figure 27. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Doc ID 16315 Rev 5 5/82

Introduction SPC560D30x, SPC560D40x

1 Introduction

1.1 Document overview

This document describes the device features and highlights the important electrical and physical characteristics.

1.2 Description

These 32-bit automotive microcontrollers are a family of system-on-chip (SoC) devices designed to be central to the development of the next wave of central vehicle body controller, smart junction box, front module, peripheral body, door control and seat control applications.

This family is one of a series of next-generation integrated automotive microcontrollers based on the Power Architecture technology and designed specifically for embedded applications.

The advanced and cost-efficient e200z0h host processor core of this automotive controller family complies with the Power Architecture technology and only implements the VLE (variable-length encoding) APU (auxiliary processing unit), providing improved code density. It operates at speeds of up to 48 MHz and offers high performance processing optimized for low power consumption. It capitalizes on the available development infrastructure of current Power Architecture devices and is supported with software drivers, operating systems and configuration code to assist with the user’s implementations.

The device platform has a single level of memory hierarchy and can support a wide range of on-chip static random access memory (SRAM) and internal flash memory.

Feature

(2)

(3)

(4)

Device

SPC560D30L1 SPC560D30L3 SPC560D40L1 SPC560D40L3

(1)

14 ch, 16-bit 28 ch, 16-bit 14 ch, 16-bit 28 ch, 16-bit

2ch 5ch 2ch 5ch

—9ch—9ch

7ch 7ch 7ch 7ch

Table 2. SPC560D30, SPC560D40 device comparison

CPU e200z0h

Execution speed Static – up to 48 MHz

Code flash memory 128 KB 256 KB

Data flash memory 64 KB (4 × 16 KB)

SRAM 12 KB 16 KB

eDMA 16 ch

ADC (12-bit) 16 ch 33 ch 16 ch 33 ch

CTU 16 ch

Total timer I/O eMIOS

– Type X

– Type Y

– Type G

6/82 Doc ID 16315 Rev 5

SPC560D30x, SPC560D40x Introduction

Table 2. SPC560D30, SPC560D40 device comparison (continued)

Device

Feature

SPC560D30L1 SPC560D30L3 SPC560D40L1 SPC560D40L3

(6)

(5)

4ch 7ch 4ch 7ch

45 79 45 79

– Type H

SCI (LINFlex) 3

SPI (DSPI) 2

CAN (FlexCAN) 1

GPIO

Debug JTAG

Package LQFP64 LQFP100 LQFP64 LQFP100

1. Refer to eMIOS chapter of device reference manual for information on the channel configuration and functions.

2. Type X = MC + MCB + OPWMT + OPWMB + OPWFMB + SAIC + SAOC.

3. Type Y = OPWMT + OPWMB + SAIC + SAOC.

4. Type G = MCB + IPWM + IPM + DAOC + OPWMT + OPWMB + OPWFMB + OPWMCB + SAIC + SAOC.

5. Type H = IPWM + IPM + DAOC + OPWMT + OPWMB + SAIC + SAOC.

6. I/O count based on multiplexing with peripherals.

Doc ID 16315 Rev 5 7/82

Block diagram SPC560D30x, SPC560D40x

2 Block diagram

Figure 1 shows a top-level block diagram of the SPC560D30, SPC560D40 device series.

Figure 1. SPC560D30, SPC560D40 series block diagram

JTAG Port

NMI

Clocks

Interrupt Request

Request

Nexus 1

Voltage

Regulator

FMPLL

RTC

SIUL

Reset Control

External Interrupt Request

IMUX

GPIO &

Pad Control

JTAG

NMI

SIUL

Interrupt requests

from peripheral

CMU

STM

33 ch.

blocks

SWT

ADC

ECSM

e200z0h

PIT

CTU

INTC

Peripheral Bridge

1 x

eMIOS

Instructions

(Master)

Data

(Master)

eDMA

(Master)

LINFlex

3 x

SRAM 16 KB

SRAM

Controller

64-bit 3 x 3 Crossbar Switch

2 x

DSPI

(Slave)

MC_PCUMC_MEMC_CGMMC_RGM

Code Flash

256 KB

Controller

(Slave)

BAM

1 x

FlexCAN

Data Flash

64 KB

Flash

(Slave)

SSCM

WKPU

Interrupt Request

I/O

Legend:

ADC Analog-to-Digital Converter BAM Boot Assist Module CMU Clock Monitor Unit CTU Cross Triggering Unit DSPI Deserial Serial Peripheral Interface ECSM Error Correction Status Module eDMA Enhanced Direct Memory Access eMIOS Enhanced Modular Input Output System Flash Flash memory FlexCAN Controller Area Network (FlexCAN) FMPLL Frequency-Modulated Phase-Locked Loop IMUX Internal Multiplexer INTC Interrupt Controller JTAG JTAG controller LINFlex Serial Communication Interface (LIN support)

. . .

MC_CGM Clock Generation Module MC_ME Mode Entry Module MC_PCU Power Control Unit MC_RGM Reset Generation Module NMI Non-Maskable Interrupt PIT Periodic Interrupt Timer RTC Real-Time Clock SIUL System Integration Unit Lite SRAM Static Random-Access Memory SSCM System Status Configuration Module STM System Timer Module SWT Software Watchdog Timer WKPU Wakeup Unit XBAR Crossbar switch

8/82 Doc ID 16315 Rev 5

. . .

SPC560D30x, SPC560D40x Block diagram

Ta bl e 3 summarizes the functions of all blocks present in the SPC560D30, SPC560D40

series of microcontrollers. Please note that the presence and number of blocks varies by device and package.

Table 3. SPC560D30, SPC560D40 series block summary

Analog-to-digital converter (ADC) Multi-channel, 12-bit analog-to digital-converter

Block Function

Boot assist module (BAM)

Clock generation module (MC_CGM)

A block of read-only memory containing VLE code which is executed according to the boot mode of the device

Provides logic and control required for the generation of system and peripheral clocks

Clock monitor unit (CMU) Monitors clock source (internal and external) integrity

Cross triggering unit (CTU)

Enables synchronization of ADC conversions with a timer event from the eMIOS or from the PIT

Supports simultaneous connections between two master ports and three slave

Crossbar switch (XBAR)

ports. The crossbar supports a 32-bit address bus width and a 64-bit data bus width.

Deserial serial peripheral interface (DSPI)

Enhanced direct memory access (eDMA)

Enhanced modular input output system (eMIOS)

Provides a synchronous serial interface for communication with external devices

Performs complex data transfers with minimal intervention from a host processor via “n” programmable channels.

Provides the functionality to generate or measure events

Provides a myriad of miscellaneous control functions for the device including Error correction status module (ECSM)

program-visible information about configuration and revision levels, a reset

status register, wakeup control for exiting sleep modes, and optional features

such as information on memory errors reported by error-correcting codes

Flash memory Provides non-volatile storage for program code, constants and variables

FlexCAN (controller area network)

Supports the standard CAN communications protocol

Frequency-modulated phaselocked loop (FMPLL)

Internal multiplexer (IMUX) SIU subblock

Generates high-speed system clocks and supports programmable frequency

modulation

Allows flexible mapping of peripheral interface on the different pins of the device

Interrupt controller (INTC) Provides priority-based preemptive scheduling of interrupt requests

JTAG controller (JTAGC)

LINFlex controller

Provides the means to test chip functionality and connectivity while remaining

transparent to system logic when not in test mode

Manages a high number of LIN (Local Interconnect Network protocol)

messages efficiently with a minimum of CPU load

Provides a mechanism for controlling the device operational mode and mode

Mode entry module (MC_ME)

transition sequences in all functional states; also manages the power control

unit, reset generation module and clock generation module, and holds the

configuration, control and status registers accessible for applications

Non-maskable interrupt (NMI)

Handles external events that must produce an immediate response, such as

power down detection

Doc ID 16315 Rev 5 9/82

Block diagram SPC560D30x, SPC560D40x

Table 3. SPC560D30, SPC560D40 series block summary (continued)

Block Function

Periodic interrupt timer (PIT) Produces periodic interrupts and triggers

Reduces the overall power consumption by disconnecting parts of the device Power control unit (MC_PCU)

from the power supply via a power switching device; device components are

grouped into sections called “power domains” which are controlled by the PCU

Real-time counter (RTC)

Reset generation module (MC_RGM)

Static random-access memory (SRAM)

Provides a free-running counter and interrupt generation capability that can be

used for timekeeping applications

Centralizes reset sources and manages the device reset sequence of the

device

Provides storage for program code, constants, and variables

Provides control over all the electrical pad controls and up 32 ports with 16 bits System integration unit lite (SIUL)

of bidirectional, general-purpose input and output signals and supports up to 32

external interrupts with trigger event configuration

System status and configuration module (SSCM)

System timer module (STM)

Provides system configuration and status data (such as memory size and

status, device mode and security status), device identification data, debug

status port enable and selection, and bus and peripheral abort enable/disable

Provides a set of output compare events to support AUTOSAR (Automotive

Open System Architecture) and operating system tasks

Software watchdog timer (SWT) Provides protection from runaway code

Supports up to 18 external sources that can generate interrupts or wakeup Wakeup unit (WKPU)

events, of which 1 can cause non-maskable interrupt requests or wakeup

events.

10/82 Doc ID 16315 Rev 5

SPC560D30x, SPC560D40x Package pinouts and signal descriptions

3 Package pinouts and signal descriptions

3.1 Package pinouts

The available LQFP pinouts are provided in the following figures. For pin signal descriptions, please refer to Tab l e 6 .

Figure 2 shows the SPC560D30, SPC560D40 in the LQFP100 package.

Figure 2. LQFP100 pin configuration (top view)

PB[2]

PC[8]

PC[13]

PC[12]

PE[7]

PE[6]

PE[5]

PE[4]

PC[4]

PC[5]

PE[3]

PE[2]

PH[9]

PC[0]

VSS_LV

VDD_LV

VDD_HV

VSS_HV

PC[1]

PH[10]

PA [ 6]

PA [ 5]

PC[2]

PC[3]

PE[12]

PB[3]

PC[9] PC[14] PC[15]

PA [2 ]

PE[0]

PA [1 ] PE[1] PE[8] PE[9]

PE[10]

PA [0 ]

PE[11]

VSS_HV

VDD_HV

VSS_HV

RESET

VSS_LV

VDD_LV

VDD_BV

PC[11] PC[10]

PB[0] PB[1] PC[6]

9998979695949392919089888786858483828180797877

100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

26272829303132333435363738394041424344454647484950

PA [4 ]

PC[7]

PA[15]

PA[14]

PA[13]

PA[12]

VDD_LV

LQFP100

XTAL

VSS_LV

VSS_HV

EXTAL

VDD_HV

PB[9]

PB[8]

PD[0]

PD[1]

PD[2]

PD[3]

PB[10]

PD[4]

PA[11]

PA[10]

PA [ 9]

PA [ 8]

PA [ 7]

VDD_HV

VSS_HV

PA [ 3]

PB[15]

PD[15]

PB[14]

PD[14]

PB[13]

PD[13]

PB[12]

PD[12]

PB[11]

PD[11]

PD[10]

PD[9]

PB[7]

PB[6]

PB[5]

VDD_HV_ADC

VSS_HV_ADC

PD[5]

PB[4]

PD[6]

PD[7]

PD[8]

Figure 3 shows the SPC560D30, SPC560D40 in the LQFP64 package.

Doc ID 16315 Rev 5 11/82

Package pinouts and signal descriptions SPC560D30x, SPC560D40x

Figure 3. LQFP64 pin configuration (top view)

PB[2]

PC[8]

PC[4]

PC[5]

PH[9]

PC[0]

VSS_LV

VDD_LV

VDD_HV

VSS_HV

PC[1]

PH[10]

PA [6 ]

PA [5 ]

PC[2]

PC[3]

PB[3] PC[9]

PA [2 ] PA [1 ] PA [0 ]

VSS_HV

VDD_HV

VSS_HV

RESET

VSS_LV

VDD_LV

VDD_BV

PC[10]

PB[0] PB[1] PC[6]

646362616059585756555453525150

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

171819202122232425

PC[7]

PA[15]

PA[14]

PA [4 ]

LQFP64

PA[13]

PA[12]

VSS_LV

VDD_LV

26272829303132

XTAL

VSS_HV

EXTAL

VDD_HV

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

PB[9]

PB[8]

PB[4]

PB[10]

3.2 Pad configuration during reset phases

All pads have a fixed configuration under reset.

PA [1 1 ] PA [1 0 ] PA [9 ] PA [8 ] PA [7 ] PA [3 ] PB[15] PB[14] PB[13] PB[12] PB[11] PB[7] PB[6] PB[5] VDD_HV_ADC VSS_HV_ADC

During the power-up phase, all pads are forced to tristate.

After power-up phase, all pads are forced to tristate with the following exceptions:

● PA[9] (FAB) is pull-down. Without external strong pull-up the device starts fetching from

flash.

● PA[8] (ABS[0]) is pull-up.

● RESET pad is driven low. This is pull-up only after PHASE2 reset completion.

● JTAG pads (TCK, TMS and TDI) are pull-up whilst TDO remains tristate.

● Precise ADC pads (PB[7:4] and PD[11:0]) are left tristate (no output buffer available).

● Main oscillator pads (EXTAL, XTAL) are tristate.

3.3 Voltage supply pins

Voltage supply pins are used to provide power to the device. Two dedicated pins are used for 1.2 V regulator stabilization.

12/82 Doc ID 16315 Rev 5

SPC560D30x, SPC560D40x Package pinouts and signal descriptions

Table 4. Voltage supply pin descriptions

Pin number

Port pin Function

LQFP64 LQFP100

VDD_HV Digital supply voltage 7, 28, 34, 56 15, 37, 52, 70, 84

VSS_HV Digital ground 6, 8, 26, 33, 55 14, 16, 35, 51, 69, 83

VDD_LV

VSS_LV

1.2V decoupling pins. Decoupling capacitor must be connected between these pins and the nearest V

(1)

pin.

SS_LV

1.2V decoupling pins. Decoupling capacitor must be connected between these pins and the nearest V

(1)

pin.

DD_LV

11, 23, 57 19, 32, 85

10, 24, 58 18, 33, 86

VDD_BV Internal regulator supply voltage 12 20

1. A decoupling capacitor must be placed between each of the three VDD_LV/VSS_LV supply pairs to ensure stable voltage (see the recommended operating conditions in the device datasheet for details).

3.4 Pad types

In the device the following types of pads are available for system pins and functional port pins:

S = Slow

M = Medium

F = Fast

I = Input only with analog feature

J = Input/Output (‘S’ pad) with analog feature

X = Oscillator

(a)

(a) (b)

(a)

3.5 System pins

The system pins are listed in Ta bl e 5 .

a. See the I/O pad electrical characteristics in the device datasheet for details.

b. All medium and fast pads are in slow configuration by default at reset and can be configured as fast or medium

(see the PCR[SRC] description in the device reference manual).

Doc ID 16315 Rev 5 13/82

Package pinouts and signal descriptions SPC560D30x, SPC560D40x

Table 5. System pin descriptions

Port

RESET

Function

Bidirectional reset with Schmitt-Trigger characteristics and noise filter.

Analog output of the oscillator amplifier circuit, when the oscillator is not in bypass

EXTAL

mode. Analog input for the clock generator when the

oscillator is in bypass mode.

(1)

Analog input of the oscillator amplifier circuit.

XTAL

1. Refer to the relevant section of the device datasheet.

Needs to be grounded if oscillator is used in bypass mode.

(1)

3.6 Functional ports

The functional port pins are listed in Ta bl e 6 .

Table 6. Functional port pin descriptions

I/O

direction

Pad

type

RESET

configuration

Pin number

LQFP64 LQFP100

Input, weak

I/O M

pull-up only

917

after PHASE2

I/O X Tristate 27 36

I X Tristate 25 34

Port pin PCR

PA[0] PCR[0]

PA[1] PCR[1]

PA[2] PCR[2]

Alternate

function

AF0 AF1 AF2 AF3

—

AF0 AF1 AF2 AF3

— —

AF0 AF1 AF2 AF3

—

Function Peripheral

(1)

GPIO[0] E0UC[0]

CLKOUT

E0UC[13]

WKPU[19]

(3)

GPIO[1] E0UC[1]

— —

(4)

NMI

WKPU[2]

(3)

GPIO[2] E0UC[2]

—

MA[2]

WKPU[3]

(3)

Por t A

SIUL

eMIOS_0

CGL

eMIOS_0

WKPU

SIUL

eMIOS_0

—

— WKPU WKPU

SIUL

eMIOS_0

—

ADC

WKPU

I/O

direction

(2)

I/O I/O

I/O

I/O I/O

— —

I I

I/O I/O

—

Pin number

Pad

type

RESET

LQFP64 LQFP100

configuration

M Tristate 5 12

S Tristate 4 7

S Tristate 3 5

14/82 Doc ID 16315 Rev 5

SPC560D30x, SPC560D40x Package pinouts and signal descriptions

Table 6. Functional port pin descriptions (continued)

Port pin PCR

PA[3] PCR[3]

PA[4] PCR[4]

PA[5] PCR[5]

PA[6] PCR[6]

Alternate

function

AF0 AF1 AF2 AF3

— —

AF0 AF1 AF2 AF3

—

AF0 AF1 AF2 AF3

—

Function Peripheral

(1)

GPIO[3] E0UC[3]

—

CS4_0

EIRQ[0]

ADC1_S[0]

GPIO[4] E0UC[4]

—

CS0_1

WKPU[9]

(3)

GPIO[5] E0UC[5]

— —

GPIO[6] E0UC[6]

—

CS1_1

EIRQ[1]

SIUL

eMIOS_0

—

DSPI_0

SIUL

ADC

SIUL

eMIOS_0

—

DSPI_1

WKPU

SIUL

eMIOS_0

—

SIUL

eMIOS_0

—

DSPI_1

SIUL

I/O

direction

(2)

I/O I/O

—

I/O

I I

I/O I/O

—

I/O

I/O I/O

— —

I/O I/O

—

I/O

Pin number

Pad

type

RESET

LQFP64 LQFP100

configuration

S Tristate 43 68

S Tristate 20 29

M Tristate 51 79

S Tristate 52 80

PA[7] PCR[7]

PA[8] PCR[8]

PA[9] PCR[9]

AF0 AF1 AF2 AF3

N/A

AF0 AF1 AF2 AF3

N/A

— —

—

(5)

GPIO[7] E0UC[7]

— —

EIRQ[2]

ADC1_S[1]

GPIO[8] E0UC[8]

E0UC[14]

—

EIRQ[3]

ABS[0]

GPIO[9] E0UC[9]

—

CS2_1

FAB

SIUL

eMIOS_0

—

SIUL

ADC

SIUL eMIOS_0 eMIOS_0

— SIUL BAM

SIUL

eMIOS_0

—

DSPI_1

BAM

I/O I/O

— —

I/O I/O

— —

I/O I/O

—

I/O

S Tristate 44 71

I I

Input,

weak pull-

45 72

I I

S Pull-down 46 73

Doc ID 16315 Rev 5 15/82

Package pinouts and signal descriptions SPC560D30x, SPC560D40x

Table 6. Functional port pin descriptions (continued)

Port pin PCR

PA[10] PCR[10]

PA[11] PCR[11]

PA[12] PCR[12]

Alternate

function

AF0 AF1 AF2 AF3

—

AF0 AF1 AF2 AF3

— — —

AF0 AF1 AF2 AF3

— —

Function Peripheral

(1)

GPIO[10] E0UC[10]

—

LIN2TX

ADC1_S[2]

GPIO[11] E0UC[11]

— —

EIRQ[16]

ADC1_S[3]

LIN2RX

GPIO[12]

— — —

EIRQ[17]

SIN_0

SIUL

eMIOS_0

—

LINFlex_2

ADC

SIUL

eMIOS_0

—

— SIUL

ADC

LINFlex_2

SIUL

—

— SIUL

DSPI_0

I/O

direction

(2)

I/O I/O

—

I/O I/O

— —

I I I

I/O

— — —

I I

Pin number

Pad

type

RESET

LQFP64 LQFP100

configuration

S Tristate 47 74

S Tristate 48 75

S Tristate 22 31

PA[13] PCR[13]

PA[14] PCR[14]

PA[15] PCR[15]

PB[0] PCR[16]

AF0 AF1 AF2 AF3

—

AF0 AF1 AF2 AF3

—

AF0 AF1 AF2 AF3

GPIO[13]

SOUT_0

—

CS3_1

GPIO[14]

SCK_0

CS0_0 E0UC[0] EIRQ[4]

GPIO[15]

CS0_0

SCK_0 E0UC[1]

WKPU[10]

GPIO[16]

CAN0TX

—

LIN2TX

(3)

FlexCAN_0

SIUL

DSPI_0

—

DSPI_1

SIUL DSPI_0 DSPI_0

eMIOS_0

SIUL

SIUL DSPI_0 DSPI_0

eMIOS_0

WKPU

Por t B

SIUL

—

LINFlex_2

I/O

—

I/O

I/O I/O I/O I/O

I/O

—

M Tristate 21 30

M Tristate 19 28

M Tristate 18 27

M Tristate 14 23

16/82 Doc ID 16315 Rev 5

SPC560D30x, SPC560D40x Package pinouts and signal descriptions

Table 6. Functional port pin descriptions (continued)

Port pin PCR

PB[1] PCR[17]

PB[2] PCR[18]

PB[3] PCR[19]

PB[4] PCR[20]

PB[5] PCR[21]

PB[6] PCR[22]

PB[7] PCR[23]

Alternate

function

AF0 AF1 AF2 AF3

— —

AF0 AF1 AF2 AF3

— —

AF0 AF1 AF2 AF3

—

AF0 AF1 AF2 AF3

—

AF0 AF1 AF2 AF3

—

AF0 AF1 AF2 AF3

—

Function Peripheral

(1)

GPIO[17]

— —

LIN0RX

WKPU[4]

(3)

CAN0RX

GPIO[18]

LIN0TX

— —

GPIO[19]

— — —

WKPU[11]

(3)

LIN0RX

GPIO[20]

— — —

ADC1_P[0]

GPIO[21]

— — —

ADC1_P[1]

GPIO[22]

— — —

ADC1_P[2]

GPIO[23]

— — —

ADC1_P[3]

SIUL

— —

LINFlex_0

WKPU

FlexCAN_0

SIUL

LINFlex_0

— —

SIUL

— — —

WKPU

LINFlex_0

SIUL

— — —

ADC

SIUL

— — —

ADC

SIUL

— — —

ADC

SIUL

— — —

ADC

I/O

direction

(2)

I/O

— —

I I I

I/O

O — —

I/O

— — —

I I

I — — —

Pin number

Pad

type

RESET

LQFP64 LQFP100

configuration

S Tristate 15 24

M Tristate 64 100

S Tristate 1 1

I Tristate 32 50

I Tristate 35 53

I Tristate 36 54

I Tristate 37 55

Doc ID 16315 Rev 5 17/82

Package pinouts and signal descriptions SPC560D30x, SPC560D40x

Table 6. Functional port pin descriptions (continued)

Port pin PCR

PB[8] PCR[24]

PB[9] PCR[25]

PB[10] PCR[26]

Alternate

function

AF0 AF1 AF2 AF3

— —

AF0 AF1 AF2 AF3

— —

AF0 AF1 AF2 AF3

— —

Function Peripheral

(1)

GPIO[24]

— — —

ADC1_S[4]

WKPU[25]

(3)

GPIO[25]

— — —

ADC1_S[5]

WKPU[26]

(3)

GPIO[26]

— —

— ADC1_S[6] WKPU[8]

(3)

SIUL

— — —

ADC

WKPU

SIUL

— — —

ADC

WKPU

SIUL

— — —

ADC

WKPU

I/O

direction

(2)

I — — —

I/O

— — —

Pin number

Pad

type

RESET

LQFP64 LQFP100

configuration

I Tristate 30 39

I Tristate 29 38

J Tristate 31 40

PB[11] PCR[27]

PB[12] PCR[28]

PB[13] PCR[29]

PB[14] PCR[30]

AF0 AF1 AF2 AF3

—

AF0 AF1 AF2 AF3

—

AF0 AF1 AF2 AF3

—

AF0 AF1 AF2 AF3

—

GPIO[27]

E0UC[3]

—

CS0_0

ADC1_S[12]

GPIO[28]

E0UC[4]

—

CS1_0

ADC1_X[0]

GPIO[29]

E0UC[5]

—

CS2_0

ADC1_X[1]

GPIO[30]

E0UC[6]

—

CS3_0

ADC1_X[2]

SIUL

eMIOS_0

—

DSPI_0

ADC

SIUL

eMIOS_0

—

DSPI_0

ADC

SIUL

eMIOS_0

—

DSPI_0

ADC

SIUL

eMIOS_0

—

DSPI_0

ADC

I/O I/O

—

I/O

I/O I/O

—

I/O I/O

—

I/O I/O

—

J Tristate 38 59

J Tristate 39 61

J Tristate 40 63

J Tristate 41 65

18/82 Doc ID 16315 Rev 5

SPC560D30x, SPC560D40x Package pinouts and signal descriptions

Table 6. Functional port pin descriptions (continued)

Port pin PCR

PB[15] PCR[31]

(6)

PCR[32]

PCR[33]

PC[0]

PC[1]

PC[2] PCR[34]

Alternate

function

AF0 AF1 AF2 AF3

—

AF0 AF1 AF2 AF3

—

Function Peripheral

(1)

GPIO[31]

E0UC[7]

—

CS4_0

ADC1_X[3]

GPIO[32]

—

TDI

—

GPIO[33]

—

TDO

—

GPIO[34]

SCK_1

— —

EIRQ[5]

SIUL

eMIOS_0

—

DSPI_0

ADC

Por t C

SIUL

—

JTAGC

—

SIUL

—

JTAGC

—

SIUL

DSPI_1

— —

SIUL

I/O

direction

(2)

I/O I/O

—

I/O

—

I —

I/O

—

I/O I/O

— —

Pin number

Pad

type

RESET

LQFP64 LQFP100

configuration

J Tristate 42 67

Input,

weak pull-

59 87

F Tristate 54 82

M Tristate 50 78

PC[3] PCR[35]

PC[4] PCR[36]

PC[5] PCR[37]

PC[6] PCR[38]

AF0 AF1 AF2 AF3

—

AF0 AF1 AF2 AF3

— —

AF0 AF1 AF2 AF3

—

AF0 AF1 AF2 AF3

GPIO[35]

CS0_1

MA[0]

—

EIRQ[6]

GPIO[36]

— — —

SIN_1

EIRQ[18]

GPIO[37]

SOUT_1

— —

EIRQ[7]

GPIO[38]

LIN1TX

— —

SIUL

DSPI_1

ADC

—

SIUL

— — —

DSPI_1

SIUL

DSPI_1

— —

SIUL

LINFlex_1

— —

I/O I/O

—

I/O

— — —

I/O

O — —

I/O

O — —

S Tristate 49 77

M Tristate 62 92

I I

M Tristate 61 91

S Tristate 16 25

Doc ID 16315 Rev 5 19/82

Package pinouts and signal descriptions SPC560D30x, SPC560D40x

Table 6. Functional port pin descriptions (continued)

Port pin PCR

PC[7] PCR[39]

PC[8] PCR[40]

PC[9] PCR[41]

PC[10] PCR[42]

Alternate

function

AF0 AF1 AF2 AF3

— —

AF0 AF1 AF2 AF3

— —

AF0 AF1 AF2 AF3

Function Peripheral

(1)

GPIO[39]

— — —

LIN1RX

WKPU[12]

(3)

GPIO[40]

LIN2TX

E0UC[3]

—

GPIO[41]

—

E0UC[7]

—

LIN2RX

WKPU[13]

(3)

GPIO[42]

— —

MA[1]

SIUL

— — —

LINFlex_1

WKPU

SIUL

LINFlex_2

eMIOS_0

—

SIUL

—

eMIOS_0

—

LINFlex_2

WKPU

SIUL

— —

ADC

I/O

direction

(2)

I/O

— — —

I I

I/O

—

I/O

—

I/O

—

I I

I/O

— —

Pin number

Pad

type

RESET

LQFP64 LQFP100

configuration

S Tristate 17 26

S Tristate 63 99

S Tristate 2 2

M Tristate 13 22

PC[11] PCR[43]

PC[12] PCR[44]

PC[13] PCR[45]

PC[14] PCR[46]

AF0 AF1 AF2 AF3

—

AF0 AF1 AF2 AF3

—

AF0 AF1 AF2 AF3

—

GPIO[43]

— —

MA[2]

WKPU[5]

GPIO[44] E0UC[12]

— —

EIRQ[19]

GPIO[45] E0UC[13]

— —

GPIO[46] E0UC[14]

— —

EIRQ[8]

(3)

SIUL

— —

ADC

WKPU

SIUL

eMIOS_0

— —

SIUL

eMIOS_0

— —

SIUL

eMIOS_0

— —

SIUL

I/O

— —

I/O I/O

— —

I/O I/O

— —

I/O I/O

— —

S Tristate — 21

M Tristate — 97

S Tristate — 98

S Tristate — 3

20/82 Doc ID 16315 Rev 5

SPC560D30x, SPC560D40x Package pinouts and signal descriptions

Table 6. Functional port pin descriptions (continued)

Port pin PCR

PC[15] PCR[47]

PD[0] PCR[48]

PD[1] PCR[49]

PD[2] PCR[50]

PD[3] PCR[51]

PD[4] PCR[52]

PD[5] PCR[53]

Alternate

function

AF0 AF1 AF2 AF3

—

AF0 AF1 AF2 AF3

— —

AF0 AF1 AF2 AF3

— —

AF0 AF1 AF2 AF3

—

AF0 AF1 AF2 AF3

—

AF0 AF1 AF2 AF3

—

AF0 AF1 AF2 AF3

—

Function Peripheral

(1)

GPIO[47] E0UC[15]

— —

EIRQ[20]

GPIO[48]

— — —

WKPU[27]

(3)

ADC1_P[4]

GPIO[49]

— — —

WKPU[28]

(3)

ADC1_P[5]

GPIO[50]

— — —

ADC1_P[6]

GPIO[51]

— — —

ADC1_P[7]

GPIO[52]

— — —

ADC1_P[8]

GPIO[53]

— — —

ADC1_P[9]

SIUL

eMIOS_0

— —

SIUL

Por t D

SIUL

— — —

WKPU

ADC

SIUL

— — —

WKPU

ADC

SIUL

— — —

ADC

SIUL

— — —

ADC

SIUL

— — —

ADC

SIUL

— — —

ADC

I/O

direction

(2)

I/O I/O

— —

I — — —

Pin number

Pad

type

RESET

LQFP64 LQFP100

configuration

M Tristate — 4

I Tristate — 41

I Tristate — 42

I Tristate — 43

I Tristate — 44

I Tristate — 45

I Tristate — 46

Doc ID 16315 Rev 5 21/82

Package pinouts and signal descriptions SPC560D30x, SPC560D40x

Table 6. Functional port pin descriptions (continued)

Port pin PCR

PD[6] PCR[54]

PD[7] PCR[55]

PD[8] PCR[56]

PD[9] PCR[57]

Alternate

function

AF0 AF1 AF2 AF3

—

AF0 AF1 AF2 AF3

—

AF0 AF1 AF2 AF3

—

AF0 AF1 AF2 AF3

—

Function Peripheral

(1)

GPIO[54]

— — —

ADC1_P[10]

GPIO[55]

— — —

ADC1_P[11]

GPIO[56]

— — —

ADC1_P[12]

GPIO[57]

— — —

ADC1_P[13]

SIUL

— — —

ADC

SIUL

— — —

ADC

SIUL

— — —

ADC

SIUL

— — —

ADC

I/O

direction

(2)

I — — —

Pin number

Pad

type

RESET

LQFP64 LQFP100

configuration

I Tristate — 47

I Tristate — 48

I Tristate — 49

I Tristate — 56

PD[10] PCR[58]

PD[11] PCR[59]

PD[12] PCR[60]

PD[13] PCR[61]

AF0 AF1 AF2 AF3

—

AF0 AF1 AF2 AF3

—

AF0 AF1 AF2 AF3

—

AF0 AF1 AF2 AF3

—

GPIO[58]

— — —

ADC1_P[14]

GPIO[59]

— — —

ADC1_P[15]

GPIO[60]

CS5_0

E0UC[24]

—

ADC1_S[8]

GPIO[61]

CS0_1

E0UC[25]

—

ADC1_S[9]

SIUL

— — —

ADC

SIUL

— — —

ADC

SIUL

DSPI_0

eMIOS_0

—

ADC

SIUL

DSPI_1

eMIOS_0

—

ADC

— — —

I/O

—

I/O I/O I/O

—

I Tristate — 57

I Tristate — 58

J Tristate — 60

J Tristate — 62

22/82 Doc ID 16315 Rev 5

SPC560D30x, SPC560D40x Package pinouts and signal descriptions

Table 6. Functional port pin descriptions (continued)

Port pin PCR

PD[14] PCR[62]

PD[15] PCR[63]

PE[0] PCR[64]

PE[1] PCR[65]

PE[2] PCR[66]

PE[3] PCR[67]

PE[4] PCR[68]

PE[5] PCR[69]

Alternate

function

AF0 AF1 AF2 AF3

—

AF0 AF1 AF2 AF3

—

AF0 AF1 AF2 AF3

—

AF0 AF1 AF2 AF3

— —

AF0 AF1 AF2 AF3

—

AF0 AF1 AF2 AF3

Function Peripheral

(1)

GPIO[62]

CS1_1

E0UC[26]

—

ADC1_S[10]

GPIO[63]

CS2_1

E0UC[27]

—

ADC1_S[11]

GPIO[64] E0UC[16]

— —

WKPU[6]

(3)

GPIO[65] E0UC[17]

— —

GPIO[66] E0UC[18]

— —

EIRQ[21]

SIN_1

GPIO[67] E0UC[19]

SOUT_1

—

GPIO[68] E0UC[20]

SCK_1

—

EIRQ[9]

GPIO[69] E0UC[21]

CS0_1

MA[2]

SIUL

DSPI_1

eMIOS_0

—

ADC

SIUL

DSPI_1

eMIOS_0

—

ADC

Por t E

SIUL

eMIOS_0

— —

WKPU

SIUL

eMIOS_0

— —

SIUL

eMIOS_0

— —

SIUL

DSPI_1

SIUL

eMIOS_0

DSPI_1

—

SIUL

eMIOS_0

DSPI_1

—

SIUL

eMIOS_0

DSPI_1

ADC

I/O

direction

(2)

I/O

—

I/O

—

I/O I/O

— —

I/O I/O

— —

I/O I/O

— —

I/O I/O

—

I/O I/O I/O

—

I/O I/O I/O

Pin number

Pad

type

RESET

LQFP64 LQFP100

configuration

J Tristate — 64

J Tristate — 66

S Tristate — 6

M Tristate — 8

M Tristate — 89

M Tristate — 90

M Tristate — 93

M Tristate — 94

Doc ID 16315 Rev 5 23/82

Package pinouts and signal descriptions SPC560D30x, SPC560D40x

Table 6. Functional port pin descriptions (continued)

Port pin PCR

PE[6] PCR[70]

PE[7] PCR[71]

PE[8] PCR[72]

PE[9] PCR[73]

PE[10] PCR[74]

PE[11] PCR[75]

PE[12] PCR[76]

Alternate

function

AF0 AF1 AF2 AF3

—

AF0 AF1 AF2 AF3

—

AF0 AF1 AF2 AF3

—

AF0 AF1 AF2 AF3

—

AF0 AF1 AF2 AF3

—

AF0 AF1 AF2 AF3

— —

Function Peripheral

(1)

GPIO[70] E0UC[22]

CS3_0

MA[1]

EIRQ[22]

GPIO[71] E0UC[23]

CS2_0

MA[0]

EIRQ[23]

GPIO[72]

—

E0UC[22]

—

GPIO[73]

—

E0UC[23]

—

WKPU[7]

(3)

GPIO[74]

—

CS3_1

—

EIRQ[10]

GPIO[75] E0UC[24]

CS4_1

—

WKPU[14]

(3)

GPIO[76]

— — —

ADC1_S[7]

EIRQ[11]

SIUL

eMIOS_0

DSPI_0

ADC

SIUL

eMIOS_0

DSPI_0

ADC

SIUL

—

eMIOS_0

—

SIUL

—

eMIOS_0

—

WKPU

SIUL

—

DSPI_1

—

SIUL

eMIOS_0

DSPI_1

—

WKPU

SIUL

— — —

ADC

SIUL

I/O

direction

(2)

I/O I/O

O O

I/O I/O

O O

I/O

—

I/O

—

I/O

—

I/O

—

I/O

—

I/O I/O

—

I/O

— — —

Pin number

Pad

type

RESET

LQFP64 LQFP100

configuration

M Tristate — 95

M Tristate — 96

M Tristate — 9

S Tristate — 10

S Tristate — 11

S Tristate — 13

S Tristate — 76

Por t H

24/82 Doc ID 16315 Rev 5

SPC560D30x, SPC560D40x Package pinouts and signal descriptions

Table 6. Functional port pin descriptions (continued)

Pin number

LQFP64 LQFP100

Port pin PCR

Alternate

function

Function Peripheral

(1)

I/O

direction

(2)

Pad

type

RESET

configuration

AF0

PH[9]

(6)

PCR[121]

AF1 AF2 AF3

AF0

PH[10]

(6)

PCR[122]

AF1 AF2 AF3

1. Alternate functions are chosen by setting the values of the PCR.PA bitfields inside the SIUL module. PCR.PA = 00 → AF0; PCR.PA = 01 → AF1; PCR.PA = 10 → AF2; PCR.PA = 11 → AF3. This is intended to select the output functions; to use one of the input functions, the PCR.IBE bit must be written to ‘1’, regardless of the values selected in the PCR.PA bitfields. For this reason, the value corresponding to an input only function is reported as “—”.

2. Multiple inputs are routed to all respective modules internally. The input of some modules must be configured by setting the values of the PSMIO.PADSELx bitfields inside the SIUL module.

3. All WKPU pins also support external interrupt capability. See “wakeup unit” chapter of the device reference manual for further details.

4. NMI has higher priority than alternate function. When NMI is selected, the PCR.AF field is ignored.

5. “Not applicable” because these functions are available only while the device is booting. Refer to “BAM” chapter of the device reference manual for details.

6. Out of reset all the functional pins except PC[0:1] and PH[9:10] are available to the user as GPIO. PC[0:1] are available as JTAG pins (TDI and TDO respectively). PH[9:10] are available as JTAG pins (TCK and TMS respectively). If the user configures these JTAG pins in GPIO mode the device is no longer compliant with IEEE 1149.1 2001.

GPIO[121]

—

TCK

—

GPIO[122]

—

TMS

—

SIUL

—

JTAGC

—

SIUL

—

JTAGC

—

I/O

—

I/O

—

Input,

weak pull-

60 88

Input,

weak pull-

53 81

Doc ID 16315 Rev 5 25/82

Electrical characteristics SPC560D30x, SPC560D40x

4 Electrical characteristics

4.1 Introduction

This section contains electrical characteristics of the device as well as temperature and power considerations.

This product contains devices to protect the inputs against damage due to high static voltages. However, it is advisable to take precautions to avoid application of any voltage higher than the specified maximum rated voltages.

To enhance reliability, unused inputs can be driven to an appropriate logic voltage level (V or V

). This can be done by the internal pull-up or pull-down, which is provided by the

product for most general purpose pins.

The parameters listed in the following tables represent the characteristics of the device and its demands on the system.

In the tables where the device logic provides signals with their respective timing characteristics, the symbol “CC” for Controller Characteristics is included in the Symbol column.

In the tables where the external system must provide signals with their respective timing characteristics to the device, the symbol “SR” for System Requirement is included in the Symbol column.

Caution: All of the following parameter values can vary depending on the application and must be

confirmed during silicon validation, silicon characterization or silicon reliability trial.

4.2 Parameter classification

The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better understanding, the classifications listed in Ta bl e 7 are used and the parameters are tagged accordingly in the tables where appropriate.

Table 7. Parameter classifications

Classification tag Tag description

P Those parameters are guaranteed during production testing on each individual device.

D Those parameters are derived mainly from simulations.

Those parameters are achieved by the design characterization by measuring a statistically relevant sample size across process variations.

Those parameters are achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. All values shown in the typical column are within this category.

Note: The classification is shown in the column labeled “C” in the parameter tables where

appropriate.

26/82 Doc ID 16315 Rev 5

SPC560D30x, SPC560D40x Electrical characteristics

4.3 NVUSRO register

Bit values in the Non-Volatile User Options (NVUSRO) Register control portions of the device configuration, namely electrical parameters such as high voltage supply and oscillator margin, as well as digital functionality (watchdog enable/disable after reset).

For a detailed description of the NVUSRO register, please refer to the device reference manual.

4.3.1 NVUSRO[PAD3V5V] field description

The DC electrical characteristics are dependent on the PAD3V5V bit value. Ta bl e 8 shows how NVUSRO[PAD3V5V] controls the device configuration.

Table 8. PAD3V5V field description

(1)

Value

0 High voltage supply is 5.0 V

1 High voltage supply is 3.3 V

1. Default manufacturing value is ‘1’. Value can be programmed by customer in Shadow Flash.

Description

4.3.2 NVUSRO[OSCILLATOR_MARGIN] field description

The fast external crystal oscillator consumption is dependent on the OSCILLATOR_MARGIN bit value. Ta bl e 9 shows how NVUSRO[OSCILLATOR_MARGIN] controls the device configuration.

Table 9. OSCILLATOR_MARGIN field description

(1)

Value

0 Low consumption configuration (4 MHz/8 MHz)

1 High margin configuration (4 MHz/16 MHz)

1. Default manufacturing value is ‘1’. Value can be programmed by customer in Shadow Flash.

Description

4.3.3 NVUSRO[WATCHDOG_EN] field description

The watchdog enable/disable configuration after reset is dependent on the WATCHDOG_EN bit value. Tab le 9 shows how NVUSRO[WATCHDOG_EN] controls the device configuration.

Table 10. WATCHDOG_EN field description

(1)

Value

0 Disable after reset)

1 Enable after reset

1. Default manufacturing value is ‘1’. Value can be programmed by customer in Shadow Flash.

Description

Doc ID 16315 Rev 5 27/82

Electrical characteristics SPC560D30x, SPC560D40x

4.4 Absolute maximum ratings

Table 11. Absolute maximum ratings

Symbol Parameter Conditions

SR Digital ground on VSS_HV pins — 0 0 V

Voltage on VDD_HV pins with respect

to ground (V

)

Voltage on VSS_LV (low voltage digital

SS_LV

DD_BV

supply) pins with respect to ground

)

Voltage on VDD_BV (regulator supply)

pin with respect to ground (V

)

Relative to V

Voltage on VSS_HV_ADC (ADC

SS_ADC

reference) pin with respect to ground

)

Voltage on VDD_HV_ADC (ADC

DD_ADC

INJPAD

INJSUM

AVGSEG

CORELV

STORAGE

1. Supply segments are described in Section 4.7.5: I/O pad current specification.

reference) pin with respect to ground

)

Voltage on any GPIO pin with respect to

ground (V

Injected input current on any pin during

overload condition

Absolute sum of all injected input

currents during overload condition

Sum of all the static I/O current within a

supply segment

Low voltage static current sink through

VDD_BV

)

(1)

Relative to V

= 5.0 V ± 10%, PAD3V5V = 0 — 70

= 3.3 V ± 10%, PAD3V5V = 1 — 64

SR Storage temperature — −55 150 °C

Value

Unit

Min Max

— −0.3 6.0 V

—V

− 0.1 VSS+0.1 V

— −0.3 6.0

VDD− 0.3 VDD+0.3

—V

− 0.1 VSS+0.1 V

— −0.3 6.0

VDD− 0.3 VDD+0.3

— −0.3 6.0

VDD− 0.3 VDD+0.3

— −10 10 mA

— −50 50 mA

— — 150 mA

Note: Stresses exceeding the recommended absolute maximum ratings may cause permanent

damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification are not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. During overload conditions (V the voltage on pins with respect to ground (V

28/82 Doc ID 16315 Rev 5

) must not exceed the recommended values.

IN>VDD

or VIN<VSS),

SPC560D30x, SPC560D40x Electrical characteristics

4.5 Recommended operating conditions

Table 12. Recommended operating conditions (3.3 V)

Val ue

Symbol C Parameter Conditions

Min Max

SS_LV

DD_BV

SS_ADC

DD_ADC

INJPAD

INJSUM

1. 100 nF capacitance needs to be provided between each VDD/VSS pair.

2. 330 nF capacitance needs to be provided between each V

3. 470 nF capacitance needs to be provided between V depending on external regulator characteristics).

4. 100 nF capacitance needs to be provided between V

5. Full electrical specification cannot be guaranteed when voltage drops below 3.0 V. In particular, ADC electrical characteristics and I/Os DC electrical specification may not be guaranteed. When voltage drops below V reset.

6. Guaranteed by device validation.

SR — Digital ground on VSS_HV pins — 0 0 V

(1)

SR —

(2)

SR —

(3)

SR —

(4)

SR —

SR — VDD slope to ensure correct power up

SR — Ambient temperature under bias f

SR — Junction temperature under bias — −40 150

Voltage on VDD_HV pins with respect to ground

)

Voltage on VSS_LV (low voltage digital supply) pins with respect to ground (V

)

Voltage on VDD_BV pin (regulator supply) with respect to ground (V

)

Voltage on VSS_HV_ADC (ADC reference) pin with respect to ground (V

)

Voltage on VDD_HV_ADC pin (ADC reference) with respect to ground (V

)

Voltage on any GPIO pin with respect to ground

)

Injected input current on any pin during overload condition

Absolute sum of all injected input currents during overload condition

(6)

DD_LV/VSS_LV

and the nearest V

DD_BV

DD_ADC/VSS_ADC

pair.

Relative to V

≤ 48 MHz −40 125

CPU

supply pair.

SS_LV

—3.03.6V

—V

− 0.1 VSS+0.1 V

—3.03.6

DDVDD

—V

—3.0

DDVDD

—V

− 0.1 VDD+0.1

− 0.1 VSS+0.1 V

(5)

− 0.1 VDD+0.1

− 0.1 —

—VDD+0.1

— −55mA

— −50 50 mA

— — 0.25 V/µs

(higher value may be needed

LVDHVL,

Unit

3.6 V

°C

device is

Doc ID 16315 Rev 5 29/82

Electrical characteristics SPC560D30x, SPC560D40x

Table 13. Recommended operating conditions (5.0 V)

Val ue

Symbol C Parameter Conditions

Min Max

Unit

(1)

(3)

— Digital ground on VSS_HV pins — 0 0 V

Voltage on VDD_HV pins with respect to

—

ground (VSS)

Voltage on VSS_LV (low voltage digital

—

supply) pins with respect to ground (VSS)

—4.55.5

Voltage drop

(2)

—V

3.0 5.5

− 0.1 VSS+0.1 V

SS_LV

—4.55.5

DD_BV

SS_ADC

(4)

Voltage on VDD_BV pin (regulator supply)

—

with respect to ground (VSS)

Voltage on VSS_HV_ADC (ADC reference)

—

pin with respect to ground (V

Relative to V

(2)

—V

3.0 5.5

VDD− 0.1 VDD+0.1

− 0.1 VSS+0.1 V

—4.55.5

DD_ADC

(5)

INJPAD

INJSUM

1. 100 nF capacitance needs to be provided between each VDD/VSS pair.

2. Full device operation is guaranteed by design when the voltage drops below 4.5 V down to 3.6 V. However, certain analog electrical characteristics will not be guaranteed to stay within the stated limits.

3. 330 nF capacitance needs to be provided between each V

4. 470 nF capacitance needs to be provided between V depending on external regulator characteristics).

5. 100 nF capacitance needs to be provided between V

6. Guaranteed by device validation

Voltage on VDD_HV_ADC pin (ADC

—

reference) with respect to ground (VSS)

Relative to V

Voltage on any GPIO pin with respect to

—

ground (V

Injected input current on any pin during

—

overload condition

Absolute sum of all injected input currents

—

during overload condition

S R

slope to ensure correct power up

—V

— Ambient temperature under bias f

— Junction temperature under bias — −40 150

)

(6)

DD_LV/VSS_LV

and the nearest V

DD_BV

DD_ADC/VSS_ADC

Relative to V

≤ 48 MHz −40 125

CPU

supply pair.

pair.

(2)

—V

3.0 5.5

VDD− 0.1 VDD+0.1

− 0.1 —

—VDD+0.1

— −55

— −50 50

— — 0.25 V/µs

(higher value may be needed

SS_LV

VVoltage drop

°C

Note: SRAM data retention is guaranteed with V

DD_LV

30/82 Doc ID 16315 Rev 5

not below 1.08 V.

SPC560D30x, SPC560D40x Electrical characteristics

4.6 Thermal characteristics

4.6.1 Package thermal characteristics

Table 14. LQFP thermal characteristics

Symbol C Parameter Conditions

(1)

(2)

Value

(3)

Unit

LQFP64 72.1

Single-layer board —1s

θJA

Thermal resistance, junction-to-ambient

natural convection

(4)

LQFP100 65.2

°C/W

LQFP64 57.3

Four-layer board — 2s2p

LQFP100 51.8

θJB

D Thermal resistance, junction-to-board

(5)

Four-layer board — 2s2p

LQFP64 44.1

°C/W

LQFP100 41.3

LQFP64 26.5

Single-layer board — 1s

θJC

D Thermal resistance, junction-to-case

(6)

LQFP100 23.9

°C/W

LQFP64 26.2

Four-layer board — 2s2p

LQFP100 23.7

LQFP64 41

Junction-to-board thermal

characterization parameter, natural convection

Single-layer board — 1s

LQFP100 41.6

°C/W

LQFP64 43

Four-layer board — 2s2p

LQFP100 43.4

LQFP64 11.5

Single-layer board — 1s

Junction-to-case thermal characterization

parameter, natural convection

LQFP100 10.4

°C/W

LQFP64 11.1

Four-layer board — 2s2p

LQFP100 10.2

1. Thermal characteristics are targets based on simulation that are subject to change per device characterization.

= 3.3 V ± 10% / 5.0 V ± 10%, TA = –40 to 125 °C

2. V

3. All values need to be confirmed during device validation.

4. Junction-to-ambient thermal resistance determined per JEDEC JESD51-3 and JESD51-7. Thermal test board meets JEDEC specification for this package. When Greek letters are not available, the symbols are typed as R

5. Junction-to-board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC specification for the specified package. When Greek letters are not available, the symbols are typed as R

6. Junction-to-case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate temperature is used for the case temperature. Reported value includes the thermal resistance of the interface layer. When Greek letters are not available, the symbols are typed as R

thJC

thJB

thJA

Doc ID 16315 Rev 5 31/82

Electrical characteristics SPC560D30x, SPC560D40x

4.6.2 Power considerations

The average chip-junction temperature, TJ, in degrees Celsius, may be calculated using

Equation 1:

Equation 1: T

= TA + (PD x R

θJA

)

Where:

is the ambient temperature in °C.

is the package junction-to-ambient thermal resistance, in °C/W.

θJA

is the sum of P

is the product of I

INT

and P

and VDD, expressed in watts. This is the chip internal

I/O (PD

= P

INT

+ P

I/O

power.

represents the power dissipation on input and output pins; user determined.

I/O

Most of the time for the applications, P P

may be significant, if the device is configured to continuously drive external modules

I/O

I/O< PINT

and may be neglected. On the other hand,

and/or memories.

An approximate relationship between P

Equation 2: P

= K / (TJ + 273 °C)

and TJ (if P

is neglected) is given by:

I/O

Therefore, solving equations Equation 1 and Equation 2:

Equation 3: K = P

x (TA + 273 °C) + R

θJA

x P

Where:

K is a constant for the particular part, which may be determined from Equation 3 by measuring P of P

and TJ may be obtained by solving equations Equation 1 and Equation 2

iteratively for any value of T

(at equilibrium) for a known TA. Using this value of K, the values

4.7 I/O pad electrical characteristics

4.7.1 I/O pad types

The device provides four main I/O pad types depending on the associated alternate functions:

● Slow pads—These pads are the most common pads, providing a good compromise

between transition time and low electromagnetic emission.

● Medium pads—These pads provide transition fast enough for the serial communication

channels with controlled current to reduce electromagnetic emission.

● Input only pads—These pads are associated to ADC channels (ADC_P[X]) providing

low input leakage.

Medium pads can use slow configuration to reduce electromagnetic emission except for PC[1], that is medium only, at the cost of reducing AC performance.

4.7.2 I/O input DC characteristics

Ta bl e 1 5 provides input DC electrical characteristics as described in Figure 4.

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SPC560D30x, SPC560D40x Electrical characteristics

Figure 4. Input DC electrical characteristics definition

HYS

(GPDI register of SIUL)

Table 15. I/O input DC electrical characteristics

Symbol C Parameter Conditions

PDIx = ‘1’

PDIx = ‘0’

(1)

Value

(2)

Min Typ Max

Input high level CMOS (Schmitt

SR P

HYS

LKG

Trigger)

Input hysteresis CMOS (Schmitt

CC C

Trigger)

CCDDigital input leakage

No injection on adjacent pin

(3)

1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified.

2. All values need to be confirmed during device validation.

3. In the range from 40 to 1000 ns, pulses can be filtered or not filtered, according to operating temperature and voltage.

SR P Digital input filtered pulse — — — 40 ns

(3)

SR P Digital input not filtered pulse — 1000 — — ns

NFI

— 0.65V

—0.1V

= −40 °C — 2 200

= 25 °C — 2 200

= 85 °C — 5 300

= 105 °C — 12 500

= 125 °C — 70 1000

—VDD+0.4

——

Unit

VVILSR P Input low level CMOS (Schmitt Trigger) — −0.4 — 0.35V

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Electrical characteristics SPC560D30x, SPC560D40x

4.7.3 I/O output DC characteristics

The following tables provide DC characteristics for bidirectional pads:

● Ta bl e 1 6 provides weak pull figures. Both pull-up and pull-down resistances are

supported.

● Ta bl e 1 7 provides output driver characteristics for I/O pads when in SLOW

configuration.

● Ta bl e 1 8 provides output driver characteristics for I/O pads when in MEDIUM

configuration.

Table 16. I/O pull-up/pull-down DC electrical characteristics

Symbol C Parameter Conditions

= VIL, VDD = 5.0 V ± 10%

WPU

|CC

Weak pull-up current absolute value

= VIL, VDD = 3.3 V ± 10% PAD3V5V = 1 10 — 150

= VIH, VDD = 5.0 V ± 10%

WPD

|CC

Weak pull-down current absolute value

1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified.

2. The configuration PAD3V5 = 1 when V configured in input or in high impedance state.

Table 17. SLOW configuration output buffer electrical characteristics

Symbol C Parameter Conditions

= VIH, VDD = 3.3 V ± 10% PAD3V5V = 1 10 — 150

= 5 V is only a transient configuration during power-up. All pads but RESET are

(1)

= −2mA,

= 5.0 V ± 10%, PAD3V5V = 0

(1)

PAD3V5V = 0 10 — 150

(recommended)

Output high level

SLOW configuration

Push Pull

= −2mA,

= 5.0 V ± 10%, PAD3V5V = 1

= −1mA,

= 3.3 V ± 10%, PAD3V5V = 1

(2)

(recommended)

= 2 mA,

= 5.0 V ± 10%, PAD3V5V = 0

(recommended)

Output low level

SLOW configuration

Push Pull

= 2 mA,

= 5.0 V ± 10%, PAD3V5V = 1

= 1 mA,

= 3.3 V ± 10%, PAD3V5V = 1

(2)

(recommended)

1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified.

2. The configuration PAD3V5 = 1 when V configured in input or in high impedance state.

= 5 V is only a transient configuration during power-up. All pads but RESET are

Value

Min Typ Max

(2)

10 — 250

(2)

10 — 250

Val ue

Min Typ Max

0.8V

——

VDD− 0.8 — —

— — 0.1V

——0.5

Unit

µAC PAD3V5V = 1

Unit

34/82 Doc ID 16315 Rev 5

SPC560D30x, SPC560D40x Electrical characteristics

Table 18. MEDIUM configuration output buffer electrical characteristics

Symbol C Parameter Conditions

(1)

= −3.8 mA,

= 5.0 V ± 10%, PAD3V5V = 0

= −2mA,

= 5.0 V ± 10%, PAD3V5V = 0

(recommended)

Output high level

MEDIUM configuration

Push Pull

= −1mA,

= 5.0 V ± 10%, PAD3V5V = 1

= −1mA,

= 3.3 V ± 10%, PAD3V5V = 1

(2)

(recommended)

= −100 µA,

= 5.0 V ± 10%, PAD3V5V = 0

= 3.8 mA,

= 5.0 V ± 10%, PAD3V5V = 0

= 2 mA,

= 5.0 V ± 10%, PAD3V5V = 0

(recommended)

VOLCC

Output low level

MEDIUM configuration

Push Pull

= 1 mA,

= 5.0 V ± 10%, PAD3V5V = 1

= 1 mA,

= 3.3 V ± 10%, PAD3V5V = 1

(2)

(recommended)

= 100 µA,

1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified.

2. The configuration PAD3V5 = 1 when V configured in input or in high impedance state.

= 5.0 V ± 10%, PAD3V5V = 0

= 5 V is only a transient configuration during power-up. All pads but RESET are

Value

Min Typ Max

0.8V

——

− 0.8 — —

——

——0.2V

——0.1V

——0.5

——0.1V

Unit

Doc ID 16315 Rev 5 35/82

Electrical characteristics SPC560D30x, SPC560D40x

4.7.4 Output pin transition times

Table 19. Output pin transition times

Symbol C Parameter Conditions

Output transition time output

ttrCC

(3)

SLOW configuration

Output transition time output

(3)

MEDIUM configuration

1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified.

2. All values need to be confirmed during device validation.

includes device and package capacitances (C

3. C

CL = 25 pF

= 50 pF — — 100

= 100 pF — — 125

= 25 pF

= 50 pF — — 100

= 100 pF — — 125

= 25 pF

= 50 pF — — 20

= 100 pF — — 40

= 25 pF

= 50 pF — — 25

= 100 pF — — 40

< 5 pF).

PKG

= 5.0 V ± 10%, PAD3V5V = 0

= 3.3 V ± 10%, PAD3V5V = 1

= 5.0 V ± 10%, PAD3V5V = 0

SIUL.PCRx.SRC = 1

= 3.3 V ± 10%, PAD3V5V = 1

SIUL.PCRx.SRC = 1

(1)

(2)

Value

Min Typ Max

——50

——10

——12

Unit

4.7.5 I/O pad current specification

The I/O pads are distributed across the I/O supply segment. Each I/O supply segment is associated to a V

DD/VSS

Ta bl e 2 1 provides I/O consumption figures.

In order to ensure device reliability, the average current of the I/O on a single segment should remain below the I

Table 20. I/O supply segment

Package

LQFP100 pin 16 – pin 35 pin 37 – pin 69 pin 70 – pin 83 pin 84 – pin 15

LQFP64 pin 8 – pin 26 pin 28 – pin 55 pin 56 – pin 7 —

supply pair as described in Ta bl e 2 0 .

AVGSEG

maximum value.

1234

Supply segment

36/82 Doc ID 16315 Rev 5

SPC560D30x, SPC560D40x Electrical characteristics

Table 21. I/O consumption

Symbol C Parameter Conditions

Dynamic I/O current

CC D

for SLOW

CL = 25 pF

SWTSLW

(3)

configuration

Dynamic I/O current

CC D

for MEDIUM

CL = 25 pF

SWTMED

(3)

configuration

= 25 pF, 2 MHz

= 25 pF, 4 MHz — — 3.2

RMSSLW

RMSMED

AVGSEG

Root mean square

CC D

I/O current for SLOW configuration

Root mean square I/O current for

CC D

MEDIUM configuration

Sum of all the static

SR D

I/O current within a supply segment

= 100 pF, 2 MHz — — 6.6

= 25 pF, 2 MHz

= 25 pF, 4 MHz — — 2.3

= 100 pF, 2 MHz — — 4.7

= 25 pF, 13 MHz

= 25 pF, 40 MHz — — 13.4

= 100 pF, 13 MHz — — 18.3

= 25 pF, 13 MHz

= 25 pF, 40 MHz — — 8.5

= 100 pF, 13 MHz — — 11

= 5.0 V ± 10%, PAD3V5V = 0 — — 70

= 3.3 V ± 10%, PAD3V5V = 1 — — 65

(1)

= 5.0 V ± 10%,

PAD3V5V = 0

= 3.3 V ± 10%,

PAD3V5V = 1

= 5.0 V ± 10%,

PAD3V5V = 0

= 3.3 V ± 10%,

PAD3V5V = 1

= 5.0 V ± 10%,

PAD3V5V = 0

= 3.3 V ± 10%,

PAD3V5V = 1

= 5.0 V ± 10%,

PAD3V5V = 0

= 3.3 V ± 10%,

PAD3V5V = 1

(2)

Val ue

Min Typ Max

——20

——16

——29

——17

——2.3

——1.6

——6.6

—— 5

Unit

1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified.

2. All values need to be confirmed during device validation.

3. Stated maximum values represent peak consumption that lasts only a few ns during I/O transition.

Ta bl e 2 2 provides the weight of concurrent switching I/Os.

In order to ensure device functionality, the sum of the weight of concurrent switching I/Os on a single segment should remain below 100%.

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Electrical characteristics SPC560D30x, SPC560D40x

Table 22. I/O weight

(1)

LQFP100/LQFP64

Pad

SRC

Weight 5 V Weight 3.3 V

(2)

= 0 SRC = 1 SRC = 0 SRC = 1

PB[3] 9% 9% 10% 10%

PC[9] 8% 8% 10% 10%

PC[14] 8% 8% 10% 10%

PC[15] 8% 11% 9% 10%

PA[2]8%8%9%9%

PE[0] 7% 7% 9% 9%

PA[1]7%7%8%8%

PE[1] 7% 10% 8% 8%

PE[8] 6% 9% 8% 8%

PE[9] 6% 6% 7% 7%

PE[10] 6% 6% 7% 7%

PA[0]5%7%6%7%

PE[11] 5% 5% 6% 6%

PC[11] 7% 7% 9% 9%

PC[10] 8% 11% 9% 10%

PB[0] 8% 11% 9% 10%

PB[1] 8% 8% 10% 10%

PC[6] 8% 8% 10% 10%

PC[7] 8% 8% 10% 10%

PA[15] 8% 11% 9% 10%

PA[14] 7% 11% 9% 9%

PA[4]7%7%8%8%

PA[13] 7% 10% 8% 9%

PA[12] 7% 7% 8% 8%

PB[9] 1% 1% 1% 1%

PB[8] 1% 1% 1% 1%

PB[10] 5% 5% 6% 6%

PD[0]1%1%1%1%

PD[1]1%1%1%1%

PD[2]1%1%1%1%

PD[3]1%1%1%1%

PD[4]1%1%1%1%

38/82 Doc ID 16315 Rev 5

SPC560D30x, SPC560D40x Electrical characteristics

Table 22. I/O weight

(1)

(continued)

LQFP100/LQFP64

Pad

SRC

Weight 5 V Weight 3.3 V

(2)

= 0 SRC = 1 SRC = 0 SRC = 1

PD[5]1%1%1%1%

PD[6]1%1%1%1%

PD[7]1%1%1%1%

PD[8]1%1%1%1%

PB[4] 1% 1% 1% 1%

PB[5] 1% 1% 1% 1%

PB[6] 1% 1% 1% 1%

PB[7] 1% 1% 1% 1%

PD[9]1%1%1%1%

PD[10] 1% 1% 1% 1%

PD[11] 1% 1% 1% 1%

PB[11] 9% 9% 11% 11%

PD[12] 8% 8% 10% 10%

PB[12] 8% 8% 10% 10%

PD[13] 8% 8% 9% 9%

PB[13] 8% 8% 9% 9%

PD[14] 7% 7% 9% 9%

PB[14] 7% 7% 8% 8%

PD[15] 7% 7% 8% 8%

PB[15] 6% 6% 7% 7%

PA[3]6%6%7%7%

PA[7]4%4%5%5%

PA[8]4%4%5%5%

PA[9]4%4%5%5%

PA[10] 5% 5% 6% 6%

PA[11] 5% 5% 6% 6%

PE[12] 5% 5% 6% 6%

PC[3]5%5%6%6%

PC[2]5%7%6%6%

PA[5]5%6%5%6%

PA[6]4%4%5%5%

PC[1] 5% 17% 4% 12%

Doc ID 16315 Rev 5 39/82

Electrical characteristics SPC560D30x, SPC560D40x

Table 22. I/O weight

(1)

(continued)

LQFP100/LQFP64

Pad

SRC

Weight 5 V Weight 3.3 V

(2)

= 0 SRC = 1 SRC = 0 SRC = 1

PC[0]6%9%7%8%

PE[2] 7% 10% 8% 9%

PE[3] 7% 10% 9% 9%

PC[5] 8% 11% 9% 10%

PC[4] 8% 11% 9% 10%

PE[4] 8% 12% 10% 10%

PE[5] 8% 12% 10% 11%

PE[6] 9% 12% 10% 11%

PE[7] 9% 12% 10% 11%

PC[12] 9% 13% 11% 11%

PC[13] 9% 9% 11% 11%

PC[8] 9% 9% 11% 11%

PB[2] 9% 13% 11% 12%

1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified.

2. SRC: “Slew Rate Control” bit in SIU_PCR.

4.8 RESET electrical characteristics

The device implements a dedicated bidirectional RESET pin.

Figure 5. Start-up reset requirements

DDMIN

RESET

device reset forced by RESET

device start-up phase

40/82 Doc ID 16315 Rev 5

SPC560D30x, SPC560D40x Electrical characteristics

Figure 6. Noise filtering on reset signal

RESET

hw_rst

filtered by hysteresis

filtered by lowpass filter

FRST

filtered by lowpass filter

FRST

unknown reset state

NFRST

device under hardware reset

‘1’

‘0’

Table 23. Reset electrical characteristics

Symbol C Parameter Conditions

Input High Level CMOS

SR P

HYS

(Schmitt Trigger)

Input low Level CMOS

SR P

(Schmitt Trigger)

Input hysteresis CMOS

CC C

(Schmitt Trigger)

Push Pull, I

= 5.0 V ± 10%, PAD3V5V = 0

= 2 mA,

(recommended)

CC P Output low level

Push Pull, I

= 5.0 V ± 10%, PAD3V5V = 1

Push Pull, I V

= 3.3 V ± 10%, PAD3V5V = 1

= 1 mA,

(recommended)

(2)

(1)

Value

Min Typ Max

— 0.65V

—VDD+0.4 V

— −0.4 — 0.35V

—0.1V

——V

— — 0.1V

(3)

——0.5

Unit

Doc ID 16315 Rev 5 41/82

Electrical characteristics SPC560D30x, SPC560D40x

Table 23. Reset electrical characteristics (continued)

(2)

Symbol C Parameter Conditions

(1)

Min Typ Max

= 25 pF,

= 5.0 V ± 10%, PAD3V5V = 0

= 50 pF,

= 5.0 V ± 10%, PAD3V5V = 0

= 100 pF,

Output transition time

CC D

output pin

(4)

MEDIUM configuration

RESET

1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified.

2. All values need to be confirmed during device validation.

3. This is a transient configuration during power-up, up to the end of reset PHASE2 (refer to RGM module section of the

4. C

5. The configuration PAD3V5 = 1 when V

SR P

FRST

SR P

NFRST

|CCP

WPU

device reference manual).

includes device and package capacitance (C

configured in input or in high impedance state.

input filtered

pulse

input not filtered

RESET pulse

Weak pull-up current absolute value

= 5.0 V ± 10%, PAD3V5V = 0

= 25 pF,

= 3.3 V ± 10%, PAD3V5V = 1

= 50 pF,

= 3.3 V ± 10%, PAD3V5V = 1

= 100 pF,

= 3.3 V ± 10%, PAD3V5V = 1

———40ns

— 1000 — — ns

= 3.3 V ± 10%, PAD3V5V = 1 10 — 150

= 5.0 V ± 10%, PAD3V5V = 0 10 — 150

= 5.0 V ± 10%, PAD3V5V = 1

<5pF).

PKG

= 5 V is only transient configuration during power-up. All pads but RESET are

(5)

Value

Unit

——10

——20

——40

——12

——25

——40

µAV

10 — 250

4.9 Power management electrical characteristics

4.9.1 Voltage regulator electrical characteristics

The device implements an internal voltage regulator to generate the low voltage core supply V common I/O supply V

● HV: High voltage external power supply for voltage regulator module. This must be

● BV: High voltage external power supply for internal ballast module. This must be

● LV: Low voltage internal power supply for core, FMPLL and flash digital logic. This is

42/82 Doc ID 16315 Rev 5

from the high voltage ballast supply V

DD_LV

. The following supplies are involved:

provided externally through V

provided externally through V V

power pin.

power pin. Voltage values should be aligned with

DD_BV

. The regulator itself is supplied by the

DD_BV

generated by the internal voltage regulator but provided outside to connect stability

SPC560D30x, SPC560D40x Electrical characteristics

capacitor. It is further split into four main domains to ensure noise isolation between critical LV modules within the device:

– LV_COR: Low voltage supply for the core. It is also used to provide supply for

FMPLL through double bonding.

– LV_CFLA: Low voltage supply for code flash module. It is supplied with dedicated

ballast and shorted to LV_COR through double bonding.

– LV_DFLA: Low voltage supply for data flash module. It is supplied with dedicated

ballast and shorted to LV_COR through double bonding.

– LV_PLL: Low voltage supply for FMPLL. It is shorted to LV_COR through double

bonding.

Figure 7. Voltage regulator capacitance connection

(LV_COR/LV_CFLA)

REG2

DD_BV

DD_LVn

SS_LVn

SS_LV

REF

Voltage Regulator

(Ballast decoupling)

DEC1

(LV_COR/LV_DFLA)

REG1

DEVICE

DD_BV

DD_LV

SS_LV

REG3

The internal voltage regulator requires external capacitance (C

DD_LV

REGn

DD_LV

DEVICE

DEC2

(supply/IO decoupling)(LV_COR/LV_PLL)

) to be connected to the device in order to provide a stable low voltage digital supply to the device. Capacitances should be placed on the board as near as possible to the associated pins. Care should also be taken to limit the serial inductance of the board to less than 5 nH.

Each decoupling capacitor must be placed between each of the three V

DD_LV/VSS_LV

pairs to ensure stable voltage (see Section 4.5: Recommended operating conditions).

Doc ID 16315 Rev 5 43/82

supply

Electrical characteristics SPC560D30x, SPC560D40x

Table 24. Voltage regulator electrical characteristics

Symbol C Parameter Conditions

(1)

Val ue

Min Typ Max

REGn

REG

DEC1

DEC2

MREG

MREGINT

LPREG

LPREGINT

ULPREG

ULPREGINT

DD_BV

1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified.

2. This capacitance value is driven by the constraints of the external voltage regulator supplying the V value is in the range of 470 nF.

3. This value is acceptable to guarantee operation from 4.5 V to 5.5 V.

4. External regulator and capacitance circuitry must be capable of providing I operating range.

5. In-rush average current is seen only for short time during power-up and on standby exit (maximum 20 µs, depending on external capacitances to be loaded).

6. The duration of the in-rush current depends on the capacitance placed on LV pins. BV decoupling capacitors must be sized accordingly. Refer to I

Internal voltage regulator external

SR —

capacitance

Stability capacitor equivalent serial

SR —

resistance

SR — Decoupling capacitance

Decoupling capacitance regulator

SR —

supply

CCTMain regulator output voltage

P After trimming 1.16 1.28 —

Main regulator current provided to

SR —

CC D

domain

DD_LV

Main regulator module current consumption

(2)

ballast

Range: 10 kHz to 20 MHz

DD_BV/VSS_LV

DD_BV

DD_BV/VSS_LV

DD_BV

VDD/VSS pair 10 100 — nF

Before exiting from reset — 1.32 —

MREG

— 200 — 500 nF

——0.2W

pair:

= 4.5 V to 5.5 V

pair:

= 3V to 3.6V

(3)

100

(4)

470

400 —

———150 mA

= 200 mA — — 2

= 0 mA — — 1

—

CC P Low-power regulator output voltage After trimming 1.16 1.28 — V

Low power regulator current provided

SR —

to V

Low-power regulator module current

consumption

—

Ultra low power regulator output

CC P

voltage

Ultra low power regulator current

SR —

provided to V

Ultra low power regulator module

CC D

current consumption

In-rush average current on V

CC D

during power-up

domain

DD_LV

domain

DD_LV

(5)

value for minimum amount of current to be provided in cc.

MREG

DD_BV

LPREG

TA = 55 °C

LPREG

= 55 °C

After trimming 1.16 1.28 — V

ULPREG

= 55 °C

ULPREG

= 55 °C

— ——15 mA

= 15 mA;

= 0 mA;

——

—

5 —

600

———5 mA

= 5 mA;

= 0 mA;

——

—

2 —

100

——— 300

voltage. A typical

DD_BV

while maintaining supply V

DD_BV

(6)

Unit

µA

44/82 Doc ID 16315 Rev 5

SPC560D30x, SPC560D40x Electrical characteristics

4.9.2 Low voltage detector electrical characteristics

The device implements a power-on reset (POR) module to ensure correct power-up initialization, as well as five low voltage detectors (LVDs) to monitor the V voltage while device is supplied:

● POR monitors V

during the power-up phase to ensure device is maintained in a safe

reset state (refer to RGM Destructive Event Status (RGM_DES) Register flag F_POR in device reference manual)

● LVDHV3 monitors V

to ensure device reset below minimum functional supply (refer

to RGM Destructive Event Status (RGM_DES) Register flag F_LVD27 in device reference manual)

● LVDHV3B monitors V

to ensure device reset below minimum functional supply

DD_BV

(refer to RGM Destructive Event Status (RGM_DES) Register flag F_LVD27_VREG in device reference manual)

● LVDHV5 monitors V

when application uses device in the 5.0 V ± 10% range (refer to

RGM Functional Event Status (RGM_FES) Register flag F_LVD45 in device reference manual)

● LVDLVCOR monitors power domain No. 1 (refer to RGM Destructive Event Status

(RGM_DES) Register flag F_LVD12_PD1 in device reference manual)

● LVDLVBKP monitors power domain No. 0 (refer to RGM Destructive Event Status

(RGM_DES) Register flag F_LVD12_PD0 in device reference manual)

and the V

DD_LV

Figure 8. Low voltage detector vs reset

LVDHVxH

LVDHVxL

RESET

Doc ID 16315 Rev 5 45/82

Electrical characteristics SPC560D30x, SPC560D40x

Table 25. Low voltage detector electrical characteristics

Symbol C Parameter Conditions

PORUP

PORH

LV DH V 3H

LV DH V 3L

LVDHV3BH

LVDHV3BL

LV DH V 5H

LV DH V 5L

LV DLV C OR L

LVDLVBKPL

1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified.

SR P Supply for functional POR module

CC P Power-on reset threshold 1.5 — 2.6

CC T LVDHV3 low voltage detector high threshold — — 2.95

CC P LVDHV3 low voltage detector low threshold 2.7 — 2.9

CC P LVDHV3B low voltage detector high threshold — — 2.95

CC P LVDHV3B low voltage detector low threshold 2.7 — 2.9

= 25 °C,

after trimming

CC T LVDHV5 low voltage detector high threshold — — 4.5

CC P LVDHV5 low voltage detector low threshold 3.8 — 4.4

CC P LVDLVCOR low voltage detector low threshold 1.08 — 1.16

CC P LVDLVBKP low voltage detector low threshold 1.08 — 1.16

4.10 Power consumption

(1)

Min Typ Max

1.0 — 5.5

Val ue

Unit

Ta bl e 2 6 provides DC electrical characteristics for significant application modes. These

values are indicative values; actual consumption depends on the application.

Table 26. Power consumption on VDD_BV and VDD_HV

Symbol C Parameter Conditions

DDMAX

DDRUN

DDHALT

DDSTOP

(2)

RUN mode maximum

CC D

average current

(4)

RUN mode typical

average current

CCCHALT mode current

CCPSTOP mode current

(5)

= 8 MHz — 7 —

CPU

= 16 MHz — 18 —

CPU

= 32 MHz — 29 —

CPU

= 48 MHz — 40 100

CPU

Slow internal RC oscillator

(6)

(128 kHz) running

Slow internal RC oscillator

(7)

(128 kHz) running

(1)

Value

Min Typ Max

— — 90 130

=25°C — 8 15

= 125 °C — 14 25

= 25 °C — 180 700

= 55 °C — 500 —

=85°C — 1 6

= 105 °C — 2 9

= 125 °C — 4.5 12

Unit

(3)

(8)

µA

(8)

mADT

(8)

46/82 Doc ID 16315 Rev 5

SPC560D30x, SPC560D40x Electrical characteristics

Table 26. Power consumption on VDD_BV and VDD_HV (continued)

Value

Symbol C Parameter Conditions

(1)

Min Typ Max

= 25 °C — 30 100

Slow internal RC oscillator

DDSTDBY

CCPSTANDBY mode current

(9)

(128 kHz) running

1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified.

2. Running consumption does not include I/Os toggling which is highly dependent on the application. The given value is thought to be a worst case value with all peripherals running, and code fetched from code flash while modify operation ongoing on data flash. Notice that this value can be significantly reduced by application: switch off not used peripherals (default), reduce peripheral frequency through internal prescaler, fetch from RAM most used functions, use low power mode when possible.

3. Higher current may be sinked by device during power-up and standby exit. Please refer to in-rush average current on

Table 24.

4. RUN current measured with typical application with accesses on both flash memory and SRAM.

5. Only for the “P” classification: Code fetched from SRAM: serial IPs CAN and LIN in loop-back mode, DSPI as Master, PLL as system clock (3 × Multiplier) peripherals on (eMIOS/CTU/ADC) and running at maximum frequency, periodic SW/WDG timer reset enabled.

6. Data flash power down. Code flash in low power. SIRC (128 kHz) and FIRC (16 MHz) on. 10 MHz XTAL clock. FlexCAN: 0 ON (clocked but no reception or transmission). LINFlex: instances: 0, 1, 2 ON (clocked but no reception or transmission), instance: 3 clocks gated. eMIOS: instance: 0 ON (16 channels on PA[0]–PA[11] and PC[12]–PC[15]) with PWM 20 kHz, instance: 1 clock gated. DSPI: instance: 0 (clocked but no communication). RTC/API ON.PIT ON. STM ON. ADC ON but no conversion except 2 analog watchdogs.

7. Only for the “P” classification: No clock, FIRC (16 MHz) off, SIRC (128 kHz) on, PLL off, HPVreg off, ULPVreg/LPVreg on. All possible peripherals off and clock gated. Flash in power down mode.

8. When going from RUN to STOP mode and the core consumption is > 6 mA, it is normal operation for the main regulator module to be kept on by the on-chip current monitoring circuit. This is most likely to occur with junction temperatures exceeding 125 °C and under these circumstances, it is possible for the current to initially exceed the maximum STOP specification by up to 2 mA. After entering stop, the application junction temperature will reduce to the ambient level and the main regulator will be automatically switched off when the load current is below 6 mA.

9. Only for the “P” classification: ULPVreg on, HP/LPVreg off, 16 KB SRAM on, device configured for minimum consumption, all possible modules switched off.

=55°C — 75 —

= 85 °C — 180 700

= 105 °C — 315 1000

= 125 °C — 560 1700

Unit

µA

4.11 Flash memory electrical characteristics

The data flash operation depends strongly on the code flash operation. If code flash is switched-off, the data flash is disabled.

4.11.1 Program/Erase characteristics

Ta bl e 2 7 shows the program and erase characteristics.

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Electrical characteristics SPC560D30x, SPC560D40x

Table 27. Program and erase specifications (code flash)

Value

Symbol C Parameter

Min Typ

dwprogram

16Kpperase

32Kpperase

128Kpperase

esus

1. Typical program and erase times assume nominal supply values and operation at 25 °C. All times are subject to change pending device characterization.

2. Initial factory condition: < 100 program/erase cycles, 25 °C, typical supply voltage.

3. The maximum program and erase times occur after the specified number of program/erase cycles. These maximum values are characterized but not guaranteed.

4. Actual hardware programming times. This does not include software overhead.

Table 28. Program and erase specifications (data flash)

Double word (64 bits) program time

16 KB block preprogram and erase time — 300 500 5000 ms

CC C

32 KB block preprogram and erase time — 400 600 5000 ms

128 KB block preprogram and erase time — 800 1300 7500 ms

Erase suspend latency — — 30 30 µs

(4)

—2250500µs

(1)

Initial

max

(2)

Max

(3)

Val ue

Symbol C Parameter

Min Typ

swprogram

16Kpperase

Bank_D

1. Typical program and erase times assume nominal supply values and operation at 25 °C. All times are subject to change pending device characterization.

2. Initial factory condition: < 100 program/erase cycles, 25 °C, typical supply voltage.

3. The maximum program and erase times occur after the specified number of program/erase cycles. These maximum values are characterized but not guaranteed.

4. Actual hardware programming times. This does not include software overhead.

Single word (32 bits) program time

16 KB block preprogram and erase time — 700 800 1500 ms

64 KB block preprogram and erase time — 1900 2300 4800 ms

(4)

— 30 70 300 µs

(1)

Initial

max

(2)

Max

(3)

Unit

Table 29. Flash module life

Symbol C Parameter Conditions

16 KB blocks 100 — —

128 KB blocks 1 100

P/E CC C

Number of program/erase cycles per block over the operating temperature range (T

)

48/82 Doc ID 16315 Rev 5

Value

Min Typ Max

(1)

—

(1)

—

Unit

kcycles32 KB blocks 10 100

SPC560D30x, SPC560D40x Electrical characteristics

Table 29. Flash module life (continued)

Value

Symbol C Parameter Conditions

Min Typ Max

Unit

Retention CC C

Minimum data retention at 85 °C average ambient temperature

(2)

Blocks with 0–1000 P/E cycles

Blocks with 1001–10000 P/E cycles

20 — —

10 — —

Blocks with 10001–100000 P/E

5——

cycles

1. To be confirmed.

2. Ambient temperature averaged over application duration. It is recommended not to exceed the product operating temperature range.

ECC circuitry provides correction of single bit faults and is used to improve further automotive reliability results. Some units will experience single bit corrections throughout the life of the product with no impact to product reliability.

Table 30. Flash memory read access timing

Symbol C Parameter

CFREAD

DFREAD

Conditions

(1)

Maximum working frequency for reading code flash memory at given

number of wait states in worst conditions

C 0 wait states 20

Maximum working frequency for reading data flash memory at given

CC P

number of wait states in worst conditions

2 wait states 48

6 wait states 48 MHz

years

Max Unit

MHz

1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified.

4.11.2 Flash power supply DC characteristics

Ta bl e 3 1 shows the power supply DC characteristics on external supply.

Note: Power supply for data flash is actually provided by code flash; this means that data flash

cannot work if code flash is not powered.

Table 31. Flash power supply DC electrical characteristics

Symbol C Parameter Conditions

CFREAD

DFREAD

CFMOD

DFMOD

Sum of the current consumption on

CC D

DDHV

and V

on read access

DDBV

Sum of the current consumption on

CC D

DDHV

and V

DDBV

on matrix

modification (program/erase)

(2)

(1)

Value

Min Typ Max

Flash module read

= 48 MHz

CPU

Program/Erase on-going

Code flash — — 33

Data flash — — 4

Code flash — — 33 while reading flash registers, f

CPU

= 48 MHz

Data flash — — 6

Doc ID 16315 Rev 5 49/82

Unit

Electrical characteristics SPC560D30x, SPC560D40x

Table 31. Flash power supply DC electrical characteristics (continued)

(2)

Value

Unit

Symbol C Parameter Conditions

(1)

Min Typ Max

Sum of the current consumption on

FLPW

CC D

DDHV

and V

DDBV

during

— Code flash — — 910 µA

flash low-power mode

CFPWD

DFPWD

1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified.

2. All values need to be confirmed during device validation.

Sum of the current consumption on

CC D

DDHV

and V

DDBV

during

flash power-down mode

—

Code flash — — 125

µA

Data flash — — 25

4.11.3 Start-up/Switch-off timings

Table 32. Start-up time/Switch-off time

Symbol C Parameter Conditions

(1)

Value

Min Typ Max

FLARSTEXIT

FLALPEXIT

FLAPDEXIT

FLALPENTRY

FLAPDENTRY

1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified.

2. Data flash does not support low-power mode.

3. If code flash is already switched-on.

T Delay for flash module to exit reset mode

C C

Delay for flash module to exit low-power

(2)

mode

Delay for flash module to exit power-down mode

Delay for flash module to enter low-power mode

Delay for flash module to enter power-down mode

Code flash — — 125

Data flash — — 150

Code flash — — 0.5

Code flash — — 30

Data flash 30

Code flash — — 0.5

Code flash — — 1.5

Data flash — — 4

4.12 Electromagnetic compatibility (EMC) characteristics

(3)

Unit

µs

Susceptibility tests are performed on a sample basis during product characterization.

4.12.1 Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular.

50/82 Doc ID 16315 Rev 5

SPC560D30x, SPC560D40x Electrical characteristics

Therefore it is recommended that the user apply EMC software optimization and prequalification tests in relation with the EMC level requested for his application.

● Software recommendations − The software flowchart must include the management of

runaway conditions such as:

– Corrupted program counter

– Unexpected reset

– Critical data corruption (control registers...)

● Prequalification trials − Most of the common failures (unexpected reset and program

counter corruption) can be reproduced by manually forcing a low state on the reset pin or the oscillator pins for 1 second.

To complete these trials, ESD stress can be applied directly on the device. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see the application note Software Techniques For Improving Microcontroller EMC Performance (AN1015)).

4.12.2 Electromagnetic interference (EMI)

The product is monitored in terms of emission based on a typical application. This emission test conforms to the IEC 61967-1 standard, which specifies the general conditions for EMI measurements.

Table 33. EMI radiated emission measurement

(1)(2)

Value

Symbol C Parameter Conditions

Min Typ Max

— SR — Scan range — 0.150 — 1000 MHz

SR — Operating frequency — — 48 — MHz

CPU

1. EMI testing and I/O port waveforms per IEC 61967-1, -2, -4.

2. For information on conducted emission and susceptibility measurement (norm IEC 61967-4), please contact your local

3. All values need to be confirmed during device validation.

SR — LV operating voltages — — 1.28 — V

DD_LV

No PLL frequency modulation

± 2% PLL frequency modulation

— — 18 dBµV

——14

CC T Peak level

EMI

marketing representative.

= 5V, TA=25°C,

LQFP100 package Test conforming to IEC 61967-2, f

OSC

= 8 MHz/f

= 48 MHz

CPU

(3)

4.12.3 Absolute maximum ratings (electrical sensitivity)

Based on two different tests (ESD and LU) using specific measurement methods, the product is stressed in order to determine its performance in terms of electrical sensitivity.

Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts * (n + 1) supply pin). This test

Unit

dBµV

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Electrical characteristics SPC560D30x, SPC560D40x

conforms to the AEC-Q100-002/-003/-011 standard. For more details, refer to the application note Electrostatic Discharge Sensitivity Measurement (AN1181).

Table 34. ESD absolute maximum ratings

(1) (2)

Symbol C Ratings Conditions Class Max value

ESD(HBM)

ESD(MM)

ESD(CDM)

1. All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits.

2. A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device specification requirements. Complete DC parametric and functional testing shall be performed per applicable device specification at room temperature followed by hot temperature, unless specified otherwise in the device specification.

CC T

Electrostatic discharge voltage (Human Body Model)

Electrostatic discharge voltage (Machine Model)

Electrostatic discharge voltage (Charged Device Model)

= 25 °C

conforming to AEC-Q100-002

= 25 °C

conforming to AEC-Q100-003

= 25 °C

conforming to AEC-Q100-011

H1C 2000

M2 200

500

C3A

750 (corners)

Static latch-up (LU)

Two complementary static tests are required on six parts to assess the latch-up performance:

● A supply overvoltage is applied to each power supply pin.

● A current injection is applied to each input, output and configurable I/O pin.

These tests are compliant with the EIA/JESD 78 IC latch-up standard.

Table 35. Latch-up results

Unit

Symbol C Parameter Conditions Class

= 125 °C

LU CC T Static latch-up class

conforming to JESD 78

4.13 Fast external crystal oscillator (4 to 16 MHz) electrical

characteristics

The device provides an oscillator/resonator driver. Figure 9 describes a simple model of the internal oscillator driver and provides an example of a connection for an oscillator or a resonator.

Ta bl e 3 6 provides the parameter description of 4 MHz to 16 MHz crystals used for the

design simulations.

II level A

52/82 Doc ID 16315 Rev 5

SPC560D30x, SPC560D40x Electrical characteristics

Figure 9. Crystal oscillator and resonator connection scheme

EXTAL

Crystal

XTAL

DEVICE

XTAL

EXTAL

DEVICE

Resonator

XTAL

DEVICE

Notes:

1. XTAL/EXTAL must not be directly used to drive external circuits

2. A series resistor may be required, according to crystal oscillator supplier recommendations.

Table 36. Crystal description

Nominal

frequency

(MHz)

NDK

crystal

reference

Crystal

equivalent

series

resistance

(ESR) Ω

Crystal

motional

capacitance

) fF

Crystal

motional

inductance

(Lm) mH

Load on

xtalin/xtalout

1=C2

(pF)

(1)

4 NX8045GB 300 2.68 591.0 21 2.93

300 2.46 160.7 17 3.01

10 150 2.93 86.6 15 2.91

Shunt

capacitance

between

xtalout and

xtalin

(2)

(pF)

12 120 3.11 56.5 15 2.93

NX5032GA

16 120 3.90 25.3 10 3.00

1. The values specified for C1 and C2 are the same as used in simulations. It should be ensured that the testing includes all the parasitics (from the board, probe, crystal, etc.) as the AC / transient behavior depends upon them.

2. The value of C0 specified here includes 2 pF additional capacitance for parasitics (to be seen with bond-pads, package, etc.).

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Electrical characteristics SPC560D30x, SPC560D40x

Figure 10. Fast external crystal oscillator (4 to 16 MHz) timing diagram

S_MTRANS bit (ME_GS register)

‘1’

‘0’

FXOSC

FXOSCOP

XTAL

FXOSCSU

90%

10%

valid internal clock

1/f

FXOSC

Table 37. Fast external crystal oscillator (4 to 16 MHz) electrical characteristics

Symbol C Parameter Conditions

(1)

Value

Min Typ Max

Fast external crystal

FXOSC

SR —

oscillator frequency

CC C

= 3.3 V ± 10%,

PAD3V5V = 1

—4.0—16.0MHz

2.2 — 8.2

OSCILLATOR_MARGIN = 0

= 5.0 V ± 10%,

PAD3V5V = 0 OSCILLATOR_MARGIN = 0

= 3.3 V ± 10%,

PAD3V5V = 1

2.0 — 7.4

2.7 — 9.7

mFXOSC

CC P

Fast external crystal oscillator transconductance

CC C

OSCILLATOR_MARGIN = 1

= 5.0 V ± 10%,

CC C

PAD3V5V = 0

2.5 — 9.2

OSCILLATOR_MARGIN = 1

= 4 MHz,

FXOSC

Oscillation amplitude at

CC T

EXTAL

OSC

OSCILLATOR_MARGIN = 0

= 16 MHz,

OSC

OSCILLATOR_MARGIN = 1

1.3 — —

Unit

mA/V

FXOSCOP

FXOSC

FXOSCSU

CC P Oscillation operating point — — 0.95 V

(2)

Fast external crystal

CC T

oscillator consumption

Fast external crystal

CC T

oscillator start-up time

——23mA

= 4 MHz,

OSC

OSCILLATOR_MARGIN = 0

= 16 MHz,

OSC

OSCILLATOR_MARGIN

54/82 Doc ID 16315 Rev 5

= 1

—— 6

——1.8

SPC560D30x, SPC560D40x Electrical characteristics

Table 37. Fast external crystal oscillator (4 to 16 MHz) electrical characteristics (continued)

Value

Symbol C Parameter Conditions

(1)

Min Typ Max

1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified.

2. Stated values take into account only analog module consumption but not the digital contributor (clock tree and enabled peripherals).

Input high level CMOS

SR P

(Schmitt Trigger)

Input low level CMOS

SR P

(Schmitt Trigger)

Oscillator bypass mode 0.65V

—VDD+0.4 V

Oscillator bypass mode −0.4 — 0.35V

4.14 FMPLL electrical characteristics

The device provides a frequency-modulated phase-locked loop (FMPLL) module to generate a fast system clock from the main oscillator driver.

Table 38. FMPLL electrical characteristics

Symbol C Parameter Conditions

PLLIN

SR — FMPLL reference clock

FMPLL reference clock duty

SR —

cycle

(3)

(2)

(1)

Val ue

Min Typ Max

—4—48MHz

—40—60%

Unit

PLLOUT

VCO

Δt

1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified.

2. All values need to be confirmed during device validation.

3. PLLIN clock retrieved directly from FXOSC clock. Input characteristics are granted when oscillator is used in functional

4. Frequency modulation is considered ±4%.

CC D FMPLL output clock frequency — 16 — 48 MHz

VCO frequency without

(4)

frequency modulation

CC P

VCO frequency with frequency modulation

SR — System clock frequency — — — 48 MHz

CPU

CC P Free-running frequency — 20 — 150 MHz

FREE

CC P FMPLL lock time Stable oscillator (f

LOCK

= 16 MHz (resonator),

CC — FMPLL long term jitter

LT JI T

CC C FMPLL consumption TA = 25 °C — — 4 mA

PLL

mode. When bypass mode is used, oscillator input clock should verify f

PLLIN

at 48 MHz, 4000 cycles

PLLCLK

—256—512

—245—533

= 16 MHz) — 40 100 µs

PLLIN

— — 10 ns

PLLIN

and Δ

PLLIN

MHz

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Electrical characteristics SPC560D30x, SPC560D40x

4.15 Fast internal RC oscillator (16 MHz) electrical characteristics

The device provides a 16 MHz fast internal RC oscillator (FIRC). This is used as the default clock at the power-up of the device.

Table 39. Fast internal RC oscillator (16 MHz) electrical characteristics

Symbol C Parameter Conditions

(2)

(1)

Val ue

Unit

Min Typ Max

FIRC

FIRCRUN

FIRCPWD

FIRCSTOP

FIRCSU

FIRCPRE

FIRCTRIM

CC P

Fast internal RC oscillator high frequency

SR — — 12 20

(3)

Fast internal RC oscillator high

CC T

frequency current in running

TA = 25 °C, trimmed — 16 —

TA = 25 °C, trimmed — — 200 µA

mode

Fast internal RC oscillator high

CC D

frequency current in power

TA = 25 °C — — 10 µA

down mode

sysclk = off — 500 —

Fast internal RC oscillator high

CC T

frequency and system clock current in stop mode

TA = 25 °C

sysclk = 2 MHz — 600 —

sysclk = 4 MHz — 700 —

sysclk = 8 MHz — 900 —

sysclk = 16 MHz — 1250 —

Fast internal RC oscillator start-

CC C

up time

= 5.0 V ± 10% — 1.1 2.0 µs

Fast internal RC oscillator

CC C

precision after software trimming of f

Fast internal RC oscillator

CC C

trimming step

FIRC

TA = 25 °C −1— 1%

TA = 25 °C — 1.6 %

MHz

µA

Fast internal RC oscillator variation in temperature and

FIRCVAR

CC C

supply with respect to f

= 55 °C in high-frequency

FIRC

— −5— 5%

configuration

1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified.

2. All values need to be confirmed during device validation.

3. This does not include consumption linked to clock tree toggling and peripherals consumption when RC oscillator is ON.

56/82 Doc ID 16315 Rev 5

SPC560D30x, SPC560D40x Electrical characteristics

4.16 Slow internal RC oscillator (128 kHz) electrical

characteristics

The device provides a 128 kHz slow internal RC oscillator (SIRC). This can be used as the reference clock for the RTC module.

Table 40. Slow internal RC oscillator (128 kHz) electrical characteristics

Symbol C Parameter Conditions

(2)

(1)

Value

Unit

Min Typ Max

SIRC

SIRCSU

SIRCPRE

SIRCTRIM

CC P

Slow internal RC oscillator low frequency

SR — — 100 — 150

(3)

Slow internal RC oscillator low

CC C

frequency current

Slow internal RC oscillator start-up

CC P

time

Slow internal RC oscillator precision

CC C

after software trimming of f

Slow internal RC oscillator trimming

CC C

step

SIRC

TA = 25 °C, trimmed — 128 —

TA = 25 °C, trimmed — — 5 µA

TA = 25 °C, VDD = 5.0 V ± 10% — 8 12 µs

TA = 25 °C −2— 2

——2.7—

Slow internal RC oscillator variation

SIRCVAR

CC P

respect to f

at TA= 55 °C in high

SIRC

High frequency configuration −10 — 10 %

in temperature and supply with

frequency configuration

1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified.

2. All values need to be confirmed during device validation.

3. This does not include consumption linked to clock tree toggling and peripherals consumption when RC oscillator is ON.

kHz

Doc ID 16315 Rev 5 57/82

Electrical characteristics SPC560D30x, SPC560D40x

4.17 ADC electrical characteristics

4.17.1 Introduction

The device provides a 12-bit Successive Approximation Register (SAR) analog-to-digital converter.

Figure 11. ADC characteristics and error definitions

code out

1023

1022

1021

1020

1019

1018

Offset Error (EO)

1 LSB ideal = V

(2)

(1)

(5)

(4)

(3)

(1) Example of an actual transfer curve

(2) The ideal transfer curve

(3) Differential non-linearity error (DNL)

(4) Integral non-linearity error (INL)

(5) Center of a step of the actual transfer curve

Gain Error (E

/ 1024

DD_ADC

)

1 2 3 4 5 6 7 1017 1018 1019 1020 1021 1022 1023

Offset Error (E

)

1 LSB (ideal)

(LSB

in(A)

4.17.2 Input impedance and ADC accuracy

In the following analysis, the input circuit corresponding to the precise channels is considered.

58/82 Doc ID 16315 Rev 5

ideal

)

SPC560D30x, SPC560D40x Electrical characteristics

To preserve the accuracy of the A/D converter, it is necessary that analog input pins have low AC impedance. Placing a capacitor with good high frequency characteristics at the input pin of the device can be effective: the capacitor should be as large as possible, ideally infinite. This capacitor contributes to attenuating the noise present on the input pin; furthermore, it sources charge during the sampling phase, when the analog signal source is a high-impedance source.

A real filter can typically be obtained by using a series resistance with a capacitor on the input pin (simple RC filter). The RC filtering may be limited according to the value of source impedance of the transducer or circuit supplying the analog signal to be measured. The filter at the input pins must be designed taking into account the dynamic characteristics of the input signal (bandwidth) and the equivalent input impedance of the ADC itself.

In fact a current sink contributor is represented by the charge sharing effects with the sampling capacitance: C

being substantially a switched capacitance, with a frequency

equal to the conversion rate of the ADC, it can be seen as a resistive path to ground. For instance, assuming a conversion rate of 1 MHz, with C 330 kΩ is obtained (R

= 1 / (fc*CS), where fc represents the conversion rate at the

equal to 3 pF, a resistance of

considered channel). To minimize the error induced by the voltage partitioning between this resistance (sampled voltage on C

) and the sum of RS + RF + RL + RSW + RAD, the external

circuit must be designed to respect the Equation 4:

Equation 4:

RSRFRLR

+++ +

---------------------------------------------------------------------------

•

SWRAD

-- -LSB 2

Equation 4 generates a constraint for external network design, in particular on a resistive

path. Internal switch resistances (R

and RAD) can be neglected with respect to external

resistances.

Doc ID 16315 Rev 5 59/82

Electrical characteristics SPC560D30x, SPC560D40x

Figure 12. Input equivalent circuit (precise channels)

EXTERNAL CIRCUIT INTERNAL CIRCUIT SCHEME

Source Filter Current Limiter

Channel

Selection

Sampling

RS: Source impedance

: Filter resistance

: Filter capacitance

: Current limiter resistance

: Channel selection switch impedance

SW1

: Sampling switch impedance

: Pin capacitance (two contributions, C

: Sampling capacitance

and CP2)

Figure 13. Input equivalent circuit (extended channels)

EXTERNAL CIRCUIT INTERNAL CIRCUIT SCHEME

Source Filter Current Limiter

SW1

Channel

Extended

Selection

Switch

Sampling

RS: Source impedance

: Filter resistance

: Filter capacitance

: Current limiter resistance

: Channel selection switch impedance (two contributions, R

SW1

: Sampling switch impedance

: Pin capacitance (two contributions, CP1, CP2 and CP3)

: Sampling capacitance

SW1

and R

60/82 Doc ID 16315 Rev 5

SW2

SW1

SW2

)

SPC560D30x, SPC560D40x Electrical characteristics

A second aspect involving the capacitance network shall be considered. Assuming the three capacitances C

, CP1 and C

are initially charged at the source voltage VA (refer to the

equivalent circuit in Figure 13): A charge sharing phenomenon is installed when the sampling phase is started (A/D switch close).

Figure 14. Transient behavior during sampling phase

Voltage transient on C

ΔV < 0.5 LSB

τ1 < (RSW + RAD) CS << t

τ2 = RL (CS + CP1 + CP2)

In particular two different transient periods can be distinguished:

1. A first and quick charge transfer from the internal capacitance C sampling capacitance C

occurs (CS is supposed initially completely discharged):

and CP2 to the

considering a worst case (since the time constant in reality would be faster) in which C

is reported in parallel to C

are in series, and the time constant is

(call CP = CP1 + CP2), the two capacitances CP and

Equation 5:

CPC

•

+()=

SWRAD

--------------------- -

•

CPCS+

Equation 5 can again be simplified considering only CS as an additional worst

condition. In reality, the transient is faster, but the A/D converter circuitry has been designed to be robust also in the very worst case: the sampling time t

is always much

longer than the internal time constant:

Equation 6:

The charge of C voltage V

on the capacitance according to Equation 7:

τ1R

and CP2 is redistributed also on CS, determining a new value of the

+()< C

SWRAD

Equation 7:

A1CSCP1CP2

++()• V

2. A second charge transfer involves also C capacitance) through the resistance R and C

were in parallel to CP1 (since the time constant in reality would be faster), the

: again considering the worst case in which CP2

time constant is:

Doc ID 16315 Rev 5 61/82

«•

(that is typically bigger than the on-chip

+()•=

P1CP2

Electrical characteristics SPC560D30x, SPC560D40x

Equation 8:

< C

τ2R

++()•

SCP1CP2

In this case, the time constant depends on the external circuit: in particular imposing that the transient is completed well before the end of sampling time t R

sizing is obtained:

, a constraints on

Equation 9:

10 τ

• 10 R

Of course, R combination with R

shall be sized also according to the current limitation constraints, in

(source impedance) and RF (filter resistance). Being CF

definitively bigger than C

, CP2 and CS, then the final voltage V

LCSCP1CP2

charge transfer transient) will be much higher than V (charge balance assuming now C

already charged at VA1):

++()••= t

. Equation 10 must be respected

(at the end of the

Equation 10:

A2CSCP1CP2CF

+++()• VAC

• V

+CP1CP2+C

+()•=

The two transients above are not influenced by the voltage source that, due to the presence of the R C

with respect to the ideal source VA; the time constant RFCF of the filter is very high with

respect to the sampling time (t

filter, is not able to provide the extra charge to compensate the voltage drop on

FCF

). The filter is typically designed to act as anti-aliasing.

Figure 15. Spectral representation of input signal

Analog source bandwidth (V

Anti-aliasing filter (f

= RC filter pole)

Noise

)

tc< 2 RFCF (conversion rate vs. filter pole)

= f0 (anti-aliasing filtering condition)

2 f0< fC (Nyquist)

Sampled signal spectrum (f

= conversion rate)

Calling f

the bandwidth of the source signal (and as a consequence the cut-off frequency of

the anti-aliasing filter, f least 2f

; it means that the constant time of the filter is greater than or at least equal to twice

the conversion period (t

), according to the Nyquist theorem the conversion rate fC must be at

). Again the conversion period tc is longer than the sampling time ts,

which is just a portion of it, even when fixed channel continuous conversion mode is selected (fastest conversion rate at a specific channel): in conclusion it is evident that the time constant of the filter R

62/82 Doc ID 16315 Rev 5

is definitively much higher than the sampling time ts, so the

FCF

SPC560D30x, SPC560D40x Electrical characteristics

charge level on CS cannot be modified by the analog signal source during the time in which the sampling switch is closed.

The considerations above lead to impose new constraints on the external circuit, to reduce the accuracy error due to the voltage drop on C above, it is simple to derive Equation 11 between the ideal and real sampled voltage on C

; from the two charge balance equations

Equation 11:

----------- V

P1CP2

------------------------------------------------------- -= C

+CFC

P1CP2

From this formula, in the worst case (when V assuming to accept a maximum error of half a count, a constraint is evident on C

Equation 12:

CF2048 C

4.17.3 ADC electrical characteristics

Table 41. ADC input leakage current

Symbol C Parameter Conditions

LKG

Table 42. ADC conversion characteristics

Symbol C Parameter Conditions

Input leakage

current

TA= −40 °C

=25 °C — 1 —

= 105 °C — 8 200

= 125 °C — 45 400

No current injection on adjacent pin

is maximum, that is for instance 5 V),

•>

Value

Min Typ Max

—1—

(1)

Value

Min Typ Max

value:

Unit

SS_ADC

DD_ADC

AINx

ADC

Voltage on VSS_HV_ADC (ADC

SR —

reference) pin with respect to ground

(2)

)

Voltage on VDD_HV_ADC pin

SR —

(ADC reference) with respect to ground

)

SR — Analog input voltage

(3)

SR — ADC analog frequency

— −0.1 — 0.1 V

—V

− 0.1 — VDD+0.1 V

SS_ADC

− 0.1 — V

DD_ADC

VDD=5.0V 3.33 — 32 + 4%

VDD=3.3V 3.33 — 20 + 4%

Doc ID 16315 Rev 5 63/82

+0.1 V

MHz

Electrical characteristics SPC560D30x, SPC560D40x

Table 42. ADC conversion characteristics (continued)

Symbol C Parameter Conditions

ADC_SYS

ADC_PU

SR —

SR — ADC power up delay — ——1.5 µs

ADC clock duty cycle (ipg_clk)

Sampling time

VDD= 3.3 V

(5)

ADCLKSEL = 1

= 20 MHz,

ADC

INPSAMP = 12

= 3.33 MHz,

ADC

INPSAMP = 255

Sampling time

VDD = 5.0 V

(5)

= 24 MHz,

ADC

INPSAMP = 13

= 3.33 MHz,

ADC

INPSAMP = 255

= 20 MHz,

ADC

INPCMP = 0

= 13.33 MHz,

ADC

Conversion time

VDD= 3.3 V

(6)

INPCMP = 0

Conversion time

VDD = 5.0 V

(6)

= 32 MHz,

ADC

INPCMP = 0

= 13.33 MHz,

ADC

INPCMP = 0

CC D

ADC input sampling capacitance

—

(4)

(1)

Value

Unit

Min Typ Max

45 —55%

600 — — ns

— — 76.2 µs

500 — — ns

— — 76.2 µs

2.4 — —

µs

——3.6

1.5 — —

µs

——3.6

5 pF

CC D

SW1

CC D

SW2

CC D

SR — Input current Injection

INJ

INLP CC T

ADC input pin capacitance 1

ADC input pin capacitance 2

ADC input pin capacitance 3

Internal resistance of analog source

Absolute Integral nonlinearity-precise channels

—

3 pF

— 1 pF

—

———

1.5 pF

1 kΩ

———2 kΩ

Current injection on one ADC input, different from the converted one

———

VDD =

3.3 V ± 10%

VDD =

5.0 V ± 10%

−5— 5

−5 — 5

0.3 kΩ

No overload —1 3LSB

64/82 Doc ID 16315 Rev 5

SPC560D30x, SPC560D40x Electrical characteristics

Table 42. ADC conversion characteristics (continued)

Value

Symbol C Parameter Conditions

(1)

Min Typ Max

Absolute Integral non-

INLX CC T

linearity-extended

No overload —1.5 5LSB

channels

DNL CC T

Absolute Differential non-linearity

No overload —0.5 1LSB

EO CC T Absolute Offset error — —2 — LSB

CC T Absolute Gain error — —2— LSB

(7)

TUEP

(7)

TUEX

1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified.

2. Analog and digital V

3. V

4. Duty cycle is ensured by using system clock without prescaling. When ADCLKSEL = 0, the duty cycle is ensured by internal

5. During the sampling time the input capacitance C

6. This parameter does not include the sampling time t

7. Total Unadjusted Error: The maximum error that occurs without adjusting Offset and Gain errors. This error is a

may exceed V

AINx

will be clamped respectively to 0x000 or 0xFFF.

divider by 2.

resistance of the analog source must allow the capacitance to reach its final voltage level within tS. After the end of the sampling time tS, changes of the analog input voltage have no effect on the conversion result. Values for the sample clock t

depend on programming.

the result’s register with the conversion result.

combination of Offset, Gain and Integral Linearity errors.

P Total unadjusted error

for precise channels,

T With current injection –8 8

input only pins

Total unadjusted error for extended channel

T With current injection –12 12

must be common (to be tied together externally).

and V

SS_ADC

DD_ADC

Without current injection –6 6

Without current injection –10 10

limits, remaining on absolute maximum ratings, but the results of the conversion

can be charged/discharged by the external source. The internal

, but only the time for determining the digital result and the time to load

Unit

LSB

4.18 On-chip peripherals

4.18.1 Current consumption

Table 43. On-chip peripherals current consumption

Symbol C Parameter Conditions Typical value

500 Kbyte/s Total (static + dynamic)

DD_BV(CAN)

CAN (FlexCAN) supply

CC T

current on V

DD_BV

125 Kbyte/s 8 * f

Doc ID 16315 Rev 5 65/82

(1)

8 * f

consumption: – FlexCAN in loop-back

mode

– XTAL at 8 MHz used as

CAN engine clock source

– Message sending period

is 580 µs

periph

(2)

Unit

+ 85 µA

+ 27 µA

Electrical characteristics SPC560D30x, SPC560D40x

Table 43. On-chip peripherals current consumption

(1)

(continued)

Symbol C Parameter Conditions Typical value

Static consumption:

DD_BV(eMIOS)

eMIOS supply current

CC T

on V

DD_BV

– eMIOS channel OFF – Global prescaler enabled

Dynamic consumption: – It does not change varying the

29 * f

periph

3µA

frequency (0.003 mA)

Total (static + dynamic) consumption: – LIN mode – Baudrate: 20 Kbyte/s

5 * f

periph

+ 31 µA

DD_BV(SCI)

SCI (LINFlex) supply

CC T

current on V

DD_BV

Ballast static consumption (only clocked) 1 µA

Ballast dynamic consumption (continuous

DD_BV(SPI)

SPI (DSPI) supply

CC T

current on V

DD_BV

communication): – Baudrate: 2 Mbit/s

16 * f

periph

– Transmission every 8 µs – Frame: 16 bits

DD_BV(ADC)

DD_HV_ADC(ADC)

ADC supply current on

CC T

DD_BV

ADC supply current on

CC T

DD_HV_ADC

VDD = 5.5 V

Ballast static consumption (no conversion)

Ballast dynamic consumption (continuous conversion)

(3)

Analog static consumption (no conversion)

Analog dynamic consumption (continuous

41 * f

5 * f

2 * f

75 * f

periph

+ 32 µA

conversion)

DD_HV(FLASH)

DD_HV(PLL)

1. Operating conditions: TA = 25 °C, f

2. f

3. During the conversion, the total current consumption is given from the sum of the static and dynamic consumption, i.e.,

is an absolute value.

periph

(41 + 5) * f

periph

CFlash + DFlash supply

CC T

current on V

PLL supply current on

CC T

DD_HV

= 8 MHz to 48 MHz.

periph

VDD = 5.5 V — 8.21 mA

VDD = 5.5 V — 30 * f

periph

(2)

Unit

µA

66/82 Doc ID 16315 Rev 5

SPC560D30x, SPC560D40x Electrical characteristics

4.18.2 DSPI characteristics

Table 44. DSPI characteristics

(1)

DSPI0/DSPI1

No. Symbol C Parameter

Min Typ Max

Master mode (MTFE = 0)

Slave mode (MTFE = 0)

Master mode (MTFE = 1)

Slave mode (MTFE = 1)

125 — —

83 — —

—f

SCK

DSPI

SCK cycle time

SR D DSPI digital controller frequency — — f

Internal delay between pad

— Δt

CSC

CC D

associated to SCK and pad associated to CSn in master

Master mode — — 130

mode

Internal delay between pad

— Δt

ASC

CC D

associated to SCK and pad associated to CSn in master

Master mode — — 130

mode for CSn1→1

10 t

11 t

12 t

1. Operating conditions: C

2. Maximum is reached when CSn pad is configured as SLOW pad while SCK pad is configured as MEDIUM pad.

3. The t DSPI_CTARx registers), delay between internal CS and internal SCK must be higher than Δt

4. The t DSPI_CTARx registers), delay between internal CS and internal SCK must be higher than Δt

5. This delay value corresponds to SMPL_PT = 00b which is bit field 9 and 8 of DSPI_MCR.

6. SCK and SOUT configured as MEDIUM pad.

(3)

CSCext

ASCext

SDC

SUI

SUO

CSC

ASC

SR D CS to SCK delay Slave mode 32 — — ns

(4)

SR D After SCK delay Slave mode 1/f

CC D

SR D Slave mode t

SR D Slave access time — 1/f

SR D Slave SOUT disable time — 7 — — ns

SCK duty cycle

SR D Data setup time for inputs

SR D Data hold time for inputs

(6)

CC D Data valid after SCK edge

(6)

CC D Data hold time for outputs

= 10 to 50 pF, SlewIN = 3.5 to 15 ns.

OUT

delay value is configurable through a register. When configuring t

Master mode — t

Master mode 43 — —

Slave mode 5 — —

Master mode 0 — —

Slave mode 2

Master mode — — 32

Slave mode — — 52

Master mode 0 — —

Slave mode 8 — —

+ 5 — — ns

DSPI

/2 —

SCK

/2 — —

SCK

+70 — — ns

DSPI

(5)

(using PCSSCK and CSSCK fields in

CSC

(using PASC and ASC fields in

ASC

CSC

ASC

——

to ensure positive t

CPU

(2)

CSCext

ASCext

Unit

MHz

Doc ID 16315 Rev 5 67/82

Electrical characteristics SPC560D30x, SPC560D40x

Figure 16. DSPI classic SPI timing – master, CPHA = 0

PCSx

SCK Output (CPOL = 0)

SCK Output (CPOL = 1)

SIN

SOUT

First Data

Data

First Data Data Last Data

Note: Numbers shown reference Ta bl e 4 4.

Last Data

Figure 17. DSPI classic SPI timing – master, CPHA = 1

PCSx

SCK Output (CPOL = 0)

SCK Output (CPOL = 1)

SIN

SOUT

First Data

Data

Note: Numbers shown reference Tab le 4 4.

Last Data

68/82 Doc ID 16315 Rev 5

SPC560D30x, SPC560D40x Electrical characteristics

Figure 18. DSPI classic SPI timing – slave, CPHA = 0

Data

Note: Numbers shown reference Tab l e 4 4 .

Last Data

SCK Input (CPOL = 0)

SCK Input (CPOL = 1)

SOUT

SIN

First Data

Figure 19. DSPI classic SPI timing – slave, CPHA = 1

SCK Input (CPOL = 0)

SCK Input (CPOL = 1)

SOUT

SIN

First Data

Note: Numbers shown reference Tab l e 4 4 .

Data

Last Data

Doc ID 16315 Rev 5 69/82

Electrical characteristics SPC560D30x, SPC560D40x

Figure 20. DSPI modified transfer format timing – master, CPHA = 0

PCSx

SCK Output (CPOL = 0)

SCK Output (CPOL = 1)

SIN

SOUT

First Data

Data

Note: Numbers shown reference Tab le 4 4.

Last Data

Figure 21. DSPI modified transfer format timing – master, CPHA = 1

PCSx

SCK Output (CPOL = 0)

SCK Output (CPOL = 1)

SIN

SOUT

70/82 Doc ID 16315 Rev 5

First Data

Note: Numbers shown reference Ta bl e 4 4 .

Data

Last Data

SPC560D30x, SPC560D40x Electrical characteristics

Figure 22. DSPI modified transfer format timing – slave, CPHA = 0

SCK Input (CPOL = 0)

SCK Input (CPOL = 1)

SOUT

SIN

First Data

Data

Note: Numbers shown reference Ta bl e 4 4 .

Last Data

Figure 23. DSPI modified transfer format timing – slave, CPHA = 1

SCK Input (CPOL = 0)

SCK Input (CPOL = 1)

SOUT

SIN

First Data

Data

Note: Numbers shown reference Tab l e 4 4 .

Last Data

Doc ID 16315 Rev 5 71/82

Electrical characteristics SPC560D30x, SPC560D40x

4.18.3 JTAG characteristics

Table 45. JTAG characteristics

No. Symbol C Parameter

JCYC

TDIS

TDIH

TMSS

TMSH

TDOV

TDOI

CC D TCK cycle time 83.33 — — ns

CC D TDI setup time 15 — — ns

CC D TDI hold time 5 — — ns

CC D TMS setup time 15 — — ns

CC D TMS hold time 5 — — ns

CC D TCK low to TDO valid — — 49 ns

CC D TCK low to TDO invalid 6 — — ns

Figure 24. Timing diagram – JTAG boundary scan

TCK

Value

Min Typ Max

2/4

3/5

Unit

DATA IN PUTS

DATA OUTPUTS

INPUT DATA VALID

OUTPUT DATA VALID

Note: Numbers shown reference Tab l e 4 5 .

72/82 Doc ID 16315 Rev 5

SPC560D30x, SPC560D40x Package characteristics

5 Package characteristics

5.1 ECOPACK

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK

packages, depending on their level of environmental compliance. ECOPACK®

is an ST trademark.

5.2 Package mechanical data

5.2.1 LQFP100

Figure 25. LQFP100 mechanical drawing

Doc ID 16315 Rev 5 73/82

Package characteristics SPC560D30x, SPC560D40x

Table 46. LQFP100 mechanical data

mm inches

Symbol

Min Typ Max Min Typ Max

A — — 1.600 — — 0.0630

A1 0.050 — 0.150 0.0020 — 0.0059

A2 1.350 1.400 1.450 0.0531 0.0551 0.0571

b 0.170 0.220 0.270 0.0067 0.0087 0.0106

c 0.090 — 0.200 0.0035 — 0.0079

D 15.800 16.000 16.200 0.6220 0.6299 0.6378

D1 13.800 14.000 14.200 0.5433 0.5512 0.5591

D3 — 12.000 — — 0.4724 —

E 15.800 16.000 16.200 0.6220 0.6299 0.6378

E1 13.800 14.000 14.200 0.5433 0.5512 0.5591

E3 — 12.000 — — 0.4724 —

e — 0.500 — — 0.0197 —

L 0.450 0.600 0.750 0.0177 0.0236 0.0295

L1 — 1.000 — — 0.0394 —

(1)

k 0.0 ° 3.5 ° 7.0 ° 0.0 ° 3.5 ° 7.0 °

Tolerance mm inches

ccc 0.080 0.0031

1. Values in inches are converted from mm and rounded to 4 decimal digits.

74/82 Doc ID 16315 Rev 5

SPC560D30x, SPC560D40x Package characteristics

5.2.2 LQFP64

Figure 26. LQFP64 mechanical drawing

ccc

Pin 1 identification

E1 E

A1 K

Table 47. LQFP64 mechanical data

5W_ME

mm inches

(1)

Symbol

Min Typ Max Min Typ Max

A — — 1.6 — — 0.0630

A1 0.05 — 0.15 0.0020 — 0.0059

A2 1.35 1.4 1.45 0.0531 0.0551 0.0571

b 0.17 0.22 0.27 0.0067 0.0087 0.0106

c 0.09 — 0.2 0.0035 — 0.0079

D 11.8 12 12.2 0.4646 0.4724 0.4803

D1 9.8 10 10.2 0.3858 0.3937 0.4016

D3 — 7.5 — — 0.2953 —

E 11.8 12 12.2 0.4646 0.4724 0.4803

E1 9.8 10 10.2 0.3858 0.3937 0.4016

E3 — 7.5 — — 0.2953 —

e — 0.5 — — 0.0197 —

L 0.45 0.6 0.75 0.0177 0.0236 0.0295

L1 — 1 — — 0.0394 —

k 0.0° 3.5° 7.0° 0.0° 3.5° 7.0°

ccc — — 0.08 — — 0.0031

1. Values in inches are converted from mm and rounded to 4 decimal digits.

Doc ID 16315 Rev 5 75/82

Ordering information SPC560D30x, SPC560D40x

6 Ordering information

Figure 27. Ordering information scheme

Example code:

SPC56 40 Y0D CL3 4E0

Product identifier

Memory PackingCore Family

TemperaturePackage Custom ver sion

Y = Tray X = Tape and Reel 90°

3E0 = 32 MHz EEPROM 5V/3V 4E0 = 48 MHz EEPROM 5V/3V

B = –40 to 105 °C C = –40 to 125 °C

L1 = LQFP64 L3 = LQFP100

40 = 256 KB 30 = 128 KB

D = Access family

0 = e200z0h

SPC56 = Power Architecture in 90 nm

76/82 Doc ID 16315 Rev 5

SPC560D30x, SPC560D40x Abbreviations

Appendix A Abbreviations

Ta bl e 4 8 lists abbreviations used in this document.

Table 48. Abbreviations

Abbreviation Meaning

APU Auxilliary processing unit

CMOS Complementary metal–oxide–semiconductor

CPHA Clock phase

CPOL Clock polarity

CS Peripheral chip select

DAOC Double action output compare

ECC Error code correction

EVTO Event out

GPIO General purpose input/output

IPM Input period measurement

IPWM Input pulse width measurement

MB Message buffer

MC Modulus counter

MCB Modulus counter buffered (up / down)

MCKO Message clock out

MDO Message data out

MSEO Message start/end out

MTFE Modified timing format enable

NVUSRO Non-volatile user options register

OPWFMB Output pulse width and frequency modulation buffered

OPWMB Output pulse width modulation buffered

OPWMCB Center aligned output pulse width modulation buffered with dead time

OPWMT Output pulse width modulation trigger

PWM Pulse width modulation

SAIC Single action input capture

SAOC Single action output compare

SCK Serial communications clock

SOUT Serial data out

TBD To be defined

TCK Test clock input

TDI Test data input

Doc ID 16315 Rev 5 77/82

Abbreviations SPC560D30x, SPC560D40x

Table 48. Abbreviations (continued)

Abbreviation Meaning

TDO Test data output

TMS Test mode select

78/82 Doc ID 16315 Rev 5

SPC560D30x, SPC560D40x Revision history

Revision history

Ta bl e 4 9 summarizes revisions to this document.

Table 49. Document revision history

Date Revision Changes

09-Jul-2009 1 Initial release.

Updated the following tables:

- Absolute maximum ratings

- Low voltage power domain electrical characteristics;

18-Feb-2010 2

10-Aug-2010 3

- On-chip peripherals current consumption

- DSPI characteristics;

- JTAG characteristics;

- ADC conversion characteristics; Inserted a note on “Flash power supply DC characteristics” section.

“Features” section: Updated information concerning eMIOS, ADC, LINFlex, Nexus and low power capabilities

“SPC560D30, SPC560D40 device comparison” table: updated the “Execution speed” row

“SPC560D30, SPC560D40 series block diagram” figure: – updated max number of Crossbar Switches – updated Legend “SPC560D30, SPC560D40 series block summary” table: added

contents concernig the eDMA block “LQFP100 pin configuration (top view)” figure: – removed alternate functions – updated supply pins “LQFP64 pin configuration (top view)” figure: removed alternate

functions Added “Pin muxing” section “NVUSRO register” section: Deleted “NVUSRO[WATCHDOG_EN]

field description“ section “Recommended operating conditions (3.3 V)” table: –TV – In footnote No. 3, changed capacitance value between V

: deleted min value

SS_LV

DD_BV

and

“Recommended operating conditions (5.0 V)” table: deleted TVDD min value

“LQFP thermal characteristics” table: changed R

θJC

values

“I/O input DC electrical characteristics” table:

: updated max value

–W

: updated min value

–W

NFI

“I/O consumption” table: removed I

DYNSEG

row Added “I/O weight” table “Program and erase specifications (Code Flash)” table: deleted

Bank_C

row

Doc ID 16315 Rev 5 79/82

Revision history SPC560D30x, SPC560D40x

Table 49. Document revision history (continued)

Date Revision Changes

Updated the following tables: – “Voltage regulator electrical characteristics” – “Low voltage monitor electrical characteristics” – “Low voltage power domain electrical characteristics” – “Start-up time/Switch-off time” – “Fast external crystal oscillator (4 to 16 MHz) electrical

characteristics” – “FMPLL electrical characteristics” – “Fast internal RC oscillator (16 MHz) electrical characteristics” – “ADC conversion characteristics” – “On-chip peripherals current consumption” – “DSPI characteristics” “DSPI characteristics” section: removed “DSPI PCS strobe (PCSS)

timing” figure Updated “Order codes” table Added “Order codes for engineering samples” table Updated “Commercial product code structure” table

Formatting and editorial changes throughout Device comparison table: for the “Total timer I/O eMIOS”, changed

“13 ch” to “14 ch”

10-Aug-2010

(cont.)

16-Sep-2011 4

SPC560D30/SPC560D40 series block summary: – added definition for “AUTOSAR” acronym – changed “System watchdog timer” to “Software watchdog timer” LQFP64 pin configuration (top view): changed pin 6 from VPP_TEST

to VSS_HV Added section “Pad configuration during reset phases” Added section “Voltage supply pins” Added section “Pad types” Added section “System pins” Renamed and updated section “Functional ports” (was previously

section “Pin muxing”); update includes replacing all instances of WKUP with WKPU (WKPU is the correct abbreviation for Wakeup Unit)

Section “NVUSRO register”: edited content to separate configuration into electrical parameters and digital functionality

Added section “NVUSRO[WATCHDOG_EN] field description” Absolute maximum ratings: Removed “C” column from table Replaced “TBD” with “—” in T

min value cell of 3.3 V and 5 V

VDD

recommended operating conditions tables LQFP thermal characteristics: removed R

single layer board

θJB

conditions; updated footnote 4 I/O input DC electrical characteristics: removed footnote “All values

need to be confirmed during device validation”; updated I

LKG

characteristics

80/82 Doc ID 16315 Rev 5

SPC560D30x, SPC560D40x Revision history

Table 49. Document revision history (continued)

Date Revision Changes

MEDIUM configuration output buffer electrical characteristics:

= 100 µA” to “IOL= 100 µA” in VOL conditions

values

esus

EMI

values

16-Sep-2011

(cont.)

changed “I I/O consumption: replaced instances of “Root medium square” with

“Root mean square” Updated section “Voltage regulator electrical characteristics” Section “Low voltage detector electrical characteristics”: changed

title (was “Voltage monitor electrical characteristics”); added a fifth LVD (LVDHV3B); added event status flag names found in RGM chapter of device reference manual to POR module and LVD descriptions; replaced instances of “Low voltage monitor” with “Low voltage detector”; deleted note referencing power domain No. 2 (this domain is not present on the device); updated electrical characteristics table

Updated and renamed section “Power consumption” (was previously section “Low voltage domain power consumption”)

Program and erase specifications (code flash): updated symbols; updated t

Updated Flash memory read access timing EMI radiated emission measurement: updated S Updated FMPLL electrical characteristics

01-Dec-2011 5

Crystal oscillator and resonator connection scheme: inserted footnote about possibly requiring a series resistor

Fast internal RC oscillator (16 MHz) electrical characteristics: updated t

Section “Input impedance and ADC accuracy”: changed “V

FIRCSU

values

A/VA2

“VA2/VA” in Equation 13 ADC conversion characteristics: – updated conditions for sampling time V

= 5.0 V

– updated conditions for conversion time VDD =5.0 V

Updated Abbreviations

Removed Order codes tables.

Replaced “TBD” with “8.21 mA” in I

DD_HV(FLASH)

cell of On-chip

peripherals current consumption table

” to

Doc ID 16315 Rev 5 81/82

SPC560D30x, SPC560D40x

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82/82 Doc ID 16315 Rev 5

ST SPC560D30L3, SPC560D40L3, SPC560D30L1, SPC560D40L1 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

1 Introduction

1.1 Document overview

1.2 Description

2 Block diagram

3 Package pinouts and signal descriptions

3.1 Package pinouts

3.2 Pad configuration during reset phases

3.3 Voltage supply pins

3.4 Pad types

3.5 System pins

3.6 Functional ports

4 Electrical characteristics

4.1 Introduction

4.2 Parameter classification

4.3 NVUSRO register

4.3.1 NVUSRO[PAD3V5V] field description

4.3.2 NVUSRO[OSCILLATOR_MARGIN] field description

4.3.3 NVUSRO[WATCHDOG_EN] field description

4.4 Absolute maximum ratings

4.5 Recommended operating conditions

4.6 Thermal characteristics

4.6.1 Package thermal characteristics

4.6.2 Power considerations

4.7 I/O pad electrical characteristics

4.7.1 I/O pad types

4.7.2 I/O input DC characteristics

4.7.3 I/O output DC characteristics

4.7.4 Output pin transition times

4.7.5 I/O pad current specification

4.8 RESET electrical characteristics

4.9 Power management electrical characteristics

4.9.1 Voltage regulator electrical characteristics

4.9.2 Low voltage detector electrical characteristics

4.10 Power consumption

4.11 Flash memory electrical characteristics

4.11.1 Program/Erase characteristics

4.11.2 Flash power supply DC characteristics

4.11.3 Start-up/Switch-off timings

4.12 Electromagnetic compatibility (EMC) characteristics

4.12.1 Designing hardened software to avoid noise problems

4.12.2 Electromagnetic interference (EMI)

4.12.3 Absolute maximum ratings (electrical sensitivity)

4.14 FMPLL electrical characteristics

4.15 Fast internal RC oscillator (16 MHz) electrical characteristics

Table 40. Slow internal RC oscillator (128 kHz) electrical characteristics

4.17 ADC electrical characteristics

4.17.1 Introduction

4.17.2 Input impedance and ADC accuracy

4.17.3 ADC electrical characteristics

4.18 On-chip peripherals

4.18.1 Current consumption

4.18.2 DSPI characteristics

4.18.3 JTAG characteristics

5 Package characteristics

5.2 Package mechanical data

5.2.1 LQFP100

5.2.2 LQFP64

6 Ordering information

Appendix A Abbreviations

Revision history