This reference manual targets application developers. It provides complete information on
how to use the STM32F101xx, STM32F102xx, STM32F103xx and
STM32F105xx/STM32F107xx microcontroller memory and peripherals. The STM32F101xx,
STM32F102xx, STM32F103xx and STM32F105xx/STM32F107xx will be referred to as
STM32F10xxx throughout the document, unless otherwise specified.
The STM32F10xxx is a family of microcontrollers with different memory sizes, packages and
peripherals.
For ordering information, mechanical and electrical device characteristics please refer to the
low-, medium- and high-density STM32F101xx and STM32F103xx datasheets, to the low-
and medium-density STM32F102xx datasheets and to the STM32F105xx/STM32F107xx
connectivity line datasheet.
For information on programming, erasing and protection of the internal Flash memory
please refer to the STM32F10xxx Flash programming manual.
For information on the ARM Cortex™-M3 core, please refer to the Cortex™-M3 Technical Reference Manual.
Related documents
Available from www.arm.com:
■
Cortex™-M3 Technical Reference Manual, available from:
The following abbreviations are used in register descriptions:
read/write (rw)Software can read and write to these bits.
read-only (r)Software can only read these bits.
write-only (w)Software can only write to this bit. Reading the bit returns the reset
value.
read/clear (rc_w1) Software can read as well as clear this bit by writing 1. Writing ‘0’ has
no effect on the bit value.
read/clear (rc_w0) Software can read as well as clear this bit by writing 0. Writing ‘1’ has
no effect on the bit value.
read/clear by read
(rc_r)
Software can read this bit. Reading this bit automatically clears it to ‘0’.
Writing ‘0’ has no effect on the bit value.
read/set (rs)Software can read as well as set this bit. Writing ‘0’ has no effect on the
bit value.
read-only write
trigger (rt_w)
Software can read this bit. Writing ‘0’ or ‘1’ triggers an event but has no
effect on the bit value.
toggle (t)Software can only toggle this bit by writing ‘1’. Writing ‘0’ has no effect.
Reserved (Res.)Reserved bit, must be kept at reset value.
1.2 Glossary
●Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx
microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
●Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx
microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
●High-density devices are STM32F101xx and STM32F103xx microcontrollers where
the Flash memory density ranges between 256 and 512 Kbytes.
●Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
1.3 Peripheral availability
For peripheral availability and number across all STM32F10xxx sales types, please refer to
the low-, medium- and high-density STM32F101xx and STM32F103xx datasheets, to the
low- and medium-density STM32F102xx datasheets and to the connectivity line devices,
STM32F105xx/STM32F107xx.
Doc ID 13902 Rev 937/995
Memory and bus architectureRM0008
FLITF
Ch.1
Ch.2
Ch.7
Cor tex -M3
DMA1
ICode
DCode
System
AHB system bus
DMA Request
APB 1
Flash
Bridge 2
Bridge 1
Ch.1
Ch.2
Ch.5
DMA2
SRAM
FSMC
SDIO
APB2
DMA request
ADC3
GPIOC
USART1
TIM8
SPI1
TIM1
ADC2
ADC1
GPIOG
GPIOF
GPIOE
GPIOD
GPIOB
GPIOA
EXTI
AFIO
DAC SPI3/I2S
TIM2
PWR
BKP
bxCAN
USB
I2C2
I2C1
UART5
UART4
USART3
USART2
SPI2/I2S
IWDG
WWDG
RTC
TIM7
TIM6
TIM5
TIM4
TIM3
ai14800c
Bus matrix
DMA
DMA
Reset & clock
control (RCC)
2 Memory and bus architecture
2.1 System architecture
In low-, medium- and high-density devices, the main system consists of:
●Four masters:
–Cortex™-M3 core DCode bus (D-bus) and System bus (S-bus)
–GP-DMA1 & 2 (general-purpose DMA)
●Four slaves:
–Internal SRAM
–Internal Flash memory
–FSMC
–AHB to APB bridges (AHB2APBx), which connect all the APB peripherals
These are interconnected using a multilayer AHB bus architecture as shown in Figure 1:
Figure 1.System architecture
38/995 Doc ID 13902 Rev 9
RM0008Memory and bus architecture
FLITF
Ch.1
Ch.2
Ch.7
Cor tex -M3
DMA1
ICode
DCode
System
DMA request
APB 1
Flash
Bridge 2
Bridge 1
Ch.1
Ch.2
Ch.5
DMA2
SRAM
APB2
GPIOC
USART1
SPI1
TIM1
ADC2
ADC1
GPIOE
GPIOD
GPIOB
GPIOA
EXTI
AFIO
DAC
SPI3/I2S
TIM2
PWR
BKP
CAN1
CAN2
I2C2
I2C1
UART5
UART4
USART3
USART2
SPI2/I2S
IWDG
WWDG
RTC
TIM7
TIM6
TIM5
TIM4
TIM3
ai15810
Bus matrix
DMA
DMA
Reset & clock
control (RCC)
USB OTG FS
AHB system bus
Ethernet MAC
DMA
DMA request
In connectivity line devices the main system consists of:
●Five masters:
–Cortex™-M3 core DCode bus (D-bus) and System bus (S-bus)
–GP-DMA1 & 2 (general-purpose DMA)
–Ethernet DMA
●Three slaves:
–Internal SRAM
–Internal Flash memory
–AHB to APB bridges (AHB2APBx), which connect all the APB peripherals
These are interconnected using a multilayer AHB bus architecture as shown in Figure 2:
Figure 2.System architecture in connectivity line devices
ICode bus
This bus connects the Instruction bus of the Cortex™-M3 core to the Flash memory
instruction interface. Prefetching is performed on this bus.
Doc ID 13902 Rev 939/995
Memory and bus architectureRM0008
DCode bus
This bus connects the DCode bus (literal load and debug access) of the Cortex™-M3 core
to the Flash memory Data interface.
System bus
This bus connects the system bus of the Cortex™-M3 core (peripherals bus) to a BusMatrix
which manages the arbitration between the core and the DMA.
DMA bus
This bus connects the AHB master interface of the DMA to the BusMatrix which manages
the access of CPU DCode and DMA to SRAM, Flash memory and peripherals.
BusMatrix
The BusMatrix manages the access arbitration between the core system bus and the DMA
master bus. The arbitration uses a Round Robin algorithm. In connectivity line devices, the
BusMatrix is composed of five masters (CPU DCode, System bus, Ethernet DMA, DMA1
and DMA2 bus) and three slaves (FLITF, SRAM and AHB2APB bridges). In other devices,
the BusMatrix is composed of four masters (CPU DCode, System bus, DMA1 bus and
DMA2 bus) and four slaves (FLITF, SRAM, FSMC and AHB2APB bridges).
AHB peripherals are connected on system bus through a BusMatrix to allow DMA access.
AHB/APB bridges (APB)
The two AHB/APB bridges provide full synchronous connections between the AHB and the
2 APB buses. APB1 is limited to 36 MHz, APB2 operates at full speed (up to 72 MHz
depending on the device).
Refer to Table 1 on page 41 for the address mapping of the peripherals connected to each
bridge.
After each device reset, all peripheral clocks are disabled (except for the SRAM and FLITF).
Before using a peripheral you have to enable its clock in the RCC_AHBENR,
RCC_APB2ENR or RCC_APB1ENR register.
Note:When a 16- or 8-bit access is performed on an APB register, the access is transformed into
a 32-bit access: the bridge duplicates the 16- or 8-bit data to feed the 32-bit vector.
2.2 Memory organization
Program memory, data memory, registers and I/O ports are organized within the same linear
4-Gbyte address space.
The bytes are coded in memory in Little Endian format. The lowest numbered byte in a word
is considered the word’s least significant byte and the highest numbered byte the most
significant.
For the detailed mapping of peripheral registers, please refer to the related chapters.
The addressable memory space is divided into 8 main blocks, each of 512 MB.
All the memory areas that are not allocated to on-chip memories and peripherals are
considered “Reserved”). Refer to the Memory map figure in the corresponding product
datasheet.
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RM0008Memory and bus architecture
2.3 Memory map
See the datasheet corresponding to your device for a comprehensive diagram of the
memory map. Tab le 1 gives the boundary addresses of the peripherals available in all
STM32F10xxx devices.
Table 1.Register boundary addresses
Boundary addressPeripheralBusRegister map
0x5000 0000 - 0x5000 03FFUSB OTG FS
0x4003 0000 - 0x4FFF FFFFReserved
AHB
Section 26.14.6 on page 778
0x4002 8000 - 0x4002 9FFFEthernetSection 27.8.5 on page 946
0x4002 3400 - 0x4002 7FFFReserved
0x4002 3000 - 0x4002 33FFCRCSection 3.4.4 on page 52
0x4002 2000 - 0x4002 23FFFlash memory interface
0x4002 1400 - 0x4002 1FFFReserved
0x4002 1000 - 0x4002 13FFReset and clock control RCCSection 6.3.11 on page 102
AHB
0x4002 0800 - 0x4002 0FFFReserved
0x4002 0400 - 0x4002 07FFDMA2Section 10.4.7 on page 196
0x4002 0000 - 0x4002 03FFDMA1Section 10.4.7 on page 196
0x4001 8400 - 0x4001 7FFFReserved
0x4001 8000 - 0x4001 83FFSDIOSection 20.9.16 on page 510
0x4001 4000 - 0x4001 7FFFReserved
0x4001 3C00 - 0x4001 3FFFADC3Section 11.12.15 on page 231
0x4001 3800 - 0x4001 3BFFUSART1 Section 25.6.8 on page 693
0x4001 3400 - 0x4001 37FFTIM8 timerSection 13.4.21 on page 317
0x4001 3000 - 0x4001 33FFSPI1Section 23.5 on page 614
0x4001 2C00 - 0x4001 2FFFTIM1 timerSection 13.4.21 on page 317
0x4001 2800 - 0x4001 2BFFADC2Section 11.12.15 on page 231
0x4001 2400 - 0x4001 27FFADC1Section 11.12.15 on page 231
0x4001 2000 - 0x4001 23FFGPIO Port GSection 8.5 on page 167
APB2
0x4001 1C00 - 0x4001 1FFFGPIO Port FSection 8.5 on page 167
0x4001 1800 - 0x4001 1BFFGPIO Port ESection 8.5 on page 167
0x4001 1400 - 0x4001 17FFGPIO Port DSection 8.5 on page 167
0x4001 1000 - 0x4001 13FFGPIO Port CSection 8.5 on page 167
0x4001 0C00 - 0x4001 0FFFGPIO Port BSection 8.5 on page 167
0x4001 0800 - 0x4001 0BFFGPIO Port ASection 8.5 on page 167
0x4001 0400 - 0x4001 07FFEXTISection 9.3.7 on page 181
0x4001 0000 - 0x4001 03FFAFIOSection 8.5 on page 167
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Memory and bus architectureRM0008
Table 1.Register boundary addresses (continued)
Boundary addressPeripheralBusRegister map
0x4000 7800 - 0x4000 FFFFReserved
0x4000 7400 - 0x4000 77FFDACSection 12.5.14 on page 252
0x4000 7000 - 0x4000 73FFPower control PWRSection 4.4.3 on page 65
0x4000 2800 - 0x4000 2BFFRTCSection 16.4.7 on page 398
0x4000 1800 - 0x4000 27FFReserved
0x4000 1400 - 0x4000 17FFTIM7 timerSection 15.4.9 on page 386
0x4000 1000 - 0x4000 13FFTIM6 timerSection 15.4.9 on page 386
0x4000 0C00 - 0x4000 0FFFTIM5 timerSection 14.4.19 on page 373
0x4000 0800 - 0x4000 0BFFTIM4 timerSection 14.4.19 on page 373
0x4000 0400 - 0x4000 07FFTIM3 timerSection 14.4.19 on page 373
0x4000 0000 - 0x4000 03FFTIM2 timerSection 14.4.19 on page 373
1. This shared SRAM can be fully accessed only in low-, medium- and high-density devices, not in connectivity line devices.
2.3.1 Embedded SRAM
The STM32F10xxx features 64 Kbytes of static SRAM. It can be accessed as bytes, halfwords (16 bits) or full words (32 bits). The SRAM start address is 0x2000 0000.
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2.3.2 Bit banding
The Cortex™-M3 memory map includes two bit-band regions. These regions map each
word in an alias region of memory to a bit in a bit-band region of memory. Writing to a word
in the alias region has the same effect as a read-modify-write operation on the targeted bit in
the bit-band region.
In the STM32F10xxx both peripheral registers and SRAM are mapped in a bit-band region.
This allows single bit-band write and read operations to be performed.
A mapping formula shows how to reference each word in the alias region to a corresponding
bit in the bit-band region. The mapping formula is:
Table 5.Flash module organization (connectivity line devices)
BlockNameBase addressesSize (bytes)
Page 00x0800 0000 - 0x0800 07FF2 Kbytes
Page 10x0800 0800 - 0x0800 0FFF2 Kbytes
Page 2 0x0800 1000 - 0x0800 17FF2 Kbytes
Main memory
Page 30x0800 1800 - 0x0800 1FFF2 Kbytes
.
.
.
.
.
.
Page 1270x0803 F800 - 0x0803 FFFF2 Kbytes
System memory0x1FFF B000 - 0x1FFF F7FF18 Kbytes
Information block
Option Bytes0x1FFF F800 - 0x1FFF F80F16
FLASH_ACR0x4002 2000 - 0x4002 20034
FLASH_KEYR0x4002 2004 - 0x4002 20074
FLASH_OPTKEYR0x4002 2008 - 0x4002 200B4
Flash memory
interface
registers
FLASH_SR0x4002 200C - 0x4002 200F4
FLASH_CR0x4002 2010 - 0x4002 20134
FLASH_AR0x4002 2014 - 0x4002 20174
Reserved0x4002 2018 - 0x4002 201B4
FLASH_OBR0x4002 201C - 0x4002 201F4
FLASH_WRPR0x4002 2020 - 0x4002 20234
Note:For further information on the Flash memory interface registers, please refer to the
STM32F10xxx Flash programming manual.
.
.
.
Reading the Flash memory
Flash memory instructions and data access are performed through the AHB bus. The
prefetch block is used for instruction fetches through the ICode bus. Arbitration is performed
in the Flash memory interface, and priority is given to data access on the DCode bus.
Read accesses can be performed with the following configuration options:
●Latency: number of wait states for a read operation programmed on-the-fly
●Prefetch buffer (2 x 64-bit blocks): it is enabled after reset; a whole block can be
replaced with a single read from the Flash memory as the size of the block matches the
bandwidth of the Flash memory. Thanks to the prefetch buffer, faster CPU execution is
possible as the CPU fetches one word at a time with the next word readily available in
the prefetch buffer
●Half cycle: for power optimization
Doc ID 13902 Rev 947/995
Memory and bus architectureRM0008
Note:1These options should be used in accordance with the Flash memory access time. The wait
states represent the ratio of the SYSCLK (system clock) period to the Flash memory access
time:
zero wait state, if 0 < SYSCLK
one wait state, if 24 MHz < SYSCLK
two wait states, if 48 MHz < SYSCLK
24 MHz
48 MHz
72 MHz
2Half cycle configuration is not available in combination with a prescaler on the AHB. The
system clock (SYSCLK) should be equal to the HCLK clock. This feature can therefore be
used only with a low-frequency clock of 8 MHz or less. It can be generated from the HSI or
the HSE but not from the PLL.
3The prefetch buffer must be kept on when using a prescaler different from 1 on the AHB
clock.
4The prefetch buffer must be switched on/off only when SYSCLK is lower than 24 MHz. The
prefetch buffer is usually switched on/off during the initialization routine, while the
microcontroller is running on the internal 8 MHz RC (HSI) oscillator.
5Using DMA: DMA accesses Flash memory on the DCode bus and has priority over ICode
instructions. The DMA provides one free cycle after each transfer. Some instructions can be
performed together with DMA transfer.
Programming and erasing the Flash memory
The Flash memory can be programmed 16 bits (half words) at a time.
The Flash memory erase operation can be performed at page level or on the whole Flash
area (mass-erase). The mass-erase does not affect the information blocks.
To ensure that there is no over-programming, the Flash Programming and Erase Controller
blocks are clocked by a fixed clock.
The End of write operation (programming or erasing) can trigger an interrupt. This interrupt
can be used to exit from WFI mode, only if the FLITF clock is enabled. Otherwise, the
interrupt is served only after an exit from WFI.
Note:For further information on Flash memory operations and register configurations, please refer
to the STM32F10xxx Flash programming manual.
2.4 Boot configuration
In the STM32F10xxx, 3 different boot modes can be selected through BOOT[1:0] pins as
shown in Ta bl e 6 .
Table 6.Boot modes
Boot mode selection pins
Boot modeAliasing
BOOT1BOOT0
x0Main Flash memoryMain Flash memory is selected as boot space
01System memorySystem memory is selected as boot space
11Embedded SRAMEmbedded SRAM is selected as boot space
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RM0008Memory and bus architecture
The values on the BOOT pins are latched on the 4th rising edge of SYSCLK after a Reset. It
is up to the user to set the BOOT1 and BOOT0 pins after Reset to select the required boot
mode.
The BOOT pins are also re-sampled when exiting from Standby mode. Consequently they
must be kept in the required Boot mode configuration in Standby mode. After this startup
delay has elapsed, the CPU fetches the top-of-stack value from address 0x0000 0000, then
starts code execution from the boot memory starting from 0x0000 0004.
Due to its fixed memory map, the code area starts from address 0x0000 0000 (accessed
through the ICode/DCode buses) while the data area (SRAM) starts from address
0x2000 0000 (accessed through the system bus). The Cortex-M3 CPU always fetches the
reset vector on the ICode bus, which implies to have the boot space available only in the
code area (typically, Flash memory). STM32F10xxx microcontrollers implement a special
mechanism to be able to boot also from SRAM and not only from main Flash memory and
System memory.
Depending on the selected boot mode main Flash memory, System memory or SRAM is
accessible as follows:
●Boot from main Flash memory: the main Flash memory is aliased in the boot memory
space (0x0000 0000), but still accessible from its original memory space (0x800 0000).
In other words, the Flash memory contents can be accessed starting from address
0x0000 0000 or 0x800 0000.
●Boot from System memory: the System memory is aliased in the boot memory space
(0x0000 0000), but still accessible from its original memory space (0x1FFF B000 in
connectivity line devices, 0x1FFF F000 in other devices).
●Boot from the embedded SRAM: SRAM is accessible only at address 0x2000 0000.
Note:When booting from SRAM, in the application initialization code, you have to relocate the
vector table in SRAM using the NVIC exception table and offset register.
Embedded boot loader
The embedded boot loader is located in the System memory, programmed by ST during
production. It is used to reprogram the Flash memory with one of the available serial
interfaces:
●In low-, medium- and high-density devices the bootloader is activated through the
USART1 interface. For further details please refer to AN2606.
●In connectivity line devices the bootloader can be activated through one of the following
interfaces: USART1, USART2 (remapped), CAN2 (remapped) or USB OTG FS in
Device mode (DFU: device firmware upgrade).
The USART peripheral operates with the internal 8 MHz oscillator (HSI). The CAN and
USB OTG FS, however, can only function if an external 8 MHz, 14.7456 MHz or
25 MHz clock (HSE) is present. For further details, please refer to AN2662.
Doc ID 13902 Rev 949/995
CRC calculation unitRM0008
3 CRC calculation unit
Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx
microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
Medium-densitydevices are STM32F101xx, STM32F102xx and STM32F103xx
microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
High-density devices are STM32F101xx and STM32F103xx microcontrollers where the
Flash memory density ranges between 256 and 512 Kbytes.
Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
This section applies to the whole STM32F10xxx family, unless otherwise specified.
3.1 CRC introduction
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit
data word and a fixed generator polynomial.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of
the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location.
3.2 CRC main features
●Uses CRC-32 (Ethernet) polynomial: 0x4C11DB7
32
–X
●Single input/output 32-bit data register
●CRC computation done in 4 AHB clock cycles (HCLK)
●General-purpose 8-bit register (can be used for temporary storage)
The CRC calculation unit mainly consists of a single 32-bit data register, which:
●is used as an input register to enter new data in the CRC calculator (when writing into
the register)
●holds the result of the previous CRC calculation (when reading the register)
Each write operation into the data register creates a combination of the previous CRC value
and the new one (CRC computation is done on the whole 32-bit data word, and not byte per
byte).
The write operation is stalled until the end of the CRC computation, thus allowing back-toback write accesses or consecutive write and read accesses.
The CRC calculator can be reset to FFFF FFFFh with the RESET control bit in the CRC_CR
register. This operation does not affect the contents of the CRC_IDR register.
3.4 CRC registers
The CRC calculation unit contains two data registers and a control register.
3.4.1 Data register (CRC_DR)
Address offset: 0x00
Reset value: 0xFFFF FFFF
31302928272625242322212019181716
DR [31:16]
rwrwrwrwrwrwrwrwrwrwrwrwrwrwrwrw
1514131211109876543210
DR [15:0]
rwrwrwrwrwrwrwrwrwrwrwrwrwrwrwrw
Bits 31:0 Data register bits
Used as an input register when writing new data into the CRC calculator.
Holds the previous CRC calculation result when it is read.
Doc ID 13902 Rev 951/995
CRC calculation unitRM0008
3.4.2 Independent data register (CRC_IDR)
Address offset: 0x04
Reset value: 0x0000 0000
1514131211109876543210
Reserved
Bits 31:8Reserved
Bits 7:0 General-purpose 8-bit data register bits
Can be used as a temporary storage location for one byte.
This register is not affected by CRC resets generated by the RESET bit in the CRC_CR
register.
rwrwrwrwrwrwrwrw
IDR[7:0]
3.4.3 Control register (CRC_CR)
Address offset: 0x08
Reset value: 0x0000 0000
31302928272625242322212019181716
Reserved
1514131211109876543210
Reserved
Bits 31:1Reserved
RESET
w
RESET bit
Bit 0
Resets the CRC calculation unit and sets the data register to FFFF FFFFh.
This bit can only be set, it is automatically cleared by hardware.
3.4.4 CRC register map
The following table provides the CRC register map and reset values.
Table 7.CRC calculation unit register map and reset values
OffsetRegister31-24 23-1615-876543210
CRC_DR
0x00
Reset value
CRC_IDR
0x04
Reset value
CRC_CR
0x08
Reset value
52/995 Doc ID 13902 Rev 9
Reserved
Reserved
Data register
0xFFFF FFFF
Independent data register
0x00
Reserved0RESET
0
RM0008Power control (PWR)
A/D converter
V
DDA
V
DD
V
SSA
V
REF+
V
BAT
V
SS
I/O Ring
(V
DD
)
(from 2.4 V up to V
DDA
)
BKP registers
Temp. sensor
Reset block
Standby circuitry
PLL
(Wakeup logic,
IWDG)
RTC
Voltage Regulator
Core
Memories
digital
peripherals
Low voltage detector
V
REF-
V
DDA
domain
V
DD
domain
1.8 V domain
Backup domain
LSE crystal 32K osc
RCC BDCR register
(V
SSA
)
(V
SS
)
4 Power control (PWR)
Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx
microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
Medium-densitydevices are STM32F101xx, STM32F102xx and STM32F103xx
microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
High-density devices are STM32F101xx and STM32F103xx microcontrollers where the
Flash memory density ranges between 256 and 512 Kbytes.
Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
This section applies to the whole STM32F10xxx family, unless otherwise specified.
4.1 Power supplies
The device requires a 2.0-to-3.6 V operating voltage supply (VDD). An embedded regulator
is used to supply the internal 1.8 V digital power.
The real-time clock (RTC) and backup registers can be powered from the V
the main V
supply is powered off.
DD
Figure 4.Power supply overview
voltage when
BAT
Note:1V
DDA
and V
must be connected to VDD and VSS, respectively.
SSA
Doc ID 13902 Rev 953/995
Power control (PWR)RM0008
4.1.1 Independent A/D converter supply and reference voltage
To improve conversion accuracy, the ADC has an independent power supply which can be
separately filtered and shielded from noise on the PCB.
●The ADC voltage supply input is available on a separate V
●An isolated supply ground connection is provided on pin V
When available (according to package), V
must be tied to V
REF-
On 100-pin and 144- pin packages
To ensure a better accuracy on low voltage inputs, the user can connect a separate external
reference voltage ADC input on V
2.4 V to V
DDA
.
REF+
and V
. The voltage on V
REF-
On 64-pin packages
DDA
SSA
SSA
pin.
.
.
can range from
REF+
The V
voltage supply (V
REF+
and V
pins are not available, they are internally connected to the ADC
REF-
) and ground (V
DDA
4.1.2 Battery backup domain
To retain the content of the Backup registers and supply the RTC function when V
turned off, V
by another source.
The V
BAT
the RTC to operate even when the main digital supply (V
V
supply is controlled by the Power Down Reset embedded in the Reset block.
BAT
Warning:During t
pin can be connected to an optional standby voltage supplied by a battery or
BAT
pin powers the RTC unit, the LSE oscillator and the PC13 to PC15 IOs, allowing
is detected, the power switch between V
RSTTEMPO
connected to V
During the startup phase, if V
t
RSTTEMPO
and V
DD
> V
through an internal diode connected between V
power switch (V
If the power supply/battery connected to the V
support this current injection, it is strongly recommended to
connect an external low-drop diode between this power
supply and the V
).
SSA
) is turned off. The switch to the
DD
(temporization at VDD startup) or after a PDR
and VDD remains
BAT
BAT
.
is established in less than
DD
(Refer to the datasheet for the value of t
+ 0.6 V, a current may be injected into V
BAT
DD
BAT
BAT
BAT
).
pin.
DD
RSTTEMPO
BAT
and the
pin cannot
is
)
If no external battery is used in the application, it is recommended to connect V
externally to VDD through a 100 nF external ceramic capacitor (for more details refer to
AN2586).
When the backup domain is supplied by V
following functions are available:
●PC14 and PC15 can be used as either GPIO or LSE pins
●PC13 can be used as GPIO, TAMPER pin, RTC Calibration Clock, RTC Alarm or
second output (refer to Section 5: Backup registers (BKP) on page 66)
54/995 Doc ID 13902 Rev 9
(analog switch connected to VDD), the
DD
BAT
RM0008Power control (PWR)
Note:Due to the fact that the switch only sinks a limited amount of current (3 mA), the use of
GPIOs PC13 to PC15 in output mode is restricted: the speed has to be limited to 2 MHz with
a maximum load of 30 pF and these IOs must not be used as a current source (e.g. to drive
an LED).
When the backup domain is supplied by V
V
is not present), the following functions are available:
DD
●PC14 and PC15 can be used as LSE pins only
●PC13 can be used as TAMPER pin, RTC Alarm or Second output (refer to section
(analog switch connected to V
BAT
Section 5.4.2: RTC clock calibration register (BKP_RTCCR) on page 68).
4.1.3 Voltage regulator
The voltage regulator is always enabled after Reset. It works in three different modes
depending on the application modes.
●In Run mode, the regulator supplies full power to the 1.8 V domain (core, memories
and digital peripherals).
●In Stop mode the regulator supplies low-power to the 1.8 V domain, preserving
contents of registers and SRAM
●In Standby Mode, the regulator is powered off. The contents of the registers and SRAM
are lost except for the Standby circuitry and the Backup Domain.
4.2 Power supply supervisor
4.2.1 Power on reset (POR)/power down reset (PDR)
The device has an integrated POR/PDR circuitry that allows proper operation starting
from/down to 2 V.
because
BAT
The device remains in Reset mode when V
V
POR/PDR
, without the need for an external reset circuit. For more details concerning the
DD/VDDA
is below a specified threshold,
power on/power down reset threshold, refer to the electrical characteristics of the datasheet.
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Power control (PWR)RM0008
VDD/V
DDA
Reset
40 mV
hysteresis
POR
PDR
Temporization
t
RSTTEMPO
VDD/V
DDA
PVD output
100 mV
hysteresis
PVD threshold
Figure 5.Power on reset/power down reset waveform
4.2.2 Programmable voltage detector (PVD)
You can use the PVD to monitor the VDD/V
power supply by comparing it to a threshold
DDA
selected by the PLS[2:0] bits in the Power control register (PWR_CR).
The PVD is enabled by setting the PVDE bit.
A PVDO flag is available, in the Power control/status register (PWR_CSR), to indicate if
V
DD/VDDA
is higher or lower than the PVD threshold. This event is internally connected to
the EXTI line16 and can generate an interrupt if enabled through the EXTI registers. The
PVD output interrupt can be generated when V
and/or when V
DD/VDDA
rises above the PVD threshold depending on EXTI line16
DD/VDDA
drops below the PVD threshold
rising/falling edge configuration. As an example the service routine could perform
emergency shutdown tasks.
Figure 6.PVD thresholds
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RM0008Power control (PWR)
4.3 Low-power modes
By default, the microcontroller is in Run mode after a system or a power Reset. Several lowpower modes are available to save power when the CPU does not need to be kept running,
for example when waiting for an external event. It is up to the user to select the mode that
gives the best compromise between low-power consumption, short startup time and
available wakeup sources.
The STM32F10xxx devices feature three low-power modes:
●Sleep mode (CPU clock off, all peripherals including Cortex-M3 core peripherals like
NVIC, SysTick, etc. are kept running)
●Stop mode (all clocks are stopped)
●Standby mode (1.8V domain powered-off)
In addition, the power consumption in Run mode can be reduce by one of the following
means:
●Slowing down the system clocks
●Gating the clocks to the APB and AHB peripherals when they are unused.
Table 8.Low-power mode summary
Effect on
Mode nameEntrywakeup
Effect on 1.8V
domain clocks
V
DD
domain
clocks
Voltag e
regulator
Sleep
WFIAny interruptCPU clock OFF
(Sleep now or
Sleep-on -
WFEWakeup event
exit)
PDDS and LPDS
Stop
bits +
SLEEPDEEP bit
+ WFI or WFE
PDDS bit +
Standby
SLEEPDEEP bit
+ WFI or WFE
4.3.1 Slowing down system clocks
In Run mode the speed of the system clocks (SYSCLK, HCLK, PCLK1, PCLK2) can be
reduced by programming the prescaler registers. These prescalers can also be used to slow
down peripherals before entering Sleep mode.
For more details refer to Section 6.3.2: Clock configuration register (RCC_CFGR).
The Sleep mode is entered by executing the WFI (Wait For Interrupt) or WFE (Wait for
Event) instructions. Two options are available to select the Sleep mode entry mechanism,
depending on the SLEEPONEXIT bit in the Cortex-M3 System Control register:
●Sleep-now: if the SLEEPONEXIT bit is cleared, the MCU enters Sleep mode as soon
as WFI or WFE instruction is executed.
●Sleep-on-exit: if the SLEEPONEXIT bit is set, the MCU enters Sleep mode as soon as
it exits the lowest priority ISR.
In the Sleep mode, all I/O pins keep the same state as in the Run mode.
Refer to Ta bl e 9 and Ta bl e 1 0 for details on how to enter Sleep mode.
Exiting Sleep mode
If the WFI instruction is used to enter Sleep mode, any peripheral interrupt acknowledged by
the nested vectored interrupt controller (NVIC) can wake up the device from Sleep mode.
If the WFE instruction is used to enter Sleep mode, the MCU exits Sleep mode as soon as
an event occurs. The wakeup event can be generated either by:
●enabling an interrupt in the peripheral control register but not in the NVIC, and enabling
the SEVONPEND bit in the Cortex-M3 System Control register. When the MCU
resumes from WFE, the peripheral interrupt pending bit and the peripheral NVIC IRQ
channel pending bit (in the NVIC interrupt clear pending register) have to be cleared.
●or configuring an external or internal EXTI line in event mode. When the CPU resumes
from WFE, it is not necessary to clear the peripheral interrupt pending bit or the NVIC
IRQ channel pending bit as the pending bit corresponding to the event line is not set.
This mode offers the lowest wakeup time as no time is wasted in interrupt entry/exit.
Refer to Ta bl e 9 and Ta bl e 1 0 for more details on how to exit Sleep mode.
58/995 Doc ID 13902 Rev 9
RM0008Power control (PWR)
Table 9.Sleep-now
Sleep-now modeDescription
WFI (Wait for Interrupt) or WFE (Wait for Event) while:
Mode entry
Mode exit
Wakeup latencyNone
Table 10.Sleep-on-exit
Sleep-on-exitDescription
Mode entry
Mode exitInterrupt: refer to Table 53: Vector table for other STM32F10xxx devices.
Wakeup latencyNone
– SLEEPDEEP = 0 and
– SLEEPONEXIT = 0
Refer to the Cortex™-M3 System Control register.
If WFI was used for entry:
Interrupt: Refer to Table 53: Vector table for other STM32F10xxx devices
If WFE was used for entry
Wakeup event: Refer to Section 9.2.3: Wakeup event management
WFI (wait for interrupt) while:
– SLEEPDEEP = 0 and
– SLEEPONEXIT = 1
Refer to the Cortex™-M3 System Control register.
4.3.4 Stop mode
The Stop mode is based on the Cortex-M3 deepsleep mode combined with peripheral clock
gating. The voltage regulator can be configured either in normal or low-power mode. In Stop
mode, all clocks in the 1.8 V domain are stopped, the PLL, the HSI and the HSE RC
oscillators are disabled. SRAM and register contents are preserved.
In the Stop mode, all I/O pins keep the same state as in the Run mode.
Entering Stop mode
Refer to Ta bl e 1 1 for details on how to enter the Stop mode.
To further reduce power consumption in Stop mode, the internal voltage regulator can be
put in low-power mode. This is configured by the LPDS bit of the Power control register
(PWR_CR).
If Flash memory programming is ongoing, the Stop mode entry is delayed until the memory
access is finished.
If an access to the APB domain is ongoing, The Stop mode entry is delayed until the APB
access is finished.
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Power control (PWR)RM0008
In Stop mode, the following features can be selected by programming individual control bits:
●Independent watchdog (IWDG): the IWDG is started by writing to its Key register or by
hardware option. Once started it cannot be stopped except by a Reset. See
Section 17.3 in Section 17: Independent watchdog (IWDG).
●real-time clock (RTC): this is configured by the RTCEN bit in the Backup domain control
register (RCC_BDCR)
●Internal RC oscillator (LSI RC): this is configured by the LSION bit in the Control/status
register (RCC_CSR).
●External 32.768 kHz oscillator (LSE OSC): this is configured by the LSEON bit in the
Backup domain control register (RCC_BDCR).
The ADC or DAC can also consume power during the Stop mode, unless they are disabled
before entering it. To disable them, the ADON bit in the ADC_CR2 register and the ENx bit
in the DAC_CR register must both be written to 0.
Exiting Stop mode
Refer to Ta bl e 1 1 for more details on how to exit Stop mode.
When exiting Stop mode by issuing an interrupt or a wakeup event, the HSI RC oscillator is
selected as system clock.
When the voltage regulator operates in low-power mode, an additional startup delay is
incurred when waking up from Stop mode. By keeping the internal regulator ON during Stop
mode, the consumption is higher although the startup time is reduced.
Table 11.Stop mode
Mode entry
Mode exit
Wakeup latencyHSI RC wakeup time + regulator wakeup time from Low-power mode
4.3.5 Standby mode
The Standby mode allows to achieve the lowest power consumption. It is based on the
Cortex-M3 deepsleep mode, with the voltage regulator disabled. The 1.8 V domain is
consequently powered off. The PLL, the HSI oscillator and the HSE oscillator are also
Stop modeDescription
WFI (Wait for Interrupt) or WFE (Wait for Event) while:
– Set SLEEPDEEP bit in Cortex™-M3 System Control register
– Clear PDDS bit in Power Control register (PWR_CR)
– Select the voltage regulator mode by configuring LPDS bit in PWR_CR
Note: To enter Stop mode, all EXTI Line pending bits (in Pending register
(EXTI_PR)) and RTC Alarm flag must be reset. Otherwise, the Stop mode
entry procedure is ignored and program execution continues.
If WFI was used for entry:
Any EXTI Line configured in Interrupt mode (the corresponding EXTI
Interrupt vector must be enabled in the NVIC). Refer to Table 53: Vector
table for other STM32F10xxx devices on page 172.
If WFE was used for entry:
Any EXTI Line configured in event mode. Refer to Section 9.2.3: Wakeup
event management on page 175
60/995 Doc ID 13902 Rev 9
RM0008Power control (PWR)
switched off. SRAM and register contents are lost except for registers in the Backup domain
and Standby circuitry (see Figure 4).
Entering Standby mode
Refer to Ta bl e 1 2 for more details on how to enter Standby mode.
In Standby mode, the following features can be selected by programming individual control
bits:
●Independent watchdog (IWDG): the IWDG is started by writing to its Key register or by
hardware option. Once started it cannot be stopped except by a reset. See
Section 17.3 in Section 17: Independent watchdog (IWDG).
●real-time clock (RTC): this is configured by the RTCEN bit in the Backup domain control
register (RCC_BDCR)
●Internal RC oscillator (LSI RC): this is configured by the LSION bit in the Control/status
register (RCC_CSR).
●External 32.768 kHz oscillator (LSE OSC): this is configured by the LSEON bit in the
Backup domain control register (RCC_BDCR)
Exiting Standby mode
The microcontroller exits Standby mode when an external Reset (NRST pin), IWDG Reset,
a rising edge on WKUP pin or an RTC alarm occurs. All registers are reset after wakeup
from Standby except for Power control/status register (PWR_CSR).
After waking up from Standby mode, program execution restarts in the same way as after a
Reset (boot pins sampling, vector reset is fetched, etc.). The SBF status flag in the Powe r
control/status register (PWR_CSR) indicates that the MCU was in Standby mode.
Refer to Ta bl e 1 2 for more details on how to exit Standby mode.
Table 12.Standby mode
Standby modeDescription
WFI (Wait for Interrupt) or WFE (Wait for Event) while:
Mode entry
– Set SLEEPDEEP in Cortex™-M3 System Control register
– Set PDDS bit in Power Control register (PWR_CR)
– Clear WUF bit in Power Control/Status register (PWR_CSR)
Mode exit
WKUP pin rising edge, RTC alarm, external Reset in
Reset.
NRST pin, IWDG
Wakeup latencyRegulator start up. Reset phase
I/O states in Standby mode
In Standby mode, all I/O pins are high impedance except:
●Reset pad (still available)
●TAMPER pin if configured for tamper or calibration out
●WKUP pin, if enabled
Doc ID 13902 Rev 961/995
Power control (PWR)RM0008
Debug mode
By default, the debug connection is lost if the application puts the MCU in Stop or Standby
mode while the debug features are used. This is due to the fact that the Cortex™-M3 core is
no longer clocked.
However, by setting some configuration bits in the DBGMCU_CR register, the software can
be debugged even when using the low-power modes extensively. For more details, refer to
Section 29.16.1: Debug support for low-power modes.
4.3.6 Auto-wakeup (AWU) from low-power mode
The RTC can be used to wakeup the MCU from low-power mode without depending on an
external interrupt (Auto-wakeup mode). The RTC provides a programmable time base for
waking up from Stop or Standby mode at regular intervals. For this purpose, two of the three
alternative RTC clock sources can be selected by programming the RTCSEL[1:0] bits in the
This clock source provides a precise time base with very low-power consumption (less
than 1µA added consumption in typical conditions)
●Low-power internal RC Oscillator (LSI RC)
This clock source has the advantage of saving the cost of the 32.768 kHz crystal. This
internal RC Oscillator is designed to add minimum power consumption.
To wakeup from Stop mode with an RTC alarm event, it is necessary to:
●Configure the EXTI Line 17 to be sensitive to rising edge
●Configure the RTC to generate the RTC alarm
To wakeup from Standby mode, there is no need to configure the EXTI Line 17.
4.4 Power control registers
4.4.1 Power control register (PWR_CR)
Address offset: 0x00
Reset value: 0x0000 0000 (reset by wakeup from Standby mode)
31302928272625242322212019181716
1514131211109876543210
Reserved
Bits 31:9Reserved, always read as 0.
Reserved
DBPPLS[2:0]PVDECSBF CWUF PDDSLPDS
rwrwrwrwrwrc_w1 rc_w1rwrw
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RM0008Power control (PWR)
Bit 8 DBP: Disable backup domain write protection.
In reset state, the RTC and backup registers are protected against parasitic write access.
This bit must be set to enable write access to these registers.
0: Access to RTC and Backup registers disabled
1: Access to RTC and Backup registers enabled
Note: If the HSE divided by 128 is used as the RTC clock, this bit must remain set to 1.
Bits 7:5 PLS[2:0]: PVD level selection.
These bits are written by software to select the voltage threshold detected by the Power
Voltage Detector
Note: Refer to the electrical characteristics of the datasheet for more details.
Bit 4 PVDE: Power voltage detector enable.
This bit is set and cleared by software.
0: PVD disabled
1: PVD enabled
Bit 3 CSBF: Clear standby flag.
This bit is always read as 0.
0: No effect
1: Clear the SBF Standby Flag (write).
Bit 2 CWUF: Clear wakeup flag.
This bit is always read as 0.
0: No effect
1: Clear the WUF Wakeup Flag after 2 System clock cycles. (write)
Bit 1 PDDS: Power down deepsleep.
This bit is set and cleared by software. It works together with the LPDS bit.
0: Enter Stop mode when the CPU enters Deepsleep. The regulator status depends on the
LPDS bit.
1: Enter Standby mode when the CPU enters Deepsleep.
Bit 0 LPDS: Low-power deepsleep.
This bit is set and cleared by software. It works together with the PDDS bit.
0: Voltage regulator on during Stop mode
1: Voltage regulator in low-power mode during Stop mode
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Power control (PWR)RM0008
4.4.2 Power control/status register (PWR_CSR)
Address offset: 0x04
Reset value: 0x0000 0000 (not reset by wakeup from Standby mode)
Additional APB cycles are needed to read this register versus a standard APB read.
31302928272625242322212019181716
Reserved
1514131211109876543210
Reserved
Bits 31:9 Reserved, always read as 0.
Bit 8 EWUP: Enable WKUP pin
This bit is set and cleared by software.
0: WKUP pin is used for general purpose I/O. An event on the WKUP pin does not wakeup
the device from Standby mode.
1: WKUP pin is used for wakeup from Standby mode and forced in input pull down
configuration (rising edge on WKUP pin wakes-up the system from Standby mode).
Note: This bit is reset by a system Reset.
Bits 7:3 Reserved, always read as 0.
Bit 2 PVDO: PVD output
This bit is set and cleared by hardware. It is valid only if PVD is enabled by the PVDE bit.
0: V
1: V
DD/VDDA
DD/VDDA
is higher than the PVD threshold selected with the PLS[2:0] bits.
is lower than the PVD threshold selected with the PLS[2:0] bits.
Note: The PVD is stopped by Standby mode. For this reason, this bit is equal to 0 after
Standby or reset until the PVDE bit is set.
Bit 1 SBF: Standby flag
This bit is set by hardware and cleared only by a POR/PDR (power on reset/power down reset)
or by setting the CSBF bit in the Power control register (PWR_CR)
0: Device has not been in Standby mode
1: Device has been in Standby mode
Bit 0 WUF: Wakeup flag
This bit is set by hardware and cleared only by a POR/PDR (power on reset/power down
reset) or by setting the CWUF bit in the Power control register (PWR_CR)
0: No wakeup event occurred
1: A wakeup event was received from the WKUP pin or from the RTC alarm
Note: An additional wakeup event is detected if the WKUP pin is enabled (by setting the
EWUP bit) when the WKUP pin level is already high.
EWUP
rwrrr
Reserved
PVDOSBFWUF
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RM0008Power control (PWR)
4.4.3 PWR register map
The following table summarizes the PWR registers.
Table 13.PWR register map and reset values
OffsetRegister
0x000
0x004
313029282726252423222120191817161514131211
PWR_CR
Reset value000000000
PWR_CSR
Reset value0000
Reserved
Reserved
987654321
10
PLS[2:0]
DBP
EWUP
PVDE
Reserved
CSBF
PDDS
CWUF
SBF
PVDO
Refer to Table 1 on page 41 for the register boundary addresses.
0
LPDS
WUF
Doc ID 13902 Rev 965/995
Backup registers (BKP)RM0008
5 Backup registers (BKP)
Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx
microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
Medium-densitydevices are STM32F101xx, STM32F102xx and STM32F103xx
microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
High-density devices are STM32F101xx and STM32F103xx microcontrollers where the
Flash memory density ranges between 256 and 512 Kbytes.
Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
This Section applies to the whole STM32F10xxx family, unless otherwise specified.
5.1 BKP introduction
The backup registers are forty two 16-bit registers for storing 84 bytes of user application
data. They are implemented in the backup domain that remains powered on by V
the V
power is switched off. They are not reset when the device wakes up from Standby
DD
mode or by a system reset or power reset.
BAT
when
In addition, the BKP control registers are used to manage the Tamper detection feature and
RTC calibration.
After reset, access to the Backup registers and RTC is disabled and the Backup domain
(BKP) is protected against possible parasitic write access. To enable access to the Backup
registers and the RTC, proceed as follows:
●enable the power and backup interface clocks by setting the PWREN and BKPEN bits
in the RCC_APB1ENR register
●set the DBP bit the Power Control Register (PWR_CR) to enable access to the Backup
registers and RTC.
5.2 BKP main features
●20-byte data registers (in medium-density and low-density devices) or 84-byte data
registers (in high-density and connectivity line devices)
●Status/control register for managing tamper detection with interrupt capability
●Calibration register for storing the RTC calibration value
●Possibility to output the RTC Calibration Clock, RTC Alarm pulse or Second pulse on
TAMPER pin PC13 (when this pin is not used for tamper detection)
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RM0008Backup registers (BKP)
5.3 BKP functional description
5.3.1 Tamper detection
The TAMPER pin generates a Tamper detection event when the pin changes from 0 to 1 or
from 1 to 0 depending on the TPAL bit in the Backup control register (BKP_CR). A tamper
detection event resets all data backup registers.
However to avoid losing Tamper events, the signal used for edge detection is logically
ANDed with the Tamper enable in order to detect a Tamper event in case it occurs before
the TAMPER pin is enabled.
●When TPAL=0: If the TAMPER pin is already high before it is enabled (by setting TPE
bit), an extra Tamper event is detected as soon as the TAMPER pin is enabled (while
there was no rising edge on the TAMPER pin after TPE was set)
●When TPAL=1: If the TAMPER pin is already low before it is enabled (by setting the
TPE bit), an extra Tamper event is detected as soon as the TAMPER pin is enabled
(while there was no falling edge on the TAMPER pin after TPE was set)
By setting the TPIE bit in the BKP_CSR register, an interrupt is generated when a Tamper
detection event occurs.
After a Tamper event has been detected and cleared, the TAMPER pin should be disabled
and then re-enabled with TPE before writing to the backup data registers (BKP_DRx) again.
This prevents software from writing to the backup data registers (BKP_DRx), while the
TAMPER pin value still indicates a Tamper detection. This is equivalent to a level detection
on the TAMPER pin.
Note:Tamper detection is still active when V
of the data backup registers, the TAMPER pin should be externally tied to the correct level.
5.3.2 RTC calibration
For measurement purposes, the RTC clock with a frequency divided by 64 can be output on
the TAMPER pin. This is enabled by setting the CCO bit in the RTC clock calibration register
(BKP_RTCCR).
The clock can be slowed down by up to 121 ppm by configuring CAL[6:0] bits.
For more details about RTC calibration and how to use it to improve timekeeping accuracy,
please refer to AN2604 "STM32F101xx and STM32F103xx RTC calibration”.
power is switched off. To avoid unwanted resetting
DD
Doc ID 13902 Rev 967/995
Backup registers (BKP)RM0008
5.4 BKP registers
Refer to Section 1.1 on page 37 for a list of abbreviations used in register descriptions.
5.4.1 Backup data register x (BKP_DRx) (x = 1 ..42)
Address offset: 0x04 to 0x28, 0x40 to 0xBC
Reset value: 0x0000 0000
1514131211109876543210
D[15:0]
rwrwrwrwrwrwrwrwrwrwrwrwrwrwrwrw
Bits 15:0 D[15:0] Backup data
These bits can be written with user data.
Note: The BKP_DRx registers are not reset by a System reset or Power reset or when the
device wakes up from Standby mode.
They are reset by a Backup Domain reset or by a TAMPER pin event (if the TAMPER
pin function is activated).
5.4.2 RTC clock calibration register (BKP_RTCCR)
Address offset: 0x2C
Reset value: 0x0000 0000
1514131211109876543210
Reserved
Bits 15:10 Reserved, always read as 0.
Bit 9 ASOS: Alarm or second output selection
When the ASOE bit is set, the ASOS bit can be used to select whether the signal output on
the TAMPER pin is the RTC Second pulse signal or the Alarm pulse signal:
0: RTC Alarm pulse output selected
1: RTC Second pulse output selected
Note: This bit is reset only by a Backup domain reset.
Bit 8 ASOE: Alarm or second output enable
Setting this bit outputs either the RTC Alarm pulse signal or the Second pulse signal on the
TAMPER pin depending on the ASOS bit.
The output pulse duration is one RTC clock period. The TAMPER pin must not be enabled
while the ASOE bit is set.
Note: This bit is reset only by a Backup domain reset.
Bit 7 CCO: Calibration clock output
0: No effect
1: Setting this bit outputs the RTC clock with a frequency divided by 64 on the TAMPER pin.
The TAMPER pin must not be enabled while the CCO bit is set in order to avoid unwanted
Tamper detection.
Note: This bit is reset when the V
ASOS ASOECCOCAL[6:0]
rwrwrwrwrwrwrwrwrwrw
supply is powered off.
DD
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RM0008Backup registers (BKP)
Bit 6:0 CAL[6:0]: Calibration value
This value indicates the number of clock pulses that will be ignored every 2^20 clock pulses.
This allows the calibration of the RTC, slowing down the clock by steps of 1000000/2^20
PPM.
The clock of the RTC can be slowed down from 0 to 121PPM.
5.4.3 Backup control register (BKP_CR)
Address offset: 0x30
Reset value: 0x0000 0000
1514131211109876543210
Reserved
Bits 15:2 Reserved, always read as 0.
Bit 1 TPAL: TAMPER pin active level
0: A high level on the TAMPER pin resets all data backup registers (if TPE bit is set).
1: A low level on the TAMPER pin resets all data backup registers (if TPE bit is set).
Bit 0 TPE: TAMPER pin enable
0: The TAMPER pin is free for general purpose I/O
1: Tamper alternate I/O function is activated.
TPALTPE
rwrw
Note:Setting the TPAL and TPE bits at the same time is always safe, however resetting both at
the same time can generate a spurious Tamper event. For this reason it is recommended to
change the TPAL bit only when the TPE bit is reset.
5.4.4 Backup control/status register (BKP_CSR)
Address offset: 0x34
Reset value: 0x0000 0000
1514131211109876543210
Reserved
TIFTEF
rrrwww
Reserved
Bits 15:10 Reserved, always read as 0.
Bit 9 TIF: Tamper interrupt flag
This bit is set by hardware when a Tamper event is detected and the TPIE bit is set. It is
cleared by writing 1 to the CTI bit (also clears the interrupt). It is also cleared if the TPIE bit
is reset.
0: No Tamper interrupt
1: A Tamper interrupt occurred
Note: This bit is reset only by a system reset and wakeup from Standby mode.
TPIECTICTE
Doc ID 13902 Rev 969/995
Backup registers (BKP)RM0008
Bit 8 TEF: Tamper event flag
This bit is set by hardware when a Tamper event is detected. It is cleared by writing 1 to the
CTE bit.
0: No Tamper event
1: A Tamper event occurred
Note: A Tamper event resets all the BKP_DRx registers. They are held in reset as long as the
TEF bit is set. If a write to the BKP_DRx registers is performed while this bit is set, the
value will not be stored.
Bits 7:3 Reserved, always read as 0.
Bit 2 TPIE: TAMPER pin interrupt enable
0: Tamper interrupt disabled
1: Tamper interrupt enabled (the TPE bit must also be set in the BKP_CR register
Note: 1: A Tamper interrupt does not wake up the core from low-power modes.
2: This bit is reset only by a system reset and wakeup from Standby mode.
Bit 1 CTI: Clear tamper interrupt
This bit is write only, and is always read as 0.
0: No effect
1: Clear the Tamper interrupt and the TIF Tamper interrupt flag.
Bit 0 CTE: Clear tamper event
This bit is write only, and is always read as 0.
0: No effect
1: Reset the TEF Tamper event flag (and the Tamper detector)
5.4.5 BKP register map
BKP registers are mapped as 16-bit addressable registers as described in the table below:
Table 14.BKP register map and reset values
OffsetRegister
0x00Reserved
0x04
0x08
0x0C
0x10
0x14
0x18
313029282726252423222120191817161514131211
BKP_DR1
Reset value0000000000000000
BKP_DR2
Reset value0000000000000000
BKP_DR3
Reset value0000000000000000
BKP_DR4
Reset value0000000000000000
BKP_DR5
Reset value0000000000000000
BKP_DR6
Reset value0000000000000000
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
987654321
10
D[15:0]
D[15:0]
D[15:0]
D[15:0]
D[15:0]
D[15:0]
0
70/995 Doc ID 13902 Rev 9
RM0008Backup registers (BKP)
Table 14.BKP register map and reset values (continued)
OffsetRegister
0x1C
BKP_DR7
Reset value0000000000000000
313029282726252423222120191817161514131211
Reserved
987654321
10
D[15:0]
0
0x20
0x24
0x28
0x2
0x30
0x34
0x38
0x3C
0x40
0x44
BKP_DR8
Reserved
D[15:0]
Reset value0000000000000000
BKP_DR9
Reserved
D[15:0]
Reset value0000000000000000
BKP_DR10
Reserved
D[15:0]
Reset value0000000000000000
BKP_RTCCR
Reserved
CCO
ASOS
ASOE
CAL[6:0]
Reset value0000000000
BKP_CR
Reset value00
BKP_CSR
Reserved
Reserved
TPAL
TIF
Reserved
TEF
TPIE
CTI
Reset value00000
Reserved
Reserved
BKP_DR11
Reserved
D[15:0]
Reset value0000000000000000
BKP_DR12
Reserved
D[15:0]
Reset value0000000000000000
TPE
CTE
0x48
BKP_DR13
Reserved
D[15:0]
Reset value0000000000000000
0x4C
BKP_DR14
Reserved
D[15:0]
Reset value0000000000000000
0x50
BKP_DR15
Reserved
D[15:0]
Reset value0000000000000000
0x54
BKP_DR16
Reserved
D[15:0]
Reset value0000000000000000
0x58
BKP_DR17
Reserved
D[15:0]
Reset value0000000000000000
0x5C
BKP_DR18
Reserved
D[15:0]
Reset value0000000000000000
0x60BKP_DR19
Reserved
D[15:0]
Reset value0000000000000000
Doc ID 13902 Rev 971/995
Backup registers (BKP)RM0008
Table 14.BKP register map and reset values (continued)
OffsetRegister
0x64
BKP_DR20
Reset value0000000000000000
313029282726252423222120191817161514131211
Reserved
987654321
10
D[15:0]
0
0x68
BKP_DR21
Reset value0000000000000000
0x6C
BKP_DR22
Reset value0000000000000000
0x70
BKP_DR23
Reset value0000000000000000
0x74
BKP_DR24
Reset value0000000000000000
0x78
BKP_DR25
Reset value0000000000000000
0x7C
BKP_DR26
Reset value0000000000000000
0x80
BKP_DR27
Reset value0000000000000000
0x84
BKP_DR28
Reset value0000000000000000
0x88BKP_DR29
Reset value0000000000000000
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
D[15:0]
D[15:0]
D[15:0]
D[15:0]
D[15:0]
D[15:0]
D[15:0]
D[15:0]
D[15:0]
0x8C
BKP_DR30
Reserved
Reset value0000000000000000
0x90
BKP_DR31
Reserved
Reset value0000000000000000
0x94
BKP_DR32
Reserved
Reset value0000000000000000
0x98
BKP_DR33
Reserved
Reset value0000000000000000
0x9C
BKP_DR34
Reserved
Reset value0000000000000000
0xA0
0xA4
BKP_DR35
Reset value0000000000000000
BKP_DR36
Reserved
Reserved
Reset value0000000000000000
72/995 Doc ID 13902 Rev 9
D[15:0]
D[15:0]
D[15:0]
D[15:0]
D[15:0]
D[15:0]
D[15:0]
RM0008Backup registers (BKP)
Table 14.BKP register map and reset values (continued)
OffsetRegister
0xA8
BKP_DR37
Reset value0000000000000000
313029282726252423222120191817161514131211
Reserved
987654321
10
D[15:0]
0
0xAC
BKP_DR38
Reset value0000000000000000
0xB0BKP_DR39
Reset value0000000000000000
0xB4
BKP_DR40
Reset value0000000000000000
0xB8BKP_DR41
Reset value0000000000000000
0xBC
BKP_DR42
Reset value0000000000000000
Refer to Table 1 on page 41 for the register boundary addresses.
Reserved
Reserved
Reserved
Reserved
Reserved
D[15:0]
D[15:0]
D[15:0]
D[15:0]
D[15:0]
Doc ID 13902 Rev 973/995
Low-, medium- and high-density reset and clock control (RCC)RM0008
6 Low-, medium- and high-density reset and clock
control (RCC)
Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx
microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
Medium-densitydevices are STM32F101xx, STM32F102xx and STM32F103xx
microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
High-density devices are STM32F101xx and STM32F103xx microcontrollers where the
Flash memory density ranges between 256 and 512 Kbytes.
Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
This Section applies to low-, medium- and high-density STM32F10xxx devices. Connectivity
line devices are discussed in a separate section (refer to Connectivity line devices: reset
and clock control (RCC) on page 104).
6.1 Reset
There are three types of reset, defined as system Reset, power Reset and backup domain
Reset.
6.1.1 System reset
A system reset sets all registers to their reset values except the reset flags in the clock
controller CSR register and the registers in the Backup domain (see Figure 4).
A system reset is generated when one of the following events occurs:
1.A low level on the NRST pin (external reset)
2. Window watchdog end of count condition (WWDG reset)
3. Independent watchdog end of count condition (IWDG reset)
4. A software reset (SW reset) (see Section : Software reset)
5. Low-power management reset (see Section : Low-power management reset)
The reset source can be identified by checking the reset flags in the Control/Status register,
RCC_CSR (see Section 6.3.10: Control/status register (RCC_CSR)).
Software reset
The SYSRESETREQ bit in Cortex™-M3 Application Interrupt and Reset Control Register
must be set to force a software reset on the device. Refer to the Cortex™-M3 technical
reference manual for more details.
Low-power management reset
There are two ways to generate a low-power management reset:
74/995 Doc ID 13902 Rev 9
RM0008Low-, medium- and high-density reset and clock control (RCC)
NRST
R
PU
VDD/V
DDA
WWDG reset
IWDG reset
Pulse
generator
Power reset
External
reset
(min 20 µs)
System reset
Filter
Software reset
Low-power management reset
ai16095
1.Reset generated when entering Standby mode:
This type of reset is enabled by resetting nRST_STDBY bit in User Option Bytes. In this
case, whenever a Standby mode entry sequence is successfully executed, the device
is reset instead of entering Standby mode.
2. Reset when entering Stop mode:
This type of reset is enabled by resetting NRST_STOP bit in User Option Bytes. In this
case, whenever a Stop mode entry sequence is successfully executed, the device is
reset instead of entering Stop mode.
For further information on the User Option Bytes, refer to the STM32F10xxx Flash
programming manual.
6.1.2 Power reset
A power reset is generated when one of the following events occurs:
1.Power-on/power-down reset (POR/PDR reset)
2. When exiting Standby mode
A power reset sets all registers to their reset values except the Backup domain (see
Figure 4)
These sources act on the NRST pin and it is always kept low during the delay phase. The
RESET service routine vector is fixed at address
details, refer to Table 53: Vector table for other STM32F10xxx devices on page 172.
0x0000_0004 in the memory map. For more
Figure 7.Reset circuit
6.1.3 Backup domain reset
The backup domain has two specific resets that affect only the backup domain (see
Figure 4).
A backup domain reset is generated when one of the following events occurs:
1.Software reset, triggered by setting the BDRST bit in the Backup domain control
register (RCC_BDCR).
2. V
DD
or V
BAT
power on, if both supplies have previously been powered off.
Doc ID 13902 Rev 975/995
Low-, medium- and high-density reset and clock control (RCC)RM0008
6.2 Clocks
Three different clock sources can be used to drive the system clock (SYSCLK):
●HSI oscillator clock
●HSE oscillator clock
●PLL clock
The devices have the following two secondary clock sources:
●40 kHz low speed internal RC (LSI RC) which drives the independent watchdog and
optionally the RTC used for Auto-wakeup from Stop/Standby mode.
●32.768 kHz low speed external crystal (LSE crystal) which optionally drives the real-
time clock (RTCCLK)
Each clock source can be switched on or off independently when it is not used, to optimize
power consumption.
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RM0008Low-, medium- and high-density reset and clock control (RCC)
Figure 8.Clock tree
OSC_OUT
OSC_IN
OSC32_IN
OSC32_OUT
8 MHz
HSI RC
PLLSRC
4-16 MHz
HSE OSC
LSE OSC
32.768 kHz
LSI RC
40 kHz
HSI
PLLMUL
..., x16
x2, x3, x4
PLL
PLLXTPRE
/2
/128
LSE
RTCSEL[1:0]
LSI
/2
SW
HSI
PLLCLK
HSE
CSS
RTCCLK
to Independent Watchdog (IWDG)
SYSCLK
72 MHz
max
to RTC
AHB
Prescaler
/1, 2..512
IWDGCLK
USB
Prescaler
/1, 1.5
Peripheral clock
enable
Peripheral clock
enable
/1, 2, 4, 8, 16
TIM2,3,4,5,6,7
If (APB1 prescaler =1) x1
/1, 2, 4, 8, 16
48 MHz
I2S3CLK
I2S2CLK
Peripheral clock
enable
Peripheral clock
enable
72 MHz max
Clock
Enable
/8
APB1
Prescaler
APB2
Prescaler
TIM1 & 8 timers
If (APB2 prescaler =1) x1
ADC
Prescaler
/2, 4, 6, 8
36 MHz max
Peripheral Clock
Enable
else x2
72 MHz max
Peripheral Clock
Enable
else x2
ADCCLK 14 MHz max
/2
Peripheral clock
enable
USBCLK
to USB interface
to I2S3
to I2S2
SDIOCLK
FSMCCLK
HCLK
to AHB bus, core,
memory and DMA
to SDIO
to FSMC
to Cortex System timer
FCLK Cortex
free running clock
Peripheral Clock
Enable
PCLK1
to APB1
peripherals
to TIM2,3,4,5,6 and 7
TIMXCLK
PCLK2
peripherals to APB2
to TIM1 and TIM8
TIMxCLK
Peripheral Clock
Enable
To SDIO AHB interface
to ADC1, 2 or 3
HCLK/2
Legend:
HSE = High-speed external clock signal
HSI = High-speed internal clock signal
LSI = Low-speed internal clock signal
LSE = Low -speed external clock signal
ai14752d
MCO
Main
Clock Output
MCO
/2
PLLCLK
HSI
HSE
SYSCLK
1. When the HSI is used as a PLL clock input, the maximum system clock frequency that can be achieved is
64 MHz.
2. For full details about the internal and external clock source characteristics, please refer to the “Electrical
characteristics” section in your device datasheet.
Several prescalers allow the configuration of the AHB frequency, the high speed APB
(APB2) and the low speed APB (APB1) domains. The maximum frequency of the AHB and
the APB2 domains is 72 MHz. The maximum allowed frequency of the APB1 domain is
36 MHz. The SDIO AHB interface is clocked with a fixed frequency equal to HCLK/2.
The RCC feeds the Cortex System Timer (SysTick) external clock with the AHB clock
(HCLK) divided by 8. The SysTick can work either with this clock or with the Cortex clock
(HCLK), configurable in the SysTick Control and Status Register. The ADCs are clocked by
the clock of the High Speed domain (APB2) divided by 2, 4, 6 or 8.
The timer clock frequencies are automatically fixed by hardware. There are two cases:
Doc ID 13902 Rev 977/995
Low-, medium- and high-density reset and clock control (RCC)RM0008
OSC_OUT
External
source
(HiZ)
OSC_IN OSC_OUT
Load
capacitors
C
L2
C
L1
1.if the APB prescaler is 1, the timer clock frequencies are set to the same frequency as
that of the APB domain to which the timers are connected.
2. otherwise, they are set to twice (×2) the frequency of the APB domain to which the
timers are connected.
FCLK acts as Cortex™-M3 free running clock. For more details refer to the ARM Cortex™M3 Technical Reference Manual.
6.2.1 HSE clock
The high speed external clock signal (HSE) can be generated from two possible clock
sources:
●HSE external crystal/ceramic resonator
●HSE user external clock
The resonator and the load capacitors have to be placed as close as possible to the
oscillator pins in order to minimize output distortion and startup stabilization time. The
loading capacitance values must be adjusted according to the selected oscillator.
Figure 9.HSE/ LSE clock sources
Clock sourceHardware configuration
External clock
Crystal/Ceramic
resonators
External source (HSE bypass)
In this mode, an external clock source must be provided. It can have a frequency of up to 25
MHz. You select this mode by setting the HSEBYP and HSEON
bits in the Clock control
register (RCC_CR). The external clock signal (square, sinus or triangle) with ~50% duty
cycle has to drive the OSC_IN pin while the OSC_OUT pin should be left hi-Z. See Figure 9.
78/995 Doc ID 13902 Rev 9
RM0008Low-, medium- and high-density reset and clock control (RCC)
External crystal/ceramic resonator (HSE crystal)
The 4 to 16 MHz external oscillator has the advantage of producing a very accurate rate on
the main clock.
The associated hardware configuration is shown in Figure 9. Refer to the electrical
characteristics section of the datasheet for more details.
The HSERDY flag in the Clock control register (RCC_CR) indicates if the high-speed
external oscillator is stable or not. At startup, the clock is not released until this bit is set by
hardware. An interrupt can be generated if enabled in the Clock interrupt register
(RCC_CIR).
The HSE Crystal can be switched on and off using the HSEON bit in the Clock control
register (RCC_CR).
6.2.2 HSI clock
The HSI clock signal is generated from an internal 8 MHz RC Oscillator and can be used
directly as a system clock or divided by 2 to be used as PLL input.
The HSI RC oscillator has the advantage of providing a clock source at low cost (no external
components). It also has a faster startup time than the HSE crystal oscillator however, even
with calibration the frequency is less accurate than an external crystal oscillator or ceramic
resonator.
6.2.3 PLL
Calibration
RC oscillator frequencies can vary from one chip to another due to manufacturing process
variations, this is why each device is factory calibrated by ST for 1% accuracy at T
After reset, the factory calibration value is loaded in the HSICAL[7:0] bits in the Clock control
register (RCC_CR).
If the application is subject to voltage or temperature variations this may affect the RC
oscillator speed. You can trim the HSI frequency in the application using the HSITRIM[4:0]
bits in the Clock control register (RCC_CR).
The HSIRDY flag in the Clock control register (RCC_CR) indicates if the HSI RC is stable or
not. At startup, the HSI RC output clock is not released until this bit is set by hardware.
The HSI RC can be switched on and off using the HSION bit in the Clock control register
(RCC_CR).
The HSI signal can also be used as a backup source (Auxiliary clock) if the HSE crystal
oscillator fails. Refer to Section 6.2.7: Clock security system (CSS) on page 81.
The internal PLL can be used to multiply the HSI RC output or HSE crystal output clock
frequency. Refer to Figure 8 and Clock control register (RCC_CR).
The PLL configuration (selection of HSI oscillator divided by 2 or HSE oscillator for PLL
input clock, and multiplication factor) must be done before enabling the PLL. Once the PLL
enabled, these parameters cannot be changed.
=25°C.
A
An interrupt can be generated when the PLL is ready if enabled in the Clock interrupt
register (RCC_CIR).
Doc ID 13902 Rev 979/995
Low-, medium- and high-density reset and clock control (RCC)RM0008
If the USB interface is used in the application, the PLL must be programmed to output 48 or
72 MHz. This is needed to provide a 48 MHz USBCLK.
6.2.4 LSE clock
The LSE crystal is a 32.768 kHz Low Speed External crystal or ceramic resonator. It has the
advantage providing a low-power but highly accurate clock source to the real-time clock
peripheral (RTC) for clock/calendar or other timing functions.
The LSE crystal is switched on and off using the LSEON bit in Backup domain control
register (RCC_BDCR).
The LSERDY flag in the Backup domain control register (RCC_BDCR) indicates if the LSE
crystal is stable or not. At startup, the LSE crystal output clock signal is not released until
this bit is set by hardware. An interrupt can be generated if enabled in the Clock interrupt
register (RCC_CIR).
External source (LSE bypass)
In this mode, an external clock source must be provided. It must have a frequency of
32.768 kHz. You select this mode by setting the LSEBYP and LSEON bits in the Backup
domain control register (RCC_BDCR). The external clock signal (square, sinus or triangle)
with ~50% duty cycle has to drive the OSC32_IN pin while the OSC32_OUT pin should be
left Hi-Z. See Figure 9.
6.2.5 LSI clock
The LSI RC acts as an low-power clock source that can be kept running in Stop and
Standby mode for the independent watchdog (IWDG) and Auto-wakeup unit (AWU). The
clock frequency is around 40 kHz (between 30 kHz and 60 kHz). For more details, refer to
the electrical characteristics section of the datasheets.
The LSI RC can be switched on and off using the LSION bit in the Control/status register
(RCC_CSR).
The LSIRDY flag in the Control/status register (RCC_CSR) indicates if the low-speed
internal oscillator is stable or not. At startup, the clock is not released until this bit is set by
hardware. An interrupt can be generated if enabled in the Clock interrupt register
(RCC_CIR).
Note:LSI calibration is only available on high-density and connectivity line devices.
LSI calibration
The frequency dispersion of the Low Speed Internal RC (LSI) oscillator can be calibrated to
have accurate RTC time base and/or IWDG timeout (when LSI is used as clock source for
these peripherals) with an acceptable accuracy.
This calibration is performed by measuring the LSI clock frequency with respect to TIM5
input clock (TIM5CLK). According to this measurement done at the precision of the HSE
oscillator, the software can adjust the programmable 20-bit prescaler of the RTC to get an
accurate time base or can compute accurate IWDG timeout.
80/995 Doc ID 13902 Rev 9
RM0008Low-, medium- and high-density reset and clock control (RCC)
Use the following procedure to calibrate the LSI:
1.Enable TIM5 timer and configure channel4 in input capture mode
2. Set the TIM5CH4_IREMAP bit in the AFIO_MAPR register to connect the LSI clock
internally to TIM5 channel4 input capture for calibration purpose.
3. Measure the frequency of LSI clock using the TIM5 Capture/compare 4 event or
interrupt.
4. Use the measured LSI frequency to update the 20-bit prescaler of the RTC depending
on the desired time base and/or to compute the IWDG timeout.
6.2.6 System clock (SYSCLK) selection
After a system reset, the HSI oscillator is selected as system clock. When a clock source is
used directly or through the PLL as system clock, it is not possible to stop it.
A switch from one clock source to another occurs only if the target clock source is ready
(clock stable after startup delay or PLL locked). If a clock source which is not yet ready is
selected, the switch will occur when the clock source will be ready. Status bits in the Clock
control register (RCC_CR) indicate which clock(s) is (are) ready and which clock is currently
used as system clock.
6.2.7 Clock security system (CSS)
Clock Security System can be activated by software. In this case, the clock detector is
enabled after the HSE oscillator startup delay, and disabled when this oscillator is stopped.
If a failure is detected on the HSE oscillator clock, this oscillator is automatically disabled, a
clock failure event is sent to the break input of the advanced-control timers (TIM1 and TIM8)
and an interrupt is generated to inform the software about the failure (Clock Security System
Interrupt CSSI), allowing the MCU to perform rescue operations. The CSSI is linked to the
Cortex™-M3 NMI (Non-Maskable Interrupt) exception vector.
Note:Once the CSS is enabled and if the HSE clock fails, the CSS interrupt occurs and an NMI is
automatically generated. The NMI will be executed indefinitely unless the CSS interrupt
pending bit is cleared. As a consequence, in the NMI ISR user must clear the CSS interrupt
by setting the CSSC bit in the Clock interrupt register (RCC_CIR).
If the HSE oscillator is used directly or indirectly as the system clock (indirectly means: it is
used as PLL input clock, and the PLL clock is used as system clock), a detected failure
causes a switch of the system clock to the HSI oscillator and the disabling of the external
HSE oscillator. If the HSE oscillator clock (divided or not) is the clock entry of the PLL used
as system clock when the failure occurs, the PLL is disabled too.
6.2.8 RTC clock
The RTCCLK clock source can be either the HSE/128, LSE or LSI clocks. This is selected
by programming the RTCSEL[1:0] bits in the Backup domain control register (RCC_BDCR).
This selection cannot be modified without resetting the Backup domain.
Doc ID 13902 Rev 981/995
Low-, medium- and high-density reset and clock control (RCC)RM0008
The LSE clock is in the Backup domain, whereas the HSE and LSI clocks are not.
Consequently:
●If LSE is selected as RTC clock:
–The RTC continues to work even if the V
V
supply is maintained.
BAT
●If LSI is selected as Auto-Wakeup unit (AWU) clock:
–The AWU state is not guaranteed if the V
supply is switched off, provided the
DD
supply is powered off. Refer to
DD
Section 6.2.5: LSI clock on page 80 for more details on LSI calibration.
●If the HSE clock divided by 128 is used as the RTC clock:
–The RTC state is not guaranteed if the V
supply is powered off or if the internal
DD
voltage regulator is powered off (removing power from the 1.8 V domain).
–The DPB bit (Disable backup domain write protection) in the Power controller
register must be set to 1 (refer to Section 4.4.1: Power control register
(PWR_CR)).
6.2.9 Watchdog clock
If the Independent watchdog (IWDG) is started by either hardware option or software
access, the LSI oscillator is forced ON and cannot be disabled. After the LSI oscillator
temporization, the clock is provided to the IWDG.
6.2.10 Clock-out capability
The microcontroller clock output (MCO) capability allows the clock to be output onto the
external MCO pin. The configuration registers of the corresponding GPIO port must be
programmed in alternate function mode. One of 4 clock signals can be selected as the MCO
clock.
●SYSCLK
●HSI
●HSE
●PLL clock divided by 2
The selection is controlled by the MCO[2:0] bits of the Clock configuration register
(RCC_CFGR).
6.3 RCC registers
Refer to Section 1.1 on page 37 for a list of abbreviations used in register descriptions.
82/995 Doc ID 13902 Rev 9
RM0008Low-, medium- and high-density reset and clock control (RCC)
6.3.1 Clock control register (RCC_CR)
Address offset: 0x00
Reset value: 0x0000 XX83 where X is undefined.
Access: no wait state, word, half-word and byte access
31302928272625242322212019181716
PLL
PLLON
Reserved
1514131211109876543210
HSICAL[7:0]HSITRIM[4:0]
rrrrrrr rrwrwrwrwrwrrw
RDY
rrwrwrwrrw
Reserved
CSS ONHSE
Res.
Bits 31:26Reserved, always read as 0.
Bit 25 PLLRDY: PLL clock ready flag
Set by hardware to indicate that the PLL is locked.
0: PLL unlocked
1: PLL locked
BYP
HSE
RDY
HSI
RDY
HSE
ON
HSION
Bit 24 PLLON: PLL enable
Set and cleared by software to enable PLL.
Cleared by hardware when entering Stop or Standby mode. This bit can not be reset if the
PLL clock is used as system clock or is selected to become the system clock.
0: PLL OFF
1: PLL ON
Bits 23:20Reserved, always read as 0.
Bit 19 CSSON: Clock security system enable
Set and cleared by software to enable clock detector.
0: Clock detector OFF
1: Clock detector ON if external 4-25 MHz oscillator is ready.
Bit 18 HSEBYP: External high-speed clock bypass
Set and cleared by software in debug for bypassing the oscillator with an external clock. This
bit can be written only if the external 4-25 MHz oscillator is disabled.
0: external 4-25 MHz oscillator not bypassed
1: external 4-25 MHz oscillator bypassed with external clock
Bit 17 HSERDY: External high-speed clock ready flag
Set by hardware to indicate that the external 4-25 MHz oscillator is stable. This bit needs 6
cycles of external 4-25 MHz oscillator clock to fall down after HSEON reset.
0: external 4-25 MHz oscillator not ready
1: external 4-25 MHz oscillator ready
Doc ID 13902 Rev 983/995
Low-, medium- and high-density reset and clock control (RCC)RM0008
Bit 16 HSEON: External high-speed clock enable
Set and cleared by software.
Cleared by hardware to stop the external 1-25MHz oscillator when entering in Stop or
Standby mode. This bit cannot be reset if the external 4-25 MHz oscillator is used directly or
indirectly as the system clock or is selected to become the system clock.
0: HSE oscillator OFF
1: HSE oscillator ON
These bits provide an additional user-programmable trimming value that is added to the
HSICAL[7:0] bits. It can be programmed to adjust to variations in voltage and temperature
that influence the frequency of the internal HSI RC.
The default value is 16, which, when added to the HSICAL value, should trim the HSI to 8
MHz ± 1%. The trimming step (F
steps.
Bit 2Reserved, always read as 0.
Bit 1 HSIRDY: Internal high-speed clock ready flag
Set by hardware to indicate that internal 8 MHz RC oscillator is stable. After the HSION bit is
cleared, HSIRDY goes low after 6 internal 8 MHz RC oscillator clock cycles.
Set and cleared by software.
Set by hardware to force the internal 8 MHz RC oscillator ON when leaving Stop or Standby
mode or in case of failure of the external 4-25 MHz oscillator used directly or indirectly as
system clock. This bit cannot be reset if the internal 8 MHz RC is used directly or indirectly
as system clock or is selected to become the system clock.
0: internal 8 MHz RC oscillator OFF
1: internal 8 MHz RC oscillator ON
6.3.2 Clock configuration register (RCC_CFGR)
Address offset: 0x04
Reset value: 0x0000 0000
Access: 0 wait state 2, word, half-word and byte access
1 or 2 wait states inserted only if the access occurs during clock source switch.
RM0008Low-, medium- and high-density reset and clock control (RCC)
Bits 31:27Reserved, always read as 0.
Bits 26:24 MCO: Microcontroller clock output
Set and cleared by software.
0xx: No clock
100: System clock (SYSCLK) selected
101: HSI clock selected
110: HSE clock selected
111: PLL clock divided by 2 selected
Note: This clock output may have some truncated cycles at startup or during MCO clock
source switching.
When the System Clock is selected to output to the MCO pin, make sure that this clock
does not exceed 50 MHz (the maximum I/O speed).
Bit 22 USBPRE: USB prescaler
Set and cleared by software to generate 48 MHz USB clock. This bit must be valid before
enabling the USB clock in the RCC_APB1ENR register. This bit can’t be reset if the USB
clock is enabled.
0: PLL clock is divided by 1.5
1: PLL clock is not divided
Bits 21:18 PLLMUL: PLL multiplication factor
These bits are written by software to define the PLL multiplication factor. These bits can be
written only when PLL is disabled.
Caution: The PLL output frequency must not exceed 72 MHz.
0000: PLL input clock x 2
0001: PLL input clock x 3
0010: PLL input clock x 4
0011: PLL input clock x 5
0100: PLL input clock x 6
0101: PLL input clock x 7
0110: PLL input clock x 8
0111: PLL input clock x 9
1000: PLL input clock x 10
1001: PLL input clock x 11
1010: PLL input clock x 12
1011: PLL input clock x 13
1100: PLL input clock x 14
1101: PLL input clock x 15
1110: PLL input clock x 16
1111: PLL input clock x 16
Bit 17 PLLXTPRE: HSE divider for PLL entry
Set and cleared by software to divide HSE before PLL entry. This bit can be written only
when PLL is disabled.
0: HSE clock not divided
1: HSE clock divided by 2
Bit 16 PLLSRC: PLL entry clock source
Set and cleared by software to select PLL clock source. This bit can be written only when
PLL is disabled.
0: HSI oscillator clock / 2 selected as PLL input clock
1: HSE oscillator clock selected as PLL input clock
Doc ID 13902 Rev 985/995
Low-, medium- and high-density reset and clock control (RCC)RM0008
Bits 14:14 ADCPRE: ADC prescaler
Set and cleared by software to select the frequency of the clock to the ADCs.
00: PLCK2 divided by 2
01: PLCK2 divided by 4
10: PLCK2 divided by 6
11: PLCK2 divided by 8
Bits 13:11 PPRE2: APB high-speed prescaler (APB2)
Set and cleared by software to control the division factor of the APB high-speed clock
(PCLK2).
0xx: HCLK not divided
100: HCLK divided by 2
101: HCLK divided by 4
110: HCLK divided by 8
111: HCLK divided by 16
Bits 10:8 PPRE1: APB low-speed prescaler (APB1)
Set and cleared by software to control the division factor of the APB low-speed clock
(PCLK1).
Warning: the software has to set correctly these bits to not exceed 36 MHz on this domain.
0xx: HCLK not divided
100: HCLK divided by 2
101: HCLK divided by 4
110: HCLK divided by 8
111: HCLK divided by 16
Bits 7:4 HPRE: AHB prescaler
Set and cleared by software to control the division factor of the AHB clock.
0xxx: SYSCLK not divided
1000: SYSCLK divided by 2
1001: SYSCLK divided by 4
1010: SYSCLK divided by 8
1011: SYSCLK divided by 16
1100: SYSCLK divided by 64
1101: SYSCLK divided by 128
1110: SYSCLK divided by 256
1111: SYSCLK divided by 512
Note: The prefetch buffer must be kept on when using a prescaler different from 1 on the
AHB clock. Refer to Reading the Flash memory on page 47 section for more details.
Bits 3:2 SWS: System clock switch status
Set and cleared by hardware to indicate which clock source is used as system clock.
00: HSI oscillator used as system clock
01: HSE oscillator used as system clock
10: PLL used as system clock
11: not applicable
86/995 Doc ID 13902 Rev 9
RM0008Low-, medium- and high-density reset and clock control (RCC)
Bits 1:0 SW: System clock switch
Set and cleared by software to select SYSCLK source.
Set by hardware to force HSI selection when leaving Stop and Standby mode or in case of
failure of the HSE oscillator used directly or indirectly as system clock (if the Clock Security
System is enabled).
00: HSI selected as system clock
01: HSE selected as system clock
10: PLL selected as system clock
11: not allowed
6.3.3 Clock interrupt register (RCC_CIR)
Address offset: 0x08
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
31302928272625242322212019181716
PLL
LSI
RDYIE
CSSC
CSSF
Reserved
wwwwww
Reserved
Reserved
1514131211109876543210
PLL
HSE
HSI
LSE
RDYIE
Reserved
RDYIE
RDYIE
RDYIE
rwrwrwrwrwrrrrrr
RDYC
RDYF
PLL
HSE
RDYC
HSE
RDYF
HSI
RDYC
HSI
RDYF
LSE
RDYC
LSE
RDYF
LSI
RDYC
LSI
RDYF
Bits 31:24Reserved, always read as 0.
Bit 23 CSSC: Clock security system interrupt clear
This bit is set by software to clear the CSSF flag.
0: No effect
1: Clear CSSF flag
Bits 22:21Reserved, always read as 0.
Bit 20 PLLRDYC: PLL ready interrupt clear
This bit is set by software to clear the PLLRDYF flag.
0: No effect
1: PLLRDYF cleared
Bit 19 HSERDYC: HSE ready interrupt clear
This bit is set by software to clear the HSERDYF flag.
0: No effect
1: HSERDYF cleared
Bit 18 HSIRDYC: HSI ready interrupt clear
This bit is set software to clear the HSIRDYF flag.
0: No effect
1: HSIRDYF cleared
Doc ID 13902 Rev 987/995
Low-, medium- and high-density reset and clock control (RCC)RM0008
Bit 17 LSERDYC: LSE ready interrupt clear
This bit is set by software to clear the LSERDYF flag.
0: No effect
1: LSERDYF cleared
Bit 16 LSIRDYC: LSI ready interrupt clear
This bit is set by software to clear the LSIRDYF flag.
0: No effect
1: LSIRDYF cleared
Bits 15:13Reserved, always read as 0.
Bit 12 PLLRDYIE: PLL ready interrupt enable
Set and cleared by software to enable/disable interrupt caused by PLL lock.
0: PLL lock interrupt disabled
1: PLL lock interrupt enabled
Bit 11 HSERDYIE: HSE ready interrupt enable
Set and cleared by software to enable/disable interrupt caused by the external 4-25 MHz
oscillator stabilization.
Set and cleared by software to enable/disable interrupt caused by the internal 8 MHz RC
oscillator stabilization.
0: HSI ready interrupt disabled
1: HSI ready interrupt enabled
Bit 9 LSERDYIE: LSE ready interrupt enable
Set and cleared by software to enable/disable interrupt caused by the external 32 kHz
oscillator stabilization.
Set by hardware when a failure is detected in the external 4-25 MHz oscillator.
Cleared by software setting the CSSC bit.
0: No clock security interrupt caused by HSE clock failure
1: Clock security interrupt caused by HSE clock failure
Bits 6:5Reserved, always read as 0.
Bit 4 PLLRDYF: PLL ready interrupt flag
Set by hardware when the PLL locks and PLLRDYDIE is set.
Cleared by software setting the PLLRDYC bit.
0: No clock ready interrupt caused by PLL lock
1: Clock ready interrupt caused by PLL lock
88/995 Doc ID 13902 Rev 9
RM0008Low-, medium- and high-density reset and clock control (RCC)
Bit3 HSERDYF: HSE ready interrupt flag
Set by hardware when External Low Speed clock becomes stable and HSERDYDIE is set.
Cleared by software setting the HSERDYC bit.
0: No clock ready interrupt caused by the external 4-25 MHz oscillator
1: Clock ready interrupt caused by the external 4-25 MHz oscillator
Bit 2 HSIRDYF: HSI ready interrupt flag
Set by hardware when the Internal High Speed clock becomes stable and HSIRDYDIE is
set.
Cleared by software setting the HSIRDYC bit.
0: No clock ready interrupt caused by the internal 8 MHz RC oscillator
1: Clock ready interrupt caused by the internal 8 MHz RC oscillator
Bit 1 LSERDYF: LSE ready interrupt flag
Set by hardware when the External Low Speed clock becomes stable and LSERDYDIE is
set.
Cleared by software setting the LSERDYC bit.
0: No clock ready interrupt caused by the external 32 kHz oscillator
1: Clock ready interrupt caused by the external 32 kHz oscillator
Bit 0 LSIRDYF: LSI ready interrupt flag
Set by hardware when the internal low speed clock becomes stable and LSIRDYDIE is set.
Cleared by software setting the LSIRDYC bit.
0: No clock ready interrupt caused by the internal RC 40 kHz oscillator
1: Clock ready interrupt caused by the internal RC 40 kHz oscillator
Access: no wait state, word, half-word and byte access
Note:When the peripheral clock is not active, the peripheral register values may not be readable
by software and the returned value is always 0x0.
31302928272625242322212019181716
Reserved
1514131211109876543210
SDIO
Reserved
EN
rwrwrwrwrwrwrw
Bits 31:11Reserved, always read as 0.
Res.
FSMC
EN
Res.
CRCE
N
Res.
FLITF
EN
SRAMENDMA2ENDMA1
Res.
EN
Doc ID 13902 Rev 993/995
Low-, medium- and high-density reset and clock control (RCC)RM0008
Bit 10 SDIOEN: SDIO clock enable
Set and cleared by software.
0: SDIO clock disabled
1: SDIO clock enabled
Bits 9Reserved, always read as 0.
Bit 8 FSMCEN: FSMC clock enable
Set and cleared by software.
0: FSMC clock disabled
1: FSMC clock enabled
Bit 7Reserved, always read as 0.
Bit 6 CRCEN: CRC clock enable
Set and cleared by software.
0: CRC clock disabled
1: CRC clock enabled
Bit 5Reserved, always read as 0.
Bit 4 FLITFEN: FLITF clock enable
Set and cleared by software to disable/enable FLITF clock during sleep mode.
0: FLITF clock disabled during Sleep mode
1: FLITF clock enabled during Sleep mode
Bit 3Reserved, always read as 0.
Bit 2 SRAMEN: SRAM interface clock enable
Set and cleared by software to disable/enable SRAM interface clock during Sleep mode.
0: SRAM interface clock disabled during Sleep mode.
1: SRAM interface clock enabled during Sleep mode
Bit 1 DMA2EN: DMA2 clock enable
Set and cleared by software.
0: DMA2 clock disabled
1: DMA2 clock enabled
Bit 0 DMA1EN: DMA1 clock enable
Set and cleared by software.
0: DMA1 clock disabled
1: DMA1 clock enabled
94/995 Doc ID 13902 Rev 9
RM0008Low-, medium- and high-density reset and clock control (RCC)
No wait states, except if the access occurs while an access to a peripheral in the APB2
domain is on going. In this case, wait states are inserted until the access to APB2 peripheral
is finished.
Note:When the peripheral clock is not active, the peripheral register values may not be readable
No wait state, except if the access occurs while an access to a peripheral on APB1 domain
is on going. In this case, wait states are inserted until this access to APB1 peripheral is
finished.
Note:When the peripheral clock is not active, the peripheral register values may not be readable
by software and the returned value is always 0x0.
31302928272625242322212019181716
Reserved
Res.rwrwrwRes.rwRes.rwrwrwrwrwrwrwRes.
1514131211109876543210
SPI3ENSPI2
rwrwRes.rwRes.rwrwrwrwrwrw
DACENPWRENBKP
Reserved
EN
EN
WWD
GEN
Res.
CAN
EN
Reserved
USBENI2C2ENI2C1ENUART5ENUART4ENUSART
Res.
TIM7ENTIM6ENTIM5ENTIM4ENTIM3ENTIM2
3EN
USART
2EN
Res.
EN
Bits 31:30Reserved, always read as 0.
Bit 29 DACEN: DAC interface clock enable
Set and cleared by software.
0: DAC interface clock disabled
1: DAC interface clock enable
Bit 28 PWREN: Power interface clock enable
Set and cleared by software.
0: Power interface clock disabled
1: Power interface clock enable
Bit 27 BKPEN: Backup interface clock enable
Set and cleared by software.
0: Backup interface clock disabled
1: Backup interface clock enabled
Bit 26Reserved, always read as 0.
Bit 25 CANEN: CAN clock enable
Set and cleared by software.
0: CAN clock disabled
1: CAN clock enabled
Bit 24Reserved, always read as 0.
Bit 23 USBEN: USB clock enable
Set and cleared by software.
0: USB clock disabled
1: USB clock enabled
Doc ID 13902 Rev 997/995
Low-, medium- and high-density reset and clock control (RCC)RM0008
Bit 22 I2C2EN: I2C 2 clock enable
Set and cleared by software.
0: I2C 2 clock disabled
1: I2C 2 clock enabled
Bit 21 I2C1EN: I2C 1 clock enable
Set and cleared by software.
0: I2C 1 clock disabled
1: I2C 1 clock enabled
Bit 20 UART 5EN: USART 5 clock enable
Set and cleared by software.
0: USART 5 clock disabled
1: USART 5 clock enabled
Bit 19 UART 4EN: USART 4 clock enable
Set and cleared by software.
0: USART 4 clock disabled
1: USART 4 clock enabled
Bit 18 USART3EN: USART 3 clock enable
Set and cleared by software.
0: USART 3 clock disabled
1: USART 3 clock enabled
Bit 17 USART2EN: USART 2 clock enable
Set and cleared by software.
0: USART 2 clock disabled
1: USART 2 clock enabled
Bits 16Reserved, always read as 0.
Bit 15 SPI3EN: SPI 3 clock enable
Set and cleared by software.
0: SPI 3 clock disabled
1: SPI 3 clock enabled
Bit 14 SPI2EN: SPI 2 clock enable
Set and cleared by software.
0: SPI 2 clock disabled
1: SPI 2 clock enabled
Bits 13:12Reserved, always read as 0.
Bit 11 WWDGEN: Window watchdog clock enable
Set and cleared by software.
0: Window watchdog clock disabled
1: Window watchdog clock enabled
Bits 10:6Reserved, always read as 0.
Bit 5 TIM7EN: Timer 7 clock enable
Set and cleared by software.
0: Timer 7 clock disabled
1: Timer 7 clock enabled
98/995 Doc ID 13902 Rev 9
RM0008Low-, medium- and high-density reset and clock control (RCC)
Bit 4 TIM6EN: Timer 6 clock enable
Set and cleared by software.
0: Timer 6 clock disabled
1: Timer 6 clock enabled
Bit 3 TIM5EN: Timer 5 clock enable
Set and cleared by software.
0: Timer 5 clock disabled
1: Timer 5 clock enabled
Bit 2 TIM4EN: Timer 4 clock enable
Set and cleared by software.
0: Timer 4 clock disabled
1: Timer 4 clock enabled
Bit 1 TIM3EN: Timer 3 clock enable
Set and cleared by software.
0: Timer 3 clock disabled
1: Timer 3 clock enabled
Bit 0 TIM2EN: Timer 2 clock enable
Set and cleared by software.
0: Timer 2 clock disabled
1: Timer 2 clock enabled
6.3.9 Backup domain control register (RCC_BDCR)
Address offset: 0x20
Reset value: 0x0000 0000, reset by Backup domain Reset.
Access: 0 wait state 3, word, half-word and byte access
Wait states are inserted in case of successive accesses to this register.
Note:LSEON, LSEBYP, RTCSEL and RTCEN bits of the Backup domain control register
(RCC_BDCR) are in the Backup domain. As a result, after Reset, these bits are write-
protected and the DBP bit in the Power control register (PWR_CR) has to be set before
these can be modified. Refer to Section 5 on page 66 for further information. These bits are
only reset after a Backup domain Reset (see Section 6.1.3: Backup domain reset). Any
internal or external Reset will not have any effect on these bits.
31302928272625242322212019181716
Reserved
1514131211109876543210
RTC
EN
rwrwrwrwrrw
Bits 31:17Reserved, always read as 0.
Reserved
RTCSEL[1:0]
Reserved
LSE
BYP
LSE
RDY
BDRST
rw
LSEON
Doc ID 13902 Rev 999/995
Low-, medium- and high-density reset and clock control (RCC)RM0008
Bit 16 BDRST: Backup domain software reset
Set and cleared by software.
0: Reset not activated
1: Resets the entire Backup domain
Bit 15 RTCEN: RTC clock enable
Set and cleared by software.
0: RTC clock disabled
1: RTC clock enabled
Bits 14:10Reserved, always read as 0.
Bits 9:8 RTCSEL[1:0]: RTC clock source selection
Set by software to select the clock source for the RTC. Once the RTC clock source has been
selected, it cannot be changed anymore unless the Backup domain is reset. The BDRST bit
can be used to reset them.
00: No clock
01: LSE oscillator clock used as RTC clock
10: LSI oscillator clock used as RTC clock
11: HSE oscillator clock divided by 128 used as RTC clock
Bits 7:3Reserved, always read as 0.
Bit 2 LSEBYP: External low-speed oscillator bypass
Set and cleared by software to bypass oscillator in debug mode. This bit can be written only
when the external 32 kHz oscillator is disabled.
0: LSE oscillator not bypassed
1: LSE oscillator bypassed
Bit 1 LSERDY: External low-speed oscillator ready
Set and cleared by hardware to indicate when the external 32 kHz oscillator is stable. After
the LSEON bit is cleared, LSERDY goes low after 6 external low-speed oscillator clock
cycles.
0: External 32 kHz oscillator not ready
1: External 32 kHz oscillator ready
Bit 0 LSEON: External low-speed oscillator enable
Set and cleared by software.
0: External 32 kHz oscillator OFF
1: External 32 kHz oscillator ON
100/995 Doc ID 13902 Rev 9
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