Datasheet RHF1401 Datasheet (ST)

RHF1401

Rad-hard 14-bit 30 Msps A/D converter

Datasheet − production data

Features

■ Qml-V qualified, smd 5962-06260

■ Rad hard: 300 kRad(Si) TID

■ Failure immune (SEFI) and latch-up immune

(SEL) up to 120 MeV-cm

2

/mg at 2.7 V and

125° C

■ Hermetic package

■ Tested at F

■ Low power: 85 mW at 20 Msps

■ Optimized for 2 Vpp differential input

■ High linearity and dynamic performances

■ 2.5 V/3.3 V compatible digital I/O

■ Internal reference voltage with external

=20Msps

s

reference option

Applications

■ Digital communication satellites

■ Space data acquisition systems

■ Aerospace instrumentation

■ Nuclear and high-energy physics

Description

The RHF1401 is a 14-bit analog-to-digital
converter that uses pure (ELDRS-free) CMOS

0.25 µm technology combining high performance,
radiation robustness and very low power
consumption.

Table 1. Device summary

Ceramic SO-48 package

The upper metallic lid is not electrically connected to any

pins, nor to the IC die inside the package.

The RHF1401 is based on a pipeline structure
and digital error correction to provide excellent
static linearity. Specifically designed to optimize
power consumption, the device only dissipates
85 mW at 20 Msps, while maintaining a high level
of performance. The device also integrates a
proprietary track-and-hold structure to ensure a
large effective resolution bandwidth.

Voltage references are integrated in the circuit to
simplify the design and minimize external
components. A tri-state capability is available on
the outputs to allow common bus sharing. A data­ready signal, which is raised when the data is
valid on the output, can be used for
synchronization purposes.

The RHF1401 has an operating temperature
range of -55° C to +125° C and is available in a
small 48-pin ceramic SO-48 package.

Order code SMD pin

RHF1401KSO1 -

RHF1401KSO-01V 5962F0626001VXC QMLV-Flight

April 2012 Doc ID 13317 Rev 7 1/39

This is information on a product in full production.

Quality

level

Engineering

model

Package

SO-48 Gold 1.1 g - -55 °C to +125 °C

Lead

finish

Mass EPPL Temp range

www.st.com

39

Contents RHF1401

Contents

1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.2 Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.3 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.4 Equivalent circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.1 Absolute maximum ratings and operating conditions . . . . . . . . . . . . . . . . . 9

2.2 Timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.3 Electrical characteristics (after 300 kRad) . . . . . . . . . . . . . . . . . . . . . . . . 11

2.4 Results for differential input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.5 Results for single ended input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3 User manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.1 Optimizing the power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.2 Driving the analog input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3.3 Reference connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

3.3.1 Internal references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

3.3.2 External references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

3.4 Clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

3.5 Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

3.5.1 Digital inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

3.5.2 Digital outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

3.5.3 Digital output load considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

3.6 PCB layout precautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

4 Definitions of specified parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

4.1 Static parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

4.2 Dynamic parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

2/39 Doc ID 13317 Rev 7

RHF1401 Contents

5 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

6 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Doc ID 13317 Rev 7 3/39

Description RHF1401

1 Description

1.1 Block diagram

Figure 1. RHF1401 block diagram

VREFP

REFMODE

VIN

INCM

VINB

stage

1

stage

2

stage

n

INCM

Reference

circuits

GNDA

IPOL

VREFM
DFSB

CLK

Timing

GND

Sequencer-phase shifting

Digital data correction

Buffers

VCCBI

OEB

DR

D0

D13

OR

VCCBE

AM04556

4/39 Doc ID 13317 Rev 7

RHF1401 Description

1.2 Pin connections

Figure 2. pin connections (top view)

GNDBI

GNDBE

VCCBE

NC
NC
OR

(MSB)D13

D12
D11
D10

D9
D8
D7
D6
D5
D4
D3
D2
D1

(LSB)D0

DR

VCCBE

GNDBE

VCCBI

10

10
11

11
12

12
13

13
14

14
15

15
16

16
17

17
18

18
19

19
20

20
21

21
22

22
23

23
24

24

1

1
2

2
3

3
4

4
5

5
6

6
7

7
8

8
9

9

48

48

DGND

47

47

DGND

46

46

CLK

45

45

DGND

44

44

DVCC

43

43

DVCC

42

42

AVCC

41

41

AVCC

40

40

AGND

39

39

INCM
AGND

38

38

VINB

37

37

AGND

36

36

VIN

35

35

AGND

34

34

VREFM

33

33

VREFP

32

32

IPOL

31

31

AGND

30

30

AVCC

29

29

AVCC

28

28

DFSB

27

27

OEB

26

26

REFMODE

25

25

Doc ID 13317 Rev 7 5/39

Description RHF1401

1.3 Pin descriptions

Table 2. Pin descriptions

Pin Name Description Observations Pin Name Description Observations

1 GNDBI Digital buffer ground 0 V 25 REFMODE Ref. mode control input

2 GNDBE Digital buffer ground 0 V 26 OEB Output enable input

3VCCBE

4NC

5NC

6 OR Out of range output

7 D13(MSB)

8 D12 Digital output

9 D11 Digital output

10 D10 Digital output

11 D9 Digital output

12 D8 Digital output

13 D7 Digital output

14 D6 Digital output

15 D5 Digital output

16 D4 Digital output

17 D3 Digital output

18 D2 Digital output

19 D1 Digital output

20 D0(LSB) Digital output LSB

21 DR Data ready output

22 VCCBE

23 GNDBE Digital buffer ground 0 V 47 DGND Digital ground 0 V

24 VCCBI

Digital buffer power
supply

Most significant bit
output

Digital buffer power
supply

Digital buffer power
supply

2.5 V/3.3 V 27 DFSB Data format select input

Not connected to the
dice

Not connected to the
dice

CMOS output
(2.5 V/3.3 V)

CMOS output
(2.5 V/3.3 V)

CMOS output
(2.5 V/3.3 V)

CMOS output
(2.5 V/3.3 V)

CMOS output
(2.5 V/3.3 V)

CMOS output
(2.5 V/3.3 V)

CMOS output
(2.5 V/3.3 V)

CMOS output
(2.5 V/3.3 V)

CMOS output
(2.5 V/3.3 V)

CMOS output
(2.5 V/3.3 V)

CMOS output
(2.5 V/3.3 V)

CMOS output
(2.5V /3.3 V)

CMOS output
(2.5 V/3.3 V)

CMOS output
(2.5 V/3.3 V)

CMOS output
(2.5 V/3.3 V)

CMOS output

(1)

(2.5 V/3.3 V)

2.5 V/3.3 V 46 CLK Clock input

2.5 V 48 DGND Digital ground 0 V

28 AVCC Analog power supply 2.5 V

29 AVCC Analog power supply 2.5 V

30 AGND Analog ground 0 V

31 IPOL Analog bias current input

32 VREFP Top voltage reference

33 VREFM Bottom voltage reference 0 V

34 AGND Analog ground 0 V

35 VIN Analog input 1 V

36 AGND Analog ground 0 V

37 VINB Inverted analog input 1 V

38 AGND Analog ground 0 V

39 INCM Input common mode

40 AGND Analog ground 0 V

41 AVCC Analog power supply 2.5 V

42 AVCC Analog power supply 2.5 V

43 DVCC Digital power supply 2.5 V

44 DVCC Digital power supply 2.5 V

45 DGND Digital ground 0 V

1. See load considerations in Chapter 2.2: Timing characteristics.

2.5 V/3.3 V CMOS
input

2.5 V/3.3 V CMOS
input

2.5 V/3.3 V CMOS
input

Can be external or
internal

pp

pp

Can be external or
internal

2.5 V compatible
CMOS input

6/39 Doc ID 13317 Rev 7

RHF1401 Description

1.4 Equivalent circuits

Figure 3. Analog inputs Figure 4. Output buffers

AVCC

VIN or VINB

7 pF

(pad)

OEB

AGND

Data

AVCC

AGND

AM04557

Figure 5. Clock input Figure 6. Data format input

VCCBE

CLK

DVCC

DFSB

VCCBE

GNDBE

D0 …D13

7 pF

(pad)

AM04558

7 pF

(pad)

DGND

AM04559

7 pF

(pad)

GNDBE

Figure 7. Reference mode control input Figure 8. Output enable input

REFMODE

7 pF

(pad)

VCCBE

GNDBE

AM04561

OEB

7 pF

(pad)

VCCBE

GNDBE

AM04560

AM04562

Doc ID 13317 Rev 7 7/39

Description RHF1401

Figure 9. VREFP and INCM input

AVCC

AVCC

VREFP

7 pF

(pad)

AGND

Figure 10. VREFM input

INCM

7 pF

REFMODE REFMODE

High input impedance

VREFM

7 pF

(pad)

(pad)

AGND

AVCC

AGND

AM04564

AM04563

8/39 Doc ID 13317 Rev 7

RHF1401 Electrical characteristics

2 Electrical characteristics

2.1 Absolute maximum ratings and operating conditions

Table 3. Absolute maximum ratings

Symbol Parameter Values Unit

AV

CC

DV

CC

V

CCBI

V

CCBE

V

IN

V

INB

V

REFP

V

INCM

I

Dout

T

stg

R

thjc

R

thja

ESD HBM (human body model)

1. Human body model: a 100 pF capacitor is charged to the specified voltage, then discharged through a

1.5 kΩ resistor between two pins of the device. This is done for all couples of connected pin combinations
while the other pins are floating.

Analog supply voltage 3.3 V

Digital supply voltage 3.3 V

Digital buffer supply voltage 3.3 V

Digital buffer supply voltage 3.6 V

Analog inputs: bottom limit −> top limit -0.6 V −> AVCC+0.6 V V

External references: bottom limit −> top limit -0.6 V −> AVCC+0.6 V V

Digital output current -100 to 100 mA

Storage temperature -65 to +150 °C

Thermal resistance junction to case 22 °C/W

Thermal resistance junction to ambient 125 °C/W

(1)

2kV

Table 4. Operating conditions

Symbol Parameter Min Typ Max Unit

AV

CC

DV

CC

V

CCBI

V

CCBE

V

REFP

V

REFM

V

INCM

V

IN

V

INB

DFSB

OEB

1. See Figure 25. for differential input and Figure 42. to Figure 49. for single-ended.

Analog supply voltage 2.3 2.5 2.7 V

Digital supply voltage 2.3 2.5 2.7 V

Digital internal buffer supply 2.3 2.5 2.7 V

Digital output buffer supply 2.3 2.5 3.4 V

Forced top voltage reference 0.8 1 1.4 V

Bottom external reference voltage 0 0 0.5 V

Forced common mode voltage 0.2 0.5 1.1 V

Max. voltage versus GND 1 1.6

(1)

Min. voltage versus GND -0.2 GND V

Digital inputs 0 V

CCBE

V

VREFMODE

Doc ID 13317 Rev 7 9/39

Electrical characteristics RHF1401

2.2 Timing characteristics

Table 5. Timing characteristics

Symbol Parameter Test conditions Min Typ Max Unit

DC Clock duty cycle

T

T

T

T

T

T

Data output delay (fall of

od

clock to data valid)

Data pipeline delay

pd

Falling edge of OEB to

on

digital output valid data

Rising edge of OEB to

off

digital output tri-state

Data rising time 10 pF load capacitance 6 ns

rD

Data falling time 10 pF load capacitance 3 ns

fD

(1)

(2)

F

= 20 Msps 45 50 65 %

s

10 pF load capacitance 5 7.5 13 ns

Duty cycle = 50% 7.5 7.5 7.5 cycles

1. As per Figure 11.

2. If the duty cycle does not equal 50%: Tpd = 7 cycles + CLK pulse width.

Figure 11. Timing diagram

N+6

N+5

N+4

Analog
input

N-2

N-1

N

N+1

N+3

N+2

1ns

1ns

N+7

N+8

CLK

Tpd+ Tod

Tod

OEB

Data
output

DR

OR

Tod

N-8 N-7 N-6 NN-5 N -4 N+1N-3 N-1

The input signal is sampled on the rising edge of the clock while the digital outputs are
synchronized on the falling edge of the clock. The duty cycles on DR and CLK are the same.

The rising and falling edges of the OR pin are synchronized with the falling edge of the DR
pin.

10/39 Doc ID 13317 Rev 7

Toff Ton

HZ state

AM06120

RHF1401 Electrical characteristics

2.3 Electrical characteristics (after 300 kRad)

Unless otherwise specified, the test conditions in the following tables are:
AVCC = DVCC = VCCBI =VCCBE = 2.5 V, F
VREFP = 1V, INCM = 0.5V, VREFM = 0 V, T

Table 6. Analog inputs

Symbol Parameter Test conditions Min Typ Max Unit

=20 Msps, FIN= 15 MHz, V

s

= 25°C.

amb

at -1 dBFS,

IN

V

IN-VINB

C

Z

Full-scale reference voltage

(1)

(FS)

Input capacitance 7 pF

IN

Input impedance Fs = 20 Msps 3.3 kΩ

IN

ERB Effective resolution bandwidth

1. See Chapter 4: Definitions of specified parameters on page 33 for more information.

Table 7. Internal reference voltage

VREFP = 1 V
(forced)
VREFM = 0 V

(1)

2V

70 MHz

Symbol Parameter Test conditions Min Typ Max Unit

REFMODE = 0
internal reference

R

Output resistance of internal

out

reference

on

REFMODE = 1
internal reference

30 Ω

7.5 kΩ

off

V

REFP

V

INCM

1. V

REFM

Table 8. External reference voltage

Top internal reference voltage

Input common mode voltage REFMODE = 0 0.40 0.44 0.50 V

connected to GND.

(1)

REFMODE = 0 0.76 0.84 0.95 V

(1)

pp

Symbol Parameter Test conditions Min Typ Max Unit

V

REFP

V

REFM

V

INCM

1. See Figure 59.& Figure 60

Table 9. Static accuracy

Forced top reference voltage REFMODE = 1 0.8 1.4 V

Forced bottom ref voltage REFMODE = 1 0 0.5 V

Forced common mode voltage REFMODE = 1 0.2 1.1 V

Symbol Parameter Test conditions Min Typ Max Unit

(2)

(1)

Fin= 1.5 Msps

±0.4 LSB
Vin at -1 dBFS
Fs=1.5 Msps

±3 LSB

Guaranteed

DNL Differential non-linearity

INL Integral non-linearity

Monotonicity and no missing
codes

1. See Figure 33 and Chapter 4 for more information. This parameter is not tested.

2. See Figure 34 and Chapter 4 for more information. This parameter is not tested.

Doc ID 13317 Rev 7 11/39

Electrical characteristics RHF1401

Table 10. Digital inputs and outputs

Symbol Parameter Test conditions Min Typ Max Unit

Clock input

CT Clock threshold DV

CA

Square clock amplitude
(DC component = 1.25 V)

= 2.5 V 1.25 V

CC

DV

= 2.5 V 0.8 2.5 Vpp

CC

Digital inputs

V

IL

V

IH

Logic "0" voltage V

Logic "1" voltage V

= 2.5 V 0

CCBE

= 2.5 V

CCBE

0.75 x
V

CCBE

0.25 x

V

CCBE

V

CCBE

Digital outputs

V

OL

V

OH

I

OZ

C

L

Table 11. Dynamic characteristics

Logic "0" voltage I

= -10 µA 0 0.25 V

OL

Logic "1" voltage IOH = 10 µA

High impedance leakage
current

Output load capacitance

OEB set to V

High CLK
frequencies

V

CCBE

-0.25

IH

-15 15 µA

15 pF

Symbol Parameter Test conditions Min Typ Max Unit

SFDR Spurious free dynamic range

SNR Signal to noise ratio 66 70 dB

THD Total harmonic distortion 70 86 dB

SINAD

Signal to noise and distortion
ratio

F

= 15 MHz

in

= 20 Msps

F

s

V

at -1 dBFS

in

internal references

= 6 pF

C

L

70 91 dBFS

65 70 dB

ENOB Effective number of bits 10.6 11.5 bits

V

V

V

Higher values of SNR, SINAD and ENOB can be obtained by increasing the full-scale range
of the analog input if the sampling frequency allows it.

12/39 Doc ID 13317 Rev 7

RHF1401 Electrical characteristics

G

2.4 Results for differential input

Setup

● AVCC = DVCC = VCCBI = VCCBE = 2.5V

● VREFP = 1 V

● VREFM = 0 V

● INCM = Vin/2

● REFMODE = 1 (internal references are disabled)

● Vin = full scale - 0.3 dB

● Ta mb = 2 5 C °

● A square clock is applied

Unless other test conditions are specified.

Figure 12. Differential configuration

External 1V

REFP

GENERATOR

ENERATOR

Dierential

input signal

C

f

VIN

2.5 V

VCCBE

VCCBI

AVCC

DVCC

VOCM

VOCM

External

C

is a filter capacitor to cut the HF noise. Its value is 10 nF for input frequencies equal to or

f

INCM

VINB

REFM

Ground

AM04565

below 20 kHz. The value of the capacitor is divided by two when the input frequency is
multiplied by 2.

Doc ID 13317 Rev 7 13/39

Electrical characteristics RHF1401

1 M

Figure 13. ENOB vs. input frequency Figure 14. SINAD vs. input frequency

12

11.6

11.2

Fs =

10 ksps

ENOB (bits)

10.8

100 ksps

1 Msps

10.4

10

10E+0 100E +0 1E+3 10E+3 100E+3 1E +6 10E +6 100E +6

10 Msps

30 Msps

Input frequency

-60

-62

-64

-66

-68

SINA D (dB)

-70

-72

-74

-76

1E +1 1 E +2 1E +3 1 E +4 1E +5 1E +6 1 E+7 1E +8

Fs =

10 ksps

100 ksps

1 Msps

10 Msps

30 Msps

Input freq uenc y

Figure 15. THD vs. input frequency Figure 16. SNR vs. input frequency

-60

Fs =

-65

10 ksps

100 ksps

1 Msps

-70

10 Msps

30 Msps

-75

THD (dB)

-80

-85

76

74

72

70

68

SNR (dB)

66

64

62

Fs =

10 ksps

100 ksps

sps

10 Msps

30 Msps

-90

1E +1 1E +2 1 E +3 1E +4 1E +5 1E +6 1 E +7 1E +8

Input frequency

60

1E+1 1E+2 1E+3 1E+4 1E+5 1E +6 1E +7 1E +8

Input frequenc y

Figure 17. SFDR vs. input frequency Figure 18. Consumption vs. input frequency

90

85

80

75

SFDR (dB)

70

Fs =

10 ksps

100 ksps

1 Msps

10 Msps

65

60

1E +1 1E +2 1E +3 1E +4 1E +5 1E +6 1E +7 1E +8

30 Msps

Input frequency

120

110

100

90

80

70

er cons umption (mW)

60

Po

50

40

30

1E +1 1 E +2 1E +3 1 E +4 1E +5 1 E +6 1E +7 1E +8

Fs =

10 ksps

100 ksps

1 Msps
10 Msps
30 Msps

Input frequency

14/39 Doc ID 13317 Rev 7

RHF1401 Electrical characteristics

50 kHz

50 kHz

50 kH

o

Figure 19. ENOB vs. sampling frequency Figure 20. SINAD vs. sampling frequency

12

11.5

11

ENOB (bits)

10.5

10

1E+4 1E+5 1E+6 1E+7 1E+8

Fin =

10 Hz

1 kHz

2 MHz

10 MHz

S ampling frequenc y

-60

-62

-64

Fin =
10 Hz

1 kHz

-66

-68

SINAD (dB)

50 kHz

2 MHz

10 MHz

-70

-72

-74

1E +4 1E +5 1E +6 1E +7 1E +8

Sampling frequency

Figure 21. THD vs. sampling frequency Figure 22. SNR vs. sampling frequency

-60

-65
Fin =

10 Hz

-70

1 kHz

50 kHz

2 MHz

-75

THD (dB)

10 MHz

-80

-85

76

74

72

70

68

SNR (dB)

66

64

62

Fin =
10 Hz

1 kHz

2 MHz

10 MHz

-90

1E+4 1E +5 1E +6 1E +7 1E +8

S ampling frequency

60

1E +4 1E +5 1E +6 1E +7 1E +8

S ampling frequenc y

Figure 23. SFDR vs. sampling frequency Figure 24. Power consumption vs. sampling

frequency

90

85

80

75

SFDR (dB)

70

65

60

1E +4 1E +5 1E +6 1E +7 1 E +8

Fin =
10 Hz

1 kHz

2 MHz

10 MHz

z

S ampling frequency

180

160

140

120

100

80

wer cons umption (mW)
P

60

40

20

1E+4 1E+5 1E+6 1E+7 1E+8

Fin =

10 Hz

1 kHz

50 kHz

2 MHz

10 MHz

S ampling frequency

Doc ID 13317 Rev 7 15/39

Electrical characteristics RHF1401

1 Msps

Figure 25. ENOB vs. VREFP Figure 26. SINAD vs. VREFP

12.5

12

11.5

11

Fs =

10 ksps

ENOB (bits)

10.5

100 ksps

10 Msps

10

20 Msps
25 Msps
30 Msps

9.5

0.8 0.9 1 1.1 1.2 1.3 1.4

35 Msps

External Vrefp (V)

-50
Fs =

10 ksps

-55

100 ksps

1 Msps

10 Msps

-60

20 Msps
25 Msps
30 Msps
35 Msps

-65

SINAD (dB)

-70

-75

-80

0.8 0.9 1 1.1 1.2 1.3 1.4

External Vrefp (V )

Figure 27. SNR vs. VREFP Figure 28. THD vs. VREFP

80

75

70

Fs =

10 ksps

65

SNR (dB)

60

55

0.8 0.9 1 1.1 1.2 1.3 1.4

100 ksps

1 Msps
10 Msps
20 Msps
25 Msps
30 Msps
35 Msps

External Vrefp (V )

-50

-55

-60

-65

Fs =

10 ksps

100 ksps

1 Msps
10 Msps
20 Msps
25 Msps
30 Msps
35 Msps

-70

THD (dB)

-75

-80

-85

-90

0.8 0.9 1 1.1 1.2 1.3 1.4

External Vrefp (V )

Figure 29. ENOB vs. sine clock, diff. input Figure 30. Clock threshold vs. temperature

12

11.5

11

ENOB (bits)

10.5

10

1 Msps 10 Msps 100 Msps

Sampling frequency

Fin =

10 Hz

1 kHz

50 kHz

2 MHz

10 MHz

16/39 Doc ID 13317 Rev 7

RHF1401 Electrical characteristics

10 k

e

100 k

Figure 31. ENOB vs. temperature Figure 32. Power consumption vs. temp.

12.5

12

11.5

11

Fs =

10.5

ENOB (bits)

10

9.5

9

-55 -35 -15 5 25 45 65 85 105 125

200 sps

1 ksps

100 ksps

1 Msps

sps

Temperature (C°)

50

40

30

20

r cons umption (mW)

Pow

10

0

-55 -35 -15 5 25 45 65 85 105 125

Fs =

10 ksps

sps

1 Msps

R pol=330 kOhms

Temperature (C °)

Figure 33. DNL, differential input Figure 34. INL, differential input

DNL (LSB)

INL (LSB)

Doc ID 13317 Rev 7 17/39

Electrical characteristics RHF1401

G

2.5 Results for single ended input

Setup

● AVCC = DVCC = VCCBI = VCCBE = 2.5V

● VREFP = 1 V

● VREFM = 0 V

● INCM = Vin/2

● REFMODE = 1 (internal references are disabled)

● Vin = full scale - 0.3 dB

● Ta mb = 2 5 C °

● A square clock is applied

Unless other test conditions are specified.

Figure 35. Single-ended input configuration

External 1V

REFP

REFM

Ground

VIN

VINB

2.5 V

VCCBE

VCCBI

AVCC
DVCC

AM04566

Single ended

GENERATOR

ENERATOR

VOCM

VOCM

C

is a filter capacitor to cut the HF noise. Its value is 10 nF for input frequencies equal to or

f

input signal

C

External

f

INCM

below 20 kHz. The value of the capacitor is divided by two when the input frequency is
multiplied by 2.

18/39 Doc ID 13317 Rev 7

RHF1401 Electrical characteristics

100 ksps

Figure 36. ENOB vs. Fin, single-ended Figure 37. SINAD vs. Fin, single-ended

11.5

11

10.5

10

ENOB (bits)

9.5

9

1E +1 1E +2 1E +3 1E +4 1E +5 1 E+6 1 E +7 1E +8

Fs =

10 ksps

1 Msps

10 Msps

30 Msps

Input frequency

-50

Fs =

10 ksps

-55

-60

SINAD (dB )

-65

-70

1E +1 1E +2 1E +3 1E +4 1E +5 1E +6 1E +7 1E +8

100 ksps

1 Msps

10 Msps

30 Msps

Input frequenc y

Figure 38. THD vs. Fin, single-ended Figure 39. SNR vs. Fin, single-ended

-55

-60

-65

-70

THD (dB)

-75

-80

Fs =

10 ksps

100 ksps

1 Msps

10 Msps

30 Msps

70

67

64

SNR (dB)

61

58

Fs =

10 ksps

100 ksps

1 Msps

10 Msps

30 Msps

-85

1E+1 1E +2 1E +3 1E +4 1E +5 1E+6 1E+7 1E+8

Input frequency

55

1E +1 1E +2 1E +3 1E +4 1 E +5 1E +6 1E +7 1E +8

Input frequency

Figure 40. SFDR vs. Fin, single-ended Figure 41. Power consumption vs. Fin

85

80

75

70

SFDR (dB)

65

60

55

1E+1 1E+2 1E+3 1E +4 1E +5 1E+6 1E +7 1E +8

Fs =

10 ksps

100 ksps

1 Msps

10 Msps

30 Msps

Input frequency

120

100

Fs =

80

60

er cons umption (mW )

Po

40

20

1E +1 1E +2 1 E +3 1E +4 1E +5 1E +6 1E +7 1E +8

10 ksps

100 ksps

1 Msps

10 Msps

30 Msps

Input frequency

Doc ID 13317 Rev 7 19/39

Electrical characteristics RHF1401

100 k

Fs =

Figure 42. ENOB vs. Vin, Fin 1 kHz, Vrefp = 0.8 V Figure 43. ENOB vs Vin, Fin = 2 MHz, Vrefp = 0.8 V

11.5
Fin = 1 kHz - VREFP=0.8V

11.0

10.5

10.0

ENOB (bits)

9.5

9.0

Fs =

10 ksps

100 ksps

1 Msps
10 Msps
20 Msps
25 Msps
30 Msps

1.01.11.21.31.41.51.6

Vin (Vpp)

11.5
Fin = 2MHz - VR EFP=0.8V

11.0

10.5

10.0

ENOB (bits)

Fs =

2 Msps

10 Msps

9.5

20 Msps
25 Msps
30 Msps

9.0

1.0 1.1 1.2 1.3 1.4 1. 5 1.6

Vin (Vpp)

Figure 44. ENOB vs. Vin, Fin 1 kHz, Vrefp = 1.0 V Figure 45. ENOB vs Vin, Fin = 2 MHz, Vrefp = 1.0 V

11.5
Fin = 1kHz - VREFP=1.0V

11.0

10.5

11.5
Fin = 2MHz - VREFP=1.0V

11.0

10.5

10.0

ENOB (bits)

9.5

9.0

Fs =

10 ksps

sps

1 Msps
10 Msps
20 Msps
25 Msps
30 Msps

1.0 1.1 1.2 1.3 1.4 1.5 1.6

Vin (Vpp)

10.0

ENOB (bits)

9.5

9.0

Fs =

2 Msps
10 Msps
20 Msps
25 Msps
30 Msps

1.01.11.21.31.41.51.6

Vin (Vpp)

Figure 46. ENOB vs. Vin, Fin 1 kHz, Vrefp = 1.2 V Figure 47. ENOB vs Vin, Fin = 2 MHz, Vrefp = 1.2 V

11.5
Fin = 1kHz - VREFP=1.2V

11.0

10.5

10.0

ENOB (bits)

9.5

9.0

Fs =

10 ksps

100ksps

1 Msps
10 Msps
20 Msps
25 Msps
30 Msps

1.0 1.1 1.2 1.3 1.4 1.5 1.6

Vin (Vpp)

11.5
F in = 2 MH z - V R E FP =1.2 V

11.0

10.5

ENOB (bits)

10.0

2 Msps

10 Msps

9.5
20 Msps
25 Msps
30 Msps

9.0

1.0 1.1 1.2 1.3 1.4 1.5 1.6

Vin (Vpp)

20/39 Doc ID 13317 Rev 7

RHF1401 Electrical characteristics

Figure 48. ENOB vs. Vin, Fin 1 kHz, Vrefp = 1.4 V Figure 49. ENOB vs Vin, Fin = 2 MHz, Vrefp = 1.4 V

11.5
Fin = 1kHz - VREFP=1.4V

11.0

10.5

10.0

ENOB (bits)

9.5

9.0

1.0 1.1 1.2 1.3 1.4 1.5 1.6

Vin (Vpp)

Fs =

10 ksps

100 ksps

1 Msps
10 Msps
20 Msps
25 Msps
30 Msps

11.5
Fin = 2MHz - VR EFP=1.4V

11.0

10.5

10.0

ENOB (bits)

9.5

9.0

1.01.11.21.31.41.51.6

Fs =

2 Msps
10 Msps
20 Msps
25 Msps
30 Msps

Vin (V pp)

Doc ID 13317 Rev 7 21/39

User manual RHF1401

3 User manual

3.1 Optimizing the power consumption

The polarization current in the input stage is set by an external resistor (R

). When

pol

selecting the resistor value, it is possible to optimize the power consumption according to
the sampling frequency of the application. For this purpose, an external R

resistor is

pol

placed between the IPOL pin and the analog ground.

The values in Figure 50 are achieved with VREFP = 1 V, VREFM = 0 V, INCM = 0.5 V and
the input signal is 2 Vpp with a differential DC connection. If the conditions are changed, the
Rpol resistor varies slightly.

Figure 50 shows the optimum Rpol resistor value to obtain the best ENOB value. It also

shows the minimum and maximum values to get good results. ENOB decreases by
approximately 0.2 dB when you change Rpol from optimum to maximum or minimum.

If Rpol is higher than the maximum value, there is not enough polarization current in the
analog stage to obtain good results. If Rpol is below the minimum, THD increases
significantly.

Therefore, the total dissipation can be adjusted across the entire sampling range to fulfill the
requirements of applications where power saving is critical.

For sampling frequencies below 2 MHz, the optimum resistor value is approximately
400 kOhms.

Figure 50. Rpol values vs. F

1000

S

max im um
optimum
minimum

100

is tor (k Ohms )

10

R pol res

1

0 5 10 15 20 25 30 35 40

S ampling frequenc y (Ms ps )

The power consumption depends on the Rpol value and the sampling frequency. In

Figure 51, it is shown with the internal references disabled (REFMODE = 1) and Rpol

defined in Figure 50 as the optimum.

22/39 Doc ID 13317 Rev 7

RHF1401 User manual

o

Figure 51. Power consumption values vs. Fs with internal references disabled

200

180

160

140

120

100

nsumption (mW)

80

60

40

Power c

20

0

0 5 10 15 20 25 30 35 40

S ampling frequency (MHz)

Doc ID 13317 Rev 7 23/39

User manual RHF1401

3.2 Driving the analog input

The input frequency can range from DC to tens of MHz.

The input stages (VIN and VINB) have a special design that limits the input amplitude. For
each of them, the maximum input voltage is 1.6 V for low sampling frequencies and less for
high sampling frequencies. The low voltage is ground.

In differential mode, high sampling limitation is seen in Figure 25.

For all input frequencies, it is mandatory to add a capacitor on the PCB (between VIN and
VINB) to cut the HF noise. The lower the frequency, the higher the capacitor.

The full-scale range is twice the difference between Vrep and Vrefm.

Figure 52. Equivalent VIN - VINB (differential input)

VIN -VINB

(level + FS, code 16383)

VIN

FS (full-scale)
= 2(VREFP - VREFM)

INCM (level 0, code 8191)

VINB

(level - FS, code 0)

AM04567

Table 12. Output codes for DFSB = 1

Vin - Vinb = Output code

+range/2 16383

0 8191

-range/2 0

The RHF1401 is designed to obtain optimum performance when driven on differential inputs
with a differential amplitude of two volts peak-to-peak (2 V

). This is the result of 1 Vpp on

pp

the VIN and VINB inputs in phase opposition.

The RHF1401 is specifically designed to meet sampling requirements for intermediate
frequency (IF) input signals. In particular, the track-and-hold in the first stage of the pipeline
is designed to minimize the linearity limitations as the analog frequency increases.

24/39 Doc ID 13317 Rev 7

RHF1401 User manual

V

Figure 53. 2 Vpp differential input

1 V

INCM

1 Vp -p

VIN

REFP

REFMODE

2.5

INCM

1 Vp -p

VIN -VINB (2 Vp-p)

VINB

INCM

0.5V

REFM

Ground

AM04570

Figure 54 shows a differential input solution. The input signal is fed to the transformer’s

primary, while the secondary drives both ADC inputs. The transformer must be matched
with generator output impedance: 50 Ω in this case for proper matching with a 50 Ω
generator. The tracks between the secondary and VIN and VINB pins must be as short as
possible.

Figure 54. Differential implementation using a balun

50 Ω track

Analog input signal

(50 Ω output)

ADT1 -1

1:1

Short track

33 pF

VIN

50 Ω

VINB

INCM

External

470 nF* ceramic
(as close as possible
to the transformer)

*the use of a ceramic technology is
preferable for a large bandwidth
stability of the capacitor

100 nF* ceramic
(as close as
possible to
INCM pin)

INCM
(optional)

AM04571

The input common-mode voltage of the ADC (INCM) is connected to the center tap of the
transformer’s secondary in order to bias the input signal around the common voltage (see

Table 7 on page 11).The INCM is decoupled to maintain a low noise level on this node.

Ceramic technology for decoupling provides good capacitor stability across a wide
bandwidth.

Doc ID 13317 Rev 7 25/39

User manual RHF1401

Figure 55. Optimized single-ended configuration (DC coupling), external REFP

high input rail

INCM

0 V (ground)

Vp - p

VIN -VINB

VIN

VIN

VINB

External

INCM

External

REFP

INCM

REFM

Ground

AM04569

The RHF1401 is designed for use in a differential input configuration. Nevertheless, it can
achieve good performance in a single-ended input configuration. In single-ended,
performances depend on the input voltage, input frequency, voltage of references and
sampling frequency (refer to Figure 42. to Figure 49.)

Some applications may require a single-ended input, which can easily be achieved with the
configuration shown in Figure 56. However, with this type of configuration, a degradation in
the rated performance of the RHF1401 may occur compared with a differential
configuration. A sufficiently decoupled DC reference should be used to bias the RHF1401
inputs. An AC-coupled analog input can also be used and the DC analog level set with a
high value resistor R (6 kΩ to 100 kΩ) connected to a proper DC source. Cin and R behave
like a high-pass filter and are calculated to set the lowest possible cut-off frequency.

26/39 Doc ID 13317 Rev 7

RHF1401 User manual

Figure 56. AC-coupling single-ended input configuration

50 Ω track

Analog input signal

(50 Ω output)

Cin

50 Ω

R

R

Short track

INCM

VIN

VINB

100 nF ceramic*
(as close as possible
to INCM pin)

External INCM
(optional)

AM04572

470 pF

ceramic*

Short track

100 nF

ceramic*

*the use of a ceramic technology is
preferable for a large bandwidth
stability of the capacitor

Figure 57. AC-coupling single-ended input configuration for low frequencies

50 Ω track

Analog input signal

(50 Ω output)

50 Ω

Cin

C

Short track

R

R

Short track

VIN

INCM

VINB

*ceramic technology for a large
bandwidth stability of the capacitor

100 nF ceramic*
(as close as possible
to INCM pin)

External INCM
(optional)

AM04573

The C capacitor is efficient in reducing noise at high frequencies. When coupled with the
resistors, R and C together behave like a high-pass filter. For example, if R = 10 k and
C = 33 pF, the cut-off frequency of this filter equals 482 kHz.

Doc ID 13317 Rev 7 27/39

User manual RHF1401

INCM

3.3 Reference connections

3.3.1 Internal references

In the standard configuration, the ADC is biased with two internal reference voltages. There
are two voltage references: VREFP and INCM. They should be decoupled to minimize low
and high frequency noise. Both are enabled when the REFMODE pin is set to 0.

The VREFM pin has no internal reference and must be connected to a voltage reference. It
is usually connected to the analog ground.

Figure 58. Internal reference setting

As close as possible
to the ADC pins

3.3.2 External references

External reference voltages can be used for specific applications requiring even better
linearity or enhanced temperature behavior or different voltage values (see Table 7: Internal

reference voltage on page 11). Internal references are disabled when the REFMODE pin is

equal to 1. In this case, external references must be applied to the device.

The external voltage references with the configuration shown in Figure 59 and Figure 60
can be used to obtain optimum performance. Decoupling is achieved by using ceramic
capacitors, which provide optimum linearity versus frequency.

VIN

VINB

REFMODE

VREFP

INCM

VREFM

100 nF*

100 nF*

*the use of a cerami c technology is
preferable for a large bandwidth
stability of the capacitor.

470 nF*

470 nF*

AM04574

28/39 Doc ID 13317 Rev 7

RHF1401 User manual

Figure 59. External reference setting Figure 60. Example with zeners

VIN

VINB

REFMODE

VCCA VREFP

INCM

VREFM

As close as possible
to the ADC pins

100 nF*

100 nF*

470 nF*

470 nF*

DC

source

DC

source

AM04575

VIN

VINB

As close as possible

As close as possible
to the ADC pins

to the ADC pins

VCCA VREFP

INCM

REFMODE

VREFM

100 nF*

100 nF*

100 nF*

100 nF*

R

R1

R2

470 nF*

470 nF*

470 nF*

470 nF*

AM04576

Note: *The use of ceramic technology is preferable to ensure large bandwidth stability of the

capacitor.

In multi-channel applications, the high impedance input (when REFMODE = 1) of the
references allows one to drive several ADCs with only two voltage reference devices.

The voltage of the analog input common mode (INCM) should stay close to V

REFP

/2. Higher

levels introduce more distortion.

Doc ID 13317 Rev 7 29/39

User manual RHF1401

3.4 Clock input

The quality of the converter very much depends on the accuracy of the clock input in terms
of jitter. The use of a low-jitter, crystal-controlled oscillator is recommended.

The following points should also be considered.

● The clock’s power supplies must be independent of the ADC’s output supplies to avoid

digital noise modulation at the output.

● When powered-on, the circuit needs several clock periods to reach its normal operating

conditions.

Figure 61. Clock input schematic

Square clock

DVcc/2

Sine clock

DVcc/2

CLK

Short track

50 Ω clock generator

50 Ω

CLK

Short track

50 Ω

AM04577

The signal applied to the CLK pin is critical to obtain full performance from the RHF1401.
Below 10 MHz, the sine clock does not have transition times fast enough to achieve good
performances. It is recommended to use a square signal with fast transition times and to
place proper termination resistors as close as possible to the device.

The sampling instant is determined by the clock signal’s rising edge. The jitter associated
with this instant must be as low as possible to avoid SNR degradation on fast moving input
signals. To make sure any error is less than 0.5 LSB, the total jitter T

must satisfy the

j

following condition for a full-scale input signal.

j

π F

⋅⋅

n1+

2

in

1

-------------------------------------- -

<

T

For example, the total jitter with a 14-bit resolution for a 10 MHz full-scale input should be no
more than 1 picosecond (rms).

In most cases, the clock signal jitter is responsible for noise. Therefore, you must pay
attention to the clock signal when fast signals are acquired with a low frequency clock.

30/39 Doc ID 13317 Rev 7

RHF1401 User manual

3.5 Operating modes

Extra functionalities are provided to simplify the application board as much as possible. The
operating modes offered by the RHF1401 are described in Tab le 1 3.

Table 13. RHF1401 operating modes

Inputs Outputs

Analog input differential

amplitude

(V

(V

(VIN-V

XXHHZ

1. High impedance.

) above maximum range

IN-VINB

) below minimum range

IN-VINB

) within range

INB

3.5.1 Digital inputs

Data format select bit (DFSB): when set to low level (VIL), the digital input DFSB provides

a two’s complement digital output MSB. This can be of interest when performing some
further signal processing. When set to high level (V
output coding.

Output enable bit (OEB): when set to low level (V
set to high level (V
converter goes on sampling. When OEB is set to a low level again, the data arrives on the
output with a very short T

Figure 11 on page 10 summarizes this functionality.

DFSB OEB OR DR Most significant bit (MSB)

HLHCLKD13

L L H CLK D13 complemented

HLHCLKD13

L L H CLK D13 complemented

HLLCLKD13

L L L CLK D13 complemented

(1)

IH

), all digital outputs remain active. When

), all digital output buffers are in a high impedance state while the

IH

delay. This feature enables the chip select of the device.

on

IL

HZ (all digital outputs are in high

HZ

impedance)

), DFSB provides standard binary

Reference mode control (REFMODE): this allows the internal or external settings of the
voltage references VREFP and INCM. REFMODE = 0 for internal references,
REFMODE = 1 for external references (and disables both references VREFP and INCM).

3.5.2 Digital outputs

Out of range (OR): this function is implemented on the output stage in order to set an "out-

of-range" flag whenever the digital data is over the full-scale range. Typically, there is a
detection of all data at ‘0’ or all data at ‘1’. It sets an output signal OR, which is in a low level
state (V
data is out of range.

Data ready (DR): the Data Ready output is an image of the clock being synchronized on the
output data (D0 to D13). This is a very helpful signal that simplifies the synchronization of
the measurement equipment of the controlling DSP. Like all other digital outputs, DR goes
into high impedance when OEB is set to a high level, as shown in Figure 11 on page 10.

) when the data stays within the range, or in a high-level state (VOH) when the

OL

Doc ID 13317 Rev 7 31/39

User manual RHF1401

3.5.3 Digital output load considerations

The features of the internal output buffers limit the maximum load on the digital data output.
In particular, the shape and amplitude of the Data Ready signal, toggling at the clock
frequency, can be weakened by a higher equivalent load.

In applications that impose higher load conditions, it is recommended to use the falling edge
of the master clock instead of the Data Ready signal. This is possible because the output
transitions are internally synchronized with the falling edge of the clock.

Figure 62. Output buffer fall time Figure 63. Output buffer rise time

25

25

20

15

10

Fall time (nS)

5

0

0 1020304050

VCCBE=2.5V

VCCBE=3.3V

load capacitor (pF)

3.6 PCB layout precautions

● The use of dedicated analog and digital ground planes on the PCB is recommended for

high-speed circuit applications to provide low parasitic inductance and resistance.
AGND is connected to the analog ground plane and DGND, GNDBI, GNDBE are
connected to the digital ground plane.

● To minimize the transition current when the output changes, the capacitive load at the

digital outputs must be reduced as much as possible by using the shortest-possible
routing tracks. One way to reduce the capacitive load is to remove the ground plane
under the output digital pins and layers at high sampling frequencies.

● The separation of the analog signal from the clock signal and digital outputs is

mandatory to prevent noise from coupling onto the input signal.

● Power supply bypass capacitors must be placed as close as possible to the IC pins to

improve high-frequency bypassing and reduce harmonic distortion.

● All leads must be as short as possible, especially for the analog input, so as to

decrease parasitic capacitance and inductance.

● Choose the smallest-possible component sizes (SMD).

20

15

10

Rise time (nS)

5

0

0 1020304050

VCCBE=2.5V

VCCBE=3.3V

load capacitor (pF)

32/39 Doc ID 13317 Rev 7

RHF1401 Definitions of specified parameters

4 Definitions of specified parameters

4.1 Static parameters

Differential non-linearity (DNL)

The average deviation of any output code width from the ideal code width of 1 LSB.

Integral non-linearity (INL)

An ideal converter exhibits a transfer function that is a straight line from the starting code to
the ending code. The INL is the deviation from this ideal line for each transition.

4.2 Dynamic parameters

Spurious free dynamic range (SFDR)

The ratio between the power of the worst spurious signal (not always a harmonic) and the
amplitude of the fundamental tone (signal power) over the full Nyquist band.
Expressed in dBc.

Total harmonic distortion (THD)

The ratio of the rms sum of the first five harmonic distortion components to the rms value of
the fundamental line. Expressed in dB.

Signal to noise ratio (SNR)

The ratio of the rms value of the fundamental component to the rms sum of all other spectral
components in the Nyquist band (F
harmonics. Reported in dB.

/2) excluding DC, fundamental and the first five

s

Signal-to-noise and distortion ratio (SINAD)

A similar ratio to the SNR but that includes the harmonic distortion components in the noise
figure (not the DC signal). Expressed in dB. From SINAD, the effective number of bits
(ENOB) can easily be deduced using the formula:

SINAD = 6.02

When the analog input signal is not full-scale (FS) but has an A
expression becomes:

SINAD = 6.02

×

ENOB + 1.76 dB

×

ENOB + 1.76 dB + 20 log (A0 / FS)

amplitude, the SINAD

0

Analog input bandwidth

The maximum analog input frequency at which the spectral response of a full power signal
is reduced by 3 dB. Higher values can be achieved with smaller input levels.

Pipeline delay

The delay between the initial sample of the analog input and the availability of the
corresponding digital data output on the output bus. Also called data latency. Expressed as
a number of clock cycles.

Doc ID 13317 Rev 7 33/39

Package information RHF1401

5 Package information

In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK

®

packages, depending on their level of environmental compliance. ECOPACK®

®

is an ST trademark.

34/39 Doc ID 13317 Rev 7

RHF1401 Package information

Figure 64. Ceramic SO-48 package mechanical drawing

Note: The upper metallic lid is not electrically connected to any pins, nor to the IC die inside the

package. Connecting unused pins or metal lid to ground or to the power supply will not affect
the electrical characteristics.

Table 14. Ceramic SO-48 package mechanical data

Dimensions

Ref.

Min. Typ. Max. Min. Typ. Max.

A 2.18 2.47 2.72 0.086 0.097 0.107

b 0.20 0.254 0.30 0.008 0.010 0.012

c 0.12 0.15 0.18 0.005 0.006 0.007

D 15.57 15.75 15.92 0.613 0.620 0.627

E 9.52 9.65 9.78 0.375 0.380 0.385

E1 10.90 0.429

E2 6.22 6.35 6.48 0.245 0.250 0.255

E3 1.52 1.65 1.78 0.060 0.065 0.070

e 0.635 0.025

f 0.20 0.008

L 12.28 12.58 12.88 0.483 0.495 0.507

P 1.30 1.45 1.60 0.051 0.057 0.063

Q 0.66 0.79 0.92 0.026 0.031 0.036

S1 0.25 0.43 0.61 0.010 0.017 0.024

Millimeters Inches

Doc ID 13317 Rev 7 35/39

Ordering information RHF1401

6 Ordering information

Table 15. Order codes

Order code Quality level Temp range Package Marking Packing

RHF1401KSO1 Engineering model

RHF1401KSO-01V QMLV-Flight 5962F0626001VXC

-55 °C to
+125 °C

SO-48

RHF1401KSO1

Strip pack

Note: Contact your local ST sales office for information regarding the specific conditions for

products in die form and QML-Q versions.

36/39 Doc ID 13317 Rev 7

RHF1401 Revision history

7 Revision history

Table 16. Document revision history

Date Revision Changes

First public release.
Failure immune and latchup immune value increased to

29-Jun-2007 1

29-Oct-2007 2

09-Nov-2009 3

120 MeV-cm2/mg.
Updated package mechanical information.
Removed reference to non rad-hard components from External

references, common mode: on page 16.

Updated Figure 1: RHF1401 block diagram.
Added explanation on Figure 3: Timing diagram.
Added introduction to Section 6: Typical performance characteristics.
Updated Section 7.2: Clock signal requirements and Section 7.3:

Power consumption optimization.

Added Section 7.4: Low sampling rate recommendations.
Updated information on Data Ready signal in Section 7.5: Digital

inputs/outputs.

Added Figure 24: Impact of clock frequency on RHF1401

performance and Figure 25: CLK signal derivation.

Changed input clock features in Ta bl e 1 0.
Modified Ta b le 1 4 .
Added Figure 62 to Figure 42.

26-Feb-2010 4

13-Sep-2010 5

Modified Figure 1: RHF1401 block diagram.
Added details for Tdr and changed values for Tpd in Table 5: Timing

characteristics.

Modified Figure 11: Timing diagram.
Changed values for VREFP in Ta bl e 4 .
Changed Vin operating conditions in Ta b le 4 , Figure 42 and

Figure 55.

Changed values for DNL in Ta bl e 9 .

Modified Figure 1 on page 4 and Figure 9 on page 8.
Added note 2. on page 10.
Modified C

typ value in Table 6: Analog inputs as per Figure 3.

IN

Modified Figure 11: Timing diagram.
Replaced Figure 18.
Added Table 12: Output codes for DFSB = 1.
Modified Figure53: 2V

differential input.

pp

Doc ID 13317 Rev 7 37/39

Revision history RHF1401

Table 16. Document revision history

Date Revision Changes

29-Jul-2011 6

06-Apr-2012 7

Added Note: on page 31 and in the "Pin connections" diagram on the
cover page.

Added Table 1: Device summary on cover page.
Updated curves in Section 2.3: Electrical characteristics (after

300 kRad).

Modified Section 3.1: Optimizing the power consumption.
Modified Section 3.2: Driving the analog input.
Modified Section 3.3.1: Internal references.
Modified Section 3.3.2: External references.
Modified Section 3.6: PCB layout precautions.

38/39 Doc ID 13317 Rev 7

RHF1401

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Doc ID 13317 Rev 7 39/39