ST RHF1401 User Manual

RHF1401

Rad-hard 14-bit 30 Msps A/D converter

Datasheet − production data

Features

■ Qml-V qualified, smd 5962-06260

■ Rad hard: 300 kRad(Si) TID

■ Failure immune (SEFI) and latch-up immune

(SEL) up to 120 MeV-cm

2

/mg at 2.7 V and

125° C

■ Hermetic package

■ Tested at F

■ Low power: 85 mW at 20 Msps

■ Optimized for 2 Vpp differential input

■ High linearity and dynamic performances

■ 2.5 V/3.3 V compatible digital I/O

■ Internal reference voltage with external

=20Msps

s

reference option

Applications

■ Digital communication satellites

■ Space data acquisition systems

■ Aerospace instrumentation

■ Nuclear and high-energy physics

Description

The RHF1401 is a 14-bit analog-to-digital
converter that uses pure (ELDRS-free) CMOS

0.25 µm technology combining high performance,
radiation robustness and very low power
consumption.

Table 1. Device summary

Ceramic SO-48 package

The upper metallic lid is not electrically connected to any

pins, nor to the IC die inside the package.

The RHF1401 is based on a pipeline structure
and digital error correction to provide excellent
static linearity. Specifically designed to optimize
power consumption, the device only dissipates
85 mW at 20 Msps, while maintaining a high level
of performance. The device also integrates a
proprietary track-and-hold structure to ensure a
large effective resolution bandwidth.

Voltage references are integrated in the circuit to
simplify the design and minimize external
components. A tri-state capability is available on
the outputs to allow common bus sharing. A data­ready signal, which is raised when the data is
valid on the output, can be used for
synchronization purposes.

The RHF1401 has an operating temperature
range of -55° C to +125° C and is available in a
small 48-pin ceramic SO-48 package.

Order code SMD pin

RHF1401KSO1 -

RHF1401KSO-01V 5962F0626001VXC QMLV-Flight

April 2012 Doc ID 13317 Rev 7 1/39

This is information on a product in full production.

Quality

level

Engineering

model

Package

SO-48 Gold 1.1 g - -55 °C to +125 °C

Lead

finish

Mass EPPL Temp range

www.st.com

39

Contents RHF1401

Contents

1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.2 Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.3 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.4 Equivalent circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.1 Absolute maximum ratings and operating conditions . . . . . . . . . . . . . . . . . 9

2.2 Timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.3 Electrical characteristics (after 300 kRad) . . . . . . . . . . . . . . . . . . . . . . . . 11

2.4 Results for differential input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.5 Results for single ended input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3 User manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.1 Optimizing the power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.2 Driving the analog input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3.3 Reference connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

3.3.1 Internal references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

3.3.2 External references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

3.4 Clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

3.5 Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

3.5.1 Digital inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

3.5.2 Digital outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

3.5.3 Digital output load considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

3.6 PCB layout precautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

4 Definitions of specified parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

4.1 Static parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

4.2 Dynamic parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

2/39 Doc ID 13317 Rev 7

RHF1401 Contents

5 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

6 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Doc ID 13317 Rev 7 3/39

Description RHF1401

1 Description

1.1 Block diagram

Figure 1. RHF1401 block diagram

VREFP

REFMODE

VIN

INCM

VINB

stage

1

stage

2

stage

n

INCM

Reference

circuits

GNDA

IPOL

VREFM
DFSB

CLK

Timing

GND

Sequencer-phase shifting

Digital data correction

Buffers

VCCBI

OEB

DR

D0

D13

OR

VCCBE

AM04556

4/39 Doc ID 13317 Rev 7

RHF1401 Description

1.2 Pin connections

Figure 2. pin connections (top view)

GNDBI

GNDBE

VCCBE

NC
NC
OR

(MSB)D13

D12
D11
D10

D9
D8
D7
D6
D5
D4
D3
D2
D1

(LSB)D0

DR

VCCBE

GNDBE

VCCBI

10

10
11

11
12

12
13

13
14

14
15

15
16

16
17

17
18

18
19

19
20

20
21

21
22

22
23

23
24

24

1

1
2

2
3

3
4

4
5

5
6

6
7

7
8

8
9

9

48

48

DGND

47

47

DGND

46

46

CLK

45

45

DGND

44

44

DVCC

43

43

DVCC

42

42

AVCC

41

41

AVCC

40

40

AGND

39

39

INCM
AGND

38

38

VINB

37

37

AGND

36

36

VIN

35

35

AGND

34

34

VREFM

33

33

VREFP

32

32

IPOL

31

31

AGND

30

30

AVCC

29

29

AVCC

28

28

DFSB

27

27

OEB

26

26

REFMODE

25

25

Doc ID 13317 Rev 7 5/39

Description RHF1401

1.3 Pin descriptions

Table 2. Pin descriptions

Pin Name Description Observations Pin Name Description Observations

1 GNDBI Digital buffer ground 0 V 25 REFMODE Ref. mode control input

2 GNDBE Digital buffer ground 0 V 26 OEB Output enable input

3VCCBE

4NC

5NC

6 OR Out of range output

7 D13(MSB)

8 D12 Digital output

9 D11 Digital output

10 D10 Digital output

11 D9 Digital output

12 D8 Digital output

13 D7 Digital output

14 D6 Digital output

15 D5 Digital output

16 D4 Digital output

17 D3 Digital output

18 D2 Digital output

19 D1 Digital output

20 D0(LSB) Digital output LSB

21 DR Data ready output

22 VCCBE

23 GNDBE Digital buffer ground 0 V 47 DGND Digital ground 0 V

24 VCCBI

Digital buffer power
supply

Most significant bit
output

Digital buffer power
supply

Digital buffer power
supply

2.5 V/3.3 V 27 DFSB Data format select input

Not connected to the
dice

Not connected to the
dice

CMOS output
(2.5 V/3.3 V)

CMOS output
(2.5 V/3.3 V)

CMOS output
(2.5 V/3.3 V)

CMOS output
(2.5 V/3.3 V)

CMOS output
(2.5 V/3.3 V)

CMOS output
(2.5 V/3.3 V)

CMOS output
(2.5 V/3.3 V)

CMOS output
(2.5 V/3.3 V)

CMOS output
(2.5 V/3.3 V)

CMOS output
(2.5 V/3.3 V)

CMOS output
(2.5 V/3.3 V)

CMOS output
(2.5V /3.3 V)

CMOS output
(2.5 V/3.3 V)

CMOS output
(2.5 V/3.3 V)

CMOS output
(2.5 V/3.3 V)

CMOS output

(1)

(2.5 V/3.3 V)

2.5 V/3.3 V 46 CLK Clock input

2.5 V 48 DGND Digital ground 0 V

28 AVCC Analog power supply 2.5 V

29 AVCC Analog power supply 2.5 V

30 AGND Analog ground 0 V

31 IPOL Analog bias current input

32 VREFP Top voltage reference

33 VREFM Bottom voltage reference 0 V

34 AGND Analog ground 0 V

35 VIN Analog input 1 V

36 AGND Analog ground 0 V

37 VINB Inverted analog input 1 V

38 AGND Analog ground 0 V

39 INCM Input common mode

40 AGND Analog ground 0 V

41 AVCC Analog power supply 2.5 V

42 AVCC Analog power supply 2.5 V

43 DVCC Digital power supply 2.5 V

44 DVCC Digital power supply 2.5 V

45 DGND Digital ground 0 V

1. See load considerations in Chapter 2.2: Timing characteristics.

2.5 V/3.3 V CMOS
input

2.5 V/3.3 V CMOS
input

2.5 V/3.3 V CMOS
input

Can be external or
internal

pp

pp

Can be external or
internal

2.5 V compatible
CMOS input

6/39 Doc ID 13317 Rev 7

RHF1401 Description

1.4 Equivalent circuits

Figure 3. Analog inputs Figure 4. Output buffers

AVCC

VIN or VINB

7 pF

(pad)

OEB

AGND

Data

AVCC

AGND

AM04557

Figure 5. Clock input Figure 6. Data format input

VCCBE

CLK

DVCC

DFSB

VCCBE

GNDBE

D0 …D13

7 pF

(pad)

AM04558

7 pF

(pad)

DGND

AM04559

7 pF

(pad)

GNDBE

Figure 7. Reference mode control input Figure 8. Output enable input

REFMODE

7 pF

(pad)

VCCBE

GNDBE

AM04561

OEB

7 pF

(pad)

VCCBE

GNDBE

AM04560

AM04562

Doc ID 13317 Rev 7 7/39

Description RHF1401

Figure 9. VREFP and INCM input

AVCC

AVCC

VREFP

7 pF

(pad)

AGND

Figure 10. VREFM input

INCM

7 pF

REFMODE REFMODE

High input impedance

VREFM

7 pF

(pad)

(pad)

AGND

AVCC

AGND

AM04564

AM04563

8/39 Doc ID 13317 Rev 7

RHF1401 Electrical characteristics

2 Electrical characteristics

2.1 Absolute maximum ratings and operating conditions

Table 3. Absolute maximum ratings

Symbol Parameter Values Unit

AV

CC

DV

CC

V

CCBI

V

CCBE

V

IN

V

INB

V

REFP

V

INCM

I

Dout

T

stg

R

thjc

R

thja

ESD HBM (human body model)

1. Human body model: a 100 pF capacitor is charged to the specified voltage, then discharged through a

1.5 kΩ resistor between two pins of the device. This is done for all couples of connected pin combinations
while the other pins are floating.

Analog supply voltage 3.3 V

Digital supply voltage 3.3 V

Digital buffer supply voltage 3.3 V

Digital buffer supply voltage 3.6 V

Analog inputs: bottom limit −> top limit -0.6 V −> AVCC+0.6 V V

External references: bottom limit −> top limit -0.6 V −> AVCC+0.6 V V

Digital output current -100 to 100 mA

Storage temperature -65 to +150 °C

Thermal resistance junction to case 22 °C/W

Thermal resistance junction to ambient 125 °C/W

(1)

2kV

Table 4. Operating conditions

Symbol Parameter Min Typ Max Unit

AV

CC

DV

CC

V

CCBI

V

CCBE

V

REFP

V

REFM

V

INCM

V

IN

V

INB

DFSB

OEB

1. See Figure 25. for differential input and Figure 42. to Figure 49. for single-ended.

Analog supply voltage 2.3 2.5 2.7 V

Digital supply voltage 2.3 2.5 2.7 V

Digital internal buffer supply 2.3 2.5 2.7 V

Digital output buffer supply 2.3 2.5 3.4 V

Forced top voltage reference 0.8 1 1.4 V

Bottom external reference voltage 0 0 0.5 V

Forced common mode voltage 0.2 0.5 1.1 V

Max. voltage versus GND 1 1.6

(1)

Min. voltage versus GND -0.2 GND V

Digital inputs 0 V

CCBE

V

VREFMODE

Doc ID 13317 Rev 7 9/39

Electrical characteristics RHF1401

2.2 Timing characteristics

Table 5. Timing characteristics

Symbol Parameter Test conditions Min Typ Max Unit

DC Clock duty cycle

T

T

T

T

T

T

Data output delay (fall of

od

clock to data valid)

Data pipeline delay

pd

Falling edge of OEB to

on

digital output valid data

Rising edge of OEB to

off

digital output tri-state

Data rising time 10 pF load capacitance 6 ns

rD

Data falling time 10 pF load capacitance 3 ns

fD

(1)

(2)

F

= 20 Msps 45 50 65 %

s

10 pF load capacitance 5 7.5 13 ns

Duty cycle = 50% 7.5 7.5 7.5 cycles

1. As per Figure 11.

2. If the duty cycle does not equal 50%: Tpd = 7 cycles + CLK pulse width.

Figure 11. Timing diagram

N+6

N+5

N+4

Analog
input

N-2

N-1

N

N+1

N+3

N+2

1ns

1ns

N+7

N+8

CLK

Tpd+ Tod

Tod

OEB

Data
output

DR

OR

Tod

N-8 N-7 N-6 NN-5 N -4 N+1N-3 N-1

The input signal is sampled on the rising edge of the clock while the digital outputs are
synchronized on the falling edge of the clock. The duty cycles on DR and CLK are the same.

The rising and falling edges of the OR pin are synchronized with the falling edge of the DR
pin.

10/39 Doc ID 13317 Rev 7

Toff Ton

HZ state

AM06120

RHF1401 Electrical characteristics

2.3 Electrical characteristics (after 300 kRad)

Unless otherwise specified, the test conditions in the following tables are:
AVCC = DVCC = VCCBI =VCCBE = 2.5 V, F
VREFP = 1V, INCM = 0.5V, VREFM = 0 V, T

Table 6. Analog inputs

Symbol Parameter Test conditions Min Typ Max Unit

=20 Msps, FIN= 15 MHz, V

s

= 25°C.

amb

at -1 dBFS,

IN

V

IN-VINB

C

Z

Full-scale reference voltage

(1)

(FS)

Input capacitance 7 pF

IN

Input impedance Fs = 20 Msps 3.3 kΩ

IN

ERB Effective resolution bandwidth

1. See Chapter 4: Definitions of specified parameters on page 33 for more information.

Table 7. Internal reference voltage

VREFP = 1 V
(forced)
VREFM = 0 V

(1)

2V

70 MHz

Symbol Parameter Test conditions Min Typ Max Unit

REFMODE = 0
internal reference

R

Output resistance of internal

out

reference

on

REFMODE = 1
internal reference

30 Ω

7.5 kΩ

off

V

REFP

V

INCM

1. V

REFM

Table 8. External reference voltage

Top internal reference voltage

Input common mode voltage REFMODE = 0 0.40 0.44 0.50 V

connected to GND.

(1)

REFMODE = 0 0.76 0.84 0.95 V

(1)

pp

Symbol Parameter Test conditions Min Typ Max Unit

V

REFP

V

REFM

V

INCM

1. See Figure 59.& Figure 60

Table 9. Static accuracy

Forced top reference voltage REFMODE = 1 0.8 1.4 V

Forced bottom ref voltage REFMODE = 1 0 0.5 V

Forced common mode voltage REFMODE = 1 0.2 1.1 V

Symbol Parameter Test conditions Min Typ Max Unit

(2)

(1)

Fin= 1.5 Msps

±0.4 LSB
Vin at -1 dBFS
Fs=1.5 Msps

±3 LSB

Guaranteed

DNL Differential non-linearity

INL Integral non-linearity

Monotonicity and no missing
codes

1. See Figure 33 and Chapter 4 for more information. This parameter is not tested.

2. See Figure 34 and Chapter 4 for more information. This parameter is not tested.

Doc ID 13317 Rev 7 11/39

Electrical characteristics RHF1401

Table 10. Digital inputs and outputs

Symbol Parameter Test conditions Min Typ Max Unit

Clock input

CT Clock threshold DV

CA

Square clock amplitude
(DC component = 1.25 V)

= 2.5 V 1.25 V

CC

DV

= 2.5 V 0.8 2.5 Vpp

CC

Digital inputs

V

IL

V

IH

Logic "0" voltage V

Logic "1" voltage V

= 2.5 V 0

CCBE

= 2.5 V

CCBE

0.75 x
V

CCBE

0.25 x

V

CCBE

V

CCBE

Digital outputs

V

OL

V

OH

I

OZ

C

L

Table 11. Dynamic characteristics

Logic "0" voltage I

= -10 µA 0 0.25 V

OL

Logic "1" voltage IOH = 10 µA

High impedance leakage
current

Output load capacitance

OEB set to V

High CLK
frequencies

V

CCBE

-0.25

IH

-15 15 µA

15 pF

Symbol Parameter Test conditions Min Typ Max Unit

SFDR Spurious free dynamic range

SNR Signal to noise ratio 66 70 dB

THD Total harmonic distortion 70 86 dB

SINAD

Signal to noise and distortion
ratio

F

= 15 MHz

in

= 20 Msps

F

s

V

at -1 dBFS

in

internal references

= 6 pF

C

L

70 91 dBFS

65 70 dB

ENOB Effective number of bits 10.6 11.5 bits

V

V

V

Higher values of SNR, SINAD and ENOB can be obtained by increasing the full-scale range
of the analog input if the sampling frequency allows it.

12/39 Doc ID 13317 Rev 7