ST PSQ001V1 User Manual
Power management for CPU, FPGA and memory
Features
■ Input: 5 - 36 VDC, surge protection
■ Output voltages:
– Output1 (V
1.2, 1.5, 1.8 or 2.5 V, 4 A continuously (6 A
peak), tolerance: 3%
–Output2 (V
1.8, 2.5 V or 3.3 V, 2 A continuously
(3 A peak), tolerance: 3%
– Output3 V
tolerance: 4%
– Output3 V
■ Analog 5: 5 V, 0.8 A, tolerance: 4%
■ Analog 3.3 V: 3.3 V, 0.15 A, tolerance: 2%
) selectable from: 0.9, 1.0,
core
) selectable from: 1.0, 1.2, 1.5,
i/o
: 3.3 V 0.4 A (0.8 A peak),
sys
: 2.5 V, 0.4 A, tolerance: 2%
aux
STEVAL-PSQ001V1
based on the PM6680A
Data Brief
STEVAL-PSQ001V1
Description
The main purpose of this evaluation board is to
show basic principles used for design of the power
supply and to give users a working prototype for
testing and daily use. The trend in recent years in
the supply of MCUs, CPUs, memories, FPGAs
etc. is to reduce the supply voltage, increase
supply current and provide various voltage levels
for different devices in one platform. A typical
example of this is the FPGA. FPGAs contain core
parts which operate with low level voltage,
interface parts placed between the core and the
output, system parts, etc. It is important to note
that each family of parts has a slightly different
voltage level and the trend is toward decreasing
voltage for each new family. The lowest operating
voltage currently is 1 V, and this can be expected
to drop to 0.9 V or 0.8 V in the near future. The
situation is similar with other parts of digital
solutions. Typically, the main CPU, memory, and
interfaces require different supply voltage levels.
Low operating voltage also bring another
challenge - transient. Digital devices are typically
sensitive to voltage level. If voltage drops below or
crosses over established limits, the device is
reset. This limit is typically ± 3 or 5 %. On the
other hand, digital device consumption can
change very fast (approx. several amps in several
hundred nanoseconds). The power supply must
be capable of reacting very quickly with a
minimum of over/under voltage, especially in
cases where very low voltage output is required.
There is additional stress placed on power
supplies in digital applications for industrial use.
The industrial standard bus is 24 V, but this
voltage fluctuates and the maximum required
input voltage level can be up to 36 V. Additional
surge protection is also mandatory for power
supply input in industrial applications. The
purpose of this evaluation board is to address all
of required parameters outlined above. This
means satisfying industrial input requirements
(operating voltage of up to 36 V) and generating
several output voltages for middle power
applications (up to several amps). The main
output voltage level can be set easily.
February 2008 Rev 1 1/4
For further information contact your local STMicroelectronics sales office.
www.st.com
4
Circuit schematic STEVAL-PSQ001V1
J16
Input
C9
220p
C10
22n
R5
10k
3R3
FB2R
Q2
STS7NF60L
V5V
R32
10k
Vin
Q3
STS7NF60L
VLDO
Vin
R29
100k
VLDO
R2
10R
S19
3.3V/150mA
D11
STPS2L40
D9
STPS2L40
D6A
STPS1L40M
SHDN
GND
2
BYPASS
3
OUT
4
IN
5
U2
LK112_33
R20
300R
C26
560pF
R209
110k
SMAJ33A
FB2R
D10
4V7
Vin
VLDO
Vsys
R330R0R
D8
STPS2L40
Vin
R2
4
10R
R208
6k8
Vin
R1
9
1k2
R1
0
1k2
Vcc
8
COMP
D
7
H
3
FB
OUT
U1
L5970AD
S20
GND Analog
L4
3.3uH/6A
L3
4.7uH/3A
C29
330u/6.3V
Vaux
C28
330u/6.3V
S5
C22
330u/6.3V
S9
1V
S21
Vsys 3.3V/400mA
VLDO
L1
15uH/1.5A
HGATE2
10
PHASE2
11
LGATE2
13
CSENSE2
12
V5SW
17
OUT2
8
COMP2
PGOOD2
27
FB2
7
SHDN
25
2
4
F
32
IP
24
FSELL
3
C
6
HGATE1
22
PHASE1
21
LGATE1
15
CSENSE1
20
PGND
14
OUT1
29
COMP1
30
PGOOD1
26
FB1
28
SGND1
SGND2
16
BOOT1
23
BOOT2
9
O5
18
31
19
U5
PM6680
S6
L
5
10uH/1A
SKIP mode
0.9V
R205
7k5
S22
Vaux 2.5V/400mA
S7
240k
S23
GND
C30
100n
C35
100n
R3
9
10R
R4
0
10R
R3
0
0R
R3
20k
S24
A
Vcore 0.9 - 2.5V/4A
D4
STPS2L40
R35
51k
R206
110k
R2
120k
S14
1.2V
R10
2
2k
R3
7
47R
S25
S15
1.5V
R4
5k6
R36
51k
C32
1n
S17
2.5V
PGOOD2
S13
1V
S16
1.8V
S26
R10
1
1k
C5
47uF/10V
C33
1n
S27
S28
Vcore GND
C31
220n
FB2
R11
300R
R3
10k
S1
Vanalog EN
S29
R3
10k
C27
100pF
D3
36V
S30
C36
100pF
PGOOD2
R2
1
10R
S31
100n
C20
560pF
S32
Vin
VLDO
S33
GND io
S2
Vsys EN
C21
100pF
10u/6V
Vaux
C15
470n
D5
36V
S34
Vio 0.9 - 2.5V/2A
7
6
2
1
3
4
5
Q1
STS4DNF60
R26
10R
R207
2k2
C2
4.7u/35V
C14
4.7u/10V
C18
10u/50V
D7
BAW56/SOT
C23
10u/50V
C24
10u/50V
Vin
R20
1
1k
C8
4.7u/35V
VIN
VOUT
D
3
D
2
INH
U4
KF25_SOIC8
C1
47uF/50V
C17
100n
R20
2k
S18
5V/400mA
J1
4
Reset
R20
3
3k
D4A
STPS1L40M
R20
3k
C34
100n
C25
100n
S4
CH1 EN/SUS
C19
100n
R41
5k6
C16
3.3u/35V
R2
2
10R
S3
CH2 EN/SUS
R25
10R
R105
7k5
R106
110k
Vcc1
6
Vcc2
MR
3
RSTIN
RST
1
STM6719TEWB6F
R108
820k
S10
1.2V
FB1
S12
1.8V
S11
1.5V
R107
9k1
R10
3
3k
R10
3k
J1
Reset GND
C3
220p
R2
7
10R
C4
22n
R42
5k6
Vcc
8
COMP
4
D
7
H
3
FB
OUT
1
U
3
L5970AD
L
2
15uH/1.5A
VLDO
D6
STPS2L40
18k
10k
C11
100u/6V
4k7
R3
8
10R
C12
100n
R2
8
10k
C13
10u/4V
1 Circuit schematic
Figure 1. Schematic
S28
S29
S30
300R
560pF
VLDO
26
PGOOD1
PGOOD2
27
PGOOD2
VLDO
560pF
300R
S31
FB2R
FB2
1
28
FB1
SGND1
FB2
7
FB1
Vcore GND
2k2
R208
6k8
R207
C27
100pF
R33
VLDO
16
NNC
6
FSE
SGND2
S7
3
SKSKIP
S6
24
VVRREEF
S5
32
EN1
25
EENN2
4
SHDN
5
PM6680
U5
0R
0
R3
VLDO
Vin
R29
100k
100pF
C21
R108
820k
9k1
R107
3
S32
2
1
S3
CH2 EN/SUS
GND io
S33
SKIP mode
1
S4
2
3
1 10k
R3
C36
D10
CH1 EN/SUS
R36
R35
410k
R3
100pF
4V7
C30
100n
51k
51k
Reset
4
VLDO
Vsys EN
5k6
U6U6STM6719TEWB6F
J1
R209
1
RST
Vcc2
Vcc1
4
6
Vaux
R9R93R3
Vin
VLDO
S18
S19
S20
GND
10uH/1A
5
L
GND Analog
Vin
S1
R41
D1D1SMAJ33A
Vanalog EN
5k6
L5970AD
3
U
S21
Vsys
15uH/1.5A
2
L
1
8
5V/400mA
3.3V/150mA
V5V
C7C710u/6V
4
OUT
LK112_33
SHDN
BYPASS
IN
U2
1
2
3
5
C6C6100n
47uF/10V
C5
R3
20k
R4
5k6
2/4
15uH/1.5A
L5970AD
U1
Vin
J16
R2
120k
STPS1L40M
D4A
L1
D4
STPS2L40
1
5
IINNH
FB
3
OUT
GNGND
7
VREF
6
SYSYNC
2
Vcc
COMP
8
4
R1R14k7
C4
22n
C3
220p
C2
4.7u/35V
D3
36V
C1
47uF/50V
2
1
Input
S22
Vsys 3.3V/400mA
Vaux
1
VOUT
VIN
U4
KF25_SOIC8
5
8
R7R7240k
R6R618k
5
FB
OUT
Vcc
COMP
4
R5
Vaux 2.5V/400mA
C13
10u/4V
GNGND
7
GNGND
6
GNGND
3
GNGND
2
INH
C12
100n
C11
100u/6V
R8R810k
D6A
STPS1L40M
D6
STPS2L40
IINNH
3
GNGND
7
VREF
6
SYSYNC
2
10k
C10
22n
C9
220p
C8
4.7u/35V
D5
36V
S23
GND
Vin
S2
R42
5 Reset GND
J1
110k
Vss
2
MR
RSTIN
3
5
1n
C33
1n
C32
FB2R
C17
100n
BAW56/SOT
C16
3.3u/35V
C15
470n
47R
7
R3
C14
4.7u/10V
S25
S24
S26
S27
Vcore 0.9 - 2.5V/4
S13
1V
1k
1
STPS2L40
R26
10R
R25
10R
C19
Q1
19
18
31
C25
100n
6
C24
C23
Q2
100n
23
BOOT1
BOOT2
9
5
C18
10u/50V
10u/50V
STS7NF60L
Vin
Vcc
10u/50V
S14
S15
S16
S17
10R
1
R2
21
22
PHASE1
HGATE1
LDO5
PHASE2
HGATE2
10
11
3 10R
R2
4
3
8
4.7uH/3A
L3
Vio 0.9 - 2.5V/2A
S34
S35
1.2V
1.5V
1.8V
2.5V
C34
L4
3.3uH/6A
15
LGATE1
LGATE2
13
7
C35
S12
S11
S10
S9
S8S80.9V
C29
10R
2
R2
1k2
9
R1
20
12
1k2
0
R1
10R
4
R2
2
D8
1.8V
1.5V
1.2V
1V
330u/6.3V
10R
7
R2
D9
STPS2L40
Q3
14
CSENSE1
CSENSE2
17
1
10R
0
STPS2L40
R4
R20
22k
R20
3k
3
R20
43k
R20
R205
R206
C28
10R
8
100n
R3
STS7NF60L
29
PGND
V5SW
8
STS4DNF60
10R
9
100n
R3
R106
110k
R105
7k5
43k
R10
3k
3
R10
2k
2
R10
1k
1
R10
7k5
110k
330u/6.3V
OUT1
OUT2
30
2
C22
R20
C26
10k
R32
COMP1
COMP2
10k
8
R2
C20
R11
330u/6.3V
D11
PGOOD2
Vin
D7
C31
220n
Vin
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