ST PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 User Manual

PSD813F3V-12J

PSD813F2, PSD833F2

PSD834F2, PSD853F2, PSD854F2

Flash In-System Programmable (ISP)

Peripherals for 8-bit MCUs, 5V

FEATURES SUMMARY

■FLASH IN-SYSTEM PROGRAMMABLE (ISP) PERIPHERAL FOR 8-BIT MCUS

■DUAL BANK FLASH MEMORIES

–UP TO 2 Mbit OF PRIMARY FLASH MEMORY (8 Uniform Sectors, 32K x8)

–UP TO 256 Kbit SECONDARY FLASH MEMORY (4 Uniform Sectors)

–Concurrent operation: READ from one memory while erasing and writing the other

■UP TO 256 Kbit BATTERY-BACKED SRAM

■27 RECONFIGURABLE I/O PORTS

■ENHANCED JTAG SERIAL PORT

■PLD WITH MACROCELLS

–Over 3000 Gates of PLD: CPLD and DPLD

–CPLD with 16 Output Macrocells (OMCs) and 24 Input Macrocells (IMCs)

–DPLD - user defined internal chip select decoding

■27 INDIVIDUALLY CONFIGURABLE I/O PORT PINS

The can be used for the following functions:

–MCU I/Os

–PLD I/Os

–Latched MCU address output

–Special function I/Os.

–16 of the I/O ports may be configured as open-drain outputs.

■IN-SYSTEM PROGRAMMING (ISP) WITH JTAG

–Built-in JTAG compliant serial port allows full-chip In-System Programmability

–Efficient manufacturing allow easy product testing and programming

–Use low cost FlashLINK cable with PC

■PAGE REGISTER

–Internal page register that can be used to expand the microcontroller address space by a factor of 256

■PROGRAMMABLE POWER MANAGEMENT

PRELIMINARY DATA

Figure 1. Packages

PQFP52 (M)

PLCC52 (J)

TQFP64 (U)

■HIGH ENDURANCE:

–100,000 Erase/WRITE Cycles of Flash Memory

–1,000 Erase/WRITE Cycles of PLD

–15 Year Data Retention

■5V±10% SINGLE SUPPLY VOLTAGE

■STANDBY CURRENT AS LOW AS 50µA

June 2004

1/110

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

TABLE OF CONTENTS

FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

PSD ARCHITECTURAL OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Page Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

PLDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

MCU Bus Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

JTAG Port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

In-System Programming (ISP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Power Management Unit (PMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

DEVELOPMENT SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

PSD Register Description and Address Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

DETAILED OPERATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Memory Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Primary Flash Memory and Secondary Flash memory Description . . . . . . . . . . . . . . . . . . . . . 20 Memory Block Select Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Power-up Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Read Memory Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Read Primary Flash Identifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Read Memory Sector Protection Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Reading the Erase/Program Status Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Data Polling Flag (DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Toggle Flag (DQ6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Error Flag (DQ5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Erase Time-out Flag (DQ3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

PROGRAMMING FLASH MEMORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Data Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Data Toggle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Unlock Bypass (PSD833F2x, PSD834F2x, PSD853F2x, PSD854F2x) . . . . . . . . . . . . . . . . . . . . 26

ERASING FLASH MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Flash Bulk Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

2/110

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

Flash Sector Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Suspend Sector Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Resume Sector Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

SPECIFIC FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Flash Memory Sector Protect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Reset Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Reset (RESET) Signal (on the PSD83xF2 and PSD85xF2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

SECTOR SELECT AND SRAM SELECT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Memory Select Configuration for MCUs with Separate Program and Data Spaces . . . . . . . . 30 Configuration Modes for MCUs with Separate Program and Data Spaces . . . . . . . . . . . . . . . 30

PAGE REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

PLDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

The Turbo Bit in PSD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Decode PLD (DPLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Complex PLD (CPLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Output Macrocell (OMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Product Term Allocator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Loading and Reading the Output Macrocells (OMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

The OMC Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

The Output Enable of the OMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Input Macrocells (IMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

MCU BUS INTERFACE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

PSD Interface to a Multiplexed 8-Bit Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 PSD Interface to a Non-Multiplexed 8-Bit Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Data Byte Enable Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 MCU Bus Interface Examples. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 80C31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 80C251 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 80C51XA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 68HC11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

General Port Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Port Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

MCU I/O Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

PLD I/O Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Address Out Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Address In Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

3/110

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

Data Port Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Peripheral I/O Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

JTAG In-System Programming (ISP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Port Configuration Registers (PCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Direction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Drive Select Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Port Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Data In. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Data Out Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

OMC Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Input Macrocells (IMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Enable Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Ports A and B – Functionality and Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Port C – Functionality and Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Port D – Functionality and Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

External Chip Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

POWER MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Automatic Power-down (APD) Unit and Power-down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 For Users of the HC11 (or compatible) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Other Power Saving Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 PLD Power Management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 PSD Chip Select Input (CSI, PD2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Input Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Input Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

RESET TIMING AND DEVICE STATUS AT RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Power-Up Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Warm Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 I/O Pin, Register and PLD Status at Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Reset of Flash Memory Erase and Program Cycles (on the PSD834Fx) . . . . . . . . . . . . . . . . . 67

PROGRAMMING IN-CIRCUIT USING THE JTAG SERIAL INTERFACE . . . . . . . . . . . . . . . . . . . . . . 69

Standard JTAG Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 JTAG Extensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Security and Flash memory Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

INITIAL DELIVERY STATE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

AC/DC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

4/110

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

APPENDIX A.PQFP52 PIN ASSIGNMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

APPENDIX B.PLCC52 PIN ASSIGNMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

APPENDIX C.TQFP64 PIN ASSIGNMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

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PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

SUMMARY DESCRIPTION

The PSD8XXFX family of memory systems for microcontrollers (MCUs) brings In-System-Program- mability (ISP) to Flash memory and programmable logic. The result is a simple and flexible solution for embedded designs. PSD devices combine many of the peripheral functions found in MCU based applications.

Table 1 summarizes all the devices in the PSD834F2, PSD853F2, PSD854F2.

The CPLD in the PSD devices features an optimized macrocell logic architecture. The PSD macrocell was created to address the unique requirements of embedded system designs. It allows direct connection between the system address/data bus, and the internal PSD registers, to simplify communication between the MCU and other supporting devices.

The PSD device includes a JTAG Serial Programming interface, to allow In-System Programming (ISP) of the entire device. This feature reduces development time, simplifies the manufacturing flow, and dramatically lowers the cost of field upgrades. Using ST’s special Fast-JTAG programming, a design can be rapidly programmed into the PSD in as little as seven seconds.

The innovative PSD8XXFX family solves key problems faced by designers when managing discrete Flash memory devices, such as:

–First-time In-System Programming (ISP)

–Complex address decoding

–Simultaneous read and write to the device.

The JTAG Serial Interface block allows In-System Programming (ISP), and eliminates the need for an external Boot EPROM, or an external programmer. To simplify Flash memory updates, program execution is performed from a secondary Flash memory while the primary Flash memory is being updated. This solution avoids the complicated hardware and software overhead necessary to implement IAP.

ST makes available a software development tool, PSDsoft Express, that generates ANSI-C compliant code for use with your target MCU. This code allows you to manipulate the non-volatile memory (NVM) within the PSD. Code examples are also provided for:

–Flash memory IAP via the UART of the host MCU

–Memory paging to execute code across several PSD memory pages

–Loading, reading, and manipulation of PSD macrocells by the MCU.

Table 1. Product Range

		Primary Flash	Secondary			Number of		Serial
	Part Number(1)			SRAM(2)	I/O Ports	Macrocells		ISP	Turbo
		Memory	Flash Memory
								JTAG/	Mode
		(8 Sectors)	4 Sectors)			Input	Output
								ISC Port
	PSD813F2	1 Mbit	256 Kbit	16 Kbit	27	24	16	yes	yes
	PSD813F3	1 Mbit	none	16 Kbit	27	24	16	yes	yes
	PSD813F4	1 Mbit	256 Kbit	none	27	24	16	yes	yes
	PSD813F5	1 Mbit	none	none	27	24	16	yes	yes
	PSD833F2	1 Mbit	256 Kbit	64 Kbit	27	24	16	yes	yes
	PSD834F2	2 Mbit	256 Kbit	64 Kbit	27	24	16	yes	yes
	PSD853F2	1 Mbit	256 Kbit	256 Kbit	27	24	16	yes	yes
	PSD854F2	2 Mbit	256 Kbit	256 Kbit	27	24	16	yes	yes

Note: 1. All products support: JTAG serial ISP, MCU parallel ISP, ISP Flash memory, ISP CPLD, Security features, Power Management Unit (PMU), Automatic Power-down (APD)

2. SRAM may be backed up using an external battery.

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PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

Figure 2. PQFP52 Connections

																												RESET		CNTLO
					PB0		PB1		PB2		PB3		PB4		PB5		GND		PB6		PB7		CNTL1		CNTL2
	52						51		50	49			48	47		46			45		44	43		42				41	40
PD2	1																																	39 AD15
PD1	2																																	38 AD14
PD0	3																																	37 AD13
PC7	4																																	36 AD12
PC6	5																																	35 AD11
PC5	6																																	34 AD10
PC4	7																																	33 AD9
VCC	8																																	32 AD8
GND 9																																		31 VCC
PC3	10
																																		30 AD7
PC2	11																																	29 AD6
PC1	12																																	28 AD5
PC0	13																																	27 AD4
	14						15		16	17			18	19		20			21		22	23		24				25	26
					PA7		PA6		PA5		PA4		PA3		GND		PA2		PA1		PA0		AD0		AD1			AD2		AD3

AI02858

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PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

Figure 3. PLCC52 Connections

PD2	8
PD1	9
PD0	10
PC7	11
PC6	12
PC5	13
PC4	14
VCC	15
GND	16
PC3	17
PC2	18
PC1	19
PC0	20

PB0	PB1	PB2	PB3	PB4	PB5	GND	PB6	PB7	CNTL1	CNTL2	RESET	CNTL0
7	6	5	4	3	2	1	52	51	50	49	48	47
												46	AD15
												45	AD14
												44	AD13
												43	AD12
												42	AD11
												41	AD10
												40	AD9
												39	AD8
												38	VCC
												37	AD7
												36	AD6
												35	AD5
											32	34	AD4
21	22	23	24	25	26	27	28	29	30	31		33
PA7	PA6	PA5	PA4	PA3	GND	PA2	PA1	PA0	AD0	AD1	AD2	AD3	AI02857

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PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

Figure 4. TQFP64 Connections

RESET

NC

NC

PB0

PB1

PB2

PB3

PB4

PB5

GND

GND

PB6

PB7

CNTL1

CNTL2

NC

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

PD2

1

48 CNTL0

PD1

2

47 AD15

PD0

3

46 AD14

PC7

4

45 AD13

PC6

5

44 AD12

PC5

6

43 AD11

VCC 7

42 AD10

VCC 8

41 AD9

VCC 9

40 AD8

GND 10

39 VCC

GND 11

38 VCC

PC3

12

37 AD7

PC2

13

36 AD6

PC1

14

35 AD5

PC0

15

34 AD4

NC

16

33 AD3

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

NC

NC

PA7

PA6

PA5

PA4

PA3

GND

GND

PA2

PA1

PA0

AD0

AD1

ND

AD2

AI09645

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PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

PIN DESCRIPTION

Table 2. Pin Description (for the PLCC52 package - Note 1)

Pin Name

Pin

Type

Description

This is the lower Address/Data port. Connect your MCU address or address/data bus

according to the following rules:

If your MCU has a multiplexed address/data bus where the data is multiplexed with the

lower address bits, connect AD0-AD7 to this port.

If your MCU does not have a multiplexed address/data bus, or you are using an 80C251

ADIO0-7

30-37

I/O

in page mode, connect A0-A7 to this port.

If you are using an 80C51XA in burst mode, connect A4/D0 through A11/D7 to this port.

ALE or AS latches the address. The PSD drives data out only if the READ signal is active

and one of the PSD functional blocks was selected. The addresses on this port are

passed to the PLDs.

This is the upper Address/Data port. Connect your MCU address or address/data bus

according to the following rules:

If your MCU has a multiplexed address/data bus where the data is multiplexed with the

lower address bits, connect A8-A15 to this port.

If your MCU does not have a multiplexed address/data bus, connect A8-A15 to this port.

ADIO8-15

39-46

I/O

If you are using an 80C251 in page mode, connect AD8-AD15 to this port.

If you are using an 80C51XA in burst mode, connect A12/D8 through A19/D15 to this

port.

ALE or AS latches the address. The PSD drives data out only if the READ signal is active

and one of the PSD functional blocks was selected. The addresses on this port are

passed to the PLDs.

The following control signals can be connected to this port, based on your MCU:

WR – active Low Write Strobe input.

CNTL0

47

I

R_

W

– active High READ/active Low write input.

This port is connected to the PLDs. Therefore, these signals can be used in decode and

other logic equations.

The following control signals can be connected to this port, based on your MCU:

RD – active Low Read Strobe input.

E – E clock input.

DS

– active Low Data Strobe input.

CNTL1

50

I

to this port when it is being used as an active Low READ signal.

PSEN

– connect

PSEN

For example, when the 80C251 outputs more than 16 address bits, PSEN is actually the

READ signal.

This port is connected to the PLDs. Therefore, these signals can be used in decode and

other logic equations.

This port can be used to input the

(Program Select Enable) signal from any MCU

PSEN

CNTL2

49

I

that uses this signal for code exclusively. If your MCU does not output a Program Select

Enable signal, this port can be used as a generic input. This port is connected to the

PLDs.

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				PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
	Pin Name	Pin	Type	Description
	Reset	48	I	Resets I/O Ports, PLD macrocells and some of the Configuration Registers. Must be Low
				at Power-up.
				These pins make up Port A. These port pins are configurable and can have the following
				functions:
				MCU I/O – write to or read from a standard output or input port.
				CPLD macrocell (McellAB0-7) outputs.
	PA0	29		Inputs to the PLDs.
	PA1	28		Latched address outputs (see Table 6).
	PA2	27
	PA3	25	I/O	Address inputs. For example, PA0-3 could be used for A0-A3 when using an 80C51XA in
	PA4	24
				burst mode.
	PA5	23
	PA6	22		As the data bus inputs D0-D7 for non-multiplexed address/data bus MCUs.
	PA7	21
				D0/A16-D3/A19 in M37702M2 mode.
				Peripheral I/O mode.
				Note: PA0-PA3 can only output CMOS signals with an option for high slew rate. However,
				PA4-PA7 can be configured as CMOS or Open Drain Outputs.
				These pins make up Port B. These port pins are configurable and can have the following
				functions:
	PB0	7		MCU I/O – write to or read from a standard output or input port.
	PB1	6
	PB2	5		CPLD macrocell (McellAB0-7 or McellBC0-7) outputs.
	PB3	4	I/O
	PB4	3		Inputs to the PLDs.
	PB5	2
	PB6	52		Latched address outputs (see Table 6).
	PB7	51		Note: PB0-PB3 can only output CMOS signals with an option for high slew rate.
				However, PB4-PB7 can be configured as CMOS or Open Drain Outputs.
				PC0 pin of Port C. This port pin can be configured to have the following functions:
				MCU I/O – write to or read from a standard output or input port.
				CPLD macrocell (McellBC0) output.
	PC0	20	I/O	Input to the PLDs.
				TMS Input2 for the JTAG Serial Interface.
				This pin can be configured as a CMOS or Open Drain output.
				PC1 pin of Port C. This port pin can be configured to have the following functions:
				MCU I/O – write to or read from a standard output or input port.
				CPLD macrocell (McellBC1) output.
	PC1	19	I/O	Input to the PLDs.
				TCK Input2 for the JTAG Serial Interface.
				This pin can be configured as a CMOS or Open Drain output.

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PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

Pin Name	Pin	Type						Description
				PC2 pin of Port C. This port pin can be configured to have the following functions:
				MCU I/O – write to or read from a standard output or input port.
				CPLD macrocell (McellBC2) output.
PC2	18	I/O		Input to the PLDs.
				VSTBY – SRAM stand-by voltage input for SRAM battery backup.
				This pin can be configured as a CMOS or Open Drain output.
				PC3 pin of Port C. This port pin can be configured to have the following functions:
				MCU I/O – write to or read from a standard output or input port.
				CPLD macrocell (McellBC3) output.
PC3	17	I/O		Input to the PLDs.
							output2 for the JTAG Serial Interface.
				TSTAT
				Ready/Busy				output for parallel In-System Programming (ISP).
				This pin can be configured as a CMOS or Open Drain output.
				PC4 pin of Port C. This port pin can be configured to have the following functions:
				MCU I/O – write to or read from a standard output or input port.
				CPLD macrocell (McellBC4) output.
				Input to the PLDs.
PC4	14	I/O			output2 for the JTAG Serial Interface.
				TERR
				Battery-on Indicator (VBATON). Goes High when power is being drawn from the external
				battery.
				This pin can be configured as a CMOS or Open Drain output.
				PC5 pin of Port C. This port pin can be configured to have the following functions:
				MCU I/O – write to or read from a standard output or input port.
				CPLD macrocell (McellBC5) output.
PC5	13	I/O		Input to the PLDs.
				TDI input2 for the JTAG Serial Interface.
				This pin can be configured as a CMOS or Open Drain output.
				PC6 pin of Port C. This port pin can be configured to have the following functions:
				MCU I/O – write to or read from a standard output or input port.
				CPLD macrocell (McellBC6) output.
PC6	12	I/O		Input to the PLDs.
				TDO output2 for the JTAG Serial Interface.
				This pin can be configured as a CMOS or Open Drain output.

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			PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
Pin Name	Pin	Type			Description
			PC7 pin of Port C. This port pin can be configured to have the following functions:
			MCU I/O – write to or read from a standard output or input port.
			CPLD macrocell (McellBC7) output.
PC7	11	I/O	Input to the PLDs.
			DBE – active Low Data Byte Enable input from 68HC912 type MCUs.
			This pin can be configured as a CMOS or Open Drain output.
			PD0 pin of Port D. This port pin can be configured to have the following functions:
			ALE/AS input latches address output from the MCU.
PD0	10	I/O	MCU I/O – write or read from a standard output or input port.
			Input to the PLDs.
			CPLD output (External Chip Select).
			PD1 pin of Port D. This port pin can be configured to have the following functions:
			MCU I/O – write to or read from a standard output or input port.
			Input to the PLDs.
PD1	9	I/O
			CPLD output (External Chip Select).
			CLKIN – clock input to the CPLD macrocells, the APD Unit’s Power-down counter, and
			the CPLD AND Array.
			PD2 pin of Port D. This port pin can be configured to have the following functions:
			MCU I/O - write to or read from a standard output or input port.
			Input to the PLDs.
PD2	8	I/O	CPLD output (External Chip Select).
			PSD Chip Select Input (CSI). When Low, the MCU can access the PSD memory and I/O.
			When High, the PSD memory blocks are disabled to conserve power.
VCC	15, 38		Supply Voltage
GND	1, 16,		Ground pins
	26

Note: 1. The pin numbers in this table are for the PLCC package only. See the package information from Table 74., page 102 onwards, for pin numbers on other package types.

2. These functions can be multiplexed with other functions.

13/110

14/110

	ADDRESS/DATA/CONTROL BUS
	PLD
	INPUT
	BUS	1 OR 2 MBIT PRIMARY
	PAGE
		FLASH MEMORY
	REGISTER
	EMBEDDED
	ALGORITHM	8 SECTORS
	8

CNTL0,				SECTOR		256 KBIT SECONDARY
CNTL1,						NON-VOLATILE MEMORY
	PROG.			SELECTS
CNTL2						(BOOT OR DATA)
	MCU BUS			FLASH DECODE
				PLD (DPLD)		4 SECTORS
	INTRF.
		73
				SECTOR
				SELECTS
				SRAM SELECT		256 KBIT BATTERY
						BACKUP SRAM
				PERIP I/O MODE SELECTS
				CSIOP
AD0 – AD15	ADIO				RUNTIME CONTROL
					AND I/O REGISTERS
	PORT
			73	FLASH ISP CPLD	3 EXT CS TO PORT D
				(CPLD)
				16 OUTPUT MACROCELLS
					PORT A ,B & C
					24 INPUT MACROCELLS
		CLKIN			PORT A ,B & C
	GLOBAL		MACROCELL FEEDBACK OR PORT INPUT
	CONFIG. &
	SECURITY			CLKIN
	CLKIN			PLD, CONFIGURATION		JTAG
				& FLASH MEMORY		SERIAL
	(PD1)
				LOADER		CHANNEL

AI02861E

POWER					VSTDBY
MANGMT
UNIT					(PC2)
PROG.			PA0 – PA7
PORT
PORT
A
PROG.
PORT			PB0 – PB7
PORT
B
PROG.
PORT			PC0 – PC7
PORT
C
PROG.
PORT			PD0 – PD2
PORT
D

Diagram Block PSD .5Figure	PSD834F2, PSD833F2, PSD813F2,
	PSD854F2 PSD853F2,

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

PSD ARCHITECTURAL OVERVIEW

PSD devices contain several major functional blocks. Figure 5 shows the architecture of the PSD device family. The functions of each block are described briefly in the following sections. Many of the blocks perform multiple functions and are user configurable.

Memory

Each of the memory blocks is briefly discussed in the following paragraphs. A more detailed discussion can be found in the section entitled Memory Blocks, page 19.

The 1 Mbit or 2 Mbit (128K x 8, or 256K x 8) Flash memory is the primary memory of the PSD. It is divided into 8 equally-sized sectors that are individually selectable.

The optional 256 Kbit (32K x 8) secondary Flash memory is divided into 4 equally-sized sectors. Each sector is individually selectable.

The optional SRAM is intended for use as a scratch-pad memory or as an extension to the MCU SRAM. If an external battery is connected to

Voltage Stand-by (VSTBY, PC2), data is retained in the event of power failure.

Each sector of memory can be located in a different address space as defined by the user. The access times for all memory types includes the address latching and DPLD decoding time.

Page Register

The 8-bit Page Register expands the address range of the MCU by up to 256 times. The paged address can be used as part of the address space to access external memory and peripherals, or internal memory and I/O. The Page Register can also be used to change the address mapping of sectors of the Flash memories into different memory spaces for IAP.

PLDs

The device contains two PLDs, the Decode PLD (DPLD) and the Complex PLD (CPLD), as shown in Table 3, each optimized for a different function. The functional partitioning of the PLDs reduces power consumption, optimizes cost/performance, and eases design entry.

The DPLD is used to decode addresses and to generate Sector Select signals for the PSD internal memory and registers. The DPLD has combinatorial outputs. The CPLD has 16 Output Macrocells (OMC) and 3 combinatorial outputs. The PSD also has 24 Input Macrocells (IMC) that can be configured as inputs to the PLDs. The PLDs receive their inputs from the PLD Input Bus and are differentiated by their output destinations, number of product terms, and macrocells.

The PLDs consume minimal power. The speed and power consumption of the PLD is controlled by the Turbo Bit in PMMR0 and other bits in the PMMR2. These registers are set by the MCU at run-time. There is a slight penalty to PLD propagation time when invoking the power management features.

I/O Ports

The PSD has 27 individually configurable I/O pins distributed over the four ports (Port A, B, C, and D). Each I/O pin can be individually configured for different functions. Ports can be configured as standard MCU I/O ports, PLD I/O, or latched address outputs for MCUs using multiplexed address/data buses.

The JTAG pins can be enabled on Port C for InSystem Programming (ISP).

Ports A and B can also be configured as a data port for a non-multiplexed bus.

MCU Bus Interface

PSD interfaces easily with most 8-bit MCUs that have either multiplexed or non-multiplexed address/data buses. The device is configured to respond to the MCU’s control signals, which are also used as inputs to the PLDs. For examples, please see the section entitled MCU Bus Interface Examples, page 45.

Table 3. PLD I/O

	Name	Inputs	Outputs	Product
				Terms
	Decode PLD (DPLD)	73	17	42
	Complex PLD (CPLD)	73	19	140

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PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

JTAG Port

In-System Programming (ISP) can be performed through the JTAG signals on Port C. This serial interface allows complete programming of the entire PSD device. A blank device can be completely programmed. The JTAG signals (TMS, TCK, TSTAT, TERR, TDI, TDO) can be multiplexed with other functions on Port C. Table 4 indicates the JTAG pin assignments.

In-System Programming (ISP)

Using the JTAG signals on Port C, the entire PSD device can be programmed or erased without the use of the MCU. The primary Flash memory can also be programmed in-system by the MCU executing the programming algorithms out of the secondary memory, or SRAM. The secondary memory can be programmed the same way by executing out of the primary Flash memory. The PLD or other PSD Configuration blocks can be programmed through the JTAG port or a device programmer. Table 5 indicates which programming methods can program different functional blocks of the PSD.

Power Management Unit (PMU)

The Power Management Unit (PMU) gives the user control of the power consumption on selected functional blocks based on system requirements. The PMU includes an Automatic Power-down (APD) Unit that turns off device functions during

MCU inactivity. The APD Unit has a Power-down mode that helps reduce power consumption.

The PSD also has some bits that are configured at run-time by the MCU to reduce power consumption of the CPLD. The Turbo Bit in PMMR0 can be reset to '0' and the CPLD latches its outputs and goes to sleep until the next transition on its inputs.

Additionally, bits in PMMR2 can be set by the MCU to block signals from entering the CPLD to reduce power consumption. Please see the section entitled POWER MANAGEMENT, page 62 for more details.

Table 4. JTAG SIgnals on Port C

Port C Pins				JTAG Signal
PC0		TMS
PC1		TCK
PC3
		TSTAT
PC4
		TERR
PC5		TDI
PC6		TDO

Table 5. Methods of Programming Different Functional Blocks of the PSD

Functional Block	JTAG Programming	Device Programmer	IAP
Primary Flash Memory	Yes	Yes	Yes
Secondary Flash Memory	Yes	Yes	Yes
PLD Array (DPLD and CPLD)	Yes	Yes	No
PSD Configuration	Yes	Yes	No

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PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

DEVELOPMENT SYSTEM

The PSD8XXFX family is supported by PSDsoft Express, a Windows-based software development tool. A PSD design is quickly and easily produced in a point and click environment. The designer does not need to enter Hardware Description Language (HDL) equations, unless desired, to define PSD pin functions and memory map information. The general design flow is shown in Figure 6. PSDsoft Express is available from our web site (the address is given on the back page of this data sheet) or other distribution channels.

Figure 6. PSDsoft Express Development Tool

PSDsoft Express directly supports two low cost device programmers form ST: PSDpro and FlashLINK (JTAG). Both of these programmers may be purchased through your local distributor/ representative, or directly from our web site using a credit card. The PSD is also supported by third party device programmers. See our web site for the current list.

PSDabel

PLD DESCRIPTION

MODIFY ABEL TEMPLATE FILE

OR GENERATE NEW FILE

PSD Configuration

PSD TOOLS

CONFIGURE MCU BUS

GENERATE C CODE

INTERFACE AND OTHER

SPECIFIC TO PSD

PSD ATTRIBUTES

FUNCTIONS

PSD Fitter

USER'S CHOICE OF

LOGIC SYNTHESIS

FIRMWARE

AND FITTING

MICROCONTROLLER

HEX OR S-RECORD

COMPILER/LINKER

ADDRESS TRANSLATION

FORMAT

AND MEMORY MAPPING

*.OBJ FILE

PSD Simulator

PSD Programmer

*.OBJ AND *.SVF

FILES AVAILABLE

PSDsilos III

PSDPro, or

FOR 3rd PARTY

PROGRAMMERS

DEVICE SIMULATION

FlashLINK (JTAG)

(CONVENTIONAL or

(OPTIONAL)

JTAG-ISC)

AI04918

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PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

PSD REGISTER DESCRIPTION AND ADDRESS OFFSET

Table 6 shows the offset addresses to the PSD registers relative to the CSIOP base address. The CSIOP space is the 256 bytes of address that is allocated by the user to the internal PSD registers.

Table 7 provides brief descriptions of the registers in CSIOP space. The following section gives a more detailed description.

Table 6. I/O Port Latched Address Output Assignments (Note1)

	MCU		Port A		Port B
		Port A (3:0)		Port A (7:4)	Port B (3:0)	Port B (7:4)
8051XA (8-bit)		N/A		Address a7-a4	Address a11-a8	N/A
80C251 (page mode)		N/A		N/A	Address a11-a8	Address a15-a12
All other 8-bit multiplexed		Address a3-a0		Address a7-a4	Address a3-a0	Address a7-a4
8-bit non-multiplexed bus		N/A		N/A	Address a3-a0	Address a7-a4
Note: 1.	See the section entitled I/O PORTS, page 51, on how to enable the Latched Address Output function.
2.	N/A = Not Applicable

Table 7. Register Address Offset

Register Name	Port A	Port B	Port C	Port D	Other1	Description
Data In	00	01	10	11		Reads Port pin as input, MCU I/O input mode
Control	02	03				Selects mode between MCU I/O or Address Out
Data Out	04	05	12	13		Stores data for output to Port pins, MCU I/O
						output mode
Direction	06	07	14	15		Configures Port pin as input or output
						Configures Port pins as either CMOS or Open
Drive Select	08	09	16	17		Drain on some pins, while selecting high slew rate
						on other pins.
Input Macrocell	0A	0B	18			Reads Input Macrocells
Enable Out	0C	0D	1A	1B		Reads the status of the output enable to the I/O
						Port driver
Output Macrocells	20	20				READ – reads output of macrocells AB
AB						WRITE – loads macrocell flip-flops
Output Macrocells		21	21			READ – reads output of macrocells BC
BC						WRITE – loads macrocell flip-flops
Mask Macrocells AB	22	22				Blocks writing to the Output Macrocells AB
Mask Macrocells BC		23	23			Blocks writing to the Output Macrocells BC
Primary Flash					C0	Read only – Primary Flash Sector Protection
Protection
Secondary Flash					C2	Read only – PSD Security and Secondary Flash
memory Protection						memory Sector Protection
JTAG Enable					C7	Enables JTAG Port
PMMR0					B0	Power Management Register 0
PMMR2					B4	Power Management Register 2
Page					E0	Page Register
VM					E2	Places PSD memory areas in Program and/or
						Data space on an individual basis.
Note: 1. Other registers that are not part of the I/O ports.
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DETAILED OPERATION

As shown in Figure 5., page 14, the PSD consists of six major types of functional blocks:

■Memory Blocks

■PLD Blocks

■MCU Bus Interface

■I/O Ports

■Power Management Unit (PMU)

■JTAG Interface

The functions of each block are described in the following sections. Many of the blocks perform multiple functions, and are user configurable.

Table 8. Memory Block Size and Organization

Memory Blocks

The PSD has the following memory blocks:

–Primary Flash memory

–Optional Secondary Flash memory

–Optional SRAM

The Memory Select signals for these blocks originate from the Decode PLD (DPLD) and are userdefined in PSDsoft Express.

	Primary Flash Memory		Secondary Flash Memory		SRAM
Sector	Sector Size	Sector Select	Sector Size	Sector Select	SRAM Size	SRAM Select
Number	(Bytes)	Signal	(Bytes)	Signal	(Bytes)	Signal
0	32K	FS0	16K	CSBOOT0	256K	RS0
1	32K	FS1	16K	CSBOOT1
2	32K	FS2	16K	CSBOOT2
3	32K	FS3	16K	CSBOOT3
4	32K	FS4
5	32K	FS5
6	32K	FS6
7	32K	FS7
Total	512K	8 Sectors	64K	4 Sectors	256K

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Primary Flash Memory and Secondary Flash memory Description

The primary Flash memory is divided evenly into eight equal sectors. The secondary Flash memory is divided into four equal sectors. Each sector of either memory block can be separately protected from Program and Erase cycles.

Flash memory may be erased on a sector-by-sec- tor basis. Flash sector erasure may be suspended while data is read from other sectors of the block and then resumed after reading.

During a Program or Erase cycle in Flash memory, the status can be output on Ready/Busy (PC3). This pin is set up using PSDsoft Express Configuration.

Memory Block Select Signals

The DPLD generates the Select signals for all the internal memory blocks (see the section entitled PLDS, page 33). Each of the eight sectors of the primary Flash memory has a Select signal (FS0FS7) which can contain up to three product terms. Each of the four sectors of the secondary Flash memory has a Select signal (CSBOOT0CSBOOT3) which can contain up to three product terms. Having three product terms for each Select signal allows a given sector to be mapped in different areas of system memory. When using a MCU with separate Program and Data space, these flexible Select signals allow dynamic re-mapping of sectors from one memory space to the other.

Ready/Busy (PC3). This signal can be used to output the Ready/Busy status of the PSD. The output on Ready/Busy (PC3) is a 0 (Busy) when Flash memory is being written to, or when Flash memory is being erased. The output is a 1 (Ready) when no WRITE or Erase cycle is in progress.

Memory Operation. The primary Flash memory and secondary Flash memory are addressed through the MCU Bus Interface. The MCU can access these memories in one of two ways:

–The MCU can execute a typical bus WRITE or READ operation just as it would if accessing a RAM or ROM device using standard bus cycles.

–The MCU can execute a specific instruction that consists of several WRITE and READ operations. This involves writing specific data patterns to special addresses within the Flash memory to invoke an embedded algorithm. These instructions are summarized in Table 9., page 21.

Typically, the MCU can read Flash memory using READ operations, just as it would read a ROM device. However, Flash memory can only be altered using specific Erase and Program instructions. For example, the MCU cannot write a single byte directly to Flash memory as it would write a byte to RAM. To program a byte into Flash memory, the MCU must execute a Program instruction, then test the status of the Program cycle. This status test is achieved by a READ operation or polling Ready/Busy (PC3).

Flash memory can also be read by using special instructions to retrieve particular Flash device information (sector protect status and ID).

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Table 9. Instructions

		FS0-FS7 or
	Instruction	CSBOOT0-	Cycle 1	Cycle 2	Cycle 3	Cycle 4	Cycle 5	Cycle 6	Cycle 7
		CSBOOT3
	READ5	1	“READ”
			RD @ RA
	Read Main	1	AAh@	55h@	90h@	Read identifier
	Flash ID6		X555h	XAAAh	X555h	(A6,A1,A0 = 0,0,1)
	Read Sector	1	AAh@	55h@	90h@	Read identifier
	Protection6,8,13		X555h	XAAAh	X555h	(A6,A1,A0 = 0,1,0)
	Program a	1	AAh@	55h@	A0h@	PD@ PA
	Flash Byte13		X555h	XAAAh	X555h
	Flash Sector	1	AAh@	55h@	80h@	AAh@ X555h	55h@	30h@	30h7@
	Erase7,13		X555h	XAAAh	X555h		XAAAh	SA	next SA
	Flash Bulk	1	AAh@	55h@	80h@	AAh@ X555h	55h@	10h@
	Erase13		X555h	XAAAh	X555h		XAAAh	X555h
	Suspend	1	B0h@
	Sector Erase11		XXXXh
	Resume	1	30h@
	Sector Erase12		XXXXh
	Reset6	1	F0h@
			XXXXh
	Unlock Bypass	1	AAh@	55h@	20h@
			X555h	XAAAh	X555h
	Unlock Bypass	1	A0h@	PD@ PA
	Program9		XXXXh
	Unlock Bypass	1	90h@	00h@
	Reset10		XXXXh	XXXXh

Note: 1. All bus cycles are WRITE bus cycles, except the ones with the “READ” label

2.All values are in hexadecimal:

X = Don’t Care. Addresses of the form XXXXh, in this table, must be even addresses RA = Address of the memory location to be read

RD = Data read from location RA during the READ cycle

PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of Write Strobe (WR, CNTL0). PA is an even address for PSD in word programming mode.

PD = Data word to be programmed at location PA. Data is latched on the rising edge of Write Strobe (WR, CNTL0)

SA = Address of the sector to be erased or verified. The Sector Select (FS0-FS7 or CSBOOT0-CSBOOT3) of the sector to be erased, or verified, must be Active (High).

3.Sector Select (FS0 to FS7 or CSBOOT0 to CSBOOT3) signals are active High, and are defined in PSDsoft Express.

4.Only address bits A11-A0 are used in instruction decoding.

5.No Unlock or instruction cycles are required when the device is in the READ Mode

6.The Reset instruction is required to return to the READ Mode after reading the Flash ID, or after reading the Sector Protection Status, or if the Error Flag Bit (DQ5/DQ13) goes High.

7.Additional sectors to be erased must be written at the end of the Sector Erase instruction within 80µs.

8.The data is 00h for an unprotected sector, and 01h for a protected sector. In the fourth cycle, the Sector Select is active, and (A1,A0)=(1,0)

9.The Unlock Bypass instruction is required prior to the Unlock Bypass Program instruction.

10.The Unlock Bypass Reset Flash instruction is required to return to reading memory data when the device is in the Unlock Bypass mode.

11.The system may perform READ and Program cycles in non-erasing sectors, read the Flash ID or read the Sector Protection Status when in the Suspend Sector Erase mode. The Suspend Sector Erase instruction is valid only during a Sector Erase cycle.

12.The Resume Sector Erase instruction is valid only during the Suspend Sector Erase mode.

13.The MCU cannot invoke these instructions while executing code from the same Flash memory as that for which the instruction is intended. The MCU must fetch, for example, the code from the secondary Flash memory when reading the Sector Protection Status of the primary Flash memory.

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INSTRUCTIONS

An instruction consists of a sequence of specific operations. Each received byte is sequentially decoded by the PSD and not executed as a standard WRITE operation. The instruction is executed when the correct number of bytes are properly received and the time between two consecutive bytes is shorter than the time-out period. Some instructions are structured to include READ operations after the initial WRITE operations.

The instruction must be followed exactly. Any invalid combination of instruction bytes or time-out between two consecutive bytes while addressing Flash memory resets the device logic into READ Mode (Flash memory is read like a ROM device).

The PSD supports the instructions summarized in Table 9., page 21:

Flash memory:

■Erase memory by chip or sector

■Suspend or resume sector erase

■Program a Byte

■Reset to READ Mode

■Read primary Flash Identifier value

■Read Sector Protection Status

■Bypass (on the PSD833F2, PSD834F2, PSD853F2 and PSD854F2)

These instructions are detailed in Table 9., page 21. For efficient decoding of the instructions, the first two bytes of an instruction are the coded cycles and are followed by an instruction byte or confirmation byte. The coded cycles consist of writing the data AAh to address X555h during the first cycle and data 55h to address XAAAh during the second cycle. Address signals A15-A12 are Don’t Care during the instruction WRITE cycles. However, the appropriate Sector Select (FS0-FS7 or CSBOOT0-CSBOOT3) must be selected.

The primary and secondary Flash memories have the same instruction set (except for Read Primary Flash Identifier). The Sector Select signals determine which Flash memory is to receive and execute the instruction. The primary Flash memory is selected if any one of Sector Select (FS0-FS7) is High, and the secondary Flash memory is selected if any one of Sector Select (CSBOOT0CSBOOT3) is High.

Power-up Mode

The PSD internal logic is reset upon Power-up to the READ Mode. Sector Select (FS0-FS7 and CSBOOT0-CSBOOT3) must be held Low, and Write Strobe (WR, CNTL0) High, during Power-up

for maximum security of the data contents and to remove the possibility of a byte being written on the first edge of Write Strobe (WR, CNTL0). Any WRITE cycle initiation is locked when VCC is below VLKO.

READ

Under typical conditions, the MCU may read the primary Flash memory or the secondary Flash memory using READ operations just as it would a ROM or RAM device. Alternately, the MCU may use READ operations to obtain status information about a Program or Erase cycle that is currently in progress. Lastly, the MCU may use instructions to read special data from these memory blocks. The following sections describe these READ functions.

Read Memory Contents

Primary Flash memory and secondary Flash memory are placed in the READ Mode after Pow- er-up, chip reset, or a Reset Flash instruction (see Table 9., page 21). The MCU can read the memory contents of the primary Flash memory or the secondary Flash memory by using READ operations any time the READ operation is not part of an instruction.

Read Primary Flash Identifier

The primary Flash memory identifier is read with an instruction composed of 4 operations: 3 specific WRITE operations and a READ operation (see Table 9., page 21). During the READ operation, address bits A6, A1, and A0 must be '0,0,1,' respectively, and the appropriate Sector Select (FS0-FS7) must be High. The identifier for the PSD813F2/3/4/5 is E4h, and for the PSD83xF2 or PSD85xF2 it is E7h.

Read Memory Sector Protection Status

The primary Flash memory Sector Protection Status is read with an instruction composed of 4 operations: 3 specific WRITE operations and a READ operation (see Table 9., page 21). During the READ operation, address Bits A6, A1, and A0 must be '0,1,0,' respectively, while Sector Select (FS0-FS7 or CSBOOT0-CSBOOT3) designates the Flash memory sector whose protection has to be verified. The READ operation produces 01h if the Flash memory sector is protected, or 00h if the sector is not protected.

The sector protection status for all NVM blocks (primary Flash memory or secondary Flash memory) can also be read by the MCU accessing the Flash Protection registers in PSD I/O space. See the section entitled Flash Memory Sector Protect, page 28 for register definitions.

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Reading the Erase/Program Status Bits

The PSD provides several status bits to be used by the MCU to confirm the completion of an Erase or Program cycle of Flash memory. These status bits minimize the time that the MCU spends performing these tasks and are defined in Table 10. The status bits can be read as many times as needed.

For Flash memory, the MCU can perform a READ operation to obtain these status bits while an Erase or Program instruction is being executed by the embedded algorithm. See the section entitled PROGRAMMING FLASH MEMORY, page 25 for details.

Table 10. Status Bit

	Functional Block	FS0-FS7/CSBOOT0-	DQ7	DQ6	DQ5	DQ4	DQ3	DQ2	DQ1	DQ0
		CSBOOT3
		VIH	Data	Toggle	Error		Erase
	Flash Memory					X	Time-	X	X	X
			Polling	Flag	Flag
							out

Note: 1. X = Not guaranteed value, can be read either '1' or ’0.’

2.DQ7-DQ0 represent the Data Bus bits, D7-D0.

3.FS0-FS7 and CSBOOT0-CSBOOT3 are active High.

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When the internal cycle is complete, the toggling stops and the data read on the Data Bus D0-D7 is the addressed memory byte. The device is now accessible for a new READ or WRITE operation. The cycle is finished when two successive READs yield the same output data.

Erase Time-out Flag (DQ3)

The PSD offers another way for determining when the Flash memory Program cycle is completed. During the internal WRITE operation and when ei-

ther the FS0-FS7 or CSBOOT0-CSBOOT3 is true,

the Toggle Flag Bit (DQ6) toggles from '0' to '1' andThe Erase Time-out Flag Bit (DQ3) reflects the '1' to '0' on subsequent attempts to read any bytetime-out period allowed between two consecutive of the memory. Sector Erase instructions. The Erase Time-out

Flag Bit (DQ3) is reset to '0' after a Sector Erase cycle for a time period of 100µs + 20% unless an additional Sector Erase instruction is decoded. After this time period, or when the additional Sector Erase instruction is decoded, the Erase Time-out Flag Bit (DQ3) is set to '1.'

Toggle Flag (DQ6)

In case of an error in a Flash memory Sector Erase or Byte Program cycle, the Flash memory sector in which the error occurred or to which the programmed byte belongs must no longer be used. Other Flash memory sectors may still be used. The Error Flag Bit (DQ5) is reset after a Reset Flash instruction.

– If the byte to be programmed is in a protected Flash memory sector, the instruction is ignored.

– If all the Flash memory sectors to be erased are protected, the Data Polling Flag Bit (DQ7) is reset to '0' for about 100µs, and then returns to the previous addressed byte. No erasure is performed.

In the case of Flash memory programming, the Error Flag Bit (DQ5) indicates the attempt to program a Flash memory bit from the programmed state,

’0,’ to the erased state, '1,' which is not valid. The Error Flag Bit (DQ5) may also indicate a Time-out condition while attempting to program a byte.

– During an Erase cycle, the Data Polling Flag Bit (DQ7) outputs a ’0.’ After completion of the cycle, the Data Polling Flag Bit (DQ7) outputs the last bit programmed (it is a '1' after erasing).

– If all the Flash memory sectors selected for erasure are protected, the Toggle Flag Bit (DQ6) toggles to '0' for about 100µs and then returns to the previous addressed byte.

Error Flag (DQ5)

During a normal Program or Erase cycle, the Error Flag Bit (DQ5) is to ’0.’ This bit is set to '1' when there is a failure during Flash memory Byte Program, Sector Erase, or Bulk Erase cycle.

– Data Polling is effective after the fourth WRITE pulse (for a Program instruction) or after the sixth WRITE pulse (for an Erase instruction). It must be performed at the address being programmed or at an address within the Flash memory sector being erased.

– The Toggle Flag Bit (DQ6) is effective after the fourth WRITE pulse (for a Program instruction) or after the sixth WRITE pulse (for an Erase instruction).

– If the byte to be programmed belongs to a protected Flash memory sector, the instruction is ignored.

Data Polling Flag (DQ7)

When erasing or programming in Flash memory, the Data Polling Flag Bit (DQ7) outputs the complement of the bit being entered for programming/ writing on the DQ7 Bit. Once the Program instruction or the WRITE operation is completed, the true logic value is read on the Data Polling Flag Bit (DQ7, in a READ operation).

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

PROGRAMMING FLASH MEMORY

Flash memory must be erased prior to being programmed. A byte of Flash memory is erased to all 1s (FFh), and is programmed by setting selected bits to ’0.’ The MCU may erase Flash memory all at once or by-sector, but not byte-by-byte. However, the MCU may program Flash memory byte-by- byte.

The primary and secondary Flash memories require the MCU to send an instruction to program a byte or to erase sectors (see Table 9., page 21).

Once the MCU issues a Flash memory Program or Erase instruction, it must check for the status bits for completion. The embedded algorithms that are invoked inside the PSD support several means to provide status to the MCU. Status may be checked using any of three methods: Data Polling, Data Toggle, or Ready/Busy (PC3).

Data Polling

Polling on the Data Polling Flag Bit (DQ7) is a method of checking whether a Program or Erase cycle is in progress or has completed. Figure 7 shows the Data Polling algorithm.

When the MCU issues a Program instruction, the embedded algorithm within the PSD begins. The MCU then reads the location of the byte to be programmed in Flash memory to check status. The Data Polling Flag Bit (DQ7) of this location becomes the complement of b7 of the original data byte to be programmed. The MCU continues to poll this location, comparing the Data Polling Flag Bit (DQ7) and monitoring the Error Flag Bit (DQ5). When the Data Polling Flag Bit (DQ7) matches b7 of the original data, and the Error Flag Bit (DQ5) remains ’0,’ the embedded algorithm is complete.

If the Error Flag Bit (DQ5) is '1,' the MCU should test the Data Polling Flag Bit (DQ7) again since the Data Polling Flag Bit (DQ7) may have changed simultaneously with the Error Flag Bit (DQ5, see Figure 7).

The Error Flag Bit (DQ5) is set if either an internal time-out occurred while the embedded algorithm attempted to program the byte or if the MCU attempted to program a '1' to a bit that was not erased (not erased is logic '0').

It is suggested (as with all Flash memories) to read the location again after the embedded program-

ming algorithm has completed, to compare the byte that was written to the Flash memory with the byte that was intended to be written.

When using the Data Polling method during an Erase cycle, Figure 7 still applies. However, the Data Polling Flag Bit (DQ7) is '0' until the Erase cycle is complete. A 1 on the Error Flag Bit (DQ5) indicates a time-out condition on the Erase cycle; a

0 indicates no error. The MCU can read any location within the sector being erased to get the Data Polling Flag Bit (DQ7) and the Error Flag Bit (DQ5).

PSDsoft Express generates ANSI C code functions which implement these Data Polling algorithms.

Figure 7. Data Polling Flowchart

	START
READ DQ5 & DQ7
at VALID ADDRESS
	DQ7	YES
	=
	DATA
	NO
NO	DQ5
	= 1
	YES
	READ DQ7
	DQ7	YES
	=
	DATA
	NO
	FAIL	PASS
		AI01369B

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Data Toggle

Checking the Toggle Flag Bit (DQ6) is a method of determining whether a Program or Erase cycle is in progress or has completed. Figure 8 shows the Data Toggle algorithm.

When the MCU issues a Program instruction, the embedded algorithm within the PSD begins. The MCU then reads the location of the byte to be programmed in Flash memory to check status. The Toggle Flag Bit (DQ6) of this location toggles each time the MCU reads this location until the embedded algorithm is complete. The MCU continues to read this location, checking the Toggle Flag Bit (DQ6) and monitoring the Error Flag Bit (DQ5). When the Toggle Flag Bit (DQ6) stops toggling (two consecutive reads yield the same value), and the Error Flag Bit (DQ5) remains ’0,’ the embedded algorithm is complete. If the Error Flag Bit (DQ5) is '1,' the MCU should test the Toggle Flag Bit (DQ6) again, since the Toggle Flag Bit (DQ6) may have changed simultaneously with the Error Flag Bit (DQ5, see Figure 8).

The Error Flag Bit (DQ5) is set if either an internal time-out occurred while the embedded algorithm attempted to program the byte, or if the MCU attempted to program a '1' to a bit that was not erased (not erased is logic '0').

It is suggested (as with all Flash memories) to read the location again after the embedded programming algorithm has completed, to compare the byte that was written to Flash memory with the byte that was intended to be written.

When using the Data Toggle method after an Erase cycle, Figure 8 still applies. the Toggle Flag Bit (DQ6) toggles until the Erase cycle is complete.

A '1' on the Error Flag Bit (DQ5) indicates a timeout condition on the Erase cycle; a '0' indicates no error. The MCU can read any location within the sector being erased to get the Toggle Flag Bit (DQ6) and the Error Flag Bit (DQ5).

PSDsoft Express generates ANSI C code functions which implement these Data Toggling algorithms.

Unlock Bypass (PSD833F2x, PSD834F2x, PSD853F2x, PSD854F2x)

The Unlock Bypass instructions allow the system to program bytes to the Flash memories faster than using the standard Program instruction. The Unlock Bypass mode is entered by first initiating two Unlock cycles. This is followed by a third WRITE cycle containing the Unlock Bypass code, 20h (as shown in Table 9., page 21).

The Flash memory then enters the Unlock Bypass mode. A two-cycle Unlock Bypass Program instruction is all that is required to program in this mode. The first cycle in this instruction contains the Unlock Bypass Program code, A0h. The second cycle contains the program address and data. Additional data is programmed in the same manner. These instructions dispense with the initial two Unlock cycles required in the standard Program instruction, resulting in faster total Flash memory programming.

During the Unlock Bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset Flash instructions are valid.

To exit the Unlock Bypass mode, the system must issue the two-cycle Unlock Bypass Reset Flash instruction. The first cycle must contain the data 90h; the second cycle the data 00h. Addresses are Don’t Care for both cycles. The Flash memory then returns to READ Mode.

Figure 8. Data Toggle Flowchart

	START
	READ
	DQ5 & DQ6
	DQ6	NO
	=
	TOGGLE
	YES
NO	DQ5
	= 1
	YES
	READ DQ6
	DQ6	NO
	=
	TOGGLE
	YES
	FAIL	PASS
		AI01370B

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ERASING FLASH MEMORY

Flash Bulk Erase

The Flash Bulk Erase instruction uses six WRITE operations followed by a READ operation of the status register, as described in Table 9., page 21. If any byte of the Bulk Erase instruction is wrong, the Bulk Erase instruction aborts and the device is reset to the Read Flash memory status.

During a Bulk Erase, the memory status may be checked by reading the Error Flag Bit (DQ5), the Toggle Flag Bit (DQ6), and the Data Polling Flag Bit (DQ7), as detailed in the section entitled PROGRAMMING FLASH MEMORY, page 25. The Error Flag Bit (DQ5) returns a '1' if there has been an Erase Failure (maximum number of Erase cycles have been executed).

It is not necessary to program the memory with 00h because the PSD automatically does this before erasing to 0FFh.

During execution of the Bulk Erase instruction, the Flash memory does not accept any instructions.

Flash Sector Erase

The Sector Erase instruction uses six WRITE operations, as described in Table 9., page 21. Additional Flash Sector Erase codes and Flash memory sector addresses can be written subsequently to erase other Flash memory sectors in parallel, without further coded cycles, if the additional bytes are transmitted in a shorter time than the time-out period of about 100µs. The input of a new Sector Erase code restarts the time-out period.

The status of the internal timer can be monitored through the level of the Erase Time-out Flag Bit (DQ3). If the Erase Time-out Flag Bit (DQ3) is ’0,’ the Sector Erase instruction has been received and the time-out period is counting. If the Erase Time-out Flag Bit (DQ3) is '1,' the time-out period has expired and the PSD is busy erasing the Flash memory sector(s). Before and during Erase timeout, any instruction other than Suspend Sector Erase and Resume Sector Erase instructions abort the cycle that is currently in progress, and reset the device to READ Mode. It is not necessary to program the Flash memory sector with 00h as the PSD does this automatically before erasing (byte = FFh).

During a Sector Erase, the memory status may be checked by reading the Error Flag Bit (DQ5), the Toggle Flag Bit (DQ6), and the Data Polling Flag Bit (DQ7), as detailed in the section entitled PROGRAMMING FLASH MEMORY, page 25.

During execution of the Erase cycle, the Flash memory accepts only Reset and Suspend Sector Erase instructions. Erasure of one Flash memory sector may be suspended, in order to read data from another Flash memory sector, and then resumed.

Suspend Sector Erase

When a Sector Erase cycle is in progress, the Suspend Sector Erase instruction can be used to suspend the cycle by writing 0B0h to any address when an appropriate Sector Select (FS0-FS7 or CSBOOT0-CSBOOT3) is High. (See Table 9., page 21). This allows reading of data from another Flash memory sector after the Erase cycle has been suspended. Suspend Sector Erase is accepted only during an Erase cycle and defaults to READ Mode. A Suspend Sector Erase instruction executed during an Erase time-out period, in addition to suspending the Erase cycle, terminates the time out period.

The Toggle Flag Bit (DQ6) stops toggling when the PSD internal logic is suspended. The status of this bit must be monitored at an address within the Flash memory sector being erased. The Toggle Flag Bit (DQ6) stops toggling between 0.1µs and 15µs after the Suspend Sector Erase instruction has been executed. The PSD is then automatically set to READ Mode.

If an Suspend Sector Erase instruction was executed, the following rules apply:

–Attempting to read from a Flash memory sector that was being erased outputs invalid data.

–Reading from a Flash sector that was not being erased is valid.

–The Flash memory cannot be programmed, and only responds to Resume Sector Erase and Reset Flash instructions (READ is an operation and is allowed).

–If a Reset Flash instruction is received, data in the Flash memory sector that was being erased is invalid.

Resume Sector Erase

If a Suspend Sector Erase instruction was previously executed, the erase cycle may be resumed with this instruction. The Resume Sector Erase instruction consists of writing 030h to any address while an appropriate Sector Select (FS0-FS7 or CSBOOT0-CSBOOT3) is High. (See Table 9., page 21.)

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SPECIFIC FEATURES

Flash Memory Sector Protect

Each primary and secondary Flash memory sector can be separately protected against Program and Erase cycles. Sector Protection provides additional data security because it disables all Program or Erase cycles. This mode can be activated through the JTAG Port or a Device Programmer.

Sector protection can be selected for each sector using the PSDsoft Express Configuration program. This automatically protects selected sectors when the device is programmed through the JTAG Port or a Device Programmer. Flash memory sectors can be unprotected to allow updating of their contents using the JTAG Port or a Device Programmer. The MCU can read (but cannot change) the sector protection bits.

Any attempt to program or erase a protected Flash memory sector is ignored by the device. The Verify operation results in a READ of the protected data. This allows a guarantee of the retention of the Protection status.

The sector protection status can be read by the MCU through the Flash memory protection and PSD/EE protection registers (in the CSIOP block). See Tables 11 and 12.

Reset Flash

The Reset Flash instruction consists of one WRITE cycle (see Table 9., page 21). It can also be optionally preceded by the standard two WRITE decoding cycles (writing AAh to 555h and 55h to AAAh). It must be executed after:

–Reading the Flash Protection Status or Flash ID

–An Error condition has occurred (and the device has set the Error Flag Bit (DQ5) to '1') during a Flash memory Program or Erase cycle.

On the PSD813F2/3/4/5, the Reset Flash instruction puts the Flash memory back into normal READ Mode. It may take the Flash memory up to a few milliseconds to complete the Reset cycle. The Reset Flash instruction is ignored when it is issued during a Program or Bulk Erase cycle of the Flash memory. The Reset Flash instruction aborts any on-going Sector Erase cycle, and returns the Flash memory to the normal READ Mode within a few milliseconds.

On the PSD83xF2 or PSD85xF2, the Reset Flash instruction puts the Flash memory back into normal READ Mode. If an Error condition has occurred (and the device has set the Error Flag Bit (DQ5) to '1') the Flash memory is put back into normal READ Mode within 25 s of the Reset Flash instruction having been issued. The Reset Flash instruction is ignored when it is issued during a Program or Bulk Erase cycle of the Flash memory. The Reset Flash instruction aborts any on-going Sector Erase cycle, and returns the Flash memory to the normal READ Mode within 25 s.

Reset (RESET) Signal (on the PSD83xF2 and

PSD85xF2)

A pulse on Reset (RESET) aborts any cycle that is in progress, and resets the Flash memory to the READ Mode. When the reset occurs during a Program or Erase cycle, the Flash memory takes up to 25 s to return to the READ Mode. It is recommended that the Reset (RESET) pulse (except for Power On Reset, as described on RESET TIMING AND DEVICE STATUS AT RESET, page 67) be at least 25 s so that the Flash memory is always ready for the MCU to fetch the bootstrap instructions after the Reset cycle is complete.

Table 11. Sector Protection/Security Bit Definition – Flash Protection Register

Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0
Sec7_Prot	Sec6_Prot	Sec5_Prot	Sec4_Prot	Sec3_Prot	Sec2_Prot	Sec1_Prot	Sec0_Prot

Note: 1. Bit Definitions:

Sec<i>_Prot 1 = Primary Flash memory or secondary Flash memory Sector <i> is write protected. Sec<i>_Prot 0 = Primary Flash memory or secondary Flash memory Sector <i> is not write protected.

Table 12. Sector Protection/Security Bit Definition – PSD/EE Protection Register

Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0
Security_Bit	not used	not used	not used	Sec3_Prot	Sec2_Prot	Sec1_Prot	Sec0_Prot

Note: 1. Bit Definitions:

Sec<i>_Prot 1 = Secondary Flash memory Sector <i> is write protected. Sec<i>_Prot 0 = Secondary Flash memory Sector <i> is not write protected. Security_Bit 0 = Security Bit in device has not been set.

1 = Security Bit in device has been set.

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PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

SRAM

The SRAM is enabled when SRAM Select (RS0) from the DPLD is High. SRAM Select (RS0) can contain up to two product terms, allowing flexible memory mapping.

The SRAM can be backed up using an external battery. The external battery should be connected

to Voltage Stand-by (VSTBY, PC2). If you have an external battery connected to the PSD, the con-

tents of the SRAM are retained in the event of a power loss. The contents of the SRAM are retained so long as the battery voltage remains at 2 V or greater. If the supply voltage falls below the battery voltage, an internal power switch-over to the battery occurs.

PC4 can be configured as an output that indicates when power is being drawn from the external battery. Battery-on Indicator (VBATON, PC4) is High with the supply voltage falls below the battery volt-

age and the battery on Voltage Stand-by (VSTBY, PC2) is supplying power to the internal SRAM.

SRAM Select (RS0), Voltage Stand-by (VSTBY, PC2) and Battery-on Indicator (VBATON, PC4) are all configured using PSDsoft Express Configuration.

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PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

SECTOR SELECT AND SRAM SELECT

Sector Select (FS0-FS7, CSBOOT0-CSBOOT3) and SRAM Select (RS0) are all outputs of the DPLD. They are setup by writing equations for them in PSDabel. The following rules apply to the equations for these signals:

1.Primary Flash memory and secondary Flash memory Sector Select signals must not be larger than the physical sector size.

2.Any primary Flash memory sector must not be mapped in the same memory space as another Flash memory sector.

3.A secondary Flash memory sector must not be mapped in the same memory space as another secondary Flash memory sector.

4.SRAM, I/O, and Peripheral I/O spaces must not overlap.

5.A secondary Flash memory sector may overlap a primary Flash memory sector. In case of overlap, priority is given to the secondary Flash memory sector.

6.SRAM, I/O, and Peripheral I/O spaces may overlap any other memory sector. Priority is given to the SRAM, I/O, or Peripheral I/O.

Example

FS0 is valid when the address is in the range of 8000h to BFFFh, CSBOOT0 is valid from 8000h to 9FFFh, and RS0 is valid from 8000h to 87FFh. Any address in the range of RS0 always accesses the SRAM. Any address in the range of CSBOOT0 greater than 87FFh (and less than 9FFFh) automatically addresses secondary Flash memory segment 0. Any address greater than 9FFFh accesses the primary Flash memory segment 0. You can see that half of the primary Flash memory segment 0 and one-fourth of secondary Flash memory segment 0 cannot be accessed in this example. Also note that an equation that defined FS1 to anywhere in the range of 8000h to BFFFh would not be valid.

Figure 9 shows the priority levels for all memory components. Any component on a higher level can overlap and has priority over any component on a lower level. Components on the same level must not overlap. Level one has the highest priority and level 3 has the lowest.

Memory Select Configuration for MCUs with Separate Program and Data Spaces

The 8031 and compatible family of MCUs, which includes the 80C51, 80C151, 80C251, and 80C51XA, have separate address spaces for Program memory (selected using Program Select Enable (PSEN, CNTL2)) and Data memory (selected using Read Strobe (RD, CNTL1)). Any of the memories within the PSD can reside in either space or both spaces.

This is controlled through manipulation of the VM register that resides in the CSIOP space.

The VM register is set using PSDsoft Express to have an initial value. It can subsequently be changed by the MCU so that memory mapping can be changed on-the-fly.

For example, you may wish to have SRAM and primary Flash memory in the Data space at Boot-up, and secondary Flash memory in the Program space at Boot-up, and later swap the primary and secondary Flash memories. This is easily done with the VM register by using PSDsoft Express Configuration to configure it for Boot-up and having the MCU change it when desired. Table 13., page 31 describes the VM Register.

Figure 9. Priority Level of Memory and I/O

Components

Highest Priority

Level 1

SRAM, I/O, or

Peripheral I/O

Level 2

Secondary

Non-Volatile Memory

Level 3

Primary Flash Memory

Lowest Priority

AI02867D

Configuration Modes for MCUs with Separate Program and Data Spaces

Separate Space Modes. Program space is separated from Data space. For example, Program Select Enable (PSEN, CNTL2) is used to access the program code from the primary Flash memory, while Read Strobe (RD, CNTL1) is used to access data from the secondary Flash memory, SRAM and I/O Port blocks. This configuration requires the VM register to be set to 0Ch (see Figure 10., page 31).

Combined Space Modes. The Program and Data spaces are combined into one memory space that allows the primary Flash memory, secondary Flash memory, and SRAM to be accessed by either Program Select Enable (PSEN, CNTL2) or Read Strobe (RD, CNTL1). For example, to configure the primary Flash memory in Combined space, Bits b2 and b4 of the VM register are set to '1' (seeFigure 11., page 31).

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