ST PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 User Manual

Download

查询PSD813F3V-12J供应商

PSD834F2, PSD853F2, PSD854F2

FEAT URES SUM MARY

■ FLASH IN-SYSTEM PR OGRAMMABLE (ISP)

PERIPHERAL FOR 8-BIT MCUS

■ DUAL BANK FLASH MEMO RI ES

– UP TO 2 Mbit O F PR I MARY F L A SH

MEMORY (8 Uniform Sectors, 32K x8)

– UP TO 256 Kbit SECONDARY FLASH

MEMORY (4 Uniform Sectors)

– Concurrent operation: READ from one

memory while erasing and writing the other

■ UP TO 256 Kbit BATTERY-B ACKED SR AM

■ 27 RECONFIGURABLE I/O PORTS

■ ENHANCED JTAG SERIAL PORT

■ PLD WITH MACROCELLS

– Over 3000 Gates of PLD: CPLD and

DPLD

– CPLD with 16 Output Macrocells (OMCs)

and 24 Input Macrocells (IMCs)

– DPLD - user defined internal chip select

decoding

■ 27 INDIVIDUALLY CONFIGURABLE I/O

PORT PINS The can be used for the following functions: – MCU I/Os –PLD I/Os – Latched MCU address output – Special function I/Os. – 16 of the I/O ports may be configured as

open-drain outputs.

■ IN-SYSTEM PROGRAMMING (ISP) WITH

JTAG – Built-in JTAG compliant serial port allows

full-chip In-System Programmability

– Efficient manufacturing allow easy

product testing and programming

– Use low cost FlashLINK cable with PC

■ PAGE REGISTER

– Internal page register that can be used to

expand the microcontroller address space by a factor of 256

■ PROGRAMMABLE POWER MAN AGEMENT

PSD813F2, PSD833F2

Flash In-System Programmable (ISP)

Perip herals for 8-bit MCUs, 5V

PRELIMINARY DATA

Figure 1. Packages

PQFP52 (M)

PLCC52 (J)

TQFP64 (U)

■ HIGH ENDURANCE:

– 100,000 Erase/WRITE Cycles of Flash

Memory – 1,000 Erase/WRITE Cycles of PLD – 15 Year Data Retention

■ 5V±10% SINGLE SUPPLY VOLTAGE

■ STANDBY CURRENT AS LOW AS 50µA

June 2004

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

1/110

PSD813F2, PSD833F2, PSD834F 2, PSD853F2, PSD854F2

TABLE OF CONTENTS

FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

PSD ARCHITECTURAL OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Page Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

PLDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

MCU Bus Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

JTAG Port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

In-System Programming (ISP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

Power Management Unit (PMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

DEVELOPMENT SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 7

PSD Register Description and Address Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

DETAILED OPERATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Memory Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Primary Flash Memo ry and Seco nd ary Flash memo ry Description. . . . . . . . . . . . . . . . . . . . . 20

Memory Block Select Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Power-up Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Read Memory Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Read Primary Flash Identifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Read Memory Sector Protection Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Reading the Erase/Program Status Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Data Polling Flag (DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Toggle Flag (DQ6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Error Flag (DQ5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Erase Time-out Flag (DQ3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4

PROGRAMMING FLASH MEMORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Data Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Data Toggle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6

Unlock Bypass (PSD833 F2x, PSD834F2x, PSD853F2x, PSD854 F2x) . . . . . . . . . . . . . . . . . . . . 26

ERASING FLASH MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Flash Bulk Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

2/110

PSD813F2, PSD833F2, PS D834F2, PSD853F2, PSD854F2

Flash Sector Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 7

Suspend Sector Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 7

Resume Sector Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

SPECIFIC FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 8

Flash Memory Sector Protect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Reset Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Reset (RESET) Signal (on the PSD83xF2 and PSD85xF2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

SECTOR SELECT AND SRAM SELECT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 0

Memory Selec t Co nfig ur atio n fo r MCUs w it h Sepa r a t e Progr a m a n d D a t a Spaces . . . . . . . . 30

Configuration Modes for MCUs with Separate Program and Data Spaces . . . . . . . . . . . . . . . 30

PAGE REGISTER. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2

PLDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

The Turbo Bit in PSD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Decode PLD (DPLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Complex PLD (CPLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Output Macrocell (OMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 7

Product Term Allocator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Loading and Reading the Output Macrocells (OMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

The OMC Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

The Output Enable of the OMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

Input Macrocells (IMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

MCU BUS INTERFACE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

PSD Interface to a Multiplexed 8-Bit Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

PSD Interface to a Non-Multiplexed 8-Bit Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Data Byte Enable Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

MCU Bus Interface Examples. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

80C31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

80C251 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 7

80C51XA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

68HC11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

I/O PORTS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

General Port Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Port Operating Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

MCU I/O Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

PLD I/O Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Address Out Mod e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Address In Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

3/110

PSD813F2, PSD833F2, PSD834F 2, PSD853F2, PSD854F2

Data Port Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Peripheral I/O Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

JTAG In-System Programming (ISP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Port Configuration Registers (PCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Direction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Drive Select Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Port Data Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Data In. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Data Out Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

OMC Mask Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Input Macrocells (IMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Enable Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Ports A and B – Functionality and Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Port C – Functionality and Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Port D – Functionality and Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

External Chip Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

POWER MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Automatic Power-down (APD) Unit and Power-down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

For Users of the HC11 (or compatible) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Other Power Saving Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

PLD Power Management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

PSD Chip Select Input (CSI, PD2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66

Input Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 6

Input Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

RESET TIMING AND DEVICE STATUS AT RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Power-Up Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Warm Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

I/O Pin, Register and PLD Status at Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Reset of Flash Memory Erase and Program Cycle s (on the PSD834Fx) . . . . . . . . . . . . . . . . . 67

PROGRAMMING IN-CIRCUIT USING THE JTAG SERIAL INTERFACE . . . . . . . . . . . . . . . . . . . . . . 69

Standard JTAG Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 9

JTAG Extensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Security and Flash memory Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

INITIAL DELIVERY STATE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

AC/DC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

4/110

PSD813F2, PSD833F2, PS D834F2, PSD853F2, PSD854F2

PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

APPENDIX A.PQFP52 PIN ASSIGNMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

APPENDIX B.PLCC52 PIN ASSIGNMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

APPENDIX C.TQFP64 PIN ASSIGNMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

5/110

PSD813F2, PSD833F2, PSD834F 2, PSD853F2, PSD854F2

SUMMARY DESCRIPT IO N

The PSD8XXFX family of memory systems for microcontrollers (MCUs) brings In-System-Programmability (ISP) to Flash memory and programmable logic. The result is a simple and flexible solution for embedded designs. PSD devices combine many of the peripheral functions found in MCU based applications.

Table 1 summarizes all the devices in the PSD834F2, PSD853F2, PSD854F2.

The CPLD in the PSD devices features an optimized macrocell logic architecture. The PSD macrocell was created to address the unique requirements of embedded system designs. It allows direct connection between the system address/data bus, and the internal PSD registers, to simplify communication between the MCU and other supporting devices.

The PSD device includes a JTAG Serial Programming interface, to allow In-System P rogramming (ISP) of the entire device. This feature reduces de- velopment time, simplifies the manufacturing flow, and dramatically lowers the cost of field upgrades. Using ST’s special Fast-JTAG programming, a design can be rapidly programmed into the PSD in as little as seven seconds.

The innovative PSD8XXFX family solves key problems faced by designers when managing discrete Flash memory devices, such as:

– First-time In-System Programming (ISP) – Complex address decoding – Simultaneous read and write to the device. The JTAG Serial Interface block allows In-System

Programming (ISP), and elimi nates the need for an external Boot EPROM, or an external programmer. To simplify Flash memory updates, program execution is performed from a secondary Flash memory while the primary Flash memory is being updated. This solution avoids the complicated hardware and software overhead necessary to implement IAP.

ST makes available a software developm ent tool, PSDsoft Express, that generates ANSI-C com pliant code for use with your target M CU. T his c ode allows you to manipulate the non-volatile me mory (NVM) within the PSD. Code examples are also provided for:

– Flash memory IAP via the UART of the host

MCU

– Memory paging to execute code ac ross

several PSD memory pages

– Loading, reading, and manipulati on of PSD

macrocells by the MCU.

Tabl e 1. Product Range

Primary Flash

Part Number

PSD813F2 1 Mbit 256 Kbit 16 Kbit 27 24 16 yes yes PSD813F3 1 Mbit none 16 Kbit 27 24 16 yes yes PSD813F4 1 Mbit 256 Kbit none 27 24 16 yes yes PSD813F5 1 Mbit none none 27 24 16 yes yes PSD833F2 1 Mbit 256 Kbit 64 Kbit 27 24 16 yes yes PSD834F2 2 Mbit 256 Kbit 64 Kbit 27 24 16 yes yes PSD853F2 1 Mbit 256 Kbit 256 Kbit 27 24 16 yes yes PSD854F2 2 Mbit 256 Kbit 256 Kbit 27 24 16 yes yes

Note: 1. All produ cts supp ort: JTAG se rial IS P, MCU para llel ISP , ISP Flash m emory , ISP CPLD, Security featur es, Power M anagem ent

2. SRAM may be backed up usin g an external battery.

(1)

Unit (PMU ), Automat i c Power-down (APD)

Memory

(8 Sectors)

Secondary

Flash Memory

4 Sectors)

SRAM

(2)

I/O Ports

Number of

Macrocells

Input Output

Serial

ISP

JTAG/

ISC Port

Turbo

Mode

6/110

Figure 2. PQFP52 Connections

PD2

PD1

PD0

PC7

PC6

PC5

PC4

GND

PC3

PC2

PC1

PC0

PSD813F2, PSD833F2, PS D834F2, PSD853F2, PSD854F2

PB0

PB1

PB2

PB3

PB4

PB5

GND

PB6

PB7

CNTL1

CNTL2

RESET

CNTLO

52515049484746454443424140

39 AD15 38 AD14 37 AD13 36 AD12 35 AD11 34 AD10 33 AD9 32 AD8 31 V

30 AD7 29 AD6 28 AD5 27 AD4

14151617181920212223242526

PA7

PA6

PA5

PA4

PA3

PA2

PA1

PA0

AD0

AD1

AD2

GND

AD3

AI02858

7/110

PSD813F2, PSD833F2, PSD834F 2, PSD853F2, PSD854F2

Figure 3. PLC C5 2 C o nnections

PD2

PD1

PD0

PC7

PC6

PC5

PC4

GND

PC3

PC2

PC1 PC0

PB0

PB1

PB2

PB3

PB4

PB5

GND

PB6

PB7

CNTL1

19 20

21222324252627282930313233

CNTL2

RESET

CNTL0

35 34

AD15

AD14

AD13

AD12

AD11

AD10

AD9

AD8

AD7

AD6

AD5 AD4

PA7

PA6

PA5

PA4

PA3

GND

PA2

PA1

PA0

AD0

AD1

AD2

AD3

AI02857

8/110

Figure 4. TQ FP 64 Connection s

PSD813F2, PSD833F2, PS D834F2, PSD853F2, PSD854F2

PD2 PD1 PD0 PC7 PC6 PC5 V

GND GND PC3 PC2 PC1 PC0 NC

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

NCNCPB0 646362616059585756555453525150

171819202122232425262728293031 NC

PA7

PB1

PA6

PB2

PA5

PB3

PA4

PB4

PA3

PB5

GND

PA2

PB6

PA1

PB7

PA0

CNTL1

CNTL2

AD0

AD1NDAD2

RESET

NC 49

48 CNTL0 47 AD15 46 AD14 45 AD13 44 AD12 43 AD11 42 AD10 41 AD9 40 AD8 39 V

38 V

37 AD7 36 AD6 35 AD5 34 AD4 33 AD3

AI09645

9/110

PSD813F2, PSD833F2, PSD834F 2, PSD853F2, PSD854F2

PIN DES CRIPTION

Table 2. Pin Description (for the PLCC52 package - Note 1)

Pin Name Pin Type Description

This is the lower Address/Data port. Connect your MCU address or address/data bus according to the following rules: If your MCU has a multiplexed address/data bus where the data is multiplexed with the lower address bits, connect AD0-AD7 to this port.

ADIO0-7 30-37 I/O

ADIO8-15 39-46 I/O

CNTL0 47 I

If your MCU does not have a multiplexed address/data bus, or you are using an 80C251 in page mode, connect A0-A7 to this port.

If you are using an 80C51XA in burst mode, connect A4/D0 through A11/D7 to this port. ALE or AS latches the address. The PSD drives data out only if the READ signal is active

and one of the PSD functional blocks was selected. The addresses on this port are passed to the PLDs.

This is the upper Address/Data port. Connect your MCU address or address/data bus according to the following rules: If your MCU has a multiplexed address/data bus where the data is multiplexed with the lower address bits, connect A8-A15 to this port.

If your MCU does not have a multiplexed address/data bus, connect A8-A15 to this port. If you are using an 80C251 in page mode, connect AD8-AD15 to this port. If you are using an 80C51XA in burst mode, connect A12/D8 through A19/D15 to this

port. ALE or AS latches the address. The PSD drives data out only if the READ signal is active

and one of the PSD functional blocks was selected. The addresses on this port are passed to the PLDs.

The following control signals can be connected to this port, based on your MCU:

– active Low Write Strobe input.

– active High READ/active Low write input.

R_W

CNTL1 50 I

CNTL2 49 I

10/110

This port is connected to the PLDs. Therefore, these signals can be used in decode and other logic equations.

The following control signals can be connected to this port, based on your MCU:

– active Low Read Strobe input.

RD E – E clock input. DS – active Low Data Strobe input.

– connect PSEN to this port when it is being used as an active Low READ signal.

PSEN For example, when the 80C251 outputs more than 16 address bits, PSEN READ signal.

This port is connected to the PLDs. Therefore, these signals can be used in decode and other logic equations.

This port can be used to input the PSEN that uses this signal for code exclusively. If your MCU does not output a Program Select Enable signal, this port can be used as a generic input. This port is connected to the PLDs.

(Program Select Enable) signal from any MCU

is actually the

PSD813F2, PSD833F2, PS D834F2, PSD853F2, PSD854F2

Pin Name Pin Type Description

Reset 48 I

Resets I/O Ports, PLD macrocells and some of the Configuration Registers. Must be Low at Power-up.

These pins make up Port A. These port pins are configurable and can have the following functions: MCU I/O – write to or read from a standard output or input port.

CPLD macrocell (McellAB0-7) outputs.

PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7

PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7

29 28 27 25 24 23 22 21

52 51

Inputs to the PLDs. Latched address outputs (see Table 6).

I/O

Address inputs. For example, PA0-3 could be used for A0-A3 when using an 80C51XA in burst mode.

As the data bus inputs D0-D7 for non-multiplexed address/data bus MCUs. D0/A16-D3/A19 in M37702M2 mode. Peripheral I/O mode. Note: PA0-P A3 can only output CMOS signals with an option for high slew rate. However,

PA4-PA7 can be configured as CMOS or Open Drain Outputs. These pins make up Port B. These port pins are configurable and can have the following

functions:

MCU I/O – write to or read from a standard output or input port. 6 5 4 3

CPLD macrocell (McellAB0-7 or McellBC0-7) outputs.

I/O

Inputs to the PLDs. 2

Latched address outputs (see Table 6).

Note: PB0-PB3 can only output CMOS signals with an option for high slew rate.

However, PB4-PB7 can be configured as CMOS or Open Drain Outputs.

PC0 pin of Port C. This port pin can be configured to have the following functions:

MCU I/O – write to or read from a standard output or input port.

PC0 20 I/O

PC1 19 I/O

CPLD macrocell (McellBC0) output.

Input to the PLDs.

TMS Input

for the JTAG Serial Interface.

This pin can be configured as a CMOS or Open Drain output.

PC1 pin of Port C. This port pin can be configured to have the following functions:

MCU I/O – write to or read from a standard output or input port.

CPLD macrocell (McellBC1) output.

Input to the PLDs.

TCK Input

for the JTAG Serial Interface.

This pin can be configured as a CMOS or Open Drain output.

11/110

PSD813F2, PSD833F2, PSD834F 2, PSD853F2, PSD854F2

Pin Name Pin Type Description

PC2 pin of Port C. This port pin can be configured to have the following functions:

MCU I/O – write to or read from a standard output or input port.

CPLD macrocell (McellBC2) output.

PC2 18 I/O

Input to the PLDs.

– SRAM stand-by voltage input for SRAM battery backup.

STBY

This pin can be configured as a CMOS or Open Drain output.

PC3 pin of Port C. This port pin can be configured to have the following functions:

MCU I/O – write to or read from a standard output or input port.

CPLD macrocell (McellBC3) output.

PC3 17 I/O

PC4 14 I/O

PC5 13 I/O

Input to the PLDs.

TSTAT

output2 for the JTAG Serial Interface.

Ready/Busy

output for parallel In-System Programming (ISP).

This pin can be configured as a CMOS or Open Drain output.

PC4 pin of Port C. This port pin can be configured to have the following functions:

MCU I/O – write to or read from a standard output or input port.

CPLD macrocell (McellBC4) output.

Input to the PLDs.

output2 for the JTAG Serial Interface.

TERR

Battery-on Indicator (V

). Goes High when power is being drawn from the external

BATON

battery.

This pin can be configured as a CMOS or Open Drain output.

PC5 pin of Port C. This port pin can be configured to have the following functions:

MCU I/O – write to or read from a standard output or input port.

CPLD macrocell (McellBC5) output.

Input to the PLDs.

TDI input

for the JTAG Serial Interface.

PC6 12 I/O

12/110

This pin can be configured as a CMOS or Open Drain output.

PC6 pin of Port C. This port pin can be configured to have the following functions:

MCU I/O – write to or read from a standard output or input port.

CPLD macrocell (McellBC6) output.

Input to the PLDs.

TDO output

for the JTAG Serial Interface.

This pin can be configured as a CMOS or Open Drain output.

PSD813F2, PSD833F2, PS D834F2, PSD853F2, PSD854F2

Pin Name Pin Type Description

PC7 pin of Port C. This port pin can be configured to have the following functions:

MCU I/O – write to or read from a standard output or input port.

CPLD macrocell (McellBC7) output.

PC7 11 I/O

Input to the PLDs.

DBE – active Low Data Byte Enable input from 68HC912 type MCUs.

This pin can be configured as a CMOS or Open Drain output.

PD0 pin of Port D. This port pin can be configured to have the following functions:

ALE/AS input latches address output from the MCU.

PD0 10 I/O

MCU I/O – write or read from a standard output or input port.

Input to the PLDs.

CPLD output (External Chip Select).

PD1 pin of Port D. This port pin can be configured to have the following functions:

MCU I/O – write to or read from a standard output or input port.

Input to the PLDs.

PD1 9 I/O

CPLD output (External Chip Select).

CLKIN – clock input to the CPLD macrocells, the APD Unit’s Power-down counter, and

the CPLD AND Array.

PD2 pin of Port D. This port pin can be configured to have the following functions:

MCU I/O - write to or read from a standard output or input port.

Input to the PLDs.

PD2 8 I/O

CPLD output (External Chip Select).

PSD Chip Select Input (CSI

). When Low, the MCU can access the PSD memory and I/O.

When High, the PSD memory blocks are disabled to conserve power.

GND

Note: 1. The pin num bers in this table are for the PLCC package onl y. See the pack age informati on from Table 74., page 102 onwards, for

2. These funct i ons can be multi pl exed with ot her functi ons.

15, 38 Supply Voltage

1, 16,

pin numbers on other package types.

Ground pins

13/110

PSD813F2, PSD833F2, PSD834F 2, PSD853F2, PSD854F2

Figure 5. PSD Block Diagram

)

PC2

(

VSTDBY

PA0 – PA7

PB0 – PB7

PC0 – PC7

PD0 – PD2

ADDRESS/DATA/CONTROL BUS

UNIT

POWER

MANGMT

8 SECTORS

FLASH MEMORY

1 OR 2 MBIT PRIMARY

EMBEDDED

PAGE

256 KBIT SECONDARY

SECTOR

ALGORITHM

PORT

PROG.

4 SECTORS

(BOOT OR DATA)

NON-VOLATILE MEMORY

SELECTS

)

DPLD

(

PLD

FLASH DECODE

SECTOR

SELECTS

BACKUP SRAM

256 KBIT BATTERY

SRAM SELECT

PORT

RUNTIME CONTROL

AND I/O REGISTERS

PERIP I/O MODE SELECTS

CSIOP

PORT

PROG.

3 EXT CS TO PORT D

16 OUTPUT MACROCELLS

(CPLD)

FLASH ISP CPLD

PORT

PORT A ,B & C

24 INPUT MACROCELLS

CLKIN

PORT

PROG.

MACROCELL FEEDBACK OR PORT INPUT

CLKIN

PORT

PROG.

JTAG

SERIAL

& FLASH MEMORY

PLD, CONFIGURATION

CHANNEL

LOADER

14/110

PLD

BUS

INPUT

PROG.

CNTL0,

CNTL1,

INTRF.

MCU BUS

CNTL2

ADIO

PORT

AD0 – AD15

GLOBAL

SECURITY

CONFIG. &

CLKIN

(PD1)

AI02861E

PSD813F2, PSD833F2, PS D834F2, PSD853F2, PSD854F2

PSD ARCH ITECTURAL OVER VIEW

PSD devices contain several major functional blocks. Figu re 5 shows the architecture of the PSD device family. The functions of each block are described briefly in the following sections. Many of the blocks perform multiple functions and are user configurable.

Memory

Each of the memory blocks is briefly discussed in the following paragraphs. A more detail ed di scussion can be found in the section entitled Memory

Blocks, page 19.

The 1 Mbit or 2 Mbit (128K x 8, or 256K x 8) Flash memory is the primary memory of the PSD. It is divided into 8 equally-sized sectors that are individually selectable.

The optional 256 Kbit (32K x 8) secondary Flash memory is divided into 4 equally-sized sectors. Each sector is individually selectable.

The optional SRAM is intended for use as a scratch-pad memory or as an extension to the MCU SRAM. If an external battery is connected to Voltage Stand-by (V the event of power failure.

Each sector of mem ory can be located in a different address space as defined by the user. The access times for all memory types includes the address latching and DPLD decoding time.

Page Regis te r

The 8-bit Page Register expands the address range of the MCU by up to 256 times. The paged address can be used as part of the address space to access external memory and peripherals, or internal memory and I/O. The Page Register can also be used to change the address mapping of sectors of the Flash memories into different memory spaces for IAP.

PLDs

The device contains t wo PLDs, the Decode PLD (DPLD) and the Complex PLD (CPLD), as shown in Table 3, each op timized for a di fferent fun ction. The functional partitioning of the PLDs reduces power consumption, optimizes c ost/performance, and eases design entry.

, PC2), data is retained in

STBY

The DPLD is used to decode addresses and to generate Sector Select signals for the PSD internal memory and regis ters. The DPLD has combinatorial outputs. The CPLD has 16 Output Macrocells (OMC) and 3 combinatorial outputs. The PSD also has 24 Input Macrocells (IMC) that can be configured as inputs to the PLDs. The PLDs receive their inputs from the PLD Input Bus and are differentiated by their output destinations, number of product terms, and macrocells.

The PLDs consume minimal power. The speed and power consumption of the PLD i s controlled by the Turbo Bit in P MMR0 and other bi ts in the PMMR2. These registers are set by the MCU at run-time. There is a slight penalty to PLD propagation time when invoking the power m anagement features.

I/O Po rts

The PSD has 27 individually configurable I/O pins distributed over the four ports (Port A, B, C, and D). Each I/O pin can be individually configured for different functions. Ports can be configured as standard MCU I/O ports, PLD I/O, or latched address outputs for MCUs using multiplexed address/data buses.

The JTAG pins can be enabled o n Port C for InSystem Programming (ISP).

Ports A and B can also be conf igured as a data port for a non-multiplexed bus.

MCU Bus Interface

PSD interfaces easily with most 8-bit MCUs that have either multiplexed or non-multiplexed address/data buses. The device is configured to respond to the MCU’s control signals, which are also used as inputs to the PLDs. For examples, please see the section entitled MCU Bus Interface

Examples, page 45.

Table 3. PLD I/O

Name Inputs Outputs

Decode PLD (DPLD) 73 17 42 Complex PLD (CPLD) 73 19 140

Product

Terms

15/110

PSD813F2, PSD833F2, PSD834F 2, PSD853F2, PSD854F2

JTAG Port

In-System Programming (ISP) can be pe rformed through the JTAG signals on Port C. This serial interface allows complete programming of the entire PSD device. A blank device can be completely programmed. The JTAG signals (TMS, TCK, TSTAT

, TERR, TDI, TDO) can be multiplexed with other functions on Port C. Table 4 indicates the JTAG pin assignments.

In-Syst em Prog r a mming ( ISP)

Using the JTAG signals on Port C, the entire PSD device can be programmed or eras ed without the use of the MCU. The primary Flash memory can also be programmed in-system by the M CU executing the programming algorithms out of the secondary memory, or SRAM. The secondary memory can be programmed the same way by executing out of the primary Flash memory. The PLD or other PSD Configuration blocks can be programmed through the JTAG port or a de vice programmer. Table 5 indicates which programming methods can program different functional blocks of the PSD.

Power Management Unit (PMU)

The Power Management Unit (PMU) gives the user control of the power consumption on selected functional blocks based on system req uirements. The PMU includes an Automatic Power-down (APD) Unit that turns off device functions during

MCU inactivity. The APD Unit has a Power-down mode tha t help s reduce po wer c onsumption.

The PSD also has some bits that are configured at run-time by the MCU to reduce power consumption of the CPLD. The Turbo Bit in PMMR0 can be reset to '0' and the CPLD latches its outputs and goes to sleep until the next transition on its inputs.

Additionally, bits in PMMR2 can be set by the MCU to block signals from entering the CP LD to reduce power consumption. Please see t he section entitled POWER MANAGEMENT, page 62 for more details.

Table 4. JTAG SIgnals on Port C

Port C Pins JTAG Signal

PC0 TMS PC1 TCK PC3 TSTAT PC4 TERR PC5 TDI PC6 TDO

Table 5. Methods of Programming Different Functional Blocks of the PSD

Functional Block JTAG Programming Device Programmer IAP

Primary Flash Memory Yes Yes Yes Secondary Flash Memory Yes Yes Yes PLD Array (DPLD and CPLD) Yes Yes No PSD Configuration Yes Yes No

16/110

PSD813F2, PSD833F2, PS D834F2, PSD853F2, PSD854F2

DEVELOP MEN T SYSTEM

The PSD8XXFX family is supported by PSDsoft Express, a Windows-based software development tool. A PSD design is quickly and easily produced in a point and click environment. The designer does not need to enter Hardware Description Language (HDL) equations, unless des ired, to define PSD pin functions and memory map information. The general design flow is shown in Figure 6. PSDsoft Express is available from our web site (the address is given on the back page of this data sheet) or other distribution channels.

Figure 6. PSDsoft Express Development Tool

PSDabel

PLD DESCRIPTION

MODIFY ABEL TEMPLATE FILE

OR GENERATE NEW FILE

PSDsoft Express directly supports two low cost device programmers form ST: PSDpro and FlashLINK (JTAG). Both of these programmers may be purchased through your local distributor/ representative, or directly from our web site using a credit card. The PSD is also supported by third party device programmers. See our web site for the current list.

PSD Configuration

CONFIGURE MCU BUS

INTERFACE AND OTHER

PSD ATTRIBUTES

LOGIC SYNTHESIS

ADDRESS TRANSLATION

AND MEMORY MAPPING

PSD Simulator

PSDsilos III

DEVICE SIMULATION

(OPTIONAL)

PSD Fitter

AND FITTING

PSD Programmer

HEX OR S-RECORD

*.OBJ FILE

PSDPro, or

FlashLINK (JTAG)

FIRMWARE

FORMAT

PSD TOOLS

GENERATE C CODE

SPECIFIC TO PSD

FUNCTIONS

USER'S CHOICE OF

MICROCONTROLLER

COMPILER/LINKER

*.OBJ AND *.SVF

FILES AVAILABLE

FOR 3rd PARTY

PROGRAMMERS

(CONVENTIONAL or

JTAG-ISC)

AI04918

17/110

PSD813F2, PSD833F2, PSD834F 2, PSD853F2, PSD854F2

PSD REGI STER DESCRIPTION AND ADDRE SS OFFSET

Table 6 shows t he offset addresses to the PSD registers relative to the CSIOP base address. The CSIOP space is the 256 bytes of address that is allocated by the user to the internal PSD regist ers.

Table 6. I/O Port Latched Address Output Assignments (Note1)

MCU

8051XA (8-bit) N/A Address a7-a4 Address a11-a8 N/A 80C251 (page mode) N/A N/A Address a11-a8 Address a15-a12 All other 8-bit multiplexed Address a3-a0 Address a7-a4 Address a3-a0 Address a7-a4 8-bit non-multiplexed bus N/A N/A Address a3-a0 Address a7-a4

Note: 1. See the se ct i on entitled I/O PORTS, page 51, on how to enabl e the Latched A d dress Output function.

2. N/A = Not Applicable

Port A (3:0) Port A (7:4) Port B (3:0) Port B (7:4)

Port A Port B

Table 7. Register Address Offset

Data In 00 01 10 11 Reads Port pin as input, MCU I/O input mode Control 02 03 Selects mode between MCU I/O or Address Out

Data Out 04 05 12 13 Direction 06 07 14 15 Configures Port pin as input or output

Drive Select 08 09 16 17

Input Macrocell 0A 0B 18 Reads Input Macrocells Enable Out 0C 0D 1A 1B Output Macrocells

AB Output Macrocells

BC Mask Macrocells AB 22 22 Blocks writing to the Output Macrocells AB Mask Macrocells BC 23 23 Blocks writing to the Output Macrocells BC Primary Flash

Protection Secondary Flash

memory Protection JTAG Enable C7 Enables JTAG Port PMMR0 B0 Power Management Register 0 PMMR2 B4 Power Management Register 2 Page E0 Page Register

VM E2

Note: 1. Other registers that are not part of the I/O ports .

20 20

21 21

Table 7 provides brief descriptions of the registers in CSIOP space. The following section gives a more detailed description.

Other

Stores data for output to Port pins, MCU I/O output mode

Configures Port pins as either CMOS or Open Drain on some pins, while selecting high slew rate on other pins.

Reads the status of the output enable to the I/O Port driver

READ – reads output of macrocells AB WRITE – loads macrocell flip-flops

READ – reads output of macrocells BC WRITE – loads macrocell flip-flops

C0 Read only – Primary Flash Sector Protection

Read only – PSD Security and Secondary Flash memory Sector Protection

Places PSD memory areas in Program and/or Data space on an individual basis.

Description

18/110

PSD813F2, PSD833F2, PS D834F2, PSD853F2, PSD854F2

DETAILED OPERATION

As shown in Figure 5., page 14 , the PS D consi s ts of six major types of functional blocks:

■ Memory Blocks

■ PLD Blocks

■ MCU Bus Interface

■ I/O Ports

■ Power Management Unit (PMU)

■ JTAG Interface

The functions of ea ch block are described in t he following sections. Many of the blocks perform multiple functions, and are user configurable.

Table 8. Memory Block Siz e and Organizati on

Primary Flash Memory Secondary Flash Memory SRAM

Sector

Number

0 32K FS0 16K CSBOOT0 256K RS0 1 32K FS1 16K CSBOOT1 2 32K FS2 16K CSBOOT2

Sector Size

(Bytes)

Sector Select

Signal

Sector Size

Memory Blocks

The PSD has the following memory blocks: – Primary Flash memory – Optional Secondary Flash memory – Optional SRAM The Memory Select signals for these blocks origi-

nate from the Decode PLD (DPLD) an d are userdefined in PSDsoft Express.

(Bytes)

Sector Select

Signal

SRAM Size

(Bytes)

SRAM Select

Signal

3 32K FS3 16K CSBOOT3 4 32K FS4 5 32K FS5 6 32K FS6 7 32K FS7

Total 512K 8 Sectors 64K 4 Sectors 256K

19/110

PSD813F2, PSD833F2, PSD834F 2, PSD853F2, PSD854F2

Primary Flash Memory and Secon dary F lash memory Description

The primary Flash memory is divided evenly into eight equal sectors. The secondary Flash memory is divided into four e qual sectors. Each sector of either memory block can be sepa rately protected from Program and Erase cycles.

Flash memory may be erased on a sector-by-sector basis. Flash sector erasure may be suspended while data is read from other sectors of the block and then resumed after reading.

During a Program or Erase cycle in Flash memory, the status can be output on Ready/Busy

(PC3). This pin is set up using PSDsoft Express Configuration.

Memory Block Select Signals

The DPLD generates the Select signals for all the internal memory blocks (see the section entitled

PLDS, page 33). Each of the eight sectors of the

primary Flash memory has a Select signa l (FS0FS7) which can contain up to three product terms. Each of the four sectors of the secondary Flash memory has a Select signal (CSBOOT0CSBOOT3) which can contain up to three product terms. Having three product terms for each Select signal allows a given sector to be mapped in different areas of system memory. When using a MCU with separate Program and Data space, these flexible Select signals allow dynamic re-mapping of sectors from one memory space to the other.

Ready/Busy

output the Ready/Busy put on Ready/Busy

(PC3 ). This signal can be used to

status of the PSD. The out-

(PC3) is a 0 (Busy) when Flash memory is being written to, or when Flash memory is being erased. The output is a 1 (Ready) when no WRITE or Erase cycle is in progress.

Memory Operation. The primary F lash memory and secondary Flash memory are addressed through the MCU Bus Interface. The MCU can access these memories in one of two ways:

– The MCU can execute a typical bus WRITE or

READ operation j ust as i t would if accessing a RAM or ROM device using standard bus cycles.

– The MCU can execute a specific instruction

that consists of several WRITE and READ operations. This involves writing specific data patterns to special addresses within the Flash memory to invoke an embedded algorithm. These instructions are summarized in Table

9., page 21.

Typically, the MCU can read Flash memory using READ operations, just as it would read a ROM device. However, Flash memory can only be altered using specific Erase and Program instructions. For example, the MCU cannot write a single byte directly to Flash memory as it would write a byte to RAM. To program a byte into F lash memory, the MCU must execute a Program instruction, then test the status of the Program cycle. This status test is achieved by a RE AD operation or polling Ready/Busy

(PC3).

Flash memory can also be read by using special instructions to retrieve particular Flash device information (sector protect status and ID).

20/110

PSD813F2, PSD833F2, PS D834F2, PSD853F2, PSD854F2

Table 9. Instructions

6,8,13

FS0-FS7 or CSBOOT0-

CSBOOT3

Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7

“READ” RD @ RA

AAh@ X555h

B0h@ XXXXh

30h@ XXXXh

F0h@ XXXXh

AAh@ X555h

A0h@ XXXXh

90h@ XXXXh

55h@ XAAAh

PD@ PA

00h@ XXXXh

90h@ X555h

A0h@ X555h

80h@ X555h

20h@ X555h

Read identifier (A6,A1,A0 = 0,0,1)

Read identifier (A6,A1,A0 = 0,1,0)

PD@ PA

AAh@ X555h

55h@ XAAAh

30h@ SA

10h@ X555h

, CNTL0)

Instruction

READ Read Main

Flash ID

Read Sector Protection

Program a Flash Byte

Flash Sector

7,13

Erase Flash Bulk

Erase Suspend

Sector Erase Resume

Sector Erase

Reset

Unlock Bypass 1 Unlock Bypass

Program

Unlock Bypass

Reset

Note: 1. All bus cycles are WRI TE bus cycles, except the ones with the “READ” labe l

2. All values ar e i n hexadecim al: X = Don’t Care. Ad dresses of th e form XXXXh , in t h is t able, must be even addres ses RA = Address of the memory l ocation to be read RD = Data read from loca tion RA during the READ cy cle PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of Write Strobe (WR PA is an even ad dress for PS D i n word program ming mod e. PD = Data word to be programm ed at location PA. Data is latc hed on the risi ng edge of Writ e S trobe (WR SA = Addres s of t he sector to be erased or veri fied. Th e Sect or Selec t (FS0- FS7 or C SBOOT0 -CSBO OT3) of t he sector to be erased, or verified, must be Active (High).

3. Sector Select (FS0 to FS7 or CS BOOT0 to CSBOOT3) signals are active Hi gh, and are defi ned in PSDsof t E xpress.

4. Only address bits A11-A0 are used in instruction decoding.

5. No Unlock or i nstruction cycles are re quired when th e device is in the READ Mode

6. The Reset instruction is required to return to the READ Mode after reading the Flash ID, or after reading the Sector Protection Status, or if the Er ror Flag Bit (DQ5/DQ13) go es High.

7. Additiona l sec tors to be erased must be written at the end of the Secto r E rase instru ct i on within 80µ s.

8. The data is 00 h for an unprot ected sect or, and 01h fo r a protected s ector. In the fourth cycle, the Sector S elect is act ive, and (A1,A0)=(1,0)

9. The Unlock Bypass instruction is required prior to the Unlock Bypass Program instruction.

10. The Unlock Bypass Reset Flash instructi on is requi red to return to readin g memory data when t he device is i n the Unloc k Bypass mode.

11. The system may perform READ and Program cycles in non-erasing sectors, read the Flash ID or read the Sector Protection Status when in the Suspend Sector Erase mo de. T he Suspend Sector Erase instruction is valid only during a Sec tor Erase cycl e.

12. The Resume Sector Erase instruction is valid only during the Suspend Sector Erase mode.

13. The MCU cannot inv oke the se inst ruct ion s whi le exe cutin g code fr om th e sam e Flash memory as that for whic h the i nstr uctio n is intended. The MCU must fetch, for example, the code from the secondary Flash memory when reading the Sector Protection Status of the prima ry Flash m em o ry.

30h next SA

, CNTL0).

21/110

PSD813F2, PSD833F2, PSD834F 2, PSD853F2, PSD854F2

INSTRUCTIONS

An instruction consists of a sequence o f specific operations. Each received byte is sequentially decoded by the PSD and not executed as a standard WRITE operation. The instruction is executed when the correct number of bytes are properly received and the time between two consecutive bytes is shorter than the time-out period. Some instructions are structured to include READ operations after the initial WRITE operations.

The instruction must be followed exactly. Any invalid combination of instruction bytes or time-out between two consecutive byte s while addressing Flash memory resets the device logic into READ Mode (Flash memory is read like a ROM device).

The PSD supports the instructions summariz ed in

Table 9., page 21:

Flash memory:

■ Erase memory by chip or sector

■ Suspend or resume sector erase

■ Program a Byte

■ Reset to READ Mode

■ Read primary Flash Identifier value

■ Read Sector Protection Status

■ Bypass (on the PSD833F2, PSD834F2,

PSD853F2 and PSD854F2)

These instructions are detailed in Table

9., page 21. For efficient decoding of the instruc-

tions, the first two bytes of an instruction are the coded cycles and are followed by an instruction byte or confirmation byte. The coded cy cles consist of writing the data AAh to address X555h during the first cycle and data 55h to address XAAAh during the second cycle. Address signals A15-A12 are Don’t Care during the instruction WRITE cycles. However, the appropriate Sector Select (FS0-FS7 or CSBOOT0-CSBOOT3) must be selected.

The primary and secondary Flash memories have the same instruction set (except for Read Primary Flash Identifier). The Sector Select signals determine which Flash memory is to receive and execute the instruction. The primary Flash memory is selected if any one of Sector Select (FS0-FS7) is High, and the secondary Flash memory is selected if any one of Sector Select (CSBOOT0CSBOOT3) is High.

Power-up Mode

The PSD internal logic is reset upon Power-up to the READ Mode. Sector Select (FS0-FS7 and CSBOOT0-CSBOOT3) must be held Low, and Write Strobe (WR

, CNTL0) High, during Power-up

for maximum security of the data contents and to remove the possibility of a b yte being written on the first edge of Write Strobe (WR WRITE cycle initiation is locked when V

LKO

low V

READ

Under typical conditions, the MCU may read the primary Flash memory or the secondary Flash memory using READ operations just as it would a ROM or RAM device. Alternately, the MCU may use READ operations to ob tain status inform at ion about a Program or Erase cycle that is currently in progress. Lastly, the MCU may use instructions to read special data from these memory blocks. The following sections describe these READ functions.

Read Memory Contents

Primary Flash memory and secondary Flash memory are placed in the READ Mode after Power-up, chip reset, or a Reset Flash instruction (see

Table 9., page 21). The MCU can read the memo-

ry contents of the primary Flash memory or the secondary Flash memory by using READ operations any time the READ operation is not part of an instruction.

Read Primary Flash Identifier

The primary Flash mem ory identifier is read with an instruction composed of 4 operations: 3 specific WRITE operations and a READ operation (see Ta-

ble 9., pag e 2 1). During the READ operation, ad-

dress bits A6, A1, and A0 must be '0,0,1,' respectively, and the appropriate Sector Select (FS0-FS7) must be High. The identifier for the PSD813F2/3/4/5 is E4h, and for the PSD83xF2 or PSD85xF 2 it is E7h.

Read Memory Sector Protection Status

The primary Flash memory Sector Protection Status is read with an instruction composed of 4 operations: 3 specific WRITE ope rations and a REA D operation (see Table 9., page 21). During the READ operation, address Bits A6, A1, and A0 must be '0,1,0,' respectively, while Sector Select (FS0-FS7 or CSBOOT0-CSBOOT3) designates the Flash memory sec tor whos e protection has to be verified. The READ operation produces 01h if the Flash memory sector is protected, or 00h if the sector is not protected.

The sector protection status for all NVM blocks (primary Flash memory or secondary Flash memory) can also be read by the MCU a ccessing the Flash Protection registers in PSD I/O space. See the section entitled Flash Memory Sector

Protect, page 28 for register definitions.

, CNT L0). An y

is be-

22/110

PSD813F2, PSD833F2, PS D834F2, PSD853F2, PSD854F2

Reading the Erase/Program Status Bits

The PSD provides several status bits to be used by the MCU to confirm the completion of an Erase or Program cycle of Flash memory. These status bits minimize the time that the MCU spends performing these tasks and are defined in Table 10. The status bits can be read as many times as needed.

Table 10. Status Bit

Functional Block

Flash Memory

Note: 1. X = Not guarant eed value , can be read either '1' or ’0.’

2. DQ7-DQ0 re present the Data Bus bit s, D7-D0.

3. FS0-FS7 and CSBOOT0- CSBOOT3 are a cti ve High.

FS0-FS7/CSBOOT0-

CSBOOT3

DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0

Data Polling

For Flash memory, the MCU can perform a READ operation to obtain these status bits while an Erase or Program instruction is being executed by the embedded algorithm. See the section entit led

PROGRAMMING FLASH MEMORY, pag e 25 for

details.

Toggle Flag

Error Flag

Erase Timeout

XXX

23/110

PSD813F2, PSD833F2, PSD834F 2, PSD853F2, PSD854F2

Data Polling Flag (DQ7)

When erasing or programm ing in Flash memory, the Data Polling Flag Bit (DQ7) o utputs the complement of the bit being entered for programming/ writing on the DQ7 Bit. Once the Program instruction or the WRITE operation is completed, the true logic value is read on the Data Polling Flag Bit (DQ7, in a READ operation).

– Data Polling is effective after the fourth WRITE

pulse (for a Program instruction) or after the sixth WRITE pulse (for an Erase instruction). It must be performed at the address being programmed or at an address within the Flash memory sector being erased.

– During an Erase cycle, the Data Polling Flag

Bit (DQ7) outputs a ’0.’ After completion of the cycle, the Data Polling Flag B it (DQ 7 ) o utpu ts the last bit programmed (it is a '1' after erasing).

– If the byte to be programmed is in a protected

Flash memory sector, the instruction is ignored.

– If all the Flash memory sectors to be erased

are protected, the Data Polling Flag Bit (DQ7) is reset to '0' for about 100µs, and then returns to the previous addressed byte. No erasure is performed.

Toggle Flag ( D Q6)

The PSD offers another way for determining when the Flash memory Program cycle is completed. During the internal WRITE operation and when either the FS0-FS7 or CSBOOT0-CSBOOT3 is true, the Toggle Flag Bit (DQ6) toggles from '0' to '1' and '1' to '0' on subsequent attemp ts to read any byte of the memory.

When the internal cycle is complete, the toggling stops and the data read on the Data Bus D0-D7 is the addressed mem ory byte. The device is now accessible for a new READ or WRITE operation. The cycle is finished when two successive READs yield the same output data.

– The Toggle Flag Bit (DQ6) is effective after the

fourth WRITE pulse (for a Program instruction) or after the sixth WRITE pulse (for an Erase instruction).

– If the byte to be programmed belongs to a

protected Flash memory sector, the instruction is ignored.

– If all the Flash memory sectors selected for

erasure are protected, the Toggle Flag Bit (DQ6) toggles to '0' for about 100µs and then returns to the previous addressed byte.

Error Flag (DQ5 )

During a normal Program or Erase cycl e, the Erro r Flag Bit (DQ5) is to ’0.’ This bit is set to '1' when there is a failure during F lash memory Byte Program, Sector Erase, or Bulk Erase cycle.

In the case of Flash memory programming, the Error Flag Bit (DQ5) indicates the attempt to program a Flash memory bit from the programmed state, ’0,’ to the erased state, '1,' which is not valid. The Error Flag Bit (DQ5) may also indicate a Time-out condition while attempting to program a byte.

In case of an error in a Flash memory Sector Erase or Byte Progra m cycle, the Fl ash memory sector in which the error occurred or to which the programmed byte belongs must no longer be used. Other Flash memory sectors may still be used. The Error Flag Bit (DQ5) is reset after a Reset Flash instruction.

Erase Time-out Flag (DQ3)

The Erase Time-out Flag Bit (DQ3) reflects the time-out period allowed betw een two consecut ive Sector Erase instructions. The Erase Time-out Flag Bit (DQ3) is reset to '0' after a Sector Erase cycle for a time period of 100µs + 20% un less an additional Sector Erase instruction is decoded. After this time period, or when the additional Sector Erase instruction is decoded, the E rase Time-out Flag Bit (DQ3) is set to '1.'

24/110

PSD813F2, PSD833F2, PS D834F2, PSD853F2, PSD854F2

PROGR AMMING FLAS H MEMORY

Flash memory must be erased prior to being programmed. A byte of Flash memory is erased to all 1s (FFh), and is programmed by setting selected bits to ’0.’ The MCU may erase Flash memory a ll at once or by-sector, but not byte-by-byte. However, the MCU may program Flash memory byte-bybyte.

The primary and secondary Flash memories require the MCU to send an instruction to program a byte or to erase sectors (see Table 9., page 21).

Once the MCU issues a Flash memory Program or Erase instruction, it must check for the status bits for completion. The embedded algorithms that are invoked inside the PS D s upport s everal m eans to provide status to the MCU. Status may be checked using any of three methods: Data Polling, Data Toggle, or Ready/Busy

Data Polling

Polling on the Data Polling Flag Bit (DQ7) is a method of checking whether a Program or E rase cycle is in progress or has completed. Figure 7 shows the Data Polling algorithm.

When the MCU issue s a Program i nstruction, the embedded algorithm within th e PSD begins. The MCU then reads the location of the byte to be programmed in Flash memory to check status. The Data Polling Flag Bit (DQ7) of this location becomes the complement of b7 of the original data byte to be programmed. The MCU continues to poll this location, comparing the Data P olling Fl ag Bit (DQ7) and monitoring the Error Flag Bit (DQ5). When the Data Polling Flag Bit (DQ7) matches b7 of the original data, and the Error Flag Bit (DQ5) remains ’0,’ the embedded algorithm is compl ete. If the Error Flag Bit (DQ5) is '1,' the M CU should test the Data Polling Flag Bit (DQ7) again since the Data Polling Flag Bit (DQ7) may have changed simultaneously with the Error F lag Bit (DQ5, see Figure 7).

The Error Flag Bit (DQ5) is set if either an internal time-out occurred while the embedded algorithm attempted to program the byte or if the MCU a ttempted to program a '1' to a bit that was not erased (not erased is logic '0').

It is suggested (as with all Flash memories) to read the location again after the embedded program-

(PC3).

ming algorithm has completed, to compare the byte that was written to the Fl ash memory with the byte that was intended to be written.

When using the Data Polling method during an Erase cycle, Figure 7 still app lies. However , the Data Polling Flag Bit (DQ7) is '0' until the Erase cycle is complete. A 1 on the Error F l ag Bit (DQ5) indicates a time-out condition on the Erase cycle; a 0 indicates no error. The MCU can read any location within the sector being erased to get the Data Polling Flag Bit (DQ7) and the Error Flag Bit (DQ5).

PSDsoft Express generates ANSI C code functions which implement these Data Polling algorithms.

Figure 7. Data Po lli ng Flowcha rt

START

READ DQ5 & DQ7

at VALID ADDRESS

DQ7

DATA

DQ5

READ DQ7

DQ7

DATA

FAIL PASS

= 1

YES

AI01369B

25/110

PSD813F2, PSD833F2, PSD834F 2, PSD853F2, PSD854F2

Data Toggle

Checking the Toggle Flag Bit (DQ6) is a method of determining whether a Program or Erase cycle is in progress or has completed. Figure 8 shows t he Data Toggle algorithm.

When the MCU issue s a Program i nstruction, the embedded algorithm within th e PSD begins. The MCU then reads the location of the byte to be programmed in Flash memory to check status. The Toggle Flag Bit (DQ6) of this location toggles each time the MCU reads this location until the embedded algorithm is complete. The MCU c ontinues t o read this location, checking the Toggle Flag Bit (DQ6) and monitoring the Error Flag Bit (DQ5). When the Toggle Flag Bit (DQ6) stops toggling (two consecutive reads yield the same value), and the Error Flag Bit (DQ5) remains ’0,’ the em bedded algorithm is complete. If the Error Flag Bit (DQ5) is '1,' the MCU s houl d tes t th e T oggle Fl ag Bit (DQ6) again, since the Toggle Flag Bit (DQ6) may have changed simultaneously with the Error Flag Bit (DQ5, see Figure 8).

The Error Flag Bit (DQ5) is set if either an internal time-out occurred while the embedded algorithm attempted to program the byte, or if the MCU attempted to program a '1' to a bit that was not erased (not erased is logic '0').

It is suggested (as with all Flash memories) to read the location again after the embedded programming algorithm has completed, to compare the byte that was written to Flash memory with the byte that was intended to be written.

When using the Data Toggle method after an Erase cycle, Figure 8 still applies. the Toggle Flag Bit (DQ6) toggles until the Erase cycle is complete. A '1' on the Error Flag Bit (DQ5) indicates a timeout condition on the Erase cycle; a '0' indicates no error. The MCU can read any location within the sector being erased to get the Toggle Flag Bit (DQ6) and the Error Flag Bit (DQ5).

PSDsoft Express generates ANSI C code functions which implement these Data Toggling a lgorithms.

Unlock Bypass (PSD833F2x, PSD834F2x, PSD853F2x, PSD854F2x)

The Unlock Bypass instructions allow the system to program bytes to the Flash memories faster than using the standard Program instruction. The Unlock Bypass mode is entered by f irst initiating two Unlock cycles. This is followed by a third WRITE cycle containing the Unl ock Bypas s c ode, 20h (as shown in Table 9., page 21).

The Flash memory then enters the Unlock Bypass mode. A two-cycle Unlock Bypass Program instruction is all that is required t o program in this mode. The first cycle in this instruction contains the Unlock Bypass Program code, A0h. The second cycle contains the program address and data. Additional data is programmed in the s ame manner. These instructions dispense with the initial two Unlock cycles required in the standard Program instruction, resulting in faster total Flash memory programming.

During the Unlock Bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset Flash instructions are valid.

To exit th e Unlock Bypass m o de, the system mus t issue the t wo-cycl e Unl ock Bypass Reset F lash i nstruction. The first cycle must contain the data 90h; the second cycle the data 00h. Addresses are Don’t Care for both cycles. The Flash memory then returns to READ Mode.

Figure 8. Dat a Toggle Flow cha rt

START

READ

DQ5 & DQ6

DQ6

TOGGLE

YES

DQ5

= 1

YES

READ DQ6

DQ6

TOGGLE

YES

FAIL PASS

AI01370B

26/110

PSD813F2, PSD833F2, PS D834F2, PSD853F2, PSD854F2

ERASING FLASH MEMORY

Flash Bulk Erase

The Flash Bulk Erase instruction uses six WRITE operations followed by a READ operat ion of the status register, as described in Tab le 9., page 21. If any byte of the Bulk Era se instruction is wrong, the Bulk Erase instruction aborts and the device is reset to the Read Flash memory status.

During a Bulk Erase, the memory status may be checked by reading the Error Flag Bit (DQ5), the Toggle Flag Bit (DQ6), and the Data Polling Fl ag Bit (DQ7), as detailed in the section entitled PRO-

GRAMMING FLASH MEMORY , page 25. The Er-

ror Flag Bit (DQ5) returns a '1' if there has been an Erase Failure (maximum number of Erase cycles have been executed).

It is not necessary to program the memory with 00h because the PSD automatically does this before erasing to 0FFh.

During execution of the Bulk Erase instruction, the Flash memory does not accept any instructions.

Flash Sector Erase

The Sector Erase instruction uses six WRITE operations, as described in Table 9., page 21. Addi- tional Flash Sector Erase codes and Flash memory sector addresses can be written subsequently to erase other Flash memory sectors in parallel, without further coded cycles, if the additional bytes are transmitted in a sho rter time than the time-out period of about 100µs. The in put of a new Sector Erase code restarts the time-out period.

The status of the internal timer can be m onitored through the level of the Erase Time-out Flag Bit (DQ3). If the Erase Time-out Flag B it (DQ3) is ’0,’ the Sector Erase instruction has been received and the time-out period is counting. If the Erase Time-out Flag Bit (DQ3) is '1,' the time-out period has expired and the PSD is busy erasing the Flash memory sector(s). Before and during Erase timeout, any instruction other than Suspend Sector Erase and Resume Sector Erase instructions abort the cycle that is currently in progress, and reset the device to READ Mode. It is not necessary to program the Flash mem ory sector with 00h as the PSD does this automatically before erasing (byte = FFh).

During a Sector Erase, the memory status may be checked by reading the Error Flag Bit (DQ5), the Toggle Flag Bit (DQ6), and the Data Polling Fl ag Bit (DQ7), as detailed in the section entitled PRO-

GRAMMING FLASH MEMORY, page 25.

During execution of the Erase cycle, the Flash memory accepts only Reset and Suspend Sector Erase instructions. Erasure of one Flash memory sector may be suspended, in order to read data from another Flash memory se ctor, and then resumed.

Suspend Sector Erase

When a Sector Erase cycle is in progress, the Suspend Sector Erase instruction can be used to suspend the cycle by writing 0B0h to any address when an appropriate Sector Select (FS0-FS7 or CSBOOT0-CSBOOT3) is High. (See Table

9., page 21). This allows reading of data from an-

other Flash memory sector after the Erase cycle has been suspended. Suspend Sector Erase is accepted only during an Erase cycle and defaults to READ Mode. A Suspend S ector Erase instruction executed during an Erase time-o ut period, in addition to suspending the Erase cycle, terminates the time out pe rio d.

The Toggle Flag Bit (DQ6) stops toggling when the PSD internal logic is suspended. The status of this bit must be monitored at an address within the Flash memory sector being erased. The Toggle Flag Bit (DQ6) stops toggling between 0.1µ s and 15µs after the Suspend Sector Erase instruction has been executed. The PSD is then automatically set to READ Mode.

If an Suspend Sector Erase instruction was executed, the following rules apply:

– Attempting to read from a Flash memory

sector that was being erased outputs invalid data.

– Reading from a Flash sector that was not

being erased is valid.

– The Flash memory cannot be programmed,

and only responds to Resume Sector Erase and Reset Flash instructions (READ is an operation and is allowed).

– If a Reset Flash instruction is received, data in

the Flash memory sector that was being erased is invalid.

Resume Sector Erase

If a Suspend Sector E rase instruction was previously executed, the erase cycle may be resumed with this instruction. The Resume Sector Erase instruction consists of writing 030h to any address while an appropriate Sector Select (FS0-FS7 or CSBOOT0-CSBOOT3) is High. (See Table

9., page 21.)

27/110

PSD813F2, PSD833F2, PSD834F 2, PSD853F2, PSD854F2

SPECIFIC FEATURES

Flash Memory Sector Protect

Each primary and secondary Flash memory sector can be separately protected a gainst P rogram and Erase cycle s. Sector Pr ote c ti o n p r o vi d es a ddi tional data security because it disables all Program or Erase cycles. This mode ca n be activated through the JTAG Port or a Device Programmer.

Sector protection can be selected for ea ch sector using the PSDsoft Express Configuration program. This automatically protects selected sectors when the device is programmed through the JTAG Port or a Device Programmer. Flash memory sectors can be unprotecte d to allow updating of t heir contents using the JTAG Port or a Device Programmer. The MCU can read (but cannot change) the sector protection bits.

Any attempt to program or erase a protected Flash memory sector is ignored by the device. The Verify operation results in a READ of the protected data. This allows a guarantee of the retention of the Protection status.

The sector protection status ca n be read by the MCU through the Flash memory protection and PSD/EE protection registers (in the CSIOP block). See Tables 11 and 12.

Reset Flash

The Reset Flash instruction consists of one WRITE cycle (see Table 9., page21). It can also be optionally preceded by the standard two WRITE decoding cycles (writing AAh to 555h and 55h to AAAh). It must be executed after:

– Reading the Flash Protection Status or Flash

– An Error condition has occurred (and the

device has set the Error Flag Bit (DQ5) to '1') during a Flash memory Program or Erase cycle.

On the PSD813F2/3/4/5, the Reset Fla sh instruction puts the Flash memory back into normal READ Mode. It may take the Flash memory up to a few milliseconds to complete the Reset cycle. The Reset Flash instruction is ignored when it is issued during a Program or Bulk Erase cycle of the Flash memory. The Reset Flash instruction aborts any on-going Sector Erase cycle, and returns the Flash memory to the normal READ Mode within a few millis econds.

On the PSD83xF2 or PSD85xF2, the Reset Flash instruction puts the Flash m emory back into normal READ Mode. If an Error condition has occurred (and the device has set the Error Flag Bit (DQ5) to '1') the Flash memory is put back into normal READ Mode within 25µs of the Reset Flash instruction having been issued. The Reset Flash instruction is ignored when it is issued during a Program or Bulk Erase cycle of the Flash memory. The Reset Flash instruction a borts any on-going Sector Erase cycle, and returns the Flash memory to the normal READ Mode within 25µs.

Reset (RESET PSD85xF2)

A pulse on Reset (RESET in progress, and resets the Flash memory to the READ Mode. When the reset occurs during a Program or Erase cycle, the Flash memory takes up to 25 µs to return to the READ Mode. It is recommended that the Reset (RESET Power On Reset, as described on RESET TIMING

AND DEVICE STATUS AT RESET, page 67) be

at least 25µs so that the F lash memory is always ready for the MCU to fetch the bootstrap instructions after the Reset cycle is complete .

) Signal (on the PSD83xF2 and

) aborts any cycle that is

) pulse (except for

Table 11. Sector Protection/Security Bit Definition – Flash Protection Register

Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0 Sec7_Prot Sec6_Prot Sec5_Prot Sec4_Prot Sec3_Prot Sec2_Prot Sec1_Prot Sec0_Prot

Note: 1. Bit Definitions:

Sec_Prot 1 = Primary Flash memory or secondary Flash memory Sector is write protected. Sec_Prot 0 = Primary F lash memory or secondary Fla sh memory Sec to r i s no t write protec ted.

Table 12. Sector Protection/Security Bit Definition – PSD/EE Protection Register

Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0 Security_Bit not used not used not used Sec3_Prot Sec2_Prot Sec1_Prot Sec0_Prot

Note: 1. Bit Definitions:

28/110

Sec_Prot 1 = Secondary Flash memory Sector is write protected. Sec_Prot 0 = Secondary Fl ash memo ry Sect or is not write protected. Security_Bit 0 = Security Bit in device has not been set.

1 = Security Bi t in device has be en set.

PSD813F2, PSD833F2, PS D834F2, PSD853F2, PSD854F2

SRAM

The SRAM is enab led when SRAM Select (RS0) from the DPLD is High. SRAM Select (RS0) can contain up to two prod uct terms, allowing flexib le memory mapping.

The SRAM can be backed up usin g an external battery. The external battery should be connected to Voltage Stand-by (V external battery connected to the PSD , the contents of the SRAM are reta ined in the event of a power loss. The contents of the SRAM are retained so long as the battery voltage remains at 2 V or greater. If the supply voltage falls below the battery voltage, an internal power switch-over to the battery occurs.

, PC2). If you have an

STBY

PC4 can be configured as an output that indicates when power is being drawn from the ext ernal ba ttery. Battery-on Indicator (VBATON, PC4) is High with the supply voltage falls below the battery voltage and the battery on Voltage Stand-by (V

STBY

PC2) is supplying power to the internal SRAM. SRAM Select (RS0), Voltage Stand-by (V

STBY

PC2) and Battery-on Indicator (VBATON, PC4) are all configured using PSDsoft Express Configuration.

, ,

29/110

PSD813F2, PSD833F2, PSD834F 2, PSD853F2, PSD854F2

SECTOR SELECT AND SRAM SE LECT

Sector Select (FS0-FS7, CSBOOT0-CSBOOT3) and SRAM Select (RS0) are all outputs of the DPLD. They are setup by writing equations for them in PSDabel. The f ollowing rules apply to the equations for these signals:

1. Primary Flash memory and secondary Flash memory Sector Select signals must not be larger than the physical sector size.

2. Any p rimary Flas h memory sector must not be mapped in the same memory space as another Flash memory sector.

3. A secondary Flash memory sector must not be mapped in the same memory space as another secondary Flash memory sector.

4. SRAM, I/O, and Peripheral I/O spaces must not overlap.

5. A secondary Flash memory sector may overlap a prim ary Flash m emory sector. In case of overlap, priority is given to the secondary Flash memory sector.

6. SRAM, I/O, and Peripheral I/O spaces may overlap any other memory sector. Priority is given to the SRAM, I/O, or Peripheral I/O.

Example

FS0 is valid when the address is in the range of 8000h to BFFFh, CSBOOT0 is valid from 8000h to 9FFFh, and RS0 is valid from 8000h to 87FFh. Any address in the range of RS0 always accesses the SRAM. Any address in the range of CSBOOT0 greater than 87FFh (and less than 9FF Fh) automatically addresses secondary Flash memory segment 0. Any address greater than 9FFFh ac cesses the primary Flash memory segment 0. You can see that half of the primary Flash memory segment 0 and one-fourth of secondary Flash memory segment 0 cannot be acces sed in this example. Also note that an equation that defined FS1 to anywhere in the range of 8000h to BFFFh wo uld not be valid.

Figure 9 show s the priority lev els for all me mory components. Any component on a higher level can overlap and has priority over any component on a lower level. Components on the same level must not overlap. Level one has the highest priority and level 3 has the lowest.

Memory Se le c t Co nf i gur a tio n f or MCUs with Separate Program and Data Spaces

The 8031 and compatible family of MCUs, which includes the 80C51, 80C151, 80C251, and 80C51XA, have separate address spaces for Program memory (selected using Program Select Enable (PSEN using Read Strobe (RD

, CNTL2)) and Data memory (selected

, CNTL1)). Any of the memories within the PSD can reside in either space or both spaces.

This is controlled through manipulation of the VM register that resides in the CSIOP space.

The VM register is set using PSDsoft Express to have an initial value. It can subsequently be changed by the MCU so that memory mapping can be changed on-the-fly.

For example, you may wish to have SRAM and primary Flash memory in the Data space at Boot-up, and secondary Flash memory in the Program space at Boot-up, and later s wap the primary and secondary Flash memories. This is easily done with the VM register by using PSDsoft Express Configuration to configure it for Boot-up and having the MCU change it when desired. Table

13., page 31 descr ibes the VM Register.

Figure 9. Priority Level of Memory and I/O Components

Highest Priority

Lowest Priority

Conf i gurat i on Modes for MCUs with Sepa rate Program and Data Spaces

Separate Space Modes. Program space is sep-

arated from Data space. For example, Program Select Enable (PSEN the program code from the primary Flash memory, while Read Strobe (RD data from the secondary Flash memory, SRAM and I/O Port blocks. This configuration requires the VM register to be set to 0Ch (see Figure

10., page 31).

Combined Space Modes. The Program and Data spaces are combined into one memory space that allows the primary Flash memory, secondary Flash memory, and SRAM to be accessed by either Program Select Enable (PSEN or Read Strobe (RD configure the primary Flash mem ory in Combi ned space, Bits b2 and b4 of the VM register are set to '1' (see Figure 11., page 31).

Level 1

SRAM, I/O, or Peripheral I/O

Level 2

Secondary

Non-Volatile Memory

Level 3

Primary Flash Memory

, CNTL2) is used to a ccess

, CNTL1) is used to access

, CNTL1). For example, to

AI02867D

, CNTL2)

30/110

PSD813F2, PSD833F2, PS D834F2, PSD853F2, PSD854F2

Figure 10. 8031 Memory Modules – Separate Space

DPLD

RS0

CSBOOT0-3

FS0-FS7

PSEN

Primary

Flash

Memory

CS CSCS

OE OE

Figure 11. 8031 Memory Modules – Combined Space

DPLD

VM REG BIT 3

VM REG BIT 4

RS0

CSBOOT0-3

FS0-FS7

Secondary

Flash

Memory

Primary

Flash

Memory

CS CSCS

OE OE

Secondary

Flash

Memory

SRAM

AI02869C

SRAM

PSEN

VM REG BIT 1

VM REG BIT 2

VM REG BIT 0

Table 13. VM Register

Bit 7

PIO_EN

0 = disable

PIO mode

1= enable

PIO mode

Bit 6 Bit 5

not

used

not

used

not

Bit 4

Primary

FL_Data

0 = RD

can’t access

Flash memory

1 = RD

access Flash

memory

Bit 3

Secondary

EE_Data

can’t

0 = RD

access

Secondary Flash

memory

1 = RD

access

Secondary Flash

memory

Bit 2

Primary

FL_Code

0 = PSEN

can’t access

Flash

memory

1 = PSEN

access

Flash

memory

Bit 1

Secondary

EE_Code

0 = PSEN

can’t

access

Secondary Flash

memory

1 = PSEN

access

Secondary Flash

memory

AI02870C

Bit 0

SRAM_Code

0 = PSEN

can’t access

SRAM

1 = PSEN

access

SRAM

31/110

PSD813F2, PSD833F2, PSD834F 2, PSD853F2, PSD854F2

PAGE REGISTER

The 8-bit Page Register increases the addressing capability of the MCU by a factor of up to 256. The contents of the register can also be read by the MCU. The outputs of the Page Register (PGR0PGR7) are inputs to the DPLD decoder and can be included in the Sector Select (FS0-FS7, CSBOOT0-CSBOOT3), and SRA M Select (RS0) equations.

Figure 12. Pa ge R egister

RESET

If memory paging is not needed, or if not all 8 page register bits are needed for memory paging, then these bits may be used in the CPLD for gen eral logic. See Application Note AN1154.

Figure 12 shows the Page Register. The eight flipflops in the register are connected to the internal data bus D0-D7. The MCU can write to or read from the Page Register. The Page Register can be accessed at address location CSIOP + E0h.

D0 - D7

R/W

D0 Q0 D1 D2 D3 D4 D5 D6 D7

Q1 Q2 Q3 Q4 Q5 Q6 Q7

PAGE

PGR0 PGR1

PGR2 PGR3 PGR4 PGR5 PGR6 PGR7

DPLD

AND

CPLD

PLD

INTERNAL SELECTS AND LOGIC

AI02871B

32/110

PSD813F2, PSD833F2, PS D834F2, PSD853F2, PSD854F2

PLDS

The PLDs bring programmable logic f unctionality to the PSD. After specifying the logic for the PLDs using the PSDabel tool in PSDsoft Express, the logic is programmed into the device and available upon Power-up.

The PSD contains two PLDs: the Decode PLD (DPLD), and the Complex PLD (CPLD). The PLDs are briefly discussed in the next few paragraphs, and in more detail in the section entitled Decode

PLD (DPLD), page 35 and the section entitled Complex PLD (CPLD), page 36. Figure

13., page 34 shows the configuration of the PLDs.

The DPLD performs add ress decoding for Sele ct signals for internal components, such as memory, registers, and I/O ports.

The CPLD can be used for logic functions, such as loadable counters and shift registers, state machines, and encoding and decoding logic. These logic functions can be constructed using the 16 Output Macrocells (OMC), 24 Input Macrocells (IMC), and the AND Array. The CPLD can also be used to generate External Chip Select (ECS0ECS2) signals.

The AND Array is used to form product terms. These product terms are specified using PSDabel. An Input Bus consisting of 73 signals is connected to the PLDs. The signals are shown in Table 14.

The Turbo Bit in PS D

The PLDs in the PSD can minimi ze power consumption by switching of f when inputs remain unchanged for an extended time of about 70ns. Resetting the Turbo Bit to '0' (Bit 3 of PMMR0) automatically places the PLDs into standby if no inputs are changing. Turning the Turbo mode off increases propagation delays while reducing power consumption. See t he sec tion entitled POWER

MANAGEMENT, pa ge 62 on how to set the Turbo

Bit.

Additionally, five bits are available in PMMR 2 to block MCU control signals from entering the PLDs. This reduces power consumption and can be used only when these MCU control signals are not used in PLD logic equations.

Each of the two PLDs has unique characteristics suited for its applications. They are described in the following sections.

Table 14. DPLD and CPLD I nputs

Number

Input Source Input Name

MCU Address Bus MCU Control Signals CNTL2-CNTL0 3 Reset RST Power-down PDN 1 Port A Input

Macrocells Port B Input

Macrocells Port C Input

Macrocells Port D Inputs PD2-PD0 3 Page Register PGR7-PGR0 8 Macrocell AB

Feedback Macrocell BC

Feedback Secondary Flash

memory Program Status Bit

Note: 1. The addr ess inputs are A19-A4 in 80C 51XA mode.

A15-A0 16

PA7-PA0 8

PB7-PB0 8

PC7-PC0 8

MCELLAB.FB7-

FB0

MCELLBC.FB7-

FB0

Ready/Busy

Signals

33/110

PSD813F2, PSD833F2, PSD834F 2, PSD853F2, PSD854F2

Figure 13. PLD D ia gra m

DIRECT MACROCELL ACCESS FROM MCU DATA BUS

CSIOP SELECT

SRAM SELECT

PERIPHERAL SELECTS

JTAG SELECT

PRIMARY FLASH MEMORY SELECTS

SECONDARY NON-VOLATILE MEMORY SELECTS

MCELLAB

MCELLBC

TO PORT B OR C

TO PORT A OR B

ALLOC.

MACROCELL

16 OUTPUT

MACROCELL

24 INPUT MACROCELL

ALLOC.

TO PORT D

EXTERNAL CHIP SELECTS

I/O PORTS

(PORT A,B,C)

AI02872C

PAGE

DATA

BUS

DECODE PLD

CPLD

OUTPUT MACROCELL FEEDBACK

PLD INPUT BUS

PORT D INPUTS

INPUT MACROCELL & INPUT PORTS

DIRECT MACROCELL INPUT TO MCU DATA BUS

34/110

PSD813F2, PSD833F2, PS D834F2, PSD853F2, PSD854F2

Decode PLD (DPLD)

The DPLD, shown in Figure 14, is used for decoding the address for internal and external com ponents. The DPLD can be used to generate the following decode signals:

■ 8 Sector Select (FS0-F S7 ) si gna ls for the

primary Flash memory (three product terms each)

■ 4 Sector Select (CSBO OT 0 - CSBO OT 3 )

signals for the secondary Flash memory (three product terms each)

Figure 14. DP LD Logic Array

■ 1 internal SRAM Select (RS0) signal (two

product terms)

■ 1 internal CSIOP Select (PSD Configuration

■ 1 JTAG Select signal (enables JTAG on Port

■ 2 internal Peripheral Select signals

(Peripheral I/O mode).

I/O PORTS (PORT A,B,C)

MCELLAB.FB [7:0] (FEEDBACKS)

MCELLBC.FB [7:0] (FEEDBACKS)

PGR0 -PGR7

]

A[15:0

PD[2:0] (ALE,CLKIN,CSI)

PDN (APD OUTPUT)

CNTRL[2:0

RESET

RD_BSY

] (

READ/WRITE CONTROL SIGNALS)

(INPUTS)

(24)

(8)

(16)

(3)

(1)

(3)

(1)

CSBOOT 0

CSBOOT 1

CSBOOT 2

CSBOOT 3

RS0

CSIOP

PSEL0

PSEL1

JTAGSEL

FS0

FS1

FS2

FS3

8 PRIMARY FLASH MEMORY SECTOR SELECTS

FS4

FS5

FS6

FS7

SRAM SELECT

I/O DECODER SELECT

PERIPHERAL I/O MODE SELECT

AI02873D

35/110

PSD813F2, PSD833F2, PSD834F 2, PSD853F2, PSD854F2

Complex PLD (CPLD)

The CPLD can be used to implement system logic functions, such as loadable counters and shift registers, system mailboxes, hands haking protocols, state machines, and random logic. The CPLD can also be used to generate three External C hip Select (ECS0-ECS2), routed to Port D.

Although External Chip Select (ECS0-ECS2) can be produced by any Output Macrocell (OMC), these thr ee Ext ern al Chi p Sel ect (E CS0 -ECS2) o n Port D do not consume any Output Macrocells (OMC).

As shown in Figure 13., page 34, the CPLD has the following blo cks:

■ 24 Input Macrocells (IMC)

■ 16 Output Macrocells (OMC)

■ Macrocell Allocator

Figure 15. Macrocell and I/O Port

■ Product Term Allocator

■ AND Array capable of generating up to 137

product terms

■ Four I/O Ports.

Each of the blocks are described in the sections that fo llow.

The Input Macrocells (IMC) and Output Macrocells (OMC) are connected to the PSD internal data bus and can be directly accessed b y the MCU. This enables the MCU software to load data into the Output Macrocells (OMC) or read data from both the Input and Output Macrocells (IMC and OMC).

This feature allows efficient implementation of system logic and eliminat es the need to connec t the data bus to the AND Array as required in most standard PLD macrocell architectures.

PLD INPUT BUSPLD INPUT BUS

AND ARRAY

PRODUCT TERMS

FROM OTHER

MACROCELLS

CPLD MACROCELLS

PRODUCT TERM

ALLOCATOR

UP TO 10

PRODUCT TERMS

POLARITY SELECT

PT CLOCK

GLOBAL CLOCK

CLOCK SELECT

PT CLEAR

PT OUTPUT ENABLE (OE

MACROCELL FEEDBACK

I/O PORT INPUT

PT INPUT LATCH GATE/CLOCK

PT PRESET

MUX

MCU DATA IN

PR DI LD D/T

D/T/JK FF

SELECT

)

MCU ADDRESS / DATA BUS

MCU LOAD

MACROCELL

MUX

COMB.

/REG

SELECT

DATA

LOAD

CONTROL

OUT TO

MCU

MACROCELL

I/O PORT

ALLOC.

OUTPUT

CPLD

TO OTHER I/O PORTS

I/O PORTS

LATCHED

ADDRESS OUT

DATA

CPLD OUTPUT

PDR

INPUT

DIR

REG.

INPUT MACROCELLS

ALE/AS

MUX MUX

MUX

SELECT

I/O PIN

AI02874

36/110

PSD813F2, PSD833F2, PS D834F2, PSD853F2, PSD854F2

Output Ma c rocell (OMC)

Eight of the Output Macrocells (OMC) are connected to Ports A and B pins an d are named as McellAB0-McellAB7. The other eight macrocells are connected to Ports B and C pins and are named as McellBC0-McellBC7. If an McellAB output is not assigned to a specific pin in PSDabel, the Macrocell Allocator block assigns it to either Port A or B. The same is true for a McellBC output on Port B or C. Table 15 shows the macrocells and port assignment.

The Output Macrocell (OMC) architecture is shown in Figure 16., page 39. As shown in the figure, there are native prod uct term s av ailable from the AND Array, and borrowed product terms available (if unused) from other Output Macrocells (OMC). The polarity of the product term is con-

Table 15. Output Macrocell Port and Data Bit Assignments

Output

Macrocell

McellAB0 Port A0, B0 3 6 D0 McellAB1 Port A1, B1 3 6 D1 McellAB2 Port A2, B2 3 6 D2 McellAB3 Port A3, B3 3 6 D3 McellAB4 Port A4, B4 3 6 D4

Port

Assignment

Native Product Terms

trolled by the XOR gate. The Output Macrocell (OMC) can implement either sequential logic, using the flip-flop element, or combinatorial logic. The multiplexer selects between the sequent ial or combinatorial logic outputs. The multiplexer output can drive a port pin and has a feedback path to the AND Array inputs.

The flip-flop in the Output Macrocell (OMC) block can be configured as a D, T, JK, or SR type in the PSDabel program. The flip-flop’s clock, preset, and clear inputs may be driven from a product term of the AND Array. Alternatively, CLKIN (PD1) can be used for the clock input to the flip-flop. The flip-flop is clocked on the rising edge of CLKIN (PD1). The preset and clear are active High inputs. Each clear input can use up to two product terms.

Maximum Borrowed

Product Terms

Data Bit for Loading or

Reading

McellAB5 Port A5, B5 3 6 D5 McellAB6 Port A6, B6 3 6 D6

McellAB7 Port A7, B7 3 6 D7 McellBC0 Port B0, C0 4 5 D0 McellBC1 Port B1, C1 4 5 D1 McellBC2 Port B2, C2 4 5 D2 McellBC3 Port B3, C3 4 5 D3 McellBC4 Port B4, C4 4 6 D4 McellBC5 Port B5, C5 4 6 D5 McellBC6 Port B6, C6 4 6 D6 McellBC7 Port B7, C7 4 6 D7

37/110

PSD813F2, PSD833F2, PSD834F 2, PSD853F2, PSD854F2

Product Term A l lo ca tor

The CPLD has a Product Term Allocator. The PSDabel compiler uses the Product Term Allocator to borrow and place produ ct terms from one macrocell to another. The following list summarizes how product terms are allocated:

■ McellAB0-McellAB7 all have three native

product terms and may borrow up to six more

■ McellBC0-McellBC3 all have four native

product terms and may borrow up to five more

■ McellBC4-McellBC7 all have four native

product terms and may borrow up to six more.

Each macrocell may only borrow product terms from certain other macrocells. Product terms already in use by one macrocell are not available for another macrocell.

If an equation requires more product terms than are available to it, then “external” product terms are required, which consume other Output Macrocells (OMC). If external product terms are used, extra delay is added for the equation that required the extra product terms.

This is called product term expansion. PSDsoft Express performs this expansion as needed.

Loading and Reading the Output Macrocells (OMC)

The Output Macrocells (OMC) block occupies a memory location in the MCU address space, as defined by the CSIOP block (see the section entitled I/O PORTS, page 51). The flip-flops in each of the 16 Output Macrocells (OMC) can be loaded from the data bu s by a MCU. Load ing the Ou tput Macrocells (OMC) with data f rom the MCU takes priority over internal functions. As such, the preset, clear, and clock inputs to the flip-flop can be overridden by the MCU. The ability to load the flip-flops and read them back is useful in such applications as loadable counters and s hift registers, ma ilboxes, and handshaking protocols.

Data can be loaded to the Output Macrocells (OMC) on the trailing edge of Write Strobe (WR CNTL0) (edge loading) or during the time that Write Strobe (WR ing). The method of loading is specified in PSDsoft Express Configuration.

The OMC Mask Register

There is one Mask Regi ster for each of the t wo groups of eight Output Macrocells (OMC). The Mask Registers can be used to block the loading of data to individual Output Macrocells (OMC). The default value for the Mask Registers is 00h, which allows loading of the Output Macrocells (OMC). When a given bit in a Mask Register is set to a 1, the MCU is blocked from writing to the associated Output Macrocells (OMC). For example, suppose McellAB0-McellAB3 are being used for a state machine. You would not want a MCU write to McellAB to overwrite the state machine registers. Therefore, you would want to load the Mask Register for McellAB (Mask Macrocell AB) with the value 0Fh.

The Output Enable of the OMC

The Output Macrocells (OMC) block can be connected to an I/O port pin as a PLD output. The output enable of each port pin driver is controlled by a single product term from the AND Array, ORed with the Direction Register output. The pin is enabled upon Power-up if no output enable equation is defined and if the pin is declared as a PLD ou tput in PSDsoft Express.

If the Output Macroce ll (OMC) output is declared as an internal node and not as a port pin output in the PSDabel file, the port pin can be used for other I/O functions. The internal node feedback can be routed as an input to the AND Array.

, CNTL0) is active (level load-

38/110

Figure 16. CP LD Output Macrocell

PSD813F2, PSD833F2, PS D834F2, PSD853F2, PSD854F2

I/O PIN

AI02875B

REG.

MASK

] 7:0

[ D

DIRECTION

INTERNAL DATA BUS

)

.OE

(

.PR

(

PRESET

ENABLE

SELECT

COMB/REG

ALLOCATOR

MACROCELL

MUX

PRDIN

PORT

DRIVER

CLR

) (

SELECT

POLARITY

)

D/T/JK /SR

(

PROGRAMMABLE

.RE

MUX

CLEAR

INPUT

MACROCELL

)

.FB

(

PORT INPUT

FEEDBACK

MACROCELL CS

ALLOCATOR

AND ARRAY

PT CLK

CLKIN

PLD INPUT BUS

39/110

PSD813F2, PSD833F2, PSD834F 2, PSD853F2, PSD854F2

Input Macrocells (IMC)

The CPLD has 24 Input Macrocells (IMC), one for each pin on Ports A, B, and C. The architecture of the Input Macrocells (IMC) is shown in Figure

17., page 41. The Input Macrocells (IMC) are indi-

vidually configurable, and can be used as a latch, register, or to pass incoming Port signals prior to driving them onto the PLD input bus. The outputs of the Input Macrocells (IMC) can be read by the MCU through the internal data bus.

The enable for the latch and clock for the register are driven by a multiplexer whose inputs are a product term from the CPLD AND Array or the MCU Address Strobe (ALE/AS). Each product term output is used to latch or clock four Input Macrocells (IMC). Port inputs 3-0 can be controlled by one product term and 7-4 by another.

Configurations for the Input Macrocells (IMC) are specified by equations written in PSDabel (see Application Note AN1171). Outputs of the Input Macrocells (IMC) can be read by the MCU via the IMC buffer. See the section entitled I/O

PORTS, page 5 1.

Input Macrocells (IMC) can use Address Strobe (ALE/AS, PD0) to latch address bits higher than A15. Any latched addresses are routed to the PLDs as inputs.

Input Macrocells (IMC) are particularly usefu l with handshaking communication applications where two processors pass data back and forth through a common mailbox . Figure 18., page 42 shows a typical configuration where the Master MCU writes to the Port A Data Out Register. This, in turn, can be read by the Slave MCU via the activation of the “Slave-Read” output enable product term.

The Slave can also write to the Port A Input Macrocells (IMC) and the Master can then read the Input Macrocells (IMC) directly.

Note that the “Slave-Read” and “Slave-Wr” signals are product terms that are derived from the Slave MCU inputs Read Strobe (RD Strobe (WR

, CNTL1), Write

, CNTL0), and Slave_CS.

40/110

Figure 17. Input Macrocell

PSD813F2, PSD833F2, PS D834F2, PSD853F2, PSD854F2

] 7:0

[

DIRECTION

INTERNAL DATA BUS

INPUT MACROCELL

) .OE

(

AND

OUTPUT

MACROCELL AB

MACROCELLS BC

I/O PIN

PORT

DRIVER

MUX

ALE/AS

MUX

D FF

AI02876B

INPUT MACROCELL

LATCH

ENABLE

AND ARRAY

FEEDBACK

PLD INPUT BUS

41/110

PSD813F2, PSD833F2, PSD834F 2, PSD853F2, PSD854F2

Figure 18. Handshaki ng C o m m uni c at i on Us in g In put Macrocells

MCU

SLAVE

] 7:0

[ D

PORT A

AI02877C

PSD

PORT A

SLAVE–CS

SLAVE–READ

DATA OUT

CPLD

MCU-RD

MCU-WR

MASTER

SLAVE–WR

MCU

] 7:0

[ D

PORT A

INPUT

MACROCELL

MCU-RD

42/110

PSD813F2, PSD833F2, PS D834F2, PSD853F2, PSD854F2

MCU BUS INTERFACE

The “no-glue logic” MCU Bus Interface block can be directly connected to most popular MCUs and their control signals. Key 8-bit MCUs, with their

Table 16. MCUs and their Control Signals

MCU

Data Bus

Width

CNTL0 CNTL1 CNTL2 PC7

bus types and control signals, are shown in Table

16. The interface type is specified using the PSD-

soft Express Configuration.

PD0

ADIO0 PA3-PA0 PA7-PA3

8031 8 WR 80C51XA 8 WR 80C251 8 WR 80C251 8 WR 80198 8 WR 68HC11 8 R/W 68HC912 8 R/W Z80 8 WR Z8 8 R/W 68330 8 R/W M37702M2 8 R/W

Note: 1. Unused CNTL2 pin ca n be configured as CPLD inpu t. Other unused pins (PC7 , P D0, PA3-0) ca n be configured for other I/ O func-

tions.

2. ALE/AS input is optiona l for MCUs with a non-multi pl exed bus

RD PSEN RD PSEN PSEN RD PSEN RD E E RD DS DS E

(Note 1)(Note 1)

(Note 1)(Note 1) (Note (Note (Note 1)(Note 1)(Note 1) (Note 1)(Note 1) (Note 1)(Note 1) (Note 1)(Note 1)

(Note 1) (Note 1)

(Note 1)

)(Note 1)

DBE

)

ALE A0 ALE A4 A3-A0 ALE A0 ALE A0 ALE A0 AS A0 AS A0

A0 D3-D0 D7-D4 AS AS A0 ALE A0 D3-D0 D7-D4

(Note 1)(Note 1)

(Note 1) (Note 1)(Note 1) (Note 1)(Note 1) (Note 1)(Note 1) (Note 1)(Note 1)

)(Note 1)

(Note

)(Note 1)

(Note (Note 1)(Note 1)

43/110

PSD813F2, PSD833F2, PSD834F 2, PSD853F2, PSD854F2

PSD Interface to a Multiplexed 8-Bit Bus

Figure 19 shows an example of a system using a MCU with an 8-bit multiplexed bus and a PSD. The ADIO port on the PSD is connected directly to the MCU address/data bus. Address Strobe (ALE/AS, PD0) latches the address signals internally. Latched addresses can be brought out to Port A or

Figure 19. An Example of a Typical 8-bit Multiplexed Bus Interface

B. The PSD drives the ADIO data bus only when one of its internal resources is accessed and Read Strobe (RD

, CNTL1) is active. Should the system address bus exceed sixteen bits, Ports A, B, C, or D may be used as additional address inputs.

MCU

RESET

BHE

ALE

AD[7:0

A[15:8

PSD

]

ADIO

]

PORT

WR (CNTRL0 RD (CNTRL1

BHE (CNTRL2

RST

ALE (PD0

PORT D

)

PORT

)

PORT

A[7:0

(

OPTIONAL

A[15:8

(

OPTIONAL

AI02878C

]

)

]

)

44/110

PSD813F2, PSD833F2, PS D834F2, PSD853F2, PSD854F2

PSD Interface to a Non-Multiplexed 8-Bit Bus

Figure 20 shows an example of a system using a MCU with an 8-bit non-multiplexed bus and a PSD. The address bus is connected to the A DIO Port, and the data bus is connected to Port A. Port A is in tri-state mode when the PSD is not accessed by the MCU. Should the system address bus

MCU Bus Interface Examples

Figure 21 through 25 show examples of the basic connections between the PSD and some pop ular MCUs. The PSD Control input pins are labeled as to the MCU function for which they are configured. The MCU bus in terface i s s pecified us ing the PSDsoft Express Configuration.

exceed sixteen bits, Ports B, C, or D may be used for additional address inputs.

Data Byte Enable Reference

MCUs have different data byte orientations. Table

17 shows how the PSD interprets byte/word oper-

ations in different bus WRITE configurations. Even-byte refers to locations with address A0

Table 17. Eight-Bit Data Bus

BHE A0 D7-D0

X 0 Even Byte X 1 Odd Byte

equal to '0' and odd byte as locations with A0 equal to ’1.’

Figure 20. An Example of a Typical 8-bit Non-Multiplexed Bus Interface

MCU

BHE

D[7:0

A[15:0

]

PSD

ADIO

PORT

WR (CNTRL0 RD (CNTRL1

BHE (CNTRL2 RST

PORT

)

PORT

]

D[7:0

A[23:16

(OPTIONAL)

]

RESET

ALE

ALE (PD0

PORT D

)

AI02879C

45/110

PSD813F2, PSD833F2, PSD834F 2, PSD853F2, PSD854F2

80C31

Figure 21 shows the bus interface for t he 80C31, which has an 8-bit multiplexed address /data bus. The lower address byte is multiplexed with the data bus. The MCU control signals Program Select Enable (PSEN

, CNTL2), Read Strobe (RD,

Figure 21. Interfacing the PSD with an 80C31

CNTL1), and Write Strobe (WR used for accessing the internal memory and I/O Ports blocks. Address Strobe (ALE/AS, PD0) latches the address.

, CNTL0) may be

RESET

12 13 14 15

80C31

1 2 3 4 5 6 7 8

EA/VP X1

RESET

INT0 INT1 T0 T1

P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7

P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7

P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7

PSEN

ALE/P

TXD RXD

RESET

AD7-AD0

AD[7:0

]

PSD

39 38 37 36 35 34 33 32

21 22 23 24 25 26 27 28

17 16

11 10

AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7

A8 A9 A10 A11 A12 A13

A14

A15 RD

PSEN

ALE

AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7

ADIO0

ADIO1

ADIO2

ADIO3

ADIO4

ADIO5

ADIO6

ADIO7

ADIO8

ADIO9

ADIO10

ADIO11

ADIO12

ADIO13

ADIO14

ADIO15

CNTL0(WR)

CNTL1(RD)

CNTL2(PSEN)

PD0-ALE

PD1

PD2

RESET

PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7

PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7

PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7

29 28 27 25 24 23 22 21

7 6 5

4 3 2

20 19 18 17 14 13 12 11

AI02880C

46/110

PSD813F2, PSD833F2, PS D834F2, PSD853F2, PSD854F2

80C251

The Intel 80C251 MCU features a user-configurable bus interface with four possible bus configurations, as shown in Table 18., page 48.

The first configuration is 80C31-compatible, and the bus interface to the PSD is identical to that shown in Figure 21., page 46. The second and third configurations have the same bus connection as shown in F igure 22. There is only one Read Strobe (PSEN

) connected to CNTL1 on the PSD . The A16 connection to PA0 allows for a larger address input to the PSD. The fourth configuration is shown in Figure 23., page 48. Read Strobe (RD

) is connected to CNTL1 and Program Select Enable (PSEN

) is connected to CNTL2.

Figure 22. Interfacing the PSD with the 80C251, with One READ Input

The 80C251 has two major operating modes: Page mode and Non-page mode. In Non-page mode, the data is multiplexed with the lower address byte, and Address Strobe (ALE/AS, PD0) is active in every bus cycl e. I n Page mode, data (D7D0) is multiplexed with address (A15-A8). In a bus cycle where there is a P age hit, Address Strobe (ALE/AS, PD0) is not act ive and only addresses (A7-A0) are changing. The PSD supports both modes. In Page Mode, the PSD bus timing is identical to Non-Page Mode except the address hold time and setup time with respect to Address Strobe (ALE/AS, PD0) is not required. The PSD access time is measured from address (A7-A0) valid to data in v a lid.

80C251SB

P1.0

P1.1

P1.2

P1.3

P1.4

P1.5

P1.6

P1.7

P3.0/RXD

P3.1/TXD

P3.2/INT0

P3.3/INT1

P3.4/T0

P3.5/T1

RESET

RST

Note: 1. The A16 and A17 connections are opt i onal.

2. In non-Page -Mode, AD7- AD0 connects to ADIO7-ADIO0.

P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7

P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6

P2.7

ALE

PSEN

RD/A16

43 42 41

40 39 38 37

24 25

26 27

18 19

RESET

A0 A1 A2 A3 A4 A5 A6 A7

AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15

ALE RD WR A16

A0 A1 A2 A3 A4 A5 A6 A7

AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15

PSD

ADIO0

ADIO1

ADIO2

ADIO3

ADIO4

ADIO5

ADIO6

ADIO7

ADIO8

ADIO9

ADIO10

ADIO11

ADIO12

ADIO13

ADIO14

ADIO15

CNTL0(WR

CNTL1(RD

CNTL2(PSEN)

PD0-ALE

PD1

PD2

RESET

A16

PA0

PA1

PA2

PA3

PA4

PA5

PA6

PA7

PB0

PB1

PB2

PB3

PB4

PB5

PB6

)

PB7

PC0 PC1

PC2

PC3 PC4 PC5 PC6 PC7

20 19 18 17 14 13 12 11

A17

AI02881C

47/110

PSD813F2, PSD833F2, PSD834F 2, PSD853F2, PSD854F2

Figure 23. Interfacing the PSD with the 80C251, with RD and PSEN Inputs

RESET

80C251SB

P1.0

P1.1

P1.2

P1.3

P1.4

P1.5

P1.6

P1.7

P3.0/RXD

P3.1/TXD

P3.2/INT0

P3.3/INT1

P3.4/T0

P3.5/T1

RST

P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7

P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6

P2.7

ALE

PSEN

RD/A16

43 42 41 40 39 38 37 36

24 25 26 27 28 29 30 31

33 32 18 19

RESET

A0 A1 A2 A3 A4 A5 A6 A7

AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15

ALE RD WR PSEN

A0 A1 A2 A3 A4 A5 A6 A7

AD8 AD9 AD10

AD11 AD12 AD13

AD14

AD15

PSD

ADIO0

ADIO1

ADIO2

ADIO3

ADIO4

ADIO5

ADIO6

ADIO7

ADIO8

ADIO9

ADIO10

ADIO11

ADIO12

ADIO13

ADIO14

ADIO15

CNTL0(WR

CNTL1(RD

CNTL2(PSEN)

PD0-ALE

PD1

PD2

RESET

PA0

PA1

PA2

PA3

PA4

PA5

PA6

PA7

PB0

PB1

PB2

PB3

PB4

PB5

PB6

)

PB7

PC0 PC1

PC2

PC3 PC4 PC5 PC6 PC7

20 19 18 17 14 13 12 11

AI02882C

Table 18. 80C251 Configurations

Configuration

80C251 READ/WRI TE

Pins

PSEN

PSEN only

PSEN

Connecting to PSD Pins Page Mode

CNTL0 CNTL1 CNTL2

CNTL0 CNTL1

CNTL0 CNTL1 CNTL2

Non-Page Mode, 80C31 compatible A7A0 multiplex with D7-D0

Non-Page Mode A7-A0 multiplex with D7-D0

Page Mode A15-A8 multiplex with D7-D0

48/110

PSD813F2, PSD833F2, PS D834F2, PSD853F2, PSD854F2

80C51XA

The Philips 80C51XA MCU family supports an 8or 16-bit multiplexed bus that can ha ve burst cycles. Address bits (A3-A0) are not multiplexed, while (A19-A4) are multiplexed with data bits (D15-D0) in 16-bit mode. In 8-bit m ode, (A11-A4) are multiplexed with data bits (D7-D0).

The 80C51XA can be configured to operate in eight-bit data mode (as shown in Figure 24).

The 80C51XA improves bus throughput and performance by executing burst cycles for code fetch-

Figure 24. Interfacing the PSD with the 80C51X, 8-bit Data Bus

es. In Burst Mode, address A19-A4 are latched internally by the PSD, while the 80C51XA changes the A3-A0 signals to f etch up to 16 bytes of code. The PSD access time is then measured from address A3-A0 valid to data in valid. The PSD bus timing requirement in Burst Mode is identical to the normal bus cycle, except the address setup and hold time with respect to Address Strobe (ALE/AS, PD0) does not apply.

RESET

80C51XA

XTAL1

XTAL2

RXD0

TXD0

RXD1

T2EX

RST

INT0

INT1

EA/WAIT

BUSW

TXD1

A0/WRH

A4D0 A5D1 A6D2

A7D3 A8D4

A9D5 A10D6 A11D7 A12D8 A13D9

A14D10 A15D11 A16D12 A17D13 A18D14 A19D15

PSEN

WRL

ALE

RESET

A1 A2 A3

PSD

A4D0

A5D1

A6D2

A7D3

A8D4

A9D5

A10D6

A11D7

A12

A13

A14

A15

A16

A17

A18

A19

PSEN

32 19 18

RD WR

ALE

A4D0 A5D1 A6D2 A7D3 A8D4 A9D5 A10D6

A11D7

A12 A13 A14 A15 A16 A17 A18 A19

ADIO0

ADIO1

ADIO2

ADIO3

AD104

AD105

ADIO6

ADIO7

ADIO8

ADIO9

ADIO10

ADIO11

AD1012

AD1013

ADIO14

ADIO15

CNTL0(WR

CNTL1(RD

CNTL2(PSEN)

PD0-ALE

PD1

PD2

RESET

29 28 27 25

24 23 22 21

7 6 5 4 3

2 52 51

20 19 18 17 14 13 12 11

A0 A1 A2 A3

AI02883C

PA0 PA1

PA2 PA3

PA4 PA5 PA6 PA7

PB0 PB1 PB2 PB3

PB4 PB5 PB6 PB7

)

PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7

49/110

PSD813F2, PSD833F2, PSD834F 2, PSD853F2, PSD854F2

68HC11

Figure 25 shows a bus interface to a 68HC11 where the PSD is configured in 8-bit multiplexed mode with E and R/W settings. The DPLD can be

Figure 25. Interfacing the PSD with a 68HC11

used to generate the READ and WR signal s for extern al device s .

RESET

8 7

17 19 18

34 33 32

43 44 45 46 47 48 49 50

52 51

68HC11

XT EX

RESET IRQ XIRQ

MODB

PA0 PA1 PA2

PE0 PE1 PE2 PE3 PE4 PE5 PE6 PE7

VRH VRL

PA3 PA4 PA5 PA6 PA7

PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7

PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7

PD0 PD1 PD2 PD3 PD4 PD5

MODA

R/W

AD7-AD0

PSD

AD0 AD1

AD2 31 30 29 28 27

42 41 40 39

36 35

AD0

AD1

AD2

AD3

AD4

AD5

AD6

AD7

20 21 22 23 24 25

R/W

AD3

AD4

AD5

AD6

AD7

A10 A11 A12 A13 A14

A15

31 32

33 34 35 36 37

39 40

41 42 43 44 45 46

47 50

9 8

ADIO0 ADIO1 ADIO2 ADIO3 AD104 AD105 ADIO6 ADIO7

ADIO8 ADIO9 ADIO10 ADIO11 AD1012 AD1013 ADIO14 ADIO15

CNTL0(R_W) CNTL1(E)

CNTL2

PD0–AS PD1

PD2

RESET

PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7

PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7

PC0 PC1 PC2 PC3 PC4

PC5 PC6 PC7

29 28 27 25 24 23 22 21

7 6 5 4

3 2 52 51

20 19 18 17 14 13 12 11

50/110

RESET

AI02884C

PSD813F2, PSD833F2, PS D834F2, PSD853F2, PSD854F2

I/O PORT S

There are four programmable I/O ports: Ports A, B, C, and D. Each of the ports is eight bits except Port D, which is 3 bits. Each port pin is individually user configurable, thus allowing multiple functions per port. The ports are configured using PSDsoft Express Configuration or by the MCU writing to onchip registers in the CSIOP space.

The topics discussed in this section are:

■ General Port architecture

■ Port operating modes

■ Port Configuration Registers (PCR)

■ Port Data Registers

■ Individual Port functionality.

General Port Architecture

The general architecture of the I/O Port block is shown in Figure 26., page 52. Individual Port architectures are shown in Figure 28., page 58 to

Figure 31., page 61. In general, once the purpose

for a port pin has been defined, that pin is no longer available for other purposes. Exceptions are noted.

As shown in Figure 26., page 52, the ports contain an output multiplexer whose select signals are driven by the configuration bits in the Control Registers (Ports A and B only) and P SDsoft Express Configuration. Inputs to the multiplexer include the following:

■ Output data from the Data Out register

■ Latched address outputs

■ CPLD macrocell output

■ External Chip Select (ECS0-ECS2) from the

CPLD.

The Port Data Buffer (PDB) is a tri-state buffer that allows only one source at a time to be read. The Port Data Buffer (PDB) is connected to the Internal Data Bus for feedback and can be read by the MCU. The Data Out and macrocell outputs, Direction and Control Registers, and port pin input are all connected to the Port Data Buffer (PDB).

The Port pin’s tri-state output driver enable is controlled by a two input OR gate whose inputs come from the CPLD AND Array enable product term and the Direction Register. If the enable product term of any of the Array outputs are not defined and that port pin is not defined as a CP LD output in the PSDabel file, then the Direction Register has sole control of the buffer that drives the port pin.

The contents of these registers c an be altered by the MCU. The Port Data Buffer (PDB) feedback path allows the MCU to check the contents of the registers.

Ports A, B, and C have embedded Input Macrocells (IMC). The Input Macrocells (IMC) can be configured as latches, registers, or direct inputs to the PLDs. The latches and registers are clocked by Address Strobe (ALE/AS, PD0) or a product term from the PLD AND Array. The outputs from the Input Macrocells (IMC) drive the PLD input bus and can be read by the MCU. See the section entitled Input Macrocell, page 41.

Port Operat in g Modes

The I/O Ports have several modes of operat ion. Some modes can be defined using PSDabel, some by the MCU writing to the Control Registers in CSIOP space, and some by both. The modes that can only be defined using PSDsoft Express must be programmed into the device and cannot be changed unless the device i s reprogrammed. The modes that can be changed by the MCU can be done so dynamically at run-time . The PLD I /O, Data Port, Address Input, and Peripheral I/O modes are the only modes that must be defined before programming the device. All other m odes can be changed by the MCU at run-time. See A pplication Note AN1171 for more detail.

Table 19., page 53 s ummarizes which modes are

available on each port. Table 22., page 56 shows how and where the different modes are configured. Each of the port operating modes are described in the following sections.

51/110

PSD813F2, PSD833F2, PSD834F 2, PSD853F2, PSD854F2

Figure 26. Ge neral I/O P ort Arc hi tec ture

DATA OUT

REG.

ADDRESS ALE

MACROCELL OUTPUTS EXT CS

DGQ

READ MUX

DATA OUT

ADDRESS

OUTPUT

PORT PIN

MUX

INTERNAL DATA BUS

ENABLE PRODUCT TERM (.OE

P D B

CONTROL REG.

DIR REG.

CPLD-INPUT

DATA IN

)

OUTPUT

SELECT

ENABLE OUT

INPUT

MACROCELL

AI02885

52/110

PSD813F2, PSD833F2, PS D834F2, PSD853F2, PSD854F2

MCU I/O Mode

In the MCU I/O mode, the MCU uses the I/O Ports block to expand its own I/O ports. By setting up the CSIOP space, the ports on the PSD are mapped into the MCU address space. The addresses of the ports are listed in Table 7., page 18.

A port pin can be put into MCU I/O mode by writing a 0 to the corresponding bit in the Control Register. The MCU I/O direction may be changed by writing to the corresponding bit in the Direction Register, or by the output enable product term. See the section entitled Peripheral I/O

Mode, page 55. When the pin is configured as an

output, the content of the Data Out Register drives the pin. When configured as an input, the MCU can read the port input through the Data In buffer. See F igure 26., page 52.

Ports C and D do not have Control Registers, and are in MCU I/O mode by default. They can be used for PLD I/O if equations are written for them in PSDabel.

PLD I/ O Mode

The PLD I/O Mode uses a po rt as an i nput to the CPLD’s Input Macrocells (IMC), and/or as an output from the CPLD’s Output Macrocells (OMC). The output can be tri-stated with a control signal. This output enable control signal can be d efined by a product term from the PLD, or by resetting the

corresponding bit in the Direction Register to ’0.’ The corresponding bit in the Direction Register must not be set to '1' if the pin is defined for a PLD input signal in PSDabel. The PLD I/O mode is specified in PSDabel by declaring the port pins, and then writing an equ ation assigning the PLD I/ O to a port.

Address Out Mode

For MCUs with a multiplexed address/data bus, Address Out Mode can be u sed to drive latched addresses on to the port pins. These port pins can, in turn, drive external devices. Either the output enable or the corresponding bits of both the Direction Register and Control Register must be set to a 1 for pins to use Address Out Mode. This must be done by the MCU at run-time. See Table 21 for the address output pin assignments on Ports A and B for various MCUs.

For non-multiplexed 8-bit bus mode , address signals (A7-A0) are available to Port B in Address Out Mode.

Note: Do not drive address signals with Address Out Mode to an external memory device if it is intended for the MCU to Boot from the external device . The MC U m u st fi rs t Bo ot fro m P S D me mo ry so the Direction and Control register bits can be set.

Table 19. Port Operating Modes

Port Mode Port A Port B Port C Port D

MCU I/O Yes Yes Yes Yes PLD I/O

McellAB Outputs McellBC Outputs Additional Ext. CS Outputs PLD Inputs

Address Out Yes (A7 – 0)

Address In Yes Yes Yes Yes Data Port Yes (D7 – 0) No No No Peripheral I/O Yes No No No JTAG ISP No No

Note: 1. Can be mult i p l exed with ot her I/O funct i ons.

Yes No No Yes

Yes Yes No Yes

Yes (A7 – 0) or (A15 – 8)

No Yes No Yes

No No

Yes

No No Yes Yes

53/110

PSD813F2, PSD833F2, PSD834F 2, PSD853F2, PSD854F2

Table 20. Port Operating Mode Settings

Mode

Defined in

PSDabel

MCU I/O Declare pins only

Defined in PSD

Configuration

N/A

Control

Setting

PLD I/O Logic equations N/A N/A Data Port (Port A) N/A Specify bus type N/A N/A N/A N/A

Address Out (Port A,B)

Address In (Port A,B,C,D)

Declare pins only N/A 1

Logic for equation Input Macrocells

N/A N/A N/A N/A N/A

Direction

Setting

1 = output, 0 = input

)

(Note

)

1 (Note

)

Setting

N/A N/A

JTAG Enable

Peripheral I/O (Port A)

JTAG ISP (Note

Note: 1. N/A = Not Applicable

2. The direction of the Port A,B,C, and D pins are controlled by the Direction Register ORed with the individual output enable product term (.oe) fr om the CPLD AND Array.

3. Any of these t hree methods enables the JT A G pi ns on Port C.

Logic equations (PSEL0 & 1)

JTAGSEL

)

N/A N/A N/A PIO bit = 1 N/A

JTAG Configuration

N/A N/A N/A JTAG_Enable

Table 21. I/O Port Latched Address Output Assignments

MCU Port A (PA3-PA0) Port A (PA7-PA4) Port B (PB3-PB0) Port B (PB7-PB4)

8051XA (8-Bit) 80C251

(Page Mode) All Other

8-Bit Multiplexed 8-Bit

Non-Multiplexed Bus

Note: 1. N/A = Not Applicable.

N/A

Address a7-a4 Address a11-a8 N/A

N/A N/A Address a11-a8 Address a15-a12

Address a3-a0 Address a7-a4 Address a3-a0 Address a7-a4

N/A N/A Address a3-a0 Address a7-a4

54/110

PSD813F2, PSD833F2, PS D834F2, PSD853F2, PSD854F2

Address In Mode

For MCUs that have more than 16 address signals, the higher addresse s can be connect ed to Port A, B, C, and D. The address input can be latched in the Input Macrocell (IMC) by Address Strobe (ALE/AS, PD0). Any input that is inclu ded in the DPLD equations for the SRAM, or primary or secondary Flash memory is considered to be an address input.

Data Port Mode

Port A can be used as a data bus port for a MCU with a non-multiplexed address/data bus. The Data Port is connected to the data bus of the MCU. The general I/O functions a re disabl ed in Po rt A if the port is configured as a Data Port.

Figure 27. Peripheral I/O Mode

PSEL0

PSEL

PSEL1

VM REGISTER BIT 7

Peripheral I/O Mode

Peripheral I/O mode can be used to interface with external peripherals. In this mode, all of Port A serves as a tri-state, bi-directional data buffer for the MCU. Peripheral I/O Mode is enabled by setting Bit 7 of the VM Register to a ’1.’ Figure 27 shows how Port A acts as a bi-directional buffer for the MCU data bus if Peripheral I/O Mode is enabled. An equation for PSEL0 and/or PSEL1 must be written in PSDabel. The buffer is tri-stated when PSEL0 or PSEL1 is not active.

D0-D7 DATA BUS

PA0-PA7

AI02886

55/110

PSD813F2, PSD833F2, PSD834F 2, PSD853F2, PSD854F2

JTAG In-System Programming (ISP)

Port C is JTAG compliant, and can be used for InSystem Programming (ISP). You can multiplex JTAG operations with other functions on Port C because In-System Programming (ISP) is not performed in normal Operating mode. For more information on the JTA G Port, see the section ent itled

PROGRAMMING IN-CIRCUIT USING THE JTAG SERIAL INTERFACE, page 69.

Port Configuration Reg ist ers (PCR)

Each Port has a set of Port Configuration Registers (PCR) used for configuration. The contents of the registers can be accessed by the MCU through normal READ/WRITE bus cycles at the addresses given in Table 7., page 18. The ad dresses in Table 7 are the offsets in hexadecimal from the base of the CSIOP register.

The pins of a port are individually configurable and each bit in the register controls its respective pin. For example, Bit 0 in a register refers to Bit 0 of its port. The three Port Configuration Registers (PCR), shown in Table 22, are used for setting the Port configurations. The default Power-up state for each register in Table 22 is 00h.

Control Register

Any bit reset to '0' in the Control Register sets the corresponding port pin to MCU I/O Mode, and a '1' sets it to Address Out Mode. The def ault mode is MCU I/O. Only Ports A an d B have an associated Control Register.

Direction Register

The Direction Register, in conjunction with the output enable (except for Port D), controls the direction of data flow in the I/O P orts. Any bit set t o '1' in the Direction Register causes the corresponding pin to be an output, and any bit set to '0' causes it to be an input. The default mode for all port pins is input.

Figure 28., page 58 and Figure 29., page 59 show

the Port Architecture diagrams for Ports A/B and C, respectively. The direction of data flow for Ports A, B, and C are controlled not only by the direction register, but also by the output enable product term from the PLD AND Array. If the output enable product term is not active, t he Direction Register has sole control of a given pin’s direction.

An example of a configuration for a Port with the three least significant bits set to output and the remainder set to input is shown in Tab le 25. Since Port D only contains three pins (shown i n Figure

31., page 61), the Direction Register for Port D

has only the three least significant bits active.

Drive Select Register

The Drive Select Register configures the pin driver as Open Drain or CMOS f or some port pins, and controls the slew rate for the other port pins. An external pull-up resistor should b e used for pins configured as Open Drain.

A pin can be configured as Open Drain if its corresponding bit in the Drive Select Register is set to a ’1.’ The default pin drive is CMOS.

Note that the slew rate is a measureme nt of the rise and fall times of an output. A higher slew rate means a faster output response and may create more electrical noise. A pin operates in a high slew rate when the corresponding bit in the Drive Register i s set to ’1 . ’ T h e defau lt rate i s slow slew.

Table 26., page 57 shows the Drive Register for

Ports A, B, C, and D. It summarizes which pins can be configured as Open Drain outputs and which pins the slew rate can be set for.

Table 22. Port Configuration Registers (PCR)

Control A,B WRITE/READ Direction A,B,C,D WRITE/READ

Drive Select

Note: 1. See Table 26., p age 57 for Drive Register bi t definition.

A,B,C,D WRITE/READ

Table 23. Port Pin Direction Control, Output Enable P.T. Not Defined

Direction Register Bit Port Pin Mode

0 Input 1 Output

Table 24. Port Pin Direction Control, Output Enable P.T. Defined

Direction

0 0 Input 0 1 Output 1 0 Output 1 1 Output

Output Enable

P.T.

Port Pin Mode

Table 25. Port Direction Assignment Example

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

0 0 0 0 0 1 1 1

56/110

PSD813F2, PSD833F2, PS D834F2, PSD853F2, PSD854F2

Table 26. Drive Register Pin Assignment

Drive

Port A

Port B

Port C

Port D

Note: 1. NA = Not Applicable.

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Open Drain

Slew Rate

Open Drain

Slew Rate

Open Drain

Slew Rate

Open Drain

Slew Rate

Open Drain

Slew Rate

Port Data Registers

The Port Data Registers, shown in Table 27, are used by the MCU to write data to or read data f rom the ports. Table 27 sho ws the register name, t he ports having each register type, a nd M CU access for each register type. The registers are described below.

Data In

Port pins are connected directly to the Data In buffer. In MCU I/O input mode, the pin input is read through the Data In buffer.

Data Out Register

Output Ma cr ocells (OM C). The CPLD Output

Macrocells (OMC) occupy a location in the MCU’s address space. The MCU can read the output of the Output Macrocells (OMC ). If the OMC Mask Register bits are not set, writing to the macrocell loads data to the macrocell flip-flops. See the section entitled P LDS , page 33.

OMC Mask Register

Each OMC Mask Re gister bit corresponds to an Output Macrocell (OMC) flip-flop. When t he OMC Mask Register bit is set to a 1, loading data into the Output Macrocell (OMC) flip-flop is bloc ked. The default value is 0 or unblocked.

Stores output data written by the MCU in the MCU I/O output mode. The contents of the Register are driven out to the pins if the Direction Register or the output enable produ ct term is set to ’1.’ T he contents of the register can also be read back by the MCU.

Table 27. Port Data Registers

Data In A,B,C,D READ – input on pin Data Out A,B,C,D WRITE/READ

Output Macrocell A,B,C

READ – outputs of macrocells WRITE – loading macrocells flip-flop

Mask Macrocell A,B,C

Input Macrocell A,B,C READ – outputs of the Input Macrocells Enable Out A,B,C READ – the output enable control of the port driver

WRITE/READ – prevents loading into a given macrocell

57/110

PSD813F2, PSD833F2, PSD834F 2, PSD853F2, PSD854F2

Input Macrocells (IMC)

The Input Macrocells (IMC) can be used to latch or store external inputs. The outputs of the Input Macrocells (IMC) are routed to the PLD input bus, and can be read by the MCU. See the section entitled PLDS, page 33.

Enable Out

The Enable Out register can be read by the MCU. It contains the output enable values for a given port. A 1 indicates the driver is i n output m ode. A 0 indicates the driver is in tri-state and the pin is in input mode.

Ports A and B – Functionality and Structure

Ports A and B have similar functionality and structure, as shown in Figure 28. The two ports can be configured to perform one or more of the following functions:

■ MCU I/O Mode

■ CPLD Output – Macrocells McellAB7-

McellAB0 can be connected to Port A or Port B. McellBC7-McellBC0 can be connected to Port B or Port C.

■ CPLD Input – Via the Input Macrocells (IMC).

■ Latched Address output – Provide latched

address output as per Table 21., page 54.

■ Address In – Additional high address inputs

using the Input Macrocells (IMC).

■ Open Drain/Slew Rate – pins PA3-PA0 and

PB3-PB0 can be configured to fast slew rate, pins PA7-PA4 and PB7-PB4 can be configured to Open Drain Mode.

■ Data Port – Port A to D7-D0 for 8 bit non-

multiplexed bus

■ Multiplexed Address/Data port for certain

types of MCU bus interfaces.

■ Peripheral Mode – Port A only

Figure 28. Port A and Port B Structur e

DATA OUT

REG.

ADDRESS ALE

MACROCELL OUTPUTS

INTERNAL DATA BUS

ENABLE PRODUCT TERM (.OE

DGQ

READ MUX

P D B

CONTROL REG.

DIR REG.

CPLD- INPUT

DATA OUT

ADDRESS

A[7:0] OR A[15:8

)

DATA IN

]

OUTPUT

MUX

OUTPUT SELECT

ENABLE OUT

INPUT

MACROCELL

PORT

A OR B PIN

AI02887

58/110

PSD813F2, PSD833F2, PS D834F2, PSD853F2, PSD854F2

Port C – Functionality and Structure

Port C can be configured to perform one or more of the following functions (see Figure 29):

■ MCU I/O Mode

■ CPLD Output – McellBC7-McellBC0 outputs

can be connected to Port B or Port C.

■ CPLD Input – via the Input Macrocells (IMC)

■ Address In – Additional high address inputs

using the Input Macrocells (IMC).

■ In-System Programming (ISP) – JTAG port

can be enabled for programming/erase of the PSD device. (See the section entitled

PROGRAMMING IN-CIRCUIT USING THE JTAG SERIAL INTERFACE, page 69 for

more information on JTAG programming.)

Figure 29. Port C Stru ct ure

DATA OUT

REG.

MCELLBC[7:0

SPECIAL FUNCTION

]

■ Open Drain – Port C pins can be configured in

Open Drain Mode

■ Battery Backup features – PC2 can be

configured for a battery input supply, Voltage Stand-by (V

STBY

PC4 can be configured as a Battery-on Indicator (V V

BAT

), indicating when VCC is less than

BATON

Port C does not support Address Out mode, and therefore no Control Register is required.

Pin PC7 may be configured as the DBE input in certain MCU bus interfaces.

DATA OUT

OUTPUT

MUX

PORT C PIN

INTERNAL DATA BUS

ENABLE PRODUCT TERM (.OE

READ MUX

DIR REG.

CPLD- INPUT

OUTPUT

DATA IN

)

SELECT

ENABLE OUT

SPECIAL FUNCTION

INPUT

MACROCELL

CONFIGURATION

BIT

AI02888B

59/110

PSD813F2, PSD833F2, PSD834F 2, PSD853F2, PSD854F2

Port D – Functionality and Structure

Port D has three I/O pins. S ee F igure 30 and Fig-

ure 31., page 61. This port does not support Ad-

dress Out mode, and therefore no Control Register is required. Port D can be configured to perform one or more of the following functions:

■ MCU I/O Mode

■ CPLD Output – External Chip Select (ECS0-

ECS2)

■ CPLD Input – direct input to the CPLD, no

Input Macrocells (IMC)

Figure 30. Port D Stru ct ure

DATA OUT

REG.

ECS[2:0

]

READ MUX

■ Slew rate – pins can be set up for fast slew

rate

Port D pins can be configured in PSDsoft Express as input pins for other dedicated functions:

■ Address Strobe (ALE/AS, PD0)

■ CLKIN (PD1) as input to the macrocells flip-

flops and APD counter

■ PSD Chip Select Input (CSI, PD2). Driving this

signal High disables the Flash memory, SRAM and CSIOP.

DATA OUT

OUTPUT

MUX

PORT D PIN

INTERNAL DATA BUS

P D B

DIR REG.

DATA IN

OUTPUT

SELECT

CPLD- INPUT

ENABLE PRODUCT

TERM (.OE)

AI02889

60/110

PSD813F2, PSD833F2, PS D834F2, PSD853F2, PSD854F2

External Chip Select

The CPLD also provides three External Chip Select (ECS0-ECS2) outputs on Port D pins that can be used to select ext ernal devices . E ac h Ex te rnal Chip Select (ECS0-ECS2) consists of one product

Figure 31. Port D External Chip Select Signals

term that can be configured active High or Low. The output enable of the pin is controlled by either the output enable product term or the Direction Register. (See Figure 31.)

PLD INPUT BUS

PT0

POLARITY

CPLD AND ARRAY

PT1

POLARITY

PT2

POLARITY

BIT

ENABLE (.OE)

ECS0

ECS1

ECS2

DIRECTION

PD0 PIN

PD1 PIN

PD2 PIN

AI02890

61/110

PSD813F2, PSD833F2, PSD834F 2, PSD853F2, PSD854F2

POWER MA NAGEMEN T

All PSD devices offer configurable power saving options. These options may be used individually or in combinations, as follows:

■ All memory blocks in a PSD (primary and

secondary Flash memory, and SRAM) are built with power management technology. In addition to using special silicon design methodology, power management technology puts the memories into standby mode when address/data inputs are not changing (zero DC current). As soon as a transition occurs on an input, the affected memory “wakes up”, changes and latches its outputs, then goes back to standby. The designer does not have to do anything special to achieve memory standby mode when no inputs are changing— it happens automatically.

The PLD sections can also achieve Stand-by mode when its inputs are not changing, as described in the sections on the Power Management Mode Registers (PMMR).

■ As with the Power Management mode, the

Automatic Power Down (APD) block allows the PSD to reduce to stand-by current automatically. The APD Unit can also block MCU address/data signals from reaching the memories and PLDs. This feature is available on all the devices of the PSD family. The APD Unit is described in more detail in the sections entitled Automatic Power-down (APD) Unit

and Power-down Mode, page 63.

Built in logic monitors the Address Strobe of the MCU for activity. If there is no activity for a certain time period (MCU is asleep), the APD Unit initiates Power-down mode (if enabled). Once in Power-down mode, all address/data signals are blocked from reaching PSD memory and PLDs, and the memories are deselected internally. This allows the memory and PLDs to

remain in standby mode even if the address/ data signals are changing state externally (noise, other devices on the MCU bus, etc.). Keep in mind that any unblocked PLD input signals that are changing states keeps the PLD out of Stand-by mode, but not the memories.

■ PSD Chip Select Input (CSI, PD2) can be

used to disable the internal memories, placing them in standby mode even if inputs are changing. This feature does not block any internal signals or disable the PLDs. This is a good alternative to using the APD Unit. There is a slight penalty in memory access time when PSD Chip Select Input (CSI makes its initial transition from deselected to selected.

■ The PMMRs can be written by the MCU at run-

time to manage power. All PSD supports “blocking bits” in these registers that are set to block designated signals from reaching both PLDs. Current consumption of the PLDs is directly related to the composite frequency of the changes on their inputs (see Figure 35 and

Figure 36., page 72). Significant power

savings can be achieved by blocking signals that are not used in DPLD or CPLD logic equations.

PSD devices have a Turbo Bit in PMMR0. This bit can be set to turn the Turbo mode off (the default is with Turbo mode turned on). While Turbo mode is off, the PLDs can achieve standby current when no PLD inputs are changing (zero DC current). Even when inputs do change, significant power can be saved at lower frequencies (AC current), compared to when Turbo mode is on. When the Turbo mode is on, there is a significant DC current component and the AC component is higher.

, PD2)

62/110

PSD813F2, PSD833F2, PS D834F2, PSD853F2, PSD854F2

Automatic Power-down (APD) Unit and Power-down Mode

The APD Unit, shown in Figure 32, puts the PSD into Power-down mode by monitoring the activity of Address Strobe (ALE/AS, PD0). If the APD Unit is enabled, as soon as act ivity on A ddress S trobe (ALE/AS, PD0) stops, a four bit counter starts counting. If Address Strobe (ALE/AS, PD0) remains inactive for fifteen clock periods of CLKIN (PD1), Power-down (PDN) goes High, and the PSD enters Power-down mode, as discussed next.

Power -down Mode. By default, if you enable the APD Unit, Power-down mode is automatically enabled. The device enters Power-down mode if Address Strobe (ALE/AS, PD0) remains inactive for fifteen periods of CLKIN (PD1).

The following should be kept in mind when the PSD is in Power-down mode:

– If Address Strobe (ALE/AS, PD0) starts

pulsing again, the PSD returns to normal Operating mode. The PSD also returns to normal Operating mode if either PSD Chip Select Input (CSI (RESET

) input is High.

, PD2) is Low or the Reset

– The MCU address/data bus is blocked from all

memory and PLDs.

– Various signals can be blocked (prior to

Power-down mode) from entering the PLDs by setting the appropriate bits in the PMMR

registers. The blocked signals include MCU control signals and the common CLKIN (PD1). Note that blocking CLKIN (PD1) from the PLDs does not block CLKIN (PD1) from the APD Unit.

– All PSD memories enter Standby mode and

are drawing standby current. However, the PLD and I/O ports blocks do not go into Standby Mode because you don’t want to have to wait for the logic and I/O to “wake-up” before their outputs can change. See Table 28 for Power-down mode effects on PSD ports.

– Typical standby current is of the order of

microamperes. These standby current values assume that there are no transitions on any PLD input.

Table 28. Powe r-down Mode ’ s Eff ect on Ports

MCU I/O No Change PLD Out No Change Address Out Undefined Data Port Tri-State Peripheral I/O Tri-State

Port Function Pin Level

Figure 32. APD Unit

APD EN PMMR0 BIT 1=1

ALE

RESET

CSI

CLKIN

TRANSITION DETECTION

EDGE

DETECT

DISABLE FLASH/EEPROM/SRAM

CLR

APD

COUNTER

DISABLE BUS INTERFACE

PLD

EEPROM SELECT FLASH SELECT

SRAM SELECT

POWER DOWN (

)

SELECT

PDN

AI02891

Tabl e 29. PSD Ti m ing and S t and-b y C urrent during Power- down Mode

Mode

Power-down

Note: 1. Power-do wn does not affect t h e operat i o n of the PL D. T he PLD ope ra t i on in thi s m ode is based only on the Turb o Bit.

2. Typical current consumption assuming no PLD i nputs are changing stat e and the PLD Turbo Bit is ’0. ’

PLD Propagation

Delay

Normal t

(Note 1)

Memory

Access Time

No Access

Access Recovery Time

to Normal Access

LVDV

Typical Stand-by Current

5V V

75µA (Note 2) 25µA (Note 2)

3V V

63/110

PSD813F2, PSD833F2, PSD834F 2, PSD853F2, PSD854F2

For Users of the HC11 (or compatible)

The HC11 turns off its E clock when it sleeps. Therefore, if you are using an HC11 (or compatible) in your design, and y ou wish to use the Power-down mode, you m ust not conn ect the E clock to CLKIN (PD1). You should instead connect a crystal oscil lator to CLKIN (PD1). The crystal oscil lator frequency must be less than 15 times the frequency of AS. The reason for this is that if the frequency is greater than 15 times the frequency of AS, the PSD keeps going into Power-down mode.

Other Power Savi ng Op t ions

The PSD offers ot her reduced power saving options that are independent of the Power-down mode. Except for the SRAM Stand-by and PSD Chip Select Input (CSI

, PD2) features, they are en-

abled by setting bits in PMMR0 and PMMR2.

Figure 33. Enable Power-down Flow Chart

RESET

Enable APD

Set PMMR0 Bit 1 = 1

OPTIONAL

Disable desired inputs to PLD by setting PMMR0 bits 4 and 5

and PMMR2 bits 2 through 6.

PLD Po w e r Mana ge ment

The power and speed of the PLDs are controlled by the Turbo Bit (Bit 3) i n PMMR0. B y setting the bit to '1,' the Turbo mode is off and the PLDs consume the specified stand-by curren t when the inputs are not switching for an extended time of 70ns. The propagation delay time is increased by 10ns after the Turbo Bit is set to '1' (turned off) when the inputs change at a composite frequency of less than 15 MHz. When the Turbo Bit is reset to '0' (turned on), the PLDs run at full power and speed. The Turbo Bit affects the PLD’s DC power, AC power, and propagation delay.

Blocking MCU control signals with the bits of PMMR2 can further reduce PLD AC power consumption.

SRAM Standby Mode (Battery Backup). The PSD supports a battery backup mode in which the contents of the SRAM are retained in the eve nt of a power loss. The SRAM has Voltage Stand-by (V battery. When V

, PC2) that can be connected to an external

STBY

becomes lower than V

STBY

then the PSD automatically connects to Voltage Stand-by (V SRAM. The SRAM Standby Current (I

, PC2) as a power source to the

STBY

) is typically 0.5µA. The SRAM data retention voltage is 2V minimum. The Battery-on I ndicator (VBAT ON) can be routed to PC4. This s ignal indicates when the V

has dropped below V

STBY

64/110

ALE/AS idle

for 15 CLKIN

clocks?

Yes

PSD in Power

Down Mode

AI02892

PSD813F2, PSD833F2, PS D834F2, PSD853F2, PSD854F2

Table 30. Power Management Mode Regi sters PMM R0 (Note 1)

Bit 0 X 0 Not used, and should be set to zero.

Bit 1 APD Enable

Bit 2 X 0 Not used, and should be set to zero.

Bit 3 PLD Turbo

Bit 4 PLD Array clk

Bit 5 PLD MCell clk

Bit 6 X 0 Not used, and should be set to zero. Bit 7 X 0 Not used, and should be set to zero.

Note: 1. The bits of this register are cleared to zero following Power-up. Subsequent Reset (RESET) pulses do not clear th e registers.

0 = off Automatic Power-down (APD) is disabled. 1 = on Automatic Power-down (APD) is enabled.

0 = on PLD Turbo mode is on 1 = off PLD Turbo mode is off, saving power.

0 = on

1 = off CLKIN (PD1) input to PLD AND Array is disconnected, saving power. 0 = on CLKIN (PD1) input to the PLD macrocells is connected. 1 = off CLKIN (PD1) input to PLD macrocells is disconnected, saving power.

CLKIN (PD1) input to the PLD AND Array is connected. Every change of CLKIN (PD1) Powers-up the PLD when Turbo Bit is ’0.’

Table 31. Power Management Mode Regi sters PMM R2 (Note 1)

Bit 0 X 0 Not used, and should be set to zero. Bit 1 X 0 Not used, and should be set to zero.

Bit 2

Bit 3

Bit 4

PLD Array CNTL0

PLD Array CNTL1

PLD Array CNTL2

0 = on Cntl0 input to the PLD AND Array is connected. 1 = off Cntl0 input to PLD AND Array is disconnected, saving power. 0 = on Cntl1 input to the PLD AND Array is connected. 1 = off Cntl1 input to PLD AND Array is disconnected, saving power. 0 = on Cntl2 input to the PLD AND Array is connected. 1 = off Cntl2 input to PLD AND Array is disconnected, saving power.

Bit 5

Bit 6

Bit 7 X 0 Not used, and should be set to zero.

Note: 1. The bits of this register are cleared to zero following Power-up. Subsequent Reset (RESET) pulses do not clear th e registers.

PLD Array ALE

PLD Array DBE

0 = on ALE input to the PLD AND Array is connected. 1 = off ALE input to PLD AND Array is disconnected, saving power. 0 = on DBE input to the PLD AND Array is connected. 1 = off DBE input to PLD AND Array is disconnected, saving power.

65/110

PSD813F2, PSD833F2, PSD834F 2, PSD853F2, PSD854F2

PSD Chip Select Input (CSI, PD2)

PD2 of Port D can be c onfigured in PSDsoft Express as PSD Chip Select Input (CSI

). When Low, the signal selects and enables the internal Flash memory, EEPROM, SRAM, and I/O blocks for READ or WRITE operations involving the PSD. A High on PSD Chip Select Input (CSI

, PD2) disables the Flash memory, EEPROM, and SRAM, and reduces the PSD power consum ption. However, the PLD and I/O signals remain operational when PSD Chip Select Input (CSI

, PD2) is High.

There may be a timing pena lty when using PSD Chip Select Input (CSI

, PD2) depending on the speed grade of the PSD that you are using. See the timing parameter t

in Table 61., page 94

SLQV

or Table 62., page 95 .

Input Clock

The PSD provides the option to turn off CLKIN (PD1) to the PLD to save AC power consumption. CLKIN (PD1) is an input to the PLD AND Array and the Output Macrocells (OMC).

During Power-down mode, or, if CLKIN (PD1) is not being used as part of the PLD logic equation, the clock should be disabled to save AC power. CLKIN (PD1) is disconnected from the PLD AND Array or the Macrocells block by setting Bits 4 or 5 to a 1 in PMMR0.

Input Cont rol Signals

The PSD provides the op tion to turn off the input control signals (CNTL0, CNTL1, CNTL2, Address Strobe (ALE/AS, PD0) and DBE) to the PLD to save AC power consumption. These control signals are inputs to the PLD AND Array. During Power-down mode, or, if any of them are not being used as part of the PLD logic equation, these control signals should be disabled to save AC power. They are disconnected from the PLD AND Array by setting Bits 2, 3, 4, 5, and 6 to a 1 in PMMR2.

Table 32. APD Counter Operation

APD Enable Bit ALE PD Polarity ALE Level APD Counter

0 X X Not Counting 1 X Pulsing Not Counting 1 1 1 Counting (Generates PDN after 15 Clocks) 1 0 0 Counting (Generates PDN after 15 Clocks)

66/110

PSD813F2, PSD833F2, PS D834F2, PSD853F2, PSD854F2

RESET TIMING AND DEVICE STATUS AT RESET

Power-Up Reset

Upon Power-up, the PSD requi res a Reset (RESET) pulse of duration t

NLNH-PO

after VCC is steady. During this period, the device l oads internal configurations, clears some of the registers and sets the Flash memory into Operating m ode. After the rising edge of Reset (RESET

), the PSD remains in the Reset mode for an additional period, t

, before the first memory access is al-

OPR

lowed. The Flash memory is reset to the READ Mode

upon Power-up. Sector Select (FS0-FS7 and CSBOOT0-CSBOOT3) must all be Low, Write Strobe (WR

, CNTL0) High, during Power On Reset for maximum security of the data contents and to remove the possibility of a byte being written on the first edge of Write Strobe (WR

, CNT L0). An y Flash memory WRITE cycl e initiation is pr eve n ted automatically when V

is below V

LKO

Warm Reset

Once the device is up and running, the device can be reset with a pulse of a m uch shorter duration,

NLNH

The same t is operational after warm reset. Fi gure 34 shows the timing of the Power-up and warm reset.

I/O Pin, Register and PLD Status at Reset

Table 33., page 68 shows the I/O pin, register and

PLD status during Power On Reset, warm reset and Power-down mode. PLD outputs are always valid during warm reset, and they are valid in Power On Reset once the internal PSD Configuration bits are loaded. This loading of PSD is completed typically long before t he V ing level. Once the P LD is active, the state of t he outputs are determined by the PSDabel equations.

Reset of Flash Memory Erase and Program Cycles (on the PSD834Fx)

A Reset (RESET memory state machine. During a Flash memory Program or Erase cycle, Reset (RESET nates the cycle and returns the Flash memory t o the Read Mode within a period of t

period is needed before the device

OPR

ramps up to operat-

) also resets the internal Flash

NLNH-A

) termi-

Figure 34. Reset (RESET

RESET

VCC(min)

Power-On Reset

) Timing

NLNH-PO

OPR

NLNH

NLNH-A

Warm Reset

OPR

AI02866b

67/110

PSD813F2, PSD833F2, PSD834F 2, PSD853F2, PSD854F2

Table 33. Status During Power-On Reset, Warm Reset and Power-down Mode

Port Configuration Power-On Reset Warm Reset Power-down Mode

MCU I/O Input mode Input mode Unchanged

Valid after internal PSD

PLD Output

Address Out Tri-stated Tri-stated Not defined Data Port Tri-stated Tri-stated Tri-stated Peripheral I/O Tri-stated Tri-stated Tri-stated

PMMR0 and PMMR2 Cleared to '0' Unchanged Unchanged

configuration bits are loaded

Valid

Depends on inputs to PLD (addresses are blocked in PD mode)

Macrocells flip-flop status

VM Register

All other registers Cleared to '0' Cleared to '0' Unchanged

Note: 1. The SR_cod and PeriphMode bits in the VM Register are always clea red to '0' on Po wer-On Res e t or Warm Rese t.

Cleared to '0' by internal Power-On Reset

Initialized, based on the selection in PSDsoft Configuration menu

Depends on .re and .pr equations

Initialized, based on the selection in PSDsoft Configuration menu

Depends on .re and .pr equations

Unchanged

68/110

PSD813F2, PSD833F2, PS D834F2, PSD853F2, PSD854F2

PROGRAMMING IN-CIRCUIT USING THE JTAG SERIAL INTERFACE

The JTAG Serial Interface block can be enabled on Port C (see Table 34., page 70). All memory blocks (primary and secondary Flash memory), PLD logic, and PSD Configuration Register bits may be programmed through the JTAG Serial Interface block. A blank device can be mounted on a printed circuit board and programmed using JTAG.

The standard JTAG signals (IEEE 1149.1) are TMS, TCK, TDI, and TDO. Two additional signals, TSTAT used to speed up Program and Erase cycles.

By default, on a blank PSD (as shipped from the factory or after erasure), four pins on Port C are enabled for the basic JTAG signals TMS, TCK, TDI, and TDO.

See Application Not e AN1153 for more details on JTAG In-System Programming (ISP).

Standard JTAG Signals

The standard JTAG signals (TMS, TCK, TDI, and TDO) can be enabled by any of three different conditions that are logically ORed. When enabled, TDI, TDO, TCK, and TMS are inputs, waiting for a JTAG serial command from an external JTAG controller device (such as FlashLINK or Automated Test Equipment). When the e nabli ng c om ma nd is received, TDO becomes an ou tput and the JTAG channel is fully functional inside the PSD. The same command t hat enables the JTAG channel may optionally enable the two additional JTAG signals , TSTAT

The following symbolic logic equation specifies the conditions enabling the four basic JTAG signals (TMS, TCK, TDI, and TDO) on their respective Port C pins. For purposes of discussion, the logic label JTAG_ON is used. When JTAG_ON is true, the four pins are enabled for JTAG. When JTAG_ON is false, the four pins can be us ed for general PSD I/O.

JTAG_ON = PSDsoft_enabled +

and TERR, are opt ional JTAG extens ions

and TERR.

/* An NVM configuration bit inside the

PSD is set by the designer in the PSDsoft Express Configuration utility.

This dedicates the pins for JTAG at all times (compliant with IEEE 1149.1 */

Microcontroller_enabled +

/* The microcontroller can set a bit at

run-time by writing to the PSD register, JTAG Enable. This register is located at address CSIOP + offset C7h. Setting the JTAG_ENABLE bit in this register will enable the pins for JTAG use. This bit is cleared by a PSD reset or the microcontroller. See Table

35., page 71 for bit definition. */

PSD_product_term_enabled;

/* A dedicated product term (PT) inside

the PSD can be used to enable the JTAG pins. This PT has the reserved name JTAGSEL. Once defined as a node in PSDabel, the designer can write an equation for JTAGSEL. This method is used when the Port C JTAG pins are multiplexed with other I/O signals. It is recommended to logically tie the node JTAGSEL to the JEN\ signal on the Flashlink cable when multiplexing JTAG signals. See Application Note 1153 for details. */

The state of the PSD Reset (RESET not interrupt (or prevent) JTAG ope rations if the JTAG pins are dedicated by an NVM configuration bit (via PSDsoft Express). However, Reset (RESET) w ill prevent or interrupt JT AG operations if the JTAG enable register is used to enable the JTAG pins.

The PSD supports JTAG In-System-Configuration (ISC) commands, but not Boundary Scan. The PSDsoft Express software tool and FlashLI NK JTA G programming cable implem ent the JTAG In-System-Configuration (ISC) commands. A definition of these JTAG In-System-Configuration (ISC) commands and sequences is define d in a supplemental document available from ST. This document is needed only as a reference for designers who use a FlashLINK to program their PSD.

) signal does

69/110

PSD813F2, PSD833F2, PSD834F 2, PSD853F2, PSD854F2

JTAG Extensions

TSTAT

and TERR are two JTAG extension signals enabled by an “ISC_ENABLE” command received over the four standard JTAG signals (TMS , TCK, TDI, and TDO). They are used to speed Program and Erase cycles by indicating status on PSD signals instead of having to scan the status ou t serially using the standard JTAG channel. See Application Note AN1153.

indicates if an error has occurred when

TERR erasing a sector or programming a byte in F lash memory. This signal goes Low (active) when an Error condition occurs, and stays Low until an “ISC_CLEAR” command is executed or a chip Reset (RESET

) pulse is received after an

“ISC_DISABLE” command. TSTAT

behaves the same as Ready/Busy described in the section entitled Ready/B us y

(PC3), page 20. TSTAT

is High when the PSD device is in READ Mode (primary and secondary Flash memory contents can be read). TSTAT

is Low when Flash memory Program or Erase cycles are in progress, and al so when dat a is bei ng wri tten to the secondary Flash memory.

TSTAT

and TERR can be configured as opendrain type signals during an “ISC_ENABLE” command. This facilitates a wired-OR connection of TSTAT wired-OR connection of TERR

signals from multiple PS D devices and a

signals from thos e same devices. This is u seful when several PSD devices are “chained” together in a JTAG environment.

Security and Flash memory Protection

When the security bit is set, the device cannot be read on a Device Programmer or through the JTAG Port. When using the JTAG Port, only a Full Chip Erase command is allowed.

All other Program, Erase and Verify commands are blocked. Full Chip Erase returns the part to a non-secured blank state. The Security B it can be set in PSDsoft Express Configuration.

All primary and secondary Flash memory sectors can individually be sector protec ted against erasures. The sector protect bits can be set in PSDsoft Express Configuration.

Table 34. JTAG Port Signals

Port C Pin JTAG Signals Description

PC0 TMS Mode Select PC1 TCK Clock PC3 TSTAT PC4 TERR PC5 TDI Serial Data In PC6 TDO Serial Data Out

Status Error Flag

70/110

PSD813F2, PSD833F2, PS D834F2, PSD853F2, PSD854F2

INITIAL DELIVERY STATE

When delivered from ST, the PSD device has all bits in the memory and PLDs set to ’1.’ The PSD Configuration Register bits are set to ’0.’ The code, configuration, and PLD l ogic are load ed us in g the

Table 35. JTAG Enable Register

0 = off JTAG port is disabled.

Bit 0 JTAG_Enable

1 = on JTAG port is enabled. Bit 1 X 0 Not used, and should be set to zero. Bit 2 X 0 Not used, and should be set to zero. Bit 3 X 0 Not used, and should be set to zero. Bit 4 X 0 Not used, and should be set to zero. Bit 5 X 0 Not used, and should be set to zero. Bit 6 X 0 Not used, and should be set to zero. Bit 7 X 0 Not used, and should be set to zero.

Note: 1. The state of Reset (RESET) does not interrupt (or prevent) JTAG operations if the JTAG signals are dedicated by an NVM Config-

uration bit (via PSDsoft Express). However, Reset (RESET used to enable the JTAG sig nal s.

programming procedure. Information for programming the device is available directly from ST. Please contact your local sales representative.

) prevents or interr upts JTAG operations i f the JTAG en abl e register is

71/110

PSD813F2, PSD833F2, PSD834F 2, PSD853F2, PSD854F2

AC/DC PARAMETE RS

These tables describe the AD and DC parameters of the PSD:

❏ DC Electrical Specification ❏ AC Timing Specification

■ PLD Timing

– Combinatorial Timing – Synchronous Clock Mode – Asynchronous Clock Mode – Input Macrocell Timing

■ MCU Timing

– READ Timing –WRITE Timing – Periph e ra l Mode Timing

– Power-down and Reset Timing

The following are issues con cerning the param eters presented:

– In the DC specification the supply current is

given for different modes of operation. Before calculating the total power consumption, determine the percentage of time that the PSD is in each mode. Also, the supply power is considerably different if the Turbo Bit is ’0.’

– The AC power component gives the PLD,

Flash memory, and SRAM mA/MHz specification. Figures 35 and 36 show the PLD mA/MHz as a function of the number of Product Terms (PT) used.

– In the PLD timing parameters, add the

required delay when Turbo Bit is ’0.’

Figure 35. PLD I

Figure 36. PLD I

/Frequen cy C onsumptio n ( 5V range)

110 100

= 5V

90 80 70

– (mA)

40 30

20 10

010155 20 25

HIGHEST COMPOSITE FREQUENCY AT PLD INPUTS (MHz)

/Frequen cy C onsumptio n ( 3V range)

= 3V

TURBO OFF

)

(100%

TURBO ON (100%)

TURBO ON (25%)

PT 100% PT 25%

AI02894

72/110

– (mA)

010155 20 25

HIGHEST COMPOSITE FREQUENCY AT PLD INPUTS (MHz)

)

PT 100% PT 25%

AI03100

PSD813F2, PSD833F2, PS D834F2, PSD853F2, PSD854F2

Table 36. Example of PSD Typical Power Calculation at VCC = 5.0V (Turbo Mode On)

Conditions

Highest Composite PLD input frequency

(Freq PLD) = 8 MHz

MCU ALE frequency (Freq ALE) = 4 MHz

% Flash memory Access = 80% % SRAM access = 15% % I/O access = 5% (no additional power above base)

Operational Mode s

% Normal = 10% % Power-down Mode = 90%

Number of product terms used

(from fitter report) = 45 PT % of total product terms = 45/182 = 24.7% Turbo Mode = ON

Calculation (using typical values)

total = Ipwrdown x %pwrdown + %normal x (ICC (ac) + ICC (dc))

= Ipwrdown x %pwrdown + % normal x (%flash x 2.5mA/MHz x Freq ALE

+ %SRAM x 1.5mA/MHz x Freq ALE + % PLD x 2mA/MHz x Freq PLD + #PT x 400µA/PT)

= 50µA x 0.90 + 0.1 x (0.8 x 2.5mA/MHz x 4 MHz

+ 0.15 x 1.5mA/MHz x 4 MHz + 2mA/MHz x 8 MHz

+ 45 x 0.4mA/PT) = 45µA + 0.1 x (8 + 0.9 + 16 + 18mA) = 45µA + 0.1 x 42.9 = 45µA + 4.29mA = 4.34mA

This is the operating power with no EEPROM WRITE or Flash memory Erase cycles in progress. Calculation is based on I

= 0mA.

OUT

73/110

PSD813F2, PSD833F2, PSD834F 2, PSD853F2, PSD854F2

Table 37. Example of PSD Typical Power Calculation at VCC = 5.0V (Turbo Mode Off)

Conditions

Highest Composite PLD input frequency

(Freq PLD) = 8 MHz

MCU ALE frequency (Freq ALE) = 4 MHz

% Flash memory Access = 80% % SRAM access = 15% % I/O access = 5% (no additional power above base)

Operational Mode s

% Normal = 10% % Power-down Mode = 90%

Number of product terms used

(from fitter report) = 45 PT % of total product terms = 45/182 = 24.7% Turbo Mode = Off

Calculation (using typical values)

total = Ipwrdown x %pwrdown + %normal x (ICC (ac) + ICC (dc))

= Ipwrdown x %pwrdown + % normal x (%flash x 2.5mA/MHz x Freq ALE

+ %SRAM x 1.5mA/MHz x Freq ALE

+ % PLD x (from graph using Freq PLD)) = 50µA x 0.90 + 0.1 x (0.8 x 2.5mA/MHz x 4 MHz

+ 0.15 x 1.5mA/MHz x 4 MHz

+ 24mA) = 45µA + 0.1 x (8 + 0.9 + 24) = 45µA + 0.1 x 32.9 = 45µA + 3.29mA = 3.34mA

This is the operating power with no EEPROM WRITE or Flash memory Erase cycles in progress. Calculation is based on I

= 0mA.

OUT

74/110

PSD813F2, PSD833F2, PS D834F2, PSD853F2, PSD854F2

MAXIMUM RA T ING

Stressing the device above the rating l isted in the Absolute Maximum Ratings” table may cause permanent damage to the device. These are stress ratings only and operation of the device at t hese or any other conditions ab ove those i ndicated in t he Operating sections of this specificat ion is not im-

Table 38. Absolute Maximum Ratings

Symbol Parameter Min. Max. Unit

plied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevan t quality documents.

STG

LEAD

ESD

Note: 1. IPC/JEDEC J-STD-020A

2. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 Ω, R2=500 Ω)

Storage Temperature –65 125 °C Lead Temperature during Soldering (20 seconds max.)

Input and Output Voltage (Q = VOH or Hi-Z) Supply Voltage –0.6 7.0 V Device Programmer Supply Voltage –0.6 14.0 V

Electrostatic Discharge Voltage (Human Body model)

–0.6 7.0 V

–2000 2000 V

235 °C

75/110

PSD813F2, PSD833F2, PSD834F 2, PSD853F2, PSD854F2

DC AND AC PARAMETERS

This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC Characteristic tables that follow are derived from tests performed under the Measure-

Table 39. Operating Conditions (5V devices)

Symbol Parameter Min. Max. Unit

ment Conditions summarized in the relevant tables. Designers should check that the operating conditions in their circuit match t he measurem ent conditions when relying on the quoted parameters.

Supply Voltage 4.5 5.5 V Ambient Operating Temperature (industrial) –40 85 °C Ambient Operating Temperature (commercial) 0 70 °C

Table 40. Operating Conditions (3V devices)

Symbol Parameter Min. Max. Unit

Table 41. AC Signal Letters for PLD Timing

A Address Input C CEout Output D Input Data E E Input G Internal WDOG_ON signal

I Interrupt Input L ALE Input N RESET P Port Signal Output

Supply Voltage 3.0 3.6 V Ambient Operating Temperature (industrial) –40 85 °C Ambient Operating Temperature (commercial) 0 70 °C

Table 42. AC Signal Behavior Symbols for PLD Timing

tTime

L Logic Level Low or ALE

H Logic Level High

V Valid X No Longer a Valid Logic Level ZFloat

Input or Output

PW Pulse Width

Note : Ex a mple : t

= Time from Address Valid to ALE Inva l id.

AVLX

QOutput Data RWR S Chip Select Input TR/W

W Internal PDN Signal

M Output Macrocell

Note : Ex a mple : t

, UDS, LDS, DS, IORD, PSEN Inputs

Input

Output

STBY

= Time from Address Valid to ALE Invalid.

AVLX

Table 43. AC Measurement Conditions

Symbol Parameter Min. Max. Unit

Note: 1. Output H i- Z i s defined as th e poi nt where da ta out is no longe r dri v en.

76/110

Load Capacitance 30 pF

PSD813F2, PSD833F2, PS D834F2, PSD853F2, PSD854F2

Table 44. Capacitance

Symbol Parameter Test Condition

C C

OUT

VPP

Input Capacitance (for input pins) Output Capacitance (for input/

output pins) Capacitance (for CNTL2/VPP)V

Note: 1. Sampled only, not 100% tested.

2. Typical val ues are for T

= 25°C and nominal supply voltages.

OUT

= 0V

Figure 37. AC Measurem ent I/O W av eform Fi gure 38. AC Mea surement Lo ad C ir cui t

Typ.

Max. Unit

46 812

18 25

2.01 V

pF pF

3.0V Test Point 1.5V

Figure 39. Switching Waveforms – Key

WAVEFORMS

AI03103b

Device

Under Test

INPUTS OUTPUTS

STEADY INPUT

MAY CHANGE FROM HI TO LO

MAY CHANGE FROM LO TO HI

DON'T CARE

STEADY OUTPUT

WILL BE CHANGING FROM HI TO LO

WILL BE CHANGING LO TO HI

CHANGING, STATE UNKNOWN

195 Ω

= 30 pF

(Including Scope and Jig Capacitance)

AI03104b

OUTPUTS ONLY

CENTER LINE IS TRI-STATE

AI03102

77/110

PSD813F2, PSD833F2, PSD834F 2, PSD853F2, PSD854F2

Table 45. DC Characteristics (5V devices)

Test Condition

Symbol Parameter

IH1

IL1

HYS

LKO

OH1

STBY

IDLE

Input High Voltage Input Low Voltage Reset High Level Input Voltage

Reset Low Level Input Voltage Reset Pin Hysteresis 0.3 V VCC (min) for Flash Erase and

Program

Output Low Voltage

Output High Voltage Except V

STBY

Output High Voltage V

On I

STBY

SRAM Stand-by Voltage 2.0 SRAM Stand-by Current Idle Current (V

input) VCC > V

STBY

SRAM Data Retention Voltage Stand-by Supply Current

for Power-down Mode Input Leakage Current Output Leakage Current

PLD Only

(DC)

(Note 5)

Operating Supply Current

Flash memory

SRAM f = 0 MHz 0 0 mA

PLD AC Adder

(AC)

Flash memory AC Adder 2.5 3.5

(Note 5)

SRAM AC Adder 1.5 3.0

Note: 1. Reset (RESET) has hysteresis . V

deselected or intern al Po wer-down m ode is active.

2. CSI

3. PLD is in non -Turbo mode, an d none of th e i n puts are sw i t ching .

4. Please see Fi gure 35., page 72 for the PLD c urrent calculation. = 0mA

5. I

OUT

is valid at or below 0.2VCC –0.1. V

IL1

(in addition to those in

Table 39., page 76)

4.5 V < V

= 20µA, VCC = 4.5 V

= 8mA, VCC = 4.5 V

= –20µA, VCC = 4.5 V

= –2mA, VCC = 4.5 V

Only on V

>VCC –0.3 V (Notes

CSI

0.45 < V

< 5.5 V

)

(Note

)

(Note

= 1µA V

OH1

= 0 V

STBY

< VIN < V

OUT

< V

2,3

)

PLD_TURBO = Off,

f = 0 MHz (Note

)

PLD_TURBO = On,

f = 0 MHz

During Flash memory

WRITE/Erase Only

Read only, f = 0 MHz 0 0 mA

is valid at or above 0.8VCC.

IH1

Min. Typ. Max. Unit

VCC +0.5

–0.5 0.8 V

0.8V –0.5

VCC +0.5

0.2V

–0.1

V V

2.5 4.2 V

0.01 0.1 V

0.25 0.45 V

4.4 4.49 V

2.4 3.9 V

STBY

– 0.8

V V

0.5 1 µA

–0.1 0.1 µA

50 200 µA

–1 ±0.1 1 µA

–10 ±5 10 µA

0 µA/PT

400 700 µA/PT

15 30 mA

note

mA/

MHz

mA/

MHz

78/110

PSD813F2, PSD833F2, PS D834F2, PSD853F2, PSD854F2

Table 46. DC Characteristics (3V devices)

Symbol Parameter Conditions Min. Typ. Max. Unit

IH1

IL1

HYS

LKO

OH1

STBY

IDLE

(DC)

(Note 5)

High Level Input Voltage Low Level Input Voltage Reset High Level Input Voltage

Reset Low Level Input Voltage

3.0 V < V

< 3.6 V 0.7V

< 3.6 V

)

(Note

)

(Note

VCC +0.5

–0.5 0.8 V

0.8V –0.5

VCC +0.5

0.2V

–0.1

Reset Pin Hysteresis 0.3 V VCC (min) for Flash Erase and

Program

= 20µA, VCC = 3.0 V

Output Low Voltage

Output High Voltage Except

STBY

Output High Voltage V

STBY

On I

= 4mA, VCC = 3.0 V

= –20µA, VCC = 3.0 V

= –1mA, VCC = 3.0 V

= 1µA V

OH1

SRAM Stand-by Voltage 2.0

SRAM Stand-by Current Idle Current (V

input) VCC > V

STBY

SRAM Data Retention Voltage Stand-by Supply Current

for Power-down Mode Input Leakage Curren t Output Leakage Current

>VCC –0.3 V (Notes

CSI

Only on V

< VIN < V

0.45 < V

= 0 V

STBY

< V

2,3

PLD_TURBO = Off,

PLD Only

f = 0 MHz (Note

)

PLD_TURBO = On, Operating Supply Current

Flash memory

f = 0 MHz

During Flash memory

WRITE/Erase Only

1.5 2.2 V

0.01 0.1 V

0.15 0.45 V

2.9 2.99 V

2.7 2.8 V – 0.8

STBY

0.5 1 µA

–0.1 0.1 µA

)

25 100 µA

–1 ±0.1 1 µA

–10 ±5 10 µA

0 µA/PT

200 400 µA/PT

10 25 mA

Read only, f = 0 MHz 0 0 mA

V V

SRAM f = 0 MHz 0 0 mA

PLD AC Adder

(AC)

Flash memory AC Adder 1.5 2.0

(Note 5)

SRAM AC Adder 0.8 1.5

Note: 1. Reset (RESET) has hysteresis . V

deselected or internal PD i s ac tive.

2. CSI

3. PLD is in non -Turbo mode, an d none of th e i n puts are sw i t ching .

4. Please see Fi gure 36., page 72 for the PLD c urrent calculation. = 0mA

5. I

OUT

is valid at or below 0.2VCC –0.1. V

IL1

is valid at or above 0.8VCC.

IH1

note

mA/

MHz

mA/

MHz

79/110

PSD813F2, PSD833F2, PSD834F 2, PSD853F2, PSD854F2

Figure 40. Input to Output Disable / Enable

INPUT

tER tEA

INPUT TO

OUTPUT

ENABLE/DISABLE

Table 47. CPLD Combinatorial Timing (5V devices)

Symbol Parameter Conditions

CPLD Input Pin/

Feedback to CPLD Combinatorial Output

-70 -90 -15 Fast

Min Max Min Max Min Max

20 25 32 + 2 + 10 – 2 ns

AI02863

Aloc

Turbo

Off

Slew rate

Unit

ARP

ARPW

ARD

Note: 1. Fast Slew Rate output available on P A3-PA0, PB3-PB0, and PD 2-PD0. Decrement tim es by given amount.

CPLD Input to CPLD Output Enable

CPLD Input to CPLD Output Disable

CPLD Register Clear or Preset Delay

CPLD Register Clear or Preset Pulse Width

CPLD Array Delay

Any

macrocell

21 26 32 + 10 – 2 ns

21 26 33 + 10 – 2 ns

10 20 29 + 10 ns

11 16 22 + 2 ns

Table 48. CPLD Combinatorial Timing (3V devices)

Symbol Parameter Conditions

CPLD Input Pin/

Feedback to CPLD Combinatorial Output

CPLD Input to CPLD Output Enable

CPLD Input to CPLD Output Disable

CPLD Register Clear

ARP

or Preset Delay

-12 -15 -20

Min Max Min Max Min Max

40 45 50 + 4 + 20 – 6 ns

43 45 50 + 20 – 6 ns

40 43 48 + 20 – 6 ns

Aloc

Turbo

Off

Slew rate

Unit

ARPW

25 30 35 + 20 ns

Preset Pulse Width

CPLD Register Clear

ARD

Note: 1. Fast Slew Rate output available on P A3-PA0, PB3-PB0, and PD 2-PD0. Decrement tim es by given amount.

CPLD Array Delay

Any

macrocell

25 29 33 + 4 ns

80/110

PSD813F2, PSD833F2, PS D834F2, PSD853F2, PSD854F2

Figure 41. Sy nchronous C lo ck Mode Timi ng – P LD

CLKIN

INPUT

REGISTERED

OUTPUT

Table 49. CPLD Macrocell Synchronous Clock Mode Timing (5V devices)

-70 -90 -15 Fast

Symbol Parameter Conditions

Maximum Frequency External

1/(t

S+tCO

Feedback Maximum

MAX

Frequency Internal

1/(t

S+tCO

Feedback

)

CNT

Maximum Frequency

1/(t

CH+tCL

Pipelined Data

Min Max Min Max Min Max

)

–10)

)

40.0 30.30 25.00 MHz

66.6 43.48 31.25 MHz

83.3 50.00 35.71 MHz

AI02860

Aloc

Turbo

Off

Slew rate

Unit

ARD

MIN

Note: 1. Fast Slew Rate output available on P A3-PA0, PB3-PB0, and PD 2-PD0. Decrement tim es by given amount.

Input Setup Time

12 15 20 + 2 + 10 ns

Input Hold Time 0 0 0 ns Clock High Time Clock Input 6 10 15 ns Clock Low Time Clock Input 6 10 15 ns Clock to Output

Delay CPLD Array

Delay Minimum Clock

Period

2. CLKIN (PD1 ) t

CLCL

Clock Input 13 18 22 – 2 ns

Any macrocell 11 16 22 + 2 ns

= tCH + tCL.

tCH+t

12 20 30 ns

81/110

PSD813F2, PSD833F2, PSD834F 2, PSD853F2, PSD854F2

Table 50. CPLD Macrocell Synchronous Clock Mode Timing (3V devices)

Symbol Parameter Conditions

Maximum Frequency

1/(t

S+tCO

External Feedback Maximum

MAX

Frequency Internal Feedback

)

CNT

1/(tS+tCO–10)

Maximum Frequency

1/(t

CH+tCL

Pipelined Data

)

-12 -15 -20

MinMaxMinMaxMinMax

22.2 18.8 15.8 MHz

28.5 23.2 18.8 MHz

40.0 33.3 31.2 MHz

Aloc

Turbo

Off

Slew rate

Unit

ARD

MIN

Note: 1. Fast Slew Rate output available on P A3-PA0, PB3-PB0, and PD 2-PD0. Decrement tim es by given amount.

Input Setup Time 20 25 30 + 4 + 20 ns Input Hold Time 0 0 0 ns Clock High Time Clo ck Input 1 5 15 16 ns Clock Low Time Clock Input 10 15 16 ns Clock to Output

Delay

Clock Input 25 28 33 – 6 ns

CPLD Array Delay Any macrocell 25 29 33 + 4 ns Minimum Clock

Period

2. CLKIN (PD1 ) t

= tCH + tCL.

CLCL

tCH+t

25 29 32 ns

82/110

PSD813F2, PSD833F2, PS D834F2, PSD853F2, PSD854F2

Figure 42. Asynchronous Reset / Preset

tARPW

RESET/PRESET

INPUT

tARP

OUTPUT

Figure 43. Asynchronous Clock Mode Timing (product term clock)

CLOCK

INPUT

REGISTERED

OUTPUT

tCHA

tCLA

tHAtSA

tCOA

AI02864

AI02859

83/110

PSD813F2, PSD833F2, PSD834F 2, PSD853F2, PSD854F2

Table 51. CPLD Macrocell Asynchronous Clock Mode Timing (5V devices)

Symbol Parameter Conditions

Maximum Frequency External

1/(t

SA+tCOA

Feedback Maximum

Frequency

MAXA

Internal

1/(t

SA+tCOA

Feedback

)

CNTA

Maximum Frequency Pipelined

1/(t

CHA+tCLA

Data

)

–10)

)

-70 -90 -15

Min Max Min Max Min Max

38.4 26.32 21.27 MHz

62.5 35.71 27.78 MHz

71.4 41.67 35.71 MHz

Aloc

Turbo

Off

Slew

Rate

Unit

CHA

CLA

COA

ARDA

MINA

Input Setup Time

Input Hold Time

Clock Input High Time

Clock Input Low Time

Clock to Output Delay

CPLD Array Delay

Minimum Clock Period

7 8 12 + 2 + 10 ns

81214 ns

9 12 15 + 10 ns

21 30 37 + 10 – 2 ns

Any macrocell 11 16 22 + 2 ns

1/f

CNTA

16 28 39 ns

84/110

PSD813F2, PSD833F2, PS D834F2, PSD853F2, PSD854F2

Table 52. CPLD Macrocell Asynchronous Clock Mode Timing (3V devices)

Symbol Parameter Conditions

Maximum Frequency External

1/(t

SA+tCOA

Feedback Maximum

MAXA

Frequency Internal

1/(t

SA+tCOA

Feedback

)

CNTA

Maximum Frequency

1/(t

CHA+tCLA

Pipelined Data

CHA

CLA

COA

ARD

MINA

Input Setup Time

Input Hold Time 12 15 17 ns Clock High Time 17 22 25 + 20 ns Clock Low Time 13 15 16 + 20 ns Clock to Output

Delay CPLD Array

Delay Minimum Clock

Period

Any macrocell 25 29 33 + 4 ns

1/f

CNTA

)

–10)

)

-12 -15 -20

Min Max Min Max Min Max

21.7 19.2 16.9 MHz

27.8 23.8 20.4 MHz

33.3 27 24.4 MHz

10 12 13 + 4 + 20 ns

36 40 46 + 20 – 6 ns

36 42 49 ns

Aloc

Turbo

Off

Slew

Rate

Unit

85/110

PSD813F2, PSD833F2, PSD834F 2, PSD853F2, PSD854F2

Figure 44. Input Macrocell Timing (product term clock)

PT CLOCK

INPUT

OUTPUT

AI03101

INH

INL

INO

Table 53. Input Macrocell Timing (5V devices)

Symbol Parameter Conditions

INH

INL

INO

Note: 1. Inputs fro m Port A, B, an d C relative to register/ la tc h clock from t he PLD. ALE/AS latch tim i ngs refer to t

Input Setup Time Input Hold Time NIB Input High Time NIB Input Low Time

NIB Input to Combinatorial Delay

(Note (Note (Note (Note

(Note

)

-70 -90 -15

Min Max Min Max Min Max

000 ns

15 20 26 + 10 ns

91218 ns 91218 ns

34 46 59 + 2 + 10 ns

Aloc

AVLX

and t

Turbo

Off

LXAX

Unit

Table 54. Input Macrocell Timing (3V devices)

Symbol Parameter Conditions

INH

INL

INO

Note: 1. Inputs from Port A, B, and C relative to register/latch clo ck fr om th e PLD. ALE lat ch timin g s refe r to t

Input Setup Time Input Hold Time NIB Input High Time NIB Input Low Time NIB Input to Combinatorial

Delay

(Note (Note (Note (Note

(Note

)

-12 -15 -20

Min Max Min Max Min Max

000 ns 25 25 30 + 20 ns 12 13 15 ns 12 13 15 ns

46 62 70 + 4 + 20 ns

AVLX

Aloc

and t

Turbo

LXAX

Off

Unit

86/110

Figure 45. RE A D Ti m in g

ALE/AS

MULTIPLEXED

NON-MULTIPLEXED

A/D

BUS

ADDRESS

BUS

PSD813F2, PSD833F2, PS D834F2, PSD853F2, PSD854F2

AVLXtLXAX

LVLX

ADDRESS

VALID

DATA

AVQV

ADDRESS

VALID

Note: 1. t

(PSEN, DS)

and t

DATA

BUS

CSI

R/W

LXAX

NON-MULTIPLEXED

AVLX

SLQV

RLQV

THEH

RLRH

EHEL

AVPV

ADDRESS OUT

are not required for 80C251 in Page Mode or 80C51XA in Burst Mode.

DATA

VALID

RHQX

tRHQZ

ELTL

AI02895

87/110

PSD813F2, PSD833F2, PSD834F 2, PSD853F2, PSD854F2

Table 55. READ Timing (5V devices)

Symbol Parameter Conditions

LVLX

AVLX

LXAX

AVQV

ALE or AS Pulse Width 15 20 28 ns Address Setup Time Address Hold Time Address Valid to Data Valid

(Note (Note (Note

) ) )

-70 -90 -15

MinMaxMinMaxMinMax

4 6 10 ns 7811 ns

70 90 150 + 10 ns

Turbo

Off

Unit

SLQV

RLQV

RHQX

RLRH

RHQZ

EHEL

THEH

ELTL

AVPV

Note: 1. RD timing has the same timing as DS, LDS, UDS, and PSEN signals .

CS Valid to Data Valid 75 100 150 ns RD to Data Valid 8-Bit Bus RD

or PSEN to Data Valid

8-Bit Bus, 8031, 80251 RD Data Hold Time

RD Pulse Width RD to Data High-Z

(Note

(Note (Note (Note

)

24 32 40 ns

31 38 45 ns

000 ns

27 32 38 ns

20 25 30 ns E Pulse Width 27 32 38 ns R/W Setup Time to Enable 6 10 18 ns R/W Hold Time After Enable 0 0 0 ns

Address Input Valid to Address Output Delay

and PSEN have the same timing.

2. RD

3. Any input used to select an internal PSD function.

4. In multiple xed mode, latc hed address es generate d from ADIO de l ay to address output on any P ort. timing has the same tim in g as DS, LDS, and UD S signals.

5. RD

(Note

)

20 25 30 ns

88/110

PSD813F2, PSD833F2, PS D834F2, PSD853F2, PSD854F2

Table 56. READ Timing (3V devices)

Symbol Parameter Conditions

LVLX

AVLX

LXAX

AVQV

ALE or AS Pulse Width 26 26 30 ns Address Setup Time Address Hold Time Address Valid to Data Valid

(Note (Note (Note

-12 -15 -20

MinMaxMinMaxMinMax

91012 ns

)

91214 ns

) )

120 150 200 + 20 ns

Turbo

Off

Unit

SLQV

RLQV

RHQX

RLRH

RHQZ

EHEL

THEH

ELTL

AVPV

Note: 1. RD timing has the same timing as DS, LDS, UDS, and PSEN signals .

CS Valid to Data Valid 120 150 200 ns RD to Data Valid 8-Bit Bus RD

or PSEN to Data Valid 8-Bit Bus,

8031, 80251 RD Data Hold Time

(Note

)

35 35 40 ns

45 50 55 ns

000 ns RD Pulse Width 38 40 45 ns RD to Data High-Z

(Note

)

38 40 45 ns E Pulse Width 40 45 52 ns R/W Setup Time to Enable 15 18 20 ns R/W Hold Time After Enable 0 0 0 ns

Address Input Valid to Address Output Delay

2. RD

and PSEN have the same timing for 8031.

3. Any input used to select an internal PSD function.

4. In multiplexed mode latched address generated from ADIO delay to address output on any Port. timing has the same tim in g as DS, LDS, and UD S signals.

5. RD

(Note

)

33 35 40 ns

89/110

PSD813F2, PSD833F2, PSD834F 2, PSD853F2, PSD854F2

Figure 46. WRI TE Ti m in g

ALE/ AS

MULTIPLEXED

NON-MULTIPLEXED

A/D

BUS

ADDRESS

BUS

DATA

BUS

CSI

(DS)

R/ W

AVLX

ADDRESS

VALID

AVWL

ADDRESS

SLWL

LXAX

LVLX

VALID

THEH

WLWH

EHEL

DVW H

DATA

VALID

DATA

VALID

WHAX

WHDX

ELTL

AVPV

ADDRESS OUT

WLMV

WHPV

STANDARD

MCU I/O OUT

AI02896

90/110

PSD813F2, PSD833F2, PS D834F2, PSD853F2, PSD854F2

Table 57. WRITE Timing (5V devices)

Symbol Parameter Conditions

LVLX

AVLX

LXAX

ALE or AS Pulse Width 15 20 28 ns Address Setup Time Address Hold Time

(Note (Note

-70 -90 -15 Unit

Min Max Min Max Min Max

)

4 6 10 ns 7811ns

AVWL

SLWL

DVWH

WHDX

WLWH

WHAX1

WHAX2

WHPV

DVMV

Address Valid to Leading Edge of WR

CS Valid to Leading Edge of WR WR Data Setup Time WR Data Hold Time WR Pulse Width Trailing Edge of WR to Address Invalid

Trailing Edge of WR to DPLD Address Invalid

Trailing Edge of WR to Port Output Valid Using I/O Port Data Register

Data Valid to Port Output Valid Using Macrocell Regist er

(Notes

(Note 3) (Note (Note (Note (Note

(Note

(Notes

1,3

3,6

3,5

81520ns

)

12 15 20 ns

) ) ) )

)

25 35 45 ns

455ns

31 35 45 ns

6 8 10 ns

000ns

)

27 30 38 ns

)

42 55 65 ns

Preset/Clear

AVPV

WLMV

Note: 1. Any input used to select an internal PSD function.

Address Input Valid to Address Output Delay

WR Valid to Port Output Valid Using Macrocell Register Preset/Clear

2. In multiple xed mode, latc hed address generated f rom ADIO delay to address output on any port. has the s a m e t i m i ng as E, LDS , UDS, WRL, and WRH signals.

3. WR

4. Assuming data is stable before active WRITE signal.

5. Assuming WRITE is active before data becomes valid.

6. TWHAX2 is th e address hold time for DPL D i nputs that are used to generate Secto r Select signa l s f or internal PS D memory.

(Note

(Notes

3,4

)

20 25 30 ns

48 55 65 ns

91/110

PSD813F2, PSD833F2, PSD834F 2, PSD853F2, PSD854F2

Table 58. WRITE Timing (3V devices)

Symbol Parameter Conditions

LVLX

AVLX

LXAX

ALE or AS Pulse Width 26 26 30 Address Setup Time Address Hold Time

(Note (Note

Min Max Min Max Min Max

) )

-12 -15 -20 Unit

91012ns 91214ns

AVWL

SLWL

DVWH

WHDX

WLWH

WHAX1

WHAX2

WHPV

DVMV

AVPV

WLMV

Note: 1. Any input used to select an internal PSD function.

Address Valid to Leading Edge of WR

CS Valid to Leading Edge of WR WR Data Setup Time WR Data Hold Time WR Pulse Width Trailing Edge of WR to Address Invalid

Trailing Edge of WR to DPLD Address Invalid

Trailing Edge of WR to Port Output Valid Using I/O Port Data Register

Data Valid to Port Output Valid Using Macrocell Register Preset/Clear

Address Input Valid to Address Output Delay

WR Valid to Port Output Valid Using Macrocell Register Preset/Clear

2. In multiple xed mode, latc hed address generated f rom ADIO delay to address output on any port. has the s a m e t i m i ng as E, LDS , UDS, WRL, and WRH signals.

3. WR

4. Assuming data is stable before active WRITE signal.

5. Assuming WRITE is active before data becomes valid.

6. TWHAX2 is th e address hold time for DPL D i nputs that are used to generate Secto r Select signa l s f or internal PS D memory.

(Notes

(Note 3) (Note (Note (Note (Note

(Note

(Notes

(Note

(Notes

1,3

3,6

3,5

3,4

17 20 25 ns

)

17 20 25 ns

) ) ) )

)

45 45 50 ns

7 8 10 ns 46 48 53 ns 10 12 17 ns

000ns

)

33 35 40 ns

)

70 70 80 ns

33 35 40 ns

)

70 70 80 ns

Table 59. Program, WRITE and Erase Times (5V devices)

Symbol Parameter Min. Typ. Max. Unit

Flash Program 8.5 s

Flash Bulk Erase

(pre-programmed)

Flash Bulk Erase (not pre-program med ) 5 s

WHQV3

WHQV2

WHQV1

Sector Erase (pre-programmed) 1 30 s Sector Erase (not pre-programmed) 2.2 s Byte Program 14 1200 µs Program / Erase Cycles (per Sector) 100,000 cycles

WHWLO

Q7VQV

Note: 1. Programm ed to all zero before erase.

2. The polling s tatus, DQ7, is vali d tQ7VQV tim e units befo re t he data byte, DQ0-DQ7, is vali d for reading.

Sector Erase Time-Out 100 µs DQ7 Valid to Output (DQ7-DQ0) Valid (Data Polling)

92/110

330s

30 ns

PSD813F2, PSD833F2, PS D834F2, PSD853F2, PSD854F2

Table 60. Program, WRITE and Erase Times (3V devices)

Symbol Parameter Min. Typ. Max. Unit

Flash Program 8.5 s Flash Bulk Erase

(pre-programmed)

Flash Bulk Erase (not pre-program med ) 5 s

WHQV3

WHQV2

WHQV1

Sector Erase (pre-programmed) 1 30 s Sector Erase (not pre-programmed) 2.2 s Byte Program 14 1200 µs Program / Erase Cycles (per Sector) 100,000 cycles

WHWLO

Q7VQV

Note: 1. Programm ed to all zero before erase.

2. The polling s tatus, DQ7, is vali d tQ7VQV tim e units befo re t he data byte, DQ0-DQ7, is vali d for reading.

Sector Erase Time-Out 100 µs DQ7 Valid to Output (DQ7-DQ0) Valid (Data Polling)

330s

30 ns

93/110

PSD813F2, PSD833F2, PSD834F 2, PSD853F2, PSD854F2

Figure 47. Peripheral I/O READ Timing

ALE/AS

A/D BUS

CSI

ADDRESS DATA VALID

(PA)

AVQV

(PA)

SLQV

(PA)

RLQV

(PA)

RLRH

DVQV

DATA ON PORT A

Table 61. Port A Peripheral Data Mode READ Timing (5V devices)

Symbol Parameter Conditions

AVQV–PA

SLQV–PA

RLQV–PA

Address Valid to Data Valid

(Note

CSI Valid to Data Valid 27 35 45 + 10 ns RD to Data Valid RD

to Data Valid 8031 Mode 32 38 45 ns

(Notes

1,4

)

-70 -90 -15

MinMaxMinMaxMinMax

37 39 45 + 10 ns

21 32 40 ns

(PA)

QXRH

RHQZ

(PA) (PA)

AI02897

Turbo

Off

Unit

DVQV–PA

QXRH–PA

RLRH–PA

RHQZ–PA

94/110

Data In to Data Out Valid 22 30 38 ns RD Data Hold Time 0 0 0 ns RD Pulse Width

RD to Data High-Z

(Note (Note

)

27 32 38 ns

23 25 30 ns

PSD813F2, PSD833F2, PS D834F2, PSD853F2, PSD854F2

Table 62. Port A Peripheral Data Mode READ Timing (3V devices)

Symbol Parameter Conditions

AVQV–PA

SLQV–PA

RLQV–PA

DVQV–PA

QXRH–PA

RLRH–PA

RHQZ–PA

Address Valid to Data Valid

(Note CSI Valid to Data Valid 37 45 50 + 20 ns RD to Data Valid RD

to Data Valid 8031 Mode 45 45 50 ns

(Notes

Data In to Data Out Valid 38 40 45 ns RD Data Hold Time 0 0 0 ns RD Pulse Width

RD to Data High-Z

(Note

Figure 48. Peripheral I/O WRITE Timing

ALE/AS

1,4

)

) )

-12 -15 -20

MinMaxMinMaxMinMax

50 50 50 + 20 ns

37 40 45 ns

36 36 46 ns

36 40 45 ns

Turbo

Off

Unit

A/D BUS

ADDRESS DATA OUT

tWLQV (PA)

tDVQV (PA)

PORT A

DATA OUT

Table 63. Port A Peripheral Data Mode WRITE Timing (5V devices)

Symbol Parameter Conditions

WLQV–PA

DVQV–PA

WHQZ–PA

Note: 1. RD has the same tim i ng as DS, LDS, UD S, and PSEN (in 8031 combined mode).

2. WR

3. Any input used to select Port A Data Peripheral mode.

4. Data is already stable on P ort A.

5. Data stable on ADIO pins to data on Port A.

WR to Data Propagation Delay Data to Port A Data Propagation Delay WR Invalid to Port A Tri-state

has the s a m e t i m i ng as the E, LDS, UDS, WRL, and WRH signals.

(Note (Note (Note

)

-70 -90 -15

Min Max Min Max Min Max

tWHQZ (PA)

AI02898

Unit

25 35 40 ns 22 30 38 ns 20 25 33 ns

95/110

PSD813F2, PSD833F2, PSD834F 2, PSD853F2, PSD854F2

Table 64. Port A Peripheral Data Mode WRITE Timing (3V devices)

Symbol Parameter Conditions

WLQV–PA

DVQV–PA

WHQZ–PA

Note: 1. RD has the same tim i ng as DS, LDS, UD S, and PSEN (in 8031 combined mode).

2. WR

3. Any input used to select Port A Data Peripheral mode.

4. Data is already stable on P ort A.

5. Data stable on ADIO pins to data on Port A.

WR to Data Propagation Delay Data to Port A Data Propagation Delay WR Invalid to Port A Tri-state

has the s a m e t i m i ng as the E, LDS, UDS, WRL, and WRH signals.

(Note (Note (Note

)

Figure 49. Reset (RESET) Timing

-12 -15 -20

Min Max Min Max Min Max

Unit

42 45 55 ns 38 40 45 ns 33 33 35 ns

RESET

Table 65. Reset (RESET

VCC(min)

NLNH-PO

Power-On Reset

) Timing (5V devices)

OPR

NLNH

NLNH-A

Warm Reset

OPR

AI02866b

Symbol Parameter Conditions Min Max Unit

NLNH

NLNH–PO

NLNH–A

OPR

Note: 1. Reset (RESET) does not reset Fl ash memory Pr ogram or Erase cycles.

2. Warm reset aborts Flash m emory Program or Erase cycles, and puts the devi ce in READ Mod e.

RESET Active Low Time Power On Reset Active Low Time 1 ms

Warm Reset (on the PSD834Fx) RESET High to Operational Device 120 ns

150 ns

25 µs

Table 66. Reset (RESET) Timing (3V devices)

Symbol Parameter Conditions Min Max Unit

NLNH

NLNH–PO

NLNH–A

RESET Active Low Time Power On Reset Active Low Time 1 ms

Warm Reset (on the PSD834Fx)

300 ns

25 µs

OPR

Note: 1. Reset (RESET) does not reset Fl ash memory Pr ogram or Erase cycles.

2. Warm reset aborts Flash m emory Program or Erase cycles, and puts the devi ce in READ Mod e.

RESET High to Operational Device 300 ns

96/110

PSD813F2, PSD833F2, PS D834F2, PSD853F2, PSD854F2

Table 67. V

STBYON

Timing (5V devices)

Symbol Parameter Conditions Min Typ Max Unit

BVBH

BXBL

Note: 1. V

STBYON

Table 68. V

Detection to V

STBY

Off Detection to V

STBY

STBYON

Output High

Output

Low

timing is measured at VCC ramp rate of 2 ms.

STBYON

Timing (3V devices)

(Note

)

20 µs

Symbol Parameter Conditions Min Typ Max Unit

BVBH

BXBL

Note: 1. V

Detection to V

STBY

Off Detection to V

STBY

STBYON

Low

timing is measured at VCC ramp rate of 2 ms.

STBYON

Output High

Output

(Note

(Note 1)

)

20 µs

97/110

PSD813F2, PSD833F2, PSD834F 2, PSD853F2, PSD854F2

Figure 50. ISC Ti m i ng

ISCCH

TCK

ISCCL

ISCPH

TDI/TMS

ISC OUTPUTS/TDO

ISCPSU

Table 69. ISC Timing (5V devices)

Symbol Parameter Conditions

ISCCF

ISCCH

Clock (TCK, PC1) Frequency (except for PLD)

Clock (TCK, PC1) High Time (except for PLD)

(Note

ISCPZV

ISCPCO

ISCPVZ

AI02865

-70 -90 -15 Unit

Min Max Min Max Min Max

)

20 18 14 MHz

23 26 31 ns

ISCCL

ISCCFP

ISCCHP

ISCCLP

ISCPSU

ISCPH

ISCPCO

ISCPZV

ISCPVZ

Note: 1. For non- PLD Progra m m i ng, Erase or in ISC by-pass mo de.

Clock (TCK, PC1) Low Time (except for PLD)

Clock (TCK, PC1) Frequency (PLD only) Clock (TCK, PC1) High Time (PLD only) Clock (TCK, PC1) Low Time (PLD only) ISC Port Set Up Time 7 8 10 ns

ISC Port Hold Up Time 5 5 5 ns ISC Port Clock to Output 21 23 25 ns ISC Port High-Impedance to Valid Output 21 23 25 ns ISC Port Valid Output to

High-Impedance

2. For Program or Erase PLD only.

98/110

(Note

(Note (Note (Note

)

23 26 31 ns

222MHz 240 240 240 ns 240 240 240 ns

21 23 25 ns

PSD813F2, PSD833F2, PS D834F2, PSD853F2, PSD854F2

Table 70. ISC Timing (3V devices)

Symbol Parameter Conditions

ISCCF

ISCCH

ISCCL

ISCCFP

ISCCHP

ISCCLP

ISCPSU

ISCPH

ISCPCO

ISCPZV

ISCPVZ

Note: 1. For non- PLD Progra m m i ng, Erase or in ISC by-pass mo de.

Clock (TCK, PC1) Frequency (except for PLD)

Clock (TCK, PC1) High Time (except for PLD)

Clock (TCK, PC1) Low Time (except for PLD)

Clock (TCK, PC1) Frequency (PLD only) Clock (TCK, PC1) High Time (PLD only) Clock (TCK, PC1) Low Time (PLD only)

(Note

(Note (Note

(Note ISC Port Set Up Time 12 13 15 ns ISC Port Hold Up Time 5 5 5 ns ISC Port Clock to Output 30 36 40 ns ISC Port High-Impedance to Valid Output 30 36 40 ns ISC Port Valid Output to

High-Impedance

2. For Program or Erase PLD only.

-12 -15 -20 Unit

Min Max Min Max Min Max

)

12 10 9 MHz

40 45 51 ns

222MHz 240 240 240 ns 240 240 240 ns

30 36 40 ns

Table 71. Power-down Timing (5V devices)

Symbol Parameter Conditions

LVDV

CLWH

Note: 1. t

ALE Access Time from Power-down 80 90 150 ns Maximum Delay from

APD Enable to Internal PDN Valid Signal

is the period of CLKIN (P D1).

CLCL

Using CLKIN

(PD1)

Table 72. Power-down Timing (3V devices)

Symbol Parameter Conditions

LVDV

CLWH

Note: 1. t

ALE Access Time from Power-down 145 150 200 ns Maximum Delay from APD Enable to

Internal PDN Valid Signal

is the period of CLKIN (P D1).

CLCL

Using CLKIN

(PD1)

-70 -90 -15

Min Max Min Max Min Max

CLCL

15 * t

-12 -15 -20

Min Max Min Max Min Max

CLCL

15 * t

Unit

µs

Unit

µs

99/110

PSD813F2, PSD833F2, PSD834F 2, PSD853F2, PSD854F2

PACKAG E MECHANICAL

Figure 51. PQFP52 - 52-pin Plastic, Quad, Flat Package Mechanical Drawing

QFP-A

LA1 α

Note: Drawing is not to scale.

100/110

ST PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual