ST PM8803 User Manual
High-efficiency, IEEE 802.3at compliant
integrated PoE-PD interface and PWM controller
Features
■ IEEE 802.3at compliant PD interface
■ Works with power supplied from Ethernet LAN
cables or from local auxiliary sources
■ Successful IEEE802.3at Layer1 classification
indicator
■ Integrated 100 V, 0. 45 Ω, 1 A hot-swap
MOSFET
■ Accurate 140 mA typ. inrush current level
■ Programmable classification current
■ Programmable DC current limit up to 1 A
■ Integrated high-voltage startup bias regulator
■ Thermal shutdown protection
■ Current mode pulse width modulator
■ Programmable oscillator frequency
■ 80% maximum duty cycle with internal slope
compensation
■ Support for flyback, forward, forward active
clamp, flyback with synchronous rectification
Applications
■ VoIP phones, WLAN AP
■ WiMAX CPEs
■ Security cameras
■ PoE/PoE+ Powered Device appliances
PM8803
Preliminary data
HTSSOP20
Description
The PM8803 integrates a standard compliant
Power over Ethernet (PoE) interface and a current
mode PWM controller to simplify the design of the
power supply sections of all powered devices.
The PoE/PoE+ interface incorporates all the functions required by the IEEE 802.3at including
detection, classification, undervoltage lockout
(UVLO) and in-rush current limitation.
The PM8803 specifically performs IEEE802.3at
Layer1 hardware classification, providing an indication of Type 2 PSE successful detection to the
rest of the system.
The PM8803 has been designed to work with
power either from the Ethernet cable or from an
external power source such as a wall adapter,
ensuring prevalence of the auxiliary source with
respect to the PoE. The DC/DC section of the
PM8803 features a programmable oscillator frequency, an adjustable slope compensation, dual
complementary low-side drivers, programmable
dead time and an internal temperature sensor.
The PM8803 targets high-efficiency conversion at
all load conditions supporting flyback, forward,
forward with active clamp converters and synchronous rectification.
Table 1. Device summary
Part number Package Packing
PM8803 HTSSOP20 Tube
PM8803TR HTSSOP20 Tape and reel
March 2011 Doc ID 018559 Rev 1 1/34
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to
change without notice.
www.st.com
1
Contents PM8803
Contents
1 Typical application circuits and block diagrams . . . . . . . . . . . . . . . . . . 5
1.1 Application circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.2 Block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2 Pin descriptions and connection diagrams . . . . . . . . . . . . . . . . . . . . . . 9
3 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4 PD interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.1 Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.2 Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.3 Indication of successful 2-event classification . . . . . . . . . . . . . . . . . . . . . 19
4.4 Undervoltage lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.5 Inrush and DC current limiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.6 High-voltage startup regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.7 5 V bias regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5 PWM controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.1 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.2 Delay time control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.3 Soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.4 PWM comparator / slope compensation . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.5 Current limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.6 Thermal protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6 Auxiliary sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7 HTSSOP20 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . 31
8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2/34 Doc ID 018559 Rev 1
PM8803 List of tables
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 3. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 4. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 5. Electrical characteristics - interface section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 6. Electrical characteristics - SMPS section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 7. Value of the external classification resistor for the different PD classes of power . . . . . . . 19
Table 8. HTSSOP20 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 9. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Doc ID 018559 Rev 1 3/34
List of figures PM8803
List of figures
Figure 1. Simplified application schematic for powered devices using PM8803 in forward
active clamp configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. Simplified application schematic for powered devices using PM8803 in synchronous
flyback configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3. PM8803 internal block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 4. Block diagram of the DC/DC section of the PM8803 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 5. Pin connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 6. PM8803: reference schematic of the PoE classification logic. . . . . . . . . . . . . . . . . . . . . . . 19
Figure 7. T2P signal when connected to PSE supporting 1-event classification . . . . . . . . . . . . . . . . 20
Figure 8. T2P signal when connected to PSE supporting 2-event classification . . . . . . . . . . . . . . . 20
Figure 9. Line transient response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 10. DC current vs. RDC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 11. PWM frequency vs. RT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 12. Delay time vs. RDT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 13. Timing relationship between output drivers as a function of DT . . . . . . . . . . . . . . . . . . . . . 26
Figure 14. Overload (left) and short-circuit (right) behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 15. Smooth transition from POE to auxiliary source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 16. HTSSOP20 mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4/34 Doc ID 018559 Rev 1
PM8803 Typical application circuits and block diagrams
1 Typical application circuits and block diagrams
1.1 Application circuits
Figure 1. Simplified application schematic for powered devices using PM8803 in forward active
clamp configuration
AM045091v1
Doc ID 018559 Rev 1 5/34
Typical application circuits and block diagrams PM8803
Figure 2. Simplified application schematic for powered devices using PM8803 in synchronous
flyback configuration
AM045092v1
6/34 Doc ID 018559 Rev 1
PM8803 Typical application circuits and block diagrams
1.2 Block diagrams
Figure 3. PM8803 internal block diagram
AM045093v1
Doc ID 018559 Rev 1 7/34
Typical application circuits and block diagrams PM8803
Figure 4. Block diagram of the DC/DC section of the PM8803
AM045094v1
8/34 Doc ID 018559 Rev 1
PM8803 Pin descriptions and connection diagrams
2 Pin descriptions and connection diagrams
Figure 5. Pin connections (top view)
CTL
VB
CS
RTN1
GAT1
VC
GAT2
ARTN
RTN2
VSS
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
Table 2. Pin descriptions
Pin# Name Function
Input of the Pulse Width Modulator.
1CTL
2VB
3CS
4RTN1
5GAT1
6VC
7GAT2
CTL pull-up to VB is provided by an external resistor which may be used to
bias an opto-coupler transistor.
5 V, up to 10 mA Bias Rail.
This reference voltage can be used to bias an opto-coupler transistor.
Current sense input for current mode control and overcurrent protection.
Current sensing is accomplished using a dedicated current sense compara-
tor. If the CS pin voltage exceeds 0.5 V, the GAT1 pin switches low for cycleby-cycle current limiting. CS is internally held low for 60 ns after GAT1
switches high to blank leading edge current spikes.
Power ground for the GAT1 driver.
This pin must be connected to RTN2 and ARTN.
Main gate driver output of the PWM controller.
DC-DC converter gate driver output with 1 A peak sink-source current capa-
bility. (5 ohm typ MOSFETs).
Output of the internal high-voltage regulator.
When the auxiliary transformer winding (if used) raises the voltage on this
pin above the 8 V typ. regulation set point, the internal regulator will shutdown, reducing the internal power dissipation. Filter this pin with a 1µF typ.
connected to ground.
Secondary gate driver output.
AUX gate driver output for active clamp or synchronous rectification
designs. 1 A peak sink-source current capability (5 ohm typ. MOSFETs).
T2P
FRS
DT
SA
DCCL
CLS
SP
DET
VDD
VDD
AM045095v1
8ARTN
Analog PWM supply ground.
RTN for sensitive analog circuitry including the SMPS current limit amplifier.
Doc ID 018559 Rev 1 9/34
Pin descriptions and connection diagrams PM8803
Table 2. Pin descriptions (continued)
Pin# Name Function
Power ground for the secondary gate driver.
9RTN2
10 VSS
11 VDD
12 VDD
13 DET
14 SP
15 CLS
16 DCCL
17 SA
18 DT
This pin is also connected to the drain of the internal current limiting power
MOSFET which closes VSS to the return path of the DC-DC converter.
This pin must be connected to RTN1 and ARTN
System low potential input.
Diode "OR'd" to the RJ45 connector and PSE's -48V supply, it is the more
negative input potential.
System high potential input.
The diode "OR" of several lines entering the PD, it is the most positive input
potential.
System high potential input.
The diode "OR" of several lines entering the PD, it is the most positive input
potential.
Detection resistor pin.
Connect the signature resistance between the DET pin and VDD. Current
will flow through the resistor only during the detection phase.
This pin is 100V rated with negligible resistance with respect to the external
24.9KΩ.
Front auxiliary startup pin.
Pulling up this pin to the auxiliary source will change the internal UVLO set-
tings and allow PD to be powered with voltage lower than nominal PoE voltages. Default Inrush and DC current protection are active. Use a resistor
voltage divider from the auxiliary voltage to VSS to connect this low voltage
rating pin. Connect this pin to VSS if not used.
Classification resistor pin.
Connect the classification programming resistor from this pin to VSS.
DC current limit.
A resistor between this pin and VSS will set the current limit for the interface
section of PM8803. It can be set to exceed the IEEE802.3at current limit.
Leave the pin open for standard IEEE 802.3at applications.
Rear Auxiliary startup pin.
Pulling up this pin will give high priority to an auxiliary power source like an
external wall adapter. Use a resistor voltage divider from the auxiliary voltage to ARTN to connect this low voltage rating pin.
Connect this pin to ARTN if not used.
Delay time set.
A resistor connected from this pin to ARTN sets the delay time between
GAT1 and GAT2. This pin cannot be left open.
Switching Frequency Set.
19 FRS
10/34 Doc ID 018559 Rev 1
An external resistor connected from FRS to ARTN sets the oscillator frequency.
PM8803 Pin descriptions and connection diagrams
Table 2. Pin descriptions (continued)
Pin# Name Function
Successful 2-event classification indicator.
20 T2P
EP
T2P open drain signal assertion happens when powered by a PSE performing a 2-event classification.
T2P is an active-low signal.
Exposed Pad.
Connect this to a pcb copper plane to improve heat dissipation; must be
electrically connected to VSS.
Doc ID 018559 Rev 1 11/34
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