High-efficiency, IEEE 802.3at compliant
integrated PoE-PD interface and PWM controller
Features
■ IEEE 802.3at compliant PD interface
■ Works with power supplied from Ethernet LAN
cables or from local auxiliary sources
■ Successful IEEE802.3at Layer1 classification
indicator
■ Integrated 100 V, 0. 45 Ω, 1 A hot-swap
MOSFET
■ Accurate 140 mA typ. inrush current level
■ Programmable classification current
■ Programmable DC current limit up to 1 A
■ Integrated high-voltage startup bias regulator
■ Thermal shutdown protection
■ Current mode pulse width modulator
■ Programmable oscillator frequency
■ 80% maximum duty cycle with internal slope
compensation
■ Support for flyback, forward, forward active
clamp, flyback with synchronous rectification
Applications
■ VoIP phones, WLAN AP
■ WiMAX CPEs
■ Security cameras
■ PoE/PoE+ Powered Device appliances
PM8803
Preliminary data
HTSSOP20
Description
The PM8803 integrates a standard compliant
Power over Ethernet (PoE) interface and a current
mode PWM controller to simplify the design of the
power supply sections of all powered devices.
The PoE/PoE+ interface incorporates all the functions required by the IEEE 802.3at including
detection, classification, undervoltage lockout
(UVLO) and in-rush current limitation.
The PM8803 specifically performs IEEE802.3at
Layer1 hardware classification, providing an indication of Type 2 PSE successful detection to the
rest of the system.
The PM8803 has been designed to work with
power either from the Ethernet cable or from an
external power source such as a wall adapter,
ensuring prevalence of the auxiliary source with
respect to the PoE. The DC/DC section of the
PM8803 features a programmable oscillator frequency, an adjustable slope compensation, dual
complementary low-side drivers, programmable
dead time and an internal temperature sensor.
The PM8803 targets high-efficiency conversion at
all load conditions supporting flyback, forward,
forward with active clamp converters and synchronous rectification.
Table 1. Device summary
Part number Package Packing
PM8803 HTSSOP20 Tube
PM8803TR HTSSOP20 Tape and reel
March 2011 Doc ID 018559 Rev 1 1/34
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to
change without notice.
www.st.com
1
Contents PM8803
Contents
1 Typical application circuits and block diagrams . . . . . . . . . . . . . . . . . . 5
1.1 Application circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.2 Block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2 Pin descriptions and connection diagrams . . . . . . . . . . . . . . . . . . . . . . 9
3 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4 PD interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.1 Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.2 Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.3 Indication of successful 2-event classification . . . . . . . . . . . . . . . . . . . . . 19
4.4 Undervoltage lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.5 Inrush and DC current limiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.6 High-voltage startup regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.7 5 V bias regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5 PWM controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.1 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.2 Delay time control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.3 Soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.4 PWM comparator / slope compensation . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.5 Current limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.6 Thermal protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6 Auxiliary sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7 HTSSOP20 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . 31
8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2/34 Doc ID 018559 Rev 1
PM8803 List of tables
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 3. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 4. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 5. Electrical characteristics - interface section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 6. Electrical characteristics - SMPS section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 7. Value of the external classification resistor for the different PD classes of power . . . . . . . 19
Table 8. HTSSOP20 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 9. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Doc ID 018559 Rev 1 3/34
List of figures PM8803
List of figures
Figure 1. Simplified application schematic for powered devices using PM8803 in forward
active clamp configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. Simplified application schematic for powered devices using PM8803 in synchronous
flyback configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3. PM8803 internal block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 4. Block diagram of the DC/DC section of the PM8803 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 5. Pin connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 6. PM8803: reference schematic of the PoE classification logic. . . . . . . . . . . . . . . . . . . . . . . 19
Figure 7. T2P signal when connected to PSE supporting 1-event classification . . . . . . . . . . . . . . . . 20
Figure 8. T2P signal when connected to PSE supporting 2-event classification . . . . . . . . . . . . . . . 20
Figure 9. Line transient response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 10. DC current vs. RDC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 11. PWM frequency vs. RT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 12. Delay time vs. RDT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 13. Timing relationship between output drivers as a function of DT . . . . . . . . . . . . . . . . . . . . . 26
Figure 14. Overload (left) and short-circuit (right) behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 15. Smooth transition from POE to auxiliary source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 16. HTSSOP20 mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4/34 Doc ID 018559 Rev 1
PM8803 Typical application circuits and block diagrams
1 Typical application circuits and block diagrams
1.1 Application circuits
Figure 1. Simplified application schematic for powered devices using PM8803 in forward active
clamp configuration
AM045091v1
Doc ID 018559 Rev 1 5/34
Typical application circuits and block diagrams PM8803
Figure 2. Simplified application schematic for powered devices using PM8803 in synchronous
flyback configuration
AM045092v1
6/34 Doc ID 018559 Rev 1
PM8803 Typical application circuits and block diagrams
1.2 Block diagrams
Figure 3. PM8803 internal block diagram
AM045093v1
Doc ID 018559 Rev 1 7/34
Typical application circuits and block diagrams PM8803
Figure 4. Block diagram of the DC/DC section of the PM8803
AM045094v1
8/34 Doc ID 018559 Rev 1
PM8803 Pin descriptions and connection diagrams
2 Pin descriptions and connection diagrams
Figure 5. Pin connections (top view)
CTL
VB
CS
RTN1
GAT1
VC
GAT2
ARTN
RTN2
VSS
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
Table 2. Pin descriptions
Pin# Name Function
Input of the Pulse Width Modulator.
1CTL
2VB
3CS
4RTN1
5GAT1
6VC
7GAT2
CTL pull-up to VB is provided by an external resistor which may be used to
bias an opto-coupler transistor.
5 V, up to 10 mA Bias Rail.
This reference voltage can be used to bias an opto-coupler transistor.
Current sense input for current mode control and overcurrent protection.
Current sensing is accomplished using a dedicated current sense compara-
tor. If the CS pin voltage exceeds 0.5 V, the GAT1 pin switches low for cycleby-cycle current limiting. CS is internally held low for 60 ns after GAT1
switches high to blank leading edge current spikes.
Power ground for the GAT1 driver.
This pin must be connected to RTN2 and ARTN.
Main gate driver output of the PWM controller.
DC-DC converter gate driver output with 1 A peak sink-source current capa-
bility. (5 ohm typ MOSFETs).
Output of the internal high-voltage regulator.
When the auxiliary transformer winding (if used) raises the voltage on this
pin above the 8 V typ. regulation set point, the internal regulator will shutdown, reducing the internal power dissipation. Filter this pin with a 1µF typ.
connected to ground.
Secondary gate driver output.
AUX gate driver output for active clamp or synchronous rectification
designs. 1 A peak sink-source current capability (5 ohm typ. MOSFETs).
T2P
FRS
DT
SA
DCCL
CLS
SP
DET
VDD
VDD
AM045095v1
8ARTN
Analog PWM supply ground.
RTN for sensitive analog circuitry including the SMPS current limit amplifier.
Doc ID 018559 Rev 1 9/34
Pin descriptions and connection diagrams PM8803
Table 2. Pin descriptions (continued)
Pin# Name Function
Power ground for the secondary gate driver.
9RTN2
10 VSS
11 VDD
12 VDD
13 DET
14 SP
15 CLS
16 DCCL
17 SA
18 DT
This pin is also connected to the drain of the internal current limiting power
MOSFET which closes VSS to the return path of the DC-DC converter.
This pin must be connected to RTN1 and ARTN
System low potential input.
Diode "OR'd" to the RJ45 connector and PSE's -48V supply, it is the more
negative input potential.
System high potential input.
The diode "OR" of several lines entering the PD, it is the most positive input
potential.
System high potential input.
The diode "OR" of several lines entering the PD, it is the most positive input
potential.
Detection resistor pin.
Connect the signature resistance between the DET pin and VDD. Current
will flow through the resistor only during the detection phase.
This pin is 100V rated with negligible resistance with respect to the external
24.9KΩ.
Front auxiliary startup pin.
Pulling up this pin to the auxiliary source will change the internal UVLO set-
tings and allow PD to be powered with voltage lower than nominal PoE voltages. Default Inrush and DC current protection are active. Use a resistor
voltage divider from the auxiliary voltage to VSS to connect this low voltage
rating pin. Connect this pin to VSS if not used.
Classification resistor pin.
Connect the classification programming resistor from this pin to VSS.
DC current limit.
A resistor between this pin and VSS will set the current limit for the interface
section of PM8803. It can be set to exceed the IEEE802.3at current limit.
Leave the pin open for standard IEEE 802.3at applications.
Rear Auxiliary startup pin.
Pulling up this pin will give high priority to an auxiliary power source like an
external wall adapter. Use a resistor voltage divider from the auxiliary voltage to ARTN to connect this low voltage rating pin.
Connect this pin to ARTN if not used.
Delay time set.
A resistor connected from this pin to ARTN sets the delay time between
GAT1 and GAT2. This pin cannot be left open.
Switching Frequency Set.
19 FRS
10/34 Doc ID 018559 Rev 1
An external resistor connected from FRS to ARTN sets the oscillator frequency.
PM8803 Pin descriptions and connection diagrams
Table 2. Pin descriptions (continued)
Pin# Name Function
Successful 2-event classification indicator.
20 T2P
EP
T2P open drain signal assertion happens when powered by a PSE performing a 2-event classification.
T2P is an active-low signal.
Exposed Pad.
Connect this to a pcb copper plane to improve heat dissipation; must be
electrically connected to VSS.
Doc ID 018559 Rev 1 11/34
Electrical specifications PM8803
3 Electrical specifications
3.1 Absolute maximum ratings
Table 3. Absolute maximum ratings
Parameter Value Unit
VDD, DET, ARTN to VSS -0.3 to 100 V
CLS, SP, DCCL to VSS -0.3 to 3.6 V
VC to ARTN -0.3 to 16 V
GAT1, GAT2, T2P to ARTN -0.3 to VC+0.3 V
CTL, VB, DT to ARTN -0.3 to 5.5 V
FRS, SA, CS to ARTN -0.3 to 3.6 V
RTN1, RTN2 to ARTN -0.3 to 0.3 V
ESD HBM 2 KV
ESD CDM 500 V
(1)
Operating junction temperature
-40 to 150
°C
Storage temperature -40 to 150
1. Internally limited to 160 °C typ with internal overtemperature protection circuit.
Note: Absolute maximum ratings are limits beyond which damage to the device may occur.
3.2 Thermal data
Table 4. Thermal data
Symbol Parameter Value Unit
R
THJA
T
MAX
T
STG
T
T
A
1. Package mounted on a 4-layer board ( 2 signals + 2 powers ), CU thickness 35 micron, with 6-8 vias on the
exposed pad copper area connected to an inner power plane
Max thermal resistance junction to ambient
Maximum junction temperature 150 °C
Storage temperature range -40 to 150 °C
Operative junction temperature range -40 to 125 °C
J
Operative ambient temperature range -40 to 85 °C
(1)
40 °C/W
°C
12/34 Doc ID 018559 Rev 1
PM8803 Electrical specifications
3.3 Electrical characteristics
VDD = 48 V, VC = not loaded, Cvc = 1 µF, VB = not loaded, Cvb = 1 µF,
GAT1 and GAT2 = not loaded, T
Values in Bolded type apply over the full operating ambient temperature range.
Table 5. Electrical characteristics - interface section
Symbol Parameter Test conditions Min. Typ. Max. Unit
Detection and classification
Signature enable VDD rising 1.5 V
Signature pull-down
resistance
Signature disable VDD rising 10.3 10.8 11.3 V
Classification enable VDD rising 11.3 12 12.7 V
Classification turn-off VDD rising 21.5 23.0 24.5 V
Mark event threshold /
Classification turn-off
Classification reset
threshold
within signature range 150 350 Ω
VDD falling 9 10 11 V
VDD falling 3 4 5 V
= 25 °C unless otherwise specified.
A
CLS voltage
CLS max current
capability
Bias current
Idd
Undervoltage lockout
V
UVLO_R
V
UVLO_F
Hot-swap MOSFET
R
DSON
VDD supply current
during detection
VDD supply current
during classification
VDD supply current
during mark event
UVLO release VIN rising 34 35 36.5 V
UVLO lockout VIN falling 30 31 32.5 V
UVLO hysteresis 3.5 4 4.5 V
MOSFET resistance 0.45 1 Ω
Default inrush current
limit
Default DC current limit 590 640 690 mA
within classification range with
44 mA load
within classification range with CLS
pin grounded
VDD = 8 V 10 μA
1.3 1.4 1.5 V
50 65 80 mA
900 1200 μA
500 800 1100 μA
125 140 155 mA
Doc ID 018559 Rev 1 13/34
Electrical specifications PM8803
Table 5. Electrical characteristics - interface section (continued)
Symbol Parameter Test conditions Min. Typ. Max. Unit
DCCL adjust
DCCL voltage 1.4 V
DC current limit selection
range
Adjustable DC current
limit precision
Inrush to DC current switchover
V
required for inrush to
DS
DC switchover
V
required for inrush to
GS
DC switchover
required for inrush to
V
DS
DC switchover
Front auxiliary source detection
SP threshold voltage rising 1.0 1.1 1.2 V
SP hysteresis 200 mV
Minimum VDD voltage for
front aux. operations
140 1000 mA
= 30 to 150 kΩ -15 +15 %
R
DCCL
VDS falling - hot-swap Mosfet
closing.
VDS falling - hot-swap Mosfet
closing. Guaranteed by design
VDS rising - hot-swap Mosfet
opening
1.35 1.50 1.75 V
2V
11 12 13 V
13 15 V
14/34 Doc ID 018559 Rev 1
PM8803 Electrical specifications
Table 6. Electrical characteristics - SMPS section
Symbol Parameter Test conditions Min. Typ. Max. Unit
Oscillator
Frequency accuracy In the range 100 to 500 kHz +/-10 %
F
osc
Delay time
Soft-start
T
SS
Current limit
= 100 kΩ 220 245 270 kHz
R
Frequency
programmability
FRS
= 47.5 kΩ 445 495 545 kHz
R
FRS
Frequency range 100 1000 kHz
FRS voltage 1.20 1.25 1.30 V
RDT = 20 kΩ, GAT1and GAT2 open 32 ns
GAT1 to GAT2 delay time
DT = 200 kΩ, GAT1and GAT2 open 320 ns
R
DT voltage 1.20 1.25 1.30 V
Soft-start time
Over CTL full range (0 to 3 V), at
osc = 250 kHz
F
12.3 ms
Delay to output Guaranteed by design 20 ns
Cycle-by-cycle current
limit threshold voltage
Leading edge blanking
time
Slope compensation
current
Sourced by CS pin 45 μA
0.44 0.50 0.56 V
45 60 75 ns
PWM comparator
Delay to output Guaranteed by design 25 ns
Minimum duty cycle CTL = 0, CS = 0 0 %
Maximum duty cycle CTL = 2 V, CS = 0, F
CTL to PWM gain Guaranteed by design 1 : 4
CTL operative range 1 3 V
Output driver GAT1
Output high I
Output low IGD = -100 mA 0.25 0.5 V
Fall time
Rise time
= 250 kHz 75 80 85 %
osc
= 100 mA
GD
= 3.3 nF, VC = 10 V
C
LOAD
Guaranteed by design
C
= 3.3 nF, VC = 10 V
LOAD
Guaranteed by design
VC-
0.25
VC-0.5 V
40 ns
45 ns
Doc ID 018559 Rev 1 15/34
Electrical specifications PM8803
Table 6. Electrical characteristics - SMPS section (continued)
Symbol Parameter Test conditions Min. Typ. Max. Unit
= 3.3 nF, VC = 10 V
C
Peak source current
Peak sink current
Output driver GAT2
LOAD
Guaranteed by design
= 3.3 nF, VC = 10 V
C
LOAD
Guaranteed by design
800 mA
1A
Output high I
Output low IGD = -100 mA 0.25 0.5 V
Fall time
Rise time
Peak source current
Peak sink current
Thermal shutdown
Shutdown temp.
Shutdown hyst. 30
VC regulation
Internal default 7.7 8.0 8.3 V
VC
VC current limit IB = 0; GAT1, GAT2 = Open 14 20 mA
Internal default
UVLO, release
VC
UVLO
Internal default;
UVLO, lockout
VC regulator
dropout
= 100 mA
GD
C
= 3.3 nF, VC = 10 V
LOAD
Guaranteed by design
C
= 3.3 nF, VC = 10 V
LOAD
Guaranteed by design
= 3.3 nF, VC = 10 V
C
LOAD
Guaranteed by design
C
= 3.3 nF, VC = 10 V
LOAD
Guaranteed by design
Always active;
Guaranteed by design
VC-
0.25
VC-0.5 V
40 ns
45 ns
800 mA
1A
160
°C
°C
VC rising VC-0.3 V
VC falling 5.7 6.0 6.3 V
IC = 10 mA; GAT1, GAT2 = Open 2 V
VB regulation
Internal default 4.85 5.0 5.15 V
VB
VB current limit IC = 0; GAT1, GAT2 = Open 5 10 mA
VB sink current capability 1 mA
Rear auxiliary source detection
SA threshold 1.1 1.2 1.3 V
SA hysteresis 180 mV
16/34 Doc ID 018559 Rev 1
PM8803 Electrical specifications
Table 6. Electrical characteristics - SMPS section (continued)
Symbol Parameter Test conditions Min. Typ. Max. Unit
Minimum VDD voltage for
rear aux. operations
13 15 V
T2P flag
T2P pull-up current 20 25 30 μA
T2P pull-down resistance 45 75 Ω
Device current consumption
VD quiescent current VD > V
VC quiescent current VD > V
UVLO_R,
UVLO_R,
VC = 12 V, CTL = 0 1.25 1.5 mA
VC = 12 V, CTL = 0 2 2.5 mA
Note: 1 Minimum and maximum limits are guaranteed by test, design, or statistical correlation.Typical values
represent the most likely parametric norm at T
= 25 °C, and are provided for reference only.
A
2 Device thermal limitations could limit useful operating range.
3 The VC regulator is intended for internal use only as the startup supply of the PM8803; any additional
external VC current, including the VB regulator current and external MOSFET driving current, has to
be limited within the specified max current limit.
Doc ID 018559 Rev 1 17/34
PD interface PM8803
4 PD interface
4.1 Detection
In Power over Ethernet systems, the Power Sourcing Equipment (PSE) senses the Ethernet
connection to detect whether the Powered Device (PD) is plugged into the cable termination
by applying a small voltage (2.7 V to 10 V) on the Ethernet cable and measuring the
equivalent resistance in at least two consecutive steps. During this phase, the PD must
present a resistance between 23.75 kΩ and 26.25 kΩ.
The signature resistor must be connected between the DET and VDD pins. This resistor is
in-series to a pass transistor (see Figure 3) enabled only during the detection phase. No
current is flowing through the signature resistor for the rest of the operative phases
(classification and turn-on).
The value of the detection resistance has to be selected also taking into account the typical
drop in voltage of the diode bridges. The typical value that can be used in most case is
24.9 kΩ.
During detection, most of the circuits inside the PM8803 are disabled to minimize the offset
current.
4.2 Classification
The classification phase in a PoE network is the feature that allows PSE to plan and allocate
the available power to the appliances connected to various Ethernet ports.
The PM8803 complies with both IEEE802.3at 1-event and 2-event classification schemes.
1-event classification in IEEE802.3at is the same as specified in the IEEE 802.3af standard,
which divides the power levels below 12.95 W into 5 classes (Class 0 to Class 4).
While Class 4 was reserved in IEEE802.3af, in IEEE802.3at Class 4 identifies Type2 PDs
requiring up to 25.5 W.
A Type2 PD is a PD that provides a Class 4 signature during Physical Layer Classification,
understands 2-event classification and is capable of Data Link Layer classification.
Figure 8 represent the voltage at the input of the PD when connected to a PSE performing
2-event classification. A Type2 PD will present in both classification events a Class 4 current
while during the so called “mark-event”, between the 2 classification fingers, the PD will
present an invalid signature resistance.
To support the classification function, an equivalent programmable constant current
generator has been implemented. Figure 6 depicts a primary schematic of the classification
circuit. Following the successful completion of the detection phase, the voltage of the CLS
pin is set to the 1.4 V voltage reference and a pass transistor connects the VIN pin to the
CLS pin.
18/34 Doc ID 018559 Rev 1
PM8803 PD interface
Figure 6. PM8803: reference schematic of the PoE classification logic
PM8803
VDD
Thermal_alarm
1.4V
+
EN
-
Class_enable
Aux_enabled
AM045096v1
R
CLS
CLASS
VSS
The classification resistor can be disconnected for the following reasons:
– the classification has been successfully completed
– an auxiliary power source has been connected
– the device is in thermal protection
Designers can set the current by changing the value of the external resistor according to the
following table.
Table 7. Value of the external classification resistor for the different PD classes of
power
Class PD max average power (W) R
013 2k
13.84 150
26.49 80.6
313 51.1
CLS
(Ω)
4 25.5 35.6
4.3 Indication of successful 2-event classification
The PM8803 is capable of recognizing whether it is connected to a PSE performing 1-event
or 2-event physical layer classification by asserting the T2P signal.
T2P is an open-drain, active-low signal which is asserted in case a successful 2-event
classification event is completed.
T2P will be asserted as soon as the high-voltage startup regulator output is stable. ( see
Figure 7 and Figure 8 for timing sequences). If the PM8803 sees a 1-event classification or
no classification, T2P is pulled up and the main circuit in the PD can try to establish an
LLDP connection to negotiate the power. No LLDP response from the PSE means that the
PD is connected to a Type1 PSE, and only 13 W input power will be available.
Doc ID 018559 Rev 1 19/34
PD interface PM8803
A low T2P signal after the turn-on phase of the POE means that the PD is connected to a
Type2, 2-event physical layer classification PSE which may allocate power either through
further LLDP negotiation or directly feedthe PD with the required power.
In isolated applications, the main circuits and the PM8803 are at both sides of the galvanic
isolation. The T2P signal is normally connected to an optocoupler to pass the
Type 2, 2-event PSE detection information to the main circuit in the PD system.
Figure 7. T2P signal when connected to PSE supporting 1-event classification
PSE voltage
Detection
V
V
OUTPUT VOLTAGE
T2P (802.3af)
Soft Start
T2P stable before
output soft-start
Classification Range
Idle or Mark Range
On range
Time
Time
Time
AM045097v1
Figure 8. T2P signal when connected to PSE supporting 2-event classification
PSE voltage
Classification Range
On range
Detection
V
OUTPUT VOLTAGE
V
T2P (802.3at)
T2P stable before
output soft-start
Soft Start
20/34 Doc ID 018559 Rev 1
Idle or Mark Range
Time
Time
Time
AM045098v1
PM8803 PD interface
4.4 Undervoltage lockout
After classification is completed, the PSE raises the voltage to provide the Power Devices
with the negotiated power. During the transition from low to operating voltage, the internal
UVLO is released and the hot-swap MOSFET is activated, initiating the inrush sequence.
The PM8803 implements the UVLO mechanism by setting 2 internal thresholds on the
voltage across the VDD-VSS pins; one is to activate the hot-swap (V
UVLO_R
is to switch off the hot-swap MOSFET upon detection of a supply voltage drop (V
), while the other
UVLO_F
)
from normal operating conditions.
No additional external components are required to comply with the IEEE requirements. The
thermal protection alarm overrides the gate driving of the MOS, immediately switching off
the MOS itself in case of device overheating. The hot-swap is bypassed also in auxiliary
source topology, supplying directly the PWM section of the PM8803 and bypassing the hot-
swap MOSFET.
4.5 Inrush and DC current limiting
Once the detection and classification phases have been successfully completed, the PSE
raises the voltage across the Ethernet cable. When the voltage difference between VIN and
VSS is greater than the V
UVLO_R
and the DC/DC input capacitance is charged in a controlled manner.
threshold, the internal hot-swap MOSFET is switched on
During the inrush phase, the current is limited to 140 mA.
When the RTN voltage falls below 1.5 V, an internal signal (PGOOD in Figure 3) is asserted
to activate the DC/DC section.
Figure 9. Line transient response
Ch1: RTN - VSS, Ch2: VDD - VSS, Ch3: Iinput, Ch4: 5Vout (with offset)
Doc ID 018559 Rev 1 21/34
AM045099v1
PD interface PM8803
This feature is active only when working from an input voltage with a "frontal" connection,
that must use the hot-swap MOSFET; this voltage could be from the PoE interface or from
an external auxiliary adapter connected before the internal hot-swap MOSFET.
If the auxiliary source is connected after the hot-swap MOSFET, it will be opened and this
feature is disabled, allowing the converter to work with a low-voltage auxiliary source. The
PGOOD comparator includes hysteresis to allow the PM8803 to operate near the current
limit point without inadvertently disabling it. The MOSFET voltage must increase to 12 V
before PGOOD is deasserted.
This feature will also allow withstanding positive line transients of up to 12 V without
stopping DC/DC normal operations as shown in Figure 9. The line transient is managed by
the PWM section, adjusting its operating parameters accordingly without shutting down the
output voltage. The input current during the transient is controlled by the hot-swap MOSFET
at the DC current limit.
After PGOOD assertion, a comparator on the gate of the hot-swap MOSFET controls the
transition between the 140 mA to the programmed DC current limit, with a 2 V threshold.
The comparator is needed to ensure that the charge of the DC/DC input capacitor is
completed, avoiding current spikes on the last portion of the charge.
The PM8803 provides a default continuous current limitation of 640 mA. This is achieved by
leaving the pin DCCL floating. A different DC current limit can be set by connecting a
resistor R
between DCCL and VSS whose value can be obtained by the following
DC
equation:
22400
RDCkΩ[]
-----------------------=
I
DC
mA[]
Figure 10. DC current vs. R
1120
1020
920
820
720
IDC [mA]
620
520
420
320
220
120
20
20 40 60
DC
80100
RDC [kOhm]
120 140
160
AM045100v1
22/34 Doc ID 018559 Rev 1
PM8803 PD interface
This limitation is active after the in-rush phase is completed. The useful programming range
for the current limitation is between 140 mA and 1 A. The practical resistor value range is
between 22 kΩ and 150 kΩ.
4.6 High-voltage startup regulator
The PM8803 embeds a high-voltage startup regulator to provide a controlled reference
voltage of 8.0 V to the internal current mode PWM controller during its startup phase.
The regulator output is connected to the VC pin as well as to the DC/DC section
In normal isolated topology, the VC pin is diode-connected to the auxiliary winding of the
transformer used for the flyback or forward configuration. When the voltage from the
transformer exceeds the regulated voltage, the high-voltage regulator is shut off, reducing
the amount of power dissipated inside the PM8803.
In more detail, when the voltage from the auxiliary winding exceeds 8.0 V, the regulator
resets its intervention threshold to 7 V. In this way, a loosely regulated voltage from the
auxiliary winding is allowed without current-sharing with the internal regulator.
In the meantime, if the auxiliary voltage fails, the internal regulator takes over without losing
DC/DC control.
The UVLO threshold on VC is 6.0 V typically: at this voltage the DC/DC controller operations
are stopped and the outputs frozen in low state.
While the external auxiliary voltage has to be chosen higher than 8.0 V to take advantage of
the auxiliary winding, it must be also lower than 16 V for all operating conditions, to avoid the
intervention of the internal protection clamp.
A capacitor in the range of 220 nF-10 uF must be connected to DC/DC ground for stability.
For applications with high current drawn from VC, large capacitance should be used (e.g.
10 µF) in order to avoid converter switch-off during the startup phase.
A VC UVLO mechanism monitors the level of voltage on the VC pin. When VC voltage
exceeds the VC
UVLO_R,
voltage drops below its VC
the PWM controller is enabled and it remains enabled until the VC
UVLO_F
value.
When an auxiliary winding is not used, the internal HV regulator UVLO threshold is set at
6.6 V and the current limit is set at 20 mA typ. This value includes the current internally
drawn to bias the DC/DC controller, the gate drivers, the VB bias regulator and the external
components that may be connected to the VC and VB pins.
Notice that using the HV regulator without the auxiliary winding increases the internal power
dissipation, and, when operating at high ambient temperature, may lead the device to go
into thermal shutdown.
Doc ID 018559 Rev 1 23/34
PD interface PM8803
4.7 5 V bias regulator
The PM8803 features an accurate 5 V output regulator, which can be used to bias the
DC/DC feedback network and the optocoupler connected to the microcontroller.
A capacitor in the range of 100 nF - 2.2 µF must be connected to ARTN for stability.
The regulator current is supplied from the VC pin, to take advantage of the more efficient
bias from the auxiliary winding. This means that the current drawn from the VB pin must be
taken into account to evaluate the maximum current drawn from the VC pin
The current drawn from the VB pin must be limited to 10 mA maximum.
The VB regulator is also able to accept injected current up to 1 mA without losing voltage
regulation.
24/34 Doc ID 018559 Rev 1
PM8803 PWM controller
5 PWM controller
5.1 Oscillator
The internal oscillator frequency can be programmed by connecting an external resistor RT
between the FRS and ARTN pins. The relationship between the oscillator frequency F
and the R
F
osc
resistor is:
T
kHz()
25000
--------------------------------------=
3kΩ R+
kΩ()
T
The PWM switching frequency is equal to the programmed oscillator frequency.
OSC
The useful range for R
is between 20 k to 200 kOhm
T
Figure 11. PWM frequency vs. R
1100
1000
900
800
700
F
OSC
[kHz]
600
500
400
300
200
100
0
0 20 40 60 80 100 120 140 160 180 200 220 240
T
T
[kOhm]
R
AM045101v1
5.2 Delay time control
The delay between the rising edge of GAT2 and GAT1 waveforms can be set by putting a
programming resistor R
delay time and the R
t
ns() 1.6RDTkOhm()=
del
DT
resistor is:
DT
between DT and AGND or VB. The relationship between the
Doc ID 018559 Rev 1 25/34
PWM controller PM8803
The same delay time is set between the GAT1 falling edge and the subsequent GAT2 falling
edge.
The useful range for R
is between 5 k to 200 kOhm. A resistor should always be
DT
connected to this pin.
Figure 12. Delay time vs. R
320
300
280
260
240
220
200
DT [ns]
180
160
140
120
100
80
60
40
20
0
0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 170 180 190 200
DT
RDT[KOhm]
AM045102v1
Figure 13. Timing relationship between output drivers as a function of DT
GAT1
GAT2
DT DT
26/34 Doc ID 018559 Rev 1
AM045103v1
PM8803 PWM controller
5.3 Soft-start
The DC/DC section of the PM8803 features an internal, digitally controlled, soft-start to
make sure that output voltage ramps up in a safe and controlled manner.
At the startup of the converter, the input voltage of the PWM comparator (CTL pin) is
clamped to a value which is increased cycle by cycle until it reaches the regulation voltage.
This results in a converter duty-cycle increasing from zero to the operative value in 4096
switching periods maximum.
Taking into account that the output voltage will start to increase only when the CTL pin is
higher than 1 V, effective duration of the output voltage soft-start ramp can be estimated with
the following formula:
TSSms[]
4096
------------------------------
F
OSC
CTL V[] 1V–
----------------------------------
⋅=
kHz[]
4V
5.4 PWM comparator / slope compensation
In typical isolated operations, current is sensed on a sense resistor Rs put between the
source of the primary side MOS and the RTN pin.
The PWM comparator produces the PWM duty cycle by comparing the Rs ramp signal on
CS with an error voltage derived from the error amplifier output.
The error amplifier output voltage at the CTL pin is attenuated by a 4:1 resistor divider
before it is presented to the PWM comparator input.
The PWM duty cycle increases with the voltage at the CTL pin. The controller output duty
cycle reduces to zero when the CTL pin voltage drops below approximately 1 V.
For duty cycles greater than 50%, current mode control loops are subject to sub-harmonic
oscillation. The PM8803 fixes the maximum duty cycle at 80% and implements a slope
compensation technique consisting of adding an additional fixed slope voltage ramp to the
signal at the CS pin. This is achieved by injecting a 45 µA sawtooth current into the current
sense signal path on an integrated 2
Additional slope compensation may be added by increasing the source impedance of the
current sense signal with an external resistor between the CS pin and the source of the
current sense signal. The net effect in this case is to increase the slope of the voltage ramp
at the PWM comparator terminals.
kΩ resistor.
5.5 Current limit
The current sensed through the CS pin is compared to two fixed levels of 0.5 V and 0.7 V.
The lower level is used to perform a cycle-by-cycle current limit, terminating the PWM pulse.
If the overload persists for a duration longer than 4096 switching periods, the PWM is shut
down for the same duration before beginning a new soft-start.
At 250 kHz the allowed overcurrent duration is about 16 ms.
Doc ID 018559 Rev 1 27/34
PWM controller PM8803
When a severe overcurrent occurs, like a short-circuit of an internal power component, and
0.7 V level is reached on CS, the gate driver is instantaneously shut down and a new softstart is performed after 4096 switching periods.
In case of persistent severe overcurrent, the control logic tries 4 cycles of fast hiccup before
completely shutting down the PWM controller.
To restart the device, after removing the cause of the overcurrent, VDD must be reduced
below the UVLO level.
Figure 14. Overload (left) and short-circuit (right) behavior
Ch1: CTL signal, Ch2: 5Vout, Ch3: I input
5.6 Thermal protection
The PM8803 thermal protection limit is set to 160 °C on the junction temperature and is
always active. When this threshold is exceeded, the hot-swap MOSFET is opened and the
PWM controller is switched off.
When the junction temperature goes below about 130 °C, the converter will start
automatically, without recycling the input voltage.
AM045104v1
28/34 Doc ID 018559 Rev 1
PM8803 Auxiliary sources
6 Auxiliary sources
The majority of Powered Devices is designed to work with power from either a PoE network
or auxiliary sources. Even though having both sources simultaneously connected is not the
normal operating case, the presence of an auxiliary supply allows PDs to be used also when
the PoE is not available or not sufficient.
Different alternatives are available for connecting auxiliary sources to the PoE section of a
PD device. Auxiliary sources can be connected prior to the hot-swap MOSFET, after the hotswap MOSFET or even at the output of the DC/DC converter.
All the above-mentioned methods are available with the PM8803.
Both Figure 1 and Figure 2 show simplified application schematics where auxiliary sources
can be connected either Prior (Front) or After (Rear) the internal hot-swap MOSFET (VDD
and RTN) making use of a resistor divider between the external source and respectively SP
or SA pins.
Connection of the wall adapter prior to the internal hot-swap MOSFET has a limitation on
the voltage of the adapter itself, since it is seen as an alternative of the PoE line and the
embedded DC/DC section would be activated only when its value is above the UVLO_R
threshold. If the voltage on the SP pin is above 1.1 V, the internal UVLO threshold is
bypassed and the PM8803 operates with voltage as low as 15 V typical. The current flowing
into the hot-swap MOSFET will be limited by a dual threshold: typically140 mA during the
inrush phase, and a user programmable value (DCCL pin) for the rest of the phases. Priority
of one source over another cannot be guaranteed by design, since it depends on timings of
insertion and the value of the PoE line with respect to the auxiliary. If, for example, the PoE
connection is already established, the auxiliary source cannot prevail unless its value is
higher than that of the PoE after the diode bridge.
Please note that with the use of a low-voltage adapter applied before the hot swap frontal
connection, the max power drawn could be evaluated as ( Vin - Vd ) x Imax; in case of a
15 V adapter the input power will be limited to about (15 - 0.5) x 1 A = 14.5 W, much lower
than the available power from the PoE connection.
High-power systems must use high-voltage power adapters, with voltage at 48 V, and rear
connections, not to be limited by the internal DC current limitation.
Both Figure 1 and Figure 2 show simplified application schematics where auxiliary sources
are also connected after the internal hot-swap MOSFET (VDD and RTN). This connection,
together with the resistor divider on the SA pin, allows priority of the external source with
respect to the PoE. Indeed, if the voltage of this pin is above the value of 1.20 V, the PM8803
will disable its PD interface section and enable the DC/DC section only. The internal hotswap MOSFET will be opened.
Depending on the value of the auxiliary source, the resistor divider must be dimensioned in
order to have voltage on the SA and SP pins above their thresholds but still below their
maximum operative value of 3.3 V specified in Tab le 3.
Figure 15 depicts a smooth transition between a PoE and a wall adapter whose voltage is
5 V higher than the PoE voltage.
Doc ID 018559 Rev 1 29/34
Auxiliary sources PM8803
Figure 15. Smooth transition from POE to auxiliary source
AM045105v1
Ch1: VSS-RTN, Ch2: SA, Ch3: Iinput, Ch4: 5Vout
The minimum operative voltage for auxiliary sources is 13 V, thus allowing the use of a 15 V
typ. +/-5% power adapter. The internal logic will enable operations of the PWM controller
only if the input voltage is over the signature threshold (10.8 V typ, 10.3 V -11.3 V range).
Note that inrush current in this case is not limited and an external solution must be found.
The simplest solution is to put a low value resistor in-series, but this lowers the converter’s
efficiency. A more efficient solution is the use of a MOSFET as the power switch, able to limit
the current during the charging phase, and to add only a few mΩ in-series during normal
operation.
No DC current limit is foreseen for the rear connection, since the current will not be flowing
through the hot-swap MOSFET. Cycle-by-cycle, overcurrent protection and thermal
protection are instead always active, as well as when the voltage on the SA pin is above
1.20 V.
The T2P signal will remain high (de-asserted) if a rear auxiliary source is connected.
If the T2P signal was asserted when the auxiliary source was connected, it will be turned
off; its status is stored unless the input voltage drops. So if the PSE stays connected until
the auxiliary source is removed, the T2P indication turns on again when the wall adapter is
disconnected.
The removal of the external auxiliary source such as a wall adapter usually is followed by a
system reboot because the PSE needs some time to re-detect the PD.
If a rear auxiliary connection (using the SA pin) is foreseen in the converter design, it is
suggested to move the 0.1 µF capacitor required by the IEEE802.3at standard from the
input (VDD to VSS ) to the the internal hot-swap MOSFET (VSS to GND) . Alternatively, split
the 0.1 µF in two capacitors of 47 nF: one placed at the input terminal, the second one
across the hot-swap MOSFET.
30/34 Doc ID 018559 Rev 1
PM8803 HTSSOP20 package mechanical data
7 HTSSOP20 package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK®
®
is an ST trademark.
Table 8. HTSSOP20 mechanical data
mm inch
Dim.
Min. Typ. Max. Min. Typ. Max.
A 1.2 0.047
A1 0.15 0.004 0.006
A2 0.8 1 1.05 0.031 0.039 0.041
b 0.19 0.30 0.007 0.012
c 0.09 0.20 0.004 0.0089
D 6.4 6.5 6.6 0.252 0.256 0.260
D1 4.1 4.2 4.3 0.161 0.165 0.169
E 6.2 6.4 6.6 0.244 0.252 0.260
E1 4.3 4.4 4.5 0.169 0.173 0.177
E2 2.9 3.0 3.1 0.114 0.118 0.122
e 0.65 0.0256
K 0° 8° 0° 8°
L 0.45 0.60 0.75 0.018 0.024 0.030
Doc ID 018559 Rev 1 31/34
HTSSOP20 package mechanical data PM8803
Figure 16. HTSSOP20 mechanical drawing
GAUGE PLANE
32/34 Doc ID 018559 Rev 1
7292297_C
PM8803 Revision history
8 Revision history
Table 9. Document revision history
Date Revision Changes
10-Mar-2011 1 Initial release.
Doc ID 018559 Rev 1 33/34
PM8803
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