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PM8800A
User Manual
35 pgs568.31 Kb0
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ST PM8800A User Manual

Integrated IEEE 802.3af compliant PoE-PD interface
and PWM controller with support of external source
Features
■ IEEE 802.3af compliant PD interface
■ Works with power supplied from Ethernet LAN
■ Integrated 100 V, 0.5 Ω, 800 mA hot-swap
MOSFET
■ Integrated signature resistor
■ Programmable in-rush current limit
■ Programmable classification current
■ Programmable DC current limit up to 800 mA
■ High voltage start-up bias regulator
■ Thermal shutdown protection
■ Current mode pulse width modulator
■ Programmable oscillator frequency
■ Programmable soft-start
■ Power good indication
■ 80 % maximum duty cycle with internal slope
compensation
■ Supports both isolated and non-isolated
Applications.
■ HTSSOP16 package
Applications
■ VoIP phones, WLAN access points
■ Security cameras
■ PoE powered device appliances
■ High power (>12.95 W) powered devices
PM8800A
HTSSOP16
Description
The PM8800A integrates a standard power over Ethernet (PoE) interface and a current mode PWM controller to simplify the design of the power supply sections of all powered devices.
The PoE interface incorporates all the functions required by the IEEE 802.3af including detection, classification, under-voltage lockout (UVLO) and in-rush current limitation.
PM8800A specifically targets PD with extended power requirement with respect to the limit imposed by the 802.3af standard, embedding a hot-swap MOSFET capable of sustaining twice the current of the 802.3af standard with a programmable DC current limit.
The integrated switching regulator has been designed to work with power either form the Ethernet cable connection or from an external power source such as AC adapter.
The DC-DC section of the PM8800A features a programmable oscillator frequency, soft-start, slope compensation and embeds a voltage output error amplifier allowing use in both isolated and non isolated configuration.

Table 1. Device summary

Order codes Package Packing
PM8800A HTSSOP16 Tube
PM8800ATR HTSSOP16 Tape and reel
February 2008 Rev 2 1/35
www.st.com
35
Contents PM8800A
Contents
1 Typical application circuit and block diagram . . . . . . . . . . . . . . . . . . . . 4
1.1 Application circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 Pins description and connection diagrams . . . . . . . . . . . . . . . . . . . . . . 6
2.1 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.2 Electrical characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4 Device description and operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5 PD interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.1 Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.2 Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.3 Under voltage lock-out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.4 In rush current limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.5 Continuos current limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.6 HV regulator startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.7 Power good indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6 PWM section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.1 Error amplifier and loop compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.2 Oscillator and sync capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.3 Soft start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.4 PWM comparator / slope compensation . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.5 Current limiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.6 Leading edge blanking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.7 Thermal protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2/35
PM8800A Contents
7 Auxiliary sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
8 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
8.1 HTSSOP16 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3/35
Typical application circuit and block diagram PM8800A

1 Typical application circuit and block diagram

1.1 Application circuits

Figure 1. Simplified application schematic for powered devicesing PM8800A in isolated
configuration
VIN
AUXI_IRL
DCCL RCLASS
VSS
PM8800
A
AUXII
VCC
GD
COMP
nPGD
CS
VFB
SS RT
GND
AGND
Figure 2. Simplified application schematic for powered device using PM8800A in non-isolated
buck configuration
Vin
VIN AUXII nPGD
AUXI_IRL
DCCL RCLASS
VSS
PM8800
A
GD
VFB
VCC
COMP
CS SS RT
GND
AGND
Vout+
Vout-
4/35
PM8800A Typical application circuit and block diagram

1.2 Block diagram

Figure 3. Block diagram of the PoE PD interface

Zener Ref
1.25V
1.4V
0.6V
Thermal
Protection
AUXII
AUX
Manager
threshold
-
+
UVLO
High Voltage
Startup
Regulator
DC/DC
controller
Power
Good Ctrl
Logic
1.5V
DC/DC Enable
UVLO VCC
threshold
+
-
VCC
30uA
-
+
VCC
1.5V
+
-
nPGD
2V
VIN
RCLASS
AUXI_IRL
DCCL
3.3V
3.3V
24.5k
Detection
threshold
Classification
threshold
1.4V
+
-
EN
1.4V
+
-
1.4V
+
-
Interface Manager
2V
+
-
Gate
Controller
-
+
-
+
VSS
Current and
Voltage
Sense

Figure 4. Block diagram of the current mode PWM controller

RT
AGND
COMP
FB
SS
10µA
10
charge
10
10µA
discharge
1.25V
A
A
3.3V
+
E/A
-
fast discharge
+
-
LOGIC
3.3V
SS
2.5kOhm
discharge
charge
R
R
Oscillator
Slope
Compensation
0.5V
0.7V
+
PWM
-
+
OC1
-
+
OC2
-
45 A
45µA
PWM
logic
y Cycle by cycle over current
protection
y
80% duty cycle limit (PM8800A)
y Leading Edge Blanking
Hiccup on OC2 or
y
persistent OC1
SET
S
Q
R
Q
CLR
DC/DC Enable
VCC
Driver
GND
GD
CS
5/35
Pins description and connection diagrams PM8800A
0

2 Pins description and connection diagrams

Figure 5. Pins connection (top view)

AUXII
RCLASS
AUXI_IRL
DCCL

2.1 Pin descriptions

Table 2. Pin description

Pin# Name Function
Oscillator timing resistor pin and synchronization input.
1RT
An external resistor connected from RT to AGND sets the oscillator frequency. This pin will also accept narrow ac-coupled synchronization pulses from an external clock.
RT
SS
VIN
VSS
16
15
14
4
13
11
1
HTSSOP-16
AGND
VFB
COMP
CS
nPGD
VCC
GD
9
GND
Soft-start input.
2SS
3AUXII
4VIN
5 RCLASS
6 AUXI_IRL
6/35
An external capacitor connected from SS and AGND and an internal 10 µA current source set the soft-start ramp rate. this pin is also used to set the hiccup timer in case of overcurrent conditions. See Section 6 for detail.
Auxiliary source enable pin. Use this pin to power up the DC/DC section only from the external source. The
auxiliary source can prevail over the PoE source depending on the value of the resistor between this pin and the external source. See Section 7 for detail.
System high potential input. The diode “OR” of PoE line and auxiliary sources connected to the PD, it is the
most positive input potential.
Classification resistor pin. Connect a classification programming resistor between this pin and VSS.
In-rush current limit and auxiliary source enable pin. Pulling up this pin to the auxiliary source will change the internal UVLO settings
and allow PD to be powered with voltage lower than nominal PoE voltages. In this condition inrush current limit is set to default values. See Section 7 for details.
A resistance between this pin and VSS will set the level of inrush current limit.
PM8800A Pins description and connection diagrams
Table 2. Pin description (continued)
Pin# Name Function
DC current limit.
7DCCL
8 VSS System low potential input.
A resistor between DCCL and VSS will set the current limit for the interface section of the PM8800A. It can be set to exceed the IEEE802.3af current limit.
Leave the pin open for standard IEEE 802.3af applications.
9GND
10 GD Output of the PWM controller. External power MOSFET gate driver output.
11 VCC
12
nPGD
13 CS
14 COMP
15 VFB
16 AGND
System return for the PWM converter. It is the drain of the internal hot-swap power MOSFET.
Output of the internal high voltage regulator. When the auxiliary transformer winding (if used) raises the voltage on this pin
above the regulation set point, the internal regulator will be switched off, reducing the controller power dissipation.
Power good, active low signal. A high to low transition indicates that the inrush current phase has been
completed, the internal hot swap MOSFET is fully closed and the SMPS portion of the PM8800A is activated.
Current sense input. Current sense input for current mode control and over-current protection. Current
limiting is obtained with a dedicated current sense comparator. If the CS pin voltage exceeds 0.5 V the GD pin switches low for cycle-by-cycle current limiting.
Leading edge blanking is implemented to mask current spikes.
The output of the error amplifier and input of the Pulse Width Modulator. COMP pull-up is provided by an internal 2.5 kΩ resistor which may be used to
bias an opto-coupler transistor.
Feedback signal. Inverting input of the internal error amplifier. The non-inverting input is internally
connected to a 1.25 V reference. If not used must be grounded to AGND.
Analog PWM supply return. GND for sensitive analog circuitry including the SMPS current limit circuitry. Must
be connected to GND to improve noise immunity.
EP
Exposed pad. Connect this to a board plane to improve heat dissipation; must be electrically
connected to VSS
7/35
Pins description and connection diagrams PM8800A

2.2 Thermal data

Table 3. Thermal data

Symbol Parameter Value Unit
R
thJA
T
MAX
T
STG
T
J
T
A
1. Package mounted on 4 layers 35 micron demoboard
Max thermal resistance junction to ambient
Maximum junction temperature 150 °C
Storage temperature range -40 to 150 °C
Junction temperature range -40 to 125 °C
Operative temperature range -40 to 85 °C
(1)
50 °C/W
8/35
PM8800A Electrical specifications

3 Electrical specifications

3.1 Absolute maximum ratings

Table 4. Absolute maximum ratings

Parameter Value Unit
VIN, GND to VSS -0.3 to 100 V
AUXI_IRL to VSS -0.3 to 100 V
DCCL, RCLASS to VSS -0.3 to 3.6 V
AUXII to AGND -0.3 to 100 V
COMP, SS to AGND -0.3 to 3.6 V
VFB, RT, CS to AGND -0.3 to 3.6 V
VCC, GD to AGND -0.3 to 15 V
nPGD to AGND -0.3 to 15 V
GND to AGND -0.3 to 0.3 V
Note: Absolute maximum ratings are limits beyond which damage to the device may occur.
9/35
Electrical specifications PM8800A

3.2 Electrical characteristic

Table 5. Electrical characteristics - interface section

(V
= 48 V, VCC = open, TA = 25 °C unless otherwise specified).
IN
Symbol Parameter Test conditions Min Typ Max Unit
Detection and classification
Signature enable VIN rising 1.5
Signature resistance 23.5
Signature disable classification turn on
VIN rising 10.5
(1)
(1)
24.5 25.5
11.5 12.5
(1)
(1)
(1)
V
kΩ
V
Classification turn on hysteresis
Classification turn-off V
RCLASS voltage during classification
Supply current during classification
Bias current
IIN V
supply current VIN = 48 V; VCC = 10 V 3 mA
IN
Under Voltage Lock-Out
V
UVLO_R
V
UVLO_F
UVLO release VIN rising 37 38.5 40
UVLO lock-out VIN falling 30
UVLO hysteresis 7.0 V
Hot swap MOSFET
R
DSON
MOSFET resistance 0.5 1
Default in-rush current limit
Default in-rush current limit
1.40 V
1.37
(1)
23 24.5
(1)
1.4 1.43
(1)
31.5 33.5 V
(1)
140 160
(1)
250 280
rising 21.5
IN
inside classification range 1.8 mA
V
IN
> 30 V 120
V
IN
15 V < V
< 30 V 220
IN
(1)
(1)
(1)
(1)
(1)
(1)
V
V
V
Ω
mA
mA
Default in-rush current limit
Adjustable in-rush current limit
1.5 V < V
R
AUXI_IRL
< 15 V 390
IN
= 82 kΩ 120
Default DC current limit 390
Adjustable DC current limit precision
= From 15.4 kΩ to 82 kΩ -15
R
DCLL
10/35
(1)
(1)
(1)
(1)
440 490
140 160
440 490
-+15
(1)
(1)
(1)
(1)
mA
mA
mA
%
PM8800A Electrical specifications
Table 5. Electrical characteristics - interface section (continued)
(V
= 48 V, VCC = open, TA = 25 °C unless otherwise specified).
IN
Symbol Parameter Test conditions Min Typ Max Unit
Power good indication
Hot-swap VDS V
Hysteresis 1.45 V
Hot-swap VGS required for power good
nPGD current source 25
nPGD
nPGD pull down resistance
nPGD threshold nPGD rising 1.7
Auxiliary power
AUXI_IRL UVLO release VIN rising 15
AUX I
AUXI_IRL UVLO lock-out VIN falling 11.5
AUXI / IRL switch-over threshold
falling 1.45
DS
(1)
1.60 1.75
Guaranteed by design 2 V
(1)
30 35 µA
nPGD low; I = -5 mA 0.5
V
AUXI_IRL
(1)
(1)
rising 2 V
22.3
16 17
(1)
12.5 13.5
(1)
(1)
(1)
(1)
(1)
V
V
V
V
V
AUX II
Bias voltage I
= 0 to -250 µA 0.85 1.1 1.4 V
AUXII
Lower threshold current 20 35 50 µA
Upper threshold current 80 100 120 µA
11/35
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