ST PM6685 User Manual

with auxilary voltages for notebook system power

Features

■ 6 V to 28 V input voltage range

■ Fixed 5 V - 3.3 V output voltages

■ 5 V and 3.3 V voltage always available to

deliver 100 mA of peak current

PM6685

Dual step-down main supply controller

■ 1.230 V ±1% reference voltage available

■ Lossless current sensing using low side

■ MOSFETs' R

■ Negative current limit

■ Soft-start internally fixed at 2 ms

■ Soft output discharge

■ Latched OVP and UVP

■ Selectable pulse skipping at light loads

■ Selectable minimum frequency (33 kHz) in

DS(on)

pulse skip mode

■ 4 mW maximum quiescent power

■ Independent power good signals

■ Output voltage ripple compensation

Applications

■ Notebook computers

■ Tablet PC or slates

■ Mobile system power supply

■ 3 and -4 Cells Li+ battery-powered devices

VFQFPN-32 (5mm x 5mm)

Description

PM6685 is a dual step-down controller specifically
designed to provide extremely high efficiency
conversion with loss-less current sensing
technique. The constant on-time architecture
assures fast load transient response and the
embedded voltage feed-forward provides nearly
constant switching frequency operation.

An embedded integrator control loop
compensates the DC voltage error due to the
output ripple. The pulse skipping technique
increases efficiency for very light loads. Moreover,
a minimum switching frequency of 33kHz is
selectable in order to avoid audio noise issues.

The PM6685 provides a selectable switching
frequency, allowing either 200 kHz/300 kHz, 300
kHz/400 kHz, or 400 kHz/500 kHz operation of
the 5 V/3.3 V switching sections.

Table 1. Device summary

Order code Package Packaging

PM6685

VFQFPN-32 (5 mm x 5 mm)

PM6685TR Tape and reel

March 2011 Doc ID 11674 Rev 8 1/48

Tube

www.st.com

48

Contents PM6685

Contents

1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.1 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.2 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

3 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3.1 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

5 Typical operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

6 Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

7 Device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

7.1 Constant on time PWM control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

7.2 Constant on time architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

7.3 Output ripple compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

7.4 Pulse skip mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

7.5 No-audible skip mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

7.6 Current limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

7.7 Soft start and soft end . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

7.8 Gate drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

7.9 Reference voltage and bandgap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

7.10 Internal linear regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

7.11 Power up sequencing and operative modes . . . . . . . . . . . . . . . . . . . . . . . 28

8 Monitoring and protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

8.1 Power good signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

8.2 Thermal protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

8.3 Overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

2/48 Doc ID 11674 Rev 8

PM6685 Contents

8.4 Undervoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

8.5 Design guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

8.6 Switching frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

8.7 Inductor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

8.8 Output capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

8.9 Input capacitors selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

8.10 Power MOSFETs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

8.11 Closing the integrator loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

9 Other parts design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

10 Design example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

10.1 Inductor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

10.2 Output capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

10.3 Power MOSFETs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

10.4 Current limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

10.5 Input capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

10.6 Synchronous rectifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

10.7 Integrator loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

10.8 Layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

11 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Doc ID 11674 Rev 8 3/48

Block diagram PM6685

L

5V

S

+-+

4V

V

2

V

3.3V

L

4.8V

U

V

T

V

L

V

+

-

2.6V

VCCV

1 Block diagram

Figure 1. Functional block diagram

IN

REF

PGOOD

LDO3

OUT3

SKIP

FSEL

BOOT3

HGATE3

PHASE3

CSENSE3

COMP3

CC

FREQUENCY

SELECTOR

LDO5

REFERENCE
GENERATOR

LEVEL

SHIFTER

REF

DO5 ENABLE

.55

-

3.3V

SMPS

CONTROLLER

LINEAR

REGULATOR

LINEAR

REGULATOR

DO3 ENABLE

CONTROLLER

5V

SMPS

+

-

VLO

LEVEL

SHIFTER

UVLO

DO5

5SW

OUT5

BOOT5

HGATE5

PHASE5

CSENSE5

COMP5

LDO5

LGATE3

PGOOD3

SHDN

LDO3 SEL

EN3

LDO3 MODE

SELECTOR

UVLO

TARTUP

CONTROLLER

ERMIC

FAULT

LDO3 ENABLE

LDO5 ENABLE

TERMIC

CONTROLLER

LGATE5

PGOOD5

EN5

4/48 Doc ID 11674 Rev 8

PM6685 Pin settings

2 Pin settings

2.1 Connections

Figure 2. Pin connection (top view)

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&203

)6(/

(1

6+'1

3*22'B/'2

/'2

287

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















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3+$6(

/*$7(

&6(16(

3*1'

3*22'

/*$7(

(1

3*22'

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/'2

96:



6*1'

Doc ID 11674 Rev 8 5/48

Pin settings PM6685

2.2 Functions

Table 2. Pin functions

Pin Name Description

Signal ground. Reference for internal logic circuitry. It must be connected to the signal ground

1SGND1

plan of the power supply. The signal ground plan and the power ground plan must be connected
together in one point near the PGND pin.

2 COMP3 DC voltage error compensation pin for the 3.3V switching section.

Frequency selection pin.

3 FSEL

It provides a selectable switching frequency, allowing, allowing three different values of switching
frequencies for the 5V/3.3V switching sections.

3.3V SMPS enable input.
– The 3.3V section is enabled applying a voltage greater than 2.4V to this pin.

4EN3

– The 3.3V section is disabled applying a voltage lower than 0.8V.
When the section is disabled the High Side gate driver goes low and Low Side gate driver goes
high. If both EN3 and EN5 pins are low and SHDN pin is high the device enters in standby mode.

Shutdown control input.
– The device switch off if the SHDN voltage is lower than 0.8V (Shutdown mode)

5 SHDN

– The device switch on if the SHDN voltage is greater than 1.7V.
The SHDN pin can be connected to the battery through a voltage divider to program an
undervoltage lockout. In shutdown mode, the gate drivers of the two switching sections are in
high impedance (high-Z).

6

PGOOD

LDO3

Power Good signal for the 3.3V linear regulator. This pin is an open drain output. It is shorted to
GND if LDO3_SEL pin is at its low level or if the output voltage on LDO3 pin is lower than 2.6V.

7 LDO3 3.3V Linear regulator output. LDO3 can provide 100mA peak current.

8OUT3

9BOOT3

Output voltage sense for the 3.3V switching section.This pin must be directly connected to the
output voltage of the switching section.

Bootstrap capacitor connection for the switching 3.3V section. It supplies the high-side gate
driver.

10 HGATE3 High-side gate driver output for the 3.3V section.

11 PHASE3 Switch node connection and return path for the high side driver for the 3.3V section.

12 CSENSE3

Current sense input for the 3.3V section. This pin must be connected through a resistor to the
drain of the synchronous rectifier (R

sensing) to set the current limit threshold.

DSON

13 LGATE3 Low-side gate driver output for the 3.3V section.

14 PGND Power ground. This pin must be connected to the power ground plan of the power supply.

15 LGATE5 Low-side gate driver output for the 5V section.

16 SGND2

Signal ground for analog circuitry. It must be connected to the signal ground plan of the power
supply.

Internal 5V regulator bypass connection.

17 V5SW

– If V5SW is connected to OUT5 (or to an external 5V supply) and V5SW is greater than 4.9V,

the LDO5 regulator shuts down and the LDO5 pin is directly connected to OUT5 through a 3W
(max) switch.

– If V5SW is connected to GND, the LDO5 linear regulator is always on.

18 LDO5

5V internal regulator output. It can provide up to 100mA peak current. LDO5 pin supplies
embedded low side gate drivers and an external load.

6/48 Doc ID 11674 Rev 8

PM6685 Pin settings

Table 2. Pin functions (continued)

Pin Name Description

19 VIN

20 CSENSE5

21 PHASE5 Switch node connection and return path for the high side driver for the 5V section.

22 HGATE5 High-side gate driver output for the 5V section.

23 BOOT5 Bootstrap capacitor connection for the 5V section. It supplies the high-side gate driver.

24 SKIP

25 EN5

26 PGOOD5

27 PGOOD3

28 LDO3SEL

29 OUT5

30 COMP5 DC voltage error compensation pin for the 5V switching section.

31 VCC

32 VREF

Device input supply voltage. A bypass filter (4W and 4.7mF) between the battery and this pin is
recommended.

Current sense input for the 5V section. This pin must be connected through a resistor to the
drain of the synchronous rectifier (R

Pulse skip mode control input.
– If the pin is connected to LDO5 the PWM mode is enabled.

– If the pin is connected to GND, the pulse skip mode is enabled.
– If the pin is connected to VREF the pulse skip mode is enabled but the switching frequency is

kept higher than 33kHz (No-audible pulse skip mode).

5V SMPS enable input.
– The 5V section is enabled applying a voltage greater than 2.4V to this pin.

– The 5V section is disabled applying a voltage lower than 0.8V.
When the section is disabled the High Side gate driver goes low and Low Side gate driver goes
high.

Power Good signal for the 5V section. This pin is an open drain output.
The pin is pulled low if the output is disabled or if it is out of approximately +/- 10% of its nominal

value.

Power Good signal for the 3.3V section. This pin is an open drain output.
The pin is pulled low if the output is disabled or if it is out of approximately +/- 10% of its nominal

value.

Control pin for the 3.3V internal linear regulator. This pin determines three operative modes for
the LDO3.

– If LDO3_SEL pin is connected to GND the LDO3 output is always disabled.
– If LDO3_SEL pin is connected to LDO5 the LDO3 internal regulator is always enabled.
– If LDO3_SEL pin is connected to VREF and OUT3 is greater than about 3V, the LDO3

regulator shuts down and the LDO3 pin is be directly connected to OUT3 through a 3W (max)
switch.

Output voltage sense for the 5V switching section.This pin must be directly connected to the
output voltage of the switching section.

Device Supply Voltage pin. It supplies the all the internal analog circuitry except the gate drivers
(see LDO5). Connect this pin to LDO5.

High accuracy output voltage reference (1.230V). It can deliver 50uA. Bypass to SGND with a
100nF capacitor.

sensing) to set the current limit threshold.

DSON

33 EXP PAD Exposed pad.

Doc ID 11674 Rev 8 7/48

Electrical data PM6685

3 Electrical data

3.1 Maximum rating

Table 3. Absolute maximum ratings

Parameter Value Unit

COMPx,FSEL,LDO3_SEL,VREF,SKIP to SGND1,SGND2 -0.3 to VCC + 0.3 V

ENx,SHDN,PGOOD_LDO3,OUTx,PGOODx,VCC to
SGND1,SGND2

LDO3 to SGND1,SGND2 -0.3 to LDO5 + 0.3 V

LGATEx to PGND -0.3

HGATEx and BOOTx, to PHASEx -0.3 to 6 V

PHASEx to PGND -0.6

CSENSEx, to PGND -0.6 to 42 V

CSENSEx to BOOTx_ -6 to 0.3 V

V5SW, LDO5 _to PGND -0.3 to 6 V

VIN to PGND -0.3 to 36 V

-0.3 to 6 V

(1)

to LDO5 + 0.3

(2)

to 36

V

V

PGND to SGND1,SGND2_ -0.3 to 0.3 V

Power Dissipation at Tamb = 25ºC 2 W

Maximum withstanding Voltage range test
condition: CDF-AEC-Q100-002- “Human Body
Model” acceptance criteria: “Normal
Performance”

1. LGATEx to PGND up to -1V for t < 40ns

2. PHASE to PGND up to -2.5V for t < 10ns

3.2 Thermal data

Table 4. Thermal data

Symbol Parameter Value Unit

R

T

thJA

STG

T

J

Thermal resistance junction to ambient 35 °C/W

Storage temperature range -40 to 150 °C

Junction operating temperature range -10 to 125 °C

VIN pin ±1000 V

Other pins ±2000

8/48 Doc ID 11674 Rev 8

PM6685 Electrical characteristics

4 Electrical characteristics

VIN = 12V, TA = 0°C to 85°C, unless otherwise specified

Table 5. Electrical characteristics

Symbol Parameter Test condition Min Typ Max Unit

Supply section

VIN

Input voltage range

Vout=Vref, LDO5 in regulation
FSEL to GND

5.5 28 V

Vcc IC supply voltage 4.5 5.5 V

V

V5SW

Turn-on voltage
threshold

Turn-off voltage
threshold

4.6 4.75 V

4.8 4.9 V

Hysteresis 20 50 mV

V

V5SW

Rdson

Maximum operating
range

LDO5 internal bootstrap
switch resistance

LDO3 internal bootstrap
switch resistance

5.5 V

V5SW > 4.9V 1.8 3 Ω

VOUT3 = 3.3V 1.8 3 Ω

OUT3, OUT5 discharge

Rdson

mode
on-resistance

16 25 Ω

OUT3, OUT5_
discharge mode

synchronous rectifier

0.2 0.35 0.5 V

turn-on level

Pin

Operating power
consumption

>5.1V,V

V

OUT5

V5SW to 5V
LDO5, LDO3 no load

OUT3

>3.34V

4mW

Ish VIN shutdown current SHDN connected to GND, 14 18 μA

Isb VIN standby current

ENx to GND, V5SW to GND,
LDO3_SEL to 5V

270 380 μA

Shutdown section

Device on threshold 1.2 1.5 1.7 V

V

SHDN

Device off threshold 0.8 0.85 0.9 V

Soft start section

Soft start ramp time 2 3.5 ms

Current limit and zero crossing comparator

Doc ID 11674 Rev 8 9/48

Electrical characteristics PM6685

Table 5. Electrical characteristics (continued)

Symbol Parameter Test condition Min Typ Max Unit

I

CSENSE

Input bias current limit 90 100 110 μA

Comparator offset V

Zero crossing
comparator offset

Fixed negative current
limit

threshold

On time pulse width

Ton ON-time duration

OFF time

T

OFFMIN

Minimum off time 400 500 ns

Volt age ref ere nc e

Voltage accuracy 4.2V<V

V

REF

Load regulation -100μA< I

Undervoltage lockout
fault threshold

CSENSE-VPGND

V

PGND-VPHASE

V

PGND-VPHASE

-6 6 mV

-1 11 mV

-120 mV

OUT5=5V 1685 1985 2285

FSEL to GND

OUT3=3.3V 780 920 1060

OUT5=5V 1115 1315 1515

FSEL to VREF

OUT3=3.3V 585 690 795

OUT5=5V 830 980 1130

FSEL to LDO5

OUT3=3.3V 470 555 640

< 5.5V 1.217 1.230 1.243 V

LDO5

< 100μA -4 4 mV

REF

Falling edge of REF 0.95 V

ns

Integrator

Normal mode 250

Over voltage clamp

COMP

Under voltage clamp -150

Line regulation

Both SMPS, 6V<Vin<28V

LDO5 linear regulator

V

LDO5

I

LDO5

UVLO

LDO5 linear output
voltage

LDO5 line regulation

LDO5 current limit

Under voltage lockout of
LDO5

6V<VIN<28V, 0<I

6V< VIN < 28V, I
LDO3_SEL tied to GND

> UVLO, I

V

LDO5

V

>5.1V, V

OUT5

<50mA 4.9 5.0 5.1 V

LDO5

=50mA

LDO5

=0A

LDO3

>3.34V

OUT3

10/48 Doc ID 11674 Rev 8

(1)

mVPulse skip mode 60

0.004 %/V

,

0.004 %/V

270 350 400 mA

3.94 4 4.13 V

PM6685 Electrical characteristics

Table 5. Electrical characteristics (continued)

Symbol Parameter Test condition Min Typ Max Unit

LDO3 linear regulator

V

LDO3

I

LDO3

LDO3 linear output
voltage

LDO3 current limit V

0.5mA<I

LDO5

<50mA 3.23 3.3 3.37 V

LDO3

> UVLO 130 165 200 mA

High and low gate drivers

HGATE Driver On­resistance

LGATE Driver On­resistance

HGATEx high state (pull-up) 2.0 3 Ω

HGATEx low state (pull-down) 1.6 2.7 Ω

LGATEx high state (pull-up) 1.4 2.1 Ω

LGATEx low state (pull-down) 0.8 1.2 Ω

PGOOD pins UVP/OVP protections

OVP Over voltage threshold

Both SMPS sections with respect to
VREF.

113 116 120 %

UVP Under voltage threshold 66 70 72 %

Upper threshold
(VFB-VREF)

107 110 113 %

PGOOD3,5

I

PGOOD3,5

V

PGOOD3,5

PGOOD

LDO3

Lower threshold
(VFB-VREF)

PGOOD leakage
current

V

PGOOD3,5

forced to 5.5V 1 uA

Output low voltage ISink = 4mA 150 250 mV

Rising voltage threshold 77.7 81.1 %

90 92 94 %

Falling voltage threshold 72.1 76.6 %

Hysteresis 20 30 mV

I

PGOOD_LDO3

V

PGOOD_LDO3

PGOOD leakage
current

Output low voltage ISink = 4mA 150 250 mV

Thermal shutdown

T

SDN

Shutdown temperature 150 °C

Power management pins

SMPS disabled
threshold

EN3,5

SMPS enabled
threshold

V

PGOOD LDO3

(2)

(2)

forced to 5.5V 1 uA

0.8

Doc ID 11674 Rev 8 11/48

V

2.4

Electrical characteristics PM6685

Table 5. Electrical characteristics (continued)

Symbol Parameter Test condition Min Typ Max Unit

FSEL

LDO3

SEL

Frequency selection
range

3.3V linear regulator
selection pin

Pulse skip mode

SKIP

Frequency clamp mode

Input leakage current

1. by demonstration board test

2. by design

Low level

Middle level

High level

Always-off level

Bootstrap level

Always-on level

(2)

(2)

(2)

V

EN3,4

V

SKIP

V

SHDN

V

FSEL

V

LDO3_SEL

(2)

(2)

(2)

(2)

(2)

(2)

1.0 V

V

-0.8

LDO5

1.0 V

V

-0.8

LDO5

1.0 V

V

-0.8

LDO5

= 0 to 5V 1

= 0 to 5V 1

= 0 to 5V 0.1

= 0 to 5V 1

= 0 to 5V 1

0.5

LDO5

0.5

LDO5

0.5

LDO5

-1.5

-1.5

-1.5

V

VPWM mode

μA

12/48 Doc ID 11674 Rev 8

PM6685 Typical operating characteristics

5 Typical operating characteristics

FSEL = GND (200/300 kHz), SKIP = GND (skip mode), LDO3_SEL = VREF,
V5SW = OUT5, input voltage VIN = 12 V, SHDN, EN3 and EN5 high,
no load unless specified.

Figure 3. 5 V output efficiency vs

load current

Figure 4. 3.3 V output efficiency vs

load current

Figure 5. PWM no load input battery vs input

voltage

Figure 6. Skip no load battery current vs input

voltage

Doc ID 11674 Rev 8 13/48

Typical operating characteristics PM6685

Figure 7. Standby mode input battery current

vs input voltage

Figure 9. 5V switching frequency vs load

current

Figure 8. Shutdown mode input device

current vs input voltage

Figure 10. 3.3V switching frequency vs load

current

Figure 11. LDO5 vs output voltage Figure 12. LDO3 vs output voltage

14/48 Doc ID 11674 Rev 8

PM6685 Typical operating characteristics

Figure 13. 5V voltage regulation

vs load current

Figure 15. Voltage reference vs

load current

Figure 14. 3.3 V voltage regulation

vs load current

Figure 16. OUT5, LDO3 and LDO5

Power-Up

Figure 17. 5 V PWM load transient Figure 18. 3.3 V PWM load transient

Doc ID 11674 Rev 8 15/48