with auxilary voltages for notebook system power
Features
■ 6 V to 28 V input voltage range
■ Fixed 5 V - 3.3 V output voltages
■ 5 V and 3.3 V voltage always available to
deliver 100 mA of peak current
PM6685
Dual step-down main supply controller
■ 1.230 V ±1% reference voltage available
■ Lossless current sensing using low side
■ MOSFETs' R
■ Negative current limit
■ Soft-start internally fixed at 2 ms
■ Soft output discharge
■ Latched OVP and UVP
■ Selectable pulse skipping at light loads
■ Selectable minimum frequency (33 kHz) in
DS(on)
pulse skip mode
■ 4 mW maximum quiescent power
■ Independent power good signals
■ Output voltage ripple compensation
Applications
■ Notebook computers
■ Tablet PC or slates
■ Mobile system power supply
■ 3 and -4 Cells Li+ battery-powered devices
VFQFPN-32 (5mm x 5mm)
Description
PM6685 is a dual step-down controller specifically
designed to provide extremely high efficiency
conversion with loss-less current sensing
technique. The constant on-time architecture
assures fast load transient response and the
embedded voltage feed-forward provides nearly
constant switching frequency operation.
An embedded integrator control loop
compensates the DC voltage error due to the
output ripple. The pulse skipping technique
increases efficiency for very light loads. Moreover,
a minimum switching frequency of 33kHz is
selectable in order to avoid audio noise issues.
The PM6685 provides a selectable switching
frequency, allowing either 200 kHz/300 kHz, 300
kHz/400 kHz, or 400 kHz/500 kHz operation of
the 5 V/3.3 V switching sections.
Table 1. Device summary
Order code Package Packaging
PM6685
VFQFPN-32 (5 mm x 5 mm)
PM6685TR Tape and reel
March 2011 Doc ID 11674 Rev 8 1/48
Tube
www.st.com
48
Contents PM6685
Contents
1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.1 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5 Typical operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
6 Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7 Device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.1 Constant on time PWM control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.2 Constant on time architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7.3 Output ripple compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7.4 Pulse skip mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7.5 No-audible skip mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.6 Current limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.7 Soft start and soft end . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.8 Gate drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7.9 Reference voltage and bandgap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.10 Internal linear regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.11 Power up sequencing and operative modes . . . . . . . . . . . . . . . . . . . . . . . 28
8 Monitoring and protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
8.1 Power good signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
8.2 Thermal protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
8.3 Overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2/48 Doc ID 11674 Rev 8
PM6685 Contents
8.4 Undervoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
8.5 Design guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
8.6 Switching frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
8.7 Inductor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
8.8 Output capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
8.9 Input capacitors selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
8.10 Power MOSFETs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
8.11 Closing the integrator loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
9 Other parts design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
10 Design example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
10.1 Inductor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
10.2 Output capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
10.3 Power MOSFETs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
10.4 Current limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
10.5 Input capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
10.6 Synchronous rectifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
10.7 Integrator loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
10.8 Layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
11 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Doc ID 11674 Rev 8 3/48
Block diagram PM6685
L
5V
S
+-+
4V
V
2
V
3.3V
L
4.8V
U
V
T
V
L
V
+
-
2.6V
VCCV
1 Block diagram
Figure 1. Functional block diagram
IN
REF
PGOOD
LDO3
OUT3
SKIP
FSEL
BOOT3
HGATE3
PHASE3
CSENSE3
COMP3
CC
FREQUENCY
SELECTOR
LDO5
REFERENCE
GENERATOR
LEVEL
SHIFTER
REF
DO5 ENABLE
.55
-
3.3V
SMPS
CONTROLLER
LINEAR
REGULATOR
LINEAR
REGULATOR
DO3 ENABLE
CONTROLLER
5V
SMPS
+
-
VLO
LEVEL
SHIFTER
UVLO
DO5
5SW
OUT5
BOOT5
HGATE5
PHASE5
CSENSE5
COMP5
LDO5
LGATE3
PGOOD3
SHDN
LDO3 SEL
EN3
LDO3 MODE
SELECTOR
UVLO
TARTUP
CONTROLLER
ERMIC
FAULT
LDO3 ENABLE
LDO5 ENABLE
TERMIC
CONTROLLER
LGATE5
PGOOD5
EN5
4/48 Doc ID 11674 Rev 8
PM6685 Pin settings
2 Pin settings
2.1 Connections
Figure 2. Pin connection (top view)
6*1'
&203
)6(/
(1
6+'1
3*22'B/'2
/'2
287
95()
9&&
287
&203
/'2B6(/
+*$7(
%227
3+$6(
/*$7(
&6(16(
3*1'
3*22'
/*$7(
(1
3*22'
6.,3
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+*$7(
3+$6(
&6(16(
9,1
/'2
96:
6*1'
Doc ID 11674 Rev 8 5/48
Pin settings PM6685
2.2 Functions
Table 2. Pin functions
Pin Name Description
Signal ground. Reference for internal logic circuitry. It must be connected to the signal ground
1SGND1
plan of the power supply. The signal ground plan and the power ground plan must be connected
together in one point near the PGND pin.
2 COMP3 DC voltage error compensation pin for the 3.3V switching section.
Frequency selection pin.
3 FSEL
It provides a selectable switching frequency, allowing, allowing three different values of switching
frequencies for the 5V/3.3V switching sections.
3.3V SMPS enable input.
– The 3.3V section is enabled applying a voltage greater than 2.4V to this pin.
4EN3
– The 3.3V section is disabled applying a voltage lower than 0.8V.
When the section is disabled the High Side gate driver goes low and Low Side gate driver goes
high. If both EN3 and EN5 pins are low and SHDN pin is high the device enters in standby mode.
Shutdown control input.
– The device switch off if the SHDN voltage is lower than 0.8V (Shutdown mode)
5 SHDN
– The device switch on if the SHDN voltage is greater than 1.7V.
The SHDN pin can be connected to the battery through a voltage divider to program an
undervoltage lockout. In shutdown mode, the gate drivers of the two switching sections are in
high impedance (high-Z).
6
PGOOD
LDO3
Power Good signal for the 3.3V linear regulator. This pin is an open drain output. It is shorted to
GND if LDO3_SEL pin is at its low level or if the output voltage on LDO3 pin is lower than 2.6V.
7 LDO3 3.3V Linear regulator output. LDO3 can provide 100mA peak current.
8OUT3
9BOOT3
Output voltage sense for the 3.3V switching section.This pin must be directly connected to the
output voltage of the switching section.
Bootstrap capacitor connection for the switching 3.3V section. It supplies the high-side gate
driver.
10 HGATE3 High-side gate driver output for the 3.3V section.
11 PHASE3 Switch node connection and return path for the high side driver for the 3.3V section.
12 CSENSE3
Current sense input for the 3.3V section. This pin must be connected through a resistor to the
drain of the synchronous rectifier (R
sensing) to set the current limit threshold.
DSON
13 LGATE3 Low-side gate driver output for the 3.3V section.
14 PGND Power ground. This pin must be connected to the power ground plan of the power supply.
15 LGATE5 Low-side gate driver output for the 5V section.
16 SGND2
Signal ground for analog circuitry. It must be connected to the signal ground plan of the power
supply.
Internal 5V regulator bypass connection.
17 V5SW
– If V5SW is connected to OUT5 (or to an external 5V supply) and V5SW is greater than 4.9V,
the LDO5 regulator shuts down and the LDO5 pin is directly connected to OUT5 through a 3W
(max) switch.
– If V5SW is connected to GND, the LDO5 linear regulator is always on.
18 LDO5
5V internal regulator output. It can provide up to 100mA peak current. LDO5 pin supplies
embedded low side gate drivers and an external load.
6/48 Doc ID 11674 Rev 8
PM6685 Pin settings
Table 2. Pin functions (continued)
Pin Name Description
19 VIN
20 CSENSE5
21 PHASE5 Switch node connection and return path for the high side driver for the 5V section.
22 HGATE5 High-side gate driver output for the 5V section.
23 BOOT5 Bootstrap capacitor connection for the 5V section. It supplies the high-side gate driver.
24 SKIP
25 EN5
26 PGOOD5
27 PGOOD3
28 LDO3SEL
29 OUT5
30 COMP5 DC voltage error compensation pin for the 5V switching section.
31 VCC
32 VREF
Device input supply voltage. A bypass filter (4W and 4.7mF) between the battery and this pin is
recommended.
Current sense input for the 5V section. This pin must be connected through a resistor to the
drain of the synchronous rectifier (R
Pulse skip mode control input.
– If the pin is connected to LDO5 the PWM mode is enabled.
– If the pin is connected to GND, the pulse skip mode is enabled.
– If the pin is connected to VREF the pulse skip mode is enabled but the switching frequency is
kept higher than 33kHz (No-audible pulse skip mode).
5V SMPS enable input.
– The 5V section is enabled applying a voltage greater than 2.4V to this pin.
– The 5V section is disabled applying a voltage lower than 0.8V.
When the section is disabled the High Side gate driver goes low and Low Side gate driver goes
high.
Power Good signal for the 5V section. This pin is an open drain output.
The pin is pulled low if the output is disabled or if it is out of approximately +/- 10% of its nominal
value.
Power Good signal for the 3.3V section. This pin is an open drain output.
The pin is pulled low if the output is disabled or if it is out of approximately +/- 10% of its nominal
value.
Control pin for the 3.3V internal linear regulator. This pin determines three operative modes for
the LDO3.
– If LDO3_SEL pin is connected to GND the LDO3 output is always disabled.
– If LDO3_SEL pin is connected to LDO5 the LDO3 internal regulator is always enabled.
– If LDO3_SEL pin is connected to VREF and OUT3 is greater than about 3V, the LDO3
regulator shuts down and the LDO3 pin is be directly connected to OUT3 through a 3W (max)
switch.
Output voltage sense for the 5V switching section.This pin must be directly connected to the
output voltage of the switching section.
Device Supply Voltage pin. It supplies the all the internal analog circuitry except the gate drivers
(see LDO5). Connect this pin to LDO5.
High accuracy output voltage reference (1.230V). It can deliver 50uA. Bypass to SGND with a
100nF capacitor.
sensing) to set the current limit threshold.
DSON
33 EXP PAD Exposed pad.
Doc ID 11674 Rev 8 7/48
Electrical data PM6685
3 Electrical data
3.1 Maximum rating
Table 3. Absolute maximum ratings
Parameter Value Unit
COMPx,FSEL,LDO3_SEL,VREF,SKIP to SGND1,SGND2 -0.3 to VCC + 0.3 V
ENx,SHDN,PGOOD_LDO3,OUTx,PGOODx,VCC to
SGND1,SGND2
LDO3 to SGND1,SGND2 -0.3 to LDO5 + 0.3 V
LGATEx to PGND -0.3
HGATEx and BOOTx, to PHASEx -0.3 to 6 V
PHASEx to PGND -0.6
CSENSEx, to PGND -0.6 to 42 V
CSENSEx to BOOTx_ -6 to 0.3 V
V5SW, LDO5 _to PGND -0.3 to 6 V
VIN to PGND -0.3 to 36 V
-0.3 to 6 V
(1)
to LDO5 + 0.3
(2)
to 36
V
V
PGND to SGND1,SGND2_ -0.3 to 0.3 V
Power Dissipation at Tamb = 25ºC 2 W
Maximum withstanding Voltage range test
condition: CDF-AEC-Q100-002- “Human Body
Model” acceptance criteria: “Normal
Performance”
1. LGATEx to PGND up to -1V for t < 40ns
2. PHASE to PGND up to -2.5V for t < 10ns
3.2 Thermal data
Table 4. Thermal data
Symbol Parameter Value Unit
R
T
thJA
STG
T
J
Thermal resistance junction to ambient 35 °C/W
Storage temperature range -40 to 150 °C
Junction operating temperature range -10 to 125 °C
VIN pin ±1000 V
Other pins ±2000
8/48 Doc ID 11674 Rev 8
PM6685 Electrical characteristics
4 Electrical characteristics
VIN = 12V, TA = 0°C to 85°C, unless otherwise specified
Table 5. Electrical characteristics
Symbol Parameter Test condition Min Typ Max Unit
Supply section
VIN
Input voltage range
Vout=Vref, LDO5 in regulation
FSEL to GND
5.5 28 V
Vcc IC supply voltage 4.5 5.5 V
V
V5SW
Turn-on voltage
threshold
Turn-off voltage
threshold
4.6 4.75 V
4.8 4.9 V
Hysteresis 20 50 mV
V
V5SW
Rdson
Maximum operating
range
LDO5 internal bootstrap
switch resistance
LDO3 internal bootstrap
switch resistance
5.5 V
V5SW > 4.9V 1.8 3 Ω
VOUT3 = 3.3V 1.8 3 Ω
OUT3, OUT5 discharge
Rdson
mode
on-resistance
16 25 Ω
OUT3, OUT5_
discharge mode
synchronous rectifier
0.2 0.35 0.5 V
turn-on level
Pin
Operating power
consumption
>5.1V,V
V
OUT5
V5SW to 5V
LDO5, LDO3 no load
OUT3
>3.34V
4mW
Ish VIN shutdown current SHDN connected to GND, 14 18 μA
Isb VIN standby current
ENx to GND, V5SW to GND,
LDO3_SEL to 5V
270 380 μA
Shutdown section
Device on threshold 1.2 1.5 1.7 V
V
SHDN
Device off threshold 0.8 0.85 0.9 V
Soft start section
Soft start ramp time 2 3.5 ms
Current limit and zero crossing comparator
Doc ID 11674 Rev 8 9/48
Electrical characteristics PM6685
Table 5. Electrical characteristics (continued)
Symbol Parameter Test condition Min Typ Max Unit
I
CSENSE
Input bias current limit 90 100 110 μA
Comparator offset V
Zero crossing
comparator offset
Fixed negative current
limit
threshold
On time pulse width
Ton ON-time duration
OFF time
T
OFFMIN
Minimum off time 400 500 ns
Volt age ref ere nc e
Voltage accuracy 4.2V<V
V
REF
Load regulation -100μA< I
Undervoltage lockout
fault threshold
CSENSE-VPGND
V
PGND-VPHASE
V
PGND-VPHASE
-6 6 mV
-1 11 mV
-120 mV
OUT5=5V 1685 1985 2285
FSEL to GND
OUT3=3.3V 780 920 1060
OUT5=5V 1115 1315 1515
FSEL to VREF
OUT3=3.3V 585 690 795
OUT5=5V 830 980 1130
FSEL to LDO5
OUT3=3.3V 470 555 640
< 5.5V 1.217 1.230 1.243 V
LDO5
< 100μA -4 4 mV
REF
Falling edge of REF 0.95 V
ns
Integrator
Normal mode 250
Over voltage clamp
COMP
Under voltage clamp -150
Line regulation
Both SMPS, 6V<Vin<28V
LDO5 linear regulator
V
LDO5
I
LDO5
UVLO
LDO5 linear output
voltage
LDO5 line regulation
LDO5 current limit
Under voltage lockout of
LDO5
6V<VIN<28V, 0<I
6V< VIN < 28V, I
LDO3_SEL tied to GND
> UVLO, I
V
LDO5
V
>5.1V, V
OUT5
<50mA 4.9 5.0 5.1 V
LDO5
=50mA
LDO5
=0A
LDO3
>3.34V
OUT3
10/48 Doc ID 11674 Rev 8
(1)
mVPulse skip mode 60
0.004 %/V
,
0.004 %/V
270 350 400 mA
3.94 4 4.13 V
PM6685 Electrical characteristics
Table 5. Electrical characteristics (continued)
Symbol Parameter Test condition Min Typ Max Unit
LDO3 linear regulator
V
LDO3
I
LDO3
LDO3 linear output
voltage
LDO3 current limit V
0.5mA<I
LDO5
<50mA 3.23 3.3 3.37 V
LDO3
> UVLO 130 165 200 mA
High and low gate drivers
HGATE Driver Onresistance
LGATE Driver Onresistance
HGATEx high state (pull-up) 2.0 3 Ω
HGATEx low state (pull-down) 1.6 2.7 Ω
LGATEx high state (pull-up) 1.4 2.1 Ω
LGATEx low state (pull-down) 0.8 1.2 Ω
PGOOD pins UVP/OVP protections
OVP Over voltage threshold
Both SMPS sections with respect to
VREF.
113 116 120 %
UVP Under voltage threshold 66 70 72 %
Upper threshold
(VFB-VREF)
107 110 113 %
PGOOD3,5
I
PGOOD3,5
V
PGOOD3,5
PGOOD
LDO3
Lower threshold
(VFB-VREF)
PGOOD leakage
current
V
PGOOD3,5
forced to 5.5V 1 uA
Output low voltage ISink = 4mA 150 250 mV
Rising voltage threshold 77.7 81.1 %
90 92 94 %
Falling voltage threshold 72.1 76.6 %
Hysteresis 20 30 mV
I
PGOOD_LDO3
V
PGOOD_LDO3
PGOOD leakage
current
Output low voltage ISink = 4mA 150 250 mV
Thermal shutdown
T
SDN
Shutdown temperature 150 °C
Power management pins
SMPS disabled
threshold
EN3,5
SMPS enabled
threshold
V
PGOOD LDO3
(2)
(2)
forced to 5.5V 1 uA
0.8
Doc ID 11674 Rev 8 11/48
V
2.4
Electrical characteristics PM6685
Table 5. Electrical characteristics (continued)
Symbol Parameter Test condition Min Typ Max Unit
FSEL
LDO3
SEL
Frequency selection
range
3.3V linear regulator
selection pin
Pulse skip mode
SKIP
Frequency clamp mode
Input leakage current
1. by demonstration board test
2. by design
Low level
Middle level
High level
Always-off level
Bootstrap level
Always-on level
(2)
(2)
(2)
V
EN3,4
V
SKIP
V
SHDN
V
FSEL
V
LDO3_SEL
(2)
(2)
(2)
(2)
(2)
(2)
1.0 V
V
-0.8
LDO5
1.0 V
V
-0.8
LDO5
1.0 V
V
-0.8
LDO5
= 0 to 5V 1
= 0 to 5V 1
= 0 to 5V 0.1
= 0 to 5V 1
= 0 to 5V 1
0.5
LDO5
0.5
LDO5
0.5
LDO5
-1.5
-1.5
-1.5
V
VPWM mode
μA
12/48 Doc ID 11674 Rev 8
PM6685 Typical operating characteristics
5 Typical operating characteristics
FSEL = GND (200/300 kHz), SKIP = GND (skip mode), LDO3_SEL = VREF,
V5SW = OUT5, input voltage VIN = 12 V, SHDN, EN3 and EN5 high,
no load unless specified.
Figure 3. 5 V output efficiency vs
load current
Figure 4. 3.3 V output efficiency vs
load current
Figure 5. PWM no load input battery vs input
voltage
Figure 6. Skip no load battery current vs input
voltage
Doc ID 11674 Rev 8 13/48
Typical operating characteristics PM6685
Figure 7. Standby mode input battery current
vs input voltage
Figure 9. 5V switching frequency vs load
current
Figure 8. Shutdown mode input device
current vs input voltage
Figure 10. 3.3V switching frequency vs load
current
Figure 11. LDO5 vs output voltage Figure 12. LDO3 vs output voltage
14/48 Doc ID 11674 Rev 8
PM6685 Typical operating characteristics
Figure 13. 5V voltage regulation
vs load current
Figure 15. Voltage reference vs
load current
Figure 14. 3.3 V voltage regulation
vs load current
Figure 16. OUT5, LDO3 and LDO5
Power-Up
Figure 17. 5 V PWM load transient Figure 18. 3.3 V PWM load transient
Doc ID 11674 Rev 8 15/48
Typical operating characteristics PM6685
Figure 19. 5 V soft start (0.75 Ω load) Figure 20. 3.3 V soft start (0.55 Ω load)
Figure 21. 5 V soft end (no load) Figure 22. 3.3 V soft end (no load)
Figure 23. 5 V soft end (1 Ω load) Figure 24. 3.3 V soft end (1 Ω load)
16/48 Doc ID 11674 Rev 8
PM6685 Typical operating characteristics
Figure 25. 5 V no audible skip mode Figure 26. 3.3 V no audible skip mode
Doc ID 11674 Rev 8 17/48
Application schematic PM6685
6 Application schematic
Figure 27. Simplified application schematic
5V-
SGND
5V+
1
1
VIN
+
PGND
OUT5
PM6685
SGND
SGND
PGND
SGND
23
22
20
17
29
CSENSE5
V5SW
CSENSE3
PGND
12
14
1
PGND
21
15
BOOT5
HGATE5
PHASE5
LGATE5
VCC
LDO5
VIN
HGATE3
PHASE3
LGATE3
13
BOOT3
SGND
9
10
11
V+
BOOT1
BOOT2
SGND
+
SGND
31
18
19
V+
V+
PGOOD3
PGOOD5
SHDN
4
EN3
EN5
32
VREF
24
SGND
SKIP
3
FSEL
LDO3
SGND
SGND
+
V+
SGND
SGND2
COMP3
302516
COMP5
OUT3
8
2
26
27
5
PGOOD5
PGOOD3
PGOOD LD O3
LDO3SEL
6
28
7
V+
PGOODLDO3
V+
SGND
18/48 Doc ID 11674 Rev 8
PGND
PGND
+
1
1
VIN
PM6685 Device description
7 Device description
The PM6685 is a dual step-down controller dedicated to provide logic voltages for notebook
computers.
It is based on a Constant On Time control architecture. This type of control offers a very fast
load transient response with a minimum external component count. A typical application
circuit is shown in Figure 27 on page 18. The PM6685 regulates two fixed output voltages: 5
V and 3.3 V. The switching frequency of the two sections can be adjusted to approximately
200/300 kHz, 300/400 kHz or 400/500 kHz respectively. In order to maximize the efficiency
at light load condition, a pulse skipping mode can be selected. The PM6685 includes also
two linear regulators (LDO5 and LDO3) that allow the shutdown of the respective switching
sections in low consumption status. On the other hand, to maximize the efficiency in higher
consumption status, the linear regulators can be turned off and their outputs can be
supplied directly from the switching outputs. The PM6685 provides protection versus
overvoltage, undervoltage and overtemperature as well as power good signals for
monitoring purposes. An external 1.230 V reference is available.
7.1 Constant on time PWM control
If the SKIP pin is tied to 5 V, the device works in PWM mode. Each power section has an
independent on time control.The PM6685 implements a pseudo-fixed switching frequency,
constant on time (COT) controller as core of the switched mode section. Each power section
has an independent COT control.
The COT controller is based on a relatively simple algorithm and uses the ripple voltage due
to the output capacitor’s ESR to trigger the fixed on-time one-shot generator. In this way, the
output capacitor’s ESR acts as a current sense resistor providing the appropriate ramp
signal to the PWM comparator. On-time one-shot duration is directly proportional to the
output voltage VOUT, sensed at the OUT5/OUT3 pins, and inversely proportional to the
input voltage VIN, sensed at the VIN pin, as follows:
Equation 1
V
OUT
KT ×=
ON
This leads to a nearly constant switching frequency, regardless of input and output voltages.
When the output voltage goes lower than the regulated voltage Vreg, the on-time one shot
generator directly drives the high side MOSFET for a fixed on time allowing the inductor
current to increase; after the on time, an off time phase, in which the low side MOSFET is
turned on, follows. Figure 28 on page 20 shows the inductor current and the output voltage
waveforms in PWM mode.
V
IN
Doc ID 11674 Rev 8 19/48
Device description PM6685
Figure 28. Constant on time PWM control
The duty cycle D of the buck converter in steady state is:
Equation 2
V
OUT
D =
V
IN
The PWM control works at a nearly fixed frequency f
SW
:
Equation 3
V
OUT
D
f =
sw
T
ON
V
==
IN
V
ON
OUT
×
V
K
1
K
ON
IN
As mentioned the steady state switching frequency is theoretically independent from battery
voltage and from output voltage. Actually the frequency depends on parasitic voltage drops
that are present during the charging path (high side switch resistance, inductor resistance
(DCR)) and discharging path (low side switch resistance, DCR). As a result the switching
frequency increases as a function of the load current. Standard switching frequency values
can be selected for both sections by pin FSEL as shown in the following table:
Table 6. FSEL pin selection
SMPS 5V SMPS 3.3V
FSEL
Frequency K
ON
SGND 212kHz 4,7µs 297,6kHz 3.36µs
VREF 323kHz 3µs 400kHz 2.5µs
LDO5 432kHz 2.31µs 500kHz 2.0µs
Frequency K
ON
The values in the table are measured with Vin =12 V, operation mode = PWM and I
The other output are unloaded.
20/48 Doc ID 11674 Rev 8
load
= 2 A.
PM6685 Device description
7.2 Constant on time architecture
Figure 29 on page 21 shows the simplified block diagram of a constant on time controller. A
minimum off-time constrain (380 ns typ) is introduced to allow inductor valley current
sensing on the synchronous switch. A minimum on-time(150 ns typ) is also introduced to
assure the start-up switching sequence.
PM6685 has a one-shot generator for each power section that turns on the high side
MOSFET when the following conditions are satisfied simultaneously: the PWM comparator
is high, the synchronous rectifier current is below the current limit threshold, and the
minimum off-time has timed out. Once the on-time has timed out, the high side switch is
turned off, while the synchronous switch is turned on according to the anti-cross conduction
circuitry management. When the negative input voltage at the PWM comparator, which is a
scaled-down replica of the output voltage ripple (see the R
reaches the valley limit (determined by internal reference V
fb1/Rfb2
r
is turned off according to the anti-cross conduction logic once again, and a new cycle
begins.
Figure 29. Constant ON-time block diagram
4OFF
MIN
4OFF
MIN
4OFF
MIN
4OFF
MIN
divider in Figure 29),
=0.9 V), the low-side MOSFET
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6R
6R
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2&B
2&B
2&B
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6
:ERO
:ERO
:ERO
:ERO
4ON
4ON
4ON
4ON
#OMP
#OMP
#OMP
#OMP
7.3 Output ripple compensation
In a classic constant on time control, the system regulates the valley value of the output
voltage and not the average value, as shown in Figure 28 on page 20. In this condition, the
output voltage ripple is source of a DC static error.
3
3
2
2
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To compensate this error, an integrator network can be introduced in the control loop, by
connecting the output voltage to the COMP5/COMP3(for the 5 V and 3.3 V sections
respectively) pin through a capacitor C
Doc ID 11674 Rev 8 21/48
as in Figure 30 on page 22.
INT
Device description PM6685
Figure 30. Circuitry for output ripple compensation
COM P PIN
COM P PIN
VOLTAGE
VOLTAGE
? V
Vr
Vr
OU TPU T V OLT AG E
OU TPU T V OLT AG E
? V
I=gm(V1 -Vr)
t
t
CFILTCFILT
CFILTCFILT
?V
?V
t
t
LL
LL
D
D
D
D
CINT
CINT
CINT
CINT
RINT
RINT
RINT
RINT
COMP
COMP
COMP
COMP
ROUTROUT
ROUTROUT
COUTCOUT
COUTCOUT
OUTOU T
OUTOU T
VCINTVC I NT
VCINTVC I NT
I=gm(V1 -Vr)
VrVr
VrVr
RFb2RFb2
RFb2RFb2
-
--
gmgm
gmgm
VrVr
VrVr
+
+
PWMPWM
PWMPWM
-
-
Comp aratorComparator
Comp aratorComparator
+
+
RFb1
RFb1
RF b1
RF b1
V1V1
V1V1
The integrator amplifier generates a current, proportional to the DC errors, which decreases
the output voltage in order to compensate the total static error, including the voltage drop on
PCB traces. In addition, C
voltage on COMP5/COMP3 pin is the sum of the reference voltage V
(see Figure 30). In fact when the voltage on the COMP pin reaches V
and the output increases.
For example, we consider V
C
INT
>>C
FILT
, the C
DC voltage drop V
INT
an AC path for the output voltage ripple. Then the COMP pin ripple is a replica of the output
ripple, with a DC value of Vr+25 mV =925 mV.
For more details about the output ripple compensation network, see the paragraph “Closing
the integrator loop” in the Design guidelines.
7.4 Pulse skip mode
If the SKIP pin is tied to ground, the device works in skip mode.
At light loads a zero-crossing comparator truncates the low-side switch on-time when the
inductor current becomes negative. In this condition the section works in discontinuous
conduction mode. The threshold between continuous and discontinuous conduction mode
is:
Equation 4
provides an AC path for the output ripple. In steady state, the
INT
=5 V with an output ripple of ΔV=50m V. Considering
OUT
is about 5 V-Vr+25 mV=4.125 V. C
CINT
and the output ripple
r
, a fixed Ton begins
r
ensures
INT
)SKIP(ILOAD ×
=
For higher loads the inductor current doesn’t cross the zero and the device works in the
same way as in PWM mode and the frequency is fixed to the nominal value.
22/48 Doc ID 11674 Rev 8
VV
−
OU TIN
T
L2
×
ON
PM6685 Device description
Figure 31. PWM and pulse skip mode inductor current
HGRPSLNVHVOX3HGRP0:3
,QGXFWRUFXUUHQW
/RZVLGHRQ
7RQ 7R I I
7.5 No-audible skip mode
If SKIP pin is tied to V
kHz is enabled. At light load condition, If there is not a new switching cycle within a 30 µs
(typ.) period, a no-audible skip mode cycle begins.
Figure 32. Frequency clamp skip mode
, a no-audible skip mode with a minimum switching frequency of 33
REF
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7RQ 7RQ
7RQ
7RI I
/RZVLGHRII
7LPH
The low side switch is turned on until the output voltage crosses about Vreg+1%. Then the
high side MOSFET is turned on for a fixed on time period. Afterwards the low side switch is
enabled until the inductor current reaches the zero-crossing threshold. This keeps the
switching frequency higher than 33 kHz. As a consequence of the control, the regulated
voltage can be slightly higher than Vreg (up to 1%).
If, due to the load, the frequency is higher than 33 kHz, the device works like in skip mode.
No-audible skip mode reduces audio frequency noise that may occur in pulse skip mode at
very light loads, keeping the efficiency higher than in PWM mode.
7.6 Current limit
The current-limit circuit employs a “valley” current-sensing algorithm. During the conduction
time of the low side MOSFET the current flowing through it is sensed. The current-sensing
element is the low side MOSFET on-resistance(Figure 33)
Doc ID 11674 Rev 8 23/48
Device description PM6685
Figure 33. R
sensing technique
DSON
+6
+*$7(
3+$6(
5FVHQVH
&6(16(
/*$7(
/6
5'6
RQ
An internal 100 μA ΔI
a voltage drop on R
voltage drop, the controller doesn’t initiate a new cycle. A new cycle starts only when the
sensed current goes below the current limit.
Since the current limit circuit is a valley current limit, the actual peak current limit is greater
than the current limit threshold by an amount equal to the inductor ripple current. Moreover
the maximum output current is equal to the valley current limit plus half of the inductor ripple
current:
current source (I
L
CSENSE
. If the voltage across the sensing element is greater than this
CSENSE
) is connected to C
pin and determines
SENSE
Equation 5
LvalleyLOAD
2
Δ
I
L
+=
I(max)I
The output current limit depends on the current ripple, as shown in Figure 34 on page 24:
Figure 34. Current waveforms in current limit conditions
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9DOOH\FXUUHQWWKUHVKROG
7LPH
Being fixed the valley threshold, the greater the current ripple is, greater the DC output
current is
24/48 Doc ID 11674 Rev 8
PM6685 Device description
The valley current limit can be set with resistor R
CSENSE
:
Equation 6
IRR×
I
CSENSE
LvalleyDSon
calculation.
DSon
=
Where I
CSENSE
= 100 µA, R
CSENSE
is the drain-source on resistance of the low side switch.
DSon
Consider the temperature effect and the worst case value in R
The accuracy of the valley current threshold detection depends on the offset of the internal
comparator (ΔV
) and on the accuracy of the current generator(ΔI
OFF
CSENSE
):
Equation 7
I
Δ
Lvalley
I
Lvalley
=
I
Δ
CSENSE
I
CSENSE
⎡
+
⎢
⎣
Where RSNS is the sensing element (R
V
Δ
DSon
OFF
×
IR
CSENSECSENSE
).
×
100
⎤
Δ
R
CSENSE
+
⎥
R
CSENSE
⎦
Δ
R
SNS
+
R
SNS
PM6685 provides also a fixed negative peak current limit to prevent an excessive reverse
inductor current when the switching section sinks current from the load in PWM mode. This
negative current limit threshold is measured between PHASE and SGND pins, comparing
the magnitude drop on the PHASE node during the conduction time of the low side
MOSFET with an internal fixed voltage of 120 mV.
If the current is sensed on the low side MOSFET, the negative valley-current limit INEG (if
the device works in PWM mode) is given by:
Equation 8
7.7 Soft start and soft end
Each switching section is enabled separately by asserting high EN5/EN3 pins respectively.
In order to realize the soft start, at the startup the overcurrent threshold is set 25% of the
nominal value and the undervoltage protection (see related sections) is disabled. The
controller starts charging the output capacitor working in current limit. The overcurrent
threshold is increased from 25% to 100% of the nominal value with steps of 25% every 700
μs (typ.). After 2.8 ms (typ.) the undervoltage protection is enabled. The soft start time is not
programmable. A minimum capacitor C
overshoot on the output:
Equation 9
I =
NEG
is required to ensure a soft start without any
INT
C ×
≥
INT
I
Lvalley
mV120
R
DSon
uA6
Δ
I
L
+
4
2
C
out
Doc ID 11674 Rev 8 25/48
Device description PM6685
Figure 35. Soft start waveforms
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&XUUHQWOLPLWWKUHVKROG
When a switching section is turned off(EN5/EN3 pins low), the controller enters in soft end
mode. The output capacitor is discharged through an internal 16 Ω P-MOSFET switch;
when the output voltage reaches 0.3 V, the low-side MOSFET turns on, keeping the output
to ground. The soft end time also depends on load condition.
7.8 Gate drivers
The integrated high-current drivers allow to use different power MOSFETs. The high side
driver MOSFET uses a bootstrap circuit which is indirectly supplied by LDO5 output. The
BOOT and PHASE pins work respectively as supply and return rails for the HS driver.
The low side driver uses the internal LDO5 output for the supply rail and PGND pin as return
rail.
An important feature of the gate drivers is the adaptive anti-cross conduction protection,
which prevents high side and low side MOSFETs from being on at the same time. When the
high side MOSFET is turned off the voltage at the phase node begins to fall. The low side
MOSFET is turned on when the voltage at the phase node reaches an internal threshold.
When the low side MOSFET is turned off, the high side remains off until the LGATE pin
voltage goes approximately under 1 V.
The power dissipation of the drivers is a function of the total gate charge Qg of the external
power MOSFETs and of the switching frequency, as shown in the following equation:
(1(1
7LPH
Where V
26/48 Doc ID 11674 Rev 8
is the 5 V driver supply.
driver
fQVP ××=
swgdriverdriver
PM6685 Device description
7.9 Reference voltage and bandgap
The 1.230 V (typ.) internal bandgap voltage is accurate to ±1% over the temperature range.
It is externally available (VREF pin) and can supply up to ±100μA and can be used as a
voltage threshold for the multifunction pins FSEL, SKIP and LDO3_SEL to select the
appropriate working mode. Bypass VREF to ground with a 100nF minimum capacitor.
If VREF goes below 0.87 V (typ.), the system detects a fault condition and all the circuitry is
turned off. A toggle on the input voltage (power on reset) or a toggle on SHDN pin is
necessary to restart the device.
An internal divider of the bandgap provides a voltage reference Vr of 0.9 V. This voltage is
used as reference for the linear and the switching regulators outputs. The overvoltage
protection, the undervoltage protection and the power good signals are referred to Vr.
7.10 Internal linear regulators
The PM6685 has two linear regulators providing respectively 5 V(LDO5) and 3.3 V(LDO3) at
±2% accuracy. High side drivers, low side drivers and most of internal circuitry are supplied
by LDO5 output through VCC pin (an external RC filter may be applied between LDO5 and
VCC). Both linear regulators can provide an average output current of 50 mA and a peak
output current of 100 mA. Bypass both LDO5 and LDO3 outputs with a minimum 1 μF
ceramic capacitor and a 4,7 μF tantalum capacitor (ESR < 2 Ω). If the 5 V output goes below
4V, the system detects a fault condition and all the circuitry is turned off. A power on reset or
a toggle on SHDN pin is necessary to restart the device.
V5SW pin allows to keep the 5 V linear regulator always active or to enable the internal
bootstrap-switch over function: if the 5 V switching output is connected to V5SW, when the
voltage on V5SW pin is above 4.8 V, an internal 3.0 Ω max p-channel MOSFET switch
connects V5SW pin to LDO5 pin and simultaneously LDO5 shuts down. This configuration
allows to achieve higher efficiency. V5SW can be connected also to an external 5 V supply.
LDO5 regulator turns off and LDO5 is supplied externally. If V5SW is connected to ground,
the internal 5 V regulator is always on and supplies LDO5 output.
Table 7. V5SW multifunction pin
V5SW Description
GND The 5V linear regulator is always turned on and supplies LDO5 output.
Switching 5V
output
External 5V
supply
The 5V linear regulator is turned off when the voltage on V5SW is above 4.8V
and LDO5 output is supplied by the switching 5V output.
The 5V linear regulator is turned off when the voltage on V5SW is above 4.8V
and LDO5 output is supplied by the external 5V.
The 3.3 V linear regulator is supplied by LDO5 output.
LDO3_SEL pin allows to keep 3.3 V linear regulator always enabled, always disabled or to
enable the internal bootstrap-switch over function. According to
● If LDO3_SEL is connected to VREF pin, when the power good signal of the 3.3 V
Ta ble 7 :
switching output voltage PGOOD3(see related sections) is high, the internal linear
Doc ID 11674 Rev 8 27/48
Device description PM6685
regulator is turned off and LDO3 output is connected directly to OUT3 pin through an
internal 3 Ω max p-channel MOSFET switch.
● If LDO3_SEL is connected to 5V, the internal 3.3 V regulator is always on and supplies
LDO3 output.
● If LDO3_SEL is connected to ground, the internal 3.3 V regulator is always off and
LDO3 output is clamped to ground.
Table 8. LDO3_SEL multifunction pin
LDO3_SEL Description
GND The 3.3V linear regulator is always turned off.
VREF
LDO5 The 3.3V linear regulator is always turned on and supplies LDO3 output.
The 3.3V linear regulator is turned off when PGOOD3 is high. LDO3 output is
supplied by the switching 3.3V output.
7.11 Power up sequencing and operative modes
Let’s consider SHDN, EN5 and EN3 low at the beginning. The battery voltage is applied as
input voltage. The device is in shutdown mode.
When the SHDN pin voltage is above the shutdown device on threshold(1.5V typ.), the
controller begins the power-up sequence. All the latched faults are cleared. LDO5
undervoltage control is blanked for 4 ms and the internal regulator LDO5 turns on. If the
LDO5 output is above the UVLO threshold after this time, the device enters in standby
mode. The switching outputs are kept to ground by turning on the low side MOSFETs.
When EN5 and EN3 pins are forced high the switching sections begin their soft start
sequence.
LDO3 management is independent from the general power up sequence and depends only
on LDO3_SEL.
Table 9. Operatives modes
Mode Conditions Description
Run
SHDN is high EN3/EN5
pins are high
Switching regulators are enabled; internal linear
regulators outputs are enabled.
Internal Linear regulators active (LDO5 is always on
Stand
Shutdown SHDN is low All circuits off.
28/48 Doc ID 11674 Rev 8
by Both EN5/EN3 pins are
low and SHDN pin is high
while LDO3 depends on LDO3_SEL pin). In Standby
mode LGATE5/LGATE3 pins are forced high while
HGATE5/HGATE3 pins are forced low.
PM6685 Monitoring and protections
8 Monitoring and protections
8.1 Power good signals
The PM6685 provides three independent power good signals: one for each switching
section(PGOOD5/PGOOD3) and the other for the internal linear regulator
LDO3(PGOOD_LDO3).
PGOOD5/PGOOD3 signals are low if the output voltage is out of ±10% of the designed set
point or during the soft-start, the soft end and when the device works in standby and
shutdown mode.
PGOOD_LDO3 signal is low when the output voltage of LDO3 output is lower than its falling
voltage threshold(2.6 V typ.). Each power good pin is an open-drain output and can sink
current up to 4 mA.
8.2 Thermal protection
The PM6685 has a thermal protection to preserve the device from overheating. The thermal
shutdown occurs when the die temperature goes above +150°C. In this case all internal
circuitry is turned off and the power sections are turned off after the discharge mode.
A power on reset or a toggle on the SHDN pin is necessary to restart the device.
8.3 Overvoltage protection
When the switching output voltage is about 115% of its nominal value, a latched overvoltage
protection occurs. In this case, the synchronous rectifier immediately turns on while the
high-side MOSFET turns off. The output capacitor is rapidly discharged and the load is
preserved from being damaged. The overvoltage protection is also active during the soft
start. Once an overvoltage protection has been detected, a toggle on SHDN, EN3/EN5 pins
or a power on reset is necessary to exit from the latched state.
8.4 Undervoltage protection
When the switching output voltage is below 70% of its nominal value, a latched undervoltage
protection occurs. In this case the switching section is immediately disabled and both
switches are open. The controller enters in soft end mode and the output is eventually kept
to ground, turning low side MOSFET on. The undervoltage circuit protection is enabled only
at the end of the soft-start. Once an overvoltage protection has been detected, a toggle on
SHDN, EN5/EN3 pin or a power on reset is necessary to clear the undervoltage fault and
starts with a new soft-start phase.
Doc ID 11674 Rev 8 29/48
Monitoring and protections PM6685
Table 10. Protections and operatives modes
Mode Conditions Description
Overvoltage
protection
Undervoltage
protection
Thermal
shutdown
OUT5/OUT3 > 115% of the
nominal value
OUT5/OUT3 < 70% of the
nominal value
> +150°C
T
J
8.5 Design guidelines
The design of a switching section starts from two parameters:
● Input voltage range: in notebook applications it varies from the minimum battery
voltage, VINmin to the AC adapter voltage, VINmax.
● Maximum load current: it is the maximum required output current, ILOAD(max).
8.6 Switching frequency
It’s possible to set 3 different working frequency ranges for the two sections: 200 kHz/300
kHz, 400 kHz/500 kHz, 600 kHz/700 kHz with FSEL pin.
Switching frequency mainly influences two parameters:
● Inductor size: for a given saturation current and RMS current, greater frequency allows
to use lower inductor values, which means smaller size.
● Efficiency: switching losses are proportional to frequency. High frequency generally
involves low efficiency.
LGATE5/LGATE3 pin is forced high, LDO5 remains
active. Exit by a power on reset or toggling SHDN or
EN5/EN3
LGATE5/LGATE3 is forced high after the soft end
mode, LDO5 remains active. Exit by a power on reset
or toggling SHDN or EN5/EN3
All circuitry off. Exit by a POR on VIN or toggling
SHDN.
8.7 Inductor selection
Once that switching frequency is defined, inductor selection depends on the desired
inductor ripple current and load transient performance.
Low inductance means great ripple current and could generate great output noise. On the
other hand, low inductor values involve fast load transient response.
A good compromise between the transient response time, the efficiency, the cost and the
size is to choose the inductor value in order to maintain the inductor ripple current ΔIL
between 20% and 50% of the maximum output current ILOAD(max). The maximum ΔIL
occurs at the maximum input voltage. With this considerations, the inductor value can be
calculated with the following relationship:
Equation 10
VV
−
L ×
=
30/48 Doc ID 11674 Rev 8
OUTIN
If
Δ×
Lsw
V
OUT
V
IN
PM6685 Monitoring and protections
where fsw is the switching frequency, VIN is the input voltage, VOUT is the output voltage
and ΔIL is the selected inductor ripple current.
In order to prevent overtemperature working conditions, inductor must be able to provide an
RMS current greater than the maximum RMS inductor current ILRMS:
Equation 11
Δ
2
L
(max))I(I
LOADLRMS
+=
2
(max))I(
12
Where ΔIL(max) is the maximum ripple current:
Equation 12
VV
sw
−
Lf
×
(max)I ×
L
=Δ
V
OUTmaxIN
OUT
V
maxIN
If hard saturation inductors are used, the inductor saturation current should be much greater
than the maximum inductor peak current Ipeak:
Equation 13
LOAD
2
Δ
(max)I
L
+=
(max)IIpeak
Using soft saturation inductors it’s possible to choose inductors with saturation current limit
nearly to Ipeak.
Below there is a list of some inductor manufacturers.
Table 11. Inductor manufacturer
Manufacturer Series Inductor value (µH) RMS current (A) Saturation current (A)
COILCRAFT SER1360 4 to 8 6 to 8.6 7 to 12
COILCRAFT MLC 2.2 to 4.5 13.6 to 8.8 11.5 to 17
TDK RLF12560 2.7 to 10 7.5 to 11.5 7.5 to 14.4
8.8 Output capacitor
The selection of the output capacitor is based on the ESR value Rout and the voltage rating
rather than on the capacitor value Cout.
The output capacitor has to satisfy the output voltage ripple requirements. Lower inductor
value can reduce the size of the choke but increases the inductor current ripple ΔIL.
Since the voltage ripple VRIPPLEout is given by:
Equation 14
IRV Δ×=
LoutRIPPLEout
Doc ID 11674 Rev 8 31/48
Monitoring and protections PM6685
A low ESR capacitor is required to reduce the output voltage ripple. Switching sections can
work correctly even with 20 mV output ripple.
However, to reduce jitter noise between the two switching sections it’s preferable to work
with an output voltage ripple greater than 30 mV. If lower output ripple is required, a further
compensation network is needed (see
Closing the integrator loop paragraph).
Finally the output capacitor choice deeply impacts on the load transient response (see
transient response
Table 12. Output capacitor manufacturer
Manufacturer Series
SANYO
PANASONIC SPCAP UD, UE 150 to 220 4 to 6.3 9 to 18
paragraph). Below there is a list of some capacitor manufacturers.
POSCAP
TPB,TPD
8.9 Input capacitors selection
In a buck topology converter the current that flows into the input capacitor is a pulsed current
with zero average value. The input RMS current of the two switching sections can be roughly
estimated as follows:
Equation 15
Where D1, D2 are the duty cycles and I1, I2 are the maximum load currents of the two
sections.
Capacitor value
(μF)
150 to 330 4 to 6.3 35 to 65
2
11CinRMS
Rated voltage (V) ESR max (mΩ)
2
221
)D1(ID)D1(IDI
−××+−××=
2
Load
Input capacitor should be chosen with an RMS rated current higher than the maximum RMS
current given by both sections.
Tantalum capacitors are good in term of low ESR and small size, but they occasionally can
burn out if subjected to very high current during the charge. Ceramic capacitors have
usually a higher RMS current rating with smaller size and they remain the best choice.
Below there is a list of some ceramic capacitor manufacturers.
Table 13. Input capacitor manufacturer
Manufacturer Series
TAYIO YUDEN UMK325BJ106KM-T10 10 50
TAYIO YUDEN GMK325BJ106MN 10 35
TDK C3225X5R1E106M 10 25
32/48 Doc ID 11674 Rev 8
Capacitor value
(μF)
Rated voltage (V)
PM6685 Monitoring and protections
8.10 Power MOSFETs
Logic-level MOSFETs are recommended, since low side and high side gate drivers are
powered by LDO5. Their breakdown voltage VBR
In notebook applications, power management efficiency is a high level requirement. The
power dissipation on the power switches becomes an important factor in switching
selections. Losses of high-side and low-side MOSFETs depend on their working conditions.
The power dissipation of the high-side MOSFET is given by:
Equation 16
Maximum conduction losses are approximately:
Equation 17
must be higher than VINmax.
DSS
PPP +=
switchingconductionDHighSide
V
RP ××=
DSonconduction
OUT
V
LOAD
minIN
2
(max)I
where RDSon is the drain-source on resistance of the high side MOSFET.
Switching losses are approximately:
Equation 18
I
Δ
L
+×
2
ft)
××
swoff
2
P
switching
I
Δ
(max)I(V
LOADIN
=
L
−×
2
2
ft)
××
+
(max)I(V
LOADINswon
where ton and toff are the switching times of the turn off and turn off phases of the MOSFET.
As general rule, high side MOSFETs with low gate charge are recommended, in order to
minimize driver losses.
Below there is a list of possible choices for the high side MOSFET.
Table 14. High side MOSFET manufacturer
Manufacturer Type Gate charge (nC) Rated reverse voltage (V)
ST STS12NH3LL 10 30
ST STS17NH3LL 18 30
The power dissipation of the low side MOSFET is given by:
Equation 19
PP =
conductionDLowSide
Maximum conduction losses occur at the maximum input voltage:
Doc ID 11674 Rev 8 33/48
Monitoring and protections PM6685
Equation 20
DSonconduction
Choose a synchronous rectifier with low R
⎛
⎜
1RP ×
−×=
⎜
⎝
. When high side MOSFET turns on, the fast
DSon
⎞
V
OUT
⎟
LOAD
⎟
V
maxIN
⎠
2
(max)I
variation of the phase node voltage can bring up even the low side gate through its gatedrain capacitance CRSS, causing cross-conduction problems. Choose a low side MOSFET
that minimizes the ratio CRSS/CGS (CGS = CISS - CRSS).
Below there is a list of some possible low side MOSFETs.
Table 15. Low side MOSFET manufacturer
Manufacturer Type RDSon (mΩ)
ST STS17NF3LL 5.5 0.047 30
ST STS25NH3LL 3.5 0.011 30
Rated reverse voltage
(V)
Dual n-channel MOSFETs can be used in applications with a maximum output current of
about 3 A. Below there is a list of some MOSFET manufacturers.
Table 16. Dual MOSFET manufacturer
Manufacturer Type RDSon (mΩ) Gate charge (nC)
ST STS8DNH3LL 25 10 30
ST STS4DNF60L 65 32 60
Rated reverse
voltage (V)
A rectifier across the low side MOSFET is recommended. The rectifier works as a voltage
clamp across the synchronous rectifier and reduces the negative inductor swing during the
dead time between turning the high-side MOSFET off and the synchronous rectifier on. It
can increase the efficiency of the switching section, since it reduces the low side switch
losses. A schottky diode is suitable for its low forward voltage drop (0.3 V). The diode
reverse voltage must be greater than the maximum input voltage VINmax. A minimum
recovery reverse charge is preferable. Below there is a list of some schottky diode
manufacturers.
Table 17. Schottky diode manufacturer
Manufacturer Series
ST STPS1L30M 0.34 30 0.00039
ST STPS1L20M 0.37 20 0.000075
Forward voltage
8.11 Closing the integrator loop
The design of external feedback network depends on the output voltage ripple. If the ripple
is higher than approximately 30 mV, the feedback network (
keep the loop stable.
(V)
Rated reverse
voltage (V)
Reverse current
(uA)
Figure 36) is usually enough to
34/48 Doc ID 11674 Rev 8
PM6685 Monitoring and protections
Figure 36. Circuitry for output ripple compensation
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The stability of the system depends firstly on the output capacitor zero frequency. The
following condition should be satisfied:
Equation 21
fkf
=×>
Zoutsw
k
RC2
××π
outout
where k is a design parameter greater than 3 and Rout is the ESR of the output capacitor. It
determinates the minimum integrator capacitor value CINT:
Equation 22
g
C ×
>
INT
2
m
f
⎛
sw
f
−×π
⎜
⎝
Zout
k
Vr
V
⎞
OUT
⎟
⎠
where gm=50us is the integrator transconductance.
In order to ensure stability it must be also verified that:
Equation 23
g
C ×
INT
m
>
f2
×π
Vr
V
OUTZout
In order to reduce ground noise due to load transient on the other section, it is
recommended to add a resistor RINT and a capacitor Cfilt that, together with CINT, realize a
low pass filter (see
Figure 36). The cutoff frequency fCUT must be much greater (10 or more
times) than the switching frequency of the section:
Doc ID 11674 Rev 8 35/48
Monitoring and protections PM6685
J
J
U
9
Equation 24
f2
CUT
1
CC
×
××π
filtINT
CC
+
filtINT
R
=
INT
Due to the capacitive divider (CINT, Cfilt), the ripple voltage at the COMP pin is given by:
Equation 25
C
INT
VV
RIPPLEoutRIPPLE
INT
×=
CC
+
filtINT
RIPPLEout
qV
×=
Where VRIPPLEout is the output ripple and q is the attenuation factor of the output ripple.
If the ripple is very small (lower than approximately 30 mV), a further compensation network,
named virtual ESR network, is needed. This additional part generates a triangular ripple
that is added to the ESR output voltage ripple at the input of the integrator network. The
complete control schematic is represented in
Figure 37.
Figure 37. Virtual ESR network
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The T node voltage is the sum of the output voltage and the triangular waveform generated
by the virtual ESR network. In fact the virtual ESR network behaves like a further equivalent
ESR RESR.
A good trade-off is to design the network in order to achieve an RESR given by:
Equation 26
V
=
RIPPLE
Δ
I
R −
ESR
36/48 Doc ID 11674 Rev 8
7
7
R
L
out
PM6685 Monitoring and protections
where ΔIL is the inductor current ripple and VRIPPLE is the overall ripple of the T node
voltage. It should be chosen higher than approximately 30mV.
The stability of the system depends firstly on the output capacitor value and on RTOT:
Equation 27
RRR +=
outESRTOT
The following condition should be satisfied:
Equation 28
fkf
=×>
Zsw
k
××π
RC2
TOTout
Where k is a free design parameter greater than 3 and determines the minimum integrator
capacitor value CINT:
Equation 29
g
C ×
>
INT
m
f
⎛
sw
2
−×π
⎜
k
⎝
Vr
V
⎞
OUT
f
⎟
Z
⎠
In order to ensure stability it must be also verified that:
Equation 30
g
C ×
INT
m
>
f2
×π
Vr
V
OUTZout
C must be selected as shown:
Equation 31
C5C ×>
INT
R must be chosen in order to have enough ripple voltage on integrator input:
Equation 32
R
L
=
ESR
CR
×
R1 can be selected as follows:
Doc ID 11674 Rev 8 37/48
Monitoring and protections PM6685
Equation 33
⎛
⎜
R
×
⎜
1R
⎝
=
R
−
⎞
1
⎟
⎟
fC
×π×
Z
⎠
1
fC
×π×
Z
Example:
5 V section, f
=200 kHz, L=4.7 µH, Cout=100 µF ceramic (Rout~0 Ω). We design
SW
RESR = 30 mΩ. We choose CINT=1 nF by equations 31, 32 and Cfilt=47 pF, RINT=1.8 kΩ
by eq.26,27. C=6.8 nF by Eq.33. Then R=22 kΩ (eq.34) and R1=1 kΩ (eq.35).
38/48 Doc ID 11674 Rev 8
PM6685 Other parts design
S
S
9 Other parts design
● VIN filter
A VIN pin low pass filter is suggested to reduce switching noise. The low pass filter is
shown in the next figure:
Figure 38. VIN pin filter
5
5
1
,QSXW
YROWDJH
Typical components values are: R=3.9 Ω and C=4.7 µF.
● VCC filter
A VCC low pass filter helps to reject switching commutations noise:
&
&
99,,1
)
)
Figure 39. Inductor current waveforms
//''22
5
5
&
99&&&
&
&
Typical components values are: R=47 Ω and C=1 µF.
● VREF capacitor
A 10 nF to 100 nF ceramic capacitor on VREF pin must be added to ensure noise
rejection.
● LDO3 and LDO5 output capacitors
Bypass the output of each linear regulator with 1 µF ceramic capacitor closer to the LDO pin
and a 4.7 µF tantalum capacitor (ESR=2 Ω). In most applicative conditions a 4.7 µF ceramic
output capacitor can be enough to ensure stability.
● Bootstrap circuit
The external bootstrap circuit is represented in the next figure:
Doc ID 11674 Rev 8 39/48
Other parts design PM6685
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Figure 40. Bootstrap circuit
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The bootstrap circuit capacitor value CBOOT must provide the total gate charge to the high
side MOSFET during turn on phase. A typical value is 100 nF.
The bootstrap diode D must charge the capacitor during the off time phases. The maximum
rated voltage must be higher than VINmax.
A resistor RBOOT on the BOOT pin could be added in order to reduce noise when the
phase node rises up, working like a gate resistor for the turn on phase of the high side
MOSFET.
40/48 Doc ID 11674 Rev 8
PM6685 Design example
10 Design example
The following design example considers an input voltage from 7 V to 16 V. The two switching
outputs must deliver a maximum current of 5A. The selected switching frequencies are 200
kHz for the 5 V section and 300 kHz for the 3.3 V section.
10.1 Inductor selection
OUT5: I
Equation 34
We choose standard value L = 6 µH
ΔI
L(max)
I
= 5.07 A
LRMS
I
= 5 A + 0.95 A = 6.43 A
peak
OUT3: ILOAD = 5 A, 50% ripple current.
Equation 35
We choose standard value L=4 µH.
ΔI
L(max)
= 5.04 A
I
LRMS
I
= 5 A + 1.1 A = 6.1 A
peak
= 5 A, 60% ripple current.
LOAD
= 2.86 A @V
= 2.2 A @V
IN
IN
=16 V
=16 V
L μ≈
=
L μ≈
=
)V5V16(V5
−⋅
56.0V16KHz200
⋅⋅⋅
)33.316(33.3
−⋅
55.0V16KHz300
⋅⋅⋅
H7.5
H52.3
10.2 Output capacitor selection
We would like to have an output ripple greater than 35mV.
OUT5: POSCAP 6TPB330M
OUT3: POSCAP 6TPB330M
10.3 Power MOSFETs
OUT5: High side: STS12NH3LL
Low side: STS12NH3LL
OUT3: High side: STS12NH3LL
Doc ID 11674 Rev 8 41/48
Design example PM6685
Low side: STS12NH3LL
10.4 Current limit
OUT5:
Equation 36
(min)I
Δ
Equation 37
(max)I(min)I
LOADLvalley
L
−=
2
22.4
=
(Let’s assume the maximum temperature Tmax = 75°C in R
OUT3:
Equation 38
Equation 39
(Let’s assume Tmax = 75°C in R
10.5 Input capacitor
Maximum input capacitor RMS current is about 3.4 A. Then I
We put three 10 µF ceramic capacitors with Irms = 1.5 A.
R
CSENSE
R
CSENSE
≡ 686m25.16
LOADLvalley
≡ 681m25.16
calculation)
DSon
A22.4
μ
A100
(min)I
Δ
(max)I(min)I
L
−=
2
A19.4
μ
A100
Ω≈Ω⋅
calculation)
DSon
=
Ω≈Ω⋅
CinRMS
A19.4
> 3.4 A
10.6 Synchronous rectifier
OUT5: Schottky diode STPS1L30M
OUT3: Schottky diode STPS1L30M
10.7 Integrator loop
(Refer to Figure 30 on page 22)
OUT5: The ripple is greater than 30 mV, then the virtual ESR network is not required.
C
=1 nF; C
INT
42/48 Doc ID 11674 Rev 8
= 47 pF; R
filt
INT
= 1 kΩ
PM6685 Design example
OUT3: The ripple is greater than 30 mV, then the virtual ESR network is not required.
C
=1 nF; C
INT
= 47 pF; R
filt
INT
= 1 kΩ
10.8 Layout guidelines
The layout is very important in terms of efficiency, stability and noise of the system. It is
possible to refer to the PM6685 demonstration board for a complete layout example.
For good PC board layout follows these guidelines:
● Place on the top side all the power components (inductors, input and output capacitors,
MOSFETs and diodes). Refer them to a power ground plan, PGND. If possible, reserve
a layer to PGND plan. The PGND plan is the same for both the switching sections.
● AC current paths layout is very critical (see Figure 41 on page 44). The first priority is to
minimize their length. Trace the LS MOSFET connection to PGND plan as short as
possible. Place the synchronous diode D near the LS MOSFET. Connect the LS
MOSFET drain to the switching node with a short trace.
● Place input capacitors near HS MOSFET drain. It is recommended to use the same
input voltage plan for both the switching sections, in order to put together all input
capacitors.
● Place all the sensitive analog signals (feedbacks, voltage reference, current sense
paths) on the bottom side of the board or in an inner layer. Isolate them from the power
top side with a signal ground layer, SGND. Connect the SGND and PGND plans only in
one point (a multiple vias connection is preferable to a 0 ohm resistor connection) near
the PGND device pin. Place the device on the top or on the bottom size and connect
the exposed pad and the SGND pins to the SGND plan (see
Figure 41 on page 44).
Doc ID 11674 Rev 8 43/48
Design example PM6685
Figure 41. Current paths, ground connection and driver traces layout
● As general rule, make the high side and low side drivers traces wide and short.
The high side driver is powered by the bootstrap circuit. It’s very important to place
capacitor CBOOT and diode DBOOT as near as possible to the HGATE pin (for
example on the layer opposite to the device). Route HGATE and PHASE traces as near
as possible in order to minimize the area between them.
The Low side gate driver is powered by the 5V linear regulator output. Placing PGND
and LGATE pins near the low side MOSFETs reduces the length of the traces and the
crosstalk noise between the two sections.
● The linear regulator outputs are referred to SGND as long as the reference voltage
Vref. Place their output filtering capacitors as near as possible to the device.
● Place input filtering capacitors near VCC and VIN pins.
● It would be better if the feedback networks connected to COMP and OUT pins are
“referred” to SGND in the same point as reference voltage Vref. To avoid capacitive
coupling place these traces as far as possible from the gate drivers and phase
(switching) paths.
● Place the current sense traces on the bottom side. Use a dedicated connection
between the switching node and the current limit resistor RCSENSE.
44/48 Doc ID 11674 Rev 8
PM6685 Package mechanical data
11 Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.
Table 18. VFQFPN 5x5x1.0 32L pitch 0.50 package dimensions
Databook (mm)
Dim.
Min Typ Max
A0.80.91
A1 0 0.02 0.05
A3 0.2
b 0.18 0.25 0.3
D4.8555.15
D2 See exposed pad variations
E4.8555.15
E2 See exposed pad variations
e0.5
L 0.3 0.4 0.5
ddd 0.05
Table 19. Exposed pad variations
(1)(2)
D2
(2)
(2)
E2
Min Typ Max Min Typ Max
2.90 3.10 3.20 2.90 3.10 3.20
1. VFQFPN stands for Thermally Enhanced Very thin Fine pitch Quad Flat Package No lead. Very thin:
A = 1.00mm Max.
2. Dimensions D2 & E2 are not in accordance with JEDEC.
Doc ID 11674 Rev 8 45/48
Package mechanical data PM6685
Figure 42. VFQFPN 5x5x1.0 32L pitch 0.50 package drawings
46/48 Doc ID 11674 Rev 8
PM6685 Revision history
12 Revision history
*
Table 20. Document revision history
Date Revision Changes
17-Jan-2006 1 Initial release
21-Apr-2006 2 Few updates
03-May-2006 3 Graphical updates
29-Jun-2006 4 Mechanical data updated
11-Sep-2006 5
24-Oct-2006 6 Order code table updated
18-Oct-2007 7
30-Mar-2011 8
Changes electrical characteristics, added COMP value skip
mode, pin out updated
Updated: Current sensing option and absolute maximum
ratings Table 3 on page 8.
Updated: Coverpage, Ta ble 2 , Ta bl e 5 , Section 7, Figure 29,
Section 7.9
Doc ID 11674 Rev 8 47/48
PM6685
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48/48 Doc ID 11674 Rev 8
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