ST PM6681A User Manual
Dual synchronous step-down controller with adjustable LDO
Features
■ 6 V to 36 V input voltage range
■ Adjustable output voltages
■ 0.9 - 3.3 V LDO adjustable delivers 100 mA
peak current
■ 5 V LDO delivers 100 mA peak current
■ 1.237 V ±1 % reference voltage available
■ No R
MOSFETs' R
■ Negative current limit
■ Soft-start internally fixed at 2 ms
■ Soft output discharge
■ Latched UVP
■ Not-latched OVP
■ Selectable pulse skipping at light loads
■ Selectable minimum frequency (33 kHz) in
pulse skip mode
■ 5 mW maximum quiescent power
■ Independent Power Good signals
■ Output voltage ripple compensation
Applications
■ Embedded computer system
■ FPGA system power
■ Industrial applications on 24 V
■ High performance and high density DC-DC
modules
■ Notebook computer
current sensing using low side
SENSE
DS(on)
PM6681A
VFQFPN-32 (5 mm x 5 mm)
Description
PM6681A is a dual step-down controller
specifically designed to provide extremely high
efficiency conversion, with lossless current
sensing technique. The constant on-time
architecture assures fast load transient response
and the embedded voltage feed-forward provides
nearly constant switching frequency operation. An
embedded integrator control loop compensates
the DC voltage error due to the output ripple.
Pulse skipping technique increases efficiency at
very light load. Moreover a minimum switching
frequency of 33 kHz is selectable to avoid audio
noise issues. The PM6681A provides a selectable
switching frequency, allowing three different
values of switching frequencies for the two
switching sections. The output voltages OUT1
and OUT2 can be adjusted from 0.9 V to 5 V and
from 0.9 V to 3.3 V respectively. The device
provides also 2 LDOs, 5 V fixed and 0.9 V - 3.3 V
adjustable.
Table 1. Order codes
Order codes Package Packaging
PM6681A
PM6681ATR Tape and reel
June 2008 Rev 3 1/47
VFQFPN-32 (5 mm x 5 mm)
exposed pad
Tr ay
www.st.com
47
Contents PM6681A
Contents
1 Simplified application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3 Functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
6 Typical operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
7 Device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7.1 Constant on time PWM control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7.2 Constant on time architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7.3 Output ripple compensation and loop stability . . . . . . . . . . . . . . . . . . . . . 20
7.4 Pulse skip mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7.5 No-audible skip mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7.6 Current limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.7 soft-start and soft-end . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.8 Gate drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.9 Internal linear regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7.10 Power up sequencing and operative modes . . . . . . . . . . . . . . . . . . . . . . . 28
8 Monitoring and protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
8.1 Power good signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
8.2 Thermal protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
8.3 Overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
8.4 Undervoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2/47
PM6681A Contents
9 Design guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
9.1 Switching frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
9.2 Inductor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
9.3 Output capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
9.4 Input capacitors selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
9.5 Power MOSFETs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
9.6 Closing the integrator loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
9.7 Other parts design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
9.8 Design example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
9.8.1 Inductor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
9.8.2 Output capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
9.8.3 Power MOSFETs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
9.8.4 Current limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
9.8.5 Input capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
9.8.6 Synchronous rectifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
9.8.7 Integrator loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
9.8.8 Output feedback divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
10 Layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
11 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3/47
Simplified application schematic PM6681A
1 Simplified application schematic
Figure 1. Application schematic
4/47
PM6681A Pin settings
V
2 Pin settings
2.1 Connections
Figure 2. Pin connection (top view)
VREF
VCC
32 31 30 29 28 27 26 25
SGND
COMP2
FSEL
EN2
SHDN
FB2
LDO
OUT2
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
HGATE2
BOOT2
PHASE2
COMP1
OUT
FB1
PPMM66668811AA
LGATE2
CSENSE2
PGOOD2
PGOOD
EN1
24
SKIP
23
BOOT1
22
HGATE1
21
PGND
LDO FB
LGATE1
20
19
18
17
PHASE1
CSENSE1
VIN
LDO5
5SW
2.2 Functions
Table 2. Pin functions
N° Pin Function
1SGND
2 COMP2 DC voltage error compensation pin for the switching section 2
3 FSEL
Signal ground. Reference for internal logic circuitry. It must be connected to
the signal ground plan of the power supply. The signal ground plan and the
power ground plan must be connected together in one point near the PGND
pin.
Frequency selection pin. It provides a selectable switching frequency,
allowing three different values of switching frequencies for the switching
sections.
5/47
Pin settings PM6681A
Table 2. Pin functions (continued)
N° Pin Function
Enable input for the switching section 2.
– The section 2 is enabled applying a voltage greater than 2.4 V to this pin.
4EN2
5 SHDN
6FB2
7LDO
8OUT2
– The section 2 is disabled applying a voltage lower than 0.8 V.
When the section is disabled the high side gate driver goes low and Low
Side gate driver goes high. If both EN1 and EN2 pins are low and SHDN pin
is high the device enters in standby mode.
Shutdown control input.
– The device switch off if the SHDN voltage is lower than the device off
threshold (shutdown mode)
– The device switch on if the SHDN voltage is greater than the device on
threshold.
The SHDN pin can be connected to the battery through a voltage divider to
program an undervoltage lockout. In shutdown mode, the gate drivers of the
two switching sections are in high impedance (high-Z).
Feedback input for the switching section 2 This pin is connected to a
resistive voltage-divider from OUT2 to PGND to adjust the output voltage
from 0.9 V to 3.3 V.
Adjustable internal regulator output. It can be set from 0.9 V to 3.3 V.
LDO pin can provide a 100 mA peak current.
Output voltage sense for the switching section 2. This pin must be directly
connected to the output voltage of the switching section.
9BOOT2
10 HGATE2
11 PHASE2
12 CSENSE2
13 LGATE2 Low-side gate driver output for the section 2.
14 PGND
15 LGATE1 Low-side gate driver output for the section 1.
16 LDO FB
17 V5SW
Bootstrap capacitor connection for the switching section 2. It supplies the
high-side gate driver.
High-side gate driver output for section 2. This is the floating gate driver
output.
Switch node connection and return path for the high side driver for the
section 2. It is also used as negative current sense input.
Positive current sense input for the switching section 2. This pin must be
connected through a resistor to the drain of the synchronous rectifier
(R
supply controller.
Power ground. This pin must be connected to the power ground plan of the
power supply.
Feedback input for the adjustable internal linear regulator. This pin is
connected to a resistive voltage-divider from LDO to SGND to adjust the
output voltage from 0.9 V to 3.3 V.
Internal 5 V regulator bypass connection.
– If V5SW is connected to OUT5 (or to an external 5 V supply) and V5SW is
If V5SW is connected to GND, the LDO5 linear regulator is always on if the
device is not in shutdown mode.
sensing) to obtain a positive current limit threshold for the power
DS(on)
greater than 4.9 V, the LDO5 regulator shuts down and the LDO5 pin is
directly connected to OUT5 through a 3 W (max) switch.
6/47
PM6681A Pin settings
Table 2. Pin functions (continued)
N° Pin Function
18 LDO5
19 VIN
20 CSENSE1
21 PHASE1
22 HGATE1
23 BOOT1
24 SKIP
25 EN1
26 PGOOD1
27 PGOOD2
28 FB1
29 OUT1
5 V internal regulator output. It can provide up to 100 mA peak current.
LDO5 pin supplies embedded low side gate drivers and an external load.
Device supply voltage input and battery voltage sense. A bypass filter
(4 W and 4.7 µF) between the battery and this pin is recommended.
Positive current sense input for the switching section 1. This pin must be
connected through a resistor to the drain of the synchronous rectifier
(R
supply controller.
Switch node connection and return path for the high side driver for the
section 1. It is also used as negative current sense input.
High-side gate driver output for section 1. This is the floating gate driver
output.
Bootstrap capacitor connection for the switching section 1. It supplies the
high-side gate driver.
Pulse skipping mode control input.
– If the pin is connected to LDO5 the PWM mode is enabled.
– If the pin is connected to GND, the pulse skip mode is enabled.
– If the pin is connected to VREF the pulse skip mode is enabled but the
Enable input for the switching section 1.
– The section 1 is enabled applying a voltage greater than 2.4 V to this pin.
– The section 1 is disabled applying a voltage lower than 0.8 V.
when the section is disabled the high side gate driver goes low and low side
gate driver goes high.
Power Good output signal for the section 1. This pin is an open drain output
and when the output of the switching section 1 is out of +/- 10 % of its
nominal value.It is pulled down.
Power Good output signal for the section 2. This pin is an open drain output
and when the output of the switching section 2 is out of +/- 10 % of its
nominal value.It is pulled down.
Feedback input for the switching section 1. This pin is connected to a
resistive voltage-divider from OUT1 to PGND to adjust the output voltage
from 0.9 V to 5.5 V.
Output voltage sense for the switching section 1.This pin must be directly
connected to the output voltage of the switching section.
sensing) to obtain a positive current limit threshold for the power
DS(on)
switching frequency is kept higher than 33 kHz
(No-audible pulse skip mode).
30 COMP1 DC voltage error compensation pin for the switching section 1.
31 VCC
32 VREF
Device supply voltage pin. It supplies all the internal analog circuitry except
the gate drivers (see LDO5). Connect this pin to LDO5.
Internal 1.237 V high accuracy voltage reference. It can deliver 50 µA.
Bypass to SGND with a 100 nF capacitor to reduce noise.
7/47
Functional block diagram PM6681A
3 Functional block diagram
Figure 3. Functional block diagram
8/47
PM6681A Maximum ratings
4 Maximum ratings
Table 3. Absolute maximum ratings
Parameter Value Unit
V5SW, LDO5 to PGND -0.3 to 6 V
VIN to PGND -0.3 to 36 V
HGATEx and BOOTx, to PHASEx -0.3 to 6 V
PHASEx to PGND -0.6
CSENSEx, to PGND -0.6 to 42 V
CSENSEx to BOOTx -6 to 0.3 V
LGATEx to PGND -0.3
FBx, COMPx, SKIP, FSEL,VREF to SGND, LDO FB -0.3 to Vcc+0.3 V
PGND to SGND -0.3 to 0.3 V
SHDN, PGOODx, OUTx, VCC, ENx to SGND -0.3 to 6 V
Power dissipation at T
Maximum withstanding voltage range test condition:
= 25 °C 2.8 W
A
VIN ±1000 V
CDF-AEC-Q100-002- “human body model” acceptance
criteria: “normal performance”
Other pins ±2000
(1)
to36
(2)
to LDO5 +0.3
V
V
1. PHASE to PGND up to -2.5 V for t < 10 ns
2. LGATEx to PGND up to -1 V for t < 40 ns
Table 4. Thermal data
Symbol Parameter Value Unit
T
R
STG
thJA
T
T
Storage temperature range -50 to 150 °C
Thermal resistance junction to ambient 35 °C/W
Junction operating temperature range -40 to 125 °C
J
Operating ambient temperature range -40 to 85 °C
A
Table 5. Recommended operating conditions
Val ue
Symbol Parameter Test condition
Min Typ Max
VIN Input voltage range LDO5 in regulation 5.5 36 V
VCC IC supply voltage 4.5 5.5 V
V
maximum operating
V
V5SW
V5SW
range
5.5 V
Unit
9/47
Electrical characteristics PM6681A
5 Electrical characteristics
Table 6. Electrical characteristics
(V
= 24 V; TJ = 25 °C, unless otherwise specified)
IN
Symbol Parameter Test condition Min Typ Max Unit
Supply section
Turn-on voltage threshold 4.8 4.9 V
V
V5SW
R
DS(on)
Turn-off voltage threshold 4.6 4.75 V
Hysteresis 20 50 mV
LDO5 internal bootstrap
switch resistance
V5SW > 4.9 V 1.8 3 Ω
OUTx, OUTx
discharge-mode
18 25 Ω
On-resistance
OUTx, OUTx
discharge-mode
Synchronous rectifier
0.20.350.6 V
turn-on level
Pin
Ish
Isb
Operating power
consumption
Operating current sunk by
V
IN
Operating current sunk by
V
IN
Shutdown section
Device on threshold 1.2 1.5 1.7 V
V
SHDN
Device off threshold 0.8 0.85 0.9 V
soft-start section
soft-start ramp time 2 3.5 ms
Current limit and zero crossing comparator
I
CSENSE
Input bias current limit
(1)
Comparator offset V
Zero crossing comparator
offset
Fixed negative current limit
threshold
FBx > VREF, Vref in regulation,
V5WS to 5 V
4mW
SHDN connected to GND 20 30 µA
ENx to GND, V5SW to GND 250 380 µA
90 100 110 µA
CSENSE
V
PGND
V
PGND
- V
- V
- V
PHASE
PHASE
PGND
-6 6 mV
-1 11 mV
-120 mV
10/47
PM6681A Electrical characteristics
Table 6. Electrical characteristics
(V
= 24 V; TJ = 25 °C, unless otherwise specified) (continued)
IN
Symbol Parameter Test condition Min Typ Max Unit
On time pulse width
FSEL to GND
575 680 785
OUT1 = 3.3 V
195 230 265
390 460 530
145 175 205
285 340 395
To n
On time duration_
@VIN = 24 V
OUT2 = 1.8 V
FSEL to VREF
OUT1 = 3.3 V
OUT2 = 1.8 V
FSEL to LDO5
OUT1 = 3.3 V
OUT2 =1.8 V
110 135 160
OFF time
T
OFFMIN
Minimum off time
@VIN = 24 V
350 500 ns
Voltag e refe r e n c e
V
REF
Voltage accuracy 4 V < V
Load regulation -100 µA< I
Undervoltage lockout fault
threshold
Falling edge of REF 0.95 mV
< 5.5 V 1.224 1.236 1.249 V
LDO5
< 100 µA-4 4mV
REF
Integrator
FB Voltage accuracy +891 +909 mV
FB Input bias current
(1)
0.1 µA
COMP Over voltage clamp Normal mode 250
COMP Under voltage clamp -150
ns
mV
Line regulation
LDO5 linear regulator
V
LDO5
LDO5 linear output voltage
LDO5 line regulation 6 V < VIN < 36 V, I
I
LDO5
U L V O
LDO5 current limit V
Under voltage lockout of
LDO5
LDO linear regulator
V
LDO
LDO linear output voltage
= 20 mA
(1)
4.9 5.0 5.1 V
,
Both SMPS, 6 V < Vin < 36 V
6 V < VIN < 36 V,
0 < I
LDO5
< 50 mA
LDO5
LDO5
> UVLO 270 330 400 mA
3.94 4 4.13 V
4.5 V< V5SW < 5.5 V
0.5 mA < I
LDO
< 50 mA
0.887 0.905 0.923 V
LDO FB connected to LDO
11/47
1%
0.004 %/V
Electrical characteristics PM6681A
Table 6. Electrical characteristics
(V
= 24 V; TJ = 25 °C, unless otherwise specified) (continued)
IN
Symbol Parameter Test condition Min Typ Max Unit
I
LDO
I
LDO FB
LDO current limit 170 220 270 mA
Input bias current
(1)
0.1 µA
High and low gate drivers
HGATEx high state (pull-up) 2.0 3
HGATE driver on-resistance
HGATEx low state (pull-down) 1.6 2.7
LGATEx high state (pull-up) 1.4 2.1
LGATE driver on-resistance
LGATEx low state (pull-down) 0.8 1.2
PGOOD pins UVP/OVP protections
Both SMPS sections with
OVP Over voltage threshold
respect to VREF, OUT1 = 5 V,
112 116 120 %
OUT2 = 3.3 V
UVP Under voltage threshold 65 68 71 %
Upper threshold
(VFB-VREF)
107 110 113 %
PGOOD1,2
I
PGOOD1,2
V
PGOOD1,2
Lower threshold
(VFB-VREF)
PGOOD leakage current V
output low voltage I
PGOOD1,2
Sink
forced to 5.5 V 1 uA
= 4 mA 150 250 mV
88 91 94 %
Power management pins
EN1,2
SMPS disabled level
SMPS enabled level
Frequency selection range Low level
(1)
(1)
(1)
0.8
2.4
0.5
Ω
V
V
FSEL
SKIP
1. by design
Pulse skip mode
Ultrasonic mode
PWM mode
Input leakage current
(1)
(1)
V
LDO5
V
LDO5
1.0
-
0.8
1.0
-
Middle level
High level
(1)
(1)
(1)
0.8
= 0 to 5 V 1
V
EN1,2
V
= 0 to 5 V 1
SKIP
= 0 to 5 V 1
V
SHDN
V
= 0 to 5 V 1
FSEL
LDO5
V
LDO5
-
1.5
0.5
-
1.5
12/47
V
V
µA
PM6681A Typical operating characteristics
6 Typical operating characteristics
(FSEL = GND (200/300 kHz), SKIP = GND (skip mode), V5SW = EXT5 V (external 5 V
power supply connected), input voltage VIN = 24 V, SHDN, EN1 and EN2 high,
OUT1 = 3.3 V, OUT2 = 1.8 V, no load, LDO = 3.3 V, (LDO_FB divider = 5.6 k and 15 k)
unless specified)
Figure 4. Efficiency vs current load Figure 5. Efficiency vs current load
\
Figure 6. PWM no load battery current
vs input voltage
\
Figure 7. No-audible skip no load
battery current vs input
voltage
Figure 8. Skip no load battery current
\
vs input voltage
13/47
Figure 9. Shutdown mode input battery
current vs input voltage
Typical operating characteristics PM6681A
Figure 10. Standby mode input battery
\
current vs input voltage
Figure 12. OUT1 = 3.3 V switching
\
frequency
Figure 11. Voltage reference vs load
current
Figure 13. OUT2 = 1.8 V switching
frequency
Figure 14. OUT1 = 3.3 V load regulation Figure 15. OUT2 = 1.8 V load regulation
\
14/47
PM6681A Typical operating characteristics
Figure 16. LDO5 vs output current Figure 17. LDO vs output current
\
Figure 18. SHDN, OUT1, LDO and LDO5
\
power-up
Figure 19. OUT1, OUT2, LDO and LDO5
power-up
Figure 20. OUT1 = 3.3 V load transient
\
0 to 2 A
Figure 21. OUT2 = 1.8 V load transient
0 to 2 A
15/47
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