ST PM6681A User Manual

PM6681A

Dual synchronous step-down controller with adjustable LDO

Features

■6 V to 36 V input voltage range

■Adjustable output voltages

■0.9 - 3.3 V LDO adjustable delivers 100 mA peak current

■5 V LDO delivers 100 mA peak current

■1.237 V ±1 % reference voltage available

■No RSENSE current sensing using low side MOSFETs' RDS(on)

■Negative current limit

■Soft-start internally fixed at 2 ms

■Soft output discharge

■Latched UVP

■Not-latched OVP

■Selectable pulse skipping at light loads

■Selectable minimum frequency (33 kHz) in pulse skip mode

■5 mW maximum quiescent power

■Independent Power Good signals

■Output voltage ripple compensation

Applications

■Embedded computer system

■FPGA system power

■Industrial applications on 24 V

■High performance and high density DC-DC modules

■Notebook computer

VFQFPN-32 (5 mm x 5 mm)

Description

PM6681A is a dual step-down controller specifically designed to provide extremely high efficiency conversion, with lossless current sensing technique. The constant on-time architecture assures fast load transient response and the embedded voltage feed-forward provides nearly constant switching frequency operation. An embedded integrator control loop compensates the DC voltage error due to the output ripple. Pulse skipping technique increases efficiency at very light load. Moreover a minimum switching frequency of 33 kHz is selectable to avoid audio noise issues. The PM6681A provides a selectable switching frequency, allowing three different values of switching frequencies for the two switching sections. The output voltages OUT1 and OUT2 can be adjusted from 0.9 V to 5 V and from 0.9 V to 3.3 V respectively. The device provides also 2 LDOs, 5 V fixed and 0.9 V - 3.3 V adjustable.

Table 1.	Order codes
	Order codes	Package	Packaging
	PM6681A	VFQFPN-32 (5 mm x 5 mm)	Tray
		exposed pad
	PM6681ATR		Tape and reel
June 2008		Rev 3	1/47
			www.st.com

Contents	PM6681A

Contents

1	Simplified application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. 4
2	Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		5
	2.1	Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	5
	2.2	Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	5
3	Functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		8
4	Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		9
5	Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		10
6	Typical operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		13
7	Device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		18
	7.1	Constant on time PWM control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	18
	7.2	Constant on time architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	20
	7.3	Output ripple compensation and loop stability . . . . . . . . . . . . . . . . . . . . .	20
	7.4	Pulse skip mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	21
	7.5	No-audible skip mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	22
	7.6	Current limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	23
	7.7	soft-start and soft-end . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	25
	7.8	Gate drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	25
	7.9	Internal linear regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	26
	7.10	Power up sequencing and operative modes . . . . . . . . . . . . . . . . . . . . . . .	28
8	Monitoring and protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		29
	8.1	Power good signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	29
	8.2	Thermal protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	29
	8.3	Overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	29
	8.4	Undervoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	29

2/47

PM6681A Contents

9	Design guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		30
	9.1	Switching frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	30
	9.2	Inductor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	30
	9.3	Output capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	31
	9.4	Input capacitors selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	32
	9.5	Power MOSFETs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	32
	9.6	Closing the integrator loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	34
	9.7	Other parts design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	38
	9.8	Design example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	39

9.8.1 Inductor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 9.8.2 Output capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 9.8.3 Power MOSFETs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 9.8.4 Current limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 9.8.5 Input capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 9.8.6 Synchronous rectifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 9.8.7 Integrator loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 9.8.8 Output feedback divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

10 Layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

11 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

3/47

Simplified application schematic	PM6681A

1 Simplified application schematic

Figure 1. Application schematic

4/47

PM6681A	Pin settings

2 Pin settings

2.1Connections

Figure 2. Pin connection (top view)

VREF

VCC

COMP1

OUT

FB1

PGOOD2

PGOOD

EN1

32	31	30	29	28	27	26	25
1							24

SGND

SKIP

2

COMP2

3

FSEL

4

EN2

5

SHDN

6

FB2

7

LDO

8

OUT2

9

BOOT2

PM6681A

10

11

12

13

14

23

BOOT1

22

HGATE1

21

PHASE1

20

CSENSE1

19

VIN

18

LDO5

17

V5SW

15

16

HGATE2

PHASE2

CSENSE2

LGATE2

PGND

LGATE1

FB LDO

2.2Functions

Table 2.		Pin functions
N°		Pin	Function
			Signal ground. Reference for internal logic circuitry. It must be connected to
1		SGND	the signal ground plan of the power supply. The signal ground plan and the
			power ground plan must be connected together in one point near the PGND
			pin.
2		COMP2	DC voltage error compensation pin for the switching section 2
			Frequency selection pin. It provides a selectable switching frequency,
3		FSEL	allowing three different values of switching frequencies for the switching
			sections.

5/47

Pin settings				PM6681A
	Table 2.		Pin functions (continued)
	N°		Pin	Function
				Enable input for the switching section 2.
				– The section 2 is enabled applying a voltage greater than 2.4 V to this pin.
	4		EN2	– The section 2 is disabled applying a voltage lower than 0.8 V.
				When the section is disabled the high side gate driver goes low and Low
				Side gate driver goes high. If both EN1 and EN2 pins are low and SHDN pin
				is high the device enters in standby mode.
				Shutdown control input.
				– The device switch off if the SHDN voltage is lower than the device off
				threshold (shutdown mode)
	5		SHDN	– The device switch on if the SHDN voltage is greater than the device on
				threshold.
				The SHDN pin can be connected to the battery through a voltage divider to
				program an undervoltage lockout. In shutdown mode, the gate drivers of the
				two switching sections are in high impedance (high-Z).
				Feedback input for the switching section 2 This pin is connected to a
	6		FB2	resistive voltage-divider from OUT2 to PGND to adjust the output voltage
				from 0.9 V to 3.3 V.
	7		LDO	Adjustable internal regulator output. It can be set from 0.9 V to 3.3 V.
				LDO pin can provide a 100 mA peak current.
	8		OUT2	Output voltage sense for the switching section 2. This pin must be directly
				connected to the output voltage of the switching section.
	9		BOOT2	Bootstrap capacitor connection for the switching section 2. It supplies the
				high-side gate driver.
	10		HGATE2	High-side gate driver output for section 2. This is the floating gate driver
				output.
	11		PHASE2	Switch node connection and return path for the high side driver for the
				section 2. It is also used as negative current sense input.
				Positive current sense input for the switching section 2. This pin must be
	12		CSENSE2	connected through a resistor to the drain of the synchronous rectifier
				(RDS(on) sensing) to obtain a positive current limit threshold for the power
				supply controller.
	13		LGATE2	Low-side gate driver output for the section 2.
	14		PGND	Power ground. This pin must be connected to the power ground plan of the
				power supply.
	15		LGATE1	Low-side gate driver output for the section 1.
				Feedback input for the adjustable internal linear regulator. This pin is
	16		LDO FB	connected to a resistive voltage-divider from LDO to SGND to adjust the
				output voltage from 0.9 V to 3.3 V.
				Internal 5 V regulator bypass connection.
				– If V5SW is connected to OUT5 (or to an external 5 V supply) and V5SW is
	17		V5SW	greater than 4.9 V, the LDO5 regulator shuts down and the LDO5 pin is
				directly connected to OUT5 through a 3 W (max) switch.
				If V5SW is connected to GND, the LDO5 linear regulator is always on if the
				device is not in shutdown mode.

6/47

PM6681A				Pin settings
	Table 2.		Pin functions (continued)
	N°		Pin	Function
	18		LDO5	5 V internal regulator output. It can provide up to 100 mA peak current.
				LDO5 pin supplies embedded low side gate drivers and an external load.
	19		VIN	Device supply voltage input and battery voltage sense. A bypass filter
				(4 W and 4.7 µF) between the battery and this pin is recommended.
				Positive current sense input for the switching section 1. This pin must be
	20		CSENSE1	connected through a resistor to the drain of the synchronous rectifier
				(RDS(on) sensing) to obtain a positive current limit threshold for the power
				supply controller.
	21		PHASE1	Switch node connection and return path for the high side driver for the
				section 1. It is also used as negative current sense input.
	22		HGATE1	High-side gate driver output for section 1. This is the floating gate driver
				output.
	23		BOOT1	Bootstrap capacitor connection for the switching section 1. It supplies the
				high-side gate driver.
				Pulse skipping mode control input.
				– If the pin is connected to LDO5 the PWM mode is enabled.
	24		SKIP	– If the pin is connected to GND, the pulse skip mode is enabled.
				– If the pin is connected to VREF the pulse skip mode is enabled but the
				switching frequency is kept higher than 33 kHz
				(No-audible pulse skip mode).
				Enable input for the switching section 1.
				– The section 1 is enabled applying a voltage greater than 2.4 V to this pin.
	25		EN1	– The section 1 is disabled applying a voltage lower than 0.8 V.
				when the section is disabled the high side gate driver goes low and low side
				gate driver goes high.
				Power Good output signal for the section 1. This pin is an open drain output
	26		PGOOD1	and when the output of the switching section 1 is out of +/- 10 % of its
				nominal value.It is pulled down.
				Power Good output signal for the section 2. This pin is an open drain output
	27		PGOOD2	and when the output of the switching section 2 is out of +/- 10 % of its
				nominal value.It is pulled down.
				Feedback input for the switching section 1. This pin is connected to a
	28		FB1	resistive voltage-divider from OUT1 to PGND to adjust the output voltage
				from 0.9 V to 5.5 V.
	29		OUT1	Output voltage sense for the switching section 1.This pin must be directly
				connected to the output voltage of the switching section.
	30		COMP1	DC voltage error compensation pin for the switching section 1.
	31		VCC	Device supply voltage pin. It supplies all the internal analog circuitry except
				the gate drivers (see LDO5). Connect this pin to LDO5.
	32		VREF	Internal 1.237 V high accuracy voltage reference. It can deliver 50 µA.
				Bypass to SGND with a 100 nF capacitor to reduce noise.

7/47

Functional block diagram	PM6681A

3 Functional block diagram

Figure 3. Functional block diagram

8/47

PM6681A	Maximum ratings

4 Maximum ratings

Table 3.	Absolute maximum ratings
	Parameter		Value	Unit
V5SW, LDO5 to PGND			-0.3 to 6	V
VIN to PGND			-0.3 to 36	V
HGATEx and BOOTx, to PHASEx			-0.3 to 6	V
PHASEx to PGND			-0.6 (1) to36	V
CSENSEx, to PGND			-0.6 to 42	V
CSENSEx to BOOTx			-6 to 0.3	V
LGATEx to PGND			-0.3 (2) to LDO5 +0.3	V
FBx, COMPx, SKIP, FSEL,VREF to SGND, LDO FB			-0.3 to Vcc+0.3	V
PGND to SGND			-0.3 to 0.3	V
SHDN, PGOODx, OUTx, VCC, ENx to SGND			-0.3 to 6	V
Power dissipation at TA = 25 °C			2.8	W
Maximum withstanding voltage range test condition:		VIN	±1000	V
CDF-AEC-Q100-002- “human body model” acceptance
		Other pins	±2000
criteria: “normal performance”

1.PHASE to PGND up to -2.5 V for t < 10 ns

2.LGATEx to PGND up to -1 V for t < 40 ns

Table 4.	Thermal data
Symbol	Parameter	Value	Unit
TSTG	Storage temperature range	-50 to 150	°C
RthJA	Thermal resistance junction to ambient	35	°C/W
TJ	Junction operating temperature range	-40 to 125	°C
TA	Operating ambient temperature range	-40 to 85	°C

	Table 5.	Recommended operating conditions
	Symbol	Parameter	Test condition		Value		Unit
				Min	Typ	Max
	VIN	Input voltage range	LDO5 in regulation	5.5		36	V
	VCC	IC supply voltage		4.5		5.5	V
	VV5SW	VV5SW maximum operating				5.5	V
		range

9/47

Electrical characteristics	PM6681A

5 Electrical characteristics

Table 6.	Electrical characteristics
	(VIN = 24 V; TJ = 25 °C, unless otherwise specified)
Symbol		Parameter	Test condition	Min	Typ	Max	Unit
Supply section
		Turn-on voltage threshold			4.8	4.9	V
VV5SW
		Turn-off voltage threshold		4.6	4.75		V
		Hysteresis		20	50		mV
RDS(on)		LDO5 internal bootstrap	V5SW > 4.9 V		1.8	3	Ω
		switch resistance
		OUTx, OUTx
		discharge-mode			18	25	Ω
		On-resistance
		OUTx, OUTx
		discharge-mode		0.2	0.35	0.6	V
		Synchronous rectifier
		turn-on level
Pin		Operating power	FBx > VREF, Vref in regulation,			4	mW
		consumption	V5WS to 5 V
Ish		Operating current sunk by	SHDN connected to GND		20	30	µA
		VIN
Isb		Operating current sunk by	ENx to GND, V5SW to GND		250	380	µA
		VIN
Shutdown section
VSHDN		Device on threshold		1.2	1.5	1.7	V
		Device off threshold		0.8	0.85	0.9	V
soft-start section
		soft-start ramp time		2		3.5	ms
Current limit and zero crossing comparator
ICSENSE		Input bias current limit (1)		90	100	110	µA
		Comparator offset	VCSENSE - VPGND	-6		6	mV
		Zero crossing comparator	VPGND - VPHASE	-1		11	mV
		offset
		Fixed negative current limit	VPGND - VPHASE		-120		mV
		threshold

10/47

PM6681A				Electrical characteristics
Table 6.	Electrical characteristics
	(VIN = 24 V; TJ = 25 °C, unless otherwise specified) (continued)
Symbol		Parameter	Test condition	Min	Typ	Max	Unit
On time pulse width
			FSEL to GND	575	680	785
			OUT1 = 3.3 V
				195	230	265
			OUT2 = 1.8 V
		On time duration_	FSEL to VREF	390	460	530
Ton			OUT1 = 3.3 V				ns
		@VIN = 24 V		145	175	205
			OUT2 = 1.8 V
			FSEL to LDO5	285	340	395
			OUT1 = 3.3 V
				110	135	160
			OUT2 =1.8 V
OFF time
TOFFMIN		Minimum off time			350	500	ns
		@VIN = 24 V
Voltage reference
VREF		Voltage accuracy	4 V < VLDO5 < 5.5 V	1.224	1.236	1.249	V
		Load regulation	-100 µA< IREF < 100 µA	-4		4	mV
		Undervoltage lockout fault	Falling edge of REF			0.95	mV
		threshold
Integrator
FB		Voltage accuracy		+891		+909	mV
FB		Input bias current	(1)		0.1		µA
COMP		Over voltage clamp	Normal mode		250		mV
COMP		Under voltage clamp			-150
Line regulation
			Both SMPS, 6 V < Vin < 36 V (1)			1	%
LDO5 linear regulator
VLDO5		LDO5 linear output voltage	6 V < VIN < 36 V,	4.9	5.0	5.1	V
			0 < ILDO5 < 50 mA
		LDO5 line regulation	6 V < VIN < 36 V, ILDO5 = 20 mA ,			0.004	%/V
ILDO5		LDO5 current limit	VLDO5 > UVLO	270	330	400	mA
ULVO		Under voltage lockout of		3.94	4	4.13	V
		LDO5
LDO linear regulator
			4.5 V< V5SW < 5.5 V
VLDO		LDO linear output voltage	0.5 mA < ILDO < 50 mA	0.887	0.905	0.923	V
			LDO FB connected to LDO

11/47

Electrical characteristics						PM6681A
Table 6.	Electrical characteristics
	(VIN = 24 V; TJ = 25 °C, unless otherwise specified) (continued)
Symbol		Parameter	Test condition	Min	Typ	Max	Unit
ILDO		LDO current limit		170	220	270	mA
ILDO FB		Input bias current	(1)		0.1		µA
High and low gate drivers
		HGATE driver on-resistance	HGATEx high state (pull-up)		2.0	3
			HGATEx low state (pull-down)		1.6	2.7	Ω
		LGATE driver on-resistance	LGATEx high state (pull-up)		1.4	2.1
			LGATEx low state (pull-down)		0.8	1.2
PGOOD pins UVP/OVP protections
			Both SMPS sections with
OVP		Over voltage threshold	respect to VREF, OUT1 = 5 V,	112	116	120	%
			OUT2 = 3.3 V
UVP		Under voltage threshold		65	68	71	%
		Upper threshold		107	110	113	%
		(VFB-VREF)
PGOOD1,2
		Lower threshold		88	91	94	%
		(VFB-VREF)
IPGOOD1,2		PGOOD leakage current	VPGOOD1,2 forced to 5.5 V			1	uA
VPGOOD1,2		output low voltage	ISink = 4 mA		150	250	mV
Power management pins
EN1,2		SMPS disabled level	(1)			0.8	V
		SMPS enabled level	(1)	2.4
		Frequency selection range	Low level (1)			0.5
FSEL			Middle level (1)	1.0		VLDO5 -	V
						1.5
			High level (1)	VLDO5 -
				0.8
		Pulse skip mode	(1)			0.5
SKIP		Ultrasonic mode	(1)	1.0		VLDO5 -	V
						1.5
		PWM mode	(1)	VLDO5 -
				0.8
			VEN1,2 = 0 to 5 V			1
		Input leakage current	VSKIP = 0 to 5 V			1	µA
			VSHDN = 0 to 5 V			1
			VFSEL = 0 to 5 V			1
1. by design

12/47

PM6681A	Typical operating characteristics

6 Typical operating characteristics

(FSEL = GND (200/300 kHz), SKIP = GND (skip mode), V5SW = EXT5 V (external 5 V power supply connected), input voltage VIN = 24 V, SHDN, EN1 and EN2 high,

OUT1 = 3.3 V, OUT2 = 1.8 V, no load, LDO = 3.3 V, (LDO_FB divider = 5.6 k and 15 k) unless specified)

Figure 4. Efficiency vs current load	Figure 5. Efficiency vs current load
	\

Figure 6. PWM no load battery current Figure 7.		No-audible skip no load
vs input voltage		battery current vs input
		voltage
	\

Figure 8. Skip no load battery current Figure 9.		Shutdown mode input battery
vs input voltage		current vs input voltage
	\

13/47

Typical operating characteristics	PM6681A

Figure 10. Standby mode input battery current vs input voltage

Figure 11. Voltage reference vs load current

\

Figure 12. OUT1 = 3.3 V switching frequency

Figure 13. OUT2 = 1.8 V switching frequency

\

Figure 14. OUT1 = 3.3 V load regulation Figure 15. OUT2 = 1.8 V load regulation

\

14/47

PM6681A						Typical operating characteristics
	Figure 16. LDO5 vs output current					Figure 17. LDO vs output current
						\

Figure 18. SHDN, OUT1, LDO and LDO5 Figure 19.		OUT1, OUT2, LDO and LDO5
power-up		power-up
	\

Figure 20. OUT1 = 3.3 V load transient	Figure 21. OUT2 = 1.8 V load transient
0 to 2 A	0 to 2 A
	\

15/47