ST PM6680A User Manual

Dual synchronous step-down controller

with adjustable output voltages plus LDO

Features

■ 6 V to 36 V input voltage range

■ Adjustable output voltages

■ 5V LDO delivers 100 mA peak current

■ 1.237 V ± 1 % reference voltage available

externally

■ Current sensing using low side MOSFETs

■ Valley current sensing

■ Soft-start internally fixed at 2ms

■ Soft output discharge

■ Latched OVP and UVP

■ Selectable pulse skipping at light loads

■ Selectable minimum frequency (33 kHz) in

pulse skip mode

■ 5mW maximum quiescent power

■ Independent power good signals

■ Output voltage ripple compensation

■ Thermal shutdown

Applications

■ Embedded computer system

■ FPGA system power

■ Industrial applications on 24 V

■ High performance and high density DC/DC

modules

DS(on)

PM6680A

VFQFPN-32 5X5

Description

PM6680A is a dual step-down controller specifically designed to provide extremely high efficiency conversion, with loss less current sensing technique. The constant on-time architecture assures fast load transient response and the embedded voltage feed-forward provides nearly constant switching frequency operation. An embedded integrator control loop compensates the DC voltage error due to the output ripple. Pulse skipping technique increases efficiency at very light load. Moreover a minimum switching frequency of 33 kHz is selectable to avoid audio noise issues. The PM6680A provides a selectable switching frequency, allowing three different values of switching frequencies for the two switching sections. The output voltages OUT1 and OUT2 can be adjusted from 0.9 V to 5 V and from 0.9 V to 3.3 V respectively.

Table 1. Device summary

Order codes Package Packaging

PM6680A

VFQFPN-32 5X5 (exposed pad)

PM6680ATR Tape and reel

December 2007 Rev 2 1/48

Tu b e

www.st.com

Contents PM6680A

Contents

1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2.1 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2.2 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3.1 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

5 Typical operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

6 Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

7 Device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

7.1 Constant On time PWM control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

7.2 Constant On time architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

7.3 Output ripple compensation and loop stability . . . . . . . . . . . . . . . . . . . . . 21

7.4 Pulse skip mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

7.5 No-audible skip mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

7.6 Current limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

7.7 Soft start and soft end . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

7.8 Gate drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

7.9 Reference voltage and bandgap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

7.10 Internal linear regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

7.11 Power up sequencing and operative modes . . . . . . . . . . . . . . . . . . . . . . . 28

8 Monitoring and protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

2/48

PM6680A Contents

9 Design guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

9.1 Switching frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

9.2 Inductor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

9.3 Output capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

9.4 Input capacitors selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

9.5 Power MOSFETS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

9.6 Closing the integrator loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

9.7 Other parts design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

9.8 Design example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

10 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

3/48

Block diagram PM6680A

1 Block diagram

Figure 1. Functional block diagram

REF

FB2

OUT2

SKIP

FSEL

BOOT2

HGATE2

PHASE2

COMP2

FREQUENCY

SELECTOR

LDO5

REFERENCE GENERATOR

LEVEL

SHIFTER

REF

LDO5 ENABLE

OUT2

SMPS

CONTROLLER

LINEAR

REGULATOR

CONTROLLER

4.8V

OUT1

SMPS

UVLO

SHIFTER

LEVEL

UVLO

LDO5

5SW

FB1

OUT1

BOOT1

HGATE1

PHASE1

CSENSE1 COMP1

LDO5

LGATE2

SHDN

EN2

UVLO

STARTUP

CONTROLLER

TERMIC

FAULT

LDO5 ENABLE

TERMIC

CONTROLLER

LGATE1

PGOOD1

EN1

4/48

PM6680A Pin settings

2 Pin settings

2.1 Connections

Figure 2. Pin connection (through top view)

PM6680A

5/48

Pin settings PM6680A

2.2 Functions

Table 2. Pin functions

N° Pin Function

Signal ground. Reference for internal logic circuitry. It must be connected to the

1 SGND1

2 COMP2 DC voltage error compensation pin for the switching section 2

3 FSEL

4EN2

5 SHDN

signal ground plan of the power supply. The signal ground plan and the power ground plan must be connected together in one point near the PGND pin.

Frequency selection pin. It provides a selectable switching frequency, allowing three different values of switching frequencies for the switching sections.

Enable input for the switching section 2.

• The section 2 is enabled applying a voltage greater than 2.4 V to this pin.

• The section 2 is disabled applying a voltage lower than 0.8 V.

When the section is disabled the High Side gate driver goes low and Low Side gate driver goes high. If both EN1 and EN2 pins are low and SHDN pin is high the device enters in standby mode.

Shutdown control input.

• The device switch off if the SHDN voltage is lower than the device off thershold (Shutdown mode)

• The device switch on if the SHDN voltage is greater than the device on threshold. The SHDN pin can be connected to the battery through a voltage divider to program

an undervoltage lockout. In shutdown mode, the gate drivers of the two switching sections are in high impedance (high-Z).

6 NC Not connected.

7FB2

8OUT2

9BOOT2

Feedback input for the switching section 2 This pin is connected to a resistive voltage-divider from OUT2 to PGND to adjust the output voltage from 0.9 V to 3.3 V.

Output voltage sense for the switching section 2.This pin must be directly connected to the output votage of the switching section.

Bootstrap capacitor connection for the switching section 2. It supplies the high-side gate driver.

10 HGATE2 High-side gate driver ouput for section 2. This is the floating gate driver output.

11 PHASE2

Switch node connection and return path for the high side driver for the section 2.It is also used as negative current sense input.

Positive current sense input for the switching section 2. This pin must be connected

12 CSENSE2

through a resistor to the drain of the synchronous rectifier (R

sensing) to obtain

DSON

a positive current limit threshold for the power supply controller.

13 LGATE2 Low-side gate driver output for the section 2.

14 PGND

Power ground. This pin must be connected to the power ground plan of the power supply.

15 LGATE1 Low-side gate driver output for the section 1.

16 SGND2

Signal ground for analog circuitry. It must be connected to the signal ground plan of the power supply.

6/48

PM6680A Pin settings

Table 2. Pin functions (continued)

N° Pin Function

Internal 5 V regulator bypass connection.

• If V5SW is connected to OUT5 (or to an external 5 V supply) and V5SW is greater

17 V5SW

than 4.9 V, the LDO5 regulator shuts down and the LDO5 pin is directly connected to OUT5 through a 3 Ω (max) switch.

If V5SW is connected to GND, the LDO5 linear regulator is always on.

18 LDO5

19 VIN

20 CSENSE1

21 PHASE1

22 HGATE1 High-side gate driver ouput for section 1. This is the floating gate driver output.

23 BOOT1

24 SKIP

25 EN1

26 PGOOD1

27 PGOOD2

28 FB1

29 OUT1

5V internal regulator output. It can provide up to 100 mA peak current. LDO5 pin supplies embedded low side gate drivers and an external load.

Device supply voltage input and battery voltage sense. A bypass filter (4 Ω and 4.7 µF) between the battery and this pin is recommended.

Positive current sense input for the switching section 1. This pin must be connected through a resistor to the drain of the synchronous rectifier (R a positive current limit threshold for the power supply controller.

Switch node connection and return path for the high side driver for the section 1.It is also used as negative current sense input.

Bootstrap capacitor connection for the switching section 1. It supplies the high-side gate driver.

Pulse skipping mode control input.

• If the pin is connected to LDO5 the PWM mode is enabled.

• If the pin is connected to GND, the pulse skip mode is enabled.

• If the pin is connected to VREF the pulse skip mode is enabled but the switching

frequency is kept higher than 33 kHz (No-audible puse skip mode).

Enable input for the switching section 1.

• The section 1 is enabled applying a voltage greater than 2.4 V to this pin.

• The section 1 is disabled applying a voltage lower than 0.8 V.

When the section is disabled the High Side gate driver goes low and Low Side gate driver goes high.

Power Good ouput signal for the section 1. This pin is an open drain ouput and when the ouput of the switching section 1 is out of +/- 10 % of its nominal value.It is pulled down.

Power Good ouput signal for the section 2. This pin is an open drain ouput and when the ouput of the switching section 2 is out of +/- 10 % of its nominal value.It is pulled down.

Feedback input for the switching section 1. This pin is connected to a resistive voltage-divider from OUT1 to PGND to adjust the output voltage from 0.9 V to 5.5 V.

Output voltage sense for the switching section 1.This pin must be directly connected to the output votage of the switching section.

sensing) to obtain

DSON

30 COMP1 DC voltage error compensation pin for the switching section 1.

31 VCC

32 VREF

Device supply voltage pin. It supplies all the internal analog circuitry except the gate drivers (see LDO5). Connect this pin to LDO5.

Internal 1.237 V high accuracy voltage reference. It can deliver 50 µA. Bypass to SGND with a 100 nF capacitor to reduce noise.

7/48

Electrical data PM6680A

3 Electrical data

3.1 Maximum rating

Table 3. Absolute maximum ratings

Parameter Value Unit

V5SW, LDO5 to PGND -0.3 to 6 V

VIN to PGND -0.3 to 36 V

HGATEx and BOOTx, to PHASEx -0.3 to 6 V

(1)

PHASEx to PGND -0.6

CSENSEx , to PGND -0.6 to 42 V

CSENSEx to BOOTx -6 to 0.3 V

LGATEx to PGND -0.3

FBx, COMPx, SKIP, , FSEL,,VREF to SGND1,SGND2 -0.3 to Vcc+0.3 V

PGND to SGND1,SGND2 -0.3 to 0.3 V

to36

(2)

to LDO5 +0.3

SHDN,PGOODx, OUTx, VCC, ENx to SGND1,SGND2 -0.3 to 6 V

Power Dissipation at T

Maximum withstanding Voltage range test condition: CDF-AEC-Q100-002- “Human Body Model” acceptance criteria: “Normal Performance”

1. PHASE to PGND up to -2.5 V for t < 10 ns

2. LGATEx to PGND up to -1 V for t < 40 ns

3.2 Thermal data

Table 4. Thermal data

Symbol Parameter Value Unit

thJA

STG

Thermal resistance junction to ambient 35 °C/W

Storage temperature range -40 to 150 °C

Junction operating temperature range -40 to 125 °C

= 25ºC 2.8 W

VIN ±1000

Other pins ±2000

8/48

PM6680A Electrical characteristics

4 Electrical characteristics

Table 5. Electrical characteristics

= -40 °C to 125 °C, unless otherwise specified. All parameters at operating temperature

extremes are guaranteed by design and statistical analysis (not production tested).

Symbol Parameter Test condition Min Typ Max Unit

Supply section

VIN Input voltage range Vout = Vref, LDO5 in regulation 5.5 36 V

V5SW

DS(on)

Ish

Isb

Shutdown section

IC supply voltage 4.5 5.5 V

Turn-ON voltage threshold 4.8 4.9 V

Turn-OFF voltage threshold

4.6 4.75 V

Hysteresis 20 50 mV

Maximum operating range 5.5 V

LDO5 Internal bootstrap switch resistance

V5SW > 4.9 V 1.8 3 Ω

OUTx,OUTx discharge-Mode

18 25 Ω

On-resistance

OUTx, OUTx discharge-Mode

Synchronous rectifier

0.20.360.6 V

Tu r n- o n l e v el

Operating power consumption

Operating current sunk by V

FBx > V V5WS to 5V

SHDN connected to GND, 20 30 µA

ENx to GND, V5SW to GND 190 250 µA

, Vref in regulation,

REF

4mW

SHDN

Device OFF threshold 0.8 0.85 0.9 V

Soft start section

Soft start ramp time 2 3.5 ms

Current limit and zero crossing comparator

Device ON threshold 1.2 1.5 1.7 V

CSENSE

Input bias current limit

(1)

Comparator offset V

Zero crossing comparator offset

Fixed negative current limit threshold

1. TA = -25 °C to 125 °C

CSENSE

- V

PGND

- V

PGND

90 100 110 µA

- V

PGND

PHASE

-6 6 mV

-1 11 mV

-120 mV

9/48

Electrical characteristics PM6680A

Table 5. Electrical characteristics (continued)

= -40 °C to 125 °C, unless otherwise specified. All parameters at operating temperature

extremes are guaranteed by design and statistical analysis (not production tested).

Symbol Parameter Test condition Min Typ Max Unit

Minimum on time

FSEL to GND

On time pulse width@Vin = 24 V

FSEL to VREF

FSEL to LDO5

Minimum off time

TOFFMIN @ Vin = 24 V 350 500 ns

Volt a g e re f e ren c e

Voltage accuracy 4V < VLDO5 < 5.5 V 1.224 1.236 1.249 V

VREF

Load regulation -100 µA < IREF < 100 µA -4 4 mV

Undervoltage lockout fault threshold

Falling edge of REF 0.95 mV

PWM comparator

FB Voltage accuracy -909 900 909 mV

FB Input bias current 0.1 µA

COMP Over voltage clamp

Normal mode 250

COMP Under voltage clamp -150

OUT1=3.3 V 595 700 805

OUT2=1.8 V 190 225 260

OUT1=3.3 V 400 470 545

OUT2=1.8 V 145 170 200

OUT1=3.3 V 300 355 410

OUT2=1.8 V 105 125 145

mVPulse skip mode 60

Line regulation

Both SMPS, 6V < V

< 36V

(2)

LDO5 linear regulation

< 36 V,

4.9 5.0 5.1 V

0.004 %/V

VLDO5

LDO5 linear output voltage

LDO5 line regulation

6 V < V 0 < ILDO5 < 50 mA

6 V < V ILDO5 = 20 mA ,

ILDO5 LDO5 current limit VLDO5 > UVLO 270 330 400 mA

ULVO

2. By demoboard test

Under voltage lockout of LDO5

3.94 4 4.13 V

10/48

PM6680A Electrical characteristics

Table 5. Electrical characteristics (continued)

= -40 °C to 125 °C, unless otherwise specified. All parameters at operating temperature

extremes are guaranteed by design and statistical analysis (not production tested).

Symbol Parameter Test condition Min Typ Max Unit

High and low gate drivers

HGATE driver on-resistence

LGATE driver on-resistance

PGOOD pins UVP/OVP protections

OVP Over voltage threshold

UVP Under voltage threshold 65 68 71 %

Upper threshold

PGOOD1,2

(VFB-VREF)

Lower threshold (VFB-VREF)

IPGOOD1,2

VPGOOD1,2

PGOOD leakage current VPGOOD1,2 forced to 5.5 V 1 µA

Output low voltage ISink = 4 mA 150 250 mV

HGATEx high state (pullup) 2.0 3 Ω HGATEx low state (pulldown) 1.6 2.7 Ω LGATEx high state (pullup) 1.4 2.1 Ω LGATEx low state (pulldown) 0.8 1.2 Ω

Both SMPS sections with respect to VREF

112 116 120 %

107 110 113 %

88 91 94 %

Thermal shutdown

SDN

Shutdown temperature 150 °C

Power management pins

EN1,2

SMPS disabled level 0.8

SMPS enabled level 2.4

FSEL Frequency selection range

Pulse skip mode

SKIP

PWM mode

Ultrasonic mode

Input leakage current

Low level

Middle level

High level

(3)

1.0

VLDO5-

0.8

1.0

VLDO5-

0.5

VLDO5-

1.5

0.5

VLDO5-

1.5

0.8

VEN1,2 = 0 to 5 V

VSKIP = 0 to 5 V

VSHDN = 0 to 5 V 1

VFSEL = 0 to 5 V 1

µA

3. By design

11/48

Typical operating characteristics PM6680A

5 Typical operating characteristics

FSEL=GND(200/300 kHz), SKIP=GND(skip mode), V5SW=EXT5V (external 5 V power supply connected), input voltage VIN = 24 V, SHDN, EN1 and EN2 high, OUT1 = 3.3 V, OUT2 = 1.8 V, no load unless specified)

Figure 3. OUT1 = 3.3 V efficiency Figure 4. OUT2 = 1.8 V efficiency

Figure 5. PWM no load battery current vs

input voltage

Figure 6. Skip no load battery current vs

input voltage

12/48

PM6680A Typical operating characteristics

Figure 7. No-audible skip no load battery

current vs input voltage

Figure 9. Shutdown mode input battery

current vs input voltage

Figure 8. Standby mode input battery current

vs input voltage

Figure 10. LDO5 vs output current

Figure 11. OUT1 = 3.3 V switching frequency Figure 12. OUT2 = 1.8 V switching frequency

13/48

Typical operating characteristics PM6680A

Figure 13. OUT1 = 3.3 V load regulation Figure 14. OUT2 = 1.8 V load regulation

Figure 15. Voltage reference vs load current Figure 16. OUT1, OUT2 and LDO5 Power-Up

Figure 17. OUT1 = 3.3V load transient 0→2A Figure 18. OUT2 = 1.8V load transient 0→2A

14/48

PM6680A Typical operating characteristics

Figure 19. 3.3 V soft start (1Ω load) Figure 20. 1.8 V soft start (0.6Ω load)

Figure 21. OUT1 = 3.3 V soft end (no load) Figure 22. OUT2 = 1.8 V soft end (no load)

Figure 23. OUT1 = 3.3 V soft end (0.8 load) Figure 24. OUT2 = 1.8 V soft end (0.6 load)

15/48

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