– 4.5 V to 28 V input voltage range
– 0.6 V, ±1 % voltage reference
– Selectable 1.5 V fixed output voltage
– Adjustable 0.6 V to 3.3 V output voltage
– 1.237 V ±1 % reference voltage available
– Very fast load transient response using
constant on-time control loop
–No R
MOSFETs' R
– Negative current limit
– Latched OVP and UVP
– Soft-start internally fixed at 3 ms
– Selectable pulse skipping at light load
– Selectable No-Audible (33 kHz) pulse skip
– Adjustable 0.6 V to 3.3 V output voltage
– Selectable ±1 Apk or ±2 Apk current limit
– Dedicated power-good signal
– Ceramic output capacitors supported
– Output soft-end
current sensing using low side
SENSE
DS(ON)
PM6675S
High efficiency step-down controller
with embedded 2 A LDO regulator
VFQFPN-24 4x4
Description
The PM6675S device consists of a single high
efficiency step-down controller and an
independent Low Drop-Out (LDO) linear
regulator.
The Constant On-Time (COT) architecture
assures fast transient response supporting both
electrolytic and ceramic output capacitors. An
embedded integrator control loop compensates
the DC voltage error due to the output ripple.
A selectable low-consumption mode allows the
highest efficiency over a wide range of load
conditions. The low-noise mode sets the minimum
switching frequency to 33 kHz for audio-sensitive
applications.
The LDO linear regulator can sink and source up
to 2 Apk. Two fixed current limits (±1 A-±2 A) can
be chosen.
Applications
■ Notebook computers
■ Graphic cards
■ Embedded computers
Table 1.Device summary
Order codesPackagePackaging
PM6675S
PM6675STRTape and reel
February 2008 Rev 11/53
VFQFPN-24 4x4 (exposed pad)
An active soft-end is independently performed on
both the switching and the linear regulators
outputs when disabled.
LDO power ground. Connect to the negative terminal of VTT output
capacitor.
LDO remote sensing. Connect as close as possible to the load via a low
noise PCB trace.
Pulse-Skip/No-Audible Pulse-Skip Modes selector.
See Section 7.1.4: Mode-of-operation selection on page 30
LDO section power-good signal (open drain output). High when LDO output
voltage is within ±10 % of nominal value.
Ground reference for analog circuitry, control logic and VTTREF buffer.
Connect together with the thermal pad and VTTGND to a low impedance
ground plane. See the Application Note for details.
+5 V supply for internal logic. Connect to +5 V rail through a simple RC
filtering network.
High accuracy output voltage reference (1.237 V) for multilevel pins setting.
It can deliver up to 50 µA. Connect a 100 nF capacitor between VREF and
SGND in order to enhance noise rejection.
Frequency selection. Connect to the central tap of a resistor divider to set
the desired switching frequency. The pin cannot be left floating. See
Section 7: Device description on page 19 for details.
Switching section output remote sensing and discharge path during output
soft-end. Connect as close as possible to the load via a low noise PCB
trace.
Fixed output selector and feedback input for the switching controller.
If VSEL pin voltage is higher than 4 V, the fixed 1.5 V output is selected. If
VSEL pin voltage is lower than 4 V, it is used as negative input of the error
amplifier. See Section 7.1.4: Mode-of-operation selection on page 30 for
details.
DC voltage error compensation input pin for the switching section. Refer to
Section 7.1.4: Mode-of-operation selection on page 30 for more details.
Current limit selector for the LDO. Connect to SGND for ±1 A current limit or
to +5 V for ±2 A current limit.
13SWEN
14LEN
15SPG
16PGNDPower ground for the switching section.
17LGATELow-side gate driver output.
18VCC+5 V low-side gate driver supply. Bypass with a 100 nF capacitor to PGND.
6/53
Switching controller enable. When tied to ground, the switching output is
turned off and a soft-end is performed.
Linear regulator enable. When tied to ground, the LDO output is turned off
and a soft-end is performed.
Switching section power good signal (open drain output). High when the
switching regulator output voltage is within ±10 % of nominal value.
PM6675SElectrical data
Table 2.Pin functions (continued)
N°PinFunction
Current sense input for the switching section. This pin must be connected
19CSNS
20PHASESwitch node connection and return path for the high side gate driver.
21HGATEHigh-Side Gate Driver Output
22BOOT
through a resistor to the drain of the synchronous rectifier (R
DS(ON)
sensing)
to set the current limit threshold.
Bootstrap capacitor connection. Input for the supply voltage of the high-side
gate driver.
23LIN
24LOUT
Linear Regulator Input. Bypass to LGND by a 10µF ceramic capacitor for
noise rejection enhancement.
LDO linear regulator output. Bypass with a 20µF (2 x 10 µF MLCC) filter
capacitor.
3 Electrical data
3.1 Maximum rating
Table 3.Absolute maximum ratings
SymbolParameterValueUnit
V
AVC C
V
VCC
V
PHASE
1. Free air operating conditions unless otherwise specified. Stresses beyond those listed under "absolute
maximum ratings" may cause permanent damage to the device. Exposure to absolute maximum rated
conditions for extended periods may affect device reliability.