Features
■ Switching section
– 4.5 V to 28 V input voltage range
– 0.6 V, ±1 % voltage reference
– Selectable 1.5 V fixed output voltage
– Adjustable 0.6 V to 3.3 V output voltage
– 1.237 V ±1 % reference voltage available
– Very fast load transient response using
constant on-time control loop
–No R
MOSFETs' R
– Negative current limit
– Latched OVP and UVP
– Soft-start internally fixed at 3 ms
– Selectable pulse skipping at light load
– Selectable No-Audible (33 kHz) pulse skip
mode
– Ceramic output capacitors supported
– Output voltage ripple compensation
– Output soft-end
■ LDO regulator section
– Adjustable 0.6 V to 3.3 V output voltage
– Selectable ±1 Apk or ±2 Apk current limit
– Dedicated power-good signal
– Ceramic output capacitors supported
– Output soft-end
current sensing using low side
SENSE
DS(ON)
PM6675S
High efficiency step-down controller
with embedded 2 A LDO regulator
VFQFPN-24 4x4
Description
The PM6675S device consists of a single high
efficiency step-down controller and an
independent Low Drop-Out (LDO) linear
regulator.
The Constant On-Time (COT) architecture
assures fast transient response supporting both
electrolytic and ceramic output capacitors. An
embedded integrator control loop compensates
the DC voltage error due to the output ripple.
A selectable low-consumption mode allows the
highest efficiency over a wide range of load
conditions. The low-noise mode sets the minimum
switching frequency to 33 kHz for audio-sensitive
applications.
The LDO linear regulator can sink and source up
to 2 Apk. Two fixed current limits (±1 A-±2 A) can
be chosen.
Applications
■ Notebook computers
■ Graphic cards
■ Embedded computers
Table 1. Device summary
Order codes Package Packaging
PM6675S
PM6675STR Tape and reel
February 2008 Rev 1 1/53
VFQFPN-24 4x4 (exposed pad)
An active soft-end is independently performed on
both the switching and the linear regulators
outputs when disabled.
Tu b e
www.st.com
Contents PM6675S
Contents
1 Typical application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.3 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5 Typical operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7 Device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.1 Switching section - constant on-time PWM controller . . . . . . . . . . . . . . . 20
7.1.1 Constant-On-Time architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7.1.2 Output ripple compensation and loop stability . . . . . . . . . . . . . . . . . . . . 23
7.1.3 Pulse-skip and no-audible pulse-skip modes . . . . . . . . . . . . . . . . . . . . . 27
7.1.4 Mode-of-operation selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7.1.5 Current sensing and current limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.1.6 POR, UVLO and Soft Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7.1.7 Switching section power good signal . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
7.1.8 Switching section output discharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
7.1.9 Gate drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.1.10 Reference voltage and bandgap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.1.11 Switching section OV and UV protections . . . . . . . . . . . . . . . . . . . . . . . 33
7.1.12 Device thermal protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
2/53
PM6675S Contents
7.2 LDO linear regulator section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.2.1 LDO section current limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7.2.2 LDO section Soft-Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.2.3 LDO section power good signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.2.4 LDO section output discharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
8 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
8.1 External components selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
8.1.1 Inductor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
8.1.2 Input capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
8.1.3 Output capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
8.1.4 MOSFETs selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
8.1.5 Diode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
8.1.6 VOUT current limit setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
8.1.7 All ceramic capacitors application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
9 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
3/53
Typical application circuit PM6675S
1 Typical application circuit
Figure 1. Application circuit
V
LDOIN
LDO PG
V
LDO
10
C
IN4
C
OUT2
VSEL
23
LIN
4
LPG
24
LOUT
2
LFB
1
LGND
SMPS PG
R
LP
C
IN3
312618822
LILIM
NOSKIP
SGND
5151413 711
AVCC
PM6675S
PM6675
LEN
SPG
C
B
O
O
VCC
SWEN
HGATE
VOSC
T
PHASE
LGATE
VREF
COMP
C
BYP
IN2
CSNS
PGND
VSNS
21
20
17
19
16
9
+5V
C
BOOT
V
BATT
R
1
C
R
2
IN
L
V
SMPS
C
R
LIM
OUT
C
INT
4/53
PM6675S Pin settings
2 Pin settings
2.1 Connections
Figure 2. Pin connection (through top view)
LOUT
LIN
24
1
LGND
BOOT
HGATE
PHASE
CSNS
19
18
VCC
LFB
NOSKIP
LPG
SGND
AVCC
LGATE
PM6675
PM6675S
6
7
VREF
VOSC
VSNS
VSEL
12
LILIM
COMP
PGND
SPG
LEN
SWEN
13
5/53
Pin settings PM6675S
2.2 Pin description
Table 2. Pin functions
N° Pin Function
1LGND
2LFB
3NOSKIP
4LPG
5SGND
6AVCC
7VREF
8VOSC
9 VSNS
10 VSEL
11 COMP
12 LILIM
LDO power ground. Connect to the negative terminal of VTT output
capacitor.
LDO remote sensing. Connect as close as possible to the load via a low
noise PCB trace.
Pulse-Skip/No-Audible Pulse-Skip Modes selector.
See Section 7.1.4: Mode-of-operation selection on page 30
LDO section power-good signal (open drain output). High when LDO output
voltage is within ±10 % of nominal value.
Ground reference for analog circuitry, control logic and VTTREF buffer.
Connect together with the thermal pad and VTTGND to a low impedance
ground plane. See the Application Note for details.
+5 V supply for internal logic. Connect to +5 V rail through a simple RC
filtering network.
High accuracy output voltage reference (1.237 V) for multilevel pins setting.
It can deliver up to 50 µA. Connect a 100 nF capacitor between VREF and
SGND in order to enhance noise rejection.
Frequency selection. Connect to the central tap of a resistor divider to set
the desired switching frequency. The pin cannot be left floating. See
Section 7: Device description on page 19 for details.
Switching section output remote sensing and discharge path during output
soft-end. Connect as close as possible to the load via a low noise PCB
trace.
Fixed output selector and feedback input for the switching controller.
If VSEL pin voltage is higher than 4 V, the fixed 1.5 V output is selected. If
VSEL pin voltage is lower than 4 V, it is used as negative input of the error
amplifier. See Section 7.1.4: Mode-of-operation selection on page 30 for
details.
DC voltage error compensation input pin for the switching section. Refer to
Section 7.1.4: Mode-of-operation selection on page 30 for more details.
Current limit selector for the LDO. Connect to SGND for ±1 A current limit or
to +5 V for ±2 A current limit.
13 SWEN
14 LEN
15 SPG
16 PGND Power ground for the switching section.
17 LGATE Low-side gate driver output.
18 VCC +5 V low-side gate driver supply. Bypass with a 100 nF capacitor to PGND.
6/53
Switching controller enable. When tied to ground, the switching output is
turned off and a soft-end is performed.
Linear regulator enable. When tied to ground, the LDO output is turned off
and a soft-end is performed.
Switching section power good signal (open drain output). High when the
switching regulator output voltage is within ±10 % of nominal value.
PM6675S Electrical data
Table 2. Pin functions (continued)
N° Pin Function
Current sense input for the switching section. This pin must be connected
19 CSNS
20 PHASE Switch node connection and return path for the high side gate driver.
21 HGATE High-Side Gate Driver Output
22 BOOT
through a resistor to the drain of the synchronous rectifier (R
DS(ON)
sensing)
to set the current limit threshold.
Bootstrap capacitor connection. Input for the supply voltage of the high-side
gate driver.
23 LIN
24 LOUT
Linear Regulator Input. Bypass to LGND by a 10µF ceramic capacitor for
noise rejection enhancement.
LDO linear regulator output. Bypass with a 20µF (2 x 10 µF MLCC) filter
capacitor.
3 Electrical data
3.1 Maximum rating
Table 3. Absolute maximum ratings
Symbol Parameter Value Unit
V
AVC C
V
VCC
V
PHASE
1. Free air operating conditions unless otherwise specified. Stresses beyond those listed under "absolute
maximum ratings" may cause permanent damage to the device. Exposure to absolute maximum rated
conditions for extended periods may affect device reliability.
AVCC to SGND -0.3 to 6
VCC to SGND -0.3 to 6
PGND, LGND to SGND -0.3 to 0.3
HGATE and BOOT to PHASE -0.3 to 6
HGATE and BOOT to PGND -0.3 to 44
PHASE to SGND -0.3 to 38
LGATE to PGND -0.3 to V
CSNS, SPG, LEN, SWEN, LILIM, COMP, VSEL,
VSNS, VOSC, VREF, NOSKIP to SGND
LPG,VREF, LOUT, LFB to SGND -0.3 to V
LIN, LOUT, LPG, LIN to LGND -0.3 to V
Maximum withstanding Voltage range test
condition: CDF-AEC-Q100-002- “Human Body
Model” acceptance criteria: “Normal
Performance”
(1)
CC
-0.3 to V
AVC C
AVC C
AVC C
± 1250 V
V
+0.3
+ 0.3
+ 0.3
+ 0.3
7/53
Electrical data PM6675S
3.2 Thermal data
Table 4. Thermal data
Symbol Parameter Value Unit
R
T
thJA
STG
T
A
T
J
Thermal resistance junction to ambient 42 °C/W
Storage temperature range - 50 to 150 °C
Operating ambient temperature range - 40 to 85 °C
Junction operating temperature range - 40 to 125 °C
3.3 Recommended operating conditions
Table 5. Recommended operating conditions
Symbol Parameter
V
AVC C
V
VCC
IN
Input voltage range 4.5 28
IC supply voltage 4.5 5.5
IC supply voltage 4.5 5.5
Val ues
Unit
Min Typ Max
VV
8/53
PM6675S Electrical characteristics
4 Electrical characteristics
Table 6. Electrical characteristics
T
= 0 °C to 85 °C, VCC = AVCC = +5 V, LIN = 1.5 V and LOUT = 0.6 V, if not otherwise
A
specified
(1)
Symbol Parameter Test condition
Supply section
I
IN
Operating current
(Switching + LDO)
SWEN, LEN, VSEL and
NOSKIP connected to AVCC,
No load on LOUT output.
SWEN, VSEL and NOSKIP
I
SW
Operating current (Switching)
connected to AVCC, LEN
connected to SGND.
I
SHDN
Shutdown operating current SWEN and LEN tied to SGND. 10 µA
AVCC under voltage lockout
upper threshold
UVLO
AVCC under voltage lockout
upper threshold
UVLO hysteresis 70 mV
ON-time (SMPS)
Val ues
Unit
Min Typ Max
2
mA
1
4.1 4.25 4.4
V
3.85 4.0 4.1
t
ON
On-time duration
OFF-time (SMPS)
t
OFFMIN
Minimum OFF-time 300 350 ns
Volt a g e re f e r enc e
Voltage accuracy 4.5 V< V
Load regulation -50 µA< I
Undervoltage Lockout Fault
Threshold
VSEL low,
VOSC=300 mV 530 630 730
NOSKIP low,
V
VSNS
= 2V
VOSC=500 mV 320 380 440
< 25 V 1.224 1.237 1.249 V
IN
< 50 µA -4 4
VREF
800
ns
mV
9/53
Electrical characteristics PM6675S
Table 6. Electrical characteristics (continued)
T
= 0 °C to 85 °C, VCC = AVCC = +5 V, LIN = 1.5 V and LOUT = 0.6 V, if not otherwise
A
specified
Symbol Parameter Test condition
SMPS output
(1)
Val ues
Unit
Min Typ Max
V
OUT
SMPS fixed output voltage
Feedback output voltage
accuracy
VSEL connected to AVCC,
NOSKIP tied to SGND, No Load
-1.5 1.5 %
1.5 V
Current limit and zero crossing comparator
I
CSNS
CSNS input bias current 90 100 110 µA
Comparator offset -6 6
V
ZC,OFFS
Positive current limit threshold V
Fixed negative current limit
threshold
Zero crossing comparator
offset
PGND
- V
CSNS
100
110
-11 -5 1
High and low side gate drivers
HGATE high state (pull-up) 2.0 3
HGATE driver on-resistance
HGATE low state (pull-down) 1.8 2.7
LGATE high state (pull-up) 1.4 2.1
LGATE driver on-resistance
LGATE low state (pull-down) 0.6 0.9
UVP/OVP protections and PGOOD signals
OVP Over voltage threshold 112 115 118
UVP Under voltage threshold 67 70 73
SMPS upper threshold 107 110 113
SMPS lower threshold 86 90 93
PGOOD
LDO upper threshold 107 110 113
LDO lower threshold 86 90 93
mV
Ω
%
I
PG,LEAK
V
PG,LOW
SPG and LPG Leakage
Current
SPG and LPG Low Level
Voltage
and LPG forced to 5.5 V 1 µA
SPG
I
LPG,SINK
= I
SPG,SINK
= 4 mA 150 250 mV
Soft-start section (SMPS)
Soft-start ramp time
(4 steps current limit)
234ms
Soft-start current limit step 25 µA
10/53
PM6675S Electrical characteristics
Table 6. Electrical characteristics (continued)
T
= 0 °C to 85 °C, VCC = AVCC = +5 V, LIN = 1.5 V and LOUT = 0.6 V, if not otherwise
A
specified
Symbol Parameter Test condition
Soft-end section
(1)
Val ues
Unit
Min Typ Max
LDO section
V
LREF
I
LDO,CL
I
LIN,BIAS
I
LFB,BIAS
I
LFB,LEAK
Switching section discharge
resistance
LDO section discharge
resistance
15 25 35
15 25 35
LDO reference voltage 600
LDO output accuracy respect
to VREF
LDO sink current limit
LDO source current limit
LDO input bias current, ON
-1 mA < I
-1 A < I
V
> V
LFB
> V
V
LFB
0.9 • V
LILIM = 5V
0.9 • V
LILIM = 0V
< 0.9 • V
V
LFB
< 0.9 • V
V
LFB
LEN connected to AVCC, no
load
< 1 mA -20 20
LDO
< 1 A -25 25
LDO
, LILIM = 5 V -3 -2.3 -2
LREF
, LILIM = 0 V -1.6 -1.3 -1
LREF
< V
LREF
LREF
< V
LFB
< V
< V
LFB
, LILIM = 5 V 1 1.3 1.6
LREF
, LILIM = 0 V 0.5 0.8 1.1
LREF
LREF
LREF
,
,
22.43
11.31.6
110
LDO input bias current, OFF LEN = 0 V, no load 1
LFB input bias current
LEN connected to AVCC
= 0.6 V
V
LFB
LFB leakage current LEN = 0 V, V
= 0.6 V -1 1
LFB
-1 1
Ω
mV
A
µA
11/53
Electrical characteristics PM6675S
Table 6. Electrical characteristics (continued)
T
= 0 °C to 85 °C, VCC = AVCC = +5 V, LIN = 1.5 V and LOUT = 0.6 V, if not otherwise
A
specified
Symbol Parameter Test condition
Power management section
V
VTHVSEL
V
VTHNOSKIP
VSEL pin thresholds
NOSKIP pin thresholds
(1)
Val ues
Min Typ Max
V
Fixed mode
Adjustable mode
Forced-PWM mode
No-audible mode 1.0
AVC C
-0.7
V
AVC C
-
0.8
V
AVC C
-
1.3
V
AVC C
-
1.5
Pulse-skip mode 0.5
Unit
V
V
VTHLEN
V
VTHSWEN
V
VTHLILIM
LEN, SWEN turn off level 0.4
,
LEN, SWEN turn on level 1.6
V
LILIM pin thresholds
±2 A LDO current limit
AVC C
-0.8
±1 A LDO current limit 0.5
I
IN,LEAK
IN3,LEAK
I
OSC,LEAK
Logic input leakage current LEN, SWEN and LILIM = 5 V 10
Multilevel input leakage
current
VSEL and NOSKIP = 5 V 10
VOSC pin leakage current VOSC = 1 V 1
Thermal shutdown
T
SHDN
1. TA = TJ. All parameters at operating temperature extremes are guaranteed by design and statistical analysis
(not production tested)
2. Guaranteed by design. Not production tested.
Shutdown temperature
(2)
150 °C
µAI
12/53
PM6675S Typical operating characteristics
5 Typical operating characteristics
Figure 3. VOUT efficiency vs load, 1.5 V,
100
90
80
70
60
50
40
Eff ici ency [%]
30
20
10
0
0.01 0.10 1.00 10.00
SW frequency = 400 kHz
SKIP @ 8V
SKIP @ 12V
SKIP @ 16V
No Aud. SKIP @ 8V
No Aud. SKIP @ 12 V
No Aud. SKIP @ 16 V
PWM @ 8V
PWM @ 12V
PWM @16V
Output Current [A]
Figure 4. VOUT efficiency vs load, 1.25 V,
SW frequency = 400 kHz
100
90
80
70
60
50
40
30
Efficiency [%]
20
10
0
0.01 0.10 1.00 10.00
Output Current [A]
SKIP @ 8V
SKIP @ 12V
SKIP @ 16V
No Aud. SKIP @ 8V
No Aud. SKIP @ 12V
No Aud. SKIP @ 16V
PWM @ 8V
PWM @ 12V
PWM @ 16V
Figure 5. VOUT load regulation, 1.5 V,
1.54
1.53
1.52
1.51
1.50
Output Volt age [ V]
1.49
1.48
Vin = 12 V
PWM
No Aud. SKIP
SKIP
0.01 0.10 1.00 10.00
Output Current [A]
Figure 7. VOUT load regulation, 2.5 V,
2.56
2.55
2.54
2.53
2.52
2.51
2.50
Output Voltage [V ]
2.49
2.48
Vin = 12 V
PWM
No A u d. S KIP
SKIP
0.01 0.1 1 10
Output Curre nt [A]
Figure 6. VOUT load regulation, 1.25 V,
Vin = 12 V
1.280
1.275
1.270
1.265
1.260
PWM
No Aud. SKIP
SKIP
1.255
1.250
Output Voltage [V]
1.245
1.240
0.01 0.10 1.00 10.00
Output Curre nt [A]
Figure 8. LOUT load regulation, LOUT = 0.9 V,
LIN = 1.5 V
0.94
0.93
0.92
0.91
0.90
LOUT [V]
0.89
0.88
0.87
-2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0
Output Curre nt [A]
13/53
Typical operating characteristics PM6675S
Figure 9. VOUT line regulation, 1.5 V, 0 A Figure 10. VOUT line regulation, 1.25 V, 0 A
1.540
1.535
1.530
1.525
1.520
1.515
Output Voltage [V]
1.510
0 102030
SKIP @ 0A
No Aud. SKIP @ 0A
PWM @ 0A
Input Voltage [V]
Figure 11. VOUT line regulation, 1.5 V Figure 12. VOUT line regulation, 1.25 V
1.5170
1.5165
1.5160
1.5155
1.5150
1.5145
1.5140
Output Voltage [V]
1.5135
1.5130
0 5 10 15 20 25 30
PWM @ 0A
PWM @ 7A
Input Voltage [V]
1.285
1.280
1.275
1.270
1.265
Output Voltage [V]
1.260
0 102030
Input Voltage [V]
1.2660
1.2655
1.2650
1.2645
1.2640
1.2635
Output Voltage [V]
1.2630
1.2625
0 5 10 15 20 25 30
Input Voltage [V]
SKIP @ 0A
No Aud. SKIP @ 0A
PWM @ 0 A
PWM @ 0 A
PWM @ 7 A
Figure 13. Switching frequency vs input
600
550
500
450
400
fsw [kHz ]
350
300
250
voltage, 1.5 V
PWM @ 0A
PWM @ 7A
0 5 10 15 20 25 30
Input Voltage [V]
Figure 14. Switching frequency vs input
voltage, 1.25 V
600
550
500
450
400
350
fsw [kHz ]
300
250
200
0 5 10 15 20 25 30
Input Voltage [V]
PWM @ 0 A
PWM @ 7 A
14/53
PM6675S Typical operating characteristics
Figure 15. Switching frequency vs load - 1.5 V Figure 16. PWM waveforms
600
500
400
300
fsw [kHz]
200
100
0
0.01 0.1 1 10
Output Current [A]
Figure 17. No-audible pulse-skip waveforms Figure 18. Pulse-skip waveforms
Pulse SKIP
No Aud. SKIP
PWM
Figure 19. Power-up sequence
VCC above UVLO
Figure 20. VOUT soft-start, 1.5 V, heavy load
15/53
Typical operating characteristics PM6675S
Figure 21. Switching section output soft-end Figure 22. LDO section output soft-end
Figure 23. -1.8 A to 1.8 A LOUT
load transient, 0.9 V
Figure 25. 0 A to 8 A VOUT
load transient, PWM
Figure 24. -1 A to 1 A LOUT
load transient, 0.9 V
Figure 26. 8 A to 0 A VOUT
load transient, PWM
16/53
PM6675S Typical operating characteristics
Figure 27. 0 A to 5 A VOUT load transient,
Pulse-Skip
Figure 29. Over-voltage protection,
VOUT = 1.5 V
Figure 28. 5 A to 0 A VOUT load transient,
Pulse-Skip
Figure 30. Under-voltage protection,
VOUT = 1.5 V
17/53
Block diagram PM6675S
6 Block diagram
Figure 31. Functional and block diagram
VREF
VREF
LFB
LFB
LFB
LIN
LIN
LIN
LOUT
LOUT
LOUT
LGND
LGND
LPG
LPG
LPG
SGND
SGND
SGND
Vr = 0.6V
Vr = 0.6V
Vr = 0.6V
LDS
LDS
Vr +10
Vr +10
Vr +10
VREF
_
_
_
+
+
+
LEN
LEN
LEN
%
%
%
+
+
+
-
-
-
+
+
+
-
-
-
Vr -10
Vr -10
Vr -10
UVP/OVP
UVP/OVP
UVP/OVP
0.6V
0.6V
0.6V
1.236V
1.236V
1.236V
Bandgap
Bandgap
Bandgap
LILIM
LILIM
LILIM
%
%
%
VOSC
VOSC
VOSC
Ton
Ton
Ton
1-shot
1-shot
1-shot
Ton
Ton
Ton
min
min
min
1-shot
1-shot
1-shot
Toff
Toff
Toff
min
min
min
1-shot
1-shot
1-shot
SWEN
SWEN
SWEN
Vr
Vr
Vr
Anti Cross
Anti Cross
Anti Cross
Conduction
Conduction
Conduction
_
_
_
+
+
+
g
g
g
m
m
m
_
_
_
+
+
+
VREF
VREF
VREF
Vr +10
Vr +10
Vr +10
Vr
Vr
Vr
Vr -10
Vr -10
Vr -10
Level
Level
Level
shifter
shifter
shifter
Zero Crossing
Zero Crossing
Zero Crossing
& Current
& Current
& Current
Limit
Limit
Limit
%
%
%
+
+
+
-
-
-
+
+
+
-
-
-
%
%
%
BOOT
BOOT
BOOT
HGATE
HGATE
HGATE
PHASE
PHASE
PHASE
VCC
VCC
VCC
LGATE
LGATE
LGATE
PGND
PGND
PGND
CSNS
CSNS
CSNS
COMP
COMP
COMP
SPG
SPG
SPG
AVCC
AVCC
AVCC
LILIM
LILIM
NOSKIP
NOSKIP
NOSKIP
Table 7. Legend
UVLO
UVLO
UVLO
Thermal S hutdown
Thermal S hutdown
Thermal S hutdown
LEN
LEN
LEN
LDS
LDS
LDS
SWEN
SWEN
SWEN
CONTROL LOGIC
CONTROL LOGIC
CONTROL LOGIC
SWEN
SWEN
SWEN
LDS
LDS
VSEL
VSEL
VSEL
LEN
LEN
LEN
VSNS
VSNS
VSNS
SDS
SDS
SDS
fixadj
fixadj
fixadj
SWEN Switching controller enable
LEN LDO regulator enable
LDS LDO output discharge enable
SDS Switching output discharge enable
LILIM LDO regulator current limit
18/53
PM6675S Device description
7 Device description
The PM6675S combines a single high efficiency step-down controller and an independent
Low Drop-Out (LDO) linear regulator in the same package.
The switching controller section is a high-performance, pseudo-fixed frequency, ConstantOn-Time (COT) based regulator specifically designed for handling fast load transient over a
wide range of input voltages.
The switching section output can be easily set to a fixed 1.5 V voltage without additional
components or adjusted in the 0.6 V to 3.3 V range using an external resistor divider. The
Switching Mode Power Supply (SMPS) can handle different modes of operation in order to
minimize noise or power consumption, depending on the application needs. Selectable lowconsumption and low-noise modes allow the highest efficiency and a 33 kHz minimum
switching frequency respectively at light loads.
A lossless current sensing scheme, based on the Low-Side MOSFET turn-on resistance,
avoids the need for an external sensing resistor.
The input of the LDO can be either the switching section output or a lower voltage rail in
order to reduce the total power dissipation. Linear regulator stability is achieved by filtering
its output with a ceramic capacitor (20 µF or greater). The LDO linear regulator can sink and
source up to 2 Apk.
Two fixed current limit (±1 A-±2 A) can be chosen.
An active soft-end is independently performed on both the switching and the linear
regulators outputs when disabled.
19/53
Device description PM6675S
7.1 Switching section - constant on-time PWM controller
The PM6675S employes a pseudo-fixed frequency, Constant On-Time (COT) controller as
the core of the switching section. It is well known that the COT controller uses a relatively
simple algorithm and uses the ripple voltage derived across the output capacitor ESR to
trigger the On-Time one-shot generator. In this way, the output capacitor ESR acts as a
current sense resistor providing the appropriate ramp signal to the PWM comparator.
Nearly constant switching frequency is achieved by the system loop in steady-state
operating conditions by varying the On-Time duration, avoiding thus the need for a clock
generator. The On-Time one shot duration is directly proportional to the output voltage,
detected by theVSNS pin, and inversely proportional to the input voltage, detected by the
the VOSC pin, as follows:
Equation 1
V
KT
SNS
OSCON
V
τ+=
OSC
where K
is a constant value (130 ns typ.) and τ is the internal propagation delay
OSC
(40ns typ.). The one-shot generator directly drives the high-side MOSFET at the beginning
of each switching cycle allowing the inductor current to increase; after the On-Time has
expired, an Off-Time phase, in which the low-side MOSFET is turned on, follows. The OffTime duration is solely determined by the output voltage: when lower than the set value (i.e.
the voltage at VSNS pin is lower than the internal reference V
= 0.6 V), the synchronous
R
rectifier is turned off and a new cycle begins (Figure 32).
Figure 32. Inductor current and output voltage in steady state conditions
Inductor
current
Output
voltage
V
reg
Ton
Toff
t
20/53
PM6675S Device description
The duty-cycle of the buck converter is, in steady-state conditions, given by
Equation 2
V
OUT
D
--------------=
V
IN
The switching frequency is thus calculated as
Equation 3
V
OUT
SW
D
T
ON
f ⋅
V
IN
V
OSC
V
SNS
OSC
K
α
OSC
===
α
1
K
OSCOUT
where
Equation 4a
V
α
OSC
-------------- -=
OSC
V
IN
Equation 4b
V
α
OUT
--------------=
V
SNS
OUT
Referring to the typical application schematic (figures on cover page and Figure 33), the
final expression is then:
Equation 5
α
f ⋅
SW
OSC
=
K
OSC
R
2
=
+
1
K
RR
OSC21
Even if the switching frequency is theoretically independent from battery and output
voltages, parasitic parameters involved in the power path (like MOSFET on-resistance and
inductor DCR) introduce voltage drops responsible for a slight dependence on load current.
In addition, the internal delay is due to a small dependence on input voltage.
The PM6675S switching frequency can be set by an external divider connected to the
VOSC pin.
21/53
Device description PM6675S
Figure 33. Switching frequency selection and VOSC pin
VIN
R1
R2
R2
VIN
R1
PM6675
PM6675
PM6675S
VOSC
VOSC
The voltage seen at this pin must be greater than 0.8 V and lower than 2 V in order to
ensure the system linearity.
7.1.1 Constant-On-Time architecture
Figure 34 shows the simplified block diagram of the Constant-On-Time controller.
The switching regulator of the PM6675S controls a one-shot generator that turns on the
high-side MOSFET when the following conditions are simultaneously satisfied: the PWM
comparator is high (i.e. output voltage is lower than Vr = 0.6 V), the synchronous rectifier
current is below the current limit threshold and the minimum off-time has expired.
A minimum Off-Time contraint (300ns typ.) is introduced to assure the boot capacitor charge
and allow inductor valley current sensing on low-side MOSFET. A minimum On-Time is also
introduced to assure the start-up switching sequence.
Once the On-Time has timed out, the high side switch is turned off, while the synchronous
rectifier is ignited according to the anti-cross conduction management circuitry.
When the output voltage reaches the valley limit (determined by internal reference
Vr = 0.6 V), the low-side MOSFET is turned off according to the anti-cross conduction logic
once again, and a new cycle begins.
22/53
PM6675S Device description
Figure 34. Switching section simplified block diagram
VOSC
VOSC
VOSC
VOSC
BOOT
BOOT
BOOT
BOOT
HGATE
HGATE
HGATE
HGATE
PHASE
PHASE
PHASE
PHASE
VCC
VCC
VCC
VCC
LGATE
LGATE
LGATE
LGATE
PGND
PGND
PGND
PGND
CSNS
CSNS
CSNS
CSNS
COMP
COMP
COMP
COMP
VSEL
VSEL
VSEL
VSEL
VSNS
VSNS
VSNS
VSNS
Positive Current Limit comparator
Positive Current Limit comparator
Positive Current Limit comparator
Positive Current Limit comparator
+
+
-
+
+
-
+
+
PWM Comparator
PWM Comparator
PWM Comparator
PWM Comparator
100uA
100uA
100uA
100uA
Integrator
Integrator
Integrator
Integrator
Min
Min
Min
Min
counter
counter
counter
counter
Zero--
Zero--
VBG
VBG
VBG
VBG
gm
gm
gm
gm
-
-
0.6V
0.6V
0.6V
0.6V
fsw
fsw
fsw
fsw
crossing
crossing
Zero
crossing
Zero
crossing
Comparator
Comparator
Comparator
Comparator
VOSC
VOSC
VOSC
Toff--
min
Toff--
min
Toff
min
Toff
min
1-Shot generator
1-Shot generator
S
S
-
-
R
R
Ton--
min
Ton--
min
Ton
min
Ton
min
VSEL<4V
VSEL<4V
Ton
Ton
Ton
Ton
VSNS
VOSC
VSNS
VOSC
VSNS
VOSC
VSNS
SKIP
SKIP
SKIP
SKIP
VOSC
Q
Q
S
S
R
R
Q
Q
+
+
_
_
PULSE --
PULSE --
PULSE
PULSE
VOSC
Level
Level
Level
Level
shifter
shifter
shifter
shifter
Q
Q
2.5V
2.5V
+
Anti cross-
Anti crossconduction
Q
Q
conduction
circuitry
circuitry
+
+
-
-
2.5V
2.5V
+
-
-
+
+
-
-
500mV
500mV
Q
S
Q
S
R
R
0.6V
0.6V
0.6V
0.6V
VBG
VBG
VBG
VBG
HS
HS
HS
HS
driver
driver
driver
driver
LS
LS
LS
LS
driver
driver
driver
driver
bandgap
bandgap
bandgap
bandgap
1.236V
1.236V
1.236V
1.236V
SGND
SGND
SGND
SGND
7.1.2 Output ripple compensation and loop stability
The loop is closed connecting the center tap of the output divider (internally, when the fixed
output voltage is chosen, or externally, using the VSEL pin in the adjustable output voltage
mode). The feedback node is the negative input of the error comparator, while the positive
input is internally connected to the reference voltage (Vr = 0.6 V). When the feedback
voltage becomes lower than the reference voltage, the PWM comparator goes to high and
sets the control logic, turning on the high-side MOSFET. After the On-Time (calculated as
previously described), the system releases the high-side MOSFET and turns on the
synchronous rectifier.
The voltage drop along ground and supply PCB paths, used to connect the output capacitor
to the load, is a source of DC error. Furthermore the system regulates the output voltage
valley, not the average, as shown in
capacitor is an additional source of DC error. To compensate this error, an integrative
network is introduced in the control loop, by connecting the output voltage to the COMP pin
through a capacitor (C
) as shown in Figure 35.
INT
Figure 37. Thus, the voltage ripple on the output
VREF
VREF
VREF
VREF
23/53
Device description PM6675S
Figure 35. Circuitry for output ripple compensation
COMP PIN
VOLTAGE
Vr
OUTPUT
VOLTAGE
∆V
REF
V
V
REF
R
Fb1
R
Fb1
+
-
PWM
PWM
Comparator
Comparator
t
C
C
∆V
t
ESR
ESR
OUT
C
OUT
C
FILT
FILT
C
C
R
R
INT
INT
INT
INT
COMP
COMP
V
V
VSNS
VSNS
C
C
INT
INT
I=gm(V1-Vr)
Vr
Vr
R
g
m
g
m
+
V
1
1
V
Fb2
R
Fb2
The additional capacitor is used to reduce the voltage on the COMP pin when higher than
300 mVpp and is unnecessary for most of applications. The trans conductance amplifier
(gm) generates a current, proportional to the DC error, used to charge the C
The voltage across the C
capacitor feeds the negative input of the PWM comparator,
INT
capacitor.
INT
forcing the loop to compensate the total static error. An internal voltage clamp forces the
COMP pin voltage range to ±150 mV respect to V
. This is useful to avoid or smooth
REF
output voltage overshoot during a load transient. When the Pulse-Skip Mode is entered, the
clamping range is automatically reduced to 60 mV in order to enhance the recovering
capability. If the ripple amplitude is larger than 150 mV, an additional capacitor C
FILT
can be
connected between the COMP pin and ground to reduce ripple amplitude, otherwise the
integrator will operate out of its linearity range. This capacitor is unnecessary for most of
applications and can be omitted.
The design of the external feedback network depends on the output voltage ripple. If the
ripple is higher than approximately 20 mV, the correct C
capacitor is usually enough to
INT
keep the loop stable. The stability of the system depends firstly on the output capacitor zero
frequency.
The following condition must be satisfied:
Equation 6
out
k
ESRC2
⋅⋅π
fkf
=⋅>
ZoutSW
where k is a fixed design parameter (k > 3). It determinates the minimum integrator
capacitor value:
24/53
PM6675S Device description
Equation 7
g
C
>
INT
2
m
f
⎛
SW
f
−⋅π
⎜
⎝
Zout
k
⎞
⎟
⎠
⋅
Vout
Vr
where gm = 50 µs is the integrator trans conductance.
If the ripple on the COMP pin is greater than 150 mV, the auxiliary capacitor C
added. If q is the desired attenuation factor of the output ripple, C
is given by:
FILT
FILT
can be
Equation 8
−⋅
INT
=
C
FILT
In order to reduce the noise on the COMP pin, it is possible to add a resistor R
together with CINT and C
, becomes a low pass filter. The cutoff frequency f
FILT
)q1(C
q
that,
INT
must be
CUT
much greater (10 or more times) than the switching frequency:
Equation 9
f2
CUT
1
CC
⋅
⋅⋅π
FILTINT
CC
+
FILTINT
R
=
INT
If the ripple is very small (lower than approximately 20mV), a different compensation
network, called "Virtual-ESR" Network, is needed. This additional circuit generates a
triangular ripple that is added to the output voltage ripple at the input of the integrator. The
complete control scheme is shown in
Figure 36.
25/53
Device description PM6675S
Figure 36. "Virtual-ESR" network
R
R
COMP PIN
VOLTAGE
T
∆V
∆V
V
REF
t
INT
C
INT
INT
R
C
INT
R
1
R
1
R
C
C
t
2
t
COMP
COMP
FILT
C
FILT
C
VSNS
VSNS
ESR
ESR
OUT
C
OUT
C
I=gm(V1-Vr)
-
Vr
Vr
R
R
Fb2
Fb2
V
REF
V
REF
+
-
PWM
PWM
Comparator
+
R
Fb1
R
Fb1
Comparator
g
m
g
m
V
1
1
V
T NODE
VOLTAGE
∆V
1
OUTPUT
VOLTAGE
The ripple on the COMP pin is the sum of the output voltage ripple and the triangular ripple
generated by the Virtual-ESR Network. In fact the Virtual-ESR Network behaves like a
another equivalent series resistor R
A good trade-off is to design the network in order to achieve an R
VESR
.
given by:
VESR
Equation 10
R
VESR
V
=
where ∆IL is the inductor current ripple and V
greater than approximately 20 mV.
The new closed-loop gain depends on C
. In order to ensure stability it must be verified
INT
that:
Equation 11
C
>
INT
where:
Equation 12
f
=
Z
and:
RIPPLE
I
∆
L
RIPPLE
g
m
f2
⋅π
Z
1
ESR
−
is the total ripple at the T node, chosen
Vr
⋅
Vout
RC2
⋅⋅π
TOTout
26/53
PM6675S Device description
Equation 13
R
= ESR + R
TOT
VESR
Moreover, the C
capacitor must meet the following condition:
INT
Equation 14
fkf
=⋅>
ZSW
where R
the Virtual-ESR Network (R
is the sum of the ESR of the output capacitor and the equivalent ESR given by
TOT
). The k parameter must be greater than unity (k > 3) and
VESR
determines the minimum integrator capacitor value C
k
⋅⋅π
RC2
TOTout
:
INT
Equation 15
g
C
>
INT
2
m
f
⎛
SW
−⋅π
⎜
k
⎝
Vr
⋅
Vout
⎞
f
⎟
Z
⎠
The capacitor of the Virtual-ESR Network, C, is chosen as follow
Equation 16
C5C⋅>
INT
and R is calculated to provide the desired triangular ripple voltage:
Equation 17
R
L
=
VESR
CR
⋅
Finally the R1 resistor is calculated according to Equation 18:
Equation 18
⎛
⎜
R
⋅
⎜
⎝
1R
=
R
−
⎞
1
⎟
⎟
Cf
⋅⋅π
Z
⎠
1
Cf
⋅⋅π
Z
27/53
Device description PM6675S
⋅
7.1.3 Pulse-skip and no-audible pulse-skip modes
High efficiency at light load conditions is achieved by PM6675S by entering the Pulse-Skip
Mode (if enabled). At light load conditions the zero-crossing comparator truncates the lowside switch On-Time as soon as the inductor current becomes negative; in this way the
comparator determines the On-Time duration instead of the output ripple.
(see
Figure 37).
Figure 37. Inductor current and output voltage at light load with Pulse-Skip
Inductor
current
Output
voltage
V
reg
T
ON
T
OFF
T
IDLE
t
As a consequence, the output capacitor is left floating and its discharge depends solely on
the current drained from the load. When the output ripple on the pin COMP falls under the
reference, a new shot is triggered and the next cycle begins. The Pulse-Skip mode is
naturally obtained enabling the zero-crossing comparator and automatically takes part in the
COT algorithm when the inductor current is about half the ripple current amount, i.e.
migrating from continuous conduction mode (C.C.M.) to discontinuous conduction mode
(D.C.M.).
The output current threshold related to the transition between PWM Mode and Pulse-Skip
Mode can be approximately calculated as:
Equation 19
VV
−
OUTIN
LOAD
)Skip2PWM(I ⋅
=
T
L2
ON
At higher loads, the inductor current never crosses the zero and the device works in pure
PWM mode with a switching frequency around the nominal value.
A physiological consequence of Pulse-Skip Mode is a more noisy and asynchronous (than
normal conditions) output, mainly due to very low load. If the Pulse-Skip is not compatible
with the application, the PM6675S allows the user to choose between forced-PWM and NoAudible Pulse-Skip alternative modes (see
page 30
for details).
Section 7.1.4: Mode-of-operation selection on
28/53
PM6675S Device description
No-audible pulse-skip mode
Some audio-noise sensitive applications cannot accept the switching frequency to enter the
audible range as it is possible in Pulse-Skip mode with very light loads. For this reason, the
PM6675S implements an additional feature to maintain a minimum switching frequency of
33kHz despite a slight efficiency loss. At very light load conditions, if any switching cycle has
taken place within 30µs (typ.) since the last one (because of the output voltage is still higher
than the reference), a No-Audible Pulse-Skip cycle begins. The low-side MOSFET is turned
on and the output is driven to fall until the reference point has been crossed. Then, the highside switch is turned on for a T
is enabled until the inductor current reaches the zero-crossing threshold (see
Figure 38. Inductor current and output voltage at light load with non-audible pulse-skip
Inductor
current
Output
voltage
V
reg
period and, once it has expired, the synchronous rectifier
ON
Figure 38).
T
MAX
TONT
OFF
T
IDLE
t
For frequencies higher than 33 kHz (due to heavier loads) the device works in the same way
as in Pulse-Skip mode. It is important to notice that in both Pulse-Skip and No-Audible
Pulse-Skip modes, the switching frequency changes not only with the load but also with the
input voltage.
29/53
Device description PM6675S
7.1.4 Mode-of-operation selection
Figure 39. VSEL and NOSKIP multifunction pin configurations
VOUT
+5V
PM6675
PM6675S
R9
VSEL
R8
V
REF
NOSKIP
The PM6675S has been designed to satisfy the widest range of applications. The device is
provided with some multilevel pins which allow the user to choose the appropriate
configuration. The VSEL pin is used to firstly decide between fixed preset or adjustable
(user defined) output voltages.
When the VSEL pin is connected to +5 V, the PM6675S sets the switching section output
voltage to 1.5 V without the need of an external divider.
Applications requiring different output voltages can be managed by PM6675S simply setting
the adjustable mode. Consider that if the VSEL pin voltage is higher than 4 V, the fixed
output mode is selected. When connecting an external divider to the VSEL pin, it is used as
negative input of the error amplifier and the output voltage is given by expression (20).
Equation 20
9R8R
+
6.0VOUT
ADJ
⋅=
8R
The output voltage can be set in the range from 0.6 V to 3.3 V.
The NOSKIP is the power saving algorithm selector: if tied to +5 V, the forced-PWM (fixed
frequency) control is performed. If grounded or connected to VREF pin (1.237 V reference
voltage), the Pulse-Skip or Non-Audible Pulse-Skip Modes are respectively selected.
30/53
PM6675S Device description
Table 8. Mode-of-operation settings summary
VSEL NOSKIP VOUT Operating mode
V
VSEL
> 4.3 V
V
1V <V
NOSKIP
NOSKIP
> 4.2 V
< 3.5 V Non-audible pulse-skip
< 0.5 V Pulse-skip
V
VSEL
< 3.7 V
V
1V <V
V
> 4.2 V
NOSKIP
< 3.5 V Non-audible pulse-skip
NOSKIP
< 0.5 V Pulse-skip
NOSKIP
7.1.5 Current sensing and current limit
The PM6675S switching controller uses a valley current sensing algorithm to properly
handle the current limit protection and the inductor current zero-crossing information. The
current is detected during the conduction time of the low-side MOSFET. The current sensing
element is the on-resistance of the low-side switch. The sensing scheme is visible in
Figure 40.
Figure 40. Current sensing scheme
PM6675S
PM6675
PM6675
HGATE
HGATE
PHASE
PHASE
CSNS
CSNS
LGATE
LGATE
100µA·
100µA·
Forced-PWM
1.5 V
Forced-PWM
ADJ
V
V
IN
IN
V
V
OUT
OUT
R
R
ILIM
ILIM
I
·
R
I
·
R
VALLEY
DSon
VALLEY
DSon
PGND
PGND
An internal 100 µA current source is connected to C
pin that is also the non-inverting
SNS
input of the positive current limit comparator. When the voltage drop developed across the
sensing parameter equals the voltage drop across the programming resistor R
ILIM
, the
controller skips subsequent cycles until the overcurrent condition is detected or the output
UV protection latches off the device (see
protections on page 34
Referring to
Figure 40, the R
).
DS(on)
Section 7.1.11: Switching section OV and UV
sensing technique allows high efficiency performance
without the need for an external sensing resistor. The on-resistance of the MOSFET is
affected by temperature drift and nominal value spread of the parameter itself; this must be
considered during the R
setting resistor design.
ILIM
31/53
Device description PM6675S
It must be taken into account that the current limit circuit actually regulates the inductor
valley current. This means that R
must be calculated to set a limit threshold given by the
ILIM
maximum DC output current plus half of the inductor ripple current:
Equation 21
R
ILIM
CL
A100I ⋅µ=
R
DSon
The PM6675S provides also a fixed negative current limit to prevent excessive reverse
inductor current when the switching section sinks current from the load in forced-PWM (3
quadrant working conditions). This negative current limit threshold is measured between
PHASE and PGND pins, comparing the drop magnitude on PHASE pin with an internal
110 mV fixed threshold.
7.1.6 POR, UVLO and soft-start
The PM6675S automatically performs an internal startup sequence during the rising phase
of the analog supply of the device (AVCC). The switching controller remains in a stand-by
state until AVCC crosses the upper UVLO threshold (4.25 V typ.), keeping active the internal
discharge MOSFETs (only if AVCC > 1V).
The soft-start allows a gradual increase of the internal current limit threshold during startup
reducing the input/output surge currents. At the beginning of start-up, the PM6675S current
limit is set to 25 % of nominal value and the Under Voltage Protection is disabled. Then, the
current limit threshold is sequentially brought to 100 % in four steps of approximately 750 µs
(
Figure 41).
Figure 41. Soft-start waveforms
Switching output
rd
Current limit threshold
SWEN
Time
After a fixed 3ms total time, the soft-start finishes and UVP is released: if the output voltage
doesn't reach the under voltage threshold within soft-start duration, the UVP condition is
detected and the device performs a soft-end and latches off. Depending on the load
conditions, the inductor current may or may not reach the nominal value of the current limit
during the soft-start (
32/53
Figure 42 shows two examples).
PM6675S Device description
Figure 42. Soft-start at heavy load (a) and short-circuit (b) conditions, Pulse-Skip enabled
(a)
7.1.7 Switching section power good signal
The SPG pin is an open drain output used to monitor output voltage through VSNS (in fixed
output voltage mode) or VSEL (in adjustable output voltage mode) pins and is enabled after
the soft-start timer has expired. The SPG signal is held low if the output voltage drops 10%
below or rises 10 % above the nominal regulated value. The SPG output can sink current up
to 4 mA.
7.1.8 Switching section output discharge
Active soft-end of the output occurs when the SWEN (SWitching ENable) is forced low.
When the switching section is turned off, an internal 25 Ω resistor discharges the output
through the VSNS pin.
Figure 43. Switching section soft-end
VOUT
Resistive Discharge
SWEN
(b)
33/53
Device description PM6675S
7.1.9 Gate drivers
The integrated high-current gate drivers allow using different power MOSFETs. The highside driver uses a bootstrap circuit which is supplied by the +5 V rail. The BOOT and
PHASE pins work respectively as supply and return path for the high-side driver, while the
low-side driver is directly fed through VCC and PGND pins.
An important feature of the PM6675S gate drivers is the Adaptive Anti-Cross-Conduction
circuitry, which prevents high-side and low-side MOSFETs from being turned on at the same
time. When the high-side MOSFET is turned off, the voltage at the PHASE node begins to
fall. The low-side MOSFET is turned on only when the voltage at the PHASE node reaches
an internal threshold (2.5 V typ.). Similarly, when the low-side MOSFET is turned off, the
high-side one remains off until the LGATE pin voltage is above 1 V.
The power dissipation of the drivers is a function of the total gate charge of the external
power MOSFETs and the switching frequency, as shown in the following equation:
Equation 22
fQV)driver(P ⋅⋅=
SWgDRVD
The low-side driver has been designed to have a low-resistance pull-down transistor
(0.6 Ω typ.) in order to prevent undesired start-up of the low-side MOSFET due to the Miller
effect.
7.1.10 Reference voltage and bandgap
The 1.237 V internal bandgap reference has a granted accuracy of ±1 % over the 0 °C to
85 °C temperature range. The VREF pin is a buffered replica of the bandgap voltage. It can
supply up to ±100 µA and is suitable to set the intermediate level of NOSKIP multifunction
pin. A 100 nF (min.) bypass capacitor toward SGND is required to enhance noise rejection.
If VREF falls below 0.8 V (typ.), the system detects a fault condition and all the circuitry is
turned off.
An internal divider derives a 0.6 V ± 1 % voltage (Vr) from the bandgap. This voltage is used
as reference for both the switching and the linear sections. The Over-Voltage Protection, the
Under-Voltage Protection and the power-good signals are also referred to Vr.
7.1.11 Switching section OV and UV protections
When the switching output voltage is about 115 % of its nominal value, a latched OverVoltage Protection (OVP) occurs. In this case the synchronous rectifier immediately turns on
while the high-side MOSFET turns off. The output capacitor is rapidly discharged and the
load is preserved from being damaged. The OVP is also active during the soft-start. Once
an OVP has taken part, a toggle on SWEN pin or a Power-On-Reset is necessary to exit
from the latched state.
When the switching output voltage is below 70 % of its nominal value, a latched UnderVoltage Protection occurs. This event causes the switching section to be immediately
disabled and both switches to be opened. The controller performs a soft-end and the output
is eventually kept to ground, turning the low side MOSFET on when the voltage is lower than
400 mV.
The Under-Voltage Protection circuit is enabled only at the end of the soft-start. Once an
UVP has taken part, a toggle on SWEN pin or a Power-On-Reset is necessary to clear the
fault state and restart the section.
34/53
PM6675S Device description
7.1.12 Device thermal protection
The internal control circuitry of the PM6675S self-monitors the junction temperature and
turns all outputs off when the 150 °C limit has been overrun. This event causes the switching
section to be immediately disabled and both switches to be opened. The controller performs
a soft-end and both the outputs are eventually kept to ground, then the low side MOSFET is
turned on when the voltage of the switching section is lower than 400 mV.
The thermal fault is a latched protection and, in normal operating conditions it is restored by
a Power-On Reset or toggling SWEN and LEN pins at the same time.
Table 9. Switching section OV, UV and OT Faults management
Fault Conditions Action
Over voltage
Under voltage
Junction over
temperature
VOUT > 115 % of the
nominal value
VOUT < 70 % of the
nominal value
> +150 °C
T
J
7.2 LDO linear regulator section
The independent Low-Drop-Out (LDO) linear regulator has been designed to sink and
source up to 2 A peak current and 1 A continuously. The LDO output voltage can be
adjusted in the range 0.6 V to 3.3 V simply connecting a resistor divider as shown in
Figure 44.
Equation 23
ADJ
LGATE pin is forced high and the device latches off.
Exit by a Power-On Reset or toggling SWEN
LGATE pin is forced high after the soft-end, then the
device latches off. Exit by a Power-On Reset or
toggling SWEN.
LGATE pin is forced high after the soft-end, then the
device latches off. Exit by a Power-On Reset or
toggling SWEN and LEN after 15°C temperature
drop.
20R19R
6.0VLDO
+
⋅=
20R
Figure 44. LDO output voltage selection
V
LOUT
Cc
C
OUT
R20
35/53
R19
PM6675
PM6675S
LOUT
LFB
LGND
Device description PM6675S
A compensation capacitor Cc must be added to adjust the dynamic response of the loop.
The value of Cc is calculated according to the desired bandwidth of the LDO regulator and
depends on the value of the feedback resistors. In most of applications the pole due to the
compensation capacitor is placed at 100-200 kHz (equation 24).
Equation 24
f
p
The LIN input can be connected to the switching section output for compact solutions or to a
lower supply, if available in the system, in order to reduce the power dissipation of the LDO.
A minimum output capacitance of 20 µF (2x10 µF MLCC capacitors) is enough to assure
stability and fast load transient response.
7.2.1 LDO section current limit
The LDO regulator can handle up to ±2 Apk, depending on the LDO input voltage and the
LILIM pin setting. The output current is limited to ±1 A or ±2 A if the LILIM pin is connected
to SGND or AVCC respectively (
Figure 45. LDO current limit setting
±2A CL
±1A CL
=
Figure 45).
+5V
1
C)20R19R(2
⋅⊕π
C
PM6675
PM6675S
LILIM
kHz200
=
The maximum current that the LDO can source depends also on the input and output
voltages. Due to the high side MOSFET of the output stage, the LDO cannot source the limit
current at high output voltages. In
Figure 46 it is shown the maximum current that the LDO
can source as function of the input and output voltages. For output voltages higher than 2 V,
the maximum output current is limited as reported.
36/53
PM6675S Device description
Figure 46. Maximum LDO source able output current vs input voltage
2.2
2.0
1.8
1.6
1.4
1.2
1.0
ILOUT [A]
0.8
0.6
0.4
0.2
0.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
VOUT=1.05V
VOUT=1.2V
VOUT=1.5V
VOUT=1.8V
VOUT=2.0V
VOUT=2.2V
VOUT=2.5V
VOUT=3.3V
VLIN [V]
7.2.2 LDO section soft-start
The LDO section soft-start is performed by clamping the current limit. During startup, the
LDO current limit voltage is set to 1A and the output voltage increases linearly. When the
output voltage rises above 90 % of the nominal value, the current limit is released to 2 A
according to the LILIM pin setting. At the end of the ramp-up phase of the soft-start, the LPG
signal is masked for about 100 µs in order to ignore dynamic overshoot on the feedback pin.
7.2.3 LDO section power good signal
The LPG pin is an open drain output used to monitor the LDO output voltage through LFB
pin.
The LPG signal is held low if the output voltage drops 10 % below or rises 10 % above the
nominal regulated value. The LPG output can sink current up to 4 mA.
7.2.4 LDO section output discharge
Active soft-end of the LDO output occurs when the LEN (Linear ENable) is forced low. When
the LDO section is turned off, an internal 25 Ω resistor, directly connected to the LOUT pin,
discharges the output.
Figure 47. LDO section soft-end
VLDO
Resistive Discharge
LEN
37/53
Application information PM6675S
8 Application information
The purpose of this chapter is showing the design procedure of the switching section.
The design starts from three main specifications:
● The input voltage range, provided by the battery or the external supply. The two
extreme values (V
● The maximum load current, indicated with I
● The maximum allowed output voltage ripple V
It's also possible that specific designs should involve other specifications.
The following paragraphs will guide the user into a step-by-step design.
8.1 External components selection
The PM6675S uses a pseudo-fixed frequency, Constant On-Time (COT) controller as the
core of the switching section. The switching frequency can be set by connecting an external
divider to the VOSC pin. The voltage seen at this pin must be greater than 0.8V and lower
than 2 V in order to ensure system linearity.
INMAX
and V
) are important for the design.
INmin
LOAD,MAX
RIPPLE,MAX
.
.
Nearly constant switching frequency is achieved by the system loop in steady-state
operating conditions by varying the On-Time duration, avoiding thus the need for a clock
generator. The On-Time one shot duration is directly proportional to the output voltage,
sensed at VSNS pin, and inversely proportional to the input voltage, sensed at the VOSC
pin, as follows:
Equation 25
V
SNS
OSCON
V
τ+=
OSC
where K
KT
is a constant value (130 ns typ.) and τ is the internal propagation delay
OSC
(40 ns typ.).
The duty cycle of the buck converter is, in under steady state conditions, given by
Equation 26
V
OUT
D =
V
IN
The switching frequency is thus calculated as
Equation 27
V
OUT
D
f ⋅
SW
38/53
==
T
ON
V
IN
V
OSC
SNS
⋅
V
OSC
K
α
OSC
=
α
1
K
OSCOUT
PM6675S Application information
where
Equation 28a
V
OSC
=α
OSC
V
IN
Equation 28b
V
SNS
=α
OUT
V
OUT
Referring to the typical application schematic (figure in cover page and Figure 33), the final
expression is then:
Equation 29
α
f ⋅
SW
OSC
=
K
OSC
R
2
=
+
The switching frequency directly affects two parameters:
● Inductor size: greater frequencies mean smaller inductances. In notebook applications,
real estate solutions (i.e. low-profile power inductors) are mandatory also with high
saturation and r.m.s. currents.
● Efficiency: switching losses are proportional to the frequency. Generally, higher
frequencies imply lower efficiency.
Even if the switching frequency is theoretically independent from battery and output
voltages, parasitic parameters involved in power path (like MOSFETs on-resistance and
inductor DCR) introduce voltage drops responsible for a slight dependence on load current.
In addition, the internal delay is cause of a light dependence from input voltage.
Table 10. Typical values for switching frequency selection
R1 (kΩ)R2 (kΩ) Approx switching frequency (kHz)
330 11 250
330 13 300
330 15 350
330 18 400
1
K
RR
OSC21
330 20 450
330 22 500
39/53
Application information PM6675S
8.1.1 Inductor selection
Once the switching frequency has been defined, the inductance value depends on the
desired inductor ripple current. Low inductance value means great ripple current that brings
poor efficiency and great output noise. On the other hand a great current ripple is desirable
for fast transient response when a load step is applied.
High inductance brings to good efficiency but the transient response is critical, especially if
- V
V
INmin
system stability and jitter-free operations (see
page 42
must be taken in consideration. A good trade-off between the transient response time, the
efficiency, the cost and the size is choosing the inductance value in order to maintain the
inductor ripple current between 20 % and 50 % (usually 40 %) of the maximum output
current.
is little. Moreover a minimum output ripple voltage is necessary to assure
OUT
Section 8.1.3: Output capacitor selection on
). The product of the output capacitor ESR multiplied by the inductor ripple current
The maximum inductor ripple current, ∆I
, occurs at the maximum input voltage.
L,MAX
Given these considerations, the inductance value can be calculated using the following
expression:
Equation 30
L ⋅
−
=
∆⋅
where fSW is the switching frequency, VIN is the input voltage, V
is the inductor ripple current.
∆I
L
OUT
OUTIN
V
Ifsw
IN
L
is the output voltage and
OUT
V
VV
Once the inductor value is determined, the inductor ripple current is then recalculated:
Equation 31
VV
I ⋅
=∆
MAX,L
−
Lfsw
⋅
V
OUTMAX,IN
OUT
V
MAX,IN
The next step is the calculation of the maximum r.m.s. inductor current:
Equation 32
2
MAX,L
12
)I(
∆
2
)I(I
+=
MAX,LOADRMS,L
The inductor must have an r.m.s. current greater than I
in order to assure thermal
L,RMS
stability.
Then the calculation of the maximum inductor peak current follows:
Equation 33
I
∆
II
MAX,LOADPEAK,L
I
40/53
is important when choosing the inductor, in term of its saturation current.
L,PEAK
MAX,L
+=
2
PM6675S Application information
The saturation current of the inductor should be greater than I
hard saturation core inductors. Using soft-ferrite cores is possible (but not advisable) to push
the inductor working near its saturation current.
Ta bl e 1 1 some inductors suitable for notebook applications are listed.
In
Table 11. Evaluated inductors (@fsw = 400 kHz)
Manufacturer Series Inductance (µH)
COILCRAFT MLC1538-102 1 13.4 21.0
COILCRAFT MLC1240-901 0.9 12.4 24.5
COILCRAFT MVR1261C-112 1.1 20 20
WURTH 7443552100 1 16 20
COILTRONICS HC8-1R2 1.2 16.0 25.4
In Pulse-Skip Mode, low inductance values produce a better efficiency versus load curve,
while higher values result in higher full-load efficiency because of the smaller current ripple.
8.1.2 Input capacitor selection
In a buck topology converter the current that flows through the input capacitor is pulsed and
with zero average value. The RMS input current can be calculated as follows:
L,PEAK
+40 °C RMS
current (A)
as well as for case of
-30 % saturation
current (A)
Equation 34
Cin
RMS
LOAD
2
1
)D1(DII ∆⋅+−⋅⋅=
12
2
)I(D
L
Neglecting the second term, the equation 10 is reduced to:
Equation 35
)D1(DII
Cin
RMS
LOAD
−⋅=
The losses due to the input capacitor are thus maximized when the duty-cycle is 0.5:
Equation 36
CinRMSCinloss
2
LOADCin
The input capacitor should be selected with a RMS rated current higher than I
2
(max))I5.0(ESR(max)IESRP ⋅⋅=⋅=
CINRMS
(max).
Tantalum capacitors are good in terms of low ESR and small size, but they occasionally can
burn out if subjected to very high current during operation. Multi-Layers-Ceramic-Capacitors
(MLCC) have usually a higher RMS current rating with smaller size and they remain the best
choice. The drawback is their quite high cost.
41/53
Application information PM6675S
It must be taken into account that in some MLCC the capacitance decreases when the
operating voltage is near the rated voltage. In
Ta bl e 1 2 some MLCC suitable for most of
applications are listed.
Table 12. Evaluated MLCC for input filtering
Manufacturer Series Capacitance (µF) Rated voltage (V)
TAIYO YUDEN UMK325BJ106KM-T 10 50 2
TAIYO YUDEN GMK316F106ZL-T 10 35 2.2
TAIYO YUDEN GMK325F106ZH-T 10 35 2.2
TAIYO YUDEN GMK325BJ106KN 10 35 2.5
TDK C3225X5R1E106M 10 25
8.1.3 Output capacitor selection
Using tantalum or electrolytic capacitors, the selection is made referring to ESR and voltage
rating rather than by a specific capacitance value.
The output capacitor has to satisfy the output voltage ripple requirements. At a given
switching frequency, small inductor values are useful to reduce the size of the choke but
increase the inductor current ripple. Thus, to reduce the output voltage ripple a low ESR
capacitor is required.
To reduce jitter noise between different switching regulators in the system, it is preferable to
work with an output voltage ripple greater than 25 mV.
Concerning the load transient requirements, the Equivalent Series Resistance (ESR) of the
output capacitor must satisfy the following relationship:
Maximum Irms
@100 kHz (A)
Equation 37
where V
ESR∆≤
is the maximum tolerable ripple voltage.
RIPPLE
V
MAX,RIPPLE
I
MAX,L
In addition, the ESR must be high enough to meet stability requirements. The output
capacitor zero must be lower than the switching frequency:
Equation 38
ff
=>
ZSW
42/53
1
CESR2
⋅⋅π
out
PM6675S Application information
⋅
If ceramic capacitors are used, the output voltage ripple due to inductor current ripple is
negligible. Then the inductance should be smaller, reducing the size of the choke. In this
case it is important that output capacitor can adsorb the inductor energy without generating
an over-voltage condition when the system changes from a full load to a no load condition.
The minimum output capacitance can be chosen by the following equation:
Equation 39
where Vf is the output capacitor voltage after the load transient, while Vi is the output
capacitor voltage before the load transient.
Ta bl e 1 3 are listed some tested polymer capacitors.
In
Table 13. Evaluated output capacitors
Manufacturer Series
4TPE220MF 220 4 V 15 to 25
SANYO
HITACHI TNCB OE227MTRYF 220 2.5 V 25
4TPE150MI 220 4 V 18
4TPC220M 220 4 V 40
8.1.4 MOSFETs selection
In a notebook application, power management efficiency is a high level requirement.
The power dissipation on the power switches becomes an important factor in the selection
of switches. Losses of high-side and low-side MOSFETs depend on their working condition.
C
IL
=
min,OUT
Capacitance
(µF)
2
MAX,LOAD
22
ViVf
−
Rated voltage
(V)
ESR max @100 kHz
(mΩ)
Considering the high-side MOSFET, the power dissipation is calculated as:
Equation 40
PPP +=
switchingconductionDHighSide
Maximum conduction losses are approximately given by:
Equation 41
V
OUT
RP ⋅⋅=
DSonconduction
V
43/53
I
min.IN
2
MAX,LOAD
Application information PM6675S
∆
≅
−
=
where R
is the drain-source on-resistance of the control MOSFET.
DS(on)
Switching losses are approximately given by:
Equation 42
∆
I
L
⋅⋅
ft)
where t
P
switching
ON
and t
=
LOADIN
are the turn-on and turn-off times of the MOSFET and depend on the
OFF
2
2
−⋅
(max)I(V
gate-driver current capability and the gate charge Q
low R
. Unfortunately low R
DSon
As general rule, the R
DS(on)
x Q
MOSFETs have a great gate charge.
DSon
product should be minimized to find the suitable
gate
(max)I(V
LOADINswon
+
. A greater efficiency is achieved with
gate
I
L
+⋅
2
⋅⋅
ft)
swoff
2
MOSFET.
Logic-level MOSFETs are recommended, as long as low-side and high-side gate drivers are
powered by V
= +5 V. The breakdown voltage of the MOSFETs (V
VCC
greater than the maximum input voltage V
INmax
.
BRDSS
) must be
Below some tested high-side MOSFETs are listed.
Table 14. Evaluated high-side MOSFETs
Manufacturer Type
R
DS(on)
(mΩ)
Gate charge
(nC)
Rated reverse
voltage (V)
ST STS12NH3LL 10.5 12 30
IR IRF7811 9 18 30
In buck converters the power dissipation of the synchronous MOSFET is mainly due to
conduction losses:
Equation 43
PP
conductionDLowSide
Maximum conduction losses occur at the maximum input voltage:
Equation 44
V
⎞
OUT
⎟
I
⎟
MAX,IN
⎠
as possible. When the high-side
DS(on)
2
MAX,LOAD
⎛
⎜
1RP ⋅
DSonconduction
−⋅=
⎜
V
⎝
The synchronous rectifier should have the lowest R
MOSFET turns on, high d
through its gate-drain capacitance C
of the phase node can bring up even the low-side gate
V/dt
, causing a cross-conduction problem. Once again,
RRS
the choice of the low-side MOSFET is a trade-off between on resistance and gate charge; a
/ C
good selection should minimizes the ratio C
RSS
GS
where
Equation 45
CCC
RSSISSGS
Below some tested low-side MOSFETs are listed.
44/53
PM6675S Application information
Table 15. Evaluated low-side MOSFETs
Manufacturer Type R
ST STS12NH3LL 13.5 0.069 30
ST STS25NH3LL 4.0 0.011 30
IR IRF7811 24 0.054 30
Dual N-MOS can be used in applications with lower output current.
Ta bl e 1 6 shows some suitable dual MOSFETs for applications requiring about 3 A.
Table 16. Suitable dual MOSFETs
Manufacturer Type R
ST STS8DNH3LL 25 10 30
IR IRF7313 46 33 30
8.1.5 Diode selection
A rectifier across the synchronous switch is recommended. The rectifier works as a voltage
clamp across the synchronous rectifier and reduces the negative inductor swing during the
dead time between turning the high-side MOSFET off and the synchronous rectifier on.
Moreover it increases the efficiency of the system.
Choose a schottky diode as long as its forward voltage drop is very little (0.3 V). The reverse
voltage should be greater than the maximum input voltage V
reverse charge is preferable.
(mΩ) CGD \ C
DS(on)
(mΩ) Gate charge (nC) Rated reverse voltage (V)
DSon
GS
Rated reverse voltage (V)
and a minimum recovery
INmax
Ta bl e 1 7 shows some evaluated diodes.
Table 17. Evaluated recirculation rectifiers
Manufacturer Type
ST STPS1L30M 0.34 30 0.00039
ST STPS1L30A 0.34 30 0.00039
Forward
voltage (V)
45/53
Rated reverse
voltage (V)
Reverse current (µA)
Application information PM6675S
⋅
8.1.6 VOUT current limit setting
The valley current limit is set by R
current. The valley of the inductor current I
and must be chosen to support the maximum load
CSNS
Lvalley
is:
Equation 46
LOADLvalley
2
∆
I
L
−=
(max)II
The output current limit depends on the current ripple as shown in Figure 48:
Figure 48. Valley current limit waveforms
Current
Inductor current
MAX LOAD 1
Valley current limit
MAX LOAD 2
Inductor current
Time
As the valley threshold is fixed, the greater the current ripple, the greater the DC output
current will be. If an output current limit greater than I
(max) over all the input voltage
LOAD
range is required, the minimum current ripple must be considered in the previous formula.
Then the resistor R
CSNS
is:
Equation 47
IR
CSNS
=
where R
R
is the drain-source on-resistance of the low-side switch. Consider the
DSon
temperature effect and the worst case value in R
LvalleyDSon
uA100
calculation (typically +0.4 % / °C).
DSon
The accuracy of the valley current also depends on the offset of the internal comparator (±5
mV).
The negative valley-current limit (if the device works in forced-PWM mode) is given by:
Equation 48
I =
NEG
R
mV110
DSon
46/53
PM6675S Application information
8.1.7 All ceramic capacitors application
Design of external feedback network depends on the output voltage ripple across the output
capacitors ESR. If the ripple is great enough (at least 20 mV), the compensation network
simply consists of a C
Figure 49. Integrative compensation
COMP
capacitor.
INT
V
Vr=0.9
V
REF
Ton One-shot
generator
+
PWM
Comparator
-
g
Integrator
VSNS
VOUT
+
m
0.6V
-
VREF
C
FILT
R
INT
C
INT
The stability of the system firstly depends on the output capacitor zero frequency. It must be
verified that:
Equation 49
fkf
=⋅>
ZoutSW
k
⋅π
CR2
outout
where k is a free design parameter greater than unity (k > 3) . It determines the minimum
integrator capacitor value C
INT
:
Equation 50
g
>
C
INT
2
m
f
⎛
SW
−⋅π
⎜
⎝
f
k
Zout
Vref
⋅
Vo
⎞
⎟
⎠
If the ripple on the COMP pin is greater than the integrator output dynamic (150 mV), an
additional capacitor C
could be added in order to reduce its amplitude. If q is the desired
filt
attenuation factor of the output ripple, select:
47/53
Application information PM6675S
Equation 51
)q1(C
−⋅
INT
=
C
filt
q
In order to reduce noise on the COMP pin, it's possible to introduce a resistor R
together with C
INT
and C
, becomes a low pass filter. The cutoff frequency f
filt
CUT
that,
INT
must be
much greater (10 or more times) than the switching frequency:
Equation 52
1
CC
⋅
f2
⋅π
CUT
FILTINT
CC
+
FILTINT
For most applications both R
INT
R
INT
and C
=
are unnecessary.
filt
If the ripple is very small (e.g. such as with ceramic capacitors), a further compensation
network, called "Virtual ESR" network, is needed. This additional part generates a triangular
ripple that substitutes the ESR output voltage ripple. The complete compensation scheme is
represented in
Figure 50.
Figure 50. Virtual ESR network
L
R R1
Ton
Generation
Block
Select C as shown:
Equation 53
PWM Comparator
+
-
Vr
C
INT
VOUT
C
R
INT
+
g
m
-
0.6V
C
V
REF
FILT
Integrator
C5C⋅>
INT
1.237V
48/53
PM6675S Application information
Then calculate R in order to have enough ripple voltage on the integrator input:
Equation 54
L
=
VESR
CR
⋅
Where R
R
is the new virtual output capacitor ESR. A good trade-off is to consider an
VESR
equivalent ESR of 30-50 mΩ , even though the choice depends on inductor current ripple.
Then choose R1 as follows:
Equation 55
⎛
⎜
R
⋅
⎜
⎝
1R
=
R
−
⎞
1
⎟
⎟
Cf
⋅⋅π
Z
⎠
1
Cf
⋅⋅π
Z
49/53
Package mechanical data PM6675S
9 Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect. The category of
second Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com.
Table 18. VFQFPN-24 4 mm x 4 mm mechanical data
mm.
Dim.
Min Typ Max
A 0.80 0.90 1.00
A1 0.0 0.05
A2 0.65 0.80
D 4.00
D1 3.75
E4.00
E1 3.75
θ
P 0.240.420.60
e0.50
N 24.00
Nd 6.00
Ne 6.00
L 0.300.400.50
b 0.18 0.30
D2 1.95 2.10 2.25
E2 1.95 2.10 2.25
12°
50/53
PM6675S Package mechanical data
Figure 51. Package dimensions
51/53
Revision history PM6675S
10 Revision history
Table 19. Document revision history
Date Revision Changes
14-Feb-2008 1 Initial release
52/53
PM6675S
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