ST PM6675AS User Manual

Features

■ Switching section

– 4.5 V to 36 V input voltage range
– 0.6 V, ±1 % voltage reference
– Selectable 1.5 V fixed output voltage
– Adjustable 0.6 V to 3.3 V output voltage
– 1.237 V ±1 % reference voltage available
– Very fast load transient response using

constant-on-time control loop

–No R

MOSFETs' R
– Negative current limit
– Latched OVP and UVP
– Soft-start internally fixed at 3 ms
– Selectable pulse skipping at light load
– Selectable No-audible (33 kHz) pulse skip

mode
– Ceramic output capacitors supported
– Output voltage ripple compensation
– Output soft-end

■ LDO regulator section

– Adjustable 0.6 V to 3.3 V output voltage
– Selectable ±1 Apk or ±2 Apk current limit
– Dedicated power-good signal
– Ceramic output capacitors supported
– Output soft-end

current sensing using low side

SENSE

DS(ON)

Applications

PM6675AS

High efficiency step-down controller

with embedded 2 A LDO regulator

VFQFPN-24 4x4

Description

The PM6675AS device consists of a single high
efficiency step-down controller and an
independent low drop-out (LDO) linear regulator.

The constant on-time (COT) architecture assures
fast transient response supporting both
electrolytic and ceramic output capacitors. An
embedded integrator control loop compensates
the DC voltage error due to the output ripple.

Selectable low-consumption mode allows the
highest efficiency over a wide range of load
conditions. The low-noise mode sets the minimum
switching frequency to 33 kHz for audio-sensitive
applications. The LDO linear regulator can sink
and source up to 2 Apk. Two fixed current limit
(±1 A- ±2 A) can be chosen.

An active soft-end is independently performed on
both the switching and the linear regulators
outputs when disabled.

■ Industrial application on 24 V

■ Graphic cards

■ Embedded computer systems

Table 1. Device summary

Order codes Package Packaging

PM6675AS

VFQFPN-24 4x4 (exposed pad)

PM6675ASTR Tape and reel

February 2008 Rev 1 1/48

Tu b e

www.st.com

Contents PM6675AS

Contents

1 Typical application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.1 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

3 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3.1 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3.3 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

6 Typical operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

7 Device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

7.1 Switching section - constant on-time pwm controller . . . . . . . . . . . . . . . . 16

7.1.1 Constant-on-time architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

7.1.2 Output ripple compensation and loop stability . . . . . . . . . . . . . . . . . . . . 19

7.1.3 Pulse-skip and no-audible pulse-skip modes . . . . . . . . . . . . . . . . . . . . . 24

7.1.4 Mode-of-operation selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

7.1.5 Current sensing and current limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

7.1.6 POR, UVLO and soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

7.1.7 Switching section power-good signal . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

7.1.8 Switching section output discharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

7.1.9 Gate drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

7.1.10 Reference voltage and bandgap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

7.1.11 Switching section OV and UV protections . . . . . . . . . . . . . . . . . . . . . . . 30

2/48

PM6675AS Contents

7.1.12 Device thermal protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

7.2 LDO linear regulator section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

7.2.1 LDO section current limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

7.2.2 LDO section soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

7.2.3 LDO section power-good signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

7.2.4 LDO section output discharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

8 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

8.1 External components selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

8.1.1 Inductor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

8.1.2 Input capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

8.1.3 Output capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

8.1.4 MOSFETs selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

8.1.5 Diode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

8.1.6 VOUT current limit setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

8.1.7 All ceramic capacitors application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

9 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

3/48

Typical application circuit PM6675AS

1 Typical application circuit

Figure 1. Application circuit

V

LDOIN

V

LDOIN

LDO PG

LDO PG

V

LDO

V

LDO

10

10

VSEL

C

C

IN4

IN4CIN4

C

C

OUT2

OUT2COUT2

23

23

4

4

24

24

2

2

1

1

VSEL

LIN

LIN

LPG

LPG

LOUT

LOUT

LFB

LFB

LGND

LGND

SMPS PG

SMPS PG

R

RLPR

LP

LP

C

C

IN3

IN3CIN3

312618822

312618822

VCC

LILIM

LILIM

NOSKIP

NOSKIP

PM6675AS

PM6675A

PM6675A

SPG

SPG

SGND

SGND

5151413 711

5151413 711

VCC

AVCC

AVCC

LEN

LEN

SWEN

SWEN

C

C

B

B
O

O
O

O

VOSC

VOSC

HGATE

HGATE

T

T

PHASE

PHASE

LGATE

LGATE

VREF

VREF

COMP

COMP

C

C

BYP

BYPCBYP

IN2

IN2

CSNS

CSNS

PGND

PGND

VSNS

VSNS

21

21

20

20

17

17

19

19

16

16

9

9

+5V

+5V

C

C

BOOT

BOOT

V

IN

V

IN

R

R

1

1

C

CINC

IN

R

R

2

2

R

R

LIM

LIMRLIM

IN

L

L

V

SMPS

V

SMPS

C

C

OUT

OUTCOUT

C

C

INT

INTCINT

4/48

PM6675AS Pin settings

2 Pin settings

2.1 Connections

Figure 2. Pin connection (through top view)

LOUT

LOUT

LOUT

LOUT

LIN

LIN

LIN

LGND

LGND

LGND

LFB

LFB

LFB

NOSKIP

NOSKIP

NOSKIP

LPG

LPG

LPG

LIN

24

24

24

24

1

1

1

1

PM6675AS

PM6675A

PM6675A

PM6675A

PM6675A

BOOT

BOOT

BOOT

BOOT

HGATE

HGATE

HGATE

PHASE

PHASE

PHASE

CSNS

CSNS

CSNS

CSNS

19

19

19

19

18

18

18

18

VCC

VCC

VCC

LGATE

LGATE

LGATE

PGND

PGND

PGND

SPG

SPG

SPG

SGND

SGND

SGND

AVCC

AVCC

AVCC

LEN

LEN

LEN

SWEN

SWEN

SWEN

6

6

6

6

712

712

712

712

VSEL

VSEL

VREF

VREF

VREF

VREF

VOSC

VOSC

VOSC

VOSC

VSNS

VSNS

VSNS

VSNS

VSEL

COMP

COMP

COMP

COMP

LILIM

LILIM

LILIM

LILIM

13

13

13

13

5/48

Pin settings PM6675AS

2.2 Pin description

Table 2. Pin functions

N° Pin Function

1 LGND LDO power ground. Connect to negative terminal of VTT output capacitor.

2LFB

3NOSKIP

4LPG

5SGND

LDO remote sensing. Connect as close as possible to the load via a low
noise PCB trace.

Pulse-skip/no-audible pulse-skip modes selector.
See Section 7.1.4: Mode-of-operation selection

LDO section power-good signal (open drain output). High when LDO output
voltage is within ±10 % of nominal value.

Ground Reference for analog circuitry, control logic and VTTREF buffer.
Connect together with the thermal pad and VTTGND to a low impedance
ground plane. See the Application Note for details.

6AVCC

7VREF

8VOSC

9 VSNS

10 VSEL

11 COMP

12 LILIM

13 SWEN

14 LEN

15 SPG

+5 V supply for internal logic. Connect to +5 V rail through a simple RC
filtering network.

High accuracy output voltage reference (1.237 V) for multilevel pins setting.
It can deliver up to 50 uA. Connect a 100 nF capacitor between VREF and
SGND in order to enhance noise rejection.

Frequency Selection. Connect to the central tap of a resistor divider to set
the desired switching frequency. The pin cannot be left floating. See

Section 7: Device description for details.

Switching section output remote sensing and discharge path during output
soft-end. Connect as close as possible to the load via a low noise PCB
trace.

Fixed output selector and feedback input for the switching controller.
If VSEL pin voltage is higher than 4 V, the fixed 1.5 V output is selected. If

VSEL pin voltage is lower than 4 V, it is used as negative input of the error
amplifier. See Section 7.1.4: Mode-of-operation selection for details.

DC voltage error compensation input pin for the switching section.
Refer to Mode of Operation Selection section for more details.

Current limit selector for the LDO. Connect to SGND for ±1 A current limit or
to +5 V for ±2 A current limit.

Switching Controller Enable. When tied to ground, the switching output is
turned off and a soft-end is performed.

Linear Regulator Enable. When tied to ground, the LDO output is turned off
and a soft-end is performed.

Switching Section power-good signal (open drain output). High when the
switching regulator output voltage is within ±10 % of nominal value.

16 PGND Power ground for the switching section.

17 LGATE Low-side gate driver output.

18 VCC +5 V low-side gate driver supply. Bypass with a 100 nF capacitor to PGND.

6/48

PM6675AS Pin settings

Table 2. Pin functions (continued)

N° Pin Function

Current sense input for the switching section. This pin must be connected

19 CSNS

20 PHASE Switch node connection and return path for the high side gate driver.

21 HGATE High-Side Gate Driver Output

22 BOOT

through a resistor to the drain of the synchronous rectifier (RDSon sensing)
to set the current limit threshold.

Bootstrap capacitor connection. Input for the supply voltage of the high-side
gate driver.

23 LIN

24 LOUT

Linear Regulator Input. Bypass to LGND by a 10 µF ceramic capacitor for
noise rejection enhancement.

LDO linear regulator output. Bypass with a 20 µF (2x10 µF MLCC) filter
capacitor.

7/48

Electrical data PM6675AS

3 Electrical data

3.1 Maximum rating

Table 3. Absolute maximum ratings

(1)

Symbol Parameter Value Unit

V

AVC C

V

VCC

AVCC to SGND -0.3 to 6

VCC to SGND -0.3 to 6

PGND, LGND to SGND -0.3 to 0.3

HGATE and BOOT to PHASE -0.3 to 6

HGATE and BOOT to PGND -0.3 to 44

V

PHASE

P

TOT

1. Free air operating conditions unless otherwise specified. Stresses beyond those listed under "absolute
maximum ratings" may cause permanent damage to the device. Exposure to absolute maximum rated
conditions for extended periods may affect device reliability.

PHASE to SGND -0.3 to 38

LGATE to PGND -0.3 to V

CSNS, SPG, LEN, SWEN, LILIM, COMP, VSEL,
VSNS, VOSC, VREF, NOSKIP to SGND

-0.3 to V

LPG,VREF, LOUT, LFB to SGND -0.3 to V

LIN, LOUT, LPG, LIN to LGND -0.3 to V

VCC

AVC C

AVC C

AVC C

+0.3

+ 0.3

+ 0.3

+ 0.3

Power dissipation @TA = 25°C 2.3 W

V

3.2 Thermal data

Table 4. Thermal data

Symbol Parameter Value Unit

R

T

thJA

STG

A

T

J

Thermal resistance junction to ambient 42 °C/W

Storage temperature range -50 to 150

Operating ambient temperature range -40 to 85

Junction operating temperature range -40 to 125

3.3 Recommended operating conditions

Table 5. Recommended operating conditions

Symbol Parameter Min Typ Max Unit

VIN Input voltage range 4.5 36

VAVCC IC supply voltage 4.5 5.5

VVCC IC supply voltage 4.5 5.5

°CT

V

8/48

PM6675AS Electrical characteristics

4 Electrical characteristics

Table 6. Electrical characteristics

T

= - 25 °C to 85 °C , VCC = AVCC = +5 V, LIN = 1.5 V and LOUT= 0.6 V if not otherwise

A

specified

(1)

.

Symbol Parameter Test condition Min Typ Max Unit

Supply section

I

Operating current

IN

(Switching + LDO)

SWEN, LEN, VSEL and NOSKIP
connected to AVCC,

No load on LOUT

output

.

2

SWEN, VSEL and NOSKIP

I

SW

Operating current (switching)

connected to AVCC, LEN coneected

1

to SGND.

I

SHDN

UVLO

Shutdown operating current SWEN and LEN tied to SGND. 10 µA

AVCC Under Voltage Lockout
upper threshold

AVCC Under Voltage Lockout
lower threshold

4.1 4.25 4.4

3.85 4.0 4.1

UVLO hysteresis 70 mV

On-time (SMPS)

V

= 300 mV 530 630 730

OSC

V

= 500 mV 320 380 440

OSC

t

ON

On-time duration

VSEL low,
NOSKIP low,

VVSNS = 2 V

mA

V

ns

OFF-TIME (SMPS)

t

OFFMIN

Minimum Off-Time 300 350 ns

Volt a g e re f e r enc e

Voltage accuracy 4.5 V< V

Load regulation -50 µA < I

Undervoltage Lockout
Fault Threshold

SMPS output

V

OUT

SMPS fixed output voltage

Feedback output voltage
accuracy

< 36 V 1.224 1.237 1.249 V

IN

< 50 µA -4 4

VREF

800

1.5 V

VSEL connected to AVCC, NOSKIP
tied to SGND, No Load

-1.5 1.5 %

mV

9/48

Electrical characteristics PM6675AS

Table 6. Electrical characteristics (continued)

T

= -25 °C to 85 °C , VCC = AVCC = +5 V, LIN = 1.5 V and LOUT= 0.6 V if not otherwise

A

specified.

Symbol Parameter Test condition Min Typ Max Unit

Current limit and zero crossing comparator

(1)

I

CSNS

CSNS input bias current 90 100 110 µA

Comparator offset -6 6

V

ZC,OFFS

Positive current limit threshold V

fixed negative current limit
threshold

Zero crossing comparator offset -11 -5 1

PGND

- V

CSNS

100

110

High and low side gate drivers

HGATE high state (pullup) 2.0 3

HGATE driver on-resistance

HGATE low state (pulldown) 1.8 2.7

LGATE high state (pullup) 1.4 2.1

LGATE driver on-resistance

LGATE low state (pulldown) 0.6 0.9

UVP/OVP protections and PGOOD signals

OVP Over voltage threshold 112 115 118

UVP Under voltage threshold 67 70 73

SMPS upper threshold 107 110 113

SMPS lower threshold 86 90 93

PGOOD

LDO upper threshold 107 110 113

LDO lower threshold 86 90 93

I

PG,LEAK

V

PG,LOW

SPG and LPG leakeage current SPG and LPG forced to 5.5 V 1 µA

SPG and LPG low level voltage I

LPG,SINK

= I

SPG,SINK

= 4 mA 150 250 mV

Soft-start section (SMPS)

mV

Ω

%

Soft-start ramp time
(4 steps current limit)

Soft-start current limit step 25 µA

Soft end section

Switching section discharge
resistance

LDO section discharge resistance 15 25 35

LDO section

LDO reference voltage 600

V

LREF

LDO output accuracy respect to
VREF

-1 mA < I

-1 A < I

10/48

234ms

15 25 35

< 1 mA -20 20

LDO

< 1 A -25 25

LDO

Ω

mV

PM6675AS Electrical characteristics

Table 6. Electrical characteristics (continued)

T

= -25 °C to 85 °C , VCC = AVCC = +5 V, LIN = 1.5 V and LOUT= 0.6 V if not otherwise

A

specified.

Symbol Parameter Test condition Min Typ Max Unit

LDO sink current limit

I

LDO,CL

LDO source current limit

I

LIN,BIAS

I

LFB,BIAS

I

LFB,LEAK

Power management section

LDO input bias current, on LEN connected to AVCC, no load 1 10

LDO input bias current, off LEN = 0 V, no load 1

LFB input bias current

LFB leakage current LEN=0V, V

(1)

V

LFB

V

LFB

0.9

> V

> V

⋅ V

, LILIM = 5 V -3 -2.3 -2

LREF

, LILIM = 0 V -1.6 -1.3 -1

LREF

< V

LREF

LFB

< V

LILIM=5V

0.9

⋅ V

< V

LREF

LFB

< V

LILIM = 0 V

V

LFB

V

LFB

< 0.9 ⋅ V
< 0.9 ⋅ V

, LILIM = 5 V 1 1.3 1.6

LREF

, LILIM = 0 V 0.5 0.8 1.1

LREF

LEN connected to AVCC

VLFB = 0.6 V

= 0.6V -1 1

LFB

LREF

LREF

,

22.43

A

,

11.31.6

µA

-1 1

V

AVC C

-0.7

V

AVC C

-0.8

V

AVC C

-1.3

V

AVC C

-1.5

V

VTHVSEL

V

VTHNOSKIP

VSEL pin thresholds

NOSKIP pin thresholds

Fixed mode

Adjustable mode

Forced-PWM mode

No-audible mode 1.0

Pulse-skip mode 0.5

VTHLEN

VTHLILIM

,

LEN, SWEN turn on level 1.6

LILIM pin thresholds

±2A LDO current limit

VAVCC

-0.8

V

V

VTHSWEN

V

LEN, SWEN turn off level 0.4

±1A LDO current limit 0.5

I

IN,LEAK

IN3,LEAK

I

OSC,LEAK

Logic input leakage current LEN, SWEN and LILIM = 5 V 10

Multilevel input leakage current VSEL and NOSKIP = 5 V 10

VOSC pin leakage current VOSC = 1 V 1

Thermal shutdown

T

SHDN

1. Specifications referred to TJ = TA. All the parameters at operating temperatures extremes are guaranteed by design and
statistical correlation (not production tested).

2. Guaranteed by design. Not production tested.

Shutdown temperature

(2)

150 °C

V

µAI

11/48

Block diagram PM6675AS

5 Block diagram

Figure 3. Functional and block diagram

Vr = 0.6V

Vr = 0.6V

Vr = 0.6V

LFB

LFB

LFB

LIN

LIN

LIN

LOUT

LOUT

LOUT

LGND

LGND

LPG

LPG

LPG

SGND

SGND

SGND

LDS

LDS

Vr +10

Vr +10

Vr +10

VREF

VREF

VREF

_

_

_

+

+

+

LEN

LEN

LEN

%

%

%

+

+

+

-

-

-

+

+

+

-

-

-

Vr -10

Vr -10

Vr -10

UVP/OVP

UVP/OVP

UVP/OVP

0.6V

0.6V

0.6V

1.236V

1.236V

1.236V
Bandgap

Bandgap

Bandgap

LILIM

LILIM

LILIM

%

%

%

VOSC

VOSC

VOSC

Ton

Ton

Ton

1-shot

1-shot

1-shot

Ton

Ton

Ton

min

min

min

1-shot

1-shot

1-shot

Toff

Toff

Toff

min

min

min

1-shot

1-shot

1-shot

Anti Cr oss

Anti Cr oss

Anti Cr oss
Conduction

Conduction

Conduction

SWEN

SWEN

SWEN

Vr

Vr

Vr

BOOT

BOOT

BOOT

Level

Level

Level
shifter

shifter

shifter

Zero Crossing

Zero Crossing

Zero Crossing

& Current

& Current

& Current

Limit

Limit

Limit

_

_

_

VREF

VREF

VREF

+

+

+

Vr +10

%

Vr +10

%

Vr +10

%

+

+

_

_

_

m

m

m

g

g

g

+

+

+

+

Vr

Vr

Vr

-

-

-

+

+

+

-

-

-

Vr -10

%

Vr -10

%

Vr -10

%

HGATE

HGATE

HGATE

PHASE

PHASE

PHASE

VCC

VCC

VCC

LGATE

LGATE

LGATE

PGND

PGND

PGND

CSNS

CSNS

CSNS

COMP

COMP

COMP

SPG

SPG

SPG

AVCC

AVCC

AVCC

LILIM

LILIM

NOSKIP

NOSKIP

NOSKIP

Table 7. Legend

UVLO

UVLO

UVLO

Thermal Shutdown

Thermal Shutdown

Thermal Shutdown

LEN

LEN

LEN

SWEN

CONTROL LOGIC

CONTROL LOGIC

CONTROL LOGIC

SWEN

SWEN

SWEN

LDS

LDS

VSEL

VSEL

VSEL

LDS

SWEN

LDS

SWEN

LDS

SWEN Switching controller enable

LEN LDO regulator enable

LDS LDO output discharge enable

SDS Switching output discharge enable

LILIM LDO regulator current limit

12/48

LEN

LEN

LEN

VSNS

VSNS

VSNS

SDS

SDS

SDS

fixadj

fixadj

fixadj

PM6675AS Typical operating characteristics

6 Typical operating characteristics

Figure 4. Efficiency vs output load

F

= 330 kHz VOUT=1.5 V,

SW

100

90

80

70

60

50

40

Efficiency [%]

30

20

10

0

0.001 0.010 0.100 1.000 10.000

VIN = 24 V

VOUT - Efficiency

Current [A]

Forced PWM

Pulse Ski p

Non Audible PS

Figure 5. Switching frequency vs output

current, VOUT = 1.5 V, VIN = 24 V

SW Frequency VS V OUT Load

500

400

300

200

Frequency [kHz]

100

0

0.010 0.100 1.000 10.000

Current [A]

Forced PWM

Pulse Skip

Non Audible PS

Figure 6. Switching frequency vs input

voltage, VOUT = 1.5 V, IVOUT = 2 A,

550

450

350

Frequency [kHz]

250

4142434

forced PWM mode

SW Frequency VS Input Voltage

Volt age [V]

Figure 8. LOUT load regulation

LDOIN = VOUT, VOUT in forced

1.090

1.080

1.070

1.060

1.050

Voltage [ V]

1.040

1.030

1.020

-1.500 -1.000 -0.500 0.000 0.500 1.000 1.500

PWM mode

LOUT - Load Regulation

Current [A]

Figure 7. VOUT load regulation, VIN = 24 V

VOUT - Load Regulation

1.540

1.535

1.530

1.525

1.520

1.515

Voltage [V]

1.510

1.505

1.500

0.001 0.010 0.100 1.000 10.000

Current [A]

Forced PWM

Pulse Skip

Non Audible PS

Figure 9. VOUT = 1.5 V, VIN = 24 V,

IVOUT = 0 A, pulse-skip mode

13/48

Typical operating characteristics PM6675AS

Figure 10. VOUT = 1.5V , VIN = 24V,

IVOUT = 0 A, forced-PWM mode

Figure 12. VOUT Soft-start @150mΩ load,

pulse-skip mode

Figure 11. VOUT = 1.5 V, VIN = 24 V, no load,

Non-audible pulse-skip mode
(33 kHz)

Figure 13. LOUT turn on, VOUT in pulse-skip

mode

Figure 14. VOUT Load Transient (VIN = 24 V,

LOAD = 0 A -> 7 A @2.5 A/µs).

14/48

pulse-skip mode

Figure 15. LOUT load transient (VIN = 24 V,

LOAD = -1.5 A -> 1.5 A @2.5 A/µs).
pulse-skip mode

PM6675AS Typical operating characteristics

Figure 16. VOUT and LOUT output voltages.

VOUT soft-end. LOUT powered by
an auxiliary rail

Figure 18. UV protection, pulse-skip mode

LOUT powered by an auxiliary rail

Figure 17. VOUT and LOUT output voltages

LOUT soft-end

Figure 19. OV protection, pulse-skip mode

Figure 20. VOUT current limit protection

during a load transient
(0 A to 9 A @2.5A/µs)

Figure 21. LOUT current limit during an output

short

15/48

Device description PM6675AS

7 Device description

The PM6675AS combines a single high efficiency step-down controller and an independent
Low Drop-Out (LDO) linear regulator in the same package.

The switching controller section is a high-performance, pseudo-fixed frequency, Constant­On-Time (COT) based regulator specifically designed for handling fast load transient over a
wide range of input voltage.

The switching section output can be easily set to a fixed 1.5 V voltage without additional
components or adjusted in the 0.6 V to 3.3 V range using an external resistor divider. The
Switching Mode Power Supply (SMPS) can handle different modes of operation in order to
minimize noise or power consumption, depending on the application needs. Selectable low­consumption and low-noise modes allow the highest efficiency and a 33 kHz minimum
switching frequency respectively at light loads.

The current sensing is lossless, based on the Low-Side MOSFET turn-on resistance.

The input of the LDO can be either the switching section output or a lower voltage rail in
order to reduce the total power dissipation. Linear regulator stability is achieved by filtering
its output with a ceramic capacitor (20 µF or greater). The LDO linear regulator can sink and
source up to 2 Apk.

Two fixed current limit (±1A-±2A) can be chosen.

An active soft-end is independently performed on both the switching and the linear
regulators outputs when disabled.

7.1 Switching section - constant on-time pwm controller

The PM6675AS employes a pseudo-fixed frequency, Constant On-Time (COT) controller as
the core of the switching section. As well known, the COT controller concerns of a relatively
simple algorithm and uses the ripple voltage derived across the output capacitor ESR to
trigger the On-Time one-shot generator. In this way, the output capacitor ESR acts as a
current sense resistor providing the appropriate ramp signal to the PWM comparator.
Nearly constant switching frequency is achieved by the system loop in steady-state
operating conditions by varying the On-Time duration, avoiding thus the need for a clock
generator. The On-Time one shot duration is directly proportional to the output voltage,
sensed at VSNS pin, and inversely proportional to the input voltage, sensed at the VOSC
pin, as follows:

Equation 1

V

SNS

KT

OSCON

V

where K

is a constant value (130 ns typ.) and τ is the internal propagation delay (40ns

OSC

typ.). The one-shot generator directly drives the high-side MOSFET at the beginning of
each switching cycle allowing the inductor current to increase; after the On-Time has
expired, an Off-Time phase, in which the low-side MOSFET is turned on, follows.

τ+=

OSC

16/48

PM6675AS Device description

The Off-Time duration is solely determined by the output voltage: when lower than the set
value (i.e. the voltage at VSNS pin is lower than the internal reference = 0.6 V), the
synchronous rectifier is turned off and a new cycle begins (

Figure 22).

Figure 22. Inductor current and output voltage in steady state conditions

Inductor
current

Output
voltage

Vreg

Ton

Toff

The duty-cycle of the buck converter is, in steady-state conditions, given by

Equation 2

V

OUT

D =

V

IN

The switching frequency is thus calculated as

Equation 3

V

OUT

SNS

α

OSC

===

α

1

K

OSCOUT

SW

D

T

ON

f ⋅

V

IN

V

K

OSC

V

OSC

where

Equation 4 a

V

OSC

=α

OSC

V

IN

t

Equation 4 b

V

SNS

=α

OUT

V

OUT

17/48

Device description PM6675AS

V

Referring to the typical application schematic (fig. 1 and 23), the final expression is then:

Figure 23. Switching frequency selection and VOSC pin

VIN

R1

PM6675AS

OSC

R2

Equation 5

α

f ⋅

SW

OSC

=

K

OSC

R

2

=

RR

+

1

K

OSC21

Even if the switching frequency is theoretically independent from input and output voltages,
parasitic parameters involved in power path (like MOSFET on-resistance and inductor DCR)
introduce voltage drops responsible of a slight dependence on load current.

In addition, the internal delay is cause of a light dependence from input voltage.

The PM6675AS switching frequency can be set by an external divider connected to the
VOSC pin.

The voltage seen at this pin must be greater than 0.8 V and lower than 2 V in order to
ensure system's linearity.

7.1.1 Constant-on-time architecture

Figure 24 shows the simplified block diagram of the Constant-On-Time controller.

The switching regulator of the PM6675AS owns a one-shot generator that turns on the high­side MOSFET when the following conditions are simultaneously satisfied: the PWM
comparator is high (i.e. output voltage is lower than Vr = 0.6 V), the synchronous rectifier
current is below the current limit threshold and the minimum off-time has expired.

A minimum off-time constrain (300 ns typ.) is introduced to assure the boot capacitor charge
and allow inductor valley current sensing on low-side MOSFET. A minimum On-Time is also
introduced to assure the start-up switching sequence.

Once the on-time has timed out, the high side switch is turned off, while the synchronous
rectifier is ignited according to the anti-cross conduction management circuitry.

When the output voltage reaches the valley limit (determined by internal reference
Vr=0.6 V), the low-side MOSFET is turned off according to the anti-cross conduction logic
once again, and a new cycle begins.

18/48

PM6675AS Device description

p

r

r

r

r

rrr

r

p

r

r

r

r

V

V

r

r

A

g

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

Figure 24. Switching section simplified block diagram

n

Q

Q

n

SSNNS

SSGGNND

VOOSSCC

C

OOSSC

Anti cross-
conduction
circuitry

+

-

2.5V

S

D

CCSSNNS

CCOOMMP

VSSEE

SSNNS

L

L

u

S

P

S

PPoossiittiivvee CCu

110000uuA

IInntteeggrraattoor

MMiinn ffssww
ccoouunntte

A

G

BBG

r

g

m

m

6

00..6

e

ZZeerroo--ccrroossssiinngg

CCoommppaarraattoor

eenntt LLiimmiittccoom

+

­+

-

PPWWMMCCoom

+

r

m

m

VSEL<4V

S

R

_

paa

paa

o

aatto

o

aatto

Q

Q

PPUULLSSEE -- SSKKIIP

TTooffff--mmiin

1-Shot generator

S

R

TToonn--mmiin

Ton

C

OOSSC

P

7.1.2 Output ripple compensation and loop stability

T

BBOOOOT

LLeevveell

r

sshhiifftteer

2.5V

+

-

+

-

500mV

Q

S

R

6

00..6

G

BBG

VVRREEF

HHSS

LLSS

F

bbaannddggaapp

11..223366V

V

HHGGAATTE

PPHHAASSE

C

VVCCC

LLGGA

TTE

D

PPGGNND

E

E

E

The loop is closed connecting the center tap of the output divider (internally, when the fixed
output voltage is chosen, or externally, using the VSEL pin in the adjustable output voltage
mode). The feedback node is the negative input of the error comparator, while the positive
input is internally connected to the reference voltage (Vr = 0.6 V). When the feedback
voltage becomes lower than the reference voltage, the PWM comparator goes high and sets
the control logic, turning on the high-side MOSFET. After the On-Time (calculated as
previously described) the system releases the high-side MOSFET and turns-on the
synchronous rectifier.

The voltage drop along ground and supply PCB paths, used to connect the output capacitor
to the load, is a source of DC error. Further the system regulates the output voltage valley,
not the average, as shown in

Figure 22. Thus, the voltage ripple on the output capacitor is

an additional source of DC error. To compensate this error, an integrative network is
introduced in the control loop, by connecting the output voltage to the COMP pin through a
capacitor (CINT) as shown in

Figure 25.

19/48

Device description PM6675AS

V

g

g

V

r

V

V

V

V

V

Figure 25. Circuitry for output ripple compensation

COMP PIN

OLTAGE

∆

t

F

I=gm(V1-Vr)

P

CCOOMMP

T

C

FFIILLT

C

∆

C

C

capacitor feeds the negative input of the PWM comparator,

INT

EESSR

OOUUT

R

T

C

C

R

R

IINNT

IINNT

T

T

V

C

C

V

VVSSNNS

S

IINNT

T

RREEF

m

m

+

1

1

R

2

FFbb2

R

R

Fb1

+

-

PPWWMM

CCoommppaarraattoor

r

FILT

Vr

OUTPUT

OLTAGE

t

The additional capacitor is used to reduce the voltage on the COMP pin when higher than
300 mVpp and is unnecessary for most of applications. The transconductance amplifier
(gm) generates a current, proportional to the DC error, used to charge the CINT capacitor.
The voltage across the C
forcing the loop to compensate the total static error. An internal voltage clamp forces the
COMP pin voltage range to ±150 mV respect to VREF. This is useful to avoid or smooth
output voltage overshoot during a load transient. When the Pulse-Skip Mode is entered, the
clamping range is automatically reduced to 60 mV in order to enhance the recovering
capability. In case the ripple amplitude is larger than 150 mV, an additional capacitor C
can be connected between the COMP pin and ground to reduce ripple amplitude, otherwise
the integrator will operate out of its linearity range. This capacitor is unnecessary for most of
applications and can be omitted.

The design of the external feedback network depends on the output voltage ripple. If the
ripple is higher than approximately 20 mV, the correct C
keep the loop stable. The stability of the system depends firstly on the output capacitor zero
frequency.

The following condition must be satisfied:

Equation 6

fkf

20/48

capacitor is usually enough to

INT

out

k

ESRC2

××π

=×>

ZoutSW

PM6675AS Device description

where k is a fixed design parameter (k > 3). It determinates the minimum integrator
capacitor value:

Equation 7

g

C

>

INT

2

m

f

⎛

SW

f

−⋅π

⎜
⎝

Zout

k

Vr

⋅

Vout

⎞
⎟

⎠

where gm = 50 µs is the integrator transconductance.

If the ripple on the COMP pin is greater than the integrator 150 mV, the auxiliary capacitor

can be added. If q is the desired attenuation factor of the output ripple, C

C

FILT

FILT

is given

by:

Equation 8

C

FILT

In order to reduce the noise on the COMP pin, it is possible to add a resistor R
together with C

INT

and C

, realizes a low pass filter. The cutoff frequency f

FILT

INT

=

q

that,

INT

must be

CUT

)q1(C

−⋅

greater (10 or more times) than the switching frequency:

Equation 9

f2

CUT

1

⋅

CC

⋅⋅π

FILTINT

+

CC

FILTINT

=

R

INT

If the ripple is very small (lower than approximately 20 mV), a different compensation
network, called "Virtual-ESR" Network, is needed. This additional circuit generates a
triangular ripple that is added to the output voltage ripple at the input of the integrator. The
complete control scheme is shown in

Figure 26.

21/48

Device description PM6675AS

V

V

V

V

g

g

V

V

Figure 26. "Virtual-ESR" network

T NODE
VOLTAGE

ΔV1

R

OUTPUT
VOLTAGE

R

COMP PIN

t

T

Δ

OLTAGE

VREF

R

R

R

R

C

C

IINNT

1

1

Δ

2

t

F

RREEF

R

Fb1

+

-

PPWWMM

CCoommppaarraattoor

r

I=gm(V1-Vr)

P

CCOOMMP

T

C

IINNT

T

C

m

C

C

FFIILLT

T

m

+

r

S

VVSSNNS

R

EESSR

T

C

OOUUT

C

t

1

1

R

2

FFbb2

R

The ripple on the COMP pin is the sum of the output voltage ripple and the triangular ripple
generated by the Virtual-ESR Network. In fact the Virtual-ESR Network behaves like a
further equivalent series resistor RVESR.

A good trade-off is to design the network in order to achieve an RVESR given by:

Equation 10

R

VESR

=

RIPPLE

∆

ESR

−

I

L

V

where ∆IL is the inductor current ripple and VRIPPLE is the total ripple at the T node,
chosen greater than approximately 20 mV.

The new closed-loop gain depends on C

. In order to ensure stability it must be verified

INT

that:

Equation 11

C

INT

g

>

Vr

m

⋅

⋅π

Vout

f2

Z

where:

Equation 12

f

=

Z

1

RC2

⋅⋅π

TOTout

22/48

PM6675AS Device description

and

Equation 13

Moreover, the C

R

capacitor must meet the following condition:

INT

TOT

ESR R

+=

VERS

Equation 14

fkf

=⋅>

ZSW

where R
the Virtual-ESR Network (R

is the sum of the ESR of the output capacitor and the equivalent ESR given by

TOT

). The k parameter must be greater than unity (k > 3) and

VESR

determines the minimum integrator capacitor value C

k

RC2

⋅⋅π

TOTout

:

INT

Equation 15

g

C

>

INT

2

m

f

⎛

SW

−⋅π

⎜

k

⎝

Vr

⋅

Vout

⎞

f

⎟

Z

⎠

The capacitor of the Virtual-ESR Network, C, is chosen as follow

Equation 16

C5C⋅>

INT

and R is calculated to provide the desired triangular ripple voltage:

Equation 17

R

VESR

CR

⋅

L

=

Finally, the R1 resistor can be selected according to expression 18:

Equation 18

⎛
⎜

⋅

R

⎜
⎝

=

1R

R

−

23/48

⎞

1

⎟
⎟

⋅⋅π

Cf

Z

⎠

1

Cf

⋅⋅π

Z

Device description PM6675AS

7.1.3 Pulse-skip and no-audible pulse-skip modes

High efficiency at light load conditions is achieved by PM6675AS entering the Pulse-Skip
Mode (if enabled). At light load conditions the zero-crossing comparator truncates the low­side switch On-Time as soon as the inductor current becomes negative; in this way the
comparator determines the On-Time duration instead of the output ripple (see

Figure 27. Inductor current and output voltage at light load with Pulse-Skip

Inductor
current

Output
voltage

Vreg

TON

TOFF

Figure 27).

As a consequence, the output capacitor is left floating and its discharge depends solely on
the current drained from the load. When the output ripple on the pin COMP falls under the
reference, a new shot is triggered and the next cycle begins. The Pulse-Skip mode is
naturally obtained enabling the zero-crossing comparator and automatically takes part in the
COT algorithm when the inductor current is about half the ripple current amount, i.e.
migrating from continuous conduction mode (C.C.M.) to discontinuous conduction mode
(D.C.M.).

The output current threshold related to the transition between PWM Mode and Pulse-Skip
Mode can be approximately calculated as:

Equation 19

VV

−

OUTIN

LOAD

)Skip2PWM(I ⋅

=

⋅

T

L2

ON

At higher loads, the inductor current never crosses the zero and the device works in pure
PWM mode with a switching frequency around the nominal value.

A physiological consequence of Pulse-Skip Mode is a more noisy and asynchronous (than
normal conditions) output, mainly due to very low load. If the Pulse-Skip is not compatible
with the application, the PM6675AS allows the user to choose also between forced-PWM
and No-Audible Pulse-Skip alternative modes (see

Chapter 7.1.4 for details).

24/48

PM6675AS Device description

No-audible pulse-skip mode

Some audio-noise sensitive applications cannot accept the switching frequency to enter the
audible range as is possible in Pulse-Skip mode with very light loads. For this reason, the
PM6675AS implements an additional feature to maintain a minimum switching frequency of
33 kHz despite of a slight efficiency loss. At very light load conditions, if any switching cycle
has taken place within 30 µs (typ.) since the last one (because of the output voltage is still
higher than the reference), a No-audible pulse-skip cycle begins. The low-side MOSFET is
turned on and the output is driven to fall until the reference has been crossed. Then, the
high-side switch is turned on for a Ton period and, once it has expired, the synchronous
rectifier is enabled until the inductor current reaches the zero-crossing threshold
(see

Figure 28).

Figure 28. Inductor current and output voltage at light load with non-audible pulse-skip

Inductor
current

Output
voltage

Vreg

TMAX

TON TOFF TIDLE

For frequencies higher than 33 kHz (due to heavier loads) the device works in the same way
as in Pulse-Skip mode. It is important to notice that in both pulse-skip and no-audible Pulse­Skip modes the switching frequency changes not only with the load but also with the input
voltage.

t

25/48

Device description PM6675AS

7.1.4 Mode-of-operation selection

Figure 29. VSEL and NOSKIP multifunction pin configurations

VOUT

+5V

PM6675AS

R9

VSEL

R8

VREF

NOSKIP

The PM6675AS has been designed to satisfy the widest range of applications. The device is
provided of some multilevel pins which allow the user to choose the appropriate
configuration. The VSEL pin is used to firstly decide between fixed preset or adjustable
(user defined) output voltages.

When the VSEL pin is connected to +5 V, the PM6675AS set the switching section output
voltage to 1.5 V without the need of an external divider.

Applications requiring different output voltages can be managed by PM6675AS simply
setting the adjustable mode. If the VSEL pin voltage is higher than 4 V, the fixed output
mode is selected. Connecting an external divider to the VSEL pin, it is used as negative
input of the error amplifier and the output voltage is given by expression (20).

Equation 20

9R8R

+

6.0VOUT

ADJ

⋅=

8R

The output voltage can be set in the range from 0.6 V to 3.3 V.

The NOSKIP is the power saving algorithm selector: if tied to +5 V, the forced-PWM (fixed
frequency) control is performed. If grounded or connected to VREF pin (1.237 V reference
voltage), the Pulse-Skip or Non-Audible Pulse-Skip Modes are respectively selected.

Table 8. Mode-of-operation settings summary

VSEL NOSKIP VOUT Operating mode

V

V

> 4.3V

VSEL

V

< 3.7V

VSEL

26/48

1V < V

V

1 V < V

V

> 4.2 V

NOSKI P

< 3.5 V Non-Audible Pulse-skip

NOSKIP

< 0.5 V Pulse-Skip

> 4.2 V

NOSKIP

< 3.5 V Non-Audible Pulse-skip

NOSKIP

< 0.5 V Pulse-Skip

NOSKIP

Forced-PWM

1.5 V

Forced-PWM

ADJ

PM6675AS Device description

7.1.5 Current sensing and current limit

The PM6675AS switching controller employes a valley current sensing algorithm to properly
handle the current limit protection and the inductor current zero-crossing information. The
current is sensed during the conduction time of the low-side MOSFET. The current sensing
element is the low-side MOSFET on-resistance. The sensing scheme is visible in

Figure 30.

Figure 30. Current sensing scheme

HGATE

RILIM

CSNS

LGATE

An internal 100 µA current source is connected to CSNS pin that is also the non-inverting
input of the positive current limit comparator. When the voltage drop developed across the
sensing parameter equals the voltage drop across the programming resistor R

ILIM

, the
controller skips subsequent cycles until the overcurrent is detected or the output UV
protection latches off the device (see par.

Referring to

Figure 30, the RDSon sensing technique is tailored to all low cost, high

Chapter 7.1.4 UV and OV Protections).

efficiency applications.

It must be taken into account that the current limit circuit actually regulates the inductor
valley current. This means that RILIM must be calculated to set a limit threshold given by the
maximum DC output current plus half of the inductor ripple current:

Equation 21

R

ILIM

where R

is the sensing device (R

SENSE

CL

DSon

A100I ⋅µ=

R

SENSE

).

The PM6675AS provides also a fixed negative current limit to prevent excessive reverse
inductor current when the switching section sinks current from the load in forced-PWM (3rd
quadrant working conditions). This negative current limit threshold is measured between
PHASE and PGND pins, comparing the drop magnitude on PHASE pin with an internal
110mV fixed voltage.

27/48

Device description PM6675AS

7.1.6 POR, UVLO and soft-start

The PM6675AS automatically performs an internal startup sequence during the rising
phase of the analog supply of the device (AVCC). The switching controller remains in a
stand-by state until AVCC crosses the upper UVLO threshold (4.25 V typ.), keeping active
the internal discharge MOSFETs (only if AVCC > 1 V).

The soft-start allows a gradual increase of the internal current limit threshold during startup
reducing the input/output surge currents. At the beginning of start-up, the PM6675AS
current limit is set to 25 % of nominal value and the under voltage protection is disabled.
Then, the current limit threshold is sequentially brought to 100 % in four steps of
approximately 750 µs (figure 13).

Figure 31. Soft-start waveforms

Switching output

Current limit threshold

SWEN

After a fixed 3 ms total time, the soft-start finishes and UVP is released: if the output voltage
doesn't reach the
is detected; the device performs a soft end and latches off. Depending on the load
conditions, the inductor current may or may not reach the nominal value of the current limit

Figure 32 on page 29 shows two examples).

(

under voltage lower threshold within soft-start duration, the UVP condition

Time

28/48

PM6675AS Device description

Figure 32. Soft-start at heavy load (a) and short-circuit (b) condition,

pulse-skip enabled

(a)

7.1.7 Switching section power-good signal

The SPG pin is an open drain output used to monitor output voltage through VSNS (in fixed
output voltage mode) or V

(in adjustable output voltage mode) pins and is enabled after

SEL

the soft-start timer has expired. The SPG signal is held low if the output voltage drops 10 %
below or rises 10 % above the nominal regulated value. The SPG output can sink current up
to 4 mA.

7.1.8 Switching section output discharge

Active soft-end of the output occurs when the SWEN (SWitching ENable) is forced low.
When the switching section is turned off, an internal 25 Ω resistor discharges the output
through the VSNS pin.

Figure 33. Switching section soft-end

VOUT

Resistive Discharge

(b)

SWEN

29/48

Device description PM6675AS

7.1.9 Gate drivers

The integrated high-current gate drivers allow using different power MOSFETs. The high­side driver employes a bootstrap circuit which is supplied by the +5 V rail. The BOOT and
PHASE pins work respectively as supply and return path for the high-side driver, while the
low-side driver is directly feed through VCC and PGND pins.

An important feature of the PM6675AS gate drivers is the Adaptive Anti-Cross-Conduction
circuitry, which prevents high-side and low-side MOSFETs from being turned on at the same
time. When the high-side MOSFET is turned off, the voltage at the PHASE node begins to
fall. The low-side MOSFET is turned on only when the voltage at the PHASE node reaches
an internal threshold (2.5 V typ.). Similarly, when the low-side MOSFET is turned off, the
high-side one remains off until the LGATE pin voltage is above 1 V.

The power dissipation of the drivers is a function of the total gate charge of the external
power MOSFETs and the switching frequency, as shown in the following equation:

Equation 22

fQV)driver(P ⋅⋅=

SWgDRVD

The low-side driver has been designed to have a low-resistance pull-down transistor
(0.6 Ω typ.) in order to prevent undesired ignition of the low-side MOSFET due to the Miller
effect.

7.1.10 Reference voltage and bandgap

The 1.237 V internal bandgap reference has a granted accuracy of ±1 % over the -25 °C to
85 °C temperature range. The VREF pin is a buffered replica of the bandgap voltage. It can
supply up to ±100 µA and is suitable to set the intermediate level of NOSKIP multifunction
pin. A 100 nF (min.) bypass capacitor toward SGND is required to enhance noise rejection.
If VREF falls below 0.8 V (typ.), the system detects a fault condition and all the circuitry is
turned off.

An internal divider derives a 0.6 V±1 % voltage (Vr) from the bandgap. This voltage is used
as reference for both the switching and the linear sections. The Over-Voltage Protection, the
Under-Voltage Protection and the power-good signals are also referred to Vr.

7.1.11 Switching section OV and UV protections

When the switching output voltage is about 115 % of its nominal value, a latched Over­Voltage Protection (OVP) occurs. In this case the synchronous rectifier immediately turns on
while the high-side MOSFET turns off. The output capacitor is rapidly discharged and the
load is preserved from being damaged. The OVP is also active during the soft-start. Once
an OVP has taken part, a toggle on SWEN pin or a power-on-reset is necessary to exit from
the latched state.

When the switching output voltage is below 70 % of its nominal value, a latched Under­Voltage Protection occurs. This event causes the switching section to be immediately
disabled and both switches to be opened. The controller performs a soft-end and the output
is eventually kept to ground, turning the low side MOSFET on when the voltage is lower than
400 mV.

30/48

PM6675AS Device description

The Under-Voltage Protection circuit is enabled only at the end of the soft-start. Once an
UVP has taken part, a toggle on SWEN pin or a Power-On-Reset is necessary to clear the
fault state and restart the section.

7.1.12 Device thermal protection

The internal control circuitry of the PM6675AS self-monitors the junction temperature and
turns all outputs off when the 150 °C limit has been overran. This event causes the switching
section to be immediately disabled and both switches to be opened. The controller performs
a soft-end and both the outputs are eventually kept to ground, then the low side MOSFET is
turned on when the voltage of the switching section is lower than 400 mV.

The thermal fault is a latched protection and normal operating condition is restored by a
Power-On Reset or toggling SWEN and LEN pins at the same time.

Table 9. Switching section OV, UV and OT faults management

Fault Conditions Action

Over voltage

Under voltage

Junction over

temperature

VOUT > 115 % of the

nominal value

VOUT < 70 % of the nominal

value

> +150 °C

T

J

7.2 LDO linear regulator section

The independent Low-Drop-Out (LDO) linear regulator has been designed to sink and
source up to 2 A peak current and 1 A continuously. The LDO output voltage can be
adjusted in the range 0.6 V to 3.3 V simply connecting a resistor divider as shown in

Figure 34 on page 32.

Equation 23

ADJ

LGATE pin is forced high and the device latches off.
Exit by a Power-On Reset or toggling SWEN

LGATE pin is forced high after the soft-end, then the
device latches off. Exit by a Power-On Reset or
toggling SWEN.

LGATE pin is forced high after the soft-end, then the
device latches off. Exit by a Power-On Reset or
toggling SWEN and LEN after temperature drop.

20R19R

6.0VLDO

+

⋅=

20R

31/48

Device description PM6675AS

Figure 34. LDO output voltage selection

VLOUT

C

OUT

Cc

R19

R20

PM6675AS

LOUT

LFB

LGND

A compensation capacitor Cc must be added to adjust the dynamic response of the loop.
The value of Cc is calculated according to the desired bandwidth of the LDO regulator and
depends on the value of the feedback resistors. In most of applications the pole due to the
compensation capacitor is placed at 100-200 kHz (equation 24).

Equation 24

f

=

p

1

C)20R19R(2

⋅⊕π

C

kHz200

=

The LIN input can be connected to the switching section output for compact solutions or to a
lower supply, if available in the system, in order to reduce the power dissipation of the LDO.

A minimum output capacitance of 20 µF (2x10 µF MLCC capacitors) is enough to assure
stability and fast load transient response.

7.2.1 LDO section current limit

The LDO regulator can handle up to ±2 Apk, depending on the LDO input voltage and the
LILIM pin setting. The output current is limited to ±1 A or ±2 A if the LILIM pin is connected
to SGND or AVCC respectively (

Figure 35. LDO current limit setting

±2A CL

±1A CL

The maximum current that the LDO can source depends also on the input and output
voltages. Due to the high side MOSFET of the output stage, the LDO cannot source the limit
current at high output voltages.
source as function of the input and output voltages. For output voltages higher than 2 V, the
maximum output current is limited as reported.

Figure 35).

PM6675AS

+5V

LILIM

Figure 36 shows the maximum current that the LDO can

32/48

PM6675AS Device description

Figure 36. LDO current limit setting

2.2

2.0

1.8

1.6

1.4

1.2

1.0

ILOUT [A ]

0.8

0.6

0.4

0.2

0.0

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

VOUT=1.05V

VOUT=1.2V

VOUT=1.5V

VOUT=1.8V

VOUT=2.0V

VOUT=2.2V

VOUT=2.5V

VOUT=3.3V

VLIN [V]

7.2.2 LDO section soft-start

The LDO section soft-start is performed by clamping the current limit. During startup, the
LDO current limit voltage is set to 1 A and the output voltage increases linearly. When the
output voltage rises above 90 % of the nominal value, the current limit is released to 2 A
according to the LILIM pin setting.

7.2.3 LDO section power-good signal

The LPG pin is an open drain output used to monitor the LDO output voltage through LFB
pin. The LPG signal is held low if the output voltage drops 10 % below or rises 10 % above
the nominal regulated value. The LPG output can sink current up to 4 mA.

7.2.4 LDO section output discharge

Active soft-end of the LDO output occurs when the LEN (Linear ENable) is forced low. When
the LDO section is turned off, an internal 25 Ω resistor, directly connected to the LOUT pin,
discharges the output.

Figure 37. LDO section soft-end

VLDO

Resistive Discharge

LEN

33/48

Application information PM6675AS

8 Application information

The purpose of this chapter is to show the design procedure of the switching section.

The design starts from three main specifications:

● The input voltage range, provided by the battery or the AC adapter. The two extreme

values (V

● The maximum load current, indicated with I

● The maximum allowed output voltage ripple V

It’s also possible that specific designs should involve other specifications.

The following paragraphs will guide the user into a step-by-step design.

8.1 External components selection

The PM6675AS employes a pseudo-fixed frequency, Constant On-Time (COT) controller as
the core of the switching section. The switching frequency can be set by connecting an
external divider to the VOSC pin. The voltage seen at this pin must be greater than 0.8 V
and lower than 2 V in order to take advantage of the internal block linearity.

INmax

and V

) are important for the design.

INmin

LOAD,MAX

.

RIPPLE,MAX

.

Nearly constant switching frequency is achieved by the system loop in steady-state
operating conditions by varying the On-Time duration, avoiding thus the need for a clock
generator. The On-Time one shot duration is directly proportional to the output voltage,
sensed at VSNS pin, and inversely proportional to the input voltage, sensed at the VOSC
pin, as follows:

Equation 25

V

SNS

τ+=

OSC

where K

KT

OSCON

V

is a constant value (130 ns typ.) and τ is the internal propagation delay

OSC

(40 ns typ.).

The duty-cycle of the buck converter is, in steady-state conditions, given by

Equation 26

V

OUT

D =

V

IN

The switching frequency is thus calculated as

Equation 27

V

OUT

α

OSC

=

α

1

K

OSCOUT

K

OSC

V

IN

V

SNS

⋅

V

OSC

f ⋅

SW

D

==

T

ON

34/48

PM6675AS Application information

Equation 28 a

V

OSC

=α

OSC

V

IN

Equation 28 b

V

SNS

=α

OUT

V

OUT

Referring to the typical application schematic (figs. 1 and 23), the final expression is then:

Equation 29

Even if the switching frequency is theoretically independent from battery and output
voltages, parasitic parameters involved in power path (like MOSFETs on-resistance and
inductor DCR) introduce voltage drops responsible of a slight dependence on load current.

In addition, the internal delay is cause of a light dependence from input voltage.

Table 10. Typical values for switching frequency selection

R1 (kΩ)R2 (kΩ) Approx switching frequency (kHz)

330 11 250

330 13 300

330 15 350

330 18 400

330 20 450

330 22 500

8.1.1 Inductor selection

Once the switching frequency has been defined, the inductance value depends on the
desired inductor ripple current. Low inductance value means great ripple current that brings
to poor efficiency and great output noise. On the other hand a great current ripple is
desirable for fast transient response when a load step is applied.

α

f ⋅

SW

OSC

=

K

OSC

R

2

=

RR

+

1

K

OSC21

Otherwise, great inductance brings to good efficiency but the transient response is critical,
especially if V

INmin

- V

is little. Moreover a minimum output ripple voltage is necessary to

out

assure system stability and jitter-free operations (see Output capacitor selection paragraph).
The product of the output capacitor ESR multiplied by the inductor ripple current must be
taken into consideration. A good trade-off between the transient response time, the
efficiency, the cost and the size is to choose the inductance value in order to maintain the
inductor ripple current between 20 % and 50 % (usually 40 %) of the maximum output
current.

The maximum inductor ripple current, ∆I

, occurs at the maximum input voltage.

LMAX

35/48

Application information PM6675AS

With these considerations, the inductance value can be calculated with the following
expression:

Equation 30

VV

L ⋅

−

=

where fSW is the switching frequency, VIN is the input voltage, V

V

OUT

OUTIN

V

Ifsw

∆⋅

IN

L

is the output voltage and

OUT

is the inductor current ripple.

Once the inductor value is determined, the inductor current ripple is then recalculated:

Equation 31

VV

I ⋅

=∆

MAX,L

−

Lfsw

⋅

V

OUTMAX,IN

OUT

V

MAX,IN

The next step is the calculation of the maximum r.m.s. inductor current:

Equation 32

2

+=

)I(I

MAX,LOADRMS,L

The inductor must have an r.m.s. current greater than I

∆

2

)I(

MAX,L

12

in order to assure thermal

L,RMS

stability.

Then the calculation of the maximum inductor peak current follows:

Equation 33

∆

I

MAX,L

II

I

is important in inductor selection in term of its saturation current.

LPEAK

The saturation current of the inductor should be greater than I

+=

MAX,LOADPEAK,L

2

not only in case of hard

LPEAK

saturation core inductors. Using soft-ferrite cores it is possible (but not advisable) to push
the inductor working near its saturation current.

In

Ta bl e 1 1 some inductors suitable for typical working conditions are listed.

Table 11. Evaluated inductors (@ fsw = 400 kHz)

Manufacturer Series

COILCRAFT MLC1538-102 1 13.4 21.0

COILCRAFT MVR1261C-112 1.1 20 20

WURTH 7443552100 1 16 20

COILTRONICS HC8-1R2 1.2 16.0 25.4

Inductance

(µH)

+40°C rms

current (A)

-30% saturation
current (A)

36/48

PM6675AS Application information

In Pulse-Skip Mode, low inductance values produce a better efficiency versus load curve,
while higher values result in higher full-load efficiency because of the smaller current ripple.

8.1.2 Input capacitor selection

In a buck topology converter the current that flows through the input capacitor is pulsed and
with zero average value. The RMS input current can be calculated as follows:

Equation 34

Cin

RMS

LOAD

2

1

)D1(DII ∆⋅+−⋅⋅=

12

2

)I(D

L

Neglecting the second term, the equation 34 is reduced to:

Equation 35

)D1(DII

Cin

RMS

LOAD

−⋅=

The losses due to the input capacitor are thus maximized when the duty-cycle is 0.5:

Equation 36

CinRMSCinloss

2

LOADCin

The input capacitor should be selected with a RMS rated current higher than I

2

(max))I5.0(ESR(max)IESRP ⋅⋅=⋅=

.

CinRMS

Tantalum capacitors are good in term of low ESR and small size, but they occasionally can
burn out if subjected to very high current during operation. Multi-Layers-Ceramic-Capacitors
(MLCC) have usually a higher RMS current rating with smaller size and they remain the best
choice. The drawback is their quite high cost.

It must be taken in account that MLCC capacitance decreases when the operating voltage is
near the rated voltage. In table 12 some MLCC suitable for most of applications are listed.

Table 12. Evaluated MLCC for input filtering

Manufacturer Series

TAIYO YUDEN UMK325BJ106KM-T 10 50 2

TAIYO YUDEN GMK316F106ZL-T 10 35 2.2

TAIYO YUDEN GMK325F106ZH-T 10 35 2.2

TAIYO YUDEN GMK325BJ106KN 10 35 2.5

TDK C3225X5R1E106M 10 25

Capacitance

(µF)

37/48

Rated voltage

(V)

Maximum Irms

@100 kHz (A)

Application information PM6675AS

8.1.3 Output capacitor selection

Using tantalum or electrolytic capacitors, the selection is made referring to ESR and voltage
rating rather than by a specific capacitance value.

The output capacitor has to satisfy the output voltage ripple requirements. At a given
switching frequency, small inductor values are useful to reduce the size of the choke but
increase the inductor current ripple. Thus, to reduce the output voltage ripple a low ESR
capacitor is required.

To reduce jitter noise between different switching regulators in the system, it is preferable to
work with an output voltage ripple greater than 25 mV.

As far as it concerns the load transient requirements, the Equivalent Series Resistance
(ESR) of the output capacitor must satisfy this relationship:

Equation 37

where V

ESR∆≤

is the maximum tolerable ripple voltage.

RIPPLE

V

MAX,RIPPLE

I

MAX,L

In addition, the ESR must be enough high to meet stability requirements. The output
capacitor zero must be lower than the switching frequency:

Equation 38

ff

=>

ZSW

1

CESR2

⋅⋅π

out

If ceramic capacitors are used, the output voltage ripple due to inductor current ripple is
negligible; then the inductance could be smaller, reducing the size of the choke. In this case
it is important that the output capacitor can adsorb the inductor energy without generating
an over-voltage condition when the system changes from a full load to a no load condition.

The minimum output capacitance can be chosen by the following equation:

Equation 39

2

IL

⋅

C

=

min,OUT

MAX,LOAD

22

ViVf

−

where Vf is the output capacitor voltage after the load transient and Vi is the output capacitor
voltage before the load transient.

38/48

PM6675AS Application information

In Ta bl e 1 3 some tested polymer capacitors are listed.

Table 13. Evaluated output capacitors

Manufacturer Series

SANYO 4TPE220MF 220 4 V 15 to 25

HITACHI TNCB OE227MTRYF 220 2.5 V 25

8.1.4 MOSFETs selection

In SMPS converters, power management efficiency is a high level requirement, so the
power dissipation on the power switches becomes an important factor in switches selection.
Losses of high-side and low-side MOSFETs depend on their working condition.

Considering the high-side MOSFET, the power dissipation is calculated as:

Equation 40

Maximum conduction losses are approximately given by:

Equation 41

Capacitance

(µF)

4TPE150MI 150 4 V 18

4TPC220M 220 4 V 40

V

RP ⋅⋅=

DSonconduction

OUT

V

min.IN

Rated voltage

PPP +=

switchingconductionDHighSide

I

MAX,LOAD

(V)

ESR max

@100kHz (mΩ)

2

where R

is the MOSFET drain-source on-resistance.

DSon

Switching losses are approximately given by:

Equation 42

I

∆

P

switching

where tON and t

(max)I(V

LOADIN

=

are the turn-on and turn-off times of the MOSFET and depend on the

OFF

L

−⋅

2

2

ft)

⋅⋅

gate-driver current capability and the gate charge Q
low R

. Unfortunately low R

DSon

As general rule, the R

DSon

.

Q

MOSFETs have a great gate charge.

DSon

product should be minimized to find out the suitable

gate

(max)I(V

LOADINswon

+

. A greater efficiency is achieved with

gate

I

∆

L

+⋅

2

ft)

⋅⋅

swoff

2

MOSFET.

Logic-level MOSFETs are recommended, as long as low-side and high-side gate drivers are
powered by VVCC = +5 V. The breakdown voltage of the MOSFETs (VBRDSS) must be
greater than the maximum input voltage V

INmax

.

Below some tested high-side MOSFETs are listed.

39/48

Application information PM6675AS

≅

Table 14. Evaluated high-side MOSFETs

Manufacturer Type R

ST STS12NH3LL 10.5 12 30

ST STS7NF60L 17 25 60

IR IRF7811 9 18 30

(mΩ) Gate charge (Nc) Rated reverse voltage (V)

DSon

In buck converters the power dissipation of the synchronous MOSFET is mainly due to
conduction losses:

Equation 43

PP

conductionDLowSide

Maximum conduction losses occur at the maximum input voltage:

Equation 44

V

⎞

OUT

⎟

I

⎟

MAX,IN

⎠

as possible. When the high-side

DSon

2

MAX,LOAD

⎛
⎜

1RP ⋅

DSonconduction

−⋅=

⎜

V

⎝

The synchronous rectifier should have the lowest R
MOSFET turns on, high d
through its gate-drain capacitance C

of the phase node can bring up even the low-side gate

V/dt

, causing cross-conduction problem. Once again,

RES

the choice of the low-side MOSFET is a trade-off between on resistance and gate charge; a
good selection should minimizes the ratio C

RSS

where CGS = C

GS

ISS

- C

RSS

.

/ C

Below some tested low-side MOSFETs are listed.

Table 15. Evaluated low-side MOSFETs

Manufacturer Type R

ST STS12NH3LL 13.5 0.069 30

ST STS25NH3LL 40 0.011 30

IR IRF7811 24 0.054 30

Dual N-MOS can be used in applications with low output current.

Figure 16 shows some suitable dual MOSFETs for applications requiring about 3 A.

Table 16. Suitable dual MOSFETs

Manufacturer Type R

ST STS8DNH3LL 25 10 30

IR IRF7313 46 33 30

40/48

C

(mΩ)

DSon

(mΩ) Gate charge (nC)

DSon

GD

C

GS

Rated reverse voltage

(V)

Rated reverse

voltage (V)

PM6675AS Application information

8.1.5 Diode selection

A rectifier across the synchronous switch is recommended. The rectifier works as a voltage
clamp across the synchronous rectifier and reduces the negative inductor swing during the
dead time between turning the high-side MOSFET off and the synchronous rectifier on.
Moreover it increases the efficiency of the system.

The reverse voltage should be greater than the maximum input voltage V
minimum recovery reverse charge is preferable.

Table 17. Evaluated free-wheeling rectifiers

Manufacturer Type Forward voltage (V)

ST STPS1L30M 0.34 30

ST STPS1L30A 0.34 30

ST STPS1L60A 0.56 60

8.1.6 VOUT current limit setting

The valley current limit is set by R
current. The valley of the inductor current I

Equation 45

The output current limit depends on the current ripple as shown in Figure 38:

Figure 38. Valley current limit waveforms

Current

and a

INmax

Ta bl e 1 7 shows some evaluated diodes.

Rated reverse

voltage (V)

and must be chosen to support the maximum load

CSNS

Inductor current

Lvalley

LOADLvalley

is:

∆

I

L

−=

(max)II

2

Inductor current

MAX LOAD 2

MAX LOAD 1

Valley current limit

Time

Being fixed the valley threshold, the more the current ripple is greater, the more the DC
output current is greater. If an output current limit greater than over all the input voltage
range is required, the minimum current ripple must be considered in the previous formula.

Then the resistor R

CSNS

is:

Equation 46

⋅

IR

R

=

CSNS

41/48

LvalleyDSon

uA100

Application information PM6675AS

where R
effect and the worst case value in R

is the drain-source on-resistance low-side switch. Consider the temperature

DSon

calculation (typically +0.4 %/°C).

DSon

The accuracy of the valley current also depends on the offset of the internal comparator
(±6 mV).

The negative valley-current limit (if the device works in forced-PWM mode) is given by:

Equation 47

I =

NEG

8.1.7 All ceramic capacitors application

Design of external feedback network depends on the output voltage ripple across the output
capacitors ESR. If the ripple is great enough (at least 20 mV), the compensation network
simply consist of a C

Figure 39. Integrative compensation

capacitor.

INT

VREF

Ton One-shot

generator

+

PWM

Comparator

-

R

mV110

DSon

VSNS

VOUT

+

COMP

Integrator

CFILT

RINT

C

The stability of the system depends firstly on the output capacitor zero frequency. It must be
verified that:

Equation 48

INT

fkf

gm

ZoutSW

-

Vr=0.6

=⋅>

k

CR2

⋅π

outout

42/48

PM6675AS Application information

where k is a free design parameter greater than unity (k > 3) . It determinates the minimum
integrator capacitor value C

INT

:

Equation 49

g

C

>

INT

2

m

f

⎛

SW

f

−⋅π

⎜

⎜

k

⎝

Zout

Vref

⋅

Vo

⎞
⎟

⎟
⎠

If the ripple on pin COMP is greater than the integrator output dynamic (150 mV), an
additional capacitor C

could be added in order to reduce its amplitude. If q is the desired

filt

attenuation factor of the output ripple, select:

Equation 50

−⋅

INT

=

C

filt

In order to reduce noise on pin COMP, it’s possible to introduce a resistor R
with C

INT

and C

, realizes a low pass filter. The cutoff frequency must be much greater (10

filt

)q1(C

q

that, together

INT

or more times) than the switching frequency of the section:

Equation 51

1

CC

⋅

f2

CUT

FILTINT

CC

+

FILTINT

are unnecessary.

For most of applications both R

R

INT

=

INT

and C

⋅π

filt

If the ripple is very small (e.g. such as with ceramic capacitors), a further compensation
network, called “Virtual ESR” network, is needed. This additional part generates a triangular
ripple that substitutes the ESR output voltage ripple. The complete compensation scheme is
represented in

Figure 40.

Figure 40. Virtual ESR network

PWM Comparator

Ton

Generation

Block

L

R

C

INT

R1

C

R

INT

+

+

-

VREF

43/48

CFILT

gm

-

Integrator

0.6V

VOUT

Application information PM6675AS

Select C as shown:

Equation 52

C5C⋅>

INT

Then calculate R in order to have enough ripple voltage on the integrator input:

Equation 53

L

=

VESR

CR

⋅

Where R

R

is the new virtual output capacitor ESR. A good trade-off is to consider an

VERS

equivalent ESR of 30-50 mΩ, even though the choice depends on inductor current ripple.

Then choose R1 as follows:

Equation 54

⎞

⎛

1

⎟

⎜

R

⋅

1R

=

R

⎟

⎜

fC

π

Z

⎠

⎝

1

−
π

fC

Z

44/48

PM6675AS Package mechanical data

9 Package mechanical data

In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect. The category of
second Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com.

Table 18. VFQFPN-24 4mm x 4mm mechanical data

mm.

Dim.

Min Typ Max

A 0.80 0.90 1.00

A1 0.0 0.05

A2 0.65 0.80

D 4.00

D1 3.75

E4.00

E1 3.75

θ

P 0.240.420.60

e0.50

N 24.00

Nd 6.00

Ne 6.00

L 0.300.400.50

b 0.18 0.30

D2 1.95 2.10 2.25

E2 1.95 2.10 2.25

12°

45/48

Package mechanical data PM6675AS

Figure 41. Package dimensions

46/48

PM6675AS Revision history

10 Revision history

Table 19. Document revision history

Date Revision Changes

19-Feb-2008 1 Initial release.

47/48

PM6675AS

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