ST PM6675AS User Manual

Features

■ Switching section

– 4.5 V to 36 V input voltage range – 0.6 V, ±1 % voltage reference – Selectable 1.5 V fixed output voltage – Adjustable 0.6 V to 3.3 V output voltage – 1.237 V ±1 % reference voltage available – Very fast load transient response using

constant-on-time control loop

–No R

MOSFETs' R – Negative current limit – Latched OVP and UVP – Soft-start internally fixed at 3 ms – Selectable pulse skipping at light load – Selectable No-audible (33 kHz) pulse skip

mode – Ceramic output capacitors supported – Output voltage ripple compensation – Output soft-end

■ LDO regulator section

– Adjustable 0.6 V to 3.3 V output voltage – Selectable ±1 Apk or ±2 Apk current limit – Dedicated power-good signal – Ceramic output capacitors supported – Output soft-end

current sensing using low side

SENSE

DS(ON)

Applications

PM6675AS

High efficiency step-down controller

with embedded 2 A LDO regulator

VFQFPN-24 4x4

Description

The PM6675AS device consists of a single high efficiency step-down controller and an independent low drop-out (LDO) linear regulator.

The constant on-time (COT) architecture assures fast transient response supporting both electrolytic and ceramic output capacitors. An embedded integrator control loop compensates the DC voltage error due to the output ripple.

Selectable low-consumption mode allows the highest efficiency over a wide range of load conditions. The low-noise mode sets the minimum switching frequency to 33 kHz for audio-sensitive applications. The LDO linear regulator can sink and source up to 2 Apk. Two fixed current limit (±1 A- ±2 A) can be chosen.

An active soft-end is independently performed on both the switching and the linear regulators outputs when disabled.

■ Industrial application on 24 V

■ Graphic cards

■ Embedded computer systems

Table 1. Device summary

Order codes Package Packaging

PM6675AS

VFQFPN-24 4x4 (exposed pad)

PM6675ASTR Tape and reel

February 2008 Rev 1 1/48

Tu b e

www.st.com

Contents PM6675AS

Contents

1 Typical application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.1 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

3 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3.1 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3.3 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

6 Typical operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

7 Device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

7.1 Switching section - constant on-time pwm controller . . . . . . . . . . . . . . . . 16

7.1.1 Constant-on-time architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

7.1.2 Output ripple compensation and loop stability . . . . . . . . . . . . . . . . . . . . 19

7.1.3 Pulse-skip and no-audible pulse-skip modes . . . . . . . . . . . . . . . . . . . . . 24

7.1.4 Mode-of-operation selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

7.1.5 Current sensing and current limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

7.1.6 POR, UVLO and soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

7.1.7 Switching section power-good signal . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

7.1.8 Switching section output discharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

7.1.9 Gate drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

7.1.10 Reference voltage and bandgap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

7.1.11 Switching section OV and UV protections . . . . . . . . . . . . . . . . . . . . . . . 30

2/48

PM6675AS Contents

7.1.12 Device thermal protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

7.2 LDO linear regulator section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

7.2.1 LDO section current limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

7.2.2 LDO section soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

7.2.3 LDO section power-good signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

7.2.4 LDO section output discharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

8 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

8.1 External components selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

8.1.1 Inductor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

8.1.2 Input capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

8.1.3 Output capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

8.1.4 MOSFETs selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

8.1.5 Diode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

8.1.6 VOUT current limit setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

8.1.7 All ceramic capacitors application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

9 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

3/48

Typical application circuit PM6675AS

1 Typical application circuit

Figure 1. Application circuit

V

LDOIN

V

LDOIN

LDO PG

V

LDO

V

LDO

10

VSEL

C

IN4

IN4CIN4

C

OUT2

OUT2COUT2

23

4

24

2

1

VSEL

LIN

LPG

LOUT

LFB

LGND

SMPS PG

R

RLPR

LP

C

IN3

IN3CIN3

312618822

VCC

LILIM

NOSKIP

PM6675AS

PM6675A

SPG

SGND

5151413 711

VCC

AVCC

LEN

SWEN

C

B

B O

O O

O

VOSC

HGATE

T

PHASE

LGATE

VREF

COMP

C

BYP

BYPCBYP

IN2

CSNS

PGND

VSNS

21

20

17

19

16

9

+5V

C

BOOT

V

IN

V

IN

R

1

C

CINC

IN

R

2

R

LIM

LIMRLIM

IN

L

V

SMPS

V

SMPS

C

OUT

OUTCOUT

C

INT

INTCINT

4/48

PM6675AS Pin settings

2 Pin settings

2.1 Connections

Figure 2. Pin connection (through top view)

LOUT

LIN

LGND

LFB

NOSKIP

LPG

LIN

24

1

PM6675AS

PM6675A

BOOT

HGATE

PHASE

CSNS

19

18

VCC

LGATE

PGND

SPG

SGND

AVCC

LEN

SWEN

6

712

VSEL

VREF

VOSC

VSNS

VSEL

COMP

LILIM

13

5/48

Pin settings PM6675AS

2.2 Pin description

Table 2. Pin functions

N° Pin Function

1 LGND LDO power ground. Connect to negative terminal of VTT output capacitor.

2LFB

3NOSKIP

4LPG

5SGND

LDO remote sensing. Connect as close as possible to the load via a low noise PCB trace.

Pulse-skip/no-audible pulse-skip modes selector. See Section 7.1.4: Mode-of-operation selection

LDO section power-good signal (open drain output). High when LDO output voltage is within ±10 % of nominal value.

Ground Reference for analog circuitry, control logic and VTTREF buffer. Connect together with the thermal pad and VTTGND to a low impedance ground plane. See the Application Note for details.

6AVCC

7VREF

8VOSC

9 VSNS

10 VSEL

11 COMP

12 LILIM

13 SWEN

14 LEN

15 SPG

+5 V supply for internal logic. Connect to +5 V rail through a simple RC filtering network.

High accuracy output voltage reference (1.237 V) for multilevel pins setting. It can deliver up to 50 uA. Connect a 100 nF capacitor between VREF and SGND in order to enhance noise rejection.

Frequency Selection. Connect to the central tap of a resistor divider to set the desired switching frequency. The pin cannot be left floating. See

Section 7: Device description for details.

Switching section output remote sensing and discharge path during output soft-end. Connect as close as possible to the load via a low noise PCB trace.

Fixed output selector and feedback input for the switching controller. If VSEL pin voltage is higher than 4 V, the fixed 1.5 V output is selected. If

VSEL pin voltage is lower than 4 V, it is used as negative input of the error amplifier. See Section 7.1.4: Mode-of-operation selection for details.

DC voltage error compensation input pin for the switching section. Refer to Mode of Operation Selection section for more details.

Current limit selector for the LDO. Connect to SGND for ±1 A current limit or to +5 V for ±2 A current limit.

Switching Controller Enable. When tied to ground, the switching output is turned off and a soft-end is performed.

Linear Regulator Enable. When tied to ground, the LDO output is turned off and a soft-end is performed.

Switching Section power-good signal (open drain output). High when the switching regulator output voltage is within ±10 % of nominal value.

16 PGND Power ground for the switching section.

17 LGATE Low-side gate driver output.

18 VCC +5 V low-side gate driver supply. Bypass with a 100 nF capacitor to PGND.

6/48

PM6675AS Pin settings

Table 2. Pin functions (continued)

N° Pin Function

Current sense input for the switching section. This pin must be connected

19 CSNS

20 PHASE Switch node connection and return path for the high side gate driver.

21 HGATE High-Side Gate Driver Output

22 BOOT

through a resistor to the drain of the synchronous rectifier (RDSon sensing) to set the current limit threshold.

Bootstrap capacitor connection. Input for the supply voltage of the high-side gate driver.

23 LIN

24 LOUT

Linear Regulator Input. Bypass to LGND by a 10 µF ceramic capacitor for noise rejection enhancement.

LDO linear regulator output. Bypass with a 20 µF (2x10 µF MLCC) filter capacitor.

7/48

Electrical data PM6675AS

3 Electrical data

3.1 Maximum rating

Table 3. Absolute maximum ratings

(1)

Symbol Parameter Value Unit

V

AVC C

V

VCC

AVCC to SGND -0.3 to 6

VCC to SGND -0.3 to 6

PGND, LGND to SGND -0.3 to 0.3

HGATE and BOOT to PHASE -0.3 to 6

HGATE and BOOT to PGND -0.3 to 44

V

PHASE

P

TOT

1. Free air operating conditions unless otherwise specified. Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.

PHASE to SGND -0.3 to 38

LGATE to PGND -0.3 to V

CSNS, SPG, LEN, SWEN, LILIM, COMP, VSEL, VSNS, VOSC, VREF, NOSKIP to SGND

-0.3 to V

LPG,VREF, LOUT, LFB to SGND -0.3 to V

LIN, LOUT, LPG, LIN to LGND -0.3 to V

VCC

AVC C

+0.3

+ 0.3

Power dissipation @TA = 25°C 2.3 W

V

3.2 Thermal data

Table 4. Thermal data

Symbol Parameter Value Unit

R

T

thJA

STG

A

T

J

Thermal resistance junction to ambient 42 °C/W

Storage temperature range -50 to 150

Operating ambient temperature range -40 to 85

Junction operating temperature range -40 to 125

3.3 Recommended operating conditions

Table 5. Recommended operating conditions

Symbol Parameter Min Typ Max Unit

VIN Input voltage range 4.5 36

VAVCC IC supply voltage 4.5 5.5

VVCC IC supply voltage 4.5 5.5

°CT

V

8/48

PM6675AS Electrical characteristics

4 Electrical characteristics

Table 6. Electrical characteristics

T

= - 25 °C to 85 °C , VCC = AVCC = +5 V, LIN = 1.5 V and LOUT= 0.6 V if not otherwise

A

specified

(1)

.

Symbol Parameter Test condition Min Typ Max Unit

Supply section

I

Operating current

IN

(Switching + LDO)

SWEN, LEN, VSEL and NOSKIP connected to AVCC,

No load on LOUT

output

.

2

SWEN, VSEL and NOSKIP

I

SW

Operating current (switching)

connected to AVCC, LEN coneected

1

to SGND.

I

SHDN

UVLO

Shutdown operating current SWEN and LEN tied to SGND. 10 µA

AVCC Under Voltage Lockout upper threshold

AVCC Under Voltage Lockout lower threshold

4.1 4.25 4.4

3.85 4.0 4.1

UVLO hysteresis 70 mV

On-time (SMPS)

V

= 300 mV 530 630 730

OSC

V

= 500 mV 320 380 440

OSC

t

ON

On-time duration

VSEL low, NOSKIP low,

VVSNS = 2 V

mA

V

ns

OFF-TIME (SMPS)

t

OFFMIN

Minimum Off-Time 300 350 ns

Volt a g e re f e r enc e

Voltage accuracy 4.5 V< V

Load regulation -50 µA < I

Undervoltage Lockout Fault Threshold

SMPS output

V

OUT

SMPS fixed output voltage

Feedback output voltage accuracy

< 36 V 1.224 1.237 1.249 V

IN

< 50 µA -4 4

VREF

800

1.5 V

VSEL connected to AVCC, NOSKIP tied to SGND, No Load

-1.5 1.5 %

mV

9/48

Electrical characteristics PM6675AS

Table 6. Electrical characteristics (continued)

T

= -25 °C to 85 °C , VCC = AVCC = +5 V, LIN = 1.5 V and LOUT= 0.6 V if not otherwise

A

specified.

Symbol Parameter Test condition Min Typ Max Unit

Current limit and zero crossing comparator

(1)

I

CSNS

CSNS input bias current 90 100 110 µA

Comparator offset -6 6

V

ZC,OFFS

Positive current limit threshold V

fixed negative current limit threshold

Zero crossing comparator offset -11 -5 1

PGND

- V

CSNS

100

110

High and low side gate drivers

HGATE high state (pullup) 2.0 3

HGATE driver on-resistance

HGATE low state (pulldown) 1.8 2.7

LGATE high state (pullup) 1.4 2.1

LGATE driver on-resistance

LGATE low state (pulldown) 0.6 0.9

UVP/OVP protections and PGOOD signals

OVP Over voltage threshold 112 115 118

UVP Under voltage threshold 67 70 73

SMPS upper threshold 107 110 113

SMPS lower threshold 86 90 93

PGOOD

LDO upper threshold 107 110 113

LDO lower threshold 86 90 93

I

PG,LEAK

V

PG,LOW

SPG and LPG leakeage current SPG and LPG forced to 5.5 V 1 µA

SPG and LPG low level voltage I

LPG,SINK

= I

SPG,SINK

= 4 mA 150 250 mV

Soft-start section (SMPS)

mV

Ω

%

Soft-start ramp time (4 steps current limit)

Soft-start current limit step 25 µA

Soft end section

Switching section discharge resistance

LDO section discharge resistance 15 25 35

LDO section

LDO reference voltage 600

V

LREF

LDO output accuracy respect to VREF

-1 mA < I

-1 A < I

10/48

234ms

15 25 35

< 1 mA -20 20

LDO

< 1 A -25 25

LDO

Ω

mV

PM6675AS Electrical characteristics

Table 6. Electrical characteristics (continued)

T

= -25 °C to 85 °C , VCC = AVCC = +5 V, LIN = 1.5 V and LOUT= 0.6 V if not otherwise

A

specified.

Symbol Parameter Test condition Min Typ Max Unit

LDO sink current limit

I

LDO,CL

LDO source current limit

I

LIN,BIAS

I

LFB,BIAS

I

LFB,LEAK

Power management section

LDO input bias current, on LEN connected to AVCC, no load 1 10

LDO input bias current, off LEN = 0 V, no load 1

LFB input bias current

LFB leakage current LEN=0V, V

(1)

V

LFB

V

LFB

0.9

> V

⋅ V

, LILIM = 5 V -3 -2.3 -2

LREF

, LILIM = 0 V -1.6 -1.3 -1

LREF

< V

LREF

LFB

< V

LILIM=5V

0.9

⋅ V

< V

LREF

LFB

< V

LILIM = 0 V

V

LFB

V

LFB

< 0.9 ⋅ V < 0.9 ⋅ V

, LILIM = 5 V 1 1.3 1.6

LREF

, LILIM = 0 V 0.5 0.8 1.1

LREF

LEN connected to AVCC

VLFB = 0.6 V

= 0.6V -1 1

LFB

LREF

,

22.43

A

,

11.31.6

µA

-1 1

V

AVC C

-0.7

V

AVC C

-0.8

V

AVC C

-1.3

V

AVC C

-1.5

V

VTHVSEL

V

VTHNOSKIP

VSEL pin thresholds

NOSKIP pin thresholds

Fixed mode

Adjustable mode

Forced-PWM mode

No-audible mode 1.0

Pulse-skip mode 0.5

VTHLEN

VTHLILIM

,

LEN, SWEN turn on level 1.6

LILIM pin thresholds

±2A LDO current limit

VAVCC

-0.8

V

VTHSWEN

V

LEN, SWEN turn off level 0.4

±1A LDO current limit 0.5

I

IN,LEAK

IN3,LEAK

I

OSC,LEAK

Logic input leakage current LEN, SWEN and LILIM = 5 V 10

Multilevel input leakage current VSEL and NOSKIP = 5 V 10

VOSC pin leakage current VOSC = 1 V 1

Thermal shutdown

T

SHDN

1. Specifications referred to TJ = TA. All the parameters at operating temperatures extremes are guaranteed by design and statistical correlation (not production tested).

2. Guaranteed by design. Not production tested.

Shutdown temperature

(2)

150 °C

V

µAI

11/48

Block diagram PM6675AS

5 Block diagram

Figure 3. Functional and block diagram

Vr = 0.6V

LFB

LIN

LOUT

LGND

LPG

SGND

LDS

Vr +10

VREF

_

+

LEN

%

+

-

+

-

Vr -10

UVP/OVP

0.6V

1.236V

1.236V Bandgap

Bandgap

LILIM

%

VOSC

Ton

1-shot

Ton

min

1-shot

Toff

min

1-shot

Anti Cr oss

Anti Cr oss Conduction

Conduction

SWEN

Vr

BOOT

Level

Level shifter

shifter

Zero Crossing

& Current

Limit

_

VREF

+

Vr +10

%

Vr +10

%

Vr +10

%

+

_

m

g

+

Vr

-

+

-

Vr -10

%

Vr -10

%

Vr -10

%

HGATE

PHASE

VCC

LGATE

PGND

CSNS

COMP

SPG

AVCC

LILIM

NOSKIP

Table 7. Legend

UVLO

Thermal Shutdown

LEN

SWEN

CONTROL LOGIC

SWEN

LDS

VSEL

LDS

SWEN

LDS

SWEN

LDS

SWEN Switching controller enable

LEN LDO regulator enable

LDS LDO output discharge enable

SDS Switching output discharge enable

LILIM LDO regulator current limit

12/48

LEN

VSNS

SDS

fixadj

PM6675AS Typical operating characteristics

6 Typical operating characteristics

Figure 4. Efficiency vs output load

F

= 330 kHz VOUT=1.5 V,

SW

100

90

80

70

60

50

40

Efficiency [%]

30

20

10

0

0.001 0.010 0.100 1.000 10.000

VIN = 24 V

VOUT - Efficiency

Current [A]

Forced PWM

Pulse Ski p

Non Audible PS

Figure 5. Switching frequency vs output

current, VOUT = 1.5 V, VIN = 24 V

SW Frequency VS V OUT Load

500

400

300

200

Frequency [kHz]

100

0

0.010 0.100 1.000 10.000

Current [A]

Forced PWM

Pulse Skip

Non Audible PS

Figure 6. Switching frequency vs input

voltage, VOUT = 1.5 V, IVOUT = 2 A,

550

450

350

Frequency [kHz]

250

4142434

forced PWM mode

SW Frequency VS Input Voltage

Volt age [V]

Figure 8. LOUT load regulation

LDOIN = VOUT, VOUT in forced

1.090

1.080

1.070

1.060

1.050

Voltage [ V]

1.040

1.030

1.020

-1.500 -1.000 -0.500 0.000 0.500 1.000 1.500

PWM mode

LOUT - Load Regulation

Current [A]

Figure 7. VOUT load regulation, VIN = 24 V

VOUT - Load Regulation

1.540

1.535

1.530

1.525

1.520

1.515

Voltage [V]

1.510

1.505

1.500

0.001 0.010 0.100 1.000 10.000

Current [A]

Forced PWM

Pulse Skip

Non Audible PS

Figure 9. VOUT = 1.5 V, VIN = 24 V,

IVOUT = 0 A, pulse-skip mode

13/48

Typical operating characteristics PM6675AS

Figure 10. VOUT = 1.5V , VIN = 24V,

IVOUT = 0 A, forced-PWM mode

Figure 12. VOUT Soft-start @150mΩ load,

pulse-skip mode

Figure 11. VOUT = 1.5 V, VIN = 24 V, no load,

Non-audible pulse-skip mode (33 kHz)

Figure 13. LOUT turn on, VOUT in pulse-skip

mode

Figure 14. VOUT Load Transient (VIN = 24 V,

LOAD = 0 A -> 7 A @2.5 A/µs).

14/48

pulse-skip mode

Figure 15. LOUT load transient (VIN = 24 V,

LOAD = -1.5 A -> 1.5 A @2.5 A/µs). pulse-skip mode

PM6675AS Typical operating characteristics

Figure 16. VOUT and LOUT output voltages.

VOUT soft-end. LOUT powered by an auxiliary rail

Figure 18. UV protection, pulse-skip mode

LOUT powered by an auxiliary rail

Figure 17. VOUT and LOUT output voltages

LOUT soft-end

Figure 19. OV protection, pulse-skip mode

Figure 20. VOUT current limit protection

during a load transient (0 A to 9 A @2.5A/µs)

Figure 21. LOUT current limit during an output

short

15/48