ST PM6670S User Manual

Complete DDR2/3 memory power supply controller

Features

■ Switching section (VDDQ)

– 4.5 V to 28 V input voltage range – 0.9 V, ±1 % voltage reference – 1.8 V (DDR2) or 1.5 V (DDR3) fixed output

voltages – 0.9 V to 2.6 V adjustable output voltage – 1.237 V ±1 % reference voltage available – Very fast load transient response using

constant on-time control loop –No R

MOSFET’s R – Negative current limit – Latched OVP and UVP – Soft-start internally fixed at 3 ms – Selectable pulse skipping at light load – Selectable no-audible (33 kHz) pulse skip

mode – Ceramic output capacitors supported – Output voltage ripple compensation

■ VTT LDO and VTTREF

– 2 Apk LDO with foldback for VTT – Remote VTT sensing – High-Z VTT output in S3 – Ceramic output capacitors supported – ±15 mA low noise buffered reference

Applications

■ DDR2/3 memory supply

■ Notebook computers

■ Handheld and PDAs

■ CPU and chipset I/O supplies

■ SSTL18, SSTL15 and HSTL bus termination

current sensing using low side

SENSE

DS(ON)

PM6670S

VFQFPN-24 4x4

Description

The device PM6670S is a complete DDR2/3 power supply regulator designed to meet JEDEC specifications.

It integrates a constant on-time (COT) buck controller, a 2 Apk sink/source low drop out regulator and a 15 mA low noise buffered reference.

The COT architecture assures fast transient response supporting both electrolytic and ceramic output capacitors. An embedded integrator control loop compensates the DC voltage error due to the output ripple.

The 2 Apk sink/source linear regulator provides the memory termination voltage with fast load transient response.

The device is fully compliant with system sleep states S3 and S4/S5, providing LDO output high impedance in suspend-to-RAM and tracking discharge of all outputs in suspend-to-disk.

Table 1. Device summary

Order code Package Packaging

PM6670S

PM6670STR Tape and reel

VFQFPN-24 4x4

(Exposed pad)

Tube

February 2010 Doc ID 14432 Rev 4 1/54

www.st.com

54

Contents PM6670S

Contents

1 Typical application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.1 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

3 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3.1 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3.3 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

5 Typical operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

7 Device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

7.1 VDDQ section - constant on-time PWM controller . . . . . . . . . . . . . . . . . . 21

7.1.1 Constant-on-time architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

7.1.2 Output ripple compensation and loop stability . . . . . . . . . . . . . . . . . . . . 24

7.1.3 Pulse-skip and no-audible pulse-skip modes . . . . . . . . . . . . . . . . . . . . . 28

7.1.4 Mode-of-operation selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

7.1.5 Current sensing and current limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

7.1.6 POR, UVLO and soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

7.1.7 Power Good signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

7.1.8 VDDQ output discharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

7.1.9 Gate drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

7.1.10 Reference voltage and bandgap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

7.1.11 Over voltage and under voltage protections . . . . . . . . . . . . . . . . . . . . . 36

7.1.12 Device thermal protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

7.2 VTTREF buffered reference and VTT LDO section . . . . . . . . . . . . . . . . . 37

7.2.1 VTT and VTTREF Soft-Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

7.2.2 VTTREF and VTT outputs discharge . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

2/54 Doc ID 14432 Rev 4

PM6670S Contents

7.3 S3 and S5 power management pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

8 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

8.1 External components selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

8.1.1 Inductor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

8.1.2 Input capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

8.1.3 Output capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

8.1.4 MOSFETs selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

8.1.5 Diode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

8.1.6 VDDQ current limit setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

8.1.7 All ceramic capacitors application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

9 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Doc ID 14432 Rev 4 3/54

Typical application circuit PM6670S

V

(

)

1 Typical application circuit

Figure 1. Application circuit

DDQ

LDO input

C

TTREF

C

OUT3

11

IN4

23

4

2

24

TT

1

C

OUT2

C

IN3

3 12 6 18 8

SEL

DSCG

AVCC

MODE

LDOIN

VTTREF

VTTSNS

VTT

VTTGND

PM6670S

SGND

PG

S3

5 15 14 13 7 10

R

LP

+5V

IN

C

IN2

VCC

VOSC

BOOT

HGATE

PHASE

LGATE

COMP

VREF

S5

C

BYP

CSNS

PGND

VSNS

C

BOOT

21

20

17

19

R

16

9

LIM

R

1

C

R

2

IN

L

DDQ

C

OUT

C

INT

4/54 Doc ID 14432 Rev 4

PM6670S Pin settings

2 Pin settings

2.1 Connections

Figure 2. Pin connection (through top view)

VTT

LDOIN

VTTGND

VTTSNS

DDRSEL

VTTREF

LDOIN

24

1

PM6670

HGATE

BOOT

PHASE

CSNS

19

18

VCC

LGATE

PGND

S

PG

SGND

AVCC

S3

S5

6

7

VREF

VOSC

VSNS

MODE

COMP

13

12

DSCG

S5

Doc ID 14432 Rev 4 5/54

Pin settings PM6670S

2.2 Pin description

Table 2. Pin functions

N° Pin Function

1 VTTGND LDO power ground. Connect to negative terminal of VTT output capacitor.

2VTTSNS

3DDRSEL

4VTTREF

5SGND

6AVCC

7VREF

8VOSC

9 VSNS

10 MODE

LDO remote sensing. Connect as close as possible to the load via a low noise PCB trace.

DDR voltage selector (if MODE is tied to VCC) or pulse-skip/no-audible pulse-skip selector in adjustable mode (MODE voltage lower than 3 V). See

Section 7.1.4: Mode-of-operation selection on page 30.

Low noise buffered DDR reference voltage. A 22 nF (minimum) ceramic bypass capacitor is required in order to achieve stability.

Ground reference for analog circuitry, control logic and VTTREF buffer. Connect together with the thermal pad and VTTGND to a low impedance ground plane. See the Application Note for details.

+5 V supply for internal logic. Connect to +5 V rail through a simple RC filtering network.

High accuracy output voltage reference (1.237 V) for multilevel pins setting. It can deliver up to 50 μA. Connect a 100 nF capacitor between VREF and SGND in order to enhance noise rejection.

Frequency selection. Connect to the central tap of a resistor divider to set the desired switching frequency. The pin cannot be left floating. See

Section 7: Device description on page 20

VDDQ output remote sensing. Discharge path for VDDQ in Non-Tracking Discharge. Input for internal resistor divider that provides VDDQ/2 to VTTREF and VTT. Connect as close as possible to the load via a low noise PCB trace.

Mode of operation selector. If MODE pin voltage is higher than 4 V, the fixed output mode is selected. If MODE pin voltage is lower than 4 V, it is used as negative input of the error amplifier. See Section 7.1.4: Mode-of-operation

selection on page 30.

11 COMP

12 DSCG

13 S5

14 S3

15 PG

16 PGND Power ground for the switching section.

17 LGATE Low-side gate driver output.

6/54 Doc ID 14432 Rev 4

DC voltage error compensation Input for the switching section. Refer

Section 7.1.4: Mode-of-operation selection on page 30.

Discharge mode selection. Refer to Section 7.1.8: VDDQ output discharge

on page 34 for tracking/non-tracking discharge or no-discharge options.

Switching controller enable. Connect to S5 system status signal to meet S0S5 power management states compliance. See Section 7.3: S3 and S5

power management pins on page 38, S5 pin can't be left floating.

Linear regulator enable. Connect to S3 system status signal to meet S0-S5 power management states compliance. See Section 7.3: S3 and S5 power

management pins on page 38, S3 pin can't be left floating.

Power Good signal (open drain output). High when VDDQ output voltage is within ±10 % of nominal value.

PM6670S Pin settings

Table 2. Pin functions (continued)

N° Pin Function

18 VCC +5 V low-side gate driver supply. Bypass with a 100 nF capacitor to PGND.

Current sense input for the switching section. This pin must be connected

19 CSNS

20 PHASE Switch node connection and return path for the high-side gate driver.

21 HGATE High-side gate driver output

22 BOOT

23 LDOIN

24 VTT

through a resistor to the drain of the synchronous rectifier (R set the current limit threshold.

Bootstrap capacitor connection. Positive supply input of the high-side gate driver.

Linear regulator input. Connect to VDDQ in normal configuration or to a lower supply to reduce the power dissipation. A 10 μF bypass ceramic capacitor is suggested for noise rejection enhancement. See Section 7:

Device description on page 20

LDO linear regulator output. Bypass with a 20 μF (2x10 μF MLCC) filter capacitor.

DSon

sensing) to

Doc ID 14432 Rev 4 7/54

Electrical data PM6670S

3 Electrical data

3.1 Maximum rating

Table 3. Absolute maximum ratings

(1)

Symbol Parameter Value Unit

V

AVC C

V

VCC

AVCC to SGND -0.3 to 6

VCC to SGND -0.3 to 6

PGND, VTTGND to SGND -0.3 to 0.3

HGATE and BOOT to PHASE -0.3 to 6

HGATE and BOOT to PGND -0.3 to 44

V

PHASE

PHASE to SGND

LGATE to PGND -0.3 to V

CSNS, PG, S3, S5, DSCG, COMP, VSNS, VOSC, VREF, MODE, DDRSEL to GND

VTTREF, VREF, VTT, VTTSNS to SGND -0.3 to V

LDOIN, VTT, VTTREF, LDOIN to VTTGND -0.3 to V

P

TOT

1. Free air operating conditions unless otherwise specified. Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.

2. PHASE to SGND up to -2.5 V for t < 10 ns

Power dissipation @TA = 25 °C 2.3 W

(2)

-0.3 to 38

-0.3 to V

CC

AVC C

+0.3

+ 0.3

V

3.2 Thermal data

Table 4. Thermal data

Symbol Parameter Value Unit

R

thJA

T

STG

T

A

T

J

8/54 Doc ID 14432 Rev 4

Thermal resistance junction to ambient 42 °C/W

Storage temperature range - 50 to 150 °C

Operating ambient temperature range - 40 to 85 °C

Junction operating temperature range - 40 to 125 °C

PM6670S Electrical data

3.3 Recommended operating conditions

Table 5. Recommended operating conditions

Val ues

Symbol Parameter

Min Typ Max

Unit

V

AVC C

V

VCC

IN

Input voltage range 4.5 - 28

IC supply voltage 4.5 - 5.5

VV

Doc ID 14432 Rev 4 9/54

Electrical characteristics PM6670S

4 Electrical characteristics

TA = 0 °C to 85 °C, VCC = AVCC = +5 V and LDOIN connected to VDDQ output if not otherwise specified

Table 6. Electrical characteristics

Symbol Parameter Test condition

Supply section

I

IN

I

STR

I

SH

UVLO

Operating current

Operating current in STR

Operating current in shutdown

AVCC under voltage lockout upper threshold

AVCC under voltage lockout lower threshold

UVLO hysteresis 70 mV

(a)

S3, S5, MODE and DDRSEL connected to AVCC, no load on VTT and VTTREF outputs. VCC connected to AVCC

S5, MODE and DDRSEL connected to AVCC, S3 tied to SGND, no load on VTTREF.

VCC connected to AVCC

S3 and S5 tied to SGND. Discharge mode active. VCC connected to AVCC

Val ues

Unit

Min Typ Max

0.8 2

mA

0.6 1

110μA

4.1 4.25 4.4

V

3.85 4.0 4.1

ON-time (SMPS)

t

ON

On-time duration

MODE and DDRSEL high,

V

= 2 V

VSNS

VOSC

VOSC = 500 mV 390 450 510

OFF-time (SMPS)

t

OFFMIN

Minimum Off time 300 350 ns

Volt a g e re f e ren c e

Voltage accuracy 4.5 V < V Load regulation -50 μA< I

< 25 V 1.224 1.237 1.249 V

IN

< 50 μA-44mV

VREF

Undervoltage lockout fault threshold

a. TA = TJ. All parameters at operating temperature extremes are guaranteed by design and statistical analysis

(not production tested)

10/54 Doc ID 14432 Rev 4

= 300 mV 650 750 850

800

ns

PM6670S Electrical characteristics

Table 6. Electrical characteristics (continued)

Val ues

Symbol Parameter Test condition

Min Typ Max

VDDQ output

Unit

MODE connected to AVCC, DDRSEL tied to SGND, No load

MODE and DDRSEL connected to AVCC, no load

V

VDDQ

VDDQ output voltage, DDR3

VDDQ output voltage, DDR2

Feedback accuracy -1.5 1.5 %

Current limit and zero crossing comparator

I

CSNS

CSNS input bias current 110 120 130 μA

Comparator offset -6 6 mV

Positive current limit threshold

Rsense = 1 kΩ V

- V

PGND

CSNS

Fixed negative current limit threshold

V

ZC,OFFS

Zero crossing comparator offset

High and low side gate drivers

HGATE high state (pull-up) 2.0 3

HGATE driver on-resistance

HGATE low state (pull-down) 1.8 2.7

LGATE high state (pull-up) 1.4 2.1

LGATE driver on-resistance

LGATE low state (pull-down) 0.6 0.9

UVP/OVP protections and PGOOD SIGNAL (SMPS only)

1.5 V

1.8

120 mV

110 mV

-11 -5 1 mV

Ω

OVP Over voltage threshold 112 115 118

UVP Under voltage threshold 67 70 73

Power Good upper threshold 107 110 113

PGOOD

Power Good lower threshold 86 90 93

I

PG,LEAK

V

PG,LOW

PG leakage current PG forced to 5 V 1 μA

PG low-level voltage I

= 4 mA 150 250 mV

PG,SINK

Soft start section (SMPS)

Soft-start ramp time (4 steps current limit)

1.5 3 4 ms

Soft-start current limit step 30 μA

Doc ID 14432 Rev 4 11/54

%

Electrical characteristics PM6670S

Table 6. Electrical characteristics (continued)

Val ues

Symbol Parameter Test condition

Soft end section

VDDQ discharge resistance in non-tracking discharge mode

VTT discharge resistance in non-tracking discharge mode

VTTREF discharge resistance in non-tracking discharge mode

VDDQ output threshold synchronous for final tracking to non-tracking discharge transition

LDO section

V

TT

I

LDOIN,ON

I

LDOIN,

STR

I

LDOIN,

STD

I

VTTSNS,

BIAS

I

VTTSNS,

LEAK

I

VTT,LEAK

V

LDO input bias current in full-on state

LDO input bias current in suspend-to-RAM state

LDO input bias current in suspend-to-disk state

VTTSNS bias current

VTTSNS leakage current

VTT leakage current

LDO linear regulator output voltage (DDR2)

LDO linear regulator output voltage (DDR3)

VTT

LDO output accuracy respect to VTTREF

S3 = S5 = +5 V, No load on VTT 1 10

S3 = 0 V, S5 = +5 V, No Load on VTT

S3 = S5 = 0 V, No Load on VTT 1

S3 = +5 V, S5 = +5 V, V

VTTSNS

= V

VSNS

/2

S3 = 0 V, S5 = +5 V, V

VTTSNS

= V

VSNS

/2

S3 = 0 V, S5 = +5 V,

= V

V

VTT

S3 = S5= +5 V, I

VSNS

/2

VTT

= 0 A,

MODE = DDRSEL = +5 V

S3 = S5= +5 V, I

VTT

= 0 A,

MODE = +5 V, DDRSEL = 0 V

S3 = S5 = MODE = + 5 V,

-1 mA < I

VTT

< 1 mA

S3 = S5 = MODE = +5 V,

-1 A < I

VTT

< 1 A

S3 = S5 = MODE = +5 V,

-2 A < I

VTT

< 2 A

Min Typ Max

15 25 35

11.52 kΩ

0.2 0.4 0.6 V

10

-10 10

0.9

0.75

-20 20

-25 25

-35 35

Unit

Ω

μA

1

V

mV

12/54 Doc ID 14432 Rev 4

PM6670S Electrical characteristics

Table 6. Electrical characteristics (continued)

Val ues

Symbol Parameter Test condition

V

I

VTT,CL

LDO source current limit

LDO sink current limit

VTT

V

VTT

V

VTT

V

VTT

< 1.10*(V

> 1.10*(V

> 0.90*(V

< 0.90*(V

/2) 2 2.3 3

VSNS

/2) 1 1.15 1.4

VSNS

/2) -3 -2.3 -2

VSNS

/2) -1.4 -1.15 -1

VSNS

VTTREF section

Min Typ Max

Unit

A

VTTREF output voltage I

V

VTTREF

VTTREF output voltage accuracy respect to VSNS/2

I

VTTREF

VTTREF current limit VTTREF= 0 or VSNS ±40 mA

Power management section

Turn OFF level 0.4

S3,S5

Turn ON level 1.6

MODE pin high level threshold

V

MODE

MODE pin low level threshold

DDRSEL pin high level threshold

V

DDRSEL

DDRSEL pin middle level window

DDRSEL pin low level threshold

DSCG pin high level threshold

V

DSCG

I

IN,LEAK

I

IN3,LEAK

I

OSC,

LEAK

DSCG pin middle level window

DSCG pin low level threshold

Logic inputs leakage current S3, S5 = 5 V 10

Multilevel inputs leakage current

VOSC input leakage current VOSC = 500 mV 1

Thermal shutdown

T

SHDN

1. Guaranteed by design. Not production tested.

Shutdown temperature

(1)

VSNS

= 0 A, V

VTTREF

= 1.8 V

VSNS

< 15 mA,

VTTREF

-15 mA < I V

MODE, DDRSEL and DSCG = 5 V

= 1.8 V 0.9 V

-2 2 %

V

AVC C

-0.7

VAVCC -

1.3

V

AVC C

-0.8

1.0

V

AVC C

-0.8

1.0 2.0

VAVCC -

1.5

0.5

10

150 °C

μA

V

Doc ID 14432 Rev 4 13/54

Typical operating characteristics PM6670S

pg

5 Typical operating characteristics

Figure 3. Efficiency vs

100

90

80

70

60

50

40

Efficiency (%)

30

20

10

0

0.001 0.01 0.1 1 10

load - 1.5 V and 1.8 V, V

Output current (A)

= 12 V

IN

DDR2 - Forced PWM

DDR2 - Forced PWM DDR2 - No-Audible P-S

DDR2 - No-Audible P-S

DDR2 - Pulse-Skip

DDR2 - Pulse-Skip DDR3 - Forced PWM

DDR3 - Forced PWM

DDR3 - No-Audible P-S

DDR3 - No-Audible P-S DDR3 - Pulse-Skip

DDR3 - Pulse-Skip

Figure 4. Switching frequency vs

load - 1.8 V, VIN = 12 V

500

500 450

450 400

400 350

350 300

300 250

250 200

200 150

150 100

100

Swiching frequency (kHz)

50

0

0.001 0.01 0.1 1 10

Forced PWM

No-Audible P-S

Pulse-Skip

Output current (A)

Figure 5. Switching frequency vs

500

450

400

350

300

250

Switching frequency (kHz)

200

150

0.0 5.0 10.0 15.0 20.0 25.0 30.0

Figure 7. VDDQ line regulation, 1.8 V, 7 A Figure 8. VDDQ line regulation, 1.5 V, 7 A

1.8000

1.7990

1.7980

1.7970

1.7960

Output vol tage (V)

1.7950

1.7940

input voltage, 1.8 V

Input voltage (V)

Forced PWM

No-Audible P-S

Pulse-Skip

0.0 5.0 10.0 15.0 20.0 25.0 30.0

Input volt age (V)

Figure 6. Switching frequency vs

input voltage, 1.5 V

500

450

400

350

300

250

Switchin g frequency (kHz)

200

150

0.0 5.0 1 0.0 15.0 20.0 25.0 30.0

1.4980

1.4975

1.4970

1.4965

1.4960

1.4955

Output voltag e (V)

1.4950

1.4945

1.4940

0.0 5.0 10.0 15.0 20.0 25.0 30.0

Input voltage (V)

Forced PWM

No-Audible P-S

Pulse-Skip

Input voltage (V )

14/54 Doc ID 14432 Rev 4

PM6670S Typical operating characteristics

Figure 9. VDDQ load regulation, 1.8 V,

V

= 12 V

1.860

1.850

1.840

1.830

1.820

Output voltage (V)

1.810

1.800

0.001 0.01 0.1 1 10

IN

Forced PWM

No-Audible P-S

No-Audible P-S Pulse-Skip

Pulse-Skip

Output current (A)

Figure 10. VDDQ load regulation, 1.5 V,

V

= 12 V

IN

1.530

Forced PWM

1.520

1.510

1.500

1.490

1.480

Output voltage (V)

1.470

0.001 0.01 0.1 1 10

Output current (A)

Forced PWM No-Audible P-S

No-Audible P-S Pulse-Skip

Pulse-Skip

Figure 11. VTT load regulation, 0.9 V,

0.940

0.930

0.920

0.910

0.900

Output volt age (V)

0.890

0.880

LDOIN

-2.5 -1.5 -0.5 0.5 1.5 2.5

= 1.8 V

Output current (A)

Figure 13. VTTREF load regulation, 0.9 V,

VSNS = 1.8 V

Figure 12. VTT load regulation, 0.75 V,

LDOIN = 1.5 V

0.790

0.780

0.770

0.760

0.750

Output voltage (V)

0.740

0.730

-2.5 -1.5 -0.5 0.5 1.5 2.5

Output current (A)

Figure 14. No-audible pulse-skip waveforms

Doc ID 14432 Rev 4 15/54

Typical operating characteristics PM6670S

Figure 15. Power-up sequence - AVCC above

UVLO

Figure 17. -1.8 A to 1.8 A VTT

load transient, 0.9 V

Figure 16. VDDQ soft-start, 1.8 V, heavy load

Figure 18. 0 mA to 9 mA VTTREF

load transient, 0.9 V

16/54 Doc ID 14432 Rev 4

PM6670S Typical operating characteristics

Figure 19. Non-tracking (soft) discharge Figure 20. Tracking (fast) discharge,

LDOIN = VDDQ

Figure 21. 0 A to 10 A VDDQ

load transient, PWM

Figure 22. 10 A to 0 A VDDQ

load transient, PWM

Doc ID 14432 Rev 4 17/54