ST PM6670AS User Manual
Complete DDR2/3 memory power supply controller
Features
■ Switching section (VDDQ)
– 4.5 V to 36 V input voltage range
– 0.9 V, ±1% voltage reference
– 1.8 V (DDR2) or 1.5 V (DDR3) fixed output
voltages
– 0.9 V to 2.6 V adjustable output voltage
– 1.237 V ±1% reference voltage available
– Very fast load transient response using
constant-on-time control loop
–No R
MOSFETs' R
– Negative current limit
– Latched OVP and UVP
– Soft-start internally fixed at 3 ms
– Selectable pulse skipping at light load
– selectable no-audible (33 kHz) pulse skip
mode
– Ceramic output capacitors supported
– Output voltage ripple compensation
■ VTT LDO and VTTREF
– 2 Apk LDO with foldback for VTT
– Remote VTT sensing
– High-Z VTT output in S3
– Ceramic output capacitors supported
– ±15 mA Low noise buffered reference
Applications
■ DDR2/3 memory supply
■ Digital TV system
■ SSTL18, SSTL15 and HSTL bus termination
current sensing using low side
SENSE
DS(ON)
PM6670AS
Description
The device PM6670AS is a complete DDR2/3
power supply regulator designed to meet JEDEC
specifications.
It integrates a constant on-time (COT) buck
controller, a 2 Apk sink/source low drop out
regulator and a 15 mA low noise buffered
reference.
The COT architecture assures fast transient
response supporting both electrolytic and ceramic
output capacitors. An embedded integrator
control loop compensates the DC voltage error
due to the output ripple.
The 2 Apk sink/source linear regulator provides
the memory termination voltage with fast load
transient response.
The device is full compliant with system sleep
states S3 and S4/S5, providing LDO output high
impedance in Suspend-To-RAM and Tracking
Discharge of all outputs in Suspend-To-Disk.
Table 1. Device summary
Order codes Package Packaging
PM6670AS
VFQFPN-24 4x4 (Exposed pad)
PM6670ASTR Tape and reel
February 2010 Doc ID 14436 Rev 2 1/53
Tu b e
www.st.com
53
Contents PM6670AS
Contents
1 Typical application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.1 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.3 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5 Typical operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7 Device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.1 VDDQ section - constant on-time PWM controller . . . . . . . . . . . . . . . . . . 20
7.1.1 Constant-on-time architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7.1.2 Output ripple compensation and loop stability . . . . . . . . . . . . . . . . . . . . 23
7.1.3 Pulse-skip and no-audible pulse-skip modes . . . . . . . . . . . . . . . . . . . . . 28
7.1.4 Mode-of-operation selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7.1.5 Current sensing and current limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.1.6 POR, UVLO and soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7.1.7 Power-Good signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.1.8 VDDQ output discharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.1.9 Gate drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.1.10 Reference voltage and bandgap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.1.11 Over voltage and under voltage protections . . . . . . . . . . . . . . . . . . . . . 35
7.1.12 Device thermal protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7.2 VTTREF buffered reference and VTT LDO section . . . . . . . . . . . . . . . . . 36
7.2.1 VTT and VTTREF soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.2.2 VTTREF and VTT outputs discharge . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
2/53 Doc ID 14436 Rev 2
PM6670AS Contents
7.3 S3 and S5 power management pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
8 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
8.1 External components selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
8.1.1 Inductor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
8.1.2 Input capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
8.1.3 Output capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
8.1.4 MOSFETs selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
8.1.5 Diode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
8.1.6 VDDQ current limit setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
8.1.7 All ceramic capacitors application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
9 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Doc ID 14436 Rev 2 3/53
Typical application circuit PM6670AS
1 Typical application circuit
Figure 1. Application circuit
VDDQ
VDDQ
(
LDO input)
(
LDO input)
VTTREF
VTTREF
VTT
VTT
11
11
MODE
C
C
IN4
IN4CIN4
C
C
OUT3
OUT3COUT3
C
C
OUT2
OUT2COUT2
MODE
23
23
LDOIN
LDOIN
4
4
VTTREF
VTTREF
2
2
VTTSNS
VTTSNS
24
24
VTT
VTT
1
1
VTTGND
VTTGND
R
RLPR
LP
LP
C
C
IN3
IN3CIN3
312 618 8 22
312 618 8 22
AVCC
VCC
SEL
SEL
SGND_-
SGND_-
5151413 710
5151413 710
AVCC
DSCG
DSCG
PM6670AS
PM6670A
PM6670A
PGO/
PGO/
S3/////////’
S3/////////’
VCC
S5///’//
S5///’//
VOSC
VOSC
VREF///.
VREF///.
C
C
C
C
BOOT
BOOT
COMP
COMP
IN2
IN2
HGATE
HGATE
PHASE
PHASE
LGATE
LGATE
CSNS
CSNS
PGND
PGND
VSNS
VSNS
BYP
BYPCBYP
+5V
+5V
21
21
20
20
17
17
19
19
16
16
9
9
VIN
VIN
R
R
1
1
C
CINC
IN
R
R
2
2
C
C
BOOT
BOOT
R
R
LIM
LIMRLIM
IN
L
L
VDDQ
VDDQ
C
C
OUT
OUTCOUT
C
C
INT
INTCINT
4/53 Doc ID 14436 Rev 2
PM6670AS Pin settings
2 Pin settings
2.1 Connections
Figure 2. Pin connection (through top view)
VTT
VTT
VTT
VTT
LDOIN
LDOIN
LDOIN
VTTGND
VTTGND
VTTGND
VTTSNS
VTTSNS
VTTSNS
DDRSEL
DDRSEL
DDRSEL
VTTREF
VTTREF
VTTREF
LDOIN
24
24
24
24
1
1
1
1
PM6670A
PM6670A
PM6670A
PM6670A
PM6675S
PM6670AS
BOOT
BOOT
BOOT
BOOT
HGATE
HGATE
HGATE
PHASE
PHASE
PHASE
CSNS
CSNS
CSNS
CSNS
19
19
19
19
18
18
18
18
VCC
VCC
VCC
LGATE
LGATE
LGATE
PGND
PGND
PGND
PG
PG
PG
13
13
13
13
S3
S3
S3
S5
S5
SGND
SGND
SGND
AVCC S5
AVCC
AVCC
6
6
6
6
12
12
12
7
7
7
7
VREF
VREF
VREF
VREF
VOSC
VOSC
VOSC
VOSC
VSNS
VSNS
VSNS
VSNS
MODE
MODE
MODE
MODE
12
DSCG
DSCG
DSCG
DSCG
COMP
COMP
COMP
COMP
Doc ID 14436 Rev 2 5/53
Pin settings PM6670AS
2.2 Pin description
Table 2. Pin functions
N° Pin Function
1 VTTGND LDO power ground. Connect to negative terminal of VTT output capacitor.
2VTTSNS
3DDRSEL
4VTTREF
5SGND
6AVCC
7VREF
8VOSC
9 VSNS
10 MODE
LDO remote sensing. Connect as close as possible to the load via a low
noise PCB trace.
DDR voltage selector (if MODE is tied to VCC) or pulse-skip/no-audible
pulse-skip selector in adjustable mode (MODE voltage lower than 3 V). See
Mode of Operation Selection section for details.
Low noise buffered DDR Reference Voltage. A 22 nF (minimum) ceramic
bypass capacitor is required in order to achieve stability.
Ground reference for analog circuitry, control logic and VTTREF buffer.
Connect together with the thermal pad and VTTGND to a low impedance
ground plane. See the Application Note for details.
+5 V supply for internal logic. Connect to +5 V rail through a simple RC
filtering network.
High accuracy output voltage reference (1.237 V) for multilevel pins setting.
It can deliver up to 50 μA. Connect a 100 nF capacitor between VREF and
SGND in order to enhance noise rejection.
Frequency selection. Connect to the central tap of a resistor divider to set
the desired switching frequency. The pin cannot be left floating. See Device
Description section for details.
VDDQ output remote sensing. Discharge path for VDDQ in non-tracking
discharge. Input for internal resistor divider that provides VDDQ/2 to
VTTREF and VTT. Connect as close as possible to the load via a low noise
PCB trace.
Mode of operation selector. If MODE pin voltage is higher than 4 V, the fixed
output mode is selected. If MODE pin voltage is lower than 4 V, it is used as
negative input of the error amplifier. See Mode of Operation Selection
section for details.
11 COMP
12 DSCG
13 S5
14 S3
15 PG
16 PGND Power ground for the switching section.
17 LGATE Low-side gate driver output.
6/53 Doc ID 14436 Rev 2
DC voltage error compensation input for the switching section. Refer to
Mode of Operation Selection section for more details.
Discharge mode selection. Refer to output discharge selection section for
tracking/non-tracking discharge or no-discharge options.
Switching controller enable. Connect to S5 system status signal to meet S0S5 power management states compliance. See Power Management Pins
section for details. S5 pin can't be left floating.
Linear regulator enable. Connect to S3 system status signal to meet S0-S5
power management states compliance.
See Power Management Pins section for details. S3 pin can't be left floating.
Power-Good signal (open drain output). High when VDDQ output voltage is
within ±10% of nominal value.
PM6670AS Pin settings
Table 2. Pin functions (continued)
N° Pin Function
18 VCC +5 V low-side gate driver supply. Bypass with a 100 nF capacitor to PGND.
19 CSNS
20 PHASE Switch node connection and return path for the high-side gate driver.
21 HGATE High-side gate driver output
22 BOOT
23 LDOIN
24 VTT
Current Sense Input for the switching section. This pin must be connected
through a resistor to the drain of the synchronous rectifier (RDSon sensing)
Bootstrap capacitor connection. Positive supply input of the high-side gate
driver.
Linear regulator input. Connect to VDDQ in normal configuration or to a
lower supply to reduce the power dissipation. A 10 μF bypass ceramic
capacitor is suggested for noise rejection enhancement. See Device
Description section for more details.
LDO linear regulator output. Bypass with a 20 μF (2x10 μF MLCC) filter
capacitor.
Doc ID 14436 Rev 2 7/53
Electrical data PM6670AS
3 Electrical data
3.1 Maximum rating
Table 3. Absolute maximum ratings
(1)
Symbol Parameter Value Unit
V
V
AVC C
VCC
AVCC to SGND -0.3 to 6
VCC to SGND -0.3 to 6
PGND, VTTGND to SGND -0.3 to 0.3
HGATE and BOOT to PHASE -0.3 to 6
HGATE and BOOT to PGND -0.3 to 44
V
PHASE
P
TOT
1. Free air operating conditions unless otherwise specified. Stresses beyond those listed under “absolute
maximum ratings” may cause permanent damage to the device. Exposure to absolute maximum rated
conditions for extended periods may affect device reliability.
PHASE to SGND -0.3 to 38
LGATE to PGND -0.3 to V
CSNS, PG, S3, S5, DSCG, COMP, VSNS,
VOSC, VREF, MODE, DDRSEL to GND
-0.3 to V
VTTREF, VREF, VTT, VTTSNS to SGND -0.3 to V
LDOIN, VTT, VTTREF, LDOIN to VTTGND -0.3 to V
VCC
AVC C
AVC C
AVC C
+0.3
+ 0.3
+ 0.3
+ 0.3
Power dissipation @TA = 25 °C 2.3 W
V
3.2 Thermal data
Table 4. Thermal data
Symbol Parameter Value Unit
R
T
thJA
STG
T
A
T
J
Thermal resistance junction to ambient 42 °C/W
Storage temperature range - 50 to 150 °C
Operating ambient temperature range - 40 to 125 °C
Junction operating temperature range - 40 to 125 °C
3.3 Recommended operating conditions
Table 5. Recommended operating conditions
Symbol Parameter Min Typ Max Unit
V
AVC C
V
VCC
IN
Input voltage range 4.5 - 36
IC supply voltage 4.5 - 5.5
IC supply voltage 4.5 - 5.5
VV
8/53 Doc ID 14436 Rev 2
PM6670AS Electrical characteristics
4 Electrical characteristics
TA = -25 °C to 85 °C, VCC = AVCC = +5 V and LDOIN connected to VDDQ output if not
otherwise specified
(a)
Table 6. Electrical characteristics
Symbol Parameter Test condition Min Typ Max Unit
Supply section
S3, S5, MODE and DDRSEL
I
IN
I
STR
I
SH
UVLO
Operating current
Operating current in STR
Operating current in
shutdown
AVCC under voltage lockout
upper threshold
AVCC under voltage lockout
lower threshold
UVLO hysteresis 70 mV
connected to AVCC, No Load on
VTT and VTTREF outputs.
VCC connected to AVCC
S5, MODE and DDRSEL connected
to AVCC, S3 tied to SGND, No Load
on VTTREF.
VCC connected to AVCC
S3 and S5 tied to SGND.
Discharge mode active.
VCC connected to AVCC
0.8 2
0.6 1
110μA
4.1 4.25 4.4
3.85 4.0 4.1
mA
V
ON-time (SMPS)
ON
On-time duration
t
OFF-time (SMPS)
t
OFFMIN
Minimum off time 300 350 ns
Volt a g e re f e ren c e
Voltage accuracy 4.5 V < V
Load regulation -50 μA< I
Undervoltage lockout fault
threshold
VDDQ output
a. Specifications referred to TJ = TA. All the parameters at operating temperatures extremes are guaranteed by
MODE and
VOSC
DDRSEL high,
= 2 V
V
VSNS
IN
VREF
design and statistical correlation (not production tested)
VOSC = 500 mV 390 450 510
< 36 V 1.224 1.237 1.249 V
< 50 μA-44mV
= 300 mV 650 750 850
800
ns
Doc ID 14436 Rev 2 9/53
Electrical characteristics PM6670AS
Table 6. Electrical characteristics (continued)
Symbol Parameter Test condition Min Typ Max Unit
MODE connected to AVCC,
DDRSEL tied to SGND, no load
MODE and DDRSEL connected to
AVCC, no load
MODE and DDRSEL connected to
AVCC, no load
V
VDDQ
DDR3 VDDQ output voltage
DDR2 VDDQ output voltage
Feedback accuracy
Current limit and zero crossing comparator
I
CSNS
CSNS input bias current 110 120 130 μA
Comparator offset -6 6 mV
Positive current limit threshold
Rsense = 1 kΩ
V
PGND
Fixed negative current limit
threshold
V
ZC,OFFS
Zero crossing comparator
offset
High and low side gate drivers
HGATE high state (pull-up) 2.0 3
HGATE driver on-resistance
HGATE low state (pull-down) 1.8 2.7
LGATE high state (pull-up) 1.4 2.1
LGATE driver on-resistance
LGATE low state (pull-down) 0.6 0.9
- V
1.5
V
1.8
-1.5 1.5 %
120 mV
CSNS
110 mV
-11 -5 1 mV
Ω
UVP/OVP protections and PGOOD SIGNAL (SMPS only)
OVP Over voltage threshold 112 115 118
UVP Under voltage threshold 67 70 73
Power-good upper threshold 107 110 113
PGOOD
Power-good lower threshold 86 90 93
I
PG,LEAK
V
PG,LOW
PG leakeage current PG forced to 5 V 1 μA
PG low-level voltage I
= 4 mA 150 250 mV
PG,SINK
Soft-start section (SMPS)
Soft-start ramp time
(4 steps current limit)
1.5 3 4 ms
Soft-start current limit step 30 μA
Soft-end section
VDDQ discharge resistance
in non-tracking discharge
15 25 35
mode
VTT discharge resistance in
non-tracking discharge mode
15 25 35
%
Ω
10/53 Doc ID 14436 Rev 2
PM6670AS Electrical characteristics
Table 6. Electrical characteristics (continued)
Symbol Parameter Test condition Min Typ Max Unit
VTTREF discharge
LDO section
V
TT
I
LDOIN,ON
I
LDOIN,
STR
I
LDOIN,
STD
I
VTTSNS,
BIAS
I
VTTSNS,
LEAK
I
VTT,LEAK
resistance in non-tracking
discharge mode
VDDQ Output threshold
synchronous for final tracking
to non-tracking discharge
transition
LDO input bias current in fullon state
LDO input bias current in
suspend-to-RAM state
LDO input bias current in
suspend-to-disk state
VTTSNS bias current
VTTSNS leakage current
VTT leakage current
LDO linear regulator output
voltage (DDR2)
LDO linear regulator output
voltage (DDR3)
S3 = S5 = +5 V,
No Load on VTT
S3 = 0 V, S5 = +5 V,
No Load on VTT
S3 = S5 = 0 V, No Load on VTT 1
S3 = +5 V, S5 = +5 V,
V
VTTSNS
= V
VSNS
/2
S3 = 0V, S5 = +5 V,
V
VTTSNS
= V
VSNS
/2
S3 = 0V, S5 = +5 V,
= V
V
VTT
S3 = S5= +5 V, I
VSNS
/2
= 0 A, MODE =
VTT
DDRSEL = +5 V
S3 = S5= +5 V, I
VTT
= 0 A,
MODE = +5 V, DDRSEL = 0 V
11.52kΩ
0.2 0.4 0.6 V
110
10
μA
1
1
μA
-10 10
0.9
0.75
V
V
VTT
LDO output accuracy respect
to VTTREF
LDO source current limit
I
VTT,CL
LDO sink current limit
VTTREF section
VTTREF output voltage I
V
VTTREF
VTTREF output voltage
accuracy respect to VSNS/2
I
VTTREF
VTTREF current limit VTTREF = 0 or VSNS ±40 mA
S3 = S5 = MODE = + 5 V,
-1 mA < I
VTT
< 1 mA
S3 = S5 = MODE = +5 V,
-1 A < I
VTT
< 1 A
S3 = S5 = MODE = +5 V,
-2 A < I
V
VTT
V
VTT
V
VTT
V
VTT
VTTREF
-15 mA < I
< 2 A
VTT
< 1.10*(V
> 1.10*(V
> 0.90*(V
< 0.90*(V
= 0 A, V
VTTREF
/2) 2 2.3 3
VSNS
/2) 1 1.15 1.4
VSNS
/2) -3 -2.3 -2
VSNS
/2) -1.4 -1.15 -1
VSNS
= 1.8 V 0.9 V
VSNS
< 15 mA, V
1.8 V
VSNS
-20 20
-25 25
-35 35
=
-2 2 %
Doc ID 14436 Rev 2 11/53
mV
A
Electrical characteristics PM6670AS
Table 6. Electrical characteristics (continued)
Symbol Parameter Test condition Min Typ Max Unit
Power management section
S3,S5
V
MODE
V
DDRSEL
V
DSCG
I
IN,LEAK
I
IN3,LEAK
Turn OFF level 0.4
Turn ON level 1.6
MODE pin high level
threshold
MODE pin low level
threshold
DDRSEL pin high level
threshold
DDRSEL pin middle level
window
DDRSEL pin low level
threshold
DSCG pin high level
threshold
DSCG pin middle level
window
DSCG pin low level
threshold
V
AVC C
V
AVC C
V
AVC C
0.7
0.8
1.0
0.8
1.0
-
VAVCC -
1.3
-
VAVCC -
V
1.5
0.5
-
2.0
0.5
Logic inputs leakage current S3, S5 = 5 V 10 μA
Multilevel inputs leakage
current
MODE, DDRSEL and
DSCG = 5 V
10 μA
I
OSC,
LEAK
VOSC input leakage current VOSC = 500 mV 1 μA
Thermal shutdown
T
SHDN
1. Guaranteed by design. Not production tested
Shutdown temperature
(1)
150 °C
12/53 Doc ID 14436 Rev 2
PM6670AS Typical operating characteristics
z
5 Typical operating characteristics
Figure 3. Efficiency vs load - 1.5 V and 1.8 V,
100
90
80
70
60
50
40
Efficiency (%)
30
20
10
0
0.001 0.01 0.1 1 10
Vin = 12 V
Output current (A)
DDR2 - Forced PWM
DDR2 - No-Audible P-S
DDR2 - Pulse-Skip
DDR3 - Forced PWM
DDR3 - No-Audible P-S
DDR3 - Pulse-Skip
Figure 4. Switching frequency vs load - 1.8 V,
Vin = 12 V
500
450
400
350
300
250
200
150
100
Swiching frequency (kH
50
0
0.001 0.0 1 0.1 1 10
Forced PW M
No-Audible P-S
Pulse-Skip
Output current (A)
Figure 5. Switching frequency vs input
500
450
400
350
300
250
Switching frequency (kHz)
200
150
0.0 5.0 10.0 15.0 20. 0 25.0 30.0
Figure 7. VDDQ line regulation, 1.8 V, 7 A Figure 8. VDDQ line regulation, 1.5 V, 7 A
1.8000
1.7990
1.7980
1.7970
1.7960
Output voltage (V)
1.7950
1.7940
voltage, 1.8 V
Input voltage (V)
Forced PW M
No-Audibl e P-S
Pulse-Sk ip
0.0 5.0 10.0 15.0 20.0 25.0 30.0
Input voltage (V)
Figure 6. Switching frequency vs input
voltage, 1.5 V
500
450
400
350
300
250
Switc hing frequency (kHz)
200
150
0.0 5.0 10.0 15.0 20. 0 25.0 30.0
1.4980
1.4975
1.4970
1.4965
1.4960
1.4955
Output voltage (V)
1.4950
1.4945
1.4940
0.0 5.0 10.0 15.0 20.0 25.0 30.0
Input voltage (V)
Forced PWM
No-Audi ble P -S
Pulse-Skip
Inpu t volta ge (V)
Doc ID 14436 Rev 2 13/53
Typical operating characteristics PM6670AS
Figure 9. VDDQ load regulation,
1.860
1.850
1.840
1.830
1.820
Output voltage (V)
1.810
1.800
1.8 V, Vin = 12 V
Forced PWM
No-Audible P-S
Pulse-Skip
0.001 0.01 0.1 1 10
Output current (A)
Figure 11. VTT load regulation,
0.940
0.930
0.920
0.910
0.900
Output voltage (V)
0.890
0.880
0.9 V, LDOIN = 1.8 V
-2.5 -1.5 -0.5 0.5 1.5 2.5
Outpu t curr e nt (A)
Figure 10. VDDQ load regulation,
1.5 V, Vin = 12 V
1.530
1.520
1.510
Forced PWM
No-Audible P-S
Pulse-Skip
1.500
1.490
1.480
Output voltage (V)
1.470
0.001 0.01 0.1 1 10
Output current (A)
Figure 12. VTT load regulation,
0.75 V, LDOIN = 1.5 V
0.790
0.780
0.770
0.760
0.750
Output voltage (V )
0.740
0.730
-2.5 -1.5 -0.5 0.5 1.5 2.5
Outpu t curre nt (A)
Figure 13. VTTREF load regulation,
0.9 V, VSNS = 1.8 V
Figure 14. No-audible pulse-skip waveforms
14/53 Doc ID 14436 Rev 2
PM6670AS Typical operating characteristics
Figure 15. Power-up sequence - AVCC above
UVLO
Figure 17. - 1.8 A to 1.8 A VTT load transient,
0.9 V
Figure 16. VDDQ soft-start, 1.8 V, heavy load
Figure 18. 0 mA to 9 mA VTTREF load
transient, 0.9 V
Doc ID 14436 Rev 2 15/53
Typical operating characteristics PM6670AS
Figure 19. Non-tracking (soft) discharge Figure 20. Tracking (fast) discharge,
LDOIN = VDDQ
Figure 21. 0 A to 10 A VDDQ load transient,
PWM
Figure 22. 10 A to 0 A VDDQ load transient,
PWM
16/53 Doc ID 14436 Rev 2
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